[MIPS] Add LLVM 7.0 configs for Mips
Bug: b/117854176
Change-Id: I3732949af676a313e6ad284efcb91a90acd651ff
Reviewed-on: https://swiftshader-review.googlesource.com/c/21868
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
Tested-by: Gordana Cmiljanovic <gordana.cmiljanovic@mips.com>
diff --git a/third_party/llvm-7.0/configs/android/include/llvm/Config/AsmParsers.def b/third_party/llvm-7.0/configs/android/include/llvm/Config/AsmParsers.def
index d9f2476..49d8e31 100644
--- a/third_party/llvm-7.0/configs/android/include/llvm/Config/AsmParsers.def
+++ b/third_party/llvm-7.0/configs/android/include/llvm/Config/AsmParsers.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_ASM_PARSER(X86)
#endif
+#if defined(__mips__)
+LLVM_ASM_PARSER(Mips)
+#endif
#undef LLVM_ASM_PARSER
diff --git a/third_party/llvm-7.0/configs/android/include/llvm/Config/AsmPrinters.def b/third_party/llvm-7.0/configs/android/include/llvm/Config/AsmPrinters.def
index e742776..84a2c42 100644
--- a/third_party/llvm-7.0/configs/android/include/llvm/Config/AsmPrinters.def
+++ b/third_party/llvm-7.0/configs/android/include/llvm/Config/AsmPrinters.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_ASM_PRINTER(X86)
#endif
+#if defined(__mips__)
+LLVM_ASM_PRINTER(Mips)
+#endif
#undef LLVM_ASM_PRINTER
diff --git a/third_party/llvm-7.0/configs/android/include/llvm/Config/Disassemblers.def b/third_party/llvm-7.0/configs/android/include/llvm/Config/Disassemblers.def
index e863f92..e3bb9ce 100644
--- a/third_party/llvm-7.0/configs/android/include/llvm/Config/Disassemblers.def
+++ b/third_party/llvm-7.0/configs/android/include/llvm/Config/Disassemblers.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_DISASSEMBLER(X86)
#endif
+#if defined(__mips__)
+LLVM_DISASSEMBLER(Mips)
+#endif
#undef LLVM_DISASSEMBLER
diff --git a/third_party/llvm-7.0/configs/android/include/llvm/Config/Targets.def b/third_party/llvm-7.0/configs/android/include/llvm/Config/Targets.def
index 6968ed1..aaf9378 100644
--- a/third_party/llvm-7.0/configs/android/include/llvm/Config/Targets.def
+++ b/third_party/llvm-7.0/configs/android/include/llvm/Config/Targets.def
@@ -32,6 +32,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_TARGET(X86)
#endif
+#if defined(__mips__)
+LLVM_TARGET(Mips)
+#endif
#undef LLVM_TARGET
diff --git a/third_party/llvm-7.0/configs/android/include/llvm/Config/llvm-config.h b/third_party/llvm-7.0/configs/android/include/llvm/Config/llvm-config.h
index ef6e6f2..9219b63 100644
--- a/third_party/llvm-7.0/configs/android/include/llvm/Config/llvm-config.h
+++ b/third_party/llvm-7.0/configs/android/include/llvm/Config/llvm-config.h
@@ -59,6 +59,8 @@
#define LLVM_NATIVE_ARCH ARM
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ARCH X86
+#elif defined(__mips__)
+#define LLVM_NATIVE_ARCH Mips
#else
#error "unknown architecture"
#endif
@@ -70,6 +72,8 @@
#define LLVM_NATIVE_ASMPARSER LLVMInitializeARMAsmParser
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
+#elif defined(__mips__)
+#define LLVM_NATIVE_ASMPARSER LLVMInitializeMipsAsmParser
#else
#error "unknown architecture"
#endif
@@ -81,6 +85,8 @@
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeARMAsmPrinter
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
+#elif defined(__mips__)
+#define LLVM_NATIVE_ASMPRINTER LLVMInitializeMipsAsmPrinter
#else
#error "unknown architecture"
#endif
@@ -92,6 +98,8 @@
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeARMDisassembler
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeX86Disassembler
+#elif defined(__mips__)
+#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeMipsDisassembler
#else
#error "unknown architecture"
#endif
@@ -103,6 +111,8 @@
#define LLVM_NATIVE_TARGET LLVMInitializeARMTarget
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGET LLVMInitializeX86Target
+#elif defined(__mips__)
+#define LLVM_NATIVE_TARGET LLVMInitializeMipsTarget
#else
#error "unknown architecture"
#endif
@@ -114,6 +124,8 @@
#define LLVM_NATIVE_TARGETINFO LLVMInitializeARMTargetInfo
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo
+#elif defined(__mips__)
+#define LLVM_NATIVE_TARGETINFO LLVMInitializeMipsTargetInfo
#else
#error "unknown architecture"
#endif
@@ -125,6 +137,8 @@
#define LLVM_NATIVE_TARGETMC LLVMInitializeARMTargetMC
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC
+#elif defined(__mips__)
+#define LLVM_NATIVE_TARGETMC LLVMInitializeMipsTargetMC
#else
#error "unknown architecture"
#endif
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/AArch64/AArch64GenSystemOperands.inc b/third_party/llvm-7.0/configs/common/lib/Target/AArch64/AArch64GenSystemOperands.inc
index a9596a1..7c0716d 100644
--- a/third_party/llvm-7.0/configs/common/lib/Target/AArch64/AArch64GenSystemOperands.inc
+++ b/third_party/llvm-7.0/configs/common/lib/Target/AArch64/AArch64GenSystemOperands.inc
@@ -248,6 +248,7 @@
ICH_VTR_EL2 = 58969,
ICH_EISR_EL2 = 58971,
ICH_ELRSR_EL2 = 58973,
+ ID_AA64ZFR0_EL1 = 49188,
LORID_EL1 = 50471,
ERRIDR_EL1 = 49816,
ERXFR_EL1 = 49824,
@@ -883,6 +884,10 @@
TRFCR_EL12 = 59537,
DIT = 55829,
VNCR_EL2 = 57616,
+ ZCR_EL1 = 49296,
+ ZCR_EL2 = 57488,
+ ZCR_EL3 = 61584,
+ ZCR_EL12 = 59536,
CPM_IOACC_CTL_EL3 = 65424,
};
#endif
@@ -2070,642 +2075,647 @@
{ "ICH_VTR_EL2", 0xE659, true, false, {} }, // 93
{ "ICH_EISR_EL2", 0xE65B, true, false, {} }, // 94
{ "ICH_ELRSR_EL2", 0xE65D, true, false, {} }, // 95
- { "LORID_EL1", 0xC527, true, false, {AArch64::HasV8_1aOps} }, // 96
- { "ERRIDR_EL1", 0xC298, true, false, {AArch64::FeatureRAS} }, // 97
- { "ERXFR_EL1", 0xC2A0, true, false, {AArch64::FeatureRAS} }, // 98
- { "DBGDTRTX_EL0", 0x9828, false, true, {} }, // 99
- { "OSLAR_EL1", 0x8084, false, true, {} }, // 100
- { "PMSWINC_EL0", 0xDCE4, false, true, {} }, // 101
- { "TRCOSLAR", 0x8884, false, true, {} }, // 102
- { "TRCLAR", 0x8BE6, false, true, {} }, // 103
- { "ICC_EOIR1_EL1", 0xC661, false, true, {} }, // 104
- { "ICC_EOIR0_EL1", 0xC641, false, true, {} }, // 105
- { "ICC_DIR_EL1", 0xC659, false, true, {} }, // 106
- { "ICC_SGI1R_EL1", 0xC65D, false, true, {} }, // 107
- { "ICC_ASGI1R_EL1", 0xC65E, false, true, {} }, // 108
- { "ICC_SGI0R_EL1", 0xC65F, false, true, {} }, // 109
- { "OSDTRRX_EL1", 0x8002, true, true, {} }, // 110
- { "OSDTRTX_EL1", 0x801A, true, true, {} }, // 111
- { "TEECR32_EL1", 0x9000, true, true, {} }, // 112
- { "MDCCINT_EL1", 0x8010, true, true, {} }, // 113
- { "MDSCR_EL1", 0x8012, true, true, {} }, // 114
- { "DBGDTR_EL0", 0x9820, true, true, {} }, // 115
- { "OSECCR_EL1", 0x8032, true, true, {} }, // 116
- { "DBGVCR32_EL2", 0xA038, true, true, {} }, // 117
- { "DBGBVR0_EL1", 0x8004, true, true, {} }, // 118
- { "DBGBVR1_EL1", 0x800C, true, true, {} }, // 119
- { "DBGBVR2_EL1", 0x8014, true, true, {} }, // 120
- { "DBGBVR3_EL1", 0x801C, true, true, {} }, // 121
- { "DBGBVR4_EL1", 0x8024, true, true, {} }, // 122
- { "DBGBVR5_EL1", 0x802C, true, true, {} }, // 123
- { "DBGBVR6_EL1", 0x8034, true, true, {} }, // 124
- { "DBGBVR7_EL1", 0x803C, true, true, {} }, // 125
- { "DBGBVR8_EL1", 0x8044, true, true, {} }, // 126
- { "DBGBVR9_EL1", 0x804C, true, true, {} }, // 127
- { "DBGBVR10_EL1", 0x8054, true, true, {} }, // 128
- { "DBGBVR11_EL1", 0x805C, true, true, {} }, // 129
- { "DBGBVR12_EL1", 0x8064, true, true, {} }, // 130
- { "DBGBVR13_EL1", 0x806C, true, true, {} }, // 131
- { "DBGBVR14_EL1", 0x8074, true, true, {} }, // 132
- { "DBGBVR15_EL1", 0x807C, true, true, {} }, // 133
- { "DBGBCR0_EL1", 0x8005, true, true, {} }, // 134
- { "DBGBCR1_EL1", 0x800D, true, true, {} }, // 135
- { "DBGBCR2_EL1", 0x8015, true, true, {} }, // 136
- { "DBGBCR3_EL1", 0x801D, true, true, {} }, // 137
- { "DBGBCR4_EL1", 0x8025, true, true, {} }, // 138
- { "DBGBCR5_EL1", 0x802D, true, true, {} }, // 139
- { "DBGBCR6_EL1", 0x8035, true, true, {} }, // 140
- { "DBGBCR7_EL1", 0x803D, true, true, {} }, // 141
- { "DBGBCR8_EL1", 0x8045, true, true, {} }, // 142
- { "DBGBCR9_EL1", 0x804D, true, true, {} }, // 143
- { "DBGBCR10_EL1", 0x8055, true, true, {} }, // 144
- { "DBGBCR11_EL1", 0x805D, true, true, {} }, // 145
- { "DBGBCR12_EL1", 0x8065, true, true, {} }, // 146
- { "DBGBCR13_EL1", 0x806D, true, true, {} }, // 147
- { "DBGBCR14_EL1", 0x8075, true, true, {} }, // 148
- { "DBGBCR15_EL1", 0x807D, true, true, {} }, // 149
- { "DBGWVR0_EL1", 0x8006, true, true, {} }, // 150
- { "DBGWVR1_EL1", 0x800E, true, true, {} }, // 151
- { "DBGWVR2_EL1", 0x8016, true, true, {} }, // 152
- { "DBGWVR3_EL1", 0x801E, true, true, {} }, // 153
- { "DBGWVR4_EL1", 0x8026, true, true, {} }, // 154
- { "DBGWVR5_EL1", 0x802E, true, true, {} }, // 155
- { "DBGWVR6_EL1", 0x8036, true, true, {} }, // 156
- { "DBGWVR7_EL1", 0x803E, true, true, {} }, // 157
- { "DBGWVR8_EL1", 0x8046, true, true, {} }, // 158
- { "DBGWVR9_EL1", 0x804E, true, true, {} }, // 159
- { "DBGWVR10_EL1", 0x8056, true, true, {} }, // 160
- { "DBGWVR11_EL1", 0x805E, true, true, {} }, // 161
- { "DBGWVR12_EL1", 0x8066, true, true, {} }, // 162
- { "DBGWVR13_EL1", 0x806E, true, true, {} }, // 163
- { "DBGWVR14_EL1", 0x8076, true, true, {} }, // 164
- { "DBGWVR15_EL1", 0x807E, true, true, {} }, // 165
- { "DBGWCR0_EL1", 0x8007, true, true, {} }, // 166
- { "DBGWCR1_EL1", 0x800F, true, true, {} }, // 167
- { "DBGWCR2_EL1", 0x8017, true, true, {} }, // 168
- { "DBGWCR3_EL1", 0x801F, true, true, {} }, // 169
- { "DBGWCR4_EL1", 0x8027, true, true, {} }, // 170
- { "DBGWCR5_EL1", 0x802F, true, true, {} }, // 171
- { "DBGWCR6_EL1", 0x8037, true, true, {} }, // 172
- { "DBGWCR7_EL1", 0x803F, true, true, {} }, // 173
- { "DBGWCR8_EL1", 0x8047, true, true, {} }, // 174
- { "DBGWCR9_EL1", 0x804F, true, true, {} }, // 175
- { "DBGWCR10_EL1", 0x8057, true, true, {} }, // 176
- { "DBGWCR11_EL1", 0x805F, true, true, {} }, // 177
- { "DBGWCR12_EL1", 0x8067, true, true, {} }, // 178
- { "DBGWCR13_EL1", 0x806F, true, true, {} }, // 179
- { "DBGWCR14_EL1", 0x8077, true, true, {} }, // 180
- { "DBGWCR15_EL1", 0x807F, true, true, {} }, // 181
- { "TEEHBR32_EL1", 0x9080, true, true, {} }, // 182
- { "OSDLR_EL1", 0x809C, true, true, {} }, // 183
- { "DBGPRCR_EL1", 0x80A4, true, true, {} }, // 184
- { "DBGCLAIMSET_EL1", 0x83C6, true, true, {} }, // 185
- { "DBGCLAIMCLR_EL1", 0x83CE, true, true, {} }, // 186
- { "CSSELR_EL1", 0xD000, true, true, {} }, // 187
- { "VPIDR_EL2", 0xE000, true, true, {} }, // 188
- { "VMPIDR_EL2", 0xE005, true, true, {} }, // 189
- { "CPACR_EL1", 0xC082, true, true, {} }, // 190
- { "SCTLR_EL1", 0xC080, true, true, {} }, // 191
- { "SCTLR_EL2", 0xE080, true, true, {} }, // 192
- { "SCTLR_EL3", 0xF080, true, true, {} }, // 193
- { "ACTLR_EL1", 0xC081, true, true, {} }, // 194
- { "ACTLR_EL2", 0xE081, true, true, {} }, // 195
- { "ACTLR_EL3", 0xF081, true, true, {} }, // 196
- { "HCR_EL2", 0xE088, true, true, {} }, // 197
- { "SCR_EL3", 0xF088, true, true, {} }, // 198
- { "MDCR_EL2", 0xE089, true, true, {} }, // 199
- { "SDER32_EL3", 0xF089, true, true, {} }, // 200
- { "CPTR_EL2", 0xE08A, true, true, {} }, // 201
- { "CPTR_EL3", 0xF08A, true, true, {} }, // 202
- { "HSTR_EL2", 0xE08B, true, true, {} }, // 203
- { "HACR_EL2", 0xE08F, true, true, {} }, // 204
- { "MDCR_EL3", 0xF099, true, true, {} }, // 205
- { "TTBR0_EL1", 0xC100, true, true, {} }, // 206
- { "TTBR0_EL2", 0xE100, true, true, {} }, // 207
- { "TTBR0_EL3", 0xF100, true, true, {} }, // 208
- { "TTBR1_EL1", 0xC101, true, true, {} }, // 209
- { "TCR_EL1", 0xC102, true, true, {} }, // 210
- { "TCR_EL2", 0xE102, true, true, {} }, // 211
- { "TCR_EL3", 0xF102, true, true, {} }, // 212
- { "VTTBR_EL2", 0xE108, true, true, {} }, // 213
- { "VTCR_EL2", 0xE10A, true, true, {} }, // 214
- { "DACR32_EL2", 0xE180, true, true, {} }, // 215
- { "SPSR_EL1", 0xC200, true, true, {} }, // 216
- { "SPSR_EL2", 0xE200, true, true, {} }, // 217
- { "SPSR_EL3", 0xF200, true, true, {} }, // 218
- { "ELR_EL1", 0xC201, true, true, {} }, // 219
- { "ELR_EL2", 0xE201, true, true, {} }, // 220
- { "ELR_EL3", 0xF201, true, true, {} }, // 221
- { "SP_EL0", 0xC208, true, true, {} }, // 222
- { "SP_EL1", 0xE208, true, true, {} }, // 223
- { "SP_EL2", 0xF208, true, true, {} }, // 224
- { "SPSel", 0xC210, true, true, {} }, // 225
- { "NZCV", 0xDA10, true, true, {} }, // 226
- { "DAIF", 0xDA11, true, true, {} }, // 227
- { "CurrentEL", 0xC212, true, true, {} }, // 228
- { "SPSR_irq", 0xE218, true, true, {} }, // 229
- { "SPSR_abt", 0xE219, true, true, {} }, // 230
- { "SPSR_und", 0xE21A, true, true, {} }, // 231
- { "SPSR_fiq", 0xE21B, true, true, {} }, // 232
- { "FPCR", 0xDA20, true, true, {} }, // 233
- { "FPSR", 0xDA21, true, true, {} }, // 234
- { "DSPSR_EL0", 0xDA28, true, true, {} }, // 235
- { "DLR_EL0", 0xDA29, true, true, {} }, // 236
- { "IFSR32_EL2", 0xE281, true, true, {} }, // 237
- { "AFSR0_EL1", 0xC288, true, true, {} }, // 238
- { "AFSR0_EL2", 0xE288, true, true, {} }, // 239
- { "AFSR0_EL3", 0xF288, true, true, {} }, // 240
- { "AFSR1_EL1", 0xC289, true, true, {} }, // 241
- { "AFSR1_EL2", 0xE289, true, true, {} }, // 242
- { "AFSR1_EL3", 0xF289, true, true, {} }, // 243
- { "ESR_EL1", 0xC290, true, true, {} }, // 244
- { "ESR_EL2", 0xE290, true, true, {} }, // 245
- { "ESR_EL3", 0xF290, true, true, {} }, // 246
- { "FPEXC32_EL2", 0xE298, true, true, {} }, // 247
- { "FAR_EL1", 0xC300, true, true, {} }, // 248
- { "FAR_EL2", 0xE300, true, true, {} }, // 249
- { "FAR_EL3", 0xF300, true, true, {} }, // 250
- { "HPFAR_EL2", 0xE304, true, true, {} }, // 251
- { "PAR_EL1", 0xC3A0, true, true, {} }, // 252
- { "PMCR_EL0", 0xDCE0, true, true, {} }, // 253
- { "PMCNTENSET_EL0", 0xDCE1, true, true, {} }, // 254
- { "PMCNTENCLR_EL0", 0xDCE2, true, true, {} }, // 255
- { "PMOVSCLR_EL0", 0xDCE3, true, true, {} }, // 256
- { "PMSELR_EL0", 0xDCE5, true, true, {} }, // 257
- { "PMCCNTR_EL0", 0xDCE8, true, true, {} }, // 258
- { "PMXEVTYPER_EL0", 0xDCE9, true, true, {} }, // 259
- { "PMXEVCNTR_EL0", 0xDCEA, true, true, {} }, // 260
- { "PMUSERENR_EL0", 0xDCF0, true, true, {} }, // 261
- { "PMINTENSET_EL1", 0xC4F1, true, true, {} }, // 262
- { "PMINTENCLR_EL1", 0xC4F2, true, true, {} }, // 263
- { "PMOVSSET_EL0", 0xDCF3, true, true, {} }, // 264
- { "MAIR_EL1", 0xC510, true, true, {} }, // 265
- { "MAIR_EL2", 0xE510, true, true, {} }, // 266
- { "MAIR_EL3", 0xF510, true, true, {} }, // 267
- { "AMAIR_EL1", 0xC518, true, true, {} }, // 268
- { "AMAIR_EL2", 0xE518, true, true, {} }, // 269
- { "AMAIR_EL3", 0xF518, true, true, {} }, // 270
- { "VBAR_EL1", 0xC600, true, true, {} }, // 271
- { "VBAR_EL2", 0xE600, true, true, {} }, // 272
- { "VBAR_EL3", 0xF600, true, true, {} }, // 273
- { "RMR_EL1", 0xC602, true, true, {} }, // 274
- { "RMR_EL2", 0xE602, true, true, {} }, // 275
- { "RMR_EL3", 0xF602, true, true, {} }, // 276
- { "CONTEXTIDR_EL1", 0xC681, true, true, {} }, // 277
- { "TPIDR_EL0", 0xDE82, true, true, {} }, // 278
- { "TPIDR_EL2", 0xE682, true, true, {} }, // 279
- { "TPIDR_EL3", 0xF682, true, true, {} }, // 280
- { "TPIDRRO_EL0", 0xDE83, true, true, {} }, // 281
- { "TPIDR_EL1", 0xC684, true, true, {} }, // 282
- { "CNTFRQ_EL0", 0xDF00, true, true, {} }, // 283
- { "CNTVOFF_EL2", 0xE703, true, true, {} }, // 284
- { "CNTKCTL_EL1", 0xC708, true, true, {} }, // 285
- { "CNTHCTL_EL2", 0xE708, true, true, {} }, // 286
- { "CNTP_TVAL_EL0", 0xDF10, true, true, {} }, // 287
- { "CNTHP_TVAL_EL2", 0xE710, true, true, {} }, // 288
- { "CNTPS_TVAL_EL1", 0xFF10, true, true, {} }, // 289
- { "CNTP_CTL_EL0", 0xDF11, true, true, {} }, // 290
- { "CNTHP_CTL_EL2", 0xE711, true, true, {} }, // 291
- { "CNTPS_CTL_EL1", 0xFF11, true, true, {} }, // 292
- { "CNTP_CVAL_EL0", 0xDF12, true, true, {} }, // 293
- { "CNTHP_CVAL_EL2", 0xE712, true, true, {} }, // 294
- { "CNTPS_CVAL_EL1", 0xFF12, true, true, {} }, // 295
- { "CNTV_TVAL_EL0", 0xDF18, true, true, {} }, // 296
- { "CNTV_CTL_EL0", 0xDF19, true, true, {} }, // 297
- { "CNTV_CVAL_EL0", 0xDF1A, true, true, {} }, // 298
- { "PMEVCNTR0_EL0", 0xDF40, true, true, {} }, // 299
- { "PMEVCNTR1_EL0", 0xDF41, true, true, {} }, // 300
- { "PMEVCNTR2_EL0", 0xDF42, true, true, {} }, // 301
- { "PMEVCNTR3_EL0", 0xDF43, true, true, {} }, // 302
- { "PMEVCNTR4_EL0", 0xDF44, true, true, {} }, // 303
- { "PMEVCNTR5_EL0", 0xDF45, true, true, {} }, // 304
- { "PMEVCNTR6_EL0", 0xDF46, true, true, {} }, // 305
- { "PMEVCNTR7_EL0", 0xDF47, true, true, {} }, // 306
- { "PMEVCNTR8_EL0", 0xDF48, true, true, {} }, // 307
- { "PMEVCNTR9_EL0", 0xDF49, true, true, {} }, // 308
- { "PMEVCNTR10_EL0", 0xDF4A, true, true, {} }, // 309
- { "PMEVCNTR11_EL0", 0xDF4B, true, true, {} }, // 310
- { "PMEVCNTR12_EL0", 0xDF4C, true, true, {} }, // 311
- { "PMEVCNTR13_EL0", 0xDF4D, true, true, {} }, // 312
- { "PMEVCNTR14_EL0", 0xDF4E, true, true, {} }, // 313
- { "PMEVCNTR15_EL0", 0xDF4F, true, true, {} }, // 314
- { "PMEVCNTR16_EL0", 0xDF50, true, true, {} }, // 315
- { "PMEVCNTR17_EL0", 0xDF51, true, true, {} }, // 316
- { "PMEVCNTR18_EL0", 0xDF52, true, true, {} }, // 317
- { "PMEVCNTR19_EL0", 0xDF53, true, true, {} }, // 318
- { "PMEVCNTR20_EL0", 0xDF54, true, true, {} }, // 319
- { "PMEVCNTR21_EL0", 0xDF55, true, true, {} }, // 320
- { "PMEVCNTR22_EL0", 0xDF56, true, true, {} }, // 321
- { "PMEVCNTR23_EL0", 0xDF57, true, true, {} }, // 322
- { "PMEVCNTR24_EL0", 0xDF58, true, true, {} }, // 323
- { "PMEVCNTR25_EL0", 0xDF59, true, true, {} }, // 324
- { "PMEVCNTR26_EL0", 0xDF5A, true, true, {} }, // 325
- { "PMEVCNTR27_EL0", 0xDF5B, true, true, {} }, // 326
- { "PMEVCNTR28_EL0", 0xDF5C, true, true, {} }, // 327
- { "PMEVCNTR29_EL0", 0xDF5D, true, true, {} }, // 328
- { "PMEVCNTR30_EL0", 0xDF5E, true, true, {} }, // 329
- { "PMCCFILTR_EL0", 0xDF7F, true, true, {} }, // 330
- { "PMEVTYPER0_EL0", 0xDF60, true, true, {} }, // 331
- { "PMEVTYPER1_EL0", 0xDF61, true, true, {} }, // 332
- { "PMEVTYPER2_EL0", 0xDF62, true, true, {} }, // 333
- { "PMEVTYPER3_EL0", 0xDF63, true, true, {} }, // 334
- { "PMEVTYPER4_EL0", 0xDF64, true, true, {} }, // 335
- { "PMEVTYPER5_EL0", 0xDF65, true, true, {} }, // 336
- { "PMEVTYPER6_EL0", 0xDF66, true, true, {} }, // 337
- { "PMEVTYPER7_EL0", 0xDF67, true, true, {} }, // 338
- { "PMEVTYPER8_EL0", 0xDF68, true, true, {} }, // 339
- { "PMEVTYPER9_EL0", 0xDF69, true, true, {} }, // 340
- { "PMEVTYPER10_EL0", 0xDF6A, true, true, {} }, // 341
- { "PMEVTYPER11_EL0", 0xDF6B, true, true, {} }, // 342
- { "PMEVTYPER12_EL0", 0xDF6C, true, true, {} }, // 343
- { "PMEVTYPER13_EL0", 0xDF6D, true, true, {} }, // 344
- { "PMEVTYPER14_EL0", 0xDF6E, true, true, {} }, // 345
- { "PMEVTYPER15_EL0", 0xDF6F, true, true, {} }, // 346
- { "PMEVTYPER16_EL0", 0xDF70, true, true, {} }, // 347
- { "PMEVTYPER17_EL0", 0xDF71, true, true, {} }, // 348
- { "PMEVTYPER18_EL0", 0xDF72, true, true, {} }, // 349
- { "PMEVTYPER19_EL0", 0xDF73, true, true, {} }, // 350
- { "PMEVTYPER20_EL0", 0xDF74, true, true, {} }, // 351
- { "PMEVTYPER21_EL0", 0xDF75, true, true, {} }, // 352
- { "PMEVTYPER22_EL0", 0xDF76, true, true, {} }, // 353
- { "PMEVTYPER23_EL0", 0xDF77, true, true, {} }, // 354
- { "PMEVTYPER24_EL0", 0xDF78, true, true, {} }, // 355
- { "PMEVTYPER25_EL0", 0xDF79, true, true, {} }, // 356
- { "PMEVTYPER26_EL0", 0xDF7A, true, true, {} }, // 357
- { "PMEVTYPER27_EL0", 0xDF7B, true, true, {} }, // 358
- { "PMEVTYPER28_EL0", 0xDF7C, true, true, {} }, // 359
- { "PMEVTYPER29_EL0", 0xDF7D, true, true, {} }, // 360
- { "PMEVTYPER30_EL0", 0xDF7E, true, true, {} }, // 361
- { "TRCPRGCTLR", 0x8808, true, true, {} }, // 362
- { "TRCPROCSELR", 0x8810, true, true, {} }, // 363
- { "TRCCONFIGR", 0x8820, true, true, {} }, // 364
- { "TRCAUXCTLR", 0x8830, true, true, {} }, // 365
- { "TRCEVENTCTL0R", 0x8840, true, true, {} }, // 366
- { "TRCEVENTCTL1R", 0x8848, true, true, {} }, // 367
- { "TRCSTALLCTLR", 0x8858, true, true, {} }, // 368
- { "TRCTSCTLR", 0x8860, true, true, {} }, // 369
- { "TRCSYNCPR", 0x8868, true, true, {} }, // 370
- { "TRCCCCTLR", 0x8870, true, true, {} }, // 371
- { "TRCBBCTLR", 0x8878, true, true, {} }, // 372
- { "TRCTRACEIDR", 0x8801, true, true, {} }, // 373
- { "TRCQCTLR", 0x8809, true, true, {} }, // 374
- { "TRCVICTLR", 0x8802, true, true, {} }, // 375
- { "TRCVIIECTLR", 0x880A, true, true, {} }, // 376
- { "TRCVISSCTLR", 0x8812, true, true, {} }, // 377
- { "TRCVIPCSSCTLR", 0x881A, true, true, {} }, // 378
- { "TRCVDCTLR", 0x8842, true, true, {} }, // 379
- { "TRCVDSACCTLR", 0x884A, true, true, {} }, // 380
- { "TRCVDARCCTLR", 0x8852, true, true, {} }, // 381
- { "TRCSEQEVR0", 0x8804, true, true, {} }, // 382
- { "TRCSEQEVR1", 0x880C, true, true, {} }, // 383
- { "TRCSEQEVR2", 0x8814, true, true, {} }, // 384
- { "TRCSEQRSTEVR", 0x8834, true, true, {} }, // 385
- { "TRCSEQSTR", 0x883C, true, true, {} }, // 386
- { "TRCEXTINSELR", 0x8844, true, true, {} }, // 387
- { "TRCCNTRLDVR0", 0x8805, true, true, {} }, // 388
- { "TRCCNTRLDVR1", 0x880D, true, true, {} }, // 389
- { "TRCCNTRLDVR2", 0x8815, true, true, {} }, // 390
- { "TRCCNTRLDVR3", 0x881D, true, true, {} }, // 391
- { "TRCCNTCTLR0", 0x8825, true, true, {} }, // 392
- { "TRCCNTCTLR1", 0x882D, true, true, {} }, // 393
- { "TRCCNTCTLR2", 0x8835, true, true, {} }, // 394
- { "TRCCNTCTLR3", 0x883D, true, true, {} }, // 395
- { "TRCCNTVR0", 0x8845, true, true, {} }, // 396
- { "TRCCNTVR1", 0x884D, true, true, {} }, // 397
- { "TRCCNTVR2", 0x8855, true, true, {} }, // 398
- { "TRCCNTVR3", 0x885D, true, true, {} }, // 399
- { "TRCIMSPEC0", 0x8807, true, true, {} }, // 400
- { "TRCIMSPEC1", 0x880F, true, true, {} }, // 401
- { "TRCIMSPEC2", 0x8817, true, true, {} }, // 402
- { "TRCIMSPEC3", 0x881F, true, true, {} }, // 403
- { "TRCIMSPEC4", 0x8827, true, true, {} }, // 404
- { "TRCIMSPEC5", 0x882F, true, true, {} }, // 405
- { "TRCIMSPEC6", 0x8837, true, true, {} }, // 406
- { "TRCIMSPEC7", 0x883F, true, true, {} }, // 407
- { "TRCRSCTLR2", 0x8890, true, true, {} }, // 408
- { "TRCRSCTLR3", 0x8898, true, true, {} }, // 409
- { "TRCRSCTLR4", 0x88A0, true, true, {} }, // 410
- { "TRCRSCTLR5", 0x88A8, true, true, {} }, // 411
- { "TRCRSCTLR6", 0x88B0, true, true, {} }, // 412
- { "TRCRSCTLR7", 0x88B8, true, true, {} }, // 413
- { "TRCRSCTLR8", 0x88C0, true, true, {} }, // 414
- { "TRCRSCTLR9", 0x88C8, true, true, {} }, // 415
- { "TRCRSCTLR10", 0x88D0, true, true, {} }, // 416
- { "TRCRSCTLR11", 0x88D8, true, true, {} }, // 417
- { "TRCRSCTLR12", 0x88E0, true, true, {} }, // 418
- { "TRCRSCTLR13", 0x88E8, true, true, {} }, // 419
- { "TRCRSCTLR14", 0x88F0, true, true, {} }, // 420
- { "TRCRSCTLR15", 0x88F8, true, true, {} }, // 421
- { "TRCRSCTLR16", 0x8881, true, true, {} }, // 422
- { "TRCRSCTLR17", 0x8889, true, true, {} }, // 423
- { "TRCRSCTLR18", 0x8891, true, true, {} }, // 424
- { "TRCRSCTLR19", 0x8899, true, true, {} }, // 425
- { "TRCRSCTLR20", 0x88A1, true, true, {} }, // 426
- { "TRCRSCTLR21", 0x88A9, true, true, {} }, // 427
- { "TRCRSCTLR22", 0x88B1, true, true, {} }, // 428
- { "TRCRSCTLR23", 0x88B9, true, true, {} }, // 429
- { "TRCRSCTLR24", 0x88C1, true, true, {} }, // 430
- { "TRCRSCTLR25", 0x88C9, true, true, {} }, // 431
- { "TRCRSCTLR26", 0x88D1, true, true, {} }, // 432
- { "TRCRSCTLR27", 0x88D9, true, true, {} }, // 433
- { "TRCRSCTLR28", 0x88E1, true, true, {} }, // 434
- { "TRCRSCTLR29", 0x88E9, true, true, {} }, // 435
- { "TRCRSCTLR30", 0x88F1, true, true, {} }, // 436
- { "TRCRSCTLR31", 0x88F9, true, true, {} }, // 437
- { "TRCSSCCR0", 0x8882, true, true, {} }, // 438
- { "TRCSSCCR1", 0x888A, true, true, {} }, // 439
- { "TRCSSCCR2", 0x8892, true, true, {} }, // 440
- { "TRCSSCCR3", 0x889A, true, true, {} }, // 441
- { "TRCSSCCR4", 0x88A2, true, true, {} }, // 442
- { "TRCSSCCR5", 0x88AA, true, true, {} }, // 443
- { "TRCSSCCR6", 0x88B2, true, true, {} }, // 444
- { "TRCSSCCR7", 0x88BA, true, true, {} }, // 445
- { "TRCSSCSR0", 0x88C2, true, true, {} }, // 446
- { "TRCSSCSR1", 0x88CA, true, true, {} }, // 447
- { "TRCSSCSR2", 0x88D2, true, true, {} }, // 448
- { "TRCSSCSR3", 0x88DA, true, true, {} }, // 449
- { "TRCSSCSR4", 0x88E2, true, true, {} }, // 450
- { "TRCSSCSR5", 0x88EA, true, true, {} }, // 451
- { "TRCSSCSR6", 0x88F2, true, true, {} }, // 452
- { "TRCSSCSR7", 0x88FA, true, true, {} }, // 453
- { "TRCSSPCICR0", 0x8883, true, true, {} }, // 454
- { "TRCSSPCICR1", 0x888B, true, true, {} }, // 455
- { "TRCSSPCICR2", 0x8893, true, true, {} }, // 456
- { "TRCSSPCICR3", 0x889B, true, true, {} }, // 457
- { "TRCSSPCICR4", 0x88A3, true, true, {} }, // 458
- { "TRCSSPCICR5", 0x88AB, true, true, {} }, // 459
- { "TRCSSPCICR6", 0x88B3, true, true, {} }, // 460
- { "TRCSSPCICR7", 0x88BB, true, true, {} }, // 461
- { "TRCPDCR", 0x88A4, true, true, {} }, // 462
- { "TRCACVR0", 0x8900, true, true, {} }, // 463
- { "TRCACVR1", 0x8910, true, true, {} }, // 464
- { "TRCACVR2", 0x8920, true, true, {} }, // 465
- { "TRCACVR3", 0x8930, true, true, {} }, // 466
- { "TRCACVR4", 0x8940, true, true, {} }, // 467
- { "TRCACVR5", 0x8950, true, true, {} }, // 468
- { "TRCACVR6", 0x8960, true, true, {} }, // 469
- { "TRCACVR7", 0x8970, true, true, {} }, // 470
- { "TRCACVR8", 0x8901, true, true, {} }, // 471
- { "TRCACVR9", 0x8911, true, true, {} }, // 472
- { "TRCACVR10", 0x8921, true, true, {} }, // 473
- { "TRCACVR11", 0x8931, true, true, {} }, // 474
- { "TRCACVR12", 0x8941, true, true, {} }, // 475
- { "TRCACVR13", 0x8951, true, true, {} }, // 476
- { "TRCACVR14", 0x8961, true, true, {} }, // 477
- { "TRCACVR15", 0x8971, true, true, {} }, // 478
- { "TRCACATR0", 0x8902, true, true, {} }, // 479
- { "TRCACATR1", 0x8912, true, true, {} }, // 480
- { "TRCACATR2", 0x8922, true, true, {} }, // 481
- { "TRCACATR3", 0x8932, true, true, {} }, // 482
- { "TRCACATR4", 0x8942, true, true, {} }, // 483
- { "TRCACATR5", 0x8952, true, true, {} }, // 484
- { "TRCACATR6", 0x8962, true, true, {} }, // 485
- { "TRCACATR7", 0x8972, true, true, {} }, // 486
- { "TRCACATR8", 0x8903, true, true, {} }, // 487
- { "TRCACATR9", 0x8913, true, true, {} }, // 488
- { "TRCACATR10", 0x8923, true, true, {} }, // 489
- { "TRCACATR11", 0x8933, true, true, {} }, // 490
- { "TRCACATR12", 0x8943, true, true, {} }, // 491
- { "TRCACATR13", 0x8953, true, true, {} }, // 492
- { "TRCACATR14", 0x8963, true, true, {} }, // 493
- { "TRCACATR15", 0x8973, true, true, {} }, // 494
- { "TRCDVCVR0", 0x8904, true, true, {} }, // 495
- { "TRCDVCVR1", 0x8924, true, true, {} }, // 496
- { "TRCDVCVR2", 0x8944, true, true, {} }, // 497
- { "TRCDVCVR3", 0x8964, true, true, {} }, // 498
- { "TRCDVCVR4", 0x8905, true, true, {} }, // 499
- { "TRCDVCVR5", 0x8925, true, true, {} }, // 500
- { "TRCDVCVR6", 0x8945, true, true, {} }, // 501
- { "TRCDVCVR7", 0x8965, true, true, {} }, // 502
- { "TRCDVCMR0", 0x8906, true, true, {} }, // 503
- { "TRCDVCMR1", 0x8926, true, true, {} }, // 504
- { "TRCDVCMR2", 0x8946, true, true, {} }, // 505
- { "TRCDVCMR3", 0x8966, true, true, {} }, // 506
- { "TRCDVCMR4", 0x8907, true, true, {} }, // 507
- { "TRCDVCMR5", 0x8927, true, true, {} }, // 508
- { "TRCDVCMR6", 0x8947, true, true, {} }, // 509
- { "TRCDVCMR7", 0x8967, true, true, {} }, // 510
- { "TRCCIDCVR0", 0x8980, true, true, {} }, // 511
- { "TRCCIDCVR1", 0x8990, true, true, {} }, // 512
- { "TRCCIDCVR2", 0x89A0, true, true, {} }, // 513
- { "TRCCIDCVR3", 0x89B0, true, true, {} }, // 514
- { "TRCCIDCVR4", 0x89C0, true, true, {} }, // 515
- { "TRCCIDCVR5", 0x89D0, true, true, {} }, // 516
- { "TRCCIDCVR6", 0x89E0, true, true, {} }, // 517
- { "TRCCIDCVR7", 0x89F0, true, true, {} }, // 518
- { "TRCVMIDCVR0", 0x8981, true, true, {} }, // 519
- { "TRCVMIDCVR1", 0x8991, true, true, {} }, // 520
- { "TRCVMIDCVR2", 0x89A1, true, true, {} }, // 521
- { "TRCVMIDCVR3", 0x89B1, true, true, {} }, // 522
- { "TRCVMIDCVR4", 0x89C1, true, true, {} }, // 523
- { "TRCVMIDCVR5", 0x89D1, true, true, {} }, // 524
- { "TRCVMIDCVR6", 0x89E1, true, true, {} }, // 525
- { "TRCVMIDCVR7", 0x89F1, true, true, {} }, // 526
- { "TRCCIDCCTLR0", 0x8982, true, true, {} }, // 527
- { "TRCCIDCCTLR1", 0x898A, true, true, {} }, // 528
- { "TRCVMIDCCTLR0", 0x8992, true, true, {} }, // 529
- { "TRCVMIDCCTLR1", 0x899A, true, true, {} }, // 530
- { "TRCITCTRL", 0x8B84, true, true, {} }, // 531
- { "TRCCLAIMSET", 0x8BC6, true, true, {} }, // 532
- { "TRCCLAIMCLR", 0x8BCE, true, true, {} }, // 533
- { "ICC_BPR1_EL1", 0xC663, true, true, {} }, // 534
- { "ICC_BPR0_EL1", 0xC643, true, true, {} }, // 535
- { "ICC_PMR_EL1", 0xC230, true, true, {} }, // 536
- { "ICC_CTLR_EL1", 0xC664, true, true, {} }, // 537
- { "ICC_CTLR_EL3", 0xF664, true, true, {} }, // 538
- { "ICC_SRE_EL1", 0xC665, true, true, {} }, // 539
- { "ICC_SRE_EL2", 0xE64D, true, true, {} }, // 540
- { "ICC_SRE_EL3", 0xF665, true, true, {} }, // 541
- { "ICC_IGRPEN0_EL1", 0xC666, true, true, {} }, // 542
- { "ICC_IGRPEN1_EL1", 0xC667, true, true, {} }, // 543
- { "ICC_IGRPEN1_EL3", 0xF667, true, true, {} }, // 544
- { "ICC_SEIEN_EL1", 0xC668, true, true, {} }, // 545
- { "ICC_AP0R0_EL1", 0xC644, true, true, {} }, // 546
- { "ICC_AP0R1_EL1", 0xC645, true, true, {} }, // 547
- { "ICC_AP0R2_EL1", 0xC646, true, true, {} }, // 548
- { "ICC_AP0R3_EL1", 0xC647, true, true, {} }, // 549
- { "ICC_AP1R0_EL1", 0xC648, true, true, {} }, // 550
- { "ICC_AP1R1_EL1", 0xC649, true, true, {} }, // 551
- { "ICC_AP1R2_EL1", 0xC64A, true, true, {} }, // 552
- { "ICC_AP1R3_EL1", 0xC64B, true, true, {} }, // 553
- { "ICH_AP0R0_EL2", 0xE640, true, true, {} }, // 554
- { "ICH_AP0R1_EL2", 0xE641, true, true, {} }, // 555
- { "ICH_AP0R2_EL2", 0xE642, true, true, {} }, // 556
- { "ICH_AP0R3_EL2", 0xE643, true, true, {} }, // 557
- { "ICH_AP1R0_EL2", 0xE648, true, true, {} }, // 558
- { "ICH_AP1R1_EL2", 0xE649, true, true, {} }, // 559
- { "ICH_AP1R2_EL2", 0xE64A, true, true, {} }, // 560
- { "ICH_AP1R3_EL2", 0xE64B, true, true, {} }, // 561
- { "ICH_HCR_EL2", 0xE658, true, true, {} }, // 562
- { "ICH_MISR_EL2", 0xE65A, true, true, {} }, // 563
- { "ICH_VMCR_EL2", 0xE65F, true, true, {} }, // 564
- { "ICH_VSEIR_EL2", 0xE64C, true, true, {} }, // 565
- { "ICH_LR0_EL2", 0xE660, true, true, {} }, // 566
- { "ICH_LR1_EL2", 0xE661, true, true, {} }, // 567
- { "ICH_LR2_EL2", 0xE662, true, true, {} }, // 568
- { "ICH_LR3_EL2", 0xE663, true, true, {} }, // 569
- { "ICH_LR4_EL2", 0xE664, true, true, {} }, // 570
- { "ICH_LR5_EL2", 0xE665, true, true, {} }, // 571
- { "ICH_LR6_EL2", 0xE666, true, true, {} }, // 572
- { "ICH_LR7_EL2", 0xE667, true, true, {} }, // 573
- { "ICH_LR8_EL2", 0xE668, true, true, {} }, // 574
- { "ICH_LR9_EL2", 0xE669, true, true, {} }, // 575
- { "ICH_LR10_EL2", 0xE66A, true, true, {} }, // 576
- { "ICH_LR11_EL2", 0xE66B, true, true, {} }, // 577
- { "ICH_LR12_EL2", 0xE66C, true, true, {} }, // 578
- { "ICH_LR13_EL2", 0xE66D, true, true, {} }, // 579
- { "ICH_LR14_EL2", 0xE66E, true, true, {} }, // 580
- { "ICH_LR15_EL2", 0xE66F, true, true, {} }, // 581
- { "PAN", 0xC213, true, true, {AArch64::HasV8_1aOps} }, // 582
- { "LORSA_EL1", 0xC520, true, true, {AArch64::HasV8_1aOps} }, // 583
- { "LOREA_EL1", 0xC521, true, true, {AArch64::HasV8_1aOps} }, // 584
- { "LORN_EL1", 0xC522, true, true, {AArch64::HasV8_1aOps} }, // 585
- { "LORC_EL1", 0xC523, true, true, {AArch64::HasV8_1aOps} }, // 586
- { "TTBR1_EL2", 0xE101, true, true, {AArch64::HasV8_1aOps} }, // 587
- { "CONTEXTIDR_EL2", 0xE681, true, true, {AArch64::HasV8_1aOps} }, // 588
- { "CNTHV_TVAL_EL2", 0xE718, true, true, {AArch64::HasV8_1aOps} }, // 589
- { "CNTHV_CVAL_EL2", 0xE71A, true, true, {AArch64::HasV8_1aOps} }, // 590
- { "CNTHV_CTL_EL2", 0xE719, true, true, {AArch64::HasV8_1aOps} }, // 591
- { "SCTLR_EL12", 0xE880, true, true, {AArch64::HasV8_1aOps} }, // 592
- { "CPACR_EL12", 0xE882, true, true, {AArch64::HasV8_1aOps} }, // 593
- { "TTBR0_EL12", 0xE900, true, true, {AArch64::HasV8_1aOps} }, // 594
- { "TTBR1_EL12", 0xE901, true, true, {AArch64::HasV8_1aOps} }, // 595
- { "TCR_EL12", 0xE902, true, true, {AArch64::HasV8_1aOps} }, // 596
- { "AFSR0_EL12", 0xEA88, true, true, {AArch64::HasV8_1aOps} }, // 597
- { "AFSR1_EL12", 0xEA89, true, true, {AArch64::HasV8_1aOps} }, // 598
- { "ESR_EL12", 0xEA90, true, true, {AArch64::HasV8_1aOps} }, // 599
- { "FAR_EL12", 0xEB00, true, true, {AArch64::HasV8_1aOps} }, // 600
- { "MAIR_EL12", 0xED10, true, true, {AArch64::HasV8_1aOps} }, // 601
- { "AMAIR_EL12", 0xED18, true, true, {AArch64::HasV8_1aOps} }, // 602
- { "VBAR_EL12", 0xEE00, true, true, {AArch64::HasV8_1aOps} }, // 603
- { "CONTEXTIDR_EL12", 0xEE81, true, true, {AArch64::HasV8_1aOps} }, // 604
- { "CNTKCTL_EL12", 0xEF08, true, true, {AArch64::HasV8_1aOps} }, // 605
- { "CNTP_TVAL_EL02", 0xEF10, true, true, {AArch64::HasV8_1aOps} }, // 606
- { "CNTP_CTL_EL02", 0xEF11, true, true, {AArch64::HasV8_1aOps} }, // 607
- { "CNTP_CVAL_EL02", 0xEF12, true, true, {AArch64::HasV8_1aOps} }, // 608
- { "CNTV_TVAL_EL02", 0xEF18, true, true, {AArch64::HasV8_1aOps} }, // 609
- { "CNTV_CTL_EL02", 0xEF19, true, true, {AArch64::HasV8_1aOps} }, // 610
- { "CNTV_CVAL_EL02", 0xEF1A, true, true, {AArch64::HasV8_1aOps} }, // 611
- { "SPSR_EL12", 0xEA00, true, true, {AArch64::HasV8_1aOps} }, // 612
- { "ELR_EL12", 0xEA01, true, true, {AArch64::HasV8_1aOps} }, // 613
- { "UAO", 0xC214, true, true, {AArch64::HasV8_2aOps} }, // 614
- { "PMBLIMITR_EL1", 0xC4D0, true, true, {AArch64::FeatureSPE} }, // 615
- { "PMBPTR_EL1", 0xC4D1, true, true, {AArch64::FeatureSPE} }, // 616
- { "PMBSR_EL1", 0xC4D3, true, true, {AArch64::FeatureSPE} }, // 617
- { "PMBIDR_EL1", 0xC4D7, true, true, {AArch64::FeatureSPE} }, // 618
- { "PMSCR_EL2", 0xE4C8, true, true, {AArch64::FeatureSPE} }, // 619
- { "PMSCR_EL12", 0xECC8, true, true, {AArch64::FeatureSPE} }, // 620
- { "PMSCR_EL1", 0xC4C8, true, true, {AArch64::FeatureSPE} }, // 621
- { "PMSICR_EL1", 0xC4CA, true, true, {AArch64::FeatureSPE} }, // 622
- { "PMSIRR_EL1", 0xC4CB, true, true, {AArch64::FeatureSPE} }, // 623
- { "PMSFCR_EL1", 0xC4CC, true, true, {AArch64::FeatureSPE} }, // 624
- { "PMSEVFR_EL1", 0xC4CD, true, true, {AArch64::FeatureSPE} }, // 625
- { "PMSLATFR_EL1", 0xC4CE, true, true, {AArch64::FeatureSPE} }, // 626
- { "PMSIDR_EL1", 0xC4CF, true, true, {AArch64::FeatureSPE} }, // 627
- { "ERRSELR_EL1", 0xC299, true, true, {AArch64::FeatureRAS} }, // 628
- { "ERXCTLR_EL1", 0xC2A1, true, true, {AArch64::FeatureRAS} }, // 629
- { "ERXSTATUS_EL1", 0xC2A2, true, true, {AArch64::FeatureRAS} }, // 630
- { "ERXADDR_EL1", 0xC2A3, true, true, {AArch64::FeatureRAS} }, // 631
- { "ERXMISC0_EL1", 0xC2A8, true, true, {AArch64::FeatureRAS} }, // 632
- { "ERXMISC1_EL1", 0xC2A9, true, true, {AArch64::FeatureRAS} }, // 633
- { "DISR_EL1", 0xC609, true, true, {AArch64::FeatureRAS} }, // 634
- { "VDISR_EL2", 0xE609, true, true, {AArch64::FeatureRAS} }, // 635
- { "VSESR_EL2", 0xE293, true, true, {AArch64::FeatureRAS} }, // 636
- { "APIAKeyLo_EL1", 0xC108, true, true, {AArch64::HasV8_3aOps} }, // 637
- { "APIAKeyHi_EL1", 0xC109, true, true, {AArch64::HasV8_3aOps} }, // 638
- { "APIBKeyLo_EL1", 0xC10A, true, true, {AArch64::HasV8_3aOps} }, // 639
- { "APIBKeyHi_EL1", 0xC10B, true, true, {AArch64::HasV8_3aOps} }, // 640
- { "APDAKeyLo_EL1", 0xC110, true, true, {AArch64::HasV8_3aOps} }, // 641
- { "APDAKeyHi_EL1", 0xC111, true, true, {AArch64::HasV8_3aOps} }, // 642
- { "APDBKeyLo_EL1", 0xC112, true, true, {AArch64::HasV8_3aOps} }, // 643
- { "APDBKeyHi_EL1", 0xC113, true, true, {AArch64::HasV8_3aOps} }, // 644
- { "APGAKeyLo_EL1", 0xC118, true, true, {AArch64::HasV8_3aOps} }, // 645
- { "APGAKeyHi_EL1", 0xC119, true, true, {AArch64::HasV8_3aOps} }, // 646
- { "VSTCR_EL2", 0xE132, true, true, {AArch64::HasV8_4aOps} }, // 647
- { "VSTTBR_EL2", 0xE130, true, true, {AArch64::HasV8_4aOps} }, // 648
- { "CNTHVS_TVAL_EL2", 0xE720, true, true, {AArch64::HasV8_4aOps} }, // 649
- { "CNTHVS_CVAL_EL2", 0xE722, true, true, {AArch64::HasV8_4aOps} }, // 650
- { "CNTHVS_CTL_EL2", 0xE721, true, true, {AArch64::HasV8_4aOps} }, // 651
- { "CNTHPS_TVAL_EL2", 0xE728, true, true, {AArch64::HasV8_4aOps} }, // 652
- { "CNTHPS_CVAL_EL2", 0xE72A, true, true, {AArch64::HasV8_4aOps} }, // 653
- { "CNTHPS_CTL_EL2", 0xE729, true, true, {AArch64::HasV8_4aOps} }, // 654
- { "SDER32_EL2", 0xE099, true, true, {AArch64::HasV8_4aOps} }, // 655
- { "ERXPFGCTL_EL1", 0xC2A5, true, true, {AArch64::HasV8_4aOps} }, // 656
- { "ERXPFGCDN_EL1", 0xC2A6, true, true, {AArch64::HasV8_4aOps} }, // 657
- { "ERXTS_EL1", 0xC2AF, true, true, {AArch64::HasV8_4aOps} }, // 658
- { "ERXMISC2_EL1", 0xC2AA, true, true, {AArch64::HasV8_4aOps} }, // 659
- { "ERXMISC3_EL1", 0xC2AB, true, true, {AArch64::HasV8_4aOps} }, // 660
- { "ERXPFGF_EL1", 0xC2A4, true, false, {AArch64::HasV8_4aOps} }, // 661
- { "MPAM0_EL1", 0xC529, true, true, {AArch64::HasV8_4aOps} }, // 662
- { "MPAM1_EL1", 0xC528, true, true, {AArch64::HasV8_4aOps} }, // 663
- { "MPAM2_EL2", 0xE528, true, true, {AArch64::HasV8_4aOps} }, // 664
- { "MPAM3_EL3", 0xF528, true, true, {AArch64::HasV8_4aOps} }, // 665
- { "MPAM1_EL12", 0xED28, true, true, {AArch64::HasV8_4aOps} }, // 666
- { "MPAMHCR_EL2", 0xE520, true, true, {AArch64::HasV8_4aOps} }, // 667
- { "MPAMVPMV_EL2", 0xE521, true, true, {AArch64::HasV8_4aOps} }, // 668
- { "MPAMVPM0_EL2", 0xE530, true, true, {AArch64::HasV8_4aOps} }, // 669
- { "MPAMVPM1_EL2", 0xE531, true, true, {AArch64::HasV8_4aOps} }, // 670
- { "MPAMVPM2_EL2", 0xE532, true, true, {AArch64::HasV8_4aOps} }, // 671
- { "MPAMVPM3_EL2", 0xE533, true, true, {AArch64::HasV8_4aOps} }, // 672
- { "MPAMVPM4_EL2", 0xE534, true, true, {AArch64::HasV8_4aOps} }, // 673
- { "MPAMVPM5_EL2", 0xE535, true, true, {AArch64::HasV8_4aOps} }, // 674
- { "MPAMVPM6_EL2", 0xE536, true, true, {AArch64::HasV8_4aOps} }, // 675
- { "MPAMVPM7_EL2", 0xE537, true, true, {AArch64::HasV8_4aOps} }, // 676
- { "MPAMIDR_EL1", 0xC524, true, false, {AArch64::HasV8_4aOps} }, // 677
- { "AMCR_EL0", 0xDE90, true, true, {AArch64::HasV8_4aOps} }, // 678
- { "AMCFGR_EL0", 0xDE91, true, false, {AArch64::HasV8_4aOps} }, // 679
- { "AMCGCR_EL0", 0xDE92, true, false, {AArch64::HasV8_4aOps} }, // 680
- { "AMUSERENR_EL0", 0xDE93, true, true, {AArch64::HasV8_4aOps} }, // 681
- { "AMCNTENCLR0_EL0", 0xDE94, true, true, {AArch64::HasV8_4aOps} }, // 682
- { "AMCNTENSET0_EL0", 0xDE95, true, true, {AArch64::HasV8_4aOps} }, // 683
- { "AMEVCNTR00_EL0", 0xDEA0, true, true, {AArch64::HasV8_4aOps} }, // 684
- { "AMEVCNTR01_EL0", 0xDEA1, true, true, {AArch64::HasV8_4aOps} }, // 685
- { "AMEVCNTR02_EL0", 0xDEA2, true, true, {AArch64::HasV8_4aOps} }, // 686
- { "AMEVCNTR03_EL0", 0xDEA3, true, true, {AArch64::HasV8_4aOps} }, // 687
- { "AMEVTYPER00_EL0", 0xDEB0, true, false, {AArch64::HasV8_4aOps} }, // 688
- { "AMEVTYPER01_EL0", 0xDEB1, true, false, {AArch64::HasV8_4aOps} }, // 689
- { "AMEVTYPER02_EL0", 0xDEB2, true, false, {AArch64::HasV8_4aOps} }, // 690
- { "AMEVTYPER03_EL0", 0xDEB3, true, false, {AArch64::HasV8_4aOps} }, // 691
- { "AMCNTENCLR1_EL0", 0xDE98, true, true, {AArch64::HasV8_4aOps} }, // 692
- { "AMCNTENSET1_EL0", 0xDE99, true, true, {AArch64::HasV8_4aOps} }, // 693
- { "AMEVCNTR10_EL0", 0xDEE0, true, true, {AArch64::HasV8_4aOps} }, // 694
- { "AMEVCNTR11_EL0", 0xDEE1, true, true, {AArch64::HasV8_4aOps} }, // 695
- { "AMEVCNTR12_EL0", 0xDEE2, true, true, {AArch64::HasV8_4aOps} }, // 696
- { "AMEVCNTR13_EL0", 0xDEE3, true, true, {AArch64::HasV8_4aOps} }, // 697
- { "AMEVCNTR14_EL0", 0xDEE4, true, true, {AArch64::HasV8_4aOps} }, // 698
- { "AMEVCNTR15_EL0", 0xDEE5, true, true, {AArch64::HasV8_4aOps} }, // 699
- { "AMEVCNTR16_EL0", 0xDEE6, true, true, {AArch64::HasV8_4aOps} }, // 700
- { "AMEVCNTR17_EL0", 0xDEE7, true, true, {AArch64::HasV8_4aOps} }, // 701
- { "AMEVCNTR18_EL0", 0xDEE8, true, true, {AArch64::HasV8_4aOps} }, // 702
- { "AMEVCNTR19_EL0", 0xDEE9, true, true, {AArch64::HasV8_4aOps} }, // 703
- { "AMEVCNTR110_EL0", 0xDEEA, true, true, {AArch64::HasV8_4aOps} }, // 704
- { "AMEVCNTR111_EL0", 0xDEEB, true, true, {AArch64::HasV8_4aOps} }, // 705
- { "AMEVCNTR112_EL0", 0xDEEC, true, true, {AArch64::HasV8_4aOps} }, // 706
- { "AMEVCNTR113_EL0", 0xDEED, true, true, {AArch64::HasV8_4aOps} }, // 707
- { "AMEVCNTR114_EL0", 0xDEEE, true, true, {AArch64::HasV8_4aOps} }, // 708
- { "AMEVCNTR115_EL0", 0xDEEF, true, true, {AArch64::HasV8_4aOps} }, // 709
- { "AMEVTYPER10_EL0", 0xDEF0, true, true, {AArch64::HasV8_4aOps} }, // 710
- { "AMEVTYPER11_EL0", 0xDEF1, true, true, {AArch64::HasV8_4aOps} }, // 711
- { "AMEVTYPER12_EL0", 0xDEF2, true, true, {AArch64::HasV8_4aOps} }, // 712
- { "AMEVTYPER13_EL0", 0xDEF3, true, true, {AArch64::HasV8_4aOps} }, // 713
- { "AMEVTYPER14_EL0", 0xDEF4, true, true, {AArch64::HasV8_4aOps} }, // 714
- { "AMEVTYPER15_EL0", 0xDEF5, true, true, {AArch64::HasV8_4aOps} }, // 715
- { "AMEVTYPER16_EL0", 0xDEF6, true, true, {AArch64::HasV8_4aOps} }, // 716
- { "AMEVTYPER17_EL0", 0xDEF7, true, true, {AArch64::HasV8_4aOps} }, // 717
- { "AMEVTYPER18_EL0", 0xDEF8, true, true, {AArch64::HasV8_4aOps} }, // 718
- { "AMEVTYPER19_EL0", 0xDEF9, true, true, {AArch64::HasV8_4aOps} }, // 719
- { "AMEVTYPER110_EL0", 0xDEFA, true, true, {AArch64::HasV8_4aOps} }, // 720
- { "AMEVTYPER111_EL0", 0xDEFB, true, true, {AArch64::HasV8_4aOps} }, // 721
- { "AMEVTYPER112_EL0", 0xDEFC, true, true, {AArch64::HasV8_4aOps} }, // 722
- { "AMEVTYPER113_EL0", 0xDEFD, true, true, {AArch64::HasV8_4aOps} }, // 723
- { "AMEVTYPER114_EL0", 0xDEFE, true, true, {AArch64::HasV8_4aOps} }, // 724
- { "AMEVTYPER115_EL0", 0xDEFF, true, true, {AArch64::HasV8_4aOps} }, // 725
- { "TRFCR_EL1", 0xC091, true, true, {AArch64::HasV8_4aOps} }, // 726
- { "TRFCR_EL2", 0xE091, true, true, {AArch64::HasV8_4aOps} }, // 727
- { "TRFCR_EL12", 0xE891, true, true, {AArch64::HasV8_4aOps} }, // 728
- { "DIT", 0xDA15, true, true, {AArch64::HasV8_4aOps} }, // 729
- { "VNCR_EL2", 0xE110, true, true, {AArch64::HasV8_4aOps} }, // 730
- { "CPM_IOACC_CTL_EL3", 0xFF90, true, true, {AArch64::ProcCyclone} }, // 731
+ { "ID_AA64ZFR0_EL1", 0xC024, true, false, {AArch64::FeatureSVE} }, // 96
+ { "LORID_EL1", 0xC527, true, false, {AArch64::HasV8_1aOps} }, // 97
+ { "ERRIDR_EL1", 0xC298, true, false, {AArch64::FeatureRAS} }, // 98
+ { "ERXFR_EL1", 0xC2A0, true, false, {AArch64::FeatureRAS} }, // 99
+ { "DBGDTRTX_EL0", 0x9828, false, true, {} }, // 100
+ { "OSLAR_EL1", 0x8084, false, true, {} }, // 101
+ { "PMSWINC_EL0", 0xDCE4, false, true, {} }, // 102
+ { "TRCOSLAR", 0x8884, false, true, {} }, // 103
+ { "TRCLAR", 0x8BE6, false, true, {} }, // 104
+ { "ICC_EOIR1_EL1", 0xC661, false, true, {} }, // 105
+ { "ICC_EOIR0_EL1", 0xC641, false, true, {} }, // 106
+ { "ICC_DIR_EL1", 0xC659, false, true, {} }, // 107
+ { "ICC_SGI1R_EL1", 0xC65D, false, true, {} }, // 108
+ { "ICC_ASGI1R_EL1", 0xC65E, false, true, {} }, // 109
+ { "ICC_SGI0R_EL1", 0xC65F, false, true, {} }, // 110
+ { "OSDTRRX_EL1", 0x8002, true, true, {} }, // 111
+ { "OSDTRTX_EL1", 0x801A, true, true, {} }, // 112
+ { "TEECR32_EL1", 0x9000, true, true, {} }, // 113
+ { "MDCCINT_EL1", 0x8010, true, true, {} }, // 114
+ { "MDSCR_EL1", 0x8012, true, true, {} }, // 115
+ { "DBGDTR_EL0", 0x9820, true, true, {} }, // 116
+ { "OSECCR_EL1", 0x8032, true, true, {} }, // 117
+ { "DBGVCR32_EL2", 0xA038, true, true, {} }, // 118
+ { "DBGBVR0_EL1", 0x8004, true, true, {} }, // 119
+ { "DBGBVR1_EL1", 0x800C, true, true, {} }, // 120
+ { "DBGBVR2_EL1", 0x8014, true, true, {} }, // 121
+ { "DBGBVR3_EL1", 0x801C, true, true, {} }, // 122
+ { "DBGBVR4_EL1", 0x8024, true, true, {} }, // 123
+ { "DBGBVR5_EL1", 0x802C, true, true, {} }, // 124
+ { "DBGBVR6_EL1", 0x8034, true, true, {} }, // 125
+ { "DBGBVR7_EL1", 0x803C, true, true, {} }, // 126
+ { "DBGBVR8_EL1", 0x8044, true, true, {} }, // 127
+ { "DBGBVR9_EL1", 0x804C, true, true, {} }, // 128
+ { "DBGBVR10_EL1", 0x8054, true, true, {} }, // 129
+ { "DBGBVR11_EL1", 0x805C, true, true, {} }, // 130
+ { "DBGBVR12_EL1", 0x8064, true, true, {} }, // 131
+ { "DBGBVR13_EL1", 0x806C, true, true, {} }, // 132
+ { "DBGBVR14_EL1", 0x8074, true, true, {} }, // 133
+ { "DBGBVR15_EL1", 0x807C, true, true, {} }, // 134
+ { "DBGBCR0_EL1", 0x8005, true, true, {} }, // 135
+ { "DBGBCR1_EL1", 0x800D, true, true, {} }, // 136
+ { "DBGBCR2_EL1", 0x8015, true, true, {} }, // 137
+ { "DBGBCR3_EL1", 0x801D, true, true, {} }, // 138
+ { "DBGBCR4_EL1", 0x8025, true, true, {} }, // 139
+ { "DBGBCR5_EL1", 0x802D, true, true, {} }, // 140
+ { "DBGBCR6_EL1", 0x8035, true, true, {} }, // 141
+ { "DBGBCR7_EL1", 0x803D, true, true, {} }, // 142
+ { "DBGBCR8_EL1", 0x8045, true, true, {} }, // 143
+ { "DBGBCR9_EL1", 0x804D, true, true, {} }, // 144
+ { "DBGBCR10_EL1", 0x8055, true, true, {} }, // 145
+ { "DBGBCR11_EL1", 0x805D, true, true, {} }, // 146
+ { "DBGBCR12_EL1", 0x8065, true, true, {} }, // 147
+ { "DBGBCR13_EL1", 0x806D, true, true, {} }, // 148
+ { "DBGBCR14_EL1", 0x8075, true, true, {} }, // 149
+ { "DBGBCR15_EL1", 0x807D, true, true, {} }, // 150
+ { "DBGWVR0_EL1", 0x8006, true, true, {} }, // 151
+ { "DBGWVR1_EL1", 0x800E, true, true, {} }, // 152
+ { "DBGWVR2_EL1", 0x8016, true, true, {} }, // 153
+ { "DBGWVR3_EL1", 0x801E, true, true, {} }, // 154
+ { "DBGWVR4_EL1", 0x8026, true, true, {} }, // 155
+ { "DBGWVR5_EL1", 0x802E, true, true, {} }, // 156
+ { "DBGWVR6_EL1", 0x8036, true, true, {} }, // 157
+ { "DBGWVR7_EL1", 0x803E, true, true, {} }, // 158
+ { "DBGWVR8_EL1", 0x8046, true, true, {} }, // 159
+ { "DBGWVR9_EL1", 0x804E, true, true, {} }, // 160
+ { "DBGWVR10_EL1", 0x8056, true, true, {} }, // 161
+ { "DBGWVR11_EL1", 0x805E, true, true, {} }, // 162
+ { "DBGWVR12_EL1", 0x8066, true, true, {} }, // 163
+ { "DBGWVR13_EL1", 0x806E, true, true, {} }, // 164
+ { "DBGWVR14_EL1", 0x8076, true, true, {} }, // 165
+ { "DBGWVR15_EL1", 0x807E, true, true, {} }, // 166
+ { "DBGWCR0_EL1", 0x8007, true, true, {} }, // 167
+ { "DBGWCR1_EL1", 0x800F, true, true, {} }, // 168
+ { "DBGWCR2_EL1", 0x8017, true, true, {} }, // 169
+ { "DBGWCR3_EL1", 0x801F, true, true, {} }, // 170
+ { "DBGWCR4_EL1", 0x8027, true, true, {} }, // 171
+ { "DBGWCR5_EL1", 0x802F, true, true, {} }, // 172
+ { "DBGWCR6_EL1", 0x8037, true, true, {} }, // 173
+ { "DBGWCR7_EL1", 0x803F, true, true, {} }, // 174
+ { "DBGWCR8_EL1", 0x8047, true, true, {} }, // 175
+ { "DBGWCR9_EL1", 0x804F, true, true, {} }, // 176
+ { "DBGWCR10_EL1", 0x8057, true, true, {} }, // 177
+ { "DBGWCR11_EL1", 0x805F, true, true, {} }, // 178
+ { "DBGWCR12_EL1", 0x8067, true, true, {} }, // 179
+ { "DBGWCR13_EL1", 0x806F, true, true, {} }, // 180
+ { "DBGWCR14_EL1", 0x8077, true, true, {} }, // 181
+ { "DBGWCR15_EL1", 0x807F, true, true, {} }, // 182
+ { "TEEHBR32_EL1", 0x9080, true, true, {} }, // 183
+ { "OSDLR_EL1", 0x809C, true, true, {} }, // 184
+ { "DBGPRCR_EL1", 0x80A4, true, true, {} }, // 185
+ { "DBGCLAIMSET_EL1", 0x83C6, true, true, {} }, // 186
+ { "DBGCLAIMCLR_EL1", 0x83CE, true, true, {} }, // 187
+ { "CSSELR_EL1", 0xD000, true, true, {} }, // 188
+ { "VPIDR_EL2", 0xE000, true, true, {} }, // 189
+ { "VMPIDR_EL2", 0xE005, true, true, {} }, // 190
+ { "CPACR_EL1", 0xC082, true, true, {} }, // 191
+ { "SCTLR_EL1", 0xC080, true, true, {} }, // 192
+ { "SCTLR_EL2", 0xE080, true, true, {} }, // 193
+ { "SCTLR_EL3", 0xF080, true, true, {} }, // 194
+ { "ACTLR_EL1", 0xC081, true, true, {} }, // 195
+ { "ACTLR_EL2", 0xE081, true, true, {} }, // 196
+ { "ACTLR_EL3", 0xF081, true, true, {} }, // 197
+ { "HCR_EL2", 0xE088, true, true, {} }, // 198
+ { "SCR_EL3", 0xF088, true, true, {} }, // 199
+ { "MDCR_EL2", 0xE089, true, true, {} }, // 200
+ { "SDER32_EL3", 0xF089, true, true, {} }, // 201
+ { "CPTR_EL2", 0xE08A, true, true, {} }, // 202
+ { "CPTR_EL3", 0xF08A, true, true, {} }, // 203
+ { "HSTR_EL2", 0xE08B, true, true, {} }, // 204
+ { "HACR_EL2", 0xE08F, true, true, {} }, // 205
+ { "MDCR_EL3", 0xF099, true, true, {} }, // 206
+ { "TTBR0_EL1", 0xC100, true, true, {} }, // 207
+ { "TTBR0_EL2", 0xE100, true, true, {} }, // 208
+ { "TTBR0_EL3", 0xF100, true, true, {} }, // 209
+ { "TTBR1_EL1", 0xC101, true, true, {} }, // 210
+ { "TCR_EL1", 0xC102, true, true, {} }, // 211
+ { "TCR_EL2", 0xE102, true, true, {} }, // 212
+ { "TCR_EL3", 0xF102, true, true, {} }, // 213
+ { "VTTBR_EL2", 0xE108, true, true, {} }, // 214
+ { "VTCR_EL2", 0xE10A, true, true, {} }, // 215
+ { "DACR32_EL2", 0xE180, true, true, {} }, // 216
+ { "SPSR_EL1", 0xC200, true, true, {} }, // 217
+ { "SPSR_EL2", 0xE200, true, true, {} }, // 218
+ { "SPSR_EL3", 0xF200, true, true, {} }, // 219
+ { "ELR_EL1", 0xC201, true, true, {} }, // 220
+ { "ELR_EL2", 0xE201, true, true, {} }, // 221
+ { "ELR_EL3", 0xF201, true, true, {} }, // 222
+ { "SP_EL0", 0xC208, true, true, {} }, // 223
+ { "SP_EL1", 0xE208, true, true, {} }, // 224
+ { "SP_EL2", 0xF208, true, true, {} }, // 225
+ { "SPSel", 0xC210, true, true, {} }, // 226
+ { "NZCV", 0xDA10, true, true, {} }, // 227
+ { "DAIF", 0xDA11, true, true, {} }, // 228
+ { "CurrentEL", 0xC212, true, true, {} }, // 229
+ { "SPSR_irq", 0xE218, true, true, {} }, // 230
+ { "SPSR_abt", 0xE219, true, true, {} }, // 231
+ { "SPSR_und", 0xE21A, true, true, {} }, // 232
+ { "SPSR_fiq", 0xE21B, true, true, {} }, // 233
+ { "FPCR", 0xDA20, true, true, {} }, // 234
+ { "FPSR", 0xDA21, true, true, {} }, // 235
+ { "DSPSR_EL0", 0xDA28, true, true, {} }, // 236
+ { "DLR_EL0", 0xDA29, true, true, {} }, // 237
+ { "IFSR32_EL2", 0xE281, true, true, {} }, // 238
+ { "AFSR0_EL1", 0xC288, true, true, {} }, // 239
+ { "AFSR0_EL2", 0xE288, true, true, {} }, // 240
+ { "AFSR0_EL3", 0xF288, true, true, {} }, // 241
+ { "AFSR1_EL1", 0xC289, true, true, {} }, // 242
+ { "AFSR1_EL2", 0xE289, true, true, {} }, // 243
+ { "AFSR1_EL3", 0xF289, true, true, {} }, // 244
+ { "ESR_EL1", 0xC290, true, true, {} }, // 245
+ { "ESR_EL2", 0xE290, true, true, {} }, // 246
+ { "ESR_EL3", 0xF290, true, true, {} }, // 247
+ { "FPEXC32_EL2", 0xE298, true, true, {} }, // 248
+ { "FAR_EL1", 0xC300, true, true, {} }, // 249
+ { "FAR_EL2", 0xE300, true, true, {} }, // 250
+ { "FAR_EL3", 0xF300, true, true, {} }, // 251
+ { "HPFAR_EL2", 0xE304, true, true, {} }, // 252
+ { "PAR_EL1", 0xC3A0, true, true, {} }, // 253
+ { "PMCR_EL0", 0xDCE0, true, true, {} }, // 254
+ { "PMCNTENSET_EL0", 0xDCE1, true, true, {} }, // 255
+ { "PMCNTENCLR_EL0", 0xDCE2, true, true, {} }, // 256
+ { "PMOVSCLR_EL0", 0xDCE3, true, true, {} }, // 257
+ { "PMSELR_EL0", 0xDCE5, true, true, {} }, // 258
+ { "PMCCNTR_EL0", 0xDCE8, true, true, {} }, // 259
+ { "PMXEVTYPER_EL0", 0xDCE9, true, true, {} }, // 260
+ { "PMXEVCNTR_EL0", 0xDCEA, true, true, {} }, // 261
+ { "PMUSERENR_EL0", 0xDCF0, true, true, {} }, // 262
+ { "PMINTENSET_EL1", 0xC4F1, true, true, {} }, // 263
+ { "PMINTENCLR_EL1", 0xC4F2, true, true, {} }, // 264
+ { "PMOVSSET_EL0", 0xDCF3, true, true, {} }, // 265
+ { "MAIR_EL1", 0xC510, true, true, {} }, // 266
+ { "MAIR_EL2", 0xE510, true, true, {} }, // 267
+ { "MAIR_EL3", 0xF510, true, true, {} }, // 268
+ { "AMAIR_EL1", 0xC518, true, true, {} }, // 269
+ { "AMAIR_EL2", 0xE518, true, true, {} }, // 270
+ { "AMAIR_EL3", 0xF518, true, true, {} }, // 271
+ { "VBAR_EL1", 0xC600, true, true, {} }, // 272
+ { "VBAR_EL2", 0xE600, true, true, {} }, // 273
+ { "VBAR_EL3", 0xF600, true, true, {} }, // 274
+ { "RMR_EL1", 0xC602, true, true, {} }, // 275
+ { "RMR_EL2", 0xE602, true, true, {} }, // 276
+ { "RMR_EL3", 0xF602, true, true, {} }, // 277
+ { "CONTEXTIDR_EL1", 0xC681, true, true, {} }, // 278
+ { "TPIDR_EL0", 0xDE82, true, true, {} }, // 279
+ { "TPIDR_EL2", 0xE682, true, true, {} }, // 280
+ { "TPIDR_EL3", 0xF682, true, true, {} }, // 281
+ { "TPIDRRO_EL0", 0xDE83, true, true, {} }, // 282
+ { "TPIDR_EL1", 0xC684, true, true, {} }, // 283
+ { "CNTFRQ_EL0", 0xDF00, true, true, {} }, // 284
+ { "CNTVOFF_EL2", 0xE703, true, true, {} }, // 285
+ { "CNTKCTL_EL1", 0xC708, true, true, {} }, // 286
+ { "CNTHCTL_EL2", 0xE708, true, true, {} }, // 287
+ { "CNTP_TVAL_EL0", 0xDF10, true, true, {} }, // 288
+ { "CNTHP_TVAL_EL2", 0xE710, true, true, {} }, // 289
+ { "CNTPS_TVAL_EL1", 0xFF10, true, true, {} }, // 290
+ { "CNTP_CTL_EL0", 0xDF11, true, true, {} }, // 291
+ { "CNTHP_CTL_EL2", 0xE711, true, true, {} }, // 292
+ { "CNTPS_CTL_EL1", 0xFF11, true, true, {} }, // 293
+ { "CNTP_CVAL_EL0", 0xDF12, true, true, {} }, // 294
+ { "CNTHP_CVAL_EL2", 0xE712, true, true, {} }, // 295
+ { "CNTPS_CVAL_EL1", 0xFF12, true, true, {} }, // 296
+ { "CNTV_TVAL_EL0", 0xDF18, true, true, {} }, // 297
+ { "CNTV_CTL_EL0", 0xDF19, true, true, {} }, // 298
+ { "CNTV_CVAL_EL0", 0xDF1A, true, true, {} }, // 299
+ { "PMEVCNTR0_EL0", 0xDF40, true, true, {} }, // 300
+ { "PMEVCNTR1_EL0", 0xDF41, true, true, {} }, // 301
+ { "PMEVCNTR2_EL0", 0xDF42, true, true, {} }, // 302
+ { "PMEVCNTR3_EL0", 0xDF43, true, true, {} }, // 303
+ { "PMEVCNTR4_EL0", 0xDF44, true, true, {} }, // 304
+ { "PMEVCNTR5_EL0", 0xDF45, true, true, {} }, // 305
+ { "PMEVCNTR6_EL0", 0xDF46, true, true, {} }, // 306
+ { "PMEVCNTR7_EL0", 0xDF47, true, true, {} }, // 307
+ { "PMEVCNTR8_EL0", 0xDF48, true, true, {} }, // 308
+ { "PMEVCNTR9_EL0", 0xDF49, true, true, {} }, // 309
+ { "PMEVCNTR10_EL0", 0xDF4A, true, true, {} }, // 310
+ { "PMEVCNTR11_EL0", 0xDF4B, true, true, {} }, // 311
+ { "PMEVCNTR12_EL0", 0xDF4C, true, true, {} }, // 312
+ { "PMEVCNTR13_EL0", 0xDF4D, true, true, {} }, // 313
+ { "PMEVCNTR14_EL0", 0xDF4E, true, true, {} }, // 314
+ { "PMEVCNTR15_EL0", 0xDF4F, true, true, {} }, // 315
+ { "PMEVCNTR16_EL0", 0xDF50, true, true, {} }, // 316
+ { "PMEVCNTR17_EL0", 0xDF51, true, true, {} }, // 317
+ { "PMEVCNTR18_EL0", 0xDF52, true, true, {} }, // 318
+ { "PMEVCNTR19_EL0", 0xDF53, true, true, {} }, // 319
+ { "PMEVCNTR20_EL0", 0xDF54, true, true, {} }, // 320
+ { "PMEVCNTR21_EL0", 0xDF55, true, true, {} }, // 321
+ { "PMEVCNTR22_EL0", 0xDF56, true, true, {} }, // 322
+ { "PMEVCNTR23_EL0", 0xDF57, true, true, {} }, // 323
+ { "PMEVCNTR24_EL0", 0xDF58, true, true, {} }, // 324
+ { "PMEVCNTR25_EL0", 0xDF59, true, true, {} }, // 325
+ { "PMEVCNTR26_EL0", 0xDF5A, true, true, {} }, // 326
+ { "PMEVCNTR27_EL0", 0xDF5B, true, true, {} }, // 327
+ { "PMEVCNTR28_EL0", 0xDF5C, true, true, {} }, // 328
+ { "PMEVCNTR29_EL0", 0xDF5D, true, true, {} }, // 329
+ { "PMEVCNTR30_EL0", 0xDF5E, true, true, {} }, // 330
+ { "PMCCFILTR_EL0", 0xDF7F, true, true, {} }, // 331
+ { "PMEVTYPER0_EL0", 0xDF60, true, true, {} }, // 332
+ { "PMEVTYPER1_EL0", 0xDF61, true, true, {} }, // 333
+ { "PMEVTYPER2_EL0", 0xDF62, true, true, {} }, // 334
+ { "PMEVTYPER3_EL0", 0xDF63, true, true, {} }, // 335
+ { "PMEVTYPER4_EL0", 0xDF64, true, true, {} }, // 336
+ { "PMEVTYPER5_EL0", 0xDF65, true, true, {} }, // 337
+ { "PMEVTYPER6_EL0", 0xDF66, true, true, {} }, // 338
+ { "PMEVTYPER7_EL0", 0xDF67, true, true, {} }, // 339
+ { "PMEVTYPER8_EL0", 0xDF68, true, true, {} }, // 340
+ { "PMEVTYPER9_EL0", 0xDF69, true, true, {} }, // 341
+ { "PMEVTYPER10_EL0", 0xDF6A, true, true, {} }, // 342
+ { "PMEVTYPER11_EL0", 0xDF6B, true, true, {} }, // 343
+ { "PMEVTYPER12_EL0", 0xDF6C, true, true, {} }, // 344
+ { "PMEVTYPER13_EL0", 0xDF6D, true, true, {} }, // 345
+ { "PMEVTYPER14_EL0", 0xDF6E, true, true, {} }, // 346
+ { "PMEVTYPER15_EL0", 0xDF6F, true, true, {} }, // 347
+ { "PMEVTYPER16_EL0", 0xDF70, true, true, {} }, // 348
+ { "PMEVTYPER17_EL0", 0xDF71, true, true, {} }, // 349
+ { "PMEVTYPER18_EL0", 0xDF72, true, true, {} }, // 350
+ { "PMEVTYPER19_EL0", 0xDF73, true, true, {} }, // 351
+ { "PMEVTYPER20_EL0", 0xDF74, true, true, {} }, // 352
+ { "PMEVTYPER21_EL0", 0xDF75, true, true, {} }, // 353
+ { "PMEVTYPER22_EL0", 0xDF76, true, true, {} }, // 354
+ { "PMEVTYPER23_EL0", 0xDF77, true, true, {} }, // 355
+ { "PMEVTYPER24_EL0", 0xDF78, true, true, {} }, // 356
+ { "PMEVTYPER25_EL0", 0xDF79, true, true, {} }, // 357
+ { "PMEVTYPER26_EL0", 0xDF7A, true, true, {} }, // 358
+ { "PMEVTYPER27_EL0", 0xDF7B, true, true, {} }, // 359
+ { "PMEVTYPER28_EL0", 0xDF7C, true, true, {} }, // 360
+ { "PMEVTYPER29_EL0", 0xDF7D, true, true, {} }, // 361
+ { "PMEVTYPER30_EL0", 0xDF7E, true, true, {} }, // 362
+ { "TRCPRGCTLR", 0x8808, true, true, {} }, // 363
+ { "TRCPROCSELR", 0x8810, true, true, {} }, // 364
+ { "TRCCONFIGR", 0x8820, true, true, {} }, // 365
+ { "TRCAUXCTLR", 0x8830, true, true, {} }, // 366
+ { "TRCEVENTCTL0R", 0x8840, true, true, {} }, // 367
+ { "TRCEVENTCTL1R", 0x8848, true, true, {} }, // 368
+ { "TRCSTALLCTLR", 0x8858, true, true, {} }, // 369
+ { "TRCTSCTLR", 0x8860, true, true, {} }, // 370
+ { "TRCSYNCPR", 0x8868, true, true, {} }, // 371
+ { "TRCCCCTLR", 0x8870, true, true, {} }, // 372
+ { "TRCBBCTLR", 0x8878, true, true, {} }, // 373
+ { "TRCTRACEIDR", 0x8801, true, true, {} }, // 374
+ { "TRCQCTLR", 0x8809, true, true, {} }, // 375
+ { "TRCVICTLR", 0x8802, true, true, {} }, // 376
+ { "TRCVIIECTLR", 0x880A, true, true, {} }, // 377
+ { "TRCVISSCTLR", 0x8812, true, true, {} }, // 378
+ { "TRCVIPCSSCTLR", 0x881A, true, true, {} }, // 379
+ { "TRCVDCTLR", 0x8842, true, true, {} }, // 380
+ { "TRCVDSACCTLR", 0x884A, true, true, {} }, // 381
+ { "TRCVDARCCTLR", 0x8852, true, true, {} }, // 382
+ { "TRCSEQEVR0", 0x8804, true, true, {} }, // 383
+ { "TRCSEQEVR1", 0x880C, true, true, {} }, // 384
+ { "TRCSEQEVR2", 0x8814, true, true, {} }, // 385
+ { "TRCSEQRSTEVR", 0x8834, true, true, {} }, // 386
+ { "TRCSEQSTR", 0x883C, true, true, {} }, // 387
+ { "TRCEXTINSELR", 0x8844, true, true, {} }, // 388
+ { "TRCCNTRLDVR0", 0x8805, true, true, {} }, // 389
+ { "TRCCNTRLDVR1", 0x880D, true, true, {} }, // 390
+ { "TRCCNTRLDVR2", 0x8815, true, true, {} }, // 391
+ { "TRCCNTRLDVR3", 0x881D, true, true, {} }, // 392
+ { "TRCCNTCTLR0", 0x8825, true, true, {} }, // 393
+ { "TRCCNTCTLR1", 0x882D, true, true, {} }, // 394
+ { "TRCCNTCTLR2", 0x8835, true, true, {} }, // 395
+ { "TRCCNTCTLR3", 0x883D, true, true, {} }, // 396
+ { "TRCCNTVR0", 0x8845, true, true, {} }, // 397
+ { "TRCCNTVR1", 0x884D, true, true, {} }, // 398
+ { "TRCCNTVR2", 0x8855, true, true, {} }, // 399
+ { "TRCCNTVR3", 0x885D, true, true, {} }, // 400
+ { "TRCIMSPEC0", 0x8807, true, true, {} }, // 401
+ { "TRCIMSPEC1", 0x880F, true, true, {} }, // 402
+ { "TRCIMSPEC2", 0x8817, true, true, {} }, // 403
+ { "TRCIMSPEC3", 0x881F, true, true, {} }, // 404
+ { "TRCIMSPEC4", 0x8827, true, true, {} }, // 405
+ { "TRCIMSPEC5", 0x882F, true, true, {} }, // 406
+ { "TRCIMSPEC6", 0x8837, true, true, {} }, // 407
+ { "TRCIMSPEC7", 0x883F, true, true, {} }, // 408
+ { "TRCRSCTLR2", 0x8890, true, true, {} }, // 409
+ { "TRCRSCTLR3", 0x8898, true, true, {} }, // 410
+ { "TRCRSCTLR4", 0x88A0, true, true, {} }, // 411
+ { "TRCRSCTLR5", 0x88A8, true, true, {} }, // 412
+ { "TRCRSCTLR6", 0x88B0, true, true, {} }, // 413
+ { "TRCRSCTLR7", 0x88B8, true, true, {} }, // 414
+ { "TRCRSCTLR8", 0x88C0, true, true, {} }, // 415
+ { "TRCRSCTLR9", 0x88C8, true, true, {} }, // 416
+ { "TRCRSCTLR10", 0x88D0, true, true, {} }, // 417
+ { "TRCRSCTLR11", 0x88D8, true, true, {} }, // 418
+ { "TRCRSCTLR12", 0x88E0, true, true, {} }, // 419
+ { "TRCRSCTLR13", 0x88E8, true, true, {} }, // 420
+ { "TRCRSCTLR14", 0x88F0, true, true, {} }, // 421
+ { "TRCRSCTLR15", 0x88F8, true, true, {} }, // 422
+ { "TRCRSCTLR16", 0x8881, true, true, {} }, // 423
+ { "TRCRSCTLR17", 0x8889, true, true, {} }, // 424
+ { "TRCRSCTLR18", 0x8891, true, true, {} }, // 425
+ { "TRCRSCTLR19", 0x8899, true, true, {} }, // 426
+ { "TRCRSCTLR20", 0x88A1, true, true, {} }, // 427
+ { "TRCRSCTLR21", 0x88A9, true, true, {} }, // 428
+ { "TRCRSCTLR22", 0x88B1, true, true, {} }, // 429
+ { "TRCRSCTLR23", 0x88B9, true, true, {} }, // 430
+ { "TRCRSCTLR24", 0x88C1, true, true, {} }, // 431
+ { "TRCRSCTLR25", 0x88C9, true, true, {} }, // 432
+ { "TRCRSCTLR26", 0x88D1, true, true, {} }, // 433
+ { "TRCRSCTLR27", 0x88D9, true, true, {} }, // 434
+ { "TRCRSCTLR28", 0x88E1, true, true, {} }, // 435
+ { "TRCRSCTLR29", 0x88E9, true, true, {} }, // 436
+ { "TRCRSCTLR30", 0x88F1, true, true, {} }, // 437
+ { "TRCRSCTLR31", 0x88F9, true, true, {} }, // 438
+ { "TRCSSCCR0", 0x8882, true, true, {} }, // 439
+ { "TRCSSCCR1", 0x888A, true, true, {} }, // 440
+ { "TRCSSCCR2", 0x8892, true, true, {} }, // 441
+ { "TRCSSCCR3", 0x889A, true, true, {} }, // 442
+ { "TRCSSCCR4", 0x88A2, true, true, {} }, // 443
+ { "TRCSSCCR5", 0x88AA, true, true, {} }, // 444
+ { "TRCSSCCR6", 0x88B2, true, true, {} }, // 445
+ { "TRCSSCCR7", 0x88BA, true, true, {} }, // 446
+ { "TRCSSCSR0", 0x88C2, true, true, {} }, // 447
+ { "TRCSSCSR1", 0x88CA, true, true, {} }, // 448
+ { "TRCSSCSR2", 0x88D2, true, true, {} }, // 449
+ { "TRCSSCSR3", 0x88DA, true, true, {} }, // 450
+ { "TRCSSCSR4", 0x88E2, true, true, {} }, // 451
+ { "TRCSSCSR5", 0x88EA, true, true, {} }, // 452
+ { "TRCSSCSR6", 0x88F2, true, true, {} }, // 453
+ { "TRCSSCSR7", 0x88FA, true, true, {} }, // 454
+ { "TRCSSPCICR0", 0x8883, true, true, {} }, // 455
+ { "TRCSSPCICR1", 0x888B, true, true, {} }, // 456
+ { "TRCSSPCICR2", 0x8893, true, true, {} }, // 457
+ { "TRCSSPCICR3", 0x889B, true, true, {} }, // 458
+ { "TRCSSPCICR4", 0x88A3, true, true, {} }, // 459
+ { "TRCSSPCICR5", 0x88AB, true, true, {} }, // 460
+ { "TRCSSPCICR6", 0x88B3, true, true, {} }, // 461
+ { "TRCSSPCICR7", 0x88BB, true, true, {} }, // 462
+ { "TRCPDCR", 0x88A4, true, true, {} }, // 463
+ { "TRCACVR0", 0x8900, true, true, {} }, // 464
+ { "TRCACVR1", 0x8910, true, true, {} }, // 465
+ { "TRCACVR2", 0x8920, true, true, {} }, // 466
+ { "TRCACVR3", 0x8930, true, true, {} }, // 467
+ { "TRCACVR4", 0x8940, true, true, {} }, // 468
+ { "TRCACVR5", 0x8950, true, true, {} }, // 469
+ { "TRCACVR6", 0x8960, true, true, {} }, // 470
+ { "TRCACVR7", 0x8970, true, true, {} }, // 471
+ { "TRCACVR8", 0x8901, true, true, {} }, // 472
+ { "TRCACVR9", 0x8911, true, true, {} }, // 473
+ { "TRCACVR10", 0x8921, true, true, {} }, // 474
+ { "TRCACVR11", 0x8931, true, true, {} }, // 475
+ { "TRCACVR12", 0x8941, true, true, {} }, // 476
+ { "TRCACVR13", 0x8951, true, true, {} }, // 477
+ { "TRCACVR14", 0x8961, true, true, {} }, // 478
+ { "TRCACVR15", 0x8971, true, true, {} }, // 479
+ { "TRCACATR0", 0x8902, true, true, {} }, // 480
+ { "TRCACATR1", 0x8912, true, true, {} }, // 481
+ { "TRCACATR2", 0x8922, true, true, {} }, // 482
+ { "TRCACATR3", 0x8932, true, true, {} }, // 483
+ { "TRCACATR4", 0x8942, true, true, {} }, // 484
+ { "TRCACATR5", 0x8952, true, true, {} }, // 485
+ { "TRCACATR6", 0x8962, true, true, {} }, // 486
+ { "TRCACATR7", 0x8972, true, true, {} }, // 487
+ { "TRCACATR8", 0x8903, true, true, {} }, // 488
+ { "TRCACATR9", 0x8913, true, true, {} }, // 489
+ { "TRCACATR10", 0x8923, true, true, {} }, // 490
+ { "TRCACATR11", 0x8933, true, true, {} }, // 491
+ { "TRCACATR12", 0x8943, true, true, {} }, // 492
+ { "TRCACATR13", 0x8953, true, true, {} }, // 493
+ { "TRCACATR14", 0x8963, true, true, {} }, // 494
+ { "TRCACATR15", 0x8973, true, true, {} }, // 495
+ { "TRCDVCVR0", 0x8904, true, true, {} }, // 496
+ { "TRCDVCVR1", 0x8924, true, true, {} }, // 497
+ { "TRCDVCVR2", 0x8944, true, true, {} }, // 498
+ { "TRCDVCVR3", 0x8964, true, true, {} }, // 499
+ { "TRCDVCVR4", 0x8905, true, true, {} }, // 500
+ { "TRCDVCVR5", 0x8925, true, true, {} }, // 501
+ { "TRCDVCVR6", 0x8945, true, true, {} }, // 502
+ { "TRCDVCVR7", 0x8965, true, true, {} }, // 503
+ { "TRCDVCMR0", 0x8906, true, true, {} }, // 504
+ { "TRCDVCMR1", 0x8926, true, true, {} }, // 505
+ { "TRCDVCMR2", 0x8946, true, true, {} }, // 506
+ { "TRCDVCMR3", 0x8966, true, true, {} }, // 507
+ { "TRCDVCMR4", 0x8907, true, true, {} }, // 508
+ { "TRCDVCMR5", 0x8927, true, true, {} }, // 509
+ { "TRCDVCMR6", 0x8947, true, true, {} }, // 510
+ { "TRCDVCMR7", 0x8967, true, true, {} }, // 511
+ { "TRCCIDCVR0", 0x8980, true, true, {} }, // 512
+ { "TRCCIDCVR1", 0x8990, true, true, {} }, // 513
+ { "TRCCIDCVR2", 0x89A0, true, true, {} }, // 514
+ { "TRCCIDCVR3", 0x89B0, true, true, {} }, // 515
+ { "TRCCIDCVR4", 0x89C0, true, true, {} }, // 516
+ { "TRCCIDCVR5", 0x89D0, true, true, {} }, // 517
+ { "TRCCIDCVR6", 0x89E0, true, true, {} }, // 518
+ { "TRCCIDCVR7", 0x89F0, true, true, {} }, // 519
+ { "TRCVMIDCVR0", 0x8981, true, true, {} }, // 520
+ { "TRCVMIDCVR1", 0x8991, true, true, {} }, // 521
+ { "TRCVMIDCVR2", 0x89A1, true, true, {} }, // 522
+ { "TRCVMIDCVR3", 0x89B1, true, true, {} }, // 523
+ { "TRCVMIDCVR4", 0x89C1, true, true, {} }, // 524
+ { "TRCVMIDCVR5", 0x89D1, true, true, {} }, // 525
+ { "TRCVMIDCVR6", 0x89E1, true, true, {} }, // 526
+ { "TRCVMIDCVR7", 0x89F1, true, true, {} }, // 527
+ { "TRCCIDCCTLR0", 0x8982, true, true, {} }, // 528
+ { "TRCCIDCCTLR1", 0x898A, true, true, {} }, // 529
+ { "TRCVMIDCCTLR0", 0x8992, true, true, {} }, // 530
+ { "TRCVMIDCCTLR1", 0x899A, true, true, {} }, // 531
+ { "TRCITCTRL", 0x8B84, true, true, {} }, // 532
+ { "TRCCLAIMSET", 0x8BC6, true, true, {} }, // 533
+ { "TRCCLAIMCLR", 0x8BCE, true, true, {} }, // 534
+ { "ICC_BPR1_EL1", 0xC663, true, true, {} }, // 535
+ { "ICC_BPR0_EL1", 0xC643, true, true, {} }, // 536
+ { "ICC_PMR_EL1", 0xC230, true, true, {} }, // 537
+ { "ICC_CTLR_EL1", 0xC664, true, true, {} }, // 538
+ { "ICC_CTLR_EL3", 0xF664, true, true, {} }, // 539
+ { "ICC_SRE_EL1", 0xC665, true, true, {} }, // 540
+ { "ICC_SRE_EL2", 0xE64D, true, true, {} }, // 541
+ { "ICC_SRE_EL3", 0xF665, true, true, {} }, // 542
+ { "ICC_IGRPEN0_EL1", 0xC666, true, true, {} }, // 543
+ { "ICC_IGRPEN1_EL1", 0xC667, true, true, {} }, // 544
+ { "ICC_IGRPEN1_EL3", 0xF667, true, true, {} }, // 545
+ { "ICC_SEIEN_EL1", 0xC668, true, true, {} }, // 546
+ { "ICC_AP0R0_EL1", 0xC644, true, true, {} }, // 547
+ { "ICC_AP0R1_EL1", 0xC645, true, true, {} }, // 548
+ { "ICC_AP0R2_EL1", 0xC646, true, true, {} }, // 549
+ { "ICC_AP0R3_EL1", 0xC647, true, true, {} }, // 550
+ { "ICC_AP1R0_EL1", 0xC648, true, true, {} }, // 551
+ { "ICC_AP1R1_EL1", 0xC649, true, true, {} }, // 552
+ { "ICC_AP1R2_EL1", 0xC64A, true, true, {} }, // 553
+ { "ICC_AP1R3_EL1", 0xC64B, true, true, {} }, // 554
+ { "ICH_AP0R0_EL2", 0xE640, true, true, {} }, // 555
+ { "ICH_AP0R1_EL2", 0xE641, true, true, {} }, // 556
+ { "ICH_AP0R2_EL2", 0xE642, true, true, {} }, // 557
+ { "ICH_AP0R3_EL2", 0xE643, true, true, {} }, // 558
+ { "ICH_AP1R0_EL2", 0xE648, true, true, {} }, // 559
+ { "ICH_AP1R1_EL2", 0xE649, true, true, {} }, // 560
+ { "ICH_AP1R2_EL2", 0xE64A, true, true, {} }, // 561
+ { "ICH_AP1R3_EL2", 0xE64B, true, true, {} }, // 562
+ { "ICH_HCR_EL2", 0xE658, true, true, {} }, // 563
+ { "ICH_MISR_EL2", 0xE65A, true, true, {} }, // 564
+ { "ICH_VMCR_EL2", 0xE65F, true, true, {} }, // 565
+ { "ICH_VSEIR_EL2", 0xE64C, true, true, {} }, // 566
+ { "ICH_LR0_EL2", 0xE660, true, true, {} }, // 567
+ { "ICH_LR1_EL2", 0xE661, true, true, {} }, // 568
+ { "ICH_LR2_EL2", 0xE662, true, true, {} }, // 569
+ { "ICH_LR3_EL2", 0xE663, true, true, {} }, // 570
+ { "ICH_LR4_EL2", 0xE664, true, true, {} }, // 571
+ { "ICH_LR5_EL2", 0xE665, true, true, {} }, // 572
+ { "ICH_LR6_EL2", 0xE666, true, true, {} }, // 573
+ { "ICH_LR7_EL2", 0xE667, true, true, {} }, // 574
+ { "ICH_LR8_EL2", 0xE668, true, true, {} }, // 575
+ { "ICH_LR9_EL2", 0xE669, true, true, {} }, // 576
+ { "ICH_LR10_EL2", 0xE66A, true, true, {} }, // 577
+ { "ICH_LR11_EL2", 0xE66B, true, true, {} }, // 578
+ { "ICH_LR12_EL2", 0xE66C, true, true, {} }, // 579
+ { "ICH_LR13_EL2", 0xE66D, true, true, {} }, // 580
+ { "ICH_LR14_EL2", 0xE66E, true, true, {} }, // 581
+ { "ICH_LR15_EL2", 0xE66F, true, true, {} }, // 582
+ { "PAN", 0xC213, true, true, {AArch64::HasV8_1aOps} }, // 583
+ { "LORSA_EL1", 0xC520, true, true, {AArch64::HasV8_1aOps} }, // 584
+ { "LOREA_EL1", 0xC521, true, true, {AArch64::HasV8_1aOps} }, // 585
+ { "LORN_EL1", 0xC522, true, true, {AArch64::HasV8_1aOps} }, // 586
+ { "LORC_EL1", 0xC523, true, true, {AArch64::HasV8_1aOps} }, // 587
+ { "TTBR1_EL2", 0xE101, true, true, {AArch64::HasV8_1aOps} }, // 588
+ { "CONTEXTIDR_EL2", 0xE681, true, true, {AArch64::HasV8_1aOps} }, // 589
+ { "CNTHV_TVAL_EL2", 0xE718, true, true, {AArch64::HasV8_1aOps} }, // 590
+ { "CNTHV_CVAL_EL2", 0xE71A, true, true, {AArch64::HasV8_1aOps} }, // 591
+ { "CNTHV_CTL_EL2", 0xE719, true, true, {AArch64::HasV8_1aOps} }, // 592
+ { "SCTLR_EL12", 0xE880, true, true, {AArch64::HasV8_1aOps} }, // 593
+ { "CPACR_EL12", 0xE882, true, true, {AArch64::HasV8_1aOps} }, // 594
+ { "TTBR0_EL12", 0xE900, true, true, {AArch64::HasV8_1aOps} }, // 595
+ { "TTBR1_EL12", 0xE901, true, true, {AArch64::HasV8_1aOps} }, // 596
+ { "TCR_EL12", 0xE902, true, true, {AArch64::HasV8_1aOps} }, // 597
+ { "AFSR0_EL12", 0xEA88, true, true, {AArch64::HasV8_1aOps} }, // 598
+ { "AFSR1_EL12", 0xEA89, true, true, {AArch64::HasV8_1aOps} }, // 599
+ { "ESR_EL12", 0xEA90, true, true, {AArch64::HasV8_1aOps} }, // 600
+ { "FAR_EL12", 0xEB00, true, true, {AArch64::HasV8_1aOps} }, // 601
+ { "MAIR_EL12", 0xED10, true, true, {AArch64::HasV8_1aOps} }, // 602
+ { "AMAIR_EL12", 0xED18, true, true, {AArch64::HasV8_1aOps} }, // 603
+ { "VBAR_EL12", 0xEE00, true, true, {AArch64::HasV8_1aOps} }, // 604
+ { "CONTEXTIDR_EL12", 0xEE81, true, true, {AArch64::HasV8_1aOps} }, // 605
+ { "CNTKCTL_EL12", 0xEF08, true, true, {AArch64::HasV8_1aOps} }, // 606
+ { "CNTP_TVAL_EL02", 0xEF10, true, true, {AArch64::HasV8_1aOps} }, // 607
+ { "CNTP_CTL_EL02", 0xEF11, true, true, {AArch64::HasV8_1aOps} }, // 608
+ { "CNTP_CVAL_EL02", 0xEF12, true, true, {AArch64::HasV8_1aOps} }, // 609
+ { "CNTV_TVAL_EL02", 0xEF18, true, true, {AArch64::HasV8_1aOps} }, // 610
+ { "CNTV_CTL_EL02", 0xEF19, true, true, {AArch64::HasV8_1aOps} }, // 611
+ { "CNTV_CVAL_EL02", 0xEF1A, true, true, {AArch64::HasV8_1aOps} }, // 612
+ { "SPSR_EL12", 0xEA00, true, true, {AArch64::HasV8_1aOps} }, // 613
+ { "ELR_EL12", 0xEA01, true, true, {AArch64::HasV8_1aOps} }, // 614
+ { "UAO", 0xC214, true, true, {AArch64::HasV8_2aOps} }, // 615
+ { "PMBLIMITR_EL1", 0xC4D0, true, true, {AArch64::FeatureSPE} }, // 616
+ { "PMBPTR_EL1", 0xC4D1, true, true, {AArch64::FeatureSPE} }, // 617
+ { "PMBSR_EL1", 0xC4D3, true, true, {AArch64::FeatureSPE} }, // 618
+ { "PMBIDR_EL1", 0xC4D7, true, true, {AArch64::FeatureSPE} }, // 619
+ { "PMSCR_EL2", 0xE4C8, true, true, {AArch64::FeatureSPE} }, // 620
+ { "PMSCR_EL12", 0xECC8, true, true, {AArch64::FeatureSPE} }, // 621
+ { "PMSCR_EL1", 0xC4C8, true, true, {AArch64::FeatureSPE} }, // 622
+ { "PMSICR_EL1", 0xC4CA, true, true, {AArch64::FeatureSPE} }, // 623
+ { "PMSIRR_EL1", 0xC4CB, true, true, {AArch64::FeatureSPE} }, // 624
+ { "PMSFCR_EL1", 0xC4CC, true, true, {AArch64::FeatureSPE} }, // 625
+ { "PMSEVFR_EL1", 0xC4CD, true, true, {AArch64::FeatureSPE} }, // 626
+ { "PMSLATFR_EL1", 0xC4CE, true, true, {AArch64::FeatureSPE} }, // 627
+ { "PMSIDR_EL1", 0xC4CF, true, true, {AArch64::FeatureSPE} }, // 628
+ { "ERRSELR_EL1", 0xC299, true, true, {AArch64::FeatureRAS} }, // 629
+ { "ERXCTLR_EL1", 0xC2A1, true, true, {AArch64::FeatureRAS} }, // 630
+ { "ERXSTATUS_EL1", 0xC2A2, true, true, {AArch64::FeatureRAS} }, // 631
+ { "ERXADDR_EL1", 0xC2A3, true, true, {AArch64::FeatureRAS} }, // 632
+ { "ERXMISC0_EL1", 0xC2A8, true, true, {AArch64::FeatureRAS} }, // 633
+ { "ERXMISC1_EL1", 0xC2A9, true, true, {AArch64::FeatureRAS} }, // 634
+ { "DISR_EL1", 0xC609, true, true, {AArch64::FeatureRAS} }, // 635
+ { "VDISR_EL2", 0xE609, true, true, {AArch64::FeatureRAS} }, // 636
+ { "VSESR_EL2", 0xE293, true, true, {AArch64::FeatureRAS} }, // 637
+ { "APIAKeyLo_EL1", 0xC108, true, true, {AArch64::HasV8_3aOps} }, // 638
+ { "APIAKeyHi_EL1", 0xC109, true, true, {AArch64::HasV8_3aOps} }, // 639
+ { "APIBKeyLo_EL1", 0xC10A, true, true, {AArch64::HasV8_3aOps} }, // 640
+ { "APIBKeyHi_EL1", 0xC10B, true, true, {AArch64::HasV8_3aOps} }, // 641
+ { "APDAKeyLo_EL1", 0xC110, true, true, {AArch64::HasV8_3aOps} }, // 642
+ { "APDAKeyHi_EL1", 0xC111, true, true, {AArch64::HasV8_3aOps} }, // 643
+ { "APDBKeyLo_EL1", 0xC112, true, true, {AArch64::HasV8_3aOps} }, // 644
+ { "APDBKeyHi_EL1", 0xC113, true, true, {AArch64::HasV8_3aOps} }, // 645
+ { "APGAKeyLo_EL1", 0xC118, true, true, {AArch64::HasV8_3aOps} }, // 646
+ { "APGAKeyHi_EL1", 0xC119, true, true, {AArch64::HasV8_3aOps} }, // 647
+ { "VSTCR_EL2", 0xE132, true, true, {AArch64::HasV8_4aOps} }, // 648
+ { "VSTTBR_EL2", 0xE130, true, true, {AArch64::HasV8_4aOps} }, // 649
+ { "CNTHVS_TVAL_EL2", 0xE720, true, true, {AArch64::HasV8_4aOps} }, // 650
+ { "CNTHVS_CVAL_EL2", 0xE722, true, true, {AArch64::HasV8_4aOps} }, // 651
+ { "CNTHVS_CTL_EL2", 0xE721, true, true, {AArch64::HasV8_4aOps} }, // 652
+ { "CNTHPS_TVAL_EL2", 0xE728, true, true, {AArch64::HasV8_4aOps} }, // 653
+ { "CNTHPS_CVAL_EL2", 0xE72A, true, true, {AArch64::HasV8_4aOps} }, // 654
+ { "CNTHPS_CTL_EL2", 0xE729, true, true, {AArch64::HasV8_4aOps} }, // 655
+ { "SDER32_EL2", 0xE099, true, true, {AArch64::HasV8_4aOps} }, // 656
+ { "ERXPFGCTL_EL1", 0xC2A5, true, true, {AArch64::HasV8_4aOps} }, // 657
+ { "ERXPFGCDN_EL1", 0xC2A6, true, true, {AArch64::HasV8_4aOps} }, // 658
+ { "ERXTS_EL1", 0xC2AF, true, true, {AArch64::HasV8_4aOps} }, // 659
+ { "ERXMISC2_EL1", 0xC2AA, true, true, {AArch64::HasV8_4aOps} }, // 660
+ { "ERXMISC3_EL1", 0xC2AB, true, true, {AArch64::HasV8_4aOps} }, // 661
+ { "ERXPFGF_EL1", 0xC2A4, true, false, {AArch64::HasV8_4aOps} }, // 662
+ { "MPAM0_EL1", 0xC529, true, true, {AArch64::HasV8_4aOps} }, // 663
+ { "MPAM1_EL1", 0xC528, true, true, {AArch64::HasV8_4aOps} }, // 664
+ { "MPAM2_EL2", 0xE528, true, true, {AArch64::HasV8_4aOps} }, // 665
+ { "MPAM3_EL3", 0xF528, true, true, {AArch64::HasV8_4aOps} }, // 666
+ { "MPAM1_EL12", 0xED28, true, true, {AArch64::HasV8_4aOps} }, // 667
+ { "MPAMHCR_EL2", 0xE520, true, true, {AArch64::HasV8_4aOps} }, // 668
+ { "MPAMVPMV_EL2", 0xE521, true, true, {AArch64::HasV8_4aOps} }, // 669
+ { "MPAMVPM0_EL2", 0xE530, true, true, {AArch64::HasV8_4aOps} }, // 670
+ { "MPAMVPM1_EL2", 0xE531, true, true, {AArch64::HasV8_4aOps} }, // 671
+ { "MPAMVPM2_EL2", 0xE532, true, true, {AArch64::HasV8_4aOps} }, // 672
+ { "MPAMVPM3_EL2", 0xE533, true, true, {AArch64::HasV8_4aOps} }, // 673
+ { "MPAMVPM4_EL2", 0xE534, true, true, {AArch64::HasV8_4aOps} }, // 674
+ { "MPAMVPM5_EL2", 0xE535, true, true, {AArch64::HasV8_4aOps} }, // 675
+ { "MPAMVPM6_EL2", 0xE536, true, true, {AArch64::HasV8_4aOps} }, // 676
+ { "MPAMVPM7_EL2", 0xE537, true, true, {AArch64::HasV8_4aOps} }, // 677
+ { "MPAMIDR_EL1", 0xC524, true, false, {AArch64::HasV8_4aOps} }, // 678
+ { "AMCR_EL0", 0xDE90, true, true, {AArch64::HasV8_4aOps} }, // 679
+ { "AMCFGR_EL0", 0xDE91, true, false, {AArch64::HasV8_4aOps} }, // 680
+ { "AMCGCR_EL0", 0xDE92, true, false, {AArch64::HasV8_4aOps} }, // 681
+ { "AMUSERENR_EL0", 0xDE93, true, true, {AArch64::HasV8_4aOps} }, // 682
+ { "AMCNTENCLR0_EL0", 0xDE94, true, true, {AArch64::HasV8_4aOps} }, // 683
+ { "AMCNTENSET0_EL0", 0xDE95, true, true, {AArch64::HasV8_4aOps} }, // 684
+ { "AMEVCNTR00_EL0", 0xDEA0, true, true, {AArch64::HasV8_4aOps} }, // 685
+ { "AMEVCNTR01_EL0", 0xDEA1, true, true, {AArch64::HasV8_4aOps} }, // 686
+ { "AMEVCNTR02_EL0", 0xDEA2, true, true, {AArch64::HasV8_4aOps} }, // 687
+ { "AMEVCNTR03_EL0", 0xDEA3, true, true, {AArch64::HasV8_4aOps} }, // 688
+ { "AMEVTYPER00_EL0", 0xDEB0, true, false, {AArch64::HasV8_4aOps} }, // 689
+ { "AMEVTYPER01_EL0", 0xDEB1, true, false, {AArch64::HasV8_4aOps} }, // 690
+ { "AMEVTYPER02_EL0", 0xDEB2, true, false, {AArch64::HasV8_4aOps} }, // 691
+ { "AMEVTYPER03_EL0", 0xDEB3, true, false, {AArch64::HasV8_4aOps} }, // 692
+ { "AMCNTENCLR1_EL0", 0xDE98, true, true, {AArch64::HasV8_4aOps} }, // 693
+ { "AMCNTENSET1_EL0", 0xDE99, true, true, {AArch64::HasV8_4aOps} }, // 694
+ { "AMEVCNTR10_EL0", 0xDEE0, true, true, {AArch64::HasV8_4aOps} }, // 695
+ { "AMEVCNTR11_EL0", 0xDEE1, true, true, {AArch64::HasV8_4aOps} }, // 696
+ { "AMEVCNTR12_EL0", 0xDEE2, true, true, {AArch64::HasV8_4aOps} }, // 697
+ { "AMEVCNTR13_EL0", 0xDEE3, true, true, {AArch64::HasV8_4aOps} }, // 698
+ { "AMEVCNTR14_EL0", 0xDEE4, true, true, {AArch64::HasV8_4aOps} }, // 699
+ { "AMEVCNTR15_EL0", 0xDEE5, true, true, {AArch64::HasV8_4aOps} }, // 700
+ { "AMEVCNTR16_EL0", 0xDEE6, true, true, {AArch64::HasV8_4aOps} }, // 701
+ { "AMEVCNTR17_EL0", 0xDEE7, true, true, {AArch64::HasV8_4aOps} }, // 702
+ { "AMEVCNTR18_EL0", 0xDEE8, true, true, {AArch64::HasV8_4aOps} }, // 703
+ { "AMEVCNTR19_EL0", 0xDEE9, true, true, {AArch64::HasV8_4aOps} }, // 704
+ { "AMEVCNTR110_EL0", 0xDEEA, true, true, {AArch64::HasV8_4aOps} }, // 705
+ { "AMEVCNTR111_EL0", 0xDEEB, true, true, {AArch64::HasV8_4aOps} }, // 706
+ { "AMEVCNTR112_EL0", 0xDEEC, true, true, {AArch64::HasV8_4aOps} }, // 707
+ { "AMEVCNTR113_EL0", 0xDEED, true, true, {AArch64::HasV8_4aOps} }, // 708
+ { "AMEVCNTR114_EL0", 0xDEEE, true, true, {AArch64::HasV8_4aOps} }, // 709
+ { "AMEVCNTR115_EL0", 0xDEEF, true, true, {AArch64::HasV8_4aOps} }, // 710
+ { "AMEVTYPER10_EL0", 0xDEF0, true, true, {AArch64::HasV8_4aOps} }, // 711
+ { "AMEVTYPER11_EL0", 0xDEF1, true, true, {AArch64::HasV8_4aOps} }, // 712
+ { "AMEVTYPER12_EL0", 0xDEF2, true, true, {AArch64::HasV8_4aOps} }, // 713
+ { "AMEVTYPER13_EL0", 0xDEF3, true, true, {AArch64::HasV8_4aOps} }, // 714
+ { "AMEVTYPER14_EL0", 0xDEF4, true, true, {AArch64::HasV8_4aOps} }, // 715
+ { "AMEVTYPER15_EL0", 0xDEF5, true, true, {AArch64::HasV8_4aOps} }, // 716
+ { "AMEVTYPER16_EL0", 0xDEF6, true, true, {AArch64::HasV8_4aOps} }, // 717
+ { "AMEVTYPER17_EL0", 0xDEF7, true, true, {AArch64::HasV8_4aOps} }, // 718
+ { "AMEVTYPER18_EL0", 0xDEF8, true, true, {AArch64::HasV8_4aOps} }, // 719
+ { "AMEVTYPER19_EL0", 0xDEF9, true, true, {AArch64::HasV8_4aOps} }, // 720
+ { "AMEVTYPER110_EL0", 0xDEFA, true, true, {AArch64::HasV8_4aOps} }, // 721
+ { "AMEVTYPER111_EL0", 0xDEFB, true, true, {AArch64::HasV8_4aOps} }, // 722
+ { "AMEVTYPER112_EL0", 0xDEFC, true, true, {AArch64::HasV8_4aOps} }, // 723
+ { "AMEVTYPER113_EL0", 0xDEFD, true, true, {AArch64::HasV8_4aOps} }, // 724
+ { "AMEVTYPER114_EL0", 0xDEFE, true, true, {AArch64::HasV8_4aOps} }, // 725
+ { "AMEVTYPER115_EL0", 0xDEFF, true, true, {AArch64::HasV8_4aOps} }, // 726
+ { "TRFCR_EL1", 0xC091, true, true, {AArch64::HasV8_4aOps} }, // 727
+ { "TRFCR_EL2", 0xE091, true, true, {AArch64::HasV8_4aOps} }, // 728
+ { "TRFCR_EL12", 0xE891, true, true, {AArch64::HasV8_4aOps} }, // 729
+ { "DIT", 0xDA15, true, true, {AArch64::HasV8_4aOps} }, // 730
+ { "VNCR_EL2", 0xE110, true, true, {AArch64::HasV8_4aOps} }, // 731
+ { "ZCR_EL1", 0xC090, true, true, {AArch64::FeatureSVE} }, // 732
+ { "ZCR_EL2", 0xE090, true, true, {AArch64::FeatureSVE} }, // 733
+ { "ZCR_EL3", 0xF090, true, true, {AArch64::FeatureSVE} }, // 734
+ { "ZCR_EL12", 0xE890, true, true, {AArch64::FeatureSVE} }, // 735
+ { "CPM_IOACC_CTL_EL3", 0xFF90, true, true, {AArch64::ProcCyclone} }, // 736
};
const SysReg *lookupSysRegByName(StringRef Name) {
@@ -2714,301 +2724,301 @@
unsigned _index;
};
static const struct IndexType Index[] = {
- { "ACTLR_EL1", 194 },
- { "ACTLR_EL2", 195 },
- { "ACTLR_EL3", 196 },
- { "AFSR0_EL1", 238 },
- { "AFSR0_EL12", 597 },
- { "AFSR0_EL2", 239 },
- { "AFSR0_EL3", 240 },
- { "AFSR1_EL1", 241 },
- { "AFSR1_EL12", 598 },
- { "AFSR1_EL2", 242 },
- { "AFSR1_EL3", 243 },
+ { "ACTLR_EL1", 195 },
+ { "ACTLR_EL2", 196 },
+ { "ACTLR_EL3", 197 },
+ { "AFSR0_EL1", 239 },
+ { "AFSR0_EL12", 598 },
+ { "AFSR0_EL2", 240 },
+ { "AFSR0_EL3", 241 },
+ { "AFSR1_EL1", 242 },
+ { "AFSR1_EL12", 599 },
+ { "AFSR1_EL2", 243 },
+ { "AFSR1_EL3", 244 },
{ "AIDR_EL1", 14 },
- { "AMAIR_EL1", 268 },
- { "AMAIR_EL12", 602 },
- { "AMAIR_EL2", 269 },
- { "AMAIR_EL3", 270 },
- { "AMCFGR_EL0", 679 },
- { "AMCGCR_EL0", 680 },
- { "AMCNTENCLR0_EL0", 682 },
- { "AMCNTENCLR1_EL0", 692 },
- { "AMCNTENSET0_EL0", 683 },
- { "AMCNTENSET1_EL0", 693 },
- { "AMCR_EL0", 678 },
- { "AMEVCNTR00_EL0", 684 },
- { "AMEVCNTR01_EL0", 685 },
- { "AMEVCNTR02_EL0", 686 },
- { "AMEVCNTR03_EL0", 687 },
- { "AMEVCNTR10_EL0", 694 },
- { "AMEVCNTR110_EL0", 704 },
- { "AMEVCNTR111_EL0", 705 },
- { "AMEVCNTR112_EL0", 706 },
- { "AMEVCNTR113_EL0", 707 },
- { "AMEVCNTR114_EL0", 708 },
- { "AMEVCNTR115_EL0", 709 },
- { "AMEVCNTR11_EL0", 695 },
- { "AMEVCNTR12_EL0", 696 },
- { "AMEVCNTR13_EL0", 697 },
- { "AMEVCNTR14_EL0", 698 },
- { "AMEVCNTR15_EL0", 699 },
- { "AMEVCNTR16_EL0", 700 },
- { "AMEVCNTR17_EL0", 701 },
- { "AMEVCNTR18_EL0", 702 },
- { "AMEVCNTR19_EL0", 703 },
- { "AMEVTYPER00_EL0", 688 },
- { "AMEVTYPER01_EL0", 689 },
- { "AMEVTYPER02_EL0", 690 },
- { "AMEVTYPER03_EL0", 691 },
- { "AMEVTYPER10_EL0", 710 },
- { "AMEVTYPER110_EL0", 720 },
- { "AMEVTYPER111_EL0", 721 },
- { "AMEVTYPER112_EL0", 722 },
- { "AMEVTYPER113_EL0", 723 },
- { "AMEVTYPER114_EL0", 724 },
- { "AMEVTYPER115_EL0", 725 },
- { "AMEVTYPER11_EL0", 711 },
- { "AMEVTYPER12_EL0", 712 },
- { "AMEVTYPER13_EL0", 713 },
- { "AMEVTYPER14_EL0", 714 },
- { "AMEVTYPER15_EL0", 715 },
- { "AMEVTYPER16_EL0", 716 },
- { "AMEVTYPER17_EL0", 717 },
- { "AMEVTYPER18_EL0", 718 },
- { "AMEVTYPER19_EL0", 719 },
- { "AMUSERENR_EL0", 681 },
- { "APDAKEYHI_EL1", 642 },
- { "APDAKEYLO_EL1", 641 },
- { "APDBKEYHI_EL1", 644 },
- { "APDBKEYLO_EL1", 643 },
- { "APGAKEYHI_EL1", 646 },
- { "APGAKEYLO_EL1", 645 },
- { "APIAKEYHI_EL1", 638 },
- { "APIAKEYLO_EL1", 637 },
- { "APIBKEYHI_EL1", 640 },
- { "APIBKEYLO_EL1", 639 },
+ { "AMAIR_EL1", 269 },
+ { "AMAIR_EL12", 603 },
+ { "AMAIR_EL2", 270 },
+ { "AMAIR_EL3", 271 },
+ { "AMCFGR_EL0", 680 },
+ { "AMCGCR_EL0", 681 },
+ { "AMCNTENCLR0_EL0", 683 },
+ { "AMCNTENCLR1_EL0", 693 },
+ { "AMCNTENSET0_EL0", 684 },
+ { "AMCNTENSET1_EL0", 694 },
+ { "AMCR_EL0", 679 },
+ { "AMEVCNTR00_EL0", 685 },
+ { "AMEVCNTR01_EL0", 686 },
+ { "AMEVCNTR02_EL0", 687 },
+ { "AMEVCNTR03_EL0", 688 },
+ { "AMEVCNTR10_EL0", 695 },
+ { "AMEVCNTR110_EL0", 705 },
+ { "AMEVCNTR111_EL0", 706 },
+ { "AMEVCNTR112_EL0", 707 },
+ { "AMEVCNTR113_EL0", 708 },
+ { "AMEVCNTR114_EL0", 709 },
+ { "AMEVCNTR115_EL0", 710 },
+ { "AMEVCNTR11_EL0", 696 },
+ { "AMEVCNTR12_EL0", 697 },
+ { "AMEVCNTR13_EL0", 698 },
+ { "AMEVCNTR14_EL0", 699 },
+ { "AMEVCNTR15_EL0", 700 },
+ { "AMEVCNTR16_EL0", 701 },
+ { "AMEVCNTR17_EL0", 702 },
+ { "AMEVCNTR18_EL0", 703 },
+ { "AMEVCNTR19_EL0", 704 },
+ { "AMEVTYPER00_EL0", 689 },
+ { "AMEVTYPER01_EL0", 690 },
+ { "AMEVTYPER02_EL0", 691 },
+ { "AMEVTYPER03_EL0", 692 },
+ { "AMEVTYPER10_EL0", 711 },
+ { "AMEVTYPER110_EL0", 721 },
+ { "AMEVTYPER111_EL0", 722 },
+ { "AMEVTYPER112_EL0", 723 },
+ { "AMEVTYPER113_EL0", 724 },
+ { "AMEVTYPER114_EL0", 725 },
+ { "AMEVTYPER115_EL0", 726 },
+ { "AMEVTYPER11_EL0", 712 },
+ { "AMEVTYPER12_EL0", 713 },
+ { "AMEVTYPER13_EL0", 714 },
+ { "AMEVTYPER14_EL0", 715 },
+ { "AMEVTYPER15_EL0", 716 },
+ { "AMEVTYPER16_EL0", 717 },
+ { "AMEVTYPER17_EL0", 718 },
+ { "AMEVTYPER18_EL0", 719 },
+ { "AMEVTYPER19_EL0", 720 },
+ { "AMUSERENR_EL0", 682 },
+ { "APDAKEYHI_EL1", 643 },
+ { "APDAKEYLO_EL1", 642 },
+ { "APDBKEYHI_EL1", 645 },
+ { "APDBKEYLO_EL1", 644 },
+ { "APGAKEYHI_EL1", 647 },
+ { "APGAKEYLO_EL1", 646 },
+ { "APIAKEYHI_EL1", 639 },
+ { "APIAKEYLO_EL1", 638 },
+ { "APIBKEYHI_EL1", 641 },
+ { "APIBKEYLO_EL1", 640 },
{ "CCSIDR2_EL1", 9 },
{ "CCSIDR_EL1", 8 },
{ "CLIDR_EL1", 10 },
- { "CNTFRQ_EL0", 283 },
- { "CNTHCTL_EL2", 286 },
- { "CNTHPS_CTL_EL2", 654 },
- { "CNTHPS_CVAL_EL2", 653 },
- { "CNTHPS_TVAL_EL2", 652 },
- { "CNTHP_CTL_EL2", 291 },
- { "CNTHP_CVAL_EL2", 294 },
- { "CNTHP_TVAL_EL2", 288 },
- { "CNTHVS_CTL_EL2", 651 },
- { "CNTHVS_CVAL_EL2", 650 },
- { "CNTHVS_TVAL_EL2", 649 },
- { "CNTHV_CTL_EL2", 591 },
- { "CNTHV_CVAL_EL2", 590 },
- { "CNTHV_TVAL_EL2", 589 },
- { "CNTKCTL_EL1", 285 },
- { "CNTKCTL_EL12", 605 },
+ { "CNTFRQ_EL0", 284 },
+ { "CNTHCTL_EL2", 287 },
+ { "CNTHPS_CTL_EL2", 655 },
+ { "CNTHPS_CVAL_EL2", 654 },
+ { "CNTHPS_TVAL_EL2", 653 },
+ { "CNTHP_CTL_EL2", 292 },
+ { "CNTHP_CVAL_EL2", 295 },
+ { "CNTHP_TVAL_EL2", 289 },
+ { "CNTHVS_CTL_EL2", 652 },
+ { "CNTHVS_CVAL_EL2", 651 },
+ { "CNTHVS_TVAL_EL2", 650 },
+ { "CNTHV_CTL_EL2", 592 },
+ { "CNTHV_CVAL_EL2", 591 },
+ { "CNTHV_TVAL_EL2", 590 },
+ { "CNTKCTL_EL1", 286 },
+ { "CNTKCTL_EL12", 606 },
{ "CNTPCT_EL0", 49 },
- { "CNTPS_CTL_EL1", 292 },
- { "CNTPS_CVAL_EL1", 295 },
- { "CNTPS_TVAL_EL1", 289 },
- { "CNTP_CTL_EL0", 290 },
- { "CNTP_CTL_EL02", 607 },
- { "CNTP_CVAL_EL0", 293 },
- { "CNTP_CVAL_EL02", 608 },
- { "CNTP_TVAL_EL0", 287 },
- { "CNTP_TVAL_EL02", 606 },
+ { "CNTPS_CTL_EL1", 293 },
+ { "CNTPS_CVAL_EL1", 296 },
+ { "CNTPS_TVAL_EL1", 290 },
+ { "CNTP_CTL_EL0", 291 },
+ { "CNTP_CTL_EL02", 608 },
+ { "CNTP_CVAL_EL0", 294 },
+ { "CNTP_CVAL_EL02", 609 },
+ { "CNTP_TVAL_EL0", 288 },
+ { "CNTP_TVAL_EL02", 607 },
{ "CNTVCT_EL0", 50 },
- { "CNTVOFF_EL2", 284 },
- { "CNTV_CTL_EL0", 297 },
- { "CNTV_CTL_EL02", 610 },
- { "CNTV_CVAL_EL0", 298 },
- { "CNTV_CVAL_EL02", 611 },
- { "CNTV_TVAL_EL0", 296 },
- { "CNTV_TVAL_EL02", 609 },
- { "CONTEXTIDR_EL1", 277 },
- { "CONTEXTIDR_EL12", 604 },
- { "CONTEXTIDR_EL2", 588 },
- { "CPACR_EL1", 190 },
- { "CPACR_EL12", 593 },
- { "CPM_IOACC_CTL_EL3", 731 },
- { "CPTR_EL2", 201 },
- { "CPTR_EL3", 202 },
- { "CSSELR_EL1", 187 },
+ { "CNTVOFF_EL2", 285 },
+ { "CNTV_CTL_EL0", 298 },
+ { "CNTV_CTL_EL02", 611 },
+ { "CNTV_CVAL_EL0", 299 },
+ { "CNTV_CVAL_EL02", 612 },
+ { "CNTV_TVAL_EL0", 297 },
+ { "CNTV_TVAL_EL02", 610 },
+ { "CONTEXTIDR_EL1", 278 },
+ { "CONTEXTIDR_EL12", 605 },
+ { "CONTEXTIDR_EL2", 589 },
+ { "CPACR_EL1", 191 },
+ { "CPACR_EL12", 594 },
+ { "CPM_IOACC_CTL_EL3", 736 },
+ { "CPTR_EL2", 202 },
+ { "CPTR_EL3", 203 },
+ { "CSSELR_EL1", 188 },
{ "CTR_EL0", 11 },
- { "CURRENTEL", 228 },
- { "DACR32_EL2", 215 },
- { "DAIF", 227 },
+ { "CURRENTEL", 229 },
+ { "DACR32_EL2", 216 },
+ { "DAIF", 228 },
{ "DBGAUTHSTATUS_EL1", 4 },
- { "DBGBCR0_EL1", 134 },
- { "DBGBCR10_EL1", 144 },
- { "DBGBCR11_EL1", 145 },
- { "DBGBCR12_EL1", 146 },
- { "DBGBCR13_EL1", 147 },
- { "DBGBCR14_EL1", 148 },
- { "DBGBCR15_EL1", 149 },
- { "DBGBCR1_EL1", 135 },
- { "DBGBCR2_EL1", 136 },
- { "DBGBCR3_EL1", 137 },
- { "DBGBCR4_EL1", 138 },
- { "DBGBCR5_EL1", 139 },
- { "DBGBCR6_EL1", 140 },
- { "DBGBCR7_EL1", 141 },
- { "DBGBCR8_EL1", 142 },
- { "DBGBCR9_EL1", 143 },
- { "DBGBVR0_EL1", 118 },
- { "DBGBVR10_EL1", 128 },
- { "DBGBVR11_EL1", 129 },
- { "DBGBVR12_EL1", 130 },
- { "DBGBVR13_EL1", 131 },
- { "DBGBVR14_EL1", 132 },
- { "DBGBVR15_EL1", 133 },
- { "DBGBVR1_EL1", 119 },
- { "DBGBVR2_EL1", 120 },
- { "DBGBVR3_EL1", 121 },
- { "DBGBVR4_EL1", 122 },
- { "DBGBVR5_EL1", 123 },
- { "DBGBVR6_EL1", 124 },
- { "DBGBVR7_EL1", 125 },
- { "DBGBVR8_EL1", 126 },
- { "DBGBVR9_EL1", 127 },
- { "DBGCLAIMCLR_EL1", 186 },
- { "DBGCLAIMSET_EL1", 185 },
+ { "DBGBCR0_EL1", 135 },
+ { "DBGBCR10_EL1", 145 },
+ { "DBGBCR11_EL1", 146 },
+ { "DBGBCR12_EL1", 147 },
+ { "DBGBCR13_EL1", 148 },
+ { "DBGBCR14_EL1", 149 },
+ { "DBGBCR15_EL1", 150 },
+ { "DBGBCR1_EL1", 136 },
+ { "DBGBCR2_EL1", 137 },
+ { "DBGBCR3_EL1", 138 },
+ { "DBGBCR4_EL1", 139 },
+ { "DBGBCR5_EL1", 140 },
+ { "DBGBCR6_EL1", 141 },
+ { "DBGBCR7_EL1", 142 },
+ { "DBGBCR8_EL1", 143 },
+ { "DBGBCR9_EL1", 144 },
+ { "DBGBVR0_EL1", 119 },
+ { "DBGBVR10_EL1", 129 },
+ { "DBGBVR11_EL1", 130 },
+ { "DBGBVR12_EL1", 131 },
+ { "DBGBVR13_EL1", 132 },
+ { "DBGBVR14_EL1", 133 },
+ { "DBGBVR15_EL1", 134 },
+ { "DBGBVR1_EL1", 120 },
+ { "DBGBVR2_EL1", 121 },
+ { "DBGBVR3_EL1", 122 },
+ { "DBGBVR4_EL1", 123 },
+ { "DBGBVR5_EL1", 124 },
+ { "DBGBVR6_EL1", 125 },
+ { "DBGBVR7_EL1", 126 },
+ { "DBGBVR8_EL1", 127 },
+ { "DBGBVR9_EL1", 128 },
+ { "DBGCLAIMCLR_EL1", 187 },
+ { "DBGCLAIMSET_EL1", 186 },
{ "DBGDTRRX_EL0", 1 },
- { "DBGDTRTX_EL0", 99 },
- { "DBGDTR_EL0", 115 },
- { "DBGPRCR_EL1", 184 },
- { "DBGVCR32_EL2", 117 },
- { "DBGWCR0_EL1", 166 },
- { "DBGWCR10_EL1", 176 },
- { "DBGWCR11_EL1", 177 },
- { "DBGWCR12_EL1", 178 },
- { "DBGWCR13_EL1", 179 },
- { "DBGWCR14_EL1", 180 },
- { "DBGWCR15_EL1", 181 },
- { "DBGWCR1_EL1", 167 },
- { "DBGWCR2_EL1", 168 },
- { "DBGWCR3_EL1", 169 },
- { "DBGWCR4_EL1", 170 },
- { "DBGWCR5_EL1", 171 },
- { "DBGWCR6_EL1", 172 },
- { "DBGWCR7_EL1", 173 },
- { "DBGWCR8_EL1", 174 },
- { "DBGWCR9_EL1", 175 },
- { "DBGWVR0_EL1", 150 },
- { "DBGWVR10_EL1", 160 },
- { "DBGWVR11_EL1", 161 },
- { "DBGWVR12_EL1", 162 },
- { "DBGWVR13_EL1", 163 },
- { "DBGWVR14_EL1", 164 },
- { "DBGWVR15_EL1", 165 },
- { "DBGWVR1_EL1", 151 },
- { "DBGWVR2_EL1", 152 },
- { "DBGWVR3_EL1", 153 },
- { "DBGWVR4_EL1", 154 },
- { "DBGWVR5_EL1", 155 },
- { "DBGWVR6_EL1", 156 },
- { "DBGWVR7_EL1", 157 },
- { "DBGWVR8_EL1", 158 },
- { "DBGWVR9_EL1", 159 },
+ { "DBGDTRTX_EL0", 100 },
+ { "DBGDTR_EL0", 116 },
+ { "DBGPRCR_EL1", 185 },
+ { "DBGVCR32_EL2", 118 },
+ { "DBGWCR0_EL1", 167 },
+ { "DBGWCR10_EL1", 177 },
+ { "DBGWCR11_EL1", 178 },
+ { "DBGWCR12_EL1", 179 },
+ { "DBGWCR13_EL1", 180 },
+ { "DBGWCR14_EL1", 181 },
+ { "DBGWCR15_EL1", 182 },
+ { "DBGWCR1_EL1", 168 },
+ { "DBGWCR2_EL1", 169 },
+ { "DBGWCR3_EL1", 170 },
+ { "DBGWCR4_EL1", 171 },
+ { "DBGWCR5_EL1", 172 },
+ { "DBGWCR6_EL1", 173 },
+ { "DBGWCR7_EL1", 174 },
+ { "DBGWCR8_EL1", 175 },
+ { "DBGWCR9_EL1", 176 },
+ { "DBGWVR0_EL1", 151 },
+ { "DBGWVR10_EL1", 161 },
+ { "DBGWVR11_EL1", 162 },
+ { "DBGWVR12_EL1", 163 },
+ { "DBGWVR13_EL1", 164 },
+ { "DBGWVR14_EL1", 165 },
+ { "DBGWVR15_EL1", 166 },
+ { "DBGWVR1_EL1", 152 },
+ { "DBGWVR2_EL1", 153 },
+ { "DBGWVR3_EL1", 154 },
+ { "DBGWVR4_EL1", 155 },
+ { "DBGWVR5_EL1", 156 },
+ { "DBGWVR6_EL1", 157 },
+ { "DBGWVR7_EL1", 158 },
+ { "DBGWVR8_EL1", 159 },
+ { "DBGWVR9_EL1", 160 },
{ "DCZID_EL0", 15 },
- { "DISR_EL1", 634 },
- { "DIT", 729 },
- { "DLR_EL0", 236 },
- { "DSPSR_EL0", 235 },
- { "ELR_EL1", 219 },
- { "ELR_EL12", 613 },
- { "ELR_EL2", 220 },
- { "ELR_EL3", 221 },
- { "ERRIDR_EL1", 97 },
- { "ERRSELR_EL1", 628 },
- { "ERXADDR_EL1", 631 },
- { "ERXCTLR_EL1", 629 },
- { "ERXFR_EL1", 98 },
- { "ERXMISC0_EL1", 632 },
- { "ERXMISC1_EL1", 633 },
- { "ERXMISC2_EL1", 659 },
- { "ERXMISC3_EL1", 660 },
- { "ERXPFGCDN_EL1", 657 },
- { "ERXPFGCTL_EL1", 656 },
- { "ERXPFGF_EL1", 661 },
- { "ERXSTATUS_EL1", 630 },
- { "ERXTS_EL1", 658 },
- { "ESR_EL1", 244 },
- { "ESR_EL12", 599 },
- { "ESR_EL2", 245 },
- { "ESR_EL3", 246 },
- { "FAR_EL1", 248 },
- { "FAR_EL12", 600 },
- { "FAR_EL2", 249 },
- { "FAR_EL3", 250 },
- { "FPCR", 233 },
- { "FPEXC32_EL2", 247 },
- { "FPSR", 234 },
- { "HACR_EL2", 204 },
- { "HCR_EL2", 197 },
- { "HPFAR_EL2", 251 },
- { "HSTR_EL2", 203 },
- { "ICC_AP0R0_EL1", 546 },
- { "ICC_AP0R1_EL1", 547 },
- { "ICC_AP0R2_EL1", 548 },
- { "ICC_AP0R3_EL1", 549 },
- { "ICC_AP1R0_EL1", 550 },
- { "ICC_AP1R1_EL1", 551 },
- { "ICC_AP1R2_EL1", 552 },
- { "ICC_AP1R3_EL1", 553 },
- { "ICC_ASGI1R_EL1", 108 },
- { "ICC_BPR0_EL1", 535 },
- { "ICC_BPR1_EL1", 534 },
- { "ICC_CTLR_EL1", 537 },
- { "ICC_CTLR_EL3", 538 },
- { "ICC_DIR_EL1", 106 },
- { "ICC_EOIR0_EL1", 105 },
- { "ICC_EOIR1_EL1", 104 },
+ { "DISR_EL1", 635 },
+ { "DIT", 730 },
+ { "DLR_EL0", 237 },
+ { "DSPSR_EL0", 236 },
+ { "ELR_EL1", 220 },
+ { "ELR_EL12", 614 },
+ { "ELR_EL2", 221 },
+ { "ELR_EL3", 222 },
+ { "ERRIDR_EL1", 98 },
+ { "ERRSELR_EL1", 629 },
+ { "ERXADDR_EL1", 632 },
+ { "ERXCTLR_EL1", 630 },
+ { "ERXFR_EL1", 99 },
+ { "ERXMISC0_EL1", 633 },
+ { "ERXMISC1_EL1", 634 },
+ { "ERXMISC2_EL1", 660 },
+ { "ERXMISC3_EL1", 661 },
+ { "ERXPFGCDN_EL1", 658 },
+ { "ERXPFGCTL_EL1", 657 },
+ { "ERXPFGF_EL1", 662 },
+ { "ERXSTATUS_EL1", 631 },
+ { "ERXTS_EL1", 659 },
+ { "ESR_EL1", 245 },
+ { "ESR_EL12", 600 },
+ { "ESR_EL2", 246 },
+ { "ESR_EL3", 247 },
+ { "FAR_EL1", 249 },
+ { "FAR_EL12", 601 },
+ { "FAR_EL2", 250 },
+ { "FAR_EL3", 251 },
+ { "FPCR", 234 },
+ { "FPEXC32_EL2", 248 },
+ { "FPSR", 235 },
+ { "HACR_EL2", 205 },
+ { "HCR_EL2", 198 },
+ { "HPFAR_EL2", 252 },
+ { "HSTR_EL2", 204 },
+ { "ICC_AP0R0_EL1", 547 },
+ { "ICC_AP0R1_EL1", 548 },
+ { "ICC_AP0R2_EL1", 549 },
+ { "ICC_AP0R3_EL1", 550 },
+ { "ICC_AP1R0_EL1", 551 },
+ { "ICC_AP1R1_EL1", 552 },
+ { "ICC_AP1R2_EL1", 553 },
+ { "ICC_AP1R3_EL1", 554 },
+ { "ICC_ASGI1R_EL1", 109 },
+ { "ICC_BPR0_EL1", 536 },
+ { "ICC_BPR1_EL1", 535 },
+ { "ICC_CTLR_EL1", 538 },
+ { "ICC_CTLR_EL3", 539 },
+ { "ICC_DIR_EL1", 107 },
+ { "ICC_EOIR0_EL1", 106 },
+ { "ICC_EOIR1_EL1", 105 },
{ "ICC_HPPIR0_EL1", 91 },
{ "ICC_HPPIR1_EL1", 90 },
{ "ICC_IAR0_EL1", 89 },
{ "ICC_IAR1_EL1", 88 },
- { "ICC_IGRPEN0_EL1", 542 },
- { "ICC_IGRPEN1_EL1", 543 },
- { "ICC_IGRPEN1_EL3", 544 },
- { "ICC_PMR_EL1", 536 },
+ { "ICC_IGRPEN0_EL1", 543 },
+ { "ICC_IGRPEN1_EL1", 544 },
+ { "ICC_IGRPEN1_EL3", 545 },
+ { "ICC_PMR_EL1", 537 },
{ "ICC_RPR_EL1", 92 },
- { "ICC_SEIEN_EL1", 545 },
- { "ICC_SGI0R_EL1", 109 },
- { "ICC_SGI1R_EL1", 107 },
- { "ICC_SRE_EL1", 539 },
- { "ICC_SRE_EL2", 540 },
- { "ICC_SRE_EL3", 541 },
- { "ICH_AP0R0_EL2", 554 },
- { "ICH_AP0R1_EL2", 555 },
- { "ICH_AP0R2_EL2", 556 },
- { "ICH_AP0R3_EL2", 557 },
- { "ICH_AP1R0_EL2", 558 },
- { "ICH_AP1R1_EL2", 559 },
- { "ICH_AP1R2_EL2", 560 },
- { "ICH_AP1R3_EL2", 561 },
+ { "ICC_SEIEN_EL1", 546 },
+ { "ICC_SGI0R_EL1", 110 },
+ { "ICC_SGI1R_EL1", 108 },
+ { "ICC_SRE_EL1", 540 },
+ { "ICC_SRE_EL2", 541 },
+ { "ICC_SRE_EL3", 542 },
+ { "ICH_AP0R0_EL2", 555 },
+ { "ICH_AP0R1_EL2", 556 },
+ { "ICH_AP0R2_EL2", 557 },
+ { "ICH_AP0R3_EL2", 558 },
+ { "ICH_AP1R0_EL2", 559 },
+ { "ICH_AP1R1_EL2", 560 },
+ { "ICH_AP1R2_EL2", 561 },
+ { "ICH_AP1R3_EL2", 562 },
{ "ICH_EISR_EL2", 94 },
{ "ICH_ELRSR_EL2", 95 },
- { "ICH_HCR_EL2", 562 },
- { "ICH_LR0_EL2", 566 },
- { "ICH_LR10_EL2", 576 },
- { "ICH_LR11_EL2", 577 },
- { "ICH_LR12_EL2", 578 },
- { "ICH_LR13_EL2", 579 },
- { "ICH_LR14_EL2", 580 },
- { "ICH_LR15_EL2", 581 },
- { "ICH_LR1_EL2", 567 },
- { "ICH_LR2_EL2", 568 },
- { "ICH_LR3_EL2", 569 },
- { "ICH_LR4_EL2", 570 },
- { "ICH_LR5_EL2", 571 },
- { "ICH_LR6_EL2", 572 },
- { "ICH_LR7_EL2", 573 },
- { "ICH_LR8_EL2", 574 },
- { "ICH_LR9_EL2", 575 },
- { "ICH_MISR_EL2", 563 },
- { "ICH_VMCR_EL2", 564 },
- { "ICH_VSEIR_EL2", 565 },
+ { "ICH_HCR_EL2", 563 },
+ { "ICH_LR0_EL2", 567 },
+ { "ICH_LR10_EL2", 577 },
+ { "ICH_LR11_EL2", 578 },
+ { "ICH_LR12_EL2", 579 },
+ { "ICH_LR13_EL2", 580 },
+ { "ICH_LR14_EL2", 581 },
+ { "ICH_LR15_EL2", 582 },
+ { "ICH_LR1_EL2", 568 },
+ { "ICH_LR2_EL2", 569 },
+ { "ICH_LR3_EL2", 570 },
+ { "ICH_LR4_EL2", 571 },
+ { "ICH_LR5_EL2", 572 },
+ { "ICH_LR6_EL2", 573 },
+ { "ICH_LR7_EL2", 574 },
+ { "ICH_LR8_EL2", 575 },
+ { "ICH_LR9_EL2", 576 },
+ { "ICH_MISR_EL2", 564 },
+ { "ICH_VMCR_EL2", 565 },
+ { "ICH_VSEIR_EL2", 566 },
{ "ICH_VTR_EL2", 93 },
{ "ID_AA64AFR0_EL1", 35 },
{ "ID_AA64AFR1_EL1", 36 },
@@ -3021,6 +3031,7 @@
{ "ID_AA64MMFR2_EL1", 41 },
{ "ID_AA64PFR0_EL1", 31 },
{ "ID_AA64PFR1_EL1", 32 },
+ { "ID_AA64ZFR0_EL1", 96 },
{ "ID_AFR0_EL1", 19 },
{ "ID_DFR0_EL1", 18 },
{ "ID_ISAR0_EL1", 24 },
@@ -3037,270 +3048,270 @@
{ "ID_MMFR4_EL1", 51 },
{ "ID_PFR0_EL1", 16 },
{ "ID_PFR1_EL1", 17 },
- { "IFSR32_EL2", 237 },
+ { "IFSR32_EL2", 238 },
{ "ISR_EL1", 48 },
- { "LORC_EL1", 586 },
- { "LOREA_EL1", 584 },
- { "LORID_EL1", 96 },
- { "LORN_EL1", 585 },
- { "LORSA_EL1", 583 },
- { "MAIR_EL1", 265 },
- { "MAIR_EL12", 601 },
- { "MAIR_EL2", 266 },
- { "MAIR_EL3", 267 },
- { "MDCCINT_EL1", 113 },
+ { "LORC_EL1", 587 },
+ { "LOREA_EL1", 585 },
+ { "LORID_EL1", 97 },
+ { "LORN_EL1", 586 },
+ { "LORSA_EL1", 584 },
+ { "MAIR_EL1", 266 },
+ { "MAIR_EL12", 602 },
+ { "MAIR_EL2", 267 },
+ { "MAIR_EL3", 268 },
+ { "MDCCINT_EL1", 114 },
{ "MDCCSR_EL0", 0 },
- { "MDCR_EL2", 199 },
- { "MDCR_EL3", 205 },
+ { "MDCR_EL2", 200 },
+ { "MDCR_EL3", 206 },
{ "MDRAR_EL1", 2 },
- { "MDSCR_EL1", 114 },
+ { "MDSCR_EL1", 115 },
{ "MIDR_EL1", 7 },
- { "MPAM0_EL1", 662 },
- { "MPAM1_EL1", 663 },
- { "MPAM1_EL12", 666 },
- { "MPAM2_EL2", 664 },
- { "MPAM3_EL3", 665 },
- { "MPAMHCR_EL2", 667 },
- { "MPAMIDR_EL1", 677 },
- { "MPAMVPM0_EL2", 669 },
- { "MPAMVPM1_EL2", 670 },
- { "MPAMVPM2_EL2", 671 },
- { "MPAMVPM3_EL2", 672 },
- { "MPAMVPM4_EL2", 673 },
- { "MPAMVPM5_EL2", 674 },
- { "MPAMVPM6_EL2", 675 },
- { "MPAMVPM7_EL2", 676 },
- { "MPAMVPMV_EL2", 668 },
+ { "MPAM0_EL1", 663 },
+ { "MPAM1_EL1", 664 },
+ { "MPAM1_EL12", 667 },
+ { "MPAM2_EL2", 665 },
+ { "MPAM3_EL3", 666 },
+ { "MPAMHCR_EL2", 668 },
+ { "MPAMIDR_EL1", 678 },
+ { "MPAMVPM0_EL2", 670 },
+ { "MPAMVPM1_EL2", 671 },
+ { "MPAMVPM2_EL2", 672 },
+ { "MPAMVPM3_EL2", 673 },
+ { "MPAMVPM4_EL2", 674 },
+ { "MPAMVPM5_EL2", 675 },
+ { "MPAMVPM6_EL2", 676 },
+ { "MPAMVPM7_EL2", 677 },
+ { "MPAMVPMV_EL2", 669 },
{ "MPIDR_EL1", 12 },
{ "MVFR0_EL1", 42 },
{ "MVFR1_EL1", 43 },
{ "MVFR2_EL1", 44 },
- { "NZCV", 226 },
- { "OSDLR_EL1", 183 },
- { "OSDTRRX_EL1", 110 },
- { "OSDTRTX_EL1", 111 },
- { "OSECCR_EL1", 116 },
- { "OSLAR_EL1", 100 },
+ { "NZCV", 227 },
+ { "OSDLR_EL1", 184 },
+ { "OSDTRRX_EL1", 111 },
+ { "OSDTRTX_EL1", 112 },
+ { "OSECCR_EL1", 117 },
+ { "OSLAR_EL1", 101 },
{ "OSLSR_EL1", 3 },
- { "PAN", 582 },
- { "PAR_EL1", 252 },
- { "PMBIDR_EL1", 618 },
- { "PMBLIMITR_EL1", 615 },
- { "PMBPTR_EL1", 616 },
- { "PMBSR_EL1", 617 },
- { "PMCCFILTR_EL0", 330 },
- { "PMCCNTR_EL0", 258 },
+ { "PAN", 583 },
+ { "PAR_EL1", 253 },
+ { "PMBIDR_EL1", 619 },
+ { "PMBLIMITR_EL1", 616 },
+ { "PMBPTR_EL1", 617 },
+ { "PMBSR_EL1", 618 },
+ { "PMCCFILTR_EL0", 331 },
+ { "PMCCNTR_EL0", 259 },
{ "PMCEID0_EL0", 5 },
{ "PMCEID1_EL0", 6 },
- { "PMCNTENCLR_EL0", 255 },
- { "PMCNTENSET_EL0", 254 },
- { "PMCR_EL0", 253 },
- { "PMEVCNTR0_EL0", 299 },
- { "PMEVCNTR10_EL0", 309 },
- { "PMEVCNTR11_EL0", 310 },
- { "PMEVCNTR12_EL0", 311 },
- { "PMEVCNTR13_EL0", 312 },
- { "PMEVCNTR14_EL0", 313 },
- { "PMEVCNTR15_EL0", 314 },
- { "PMEVCNTR16_EL0", 315 },
- { "PMEVCNTR17_EL0", 316 },
- { "PMEVCNTR18_EL0", 317 },
- { "PMEVCNTR19_EL0", 318 },
- { "PMEVCNTR1_EL0", 300 },
- { "PMEVCNTR20_EL0", 319 },
- { "PMEVCNTR21_EL0", 320 },
- { "PMEVCNTR22_EL0", 321 },
- { "PMEVCNTR23_EL0", 322 },
- { "PMEVCNTR24_EL0", 323 },
- { "PMEVCNTR25_EL0", 324 },
- { "PMEVCNTR26_EL0", 325 },
- { "PMEVCNTR27_EL0", 326 },
- { "PMEVCNTR28_EL0", 327 },
- { "PMEVCNTR29_EL0", 328 },
- { "PMEVCNTR2_EL0", 301 },
- { "PMEVCNTR30_EL0", 329 },
- { "PMEVCNTR3_EL0", 302 },
- { "PMEVCNTR4_EL0", 303 },
- { "PMEVCNTR5_EL0", 304 },
- { "PMEVCNTR6_EL0", 305 },
- { "PMEVCNTR7_EL0", 306 },
- { "PMEVCNTR8_EL0", 307 },
- { "PMEVCNTR9_EL0", 308 },
- { "PMEVTYPER0_EL0", 331 },
- { "PMEVTYPER10_EL0", 341 },
- { "PMEVTYPER11_EL0", 342 },
- { "PMEVTYPER12_EL0", 343 },
- { "PMEVTYPER13_EL0", 344 },
- { "PMEVTYPER14_EL0", 345 },
- { "PMEVTYPER15_EL0", 346 },
- { "PMEVTYPER16_EL0", 347 },
- { "PMEVTYPER17_EL0", 348 },
- { "PMEVTYPER18_EL0", 349 },
- { "PMEVTYPER19_EL0", 350 },
- { "PMEVTYPER1_EL0", 332 },
- { "PMEVTYPER20_EL0", 351 },
- { "PMEVTYPER21_EL0", 352 },
- { "PMEVTYPER22_EL0", 353 },
- { "PMEVTYPER23_EL0", 354 },
- { "PMEVTYPER24_EL0", 355 },
- { "PMEVTYPER25_EL0", 356 },
- { "PMEVTYPER26_EL0", 357 },
- { "PMEVTYPER27_EL0", 358 },
- { "PMEVTYPER28_EL0", 359 },
- { "PMEVTYPER29_EL0", 360 },
- { "PMEVTYPER2_EL0", 333 },
- { "PMEVTYPER30_EL0", 361 },
- { "PMEVTYPER3_EL0", 334 },
- { "PMEVTYPER4_EL0", 335 },
- { "PMEVTYPER5_EL0", 336 },
- { "PMEVTYPER6_EL0", 337 },
- { "PMEVTYPER7_EL0", 338 },
- { "PMEVTYPER8_EL0", 339 },
- { "PMEVTYPER9_EL0", 340 },
- { "PMINTENCLR_EL1", 263 },
- { "PMINTENSET_EL1", 262 },
- { "PMOVSCLR_EL0", 256 },
- { "PMOVSSET_EL0", 264 },
- { "PMSCR_EL1", 621 },
- { "PMSCR_EL12", 620 },
- { "PMSCR_EL2", 619 },
- { "PMSELR_EL0", 257 },
- { "PMSEVFR_EL1", 625 },
- { "PMSFCR_EL1", 624 },
- { "PMSICR_EL1", 622 },
- { "PMSIDR_EL1", 627 },
- { "PMSIRR_EL1", 623 },
- { "PMSLATFR_EL1", 626 },
- { "PMSWINC_EL0", 101 },
- { "PMUSERENR_EL0", 261 },
- { "PMXEVCNTR_EL0", 260 },
- { "PMXEVTYPER_EL0", 259 },
+ { "PMCNTENCLR_EL0", 256 },
+ { "PMCNTENSET_EL0", 255 },
+ { "PMCR_EL0", 254 },
+ { "PMEVCNTR0_EL0", 300 },
+ { "PMEVCNTR10_EL0", 310 },
+ { "PMEVCNTR11_EL0", 311 },
+ { "PMEVCNTR12_EL0", 312 },
+ { "PMEVCNTR13_EL0", 313 },
+ { "PMEVCNTR14_EL0", 314 },
+ { "PMEVCNTR15_EL0", 315 },
+ { "PMEVCNTR16_EL0", 316 },
+ { "PMEVCNTR17_EL0", 317 },
+ { "PMEVCNTR18_EL0", 318 },
+ { "PMEVCNTR19_EL0", 319 },
+ { "PMEVCNTR1_EL0", 301 },
+ { "PMEVCNTR20_EL0", 320 },
+ { "PMEVCNTR21_EL0", 321 },
+ { "PMEVCNTR22_EL0", 322 },
+ { "PMEVCNTR23_EL0", 323 },
+ { "PMEVCNTR24_EL0", 324 },
+ { "PMEVCNTR25_EL0", 325 },
+ { "PMEVCNTR26_EL0", 326 },
+ { "PMEVCNTR27_EL0", 327 },
+ { "PMEVCNTR28_EL0", 328 },
+ { "PMEVCNTR29_EL0", 329 },
+ { "PMEVCNTR2_EL0", 302 },
+ { "PMEVCNTR30_EL0", 330 },
+ { "PMEVCNTR3_EL0", 303 },
+ { "PMEVCNTR4_EL0", 304 },
+ { "PMEVCNTR5_EL0", 305 },
+ { "PMEVCNTR6_EL0", 306 },
+ { "PMEVCNTR7_EL0", 307 },
+ { "PMEVCNTR8_EL0", 308 },
+ { "PMEVCNTR9_EL0", 309 },
+ { "PMEVTYPER0_EL0", 332 },
+ { "PMEVTYPER10_EL0", 342 },
+ { "PMEVTYPER11_EL0", 343 },
+ { "PMEVTYPER12_EL0", 344 },
+ { "PMEVTYPER13_EL0", 345 },
+ { "PMEVTYPER14_EL0", 346 },
+ { "PMEVTYPER15_EL0", 347 },
+ { "PMEVTYPER16_EL0", 348 },
+ { "PMEVTYPER17_EL0", 349 },
+ { "PMEVTYPER18_EL0", 350 },
+ { "PMEVTYPER19_EL0", 351 },
+ { "PMEVTYPER1_EL0", 333 },
+ { "PMEVTYPER20_EL0", 352 },
+ { "PMEVTYPER21_EL0", 353 },
+ { "PMEVTYPER22_EL0", 354 },
+ { "PMEVTYPER23_EL0", 355 },
+ { "PMEVTYPER24_EL0", 356 },
+ { "PMEVTYPER25_EL0", 357 },
+ { "PMEVTYPER26_EL0", 358 },
+ { "PMEVTYPER27_EL0", 359 },
+ { "PMEVTYPER28_EL0", 360 },
+ { "PMEVTYPER29_EL0", 361 },
+ { "PMEVTYPER2_EL0", 334 },
+ { "PMEVTYPER30_EL0", 362 },
+ { "PMEVTYPER3_EL0", 335 },
+ { "PMEVTYPER4_EL0", 336 },
+ { "PMEVTYPER5_EL0", 337 },
+ { "PMEVTYPER6_EL0", 338 },
+ { "PMEVTYPER7_EL0", 339 },
+ { "PMEVTYPER8_EL0", 340 },
+ { "PMEVTYPER9_EL0", 341 },
+ { "PMINTENCLR_EL1", 264 },
+ { "PMINTENSET_EL1", 263 },
+ { "PMOVSCLR_EL0", 257 },
+ { "PMOVSSET_EL0", 265 },
+ { "PMSCR_EL1", 622 },
+ { "PMSCR_EL12", 621 },
+ { "PMSCR_EL2", 620 },
+ { "PMSELR_EL0", 258 },
+ { "PMSEVFR_EL1", 626 },
+ { "PMSFCR_EL1", 625 },
+ { "PMSICR_EL1", 623 },
+ { "PMSIDR_EL1", 628 },
+ { "PMSIRR_EL1", 624 },
+ { "PMSLATFR_EL1", 627 },
+ { "PMSWINC_EL0", 102 },
+ { "PMUSERENR_EL0", 262 },
+ { "PMXEVCNTR_EL0", 261 },
+ { "PMXEVTYPER_EL0", 260 },
{ "REVIDR_EL1", 13 },
- { "RMR_EL1", 274 },
- { "RMR_EL2", 275 },
- { "RMR_EL3", 276 },
+ { "RMR_EL1", 275 },
+ { "RMR_EL2", 276 },
+ { "RMR_EL3", 277 },
{ "RVBAR_EL1", 45 },
{ "RVBAR_EL2", 46 },
{ "RVBAR_EL3", 47 },
- { "SCR_EL3", 198 },
- { "SCTLR_EL1", 191 },
- { "SCTLR_EL12", 592 },
- { "SCTLR_EL2", 192 },
- { "SCTLR_EL3", 193 },
- { "SDER32_EL2", 655 },
- { "SDER32_EL3", 200 },
- { "SPSEL", 225 },
- { "SPSR_ABT", 230 },
- { "SPSR_EL1", 216 },
- { "SPSR_EL12", 612 },
- { "SPSR_EL2", 217 },
- { "SPSR_EL3", 218 },
- { "SPSR_FIQ", 232 },
- { "SPSR_IRQ", 229 },
- { "SPSR_UND", 231 },
- { "SP_EL0", 222 },
- { "SP_EL1", 223 },
- { "SP_EL2", 224 },
- { "TCR_EL1", 210 },
- { "TCR_EL12", 596 },
- { "TCR_EL2", 211 },
- { "TCR_EL3", 212 },
- { "TEECR32_EL1", 112 },
- { "TEEHBR32_EL1", 182 },
- { "TPIDRRO_EL0", 281 },
- { "TPIDR_EL0", 278 },
- { "TPIDR_EL1", 282 },
- { "TPIDR_EL2", 279 },
- { "TPIDR_EL3", 280 },
- { "TRCACATR0", 479 },
- { "TRCACATR1", 480 },
- { "TRCACATR10", 489 },
- { "TRCACATR11", 490 },
- { "TRCACATR12", 491 },
- { "TRCACATR13", 492 },
- { "TRCACATR14", 493 },
- { "TRCACATR15", 494 },
- { "TRCACATR2", 481 },
- { "TRCACATR3", 482 },
- { "TRCACATR4", 483 },
- { "TRCACATR5", 484 },
- { "TRCACATR6", 485 },
- { "TRCACATR7", 486 },
- { "TRCACATR8", 487 },
- { "TRCACATR9", 488 },
- { "TRCACVR0", 463 },
- { "TRCACVR1", 464 },
- { "TRCACVR10", 473 },
- { "TRCACVR11", 474 },
- { "TRCACVR12", 475 },
- { "TRCACVR13", 476 },
- { "TRCACVR14", 477 },
- { "TRCACVR15", 478 },
- { "TRCACVR2", 465 },
- { "TRCACVR3", 466 },
- { "TRCACVR4", 467 },
- { "TRCACVR5", 468 },
- { "TRCACVR6", 469 },
- { "TRCACVR7", 470 },
- { "TRCACVR8", 471 },
- { "TRCACVR9", 472 },
+ { "SCR_EL3", 199 },
+ { "SCTLR_EL1", 192 },
+ { "SCTLR_EL12", 593 },
+ { "SCTLR_EL2", 193 },
+ { "SCTLR_EL3", 194 },
+ { "SDER32_EL2", 656 },
+ { "SDER32_EL3", 201 },
+ { "SPSEL", 226 },
+ { "SPSR_ABT", 231 },
+ { "SPSR_EL1", 217 },
+ { "SPSR_EL12", 613 },
+ { "SPSR_EL2", 218 },
+ { "SPSR_EL3", 219 },
+ { "SPSR_FIQ", 233 },
+ { "SPSR_IRQ", 230 },
+ { "SPSR_UND", 232 },
+ { "SP_EL0", 223 },
+ { "SP_EL1", 224 },
+ { "SP_EL2", 225 },
+ { "TCR_EL1", 211 },
+ { "TCR_EL12", 597 },
+ { "TCR_EL2", 212 },
+ { "TCR_EL3", 213 },
+ { "TEECR32_EL1", 113 },
+ { "TEEHBR32_EL1", 183 },
+ { "TPIDRRO_EL0", 282 },
+ { "TPIDR_EL0", 279 },
+ { "TPIDR_EL1", 283 },
+ { "TPIDR_EL2", 280 },
+ { "TPIDR_EL3", 281 },
+ { "TRCACATR0", 480 },
+ { "TRCACATR1", 481 },
+ { "TRCACATR10", 490 },
+ { "TRCACATR11", 491 },
+ { "TRCACATR12", 492 },
+ { "TRCACATR13", 493 },
+ { "TRCACATR14", 494 },
+ { "TRCACATR15", 495 },
+ { "TRCACATR2", 482 },
+ { "TRCACATR3", 483 },
+ { "TRCACATR4", 484 },
+ { "TRCACATR5", 485 },
+ { "TRCACATR6", 486 },
+ { "TRCACATR7", 487 },
+ { "TRCACATR8", 488 },
+ { "TRCACATR9", 489 },
+ { "TRCACVR0", 464 },
+ { "TRCACVR1", 465 },
+ { "TRCACVR10", 474 },
+ { "TRCACVR11", 475 },
+ { "TRCACVR12", 476 },
+ { "TRCACVR13", 477 },
+ { "TRCACVR14", 478 },
+ { "TRCACVR15", 479 },
+ { "TRCACVR2", 466 },
+ { "TRCACVR3", 467 },
+ { "TRCACVR4", 468 },
+ { "TRCACVR5", 469 },
+ { "TRCACVR6", 470 },
+ { "TRCACVR7", 471 },
+ { "TRCACVR8", 472 },
+ { "TRCACVR9", 473 },
{ "TRCAUTHSTATUS", 72 },
- { "TRCAUXCTLR", 365 },
- { "TRCBBCTLR", 372 },
- { "TRCCCCTLR", 371 },
- { "TRCCIDCCTLR0", 527 },
- { "TRCCIDCCTLR1", 528 },
- { "TRCCIDCVR0", 511 },
- { "TRCCIDCVR1", 512 },
- { "TRCCIDCVR2", 513 },
- { "TRCCIDCVR3", 514 },
- { "TRCCIDCVR4", 515 },
- { "TRCCIDCVR5", 516 },
- { "TRCCIDCVR6", 517 },
- { "TRCCIDCVR7", 518 },
+ { "TRCAUXCTLR", 366 },
+ { "TRCBBCTLR", 373 },
+ { "TRCCCCTLR", 372 },
+ { "TRCCIDCCTLR0", 528 },
+ { "TRCCIDCCTLR1", 529 },
+ { "TRCCIDCVR0", 512 },
+ { "TRCCIDCVR1", 513 },
+ { "TRCCIDCVR2", 514 },
+ { "TRCCIDCVR3", 515 },
+ { "TRCCIDCVR4", 516 },
+ { "TRCCIDCVR5", 517 },
+ { "TRCCIDCVR6", 518 },
+ { "TRCCIDCVR7", 519 },
{ "TRCCIDR0", 84 },
{ "TRCCIDR1", 85 },
{ "TRCCIDR2", 86 },
{ "TRCCIDR3", 87 },
- { "TRCCLAIMCLR", 533 },
- { "TRCCLAIMSET", 532 },
- { "TRCCNTCTLR0", 392 },
- { "TRCCNTCTLR1", 393 },
- { "TRCCNTCTLR2", 394 },
- { "TRCCNTCTLR3", 395 },
- { "TRCCNTRLDVR0", 388 },
- { "TRCCNTRLDVR1", 389 },
- { "TRCCNTRLDVR2", 390 },
- { "TRCCNTRLDVR3", 391 },
- { "TRCCNTVR0", 396 },
- { "TRCCNTVR1", 397 },
- { "TRCCNTVR2", 398 },
- { "TRCCNTVR3", 399 },
- { "TRCCONFIGR", 364 },
+ { "TRCCLAIMCLR", 534 },
+ { "TRCCLAIMSET", 533 },
+ { "TRCCNTCTLR0", 393 },
+ { "TRCCNTCTLR1", 394 },
+ { "TRCCNTCTLR2", 395 },
+ { "TRCCNTCTLR3", 396 },
+ { "TRCCNTRLDVR0", 389 },
+ { "TRCCNTRLDVR1", 390 },
+ { "TRCCNTRLDVR2", 391 },
+ { "TRCCNTRLDVR3", 392 },
+ { "TRCCNTVR0", 397 },
+ { "TRCCNTVR1", 398 },
+ { "TRCCNTVR2", 399 },
+ { "TRCCNTVR3", 400 },
+ { "TRCCONFIGR", 365 },
{ "TRCDEVAFF0", 69 },
{ "TRCDEVAFF1", 70 },
{ "TRCDEVARCH", 73 },
{ "TRCDEVID", 74 },
{ "TRCDEVTYPE", 75 },
- { "TRCDVCMR0", 503 },
- { "TRCDVCMR1", 504 },
- { "TRCDVCMR2", 505 },
- { "TRCDVCMR3", 506 },
- { "TRCDVCMR4", 507 },
- { "TRCDVCMR5", 508 },
- { "TRCDVCMR6", 509 },
- { "TRCDVCMR7", 510 },
- { "TRCDVCVR0", 495 },
- { "TRCDVCVR1", 496 },
- { "TRCDVCVR2", 497 },
- { "TRCDVCVR3", 498 },
- { "TRCDVCVR4", 499 },
- { "TRCDVCVR5", 500 },
- { "TRCDVCVR6", 501 },
- { "TRCDVCVR7", 502 },
- { "TRCEVENTCTL0R", 366 },
- { "TRCEVENTCTL1R", 367 },
- { "TRCEXTINSELR", 387 },
+ { "TRCDVCMR0", 504 },
+ { "TRCDVCMR1", 505 },
+ { "TRCDVCMR2", 506 },
+ { "TRCDVCMR3", 507 },
+ { "TRCDVCMR4", 508 },
+ { "TRCDVCMR5", 509 },
+ { "TRCDVCMR6", 510 },
+ { "TRCDVCMR7", 511 },
+ { "TRCDVCVR0", 496 },
+ { "TRCDVCVR1", 497 },
+ { "TRCDVCVR2", 498 },
+ { "TRCDVCVR3", 499 },
+ { "TRCDVCVR4", 500 },
+ { "TRCDVCVR5", 501 },
+ { "TRCDVCVR6", 502 },
+ { "TRCDVCVR7", 503 },
+ { "TRCEVENTCTL0R", 367 },
+ { "TRCEVENTCTL1R", 368 },
+ { "TRCEXTINSELR", 388 },
{ "TRCIDR0", 59 },
{ "TRCIDR1", 60 },
{ "TRCIDR10", 55 },
@@ -3315,20 +3326,20 @@
{ "TRCIDR7", 66 },
{ "TRCIDR8", 53 },
{ "TRCIDR9", 54 },
- { "TRCIMSPEC0", 400 },
- { "TRCIMSPEC1", 401 },
- { "TRCIMSPEC2", 402 },
- { "TRCIMSPEC3", 403 },
- { "TRCIMSPEC4", 404 },
- { "TRCIMSPEC5", 405 },
- { "TRCIMSPEC6", 406 },
- { "TRCIMSPEC7", 407 },
- { "TRCITCTRL", 531 },
- { "TRCLAR", 103 },
+ { "TRCIMSPEC0", 401 },
+ { "TRCIMSPEC1", 402 },
+ { "TRCIMSPEC2", 403 },
+ { "TRCIMSPEC3", 404 },
+ { "TRCIMSPEC4", 405 },
+ { "TRCIMSPEC5", 406 },
+ { "TRCIMSPEC6", 407 },
+ { "TRCIMSPEC7", 408 },
+ { "TRCITCTRL", 532 },
+ { "TRCLAR", 104 },
{ "TRCLSR", 71 },
- { "TRCOSLAR", 102 },
+ { "TRCOSLAR", 103 },
{ "TRCOSLSR", 67 },
- { "TRCPDCR", 462 },
+ { "TRCPDCR", 463 },
{ "TRCPDSR", 68 },
{ "TRCPIDR0", 80 },
{ "TRCPIDR1", 81 },
@@ -3338,114 +3349,118 @@
{ "TRCPIDR5", 77 },
{ "TRCPIDR6", 78 },
{ "TRCPIDR7", 79 },
- { "TRCPRGCTLR", 362 },
- { "TRCPROCSELR", 363 },
- { "TRCQCTLR", 374 },
- { "TRCRSCTLR10", 416 },
- { "TRCRSCTLR11", 417 },
- { "TRCRSCTLR12", 418 },
- { "TRCRSCTLR13", 419 },
- { "TRCRSCTLR14", 420 },
- { "TRCRSCTLR15", 421 },
- { "TRCRSCTLR16", 422 },
- { "TRCRSCTLR17", 423 },
- { "TRCRSCTLR18", 424 },
- { "TRCRSCTLR19", 425 },
- { "TRCRSCTLR2", 408 },
- { "TRCRSCTLR20", 426 },
- { "TRCRSCTLR21", 427 },
- { "TRCRSCTLR22", 428 },
- { "TRCRSCTLR23", 429 },
- { "TRCRSCTLR24", 430 },
- { "TRCRSCTLR25", 431 },
- { "TRCRSCTLR26", 432 },
- { "TRCRSCTLR27", 433 },
- { "TRCRSCTLR28", 434 },
- { "TRCRSCTLR29", 435 },
- { "TRCRSCTLR3", 409 },
- { "TRCRSCTLR30", 436 },
- { "TRCRSCTLR31", 437 },
- { "TRCRSCTLR4", 410 },
- { "TRCRSCTLR5", 411 },
- { "TRCRSCTLR6", 412 },
- { "TRCRSCTLR7", 413 },
- { "TRCRSCTLR8", 414 },
- { "TRCRSCTLR9", 415 },
- { "TRCSEQEVR0", 382 },
- { "TRCSEQEVR1", 383 },
- { "TRCSEQEVR2", 384 },
- { "TRCSEQRSTEVR", 385 },
- { "TRCSEQSTR", 386 },
- { "TRCSSCCR0", 438 },
- { "TRCSSCCR1", 439 },
- { "TRCSSCCR2", 440 },
- { "TRCSSCCR3", 441 },
- { "TRCSSCCR4", 442 },
- { "TRCSSCCR5", 443 },
- { "TRCSSCCR6", 444 },
- { "TRCSSCCR7", 445 },
- { "TRCSSCSR0", 446 },
- { "TRCSSCSR1", 447 },
- { "TRCSSCSR2", 448 },
- { "TRCSSCSR3", 449 },
- { "TRCSSCSR4", 450 },
- { "TRCSSCSR5", 451 },
- { "TRCSSCSR6", 452 },
- { "TRCSSCSR7", 453 },
- { "TRCSSPCICR0", 454 },
- { "TRCSSPCICR1", 455 },
- { "TRCSSPCICR2", 456 },
- { "TRCSSPCICR3", 457 },
- { "TRCSSPCICR4", 458 },
- { "TRCSSPCICR5", 459 },
- { "TRCSSPCICR6", 460 },
- { "TRCSSPCICR7", 461 },
- { "TRCSTALLCTLR", 368 },
+ { "TRCPRGCTLR", 363 },
+ { "TRCPROCSELR", 364 },
+ { "TRCQCTLR", 375 },
+ { "TRCRSCTLR10", 417 },
+ { "TRCRSCTLR11", 418 },
+ { "TRCRSCTLR12", 419 },
+ { "TRCRSCTLR13", 420 },
+ { "TRCRSCTLR14", 421 },
+ { "TRCRSCTLR15", 422 },
+ { "TRCRSCTLR16", 423 },
+ { "TRCRSCTLR17", 424 },
+ { "TRCRSCTLR18", 425 },
+ { "TRCRSCTLR19", 426 },
+ { "TRCRSCTLR2", 409 },
+ { "TRCRSCTLR20", 427 },
+ { "TRCRSCTLR21", 428 },
+ { "TRCRSCTLR22", 429 },
+ { "TRCRSCTLR23", 430 },
+ { "TRCRSCTLR24", 431 },
+ { "TRCRSCTLR25", 432 },
+ { "TRCRSCTLR26", 433 },
+ { "TRCRSCTLR27", 434 },
+ { "TRCRSCTLR28", 435 },
+ { "TRCRSCTLR29", 436 },
+ { "TRCRSCTLR3", 410 },
+ { "TRCRSCTLR30", 437 },
+ { "TRCRSCTLR31", 438 },
+ { "TRCRSCTLR4", 411 },
+ { "TRCRSCTLR5", 412 },
+ { "TRCRSCTLR6", 413 },
+ { "TRCRSCTLR7", 414 },
+ { "TRCRSCTLR8", 415 },
+ { "TRCRSCTLR9", 416 },
+ { "TRCSEQEVR0", 383 },
+ { "TRCSEQEVR1", 384 },
+ { "TRCSEQEVR2", 385 },
+ { "TRCSEQRSTEVR", 386 },
+ { "TRCSEQSTR", 387 },
+ { "TRCSSCCR0", 439 },
+ { "TRCSSCCR1", 440 },
+ { "TRCSSCCR2", 441 },
+ { "TRCSSCCR3", 442 },
+ { "TRCSSCCR4", 443 },
+ { "TRCSSCCR5", 444 },
+ { "TRCSSCCR6", 445 },
+ { "TRCSSCCR7", 446 },
+ { "TRCSSCSR0", 447 },
+ { "TRCSSCSR1", 448 },
+ { "TRCSSCSR2", 449 },
+ { "TRCSSCSR3", 450 },
+ { "TRCSSCSR4", 451 },
+ { "TRCSSCSR5", 452 },
+ { "TRCSSCSR6", 453 },
+ { "TRCSSCSR7", 454 },
+ { "TRCSSPCICR0", 455 },
+ { "TRCSSPCICR1", 456 },
+ { "TRCSSPCICR2", 457 },
+ { "TRCSSPCICR3", 458 },
+ { "TRCSSPCICR4", 459 },
+ { "TRCSSPCICR5", 460 },
+ { "TRCSSPCICR6", 461 },
+ { "TRCSSPCICR7", 462 },
+ { "TRCSTALLCTLR", 369 },
{ "TRCSTATR", 52 },
- { "TRCSYNCPR", 370 },
- { "TRCTRACEIDR", 373 },
- { "TRCTSCTLR", 369 },
- { "TRCVDARCCTLR", 381 },
- { "TRCVDCTLR", 379 },
- { "TRCVDSACCTLR", 380 },
- { "TRCVICTLR", 375 },
- { "TRCVIIECTLR", 376 },
- { "TRCVIPCSSCTLR", 378 },
- { "TRCVISSCTLR", 377 },
- { "TRCVMIDCCTLR0", 529 },
- { "TRCVMIDCCTLR1", 530 },
- { "TRCVMIDCVR0", 519 },
- { "TRCVMIDCVR1", 520 },
- { "TRCVMIDCVR2", 521 },
- { "TRCVMIDCVR3", 522 },
- { "TRCVMIDCVR4", 523 },
- { "TRCVMIDCVR5", 524 },
- { "TRCVMIDCVR6", 525 },
- { "TRCVMIDCVR7", 526 },
- { "TRFCR_EL1", 726 },
- { "TRFCR_EL12", 728 },
- { "TRFCR_EL2", 727 },
- { "TTBR0_EL1", 206 },
- { "TTBR0_EL12", 594 },
- { "TTBR0_EL2", 207 },
- { "TTBR0_EL3", 208 },
- { "TTBR1_EL1", 209 },
- { "TTBR1_EL12", 595 },
- { "TTBR1_EL2", 587 },
- { "UAO", 614 },
- { "VBAR_EL1", 271 },
- { "VBAR_EL12", 603 },
- { "VBAR_EL2", 272 },
- { "VBAR_EL3", 273 },
- { "VDISR_EL2", 635 },
- { "VMPIDR_EL2", 189 },
- { "VNCR_EL2", 730 },
- { "VPIDR_EL2", 188 },
- { "VSESR_EL2", 636 },
- { "VSTCR_EL2", 647 },
- { "VSTTBR_EL2", 648 },
- { "VTCR_EL2", 214 },
- { "VTTBR_EL2", 213 },
+ { "TRCSYNCPR", 371 },
+ { "TRCTRACEIDR", 374 },
+ { "TRCTSCTLR", 370 },
+ { "TRCVDARCCTLR", 382 },
+ { "TRCVDCTLR", 380 },
+ { "TRCVDSACCTLR", 381 },
+ { "TRCVICTLR", 376 },
+ { "TRCVIIECTLR", 377 },
+ { "TRCVIPCSSCTLR", 379 },
+ { "TRCVISSCTLR", 378 },
+ { "TRCVMIDCCTLR0", 530 },
+ { "TRCVMIDCCTLR1", 531 },
+ { "TRCVMIDCVR0", 520 },
+ { "TRCVMIDCVR1", 521 },
+ { "TRCVMIDCVR2", 522 },
+ { "TRCVMIDCVR3", 523 },
+ { "TRCVMIDCVR4", 524 },
+ { "TRCVMIDCVR5", 525 },
+ { "TRCVMIDCVR6", 526 },
+ { "TRCVMIDCVR7", 527 },
+ { "TRFCR_EL1", 727 },
+ { "TRFCR_EL12", 729 },
+ { "TRFCR_EL2", 728 },
+ { "TTBR0_EL1", 207 },
+ { "TTBR0_EL12", 595 },
+ { "TTBR0_EL2", 208 },
+ { "TTBR0_EL3", 209 },
+ { "TTBR1_EL1", 210 },
+ { "TTBR1_EL12", 596 },
+ { "TTBR1_EL2", 588 },
+ { "UAO", 615 },
+ { "VBAR_EL1", 272 },
+ { "VBAR_EL12", 604 },
+ { "VBAR_EL2", 273 },
+ { "VBAR_EL3", 274 },
+ { "VDISR_EL2", 636 },
+ { "VMPIDR_EL2", 190 },
+ { "VNCR_EL2", 731 },
+ { "VPIDR_EL2", 189 },
+ { "VSESR_EL2", 637 },
+ { "VSTCR_EL2", 648 },
+ { "VSTTBR_EL2", 649 },
+ { "VTCR_EL2", 215 },
+ { "VTTBR_EL2", 214 },
+ { "ZCR_EL1", 732 },
+ { "ZCR_EL12", 735 },
+ { "ZCR_EL2", 733 },
+ { "ZCR_EL3", 734 },
};
struct KeyType {
@@ -3473,286 +3488,286 @@
unsigned _index;
};
static const struct IndexType Index[] = {
- { 0x8002, 110 },
- { 0x8004, 118 },
- { 0x8005, 134 },
- { 0x8006, 150 },
- { 0x8007, 166 },
- { 0x800C, 119 },
- { 0x800D, 135 },
- { 0x800E, 151 },
- { 0x800F, 167 },
- { 0x8010, 113 },
- { 0x8012, 114 },
- { 0x8014, 120 },
- { 0x8015, 136 },
- { 0x8016, 152 },
- { 0x8017, 168 },
- { 0x801A, 111 },
- { 0x801C, 121 },
- { 0x801D, 137 },
- { 0x801E, 153 },
- { 0x801F, 169 },
- { 0x8024, 122 },
- { 0x8025, 138 },
- { 0x8026, 154 },
- { 0x8027, 170 },
- { 0x802C, 123 },
- { 0x802D, 139 },
- { 0x802E, 155 },
- { 0x802F, 171 },
- { 0x8032, 116 },
- { 0x8034, 124 },
- { 0x8035, 140 },
- { 0x8036, 156 },
- { 0x8037, 172 },
- { 0x803C, 125 },
- { 0x803D, 141 },
- { 0x803E, 157 },
- { 0x803F, 173 },
- { 0x8044, 126 },
- { 0x8045, 142 },
- { 0x8046, 158 },
- { 0x8047, 174 },
- { 0x804C, 127 },
- { 0x804D, 143 },
- { 0x804E, 159 },
- { 0x804F, 175 },
- { 0x8054, 128 },
- { 0x8055, 144 },
- { 0x8056, 160 },
- { 0x8057, 176 },
- { 0x805C, 129 },
- { 0x805D, 145 },
- { 0x805E, 161 },
- { 0x805F, 177 },
- { 0x8064, 130 },
- { 0x8065, 146 },
- { 0x8066, 162 },
- { 0x8067, 178 },
- { 0x806C, 131 },
- { 0x806D, 147 },
- { 0x806E, 163 },
- { 0x806F, 179 },
- { 0x8074, 132 },
- { 0x8075, 148 },
- { 0x8076, 164 },
- { 0x8077, 180 },
- { 0x807C, 133 },
- { 0x807D, 149 },
- { 0x807E, 165 },
- { 0x807F, 181 },
+ { 0x8002, 111 },
+ { 0x8004, 119 },
+ { 0x8005, 135 },
+ { 0x8006, 151 },
+ { 0x8007, 167 },
+ { 0x800C, 120 },
+ { 0x800D, 136 },
+ { 0x800E, 152 },
+ { 0x800F, 168 },
+ { 0x8010, 114 },
+ { 0x8012, 115 },
+ { 0x8014, 121 },
+ { 0x8015, 137 },
+ { 0x8016, 153 },
+ { 0x8017, 169 },
+ { 0x801A, 112 },
+ { 0x801C, 122 },
+ { 0x801D, 138 },
+ { 0x801E, 154 },
+ { 0x801F, 170 },
+ { 0x8024, 123 },
+ { 0x8025, 139 },
+ { 0x8026, 155 },
+ { 0x8027, 171 },
+ { 0x802C, 124 },
+ { 0x802D, 140 },
+ { 0x802E, 156 },
+ { 0x802F, 172 },
+ { 0x8032, 117 },
+ { 0x8034, 125 },
+ { 0x8035, 141 },
+ { 0x8036, 157 },
+ { 0x8037, 173 },
+ { 0x803C, 126 },
+ { 0x803D, 142 },
+ { 0x803E, 158 },
+ { 0x803F, 174 },
+ { 0x8044, 127 },
+ { 0x8045, 143 },
+ { 0x8046, 159 },
+ { 0x8047, 175 },
+ { 0x804C, 128 },
+ { 0x804D, 144 },
+ { 0x804E, 160 },
+ { 0x804F, 176 },
+ { 0x8054, 129 },
+ { 0x8055, 145 },
+ { 0x8056, 161 },
+ { 0x8057, 177 },
+ { 0x805C, 130 },
+ { 0x805D, 146 },
+ { 0x805E, 162 },
+ { 0x805F, 178 },
+ { 0x8064, 131 },
+ { 0x8065, 147 },
+ { 0x8066, 163 },
+ { 0x8067, 179 },
+ { 0x806C, 132 },
+ { 0x806D, 148 },
+ { 0x806E, 164 },
+ { 0x806F, 180 },
+ { 0x8074, 133 },
+ { 0x8075, 149 },
+ { 0x8076, 165 },
+ { 0x8077, 181 },
+ { 0x807C, 134 },
+ { 0x807D, 150 },
+ { 0x807E, 166 },
+ { 0x807F, 182 },
{ 0x8080, 2 },
- { 0x8084, 100 },
+ { 0x8084, 101 },
{ 0x808C, 3 },
- { 0x809C, 183 },
- { 0x80A4, 184 },
- { 0x83C6, 185 },
- { 0x83CE, 186 },
+ { 0x809C, 184 },
+ { 0x80A4, 185 },
+ { 0x83C6, 186 },
+ { 0x83CE, 187 },
{ 0x83F6, 4 },
- { 0x8801, 373 },
- { 0x8802, 375 },
- { 0x8804, 382 },
- { 0x8805, 388 },
+ { 0x8801, 374 },
+ { 0x8802, 376 },
+ { 0x8804, 383 },
+ { 0x8805, 389 },
{ 0x8806, 53 },
- { 0x8807, 400 },
- { 0x8808, 362 },
- { 0x8809, 374 },
- { 0x880A, 376 },
- { 0x880C, 383 },
- { 0x880D, 389 },
+ { 0x8807, 401 },
+ { 0x8808, 363 },
+ { 0x8809, 375 },
+ { 0x880A, 377 },
+ { 0x880C, 384 },
+ { 0x880D, 390 },
{ 0x880E, 54 },
- { 0x880F, 401 },
- { 0x8810, 363 },
- { 0x8812, 377 },
- { 0x8814, 384 },
- { 0x8815, 390 },
+ { 0x880F, 402 },
+ { 0x8810, 364 },
+ { 0x8812, 378 },
+ { 0x8814, 385 },
+ { 0x8815, 391 },
{ 0x8816, 55 },
- { 0x8817, 402 },
+ { 0x8817, 403 },
{ 0x8818, 52 },
- { 0x881A, 378 },
- { 0x881D, 391 },
+ { 0x881A, 379 },
+ { 0x881D, 392 },
{ 0x881E, 56 },
- { 0x881F, 403 },
- { 0x8820, 364 },
- { 0x8825, 392 },
+ { 0x881F, 404 },
+ { 0x8820, 365 },
+ { 0x8825, 393 },
{ 0x8826, 57 },
- { 0x8827, 404 },
- { 0x882D, 393 },
+ { 0x8827, 405 },
+ { 0x882D, 394 },
{ 0x882E, 58 },
- { 0x882F, 405 },
- { 0x8830, 365 },
- { 0x8834, 385 },
- { 0x8835, 394 },
- { 0x8837, 406 },
- { 0x883C, 386 },
- { 0x883D, 395 },
- { 0x883F, 407 },
- { 0x8840, 366 },
- { 0x8842, 379 },
- { 0x8844, 387 },
- { 0x8845, 396 },
+ { 0x882F, 406 },
+ { 0x8830, 366 },
+ { 0x8834, 386 },
+ { 0x8835, 395 },
+ { 0x8837, 407 },
+ { 0x883C, 387 },
+ { 0x883D, 396 },
+ { 0x883F, 408 },
+ { 0x8840, 367 },
+ { 0x8842, 380 },
+ { 0x8844, 388 },
+ { 0x8845, 397 },
{ 0x8847, 59 },
- { 0x8848, 367 },
- { 0x884A, 380 },
- { 0x884D, 397 },
+ { 0x8848, 368 },
+ { 0x884A, 381 },
+ { 0x884D, 398 },
{ 0x884F, 60 },
- { 0x8852, 381 },
- { 0x8855, 398 },
+ { 0x8852, 382 },
+ { 0x8855, 399 },
{ 0x8857, 61 },
- { 0x8858, 368 },
- { 0x885D, 399 },
+ { 0x8858, 369 },
+ { 0x885D, 400 },
{ 0x885F, 62 },
- { 0x8860, 369 },
+ { 0x8860, 370 },
{ 0x8867, 63 },
- { 0x8868, 370 },
+ { 0x8868, 371 },
{ 0x886F, 64 },
- { 0x8870, 371 },
+ { 0x8870, 372 },
{ 0x8877, 65 },
- { 0x8878, 372 },
+ { 0x8878, 373 },
{ 0x887F, 66 },
- { 0x8881, 422 },
- { 0x8882, 438 },
- { 0x8883, 454 },
- { 0x8884, 102 },
- { 0x8889, 423 },
- { 0x888A, 439 },
- { 0x888B, 455 },
+ { 0x8881, 423 },
+ { 0x8882, 439 },
+ { 0x8883, 455 },
+ { 0x8884, 103 },
+ { 0x8889, 424 },
+ { 0x888A, 440 },
+ { 0x888B, 456 },
{ 0x888C, 67 },
- { 0x8890, 408 },
- { 0x8891, 424 },
- { 0x8892, 440 },
- { 0x8893, 456 },
- { 0x8898, 409 },
- { 0x8899, 425 },
- { 0x889A, 441 },
- { 0x889B, 457 },
- { 0x88A0, 410 },
- { 0x88A1, 426 },
- { 0x88A2, 442 },
- { 0x88A3, 458 },
- { 0x88A4, 462 },
- { 0x88A8, 411 },
- { 0x88A9, 427 },
- { 0x88AA, 443 },
- { 0x88AB, 459 },
+ { 0x8890, 409 },
+ { 0x8891, 425 },
+ { 0x8892, 441 },
+ { 0x8893, 457 },
+ { 0x8898, 410 },
+ { 0x8899, 426 },
+ { 0x889A, 442 },
+ { 0x889B, 458 },
+ { 0x88A0, 411 },
+ { 0x88A1, 427 },
+ { 0x88A2, 443 },
+ { 0x88A3, 459 },
+ { 0x88A4, 463 },
+ { 0x88A8, 412 },
+ { 0x88A9, 428 },
+ { 0x88AA, 444 },
+ { 0x88AB, 460 },
{ 0x88AC, 68 },
- { 0x88B0, 412 },
- { 0x88B1, 428 },
- { 0x88B2, 444 },
- { 0x88B3, 460 },
- { 0x88B8, 413 },
- { 0x88B9, 429 },
- { 0x88BA, 445 },
- { 0x88BB, 461 },
- { 0x88C0, 414 },
- { 0x88C1, 430 },
- { 0x88C2, 446 },
- { 0x88C8, 415 },
- { 0x88C9, 431 },
- { 0x88CA, 447 },
- { 0x88D0, 416 },
- { 0x88D1, 432 },
- { 0x88D2, 448 },
- { 0x88D8, 417 },
- { 0x88D9, 433 },
- { 0x88DA, 449 },
- { 0x88E0, 418 },
- { 0x88E1, 434 },
- { 0x88E2, 450 },
- { 0x88E8, 419 },
- { 0x88E9, 435 },
- { 0x88EA, 451 },
- { 0x88F0, 420 },
- { 0x88F1, 436 },
- { 0x88F2, 452 },
- { 0x88F8, 421 },
- { 0x88F9, 437 },
- { 0x88FA, 453 },
- { 0x8900, 463 },
- { 0x8901, 471 },
- { 0x8902, 479 },
- { 0x8903, 487 },
- { 0x8904, 495 },
- { 0x8905, 499 },
- { 0x8906, 503 },
- { 0x8907, 507 },
- { 0x8910, 464 },
- { 0x8911, 472 },
- { 0x8912, 480 },
- { 0x8913, 488 },
- { 0x8920, 465 },
- { 0x8921, 473 },
- { 0x8922, 481 },
- { 0x8923, 489 },
- { 0x8924, 496 },
- { 0x8925, 500 },
- { 0x8926, 504 },
- { 0x8927, 508 },
- { 0x8930, 466 },
- { 0x8931, 474 },
- { 0x8932, 482 },
- { 0x8933, 490 },
- { 0x8940, 467 },
- { 0x8941, 475 },
- { 0x8942, 483 },
- { 0x8943, 491 },
- { 0x8944, 497 },
- { 0x8945, 501 },
- { 0x8946, 505 },
- { 0x8947, 509 },
- { 0x8950, 468 },
- { 0x8951, 476 },
- { 0x8952, 484 },
- { 0x8953, 492 },
- { 0x8960, 469 },
- { 0x8961, 477 },
- { 0x8962, 485 },
- { 0x8963, 493 },
- { 0x8964, 498 },
- { 0x8965, 502 },
- { 0x8966, 506 },
- { 0x8967, 510 },
- { 0x8970, 470 },
- { 0x8971, 478 },
- { 0x8972, 486 },
- { 0x8973, 494 },
- { 0x8980, 511 },
- { 0x8981, 519 },
- { 0x8982, 527 },
- { 0x898A, 528 },
- { 0x8990, 512 },
- { 0x8991, 520 },
- { 0x8992, 529 },
- { 0x899A, 530 },
- { 0x89A0, 513 },
- { 0x89A1, 521 },
- { 0x89B0, 514 },
- { 0x89B1, 522 },
- { 0x89C0, 515 },
- { 0x89C1, 523 },
- { 0x89D0, 516 },
- { 0x89D1, 524 },
- { 0x89E0, 517 },
- { 0x89E1, 525 },
- { 0x89F0, 518 },
- { 0x89F1, 526 },
- { 0x8B84, 531 },
+ { 0x88B0, 413 },
+ { 0x88B1, 429 },
+ { 0x88B2, 445 },
+ { 0x88B3, 461 },
+ { 0x88B8, 414 },
+ { 0x88B9, 430 },
+ { 0x88BA, 446 },
+ { 0x88BB, 462 },
+ { 0x88C0, 415 },
+ { 0x88C1, 431 },
+ { 0x88C2, 447 },
+ { 0x88C8, 416 },
+ { 0x88C9, 432 },
+ { 0x88CA, 448 },
+ { 0x88D0, 417 },
+ { 0x88D1, 433 },
+ { 0x88D2, 449 },
+ { 0x88D8, 418 },
+ { 0x88D9, 434 },
+ { 0x88DA, 450 },
+ { 0x88E0, 419 },
+ { 0x88E1, 435 },
+ { 0x88E2, 451 },
+ { 0x88E8, 420 },
+ { 0x88E9, 436 },
+ { 0x88EA, 452 },
+ { 0x88F0, 421 },
+ { 0x88F1, 437 },
+ { 0x88F2, 453 },
+ { 0x88F8, 422 },
+ { 0x88F9, 438 },
+ { 0x88FA, 454 },
+ { 0x8900, 464 },
+ { 0x8901, 472 },
+ { 0x8902, 480 },
+ { 0x8903, 488 },
+ { 0x8904, 496 },
+ { 0x8905, 500 },
+ { 0x8906, 504 },
+ { 0x8907, 508 },
+ { 0x8910, 465 },
+ { 0x8911, 473 },
+ { 0x8912, 481 },
+ { 0x8913, 489 },
+ { 0x8920, 466 },
+ { 0x8921, 474 },
+ { 0x8922, 482 },
+ { 0x8923, 490 },
+ { 0x8924, 497 },
+ { 0x8925, 501 },
+ { 0x8926, 505 },
+ { 0x8927, 509 },
+ { 0x8930, 467 },
+ { 0x8931, 475 },
+ { 0x8932, 483 },
+ { 0x8933, 491 },
+ { 0x8940, 468 },
+ { 0x8941, 476 },
+ { 0x8942, 484 },
+ { 0x8943, 492 },
+ { 0x8944, 498 },
+ { 0x8945, 502 },
+ { 0x8946, 506 },
+ { 0x8947, 510 },
+ { 0x8950, 469 },
+ { 0x8951, 477 },
+ { 0x8952, 485 },
+ { 0x8953, 493 },
+ { 0x8960, 470 },
+ { 0x8961, 478 },
+ { 0x8962, 486 },
+ { 0x8963, 494 },
+ { 0x8964, 499 },
+ { 0x8965, 503 },
+ { 0x8966, 507 },
+ { 0x8967, 511 },
+ { 0x8970, 471 },
+ { 0x8971, 479 },
+ { 0x8972, 487 },
+ { 0x8973, 495 },
+ { 0x8980, 512 },
+ { 0x8981, 520 },
+ { 0x8982, 528 },
+ { 0x898A, 529 },
+ { 0x8990, 513 },
+ { 0x8991, 521 },
+ { 0x8992, 530 },
+ { 0x899A, 531 },
+ { 0x89A0, 514 },
+ { 0x89A1, 522 },
+ { 0x89B0, 515 },
+ { 0x89B1, 523 },
+ { 0x89C0, 516 },
+ { 0x89C1, 524 },
+ { 0x89D0, 517 },
+ { 0x89D1, 525 },
+ { 0x89E0, 518 },
+ { 0x89E1, 526 },
+ { 0x89F0, 519 },
+ { 0x89F1, 527 },
+ { 0x8B84, 532 },
{ 0x8B97, 74 },
{ 0x8B9F, 75 },
{ 0x8BA7, 76 },
{ 0x8BAF, 77 },
{ 0x8BB7, 78 },
{ 0x8BBF, 79 },
- { 0x8BC6, 532 },
+ { 0x8BC6, 533 },
{ 0x8BC7, 80 },
- { 0x8BCE, 533 },
+ { 0x8BCE, 534 },
{ 0x8BCF, 81 },
{ 0x8BD6, 69 },
{ 0x8BD7, 82 },
{ 0x8BDE, 70 },
{ 0x8BDF, 83 },
- { 0x8BE6, 103 },
+ { 0x8BE6, 104 },
{ 0x8BE7, 84 },
{ 0x8BEE, 71 },
{ 0x8BEF, 85 },
@@ -3760,13 +3775,13 @@
{ 0x8BF7, 86 },
{ 0x8BFE, 73 },
{ 0x8BFF, 87 },
- { 0x9000, 112 },
- { 0x9080, 182 },
+ { 0x9000, 113 },
+ { 0x9080, 183 },
{ 0x9808, 0 },
- { 0x9820, 115 },
+ { 0x9820, 116 },
{ 0x9828, 1 },
- { 0x9828, 99 },
- { 0xA038, 117 },
+ { 0x9828, 100 },
+ { 0xA038, 118 },
{ 0xC000, 7 },
{ 0xC005, 12 },
{ 0xC006, 13 },
@@ -3791,6 +3806,7 @@
{ 0xC01A, 44 },
{ 0xC020, 31 },
{ 0xC021, 32 },
+ { 0xC024, 96 },
{ 0xC028, 33 },
{ 0xC029, 34 },
{ 0xC02C, 35 },
@@ -3800,411 +3816,415 @@
{ 0xC038, 39 },
{ 0xC039, 40 },
{ 0xC03A, 41 },
- { 0xC080, 191 },
- { 0xC081, 194 },
- { 0xC082, 190 },
- { 0xC091, 726 },
- { 0xC100, 206 },
- { 0xC101, 209 },
- { 0xC102, 210 },
- { 0xC108, 637 },
- { 0xC109, 638 },
- { 0xC10A, 639 },
- { 0xC10B, 640 },
- { 0xC110, 641 },
- { 0xC111, 642 },
- { 0xC112, 643 },
- { 0xC113, 644 },
- { 0xC118, 645 },
- { 0xC119, 646 },
- { 0xC200, 216 },
- { 0xC201, 219 },
- { 0xC208, 222 },
- { 0xC210, 225 },
- { 0xC212, 228 },
- { 0xC213, 582 },
- { 0xC214, 614 },
- { 0xC230, 536 },
- { 0xC288, 238 },
- { 0xC289, 241 },
- { 0xC290, 244 },
- { 0xC298, 97 },
- { 0xC299, 628 },
- { 0xC2A0, 98 },
- { 0xC2A1, 629 },
- { 0xC2A2, 630 },
- { 0xC2A3, 631 },
- { 0xC2A4, 661 },
- { 0xC2A5, 656 },
- { 0xC2A6, 657 },
- { 0xC2A8, 632 },
- { 0xC2A9, 633 },
- { 0xC2AA, 659 },
- { 0xC2AB, 660 },
- { 0xC2AF, 658 },
- { 0xC300, 248 },
- { 0xC3A0, 252 },
- { 0xC4C8, 621 },
- { 0xC4CA, 622 },
- { 0xC4CB, 623 },
- { 0xC4CC, 624 },
- { 0xC4CD, 625 },
- { 0xC4CE, 626 },
- { 0xC4CF, 627 },
- { 0xC4D0, 615 },
- { 0xC4D1, 616 },
- { 0xC4D3, 617 },
- { 0xC4D7, 618 },
- { 0xC4F1, 262 },
- { 0xC4F2, 263 },
- { 0xC510, 265 },
- { 0xC518, 268 },
- { 0xC520, 583 },
- { 0xC521, 584 },
- { 0xC522, 585 },
- { 0xC523, 586 },
- { 0xC524, 677 },
- { 0xC527, 96 },
- { 0xC528, 663 },
- { 0xC529, 662 },
- { 0xC600, 271 },
+ { 0xC080, 192 },
+ { 0xC081, 195 },
+ { 0xC082, 191 },
+ { 0xC090, 732 },
+ { 0xC091, 727 },
+ { 0xC100, 207 },
+ { 0xC101, 210 },
+ { 0xC102, 211 },
+ { 0xC108, 638 },
+ { 0xC109, 639 },
+ { 0xC10A, 640 },
+ { 0xC10B, 641 },
+ { 0xC110, 642 },
+ { 0xC111, 643 },
+ { 0xC112, 644 },
+ { 0xC113, 645 },
+ { 0xC118, 646 },
+ { 0xC119, 647 },
+ { 0xC200, 217 },
+ { 0xC201, 220 },
+ { 0xC208, 223 },
+ { 0xC210, 226 },
+ { 0xC212, 229 },
+ { 0xC213, 583 },
+ { 0xC214, 615 },
+ { 0xC230, 537 },
+ { 0xC288, 239 },
+ { 0xC289, 242 },
+ { 0xC290, 245 },
+ { 0xC298, 98 },
+ { 0xC299, 629 },
+ { 0xC2A0, 99 },
+ { 0xC2A1, 630 },
+ { 0xC2A2, 631 },
+ { 0xC2A3, 632 },
+ { 0xC2A4, 662 },
+ { 0xC2A5, 657 },
+ { 0xC2A6, 658 },
+ { 0xC2A8, 633 },
+ { 0xC2A9, 634 },
+ { 0xC2AA, 660 },
+ { 0xC2AB, 661 },
+ { 0xC2AF, 659 },
+ { 0xC300, 249 },
+ { 0xC3A0, 253 },
+ { 0xC4C8, 622 },
+ { 0xC4CA, 623 },
+ { 0xC4CB, 624 },
+ { 0xC4CC, 625 },
+ { 0xC4CD, 626 },
+ { 0xC4CE, 627 },
+ { 0xC4CF, 628 },
+ { 0xC4D0, 616 },
+ { 0xC4D1, 617 },
+ { 0xC4D3, 618 },
+ { 0xC4D7, 619 },
+ { 0xC4F1, 263 },
+ { 0xC4F2, 264 },
+ { 0xC510, 266 },
+ { 0xC518, 269 },
+ { 0xC520, 584 },
+ { 0xC521, 585 },
+ { 0xC522, 586 },
+ { 0xC523, 587 },
+ { 0xC524, 678 },
+ { 0xC527, 97 },
+ { 0xC528, 664 },
+ { 0xC529, 663 },
+ { 0xC600, 272 },
{ 0xC601, 45 },
- { 0xC602, 274 },
+ { 0xC602, 275 },
{ 0xC608, 48 },
- { 0xC609, 634 },
+ { 0xC609, 635 },
{ 0xC640, 89 },
- { 0xC641, 105 },
+ { 0xC641, 106 },
{ 0xC642, 91 },
- { 0xC643, 535 },
- { 0xC644, 546 },
- { 0xC645, 547 },
- { 0xC646, 548 },
- { 0xC647, 549 },
- { 0xC648, 550 },
- { 0xC649, 551 },
- { 0xC64A, 552 },
- { 0xC64B, 553 },
- { 0xC659, 106 },
+ { 0xC643, 536 },
+ { 0xC644, 547 },
+ { 0xC645, 548 },
+ { 0xC646, 549 },
+ { 0xC647, 550 },
+ { 0xC648, 551 },
+ { 0xC649, 552 },
+ { 0xC64A, 553 },
+ { 0xC64B, 554 },
+ { 0xC659, 107 },
{ 0xC65B, 92 },
- { 0xC65D, 107 },
- { 0xC65E, 108 },
- { 0xC65F, 109 },
+ { 0xC65D, 108 },
+ { 0xC65E, 109 },
+ { 0xC65F, 110 },
{ 0xC660, 88 },
- { 0xC661, 104 },
+ { 0xC661, 105 },
{ 0xC662, 90 },
- { 0xC663, 534 },
- { 0xC664, 537 },
- { 0xC665, 539 },
- { 0xC666, 542 },
- { 0xC667, 543 },
- { 0xC668, 545 },
- { 0xC681, 277 },
- { 0xC684, 282 },
- { 0xC708, 285 },
+ { 0xC663, 535 },
+ { 0xC664, 538 },
+ { 0xC665, 540 },
+ { 0xC666, 543 },
+ { 0xC667, 544 },
+ { 0xC668, 546 },
+ { 0xC681, 278 },
+ { 0xC684, 283 },
+ { 0xC708, 286 },
{ 0xC800, 8 },
{ 0xC801, 10 },
{ 0xC802, 9 },
{ 0xC807, 14 },
- { 0xD000, 187 },
+ { 0xD000, 188 },
{ 0xD801, 11 },
{ 0xD807, 15 },
- { 0xDA10, 226 },
- { 0xDA11, 227 },
- { 0xDA15, 729 },
- { 0xDA20, 233 },
- { 0xDA21, 234 },
- { 0xDA28, 235 },
- { 0xDA29, 236 },
- { 0xDCE0, 253 },
- { 0xDCE1, 254 },
- { 0xDCE2, 255 },
- { 0xDCE3, 256 },
- { 0xDCE4, 101 },
- { 0xDCE5, 257 },
+ { 0xDA10, 227 },
+ { 0xDA11, 228 },
+ { 0xDA15, 730 },
+ { 0xDA20, 234 },
+ { 0xDA21, 235 },
+ { 0xDA28, 236 },
+ { 0xDA29, 237 },
+ { 0xDCE0, 254 },
+ { 0xDCE1, 255 },
+ { 0xDCE2, 256 },
+ { 0xDCE3, 257 },
+ { 0xDCE4, 102 },
+ { 0xDCE5, 258 },
{ 0xDCE6, 5 },
{ 0xDCE7, 6 },
- { 0xDCE8, 258 },
- { 0xDCE9, 259 },
- { 0xDCEA, 260 },
- { 0xDCF0, 261 },
- { 0xDCF3, 264 },
- { 0xDE82, 278 },
- { 0xDE83, 281 },
- { 0xDE90, 678 },
- { 0xDE91, 679 },
- { 0xDE92, 680 },
- { 0xDE93, 681 },
- { 0xDE94, 682 },
- { 0xDE95, 683 },
- { 0xDE98, 692 },
- { 0xDE99, 693 },
- { 0xDEA0, 684 },
- { 0xDEA1, 685 },
- { 0xDEA2, 686 },
- { 0xDEA3, 687 },
- { 0xDEB0, 688 },
- { 0xDEB1, 689 },
- { 0xDEB2, 690 },
- { 0xDEB3, 691 },
- { 0xDEE0, 694 },
- { 0xDEE1, 695 },
- { 0xDEE2, 696 },
- { 0xDEE3, 697 },
- { 0xDEE4, 698 },
- { 0xDEE5, 699 },
- { 0xDEE6, 700 },
- { 0xDEE7, 701 },
- { 0xDEE8, 702 },
- { 0xDEE9, 703 },
- { 0xDEEA, 704 },
- { 0xDEEB, 705 },
- { 0xDEEC, 706 },
- { 0xDEED, 707 },
- { 0xDEEE, 708 },
- { 0xDEEF, 709 },
- { 0xDEF0, 710 },
- { 0xDEF1, 711 },
- { 0xDEF2, 712 },
- { 0xDEF3, 713 },
- { 0xDEF4, 714 },
- { 0xDEF5, 715 },
- { 0xDEF6, 716 },
- { 0xDEF7, 717 },
- { 0xDEF8, 718 },
- { 0xDEF9, 719 },
- { 0xDEFA, 720 },
- { 0xDEFB, 721 },
- { 0xDEFC, 722 },
- { 0xDEFD, 723 },
- { 0xDEFE, 724 },
- { 0xDEFF, 725 },
- { 0xDF00, 283 },
+ { 0xDCE8, 259 },
+ { 0xDCE9, 260 },
+ { 0xDCEA, 261 },
+ { 0xDCF0, 262 },
+ { 0xDCF3, 265 },
+ { 0xDE82, 279 },
+ { 0xDE83, 282 },
+ { 0xDE90, 679 },
+ { 0xDE91, 680 },
+ { 0xDE92, 681 },
+ { 0xDE93, 682 },
+ { 0xDE94, 683 },
+ { 0xDE95, 684 },
+ { 0xDE98, 693 },
+ { 0xDE99, 694 },
+ { 0xDEA0, 685 },
+ { 0xDEA1, 686 },
+ { 0xDEA2, 687 },
+ { 0xDEA3, 688 },
+ { 0xDEB0, 689 },
+ { 0xDEB1, 690 },
+ { 0xDEB2, 691 },
+ { 0xDEB3, 692 },
+ { 0xDEE0, 695 },
+ { 0xDEE1, 696 },
+ { 0xDEE2, 697 },
+ { 0xDEE3, 698 },
+ { 0xDEE4, 699 },
+ { 0xDEE5, 700 },
+ { 0xDEE6, 701 },
+ { 0xDEE7, 702 },
+ { 0xDEE8, 703 },
+ { 0xDEE9, 704 },
+ { 0xDEEA, 705 },
+ { 0xDEEB, 706 },
+ { 0xDEEC, 707 },
+ { 0xDEED, 708 },
+ { 0xDEEE, 709 },
+ { 0xDEEF, 710 },
+ { 0xDEF0, 711 },
+ { 0xDEF1, 712 },
+ { 0xDEF2, 713 },
+ { 0xDEF3, 714 },
+ { 0xDEF4, 715 },
+ { 0xDEF5, 716 },
+ { 0xDEF6, 717 },
+ { 0xDEF7, 718 },
+ { 0xDEF8, 719 },
+ { 0xDEF9, 720 },
+ { 0xDEFA, 721 },
+ { 0xDEFB, 722 },
+ { 0xDEFC, 723 },
+ { 0xDEFD, 724 },
+ { 0xDEFE, 725 },
+ { 0xDEFF, 726 },
+ { 0xDF00, 284 },
{ 0xDF01, 49 },
{ 0xDF02, 50 },
- { 0xDF10, 287 },
- { 0xDF11, 290 },
- { 0xDF12, 293 },
- { 0xDF18, 296 },
- { 0xDF19, 297 },
- { 0xDF1A, 298 },
- { 0xDF40, 299 },
- { 0xDF41, 300 },
- { 0xDF42, 301 },
- { 0xDF43, 302 },
- { 0xDF44, 303 },
- { 0xDF45, 304 },
- { 0xDF46, 305 },
- { 0xDF47, 306 },
- { 0xDF48, 307 },
- { 0xDF49, 308 },
- { 0xDF4A, 309 },
- { 0xDF4B, 310 },
- { 0xDF4C, 311 },
- { 0xDF4D, 312 },
- { 0xDF4E, 313 },
- { 0xDF4F, 314 },
- { 0xDF50, 315 },
- { 0xDF51, 316 },
- { 0xDF52, 317 },
- { 0xDF53, 318 },
- { 0xDF54, 319 },
- { 0xDF55, 320 },
- { 0xDF56, 321 },
- { 0xDF57, 322 },
- { 0xDF58, 323 },
- { 0xDF59, 324 },
- { 0xDF5A, 325 },
- { 0xDF5B, 326 },
- { 0xDF5C, 327 },
- { 0xDF5D, 328 },
- { 0xDF5E, 329 },
- { 0xDF60, 331 },
- { 0xDF61, 332 },
- { 0xDF62, 333 },
- { 0xDF63, 334 },
- { 0xDF64, 335 },
- { 0xDF65, 336 },
- { 0xDF66, 337 },
- { 0xDF67, 338 },
- { 0xDF68, 339 },
- { 0xDF69, 340 },
- { 0xDF6A, 341 },
- { 0xDF6B, 342 },
- { 0xDF6C, 343 },
- { 0xDF6D, 344 },
- { 0xDF6E, 345 },
- { 0xDF6F, 346 },
- { 0xDF70, 347 },
- { 0xDF71, 348 },
- { 0xDF72, 349 },
- { 0xDF73, 350 },
- { 0xDF74, 351 },
- { 0xDF75, 352 },
- { 0xDF76, 353 },
- { 0xDF77, 354 },
- { 0xDF78, 355 },
- { 0xDF79, 356 },
- { 0xDF7A, 357 },
- { 0xDF7B, 358 },
- { 0xDF7C, 359 },
- { 0xDF7D, 360 },
- { 0xDF7E, 361 },
- { 0xDF7F, 330 },
- { 0xE000, 188 },
- { 0xE005, 189 },
- { 0xE080, 192 },
- { 0xE081, 195 },
- { 0xE088, 197 },
- { 0xE089, 199 },
- { 0xE08A, 201 },
- { 0xE08B, 203 },
- { 0xE08F, 204 },
- { 0xE091, 727 },
- { 0xE099, 655 },
- { 0xE100, 207 },
- { 0xE101, 587 },
- { 0xE102, 211 },
- { 0xE108, 213 },
- { 0xE10A, 214 },
- { 0xE110, 730 },
- { 0xE130, 648 },
- { 0xE132, 647 },
- { 0xE180, 215 },
- { 0xE200, 217 },
- { 0xE201, 220 },
- { 0xE208, 223 },
- { 0xE218, 229 },
- { 0xE219, 230 },
- { 0xE21A, 231 },
- { 0xE21B, 232 },
- { 0xE281, 237 },
- { 0xE288, 239 },
- { 0xE289, 242 },
- { 0xE290, 245 },
- { 0xE293, 636 },
- { 0xE298, 247 },
- { 0xE300, 249 },
- { 0xE304, 251 },
- { 0xE4C8, 619 },
- { 0xE510, 266 },
- { 0xE518, 269 },
- { 0xE520, 667 },
- { 0xE521, 668 },
- { 0xE528, 664 },
- { 0xE530, 669 },
- { 0xE531, 670 },
- { 0xE532, 671 },
- { 0xE533, 672 },
- { 0xE534, 673 },
- { 0xE535, 674 },
- { 0xE536, 675 },
- { 0xE537, 676 },
- { 0xE600, 272 },
+ { 0xDF10, 288 },
+ { 0xDF11, 291 },
+ { 0xDF12, 294 },
+ { 0xDF18, 297 },
+ { 0xDF19, 298 },
+ { 0xDF1A, 299 },
+ { 0xDF40, 300 },
+ { 0xDF41, 301 },
+ { 0xDF42, 302 },
+ { 0xDF43, 303 },
+ { 0xDF44, 304 },
+ { 0xDF45, 305 },
+ { 0xDF46, 306 },
+ { 0xDF47, 307 },
+ { 0xDF48, 308 },
+ { 0xDF49, 309 },
+ { 0xDF4A, 310 },
+ { 0xDF4B, 311 },
+ { 0xDF4C, 312 },
+ { 0xDF4D, 313 },
+ { 0xDF4E, 314 },
+ { 0xDF4F, 315 },
+ { 0xDF50, 316 },
+ { 0xDF51, 317 },
+ { 0xDF52, 318 },
+ { 0xDF53, 319 },
+ { 0xDF54, 320 },
+ { 0xDF55, 321 },
+ { 0xDF56, 322 },
+ { 0xDF57, 323 },
+ { 0xDF58, 324 },
+ { 0xDF59, 325 },
+ { 0xDF5A, 326 },
+ { 0xDF5B, 327 },
+ { 0xDF5C, 328 },
+ { 0xDF5D, 329 },
+ { 0xDF5E, 330 },
+ { 0xDF60, 332 },
+ { 0xDF61, 333 },
+ { 0xDF62, 334 },
+ { 0xDF63, 335 },
+ { 0xDF64, 336 },
+ { 0xDF65, 337 },
+ { 0xDF66, 338 },
+ { 0xDF67, 339 },
+ { 0xDF68, 340 },
+ { 0xDF69, 341 },
+ { 0xDF6A, 342 },
+ { 0xDF6B, 343 },
+ { 0xDF6C, 344 },
+ { 0xDF6D, 345 },
+ { 0xDF6E, 346 },
+ { 0xDF6F, 347 },
+ { 0xDF70, 348 },
+ { 0xDF71, 349 },
+ { 0xDF72, 350 },
+ { 0xDF73, 351 },
+ { 0xDF74, 352 },
+ { 0xDF75, 353 },
+ { 0xDF76, 354 },
+ { 0xDF77, 355 },
+ { 0xDF78, 356 },
+ { 0xDF79, 357 },
+ { 0xDF7A, 358 },
+ { 0xDF7B, 359 },
+ { 0xDF7C, 360 },
+ { 0xDF7D, 361 },
+ { 0xDF7E, 362 },
+ { 0xDF7F, 331 },
+ { 0xE000, 189 },
+ { 0xE005, 190 },
+ { 0xE080, 193 },
+ { 0xE081, 196 },
+ { 0xE088, 198 },
+ { 0xE089, 200 },
+ { 0xE08A, 202 },
+ { 0xE08B, 204 },
+ { 0xE08F, 205 },
+ { 0xE090, 733 },
+ { 0xE091, 728 },
+ { 0xE099, 656 },
+ { 0xE100, 208 },
+ { 0xE101, 588 },
+ { 0xE102, 212 },
+ { 0xE108, 214 },
+ { 0xE10A, 215 },
+ { 0xE110, 731 },
+ { 0xE130, 649 },
+ { 0xE132, 648 },
+ { 0xE180, 216 },
+ { 0xE200, 218 },
+ { 0xE201, 221 },
+ { 0xE208, 224 },
+ { 0xE218, 230 },
+ { 0xE219, 231 },
+ { 0xE21A, 232 },
+ { 0xE21B, 233 },
+ { 0xE281, 238 },
+ { 0xE288, 240 },
+ { 0xE289, 243 },
+ { 0xE290, 246 },
+ { 0xE293, 637 },
+ { 0xE298, 248 },
+ { 0xE300, 250 },
+ { 0xE304, 252 },
+ { 0xE4C8, 620 },
+ { 0xE510, 267 },
+ { 0xE518, 270 },
+ { 0xE520, 668 },
+ { 0xE521, 669 },
+ { 0xE528, 665 },
+ { 0xE530, 670 },
+ { 0xE531, 671 },
+ { 0xE532, 672 },
+ { 0xE533, 673 },
+ { 0xE534, 674 },
+ { 0xE535, 675 },
+ { 0xE536, 676 },
+ { 0xE537, 677 },
+ { 0xE600, 273 },
{ 0xE601, 46 },
- { 0xE602, 275 },
- { 0xE609, 635 },
- { 0xE640, 554 },
- { 0xE641, 555 },
- { 0xE642, 556 },
- { 0xE643, 557 },
- { 0xE648, 558 },
- { 0xE649, 559 },
- { 0xE64A, 560 },
- { 0xE64B, 561 },
- { 0xE64C, 565 },
- { 0xE64D, 540 },
- { 0xE658, 562 },
+ { 0xE602, 276 },
+ { 0xE609, 636 },
+ { 0xE640, 555 },
+ { 0xE641, 556 },
+ { 0xE642, 557 },
+ { 0xE643, 558 },
+ { 0xE648, 559 },
+ { 0xE649, 560 },
+ { 0xE64A, 561 },
+ { 0xE64B, 562 },
+ { 0xE64C, 566 },
+ { 0xE64D, 541 },
+ { 0xE658, 563 },
{ 0xE659, 93 },
- { 0xE65A, 563 },
+ { 0xE65A, 564 },
{ 0xE65B, 94 },
{ 0xE65D, 95 },
- { 0xE65F, 564 },
- { 0xE660, 566 },
- { 0xE661, 567 },
- { 0xE662, 568 },
- { 0xE663, 569 },
- { 0xE664, 570 },
- { 0xE665, 571 },
- { 0xE666, 572 },
- { 0xE667, 573 },
- { 0xE668, 574 },
- { 0xE669, 575 },
- { 0xE66A, 576 },
- { 0xE66B, 577 },
- { 0xE66C, 578 },
- { 0xE66D, 579 },
- { 0xE66E, 580 },
- { 0xE66F, 581 },
- { 0xE681, 588 },
- { 0xE682, 279 },
- { 0xE703, 284 },
- { 0xE708, 286 },
- { 0xE710, 288 },
- { 0xE711, 291 },
- { 0xE712, 294 },
- { 0xE718, 589 },
- { 0xE719, 591 },
- { 0xE71A, 590 },
- { 0xE720, 649 },
- { 0xE721, 651 },
- { 0xE722, 650 },
- { 0xE728, 652 },
- { 0xE729, 654 },
- { 0xE72A, 653 },
- { 0xE880, 592 },
- { 0xE882, 593 },
- { 0xE891, 728 },
- { 0xE900, 594 },
- { 0xE901, 595 },
- { 0xE902, 596 },
- { 0xEA00, 612 },
- { 0xEA01, 613 },
- { 0xEA88, 597 },
- { 0xEA89, 598 },
- { 0xEA90, 599 },
- { 0xEB00, 600 },
- { 0xECC8, 620 },
- { 0xED10, 601 },
- { 0xED18, 602 },
- { 0xED28, 666 },
- { 0xEE00, 603 },
- { 0xEE81, 604 },
- { 0xEF08, 605 },
- { 0xEF10, 606 },
- { 0xEF11, 607 },
- { 0xEF12, 608 },
- { 0xEF18, 609 },
- { 0xEF19, 610 },
- { 0xEF1A, 611 },
- { 0xF080, 193 },
- { 0xF081, 196 },
- { 0xF088, 198 },
- { 0xF089, 200 },
- { 0xF08A, 202 },
- { 0xF099, 205 },
- { 0xF100, 208 },
- { 0xF102, 212 },
- { 0xF200, 218 },
- { 0xF201, 221 },
- { 0xF208, 224 },
- { 0xF288, 240 },
- { 0xF289, 243 },
- { 0xF290, 246 },
- { 0xF300, 250 },
- { 0xF510, 267 },
- { 0xF518, 270 },
- { 0xF528, 665 },
- { 0xF600, 273 },
+ { 0xE65F, 565 },
+ { 0xE660, 567 },
+ { 0xE661, 568 },
+ { 0xE662, 569 },
+ { 0xE663, 570 },
+ { 0xE664, 571 },
+ { 0xE665, 572 },
+ { 0xE666, 573 },
+ { 0xE667, 574 },
+ { 0xE668, 575 },
+ { 0xE669, 576 },
+ { 0xE66A, 577 },
+ { 0xE66B, 578 },
+ { 0xE66C, 579 },
+ { 0xE66D, 580 },
+ { 0xE66E, 581 },
+ { 0xE66F, 582 },
+ { 0xE681, 589 },
+ { 0xE682, 280 },
+ { 0xE703, 285 },
+ { 0xE708, 287 },
+ { 0xE710, 289 },
+ { 0xE711, 292 },
+ { 0xE712, 295 },
+ { 0xE718, 590 },
+ { 0xE719, 592 },
+ { 0xE71A, 591 },
+ { 0xE720, 650 },
+ { 0xE721, 652 },
+ { 0xE722, 651 },
+ { 0xE728, 653 },
+ { 0xE729, 655 },
+ { 0xE72A, 654 },
+ { 0xE880, 593 },
+ { 0xE882, 594 },
+ { 0xE890, 735 },
+ { 0xE891, 729 },
+ { 0xE900, 595 },
+ { 0xE901, 596 },
+ { 0xE902, 597 },
+ { 0xEA00, 613 },
+ { 0xEA01, 614 },
+ { 0xEA88, 598 },
+ { 0xEA89, 599 },
+ { 0xEA90, 600 },
+ { 0xEB00, 601 },
+ { 0xECC8, 621 },
+ { 0xED10, 602 },
+ { 0xED18, 603 },
+ { 0xED28, 667 },
+ { 0xEE00, 604 },
+ { 0xEE81, 605 },
+ { 0xEF08, 606 },
+ { 0xEF10, 607 },
+ { 0xEF11, 608 },
+ { 0xEF12, 609 },
+ { 0xEF18, 610 },
+ { 0xEF19, 611 },
+ { 0xEF1A, 612 },
+ { 0xF080, 194 },
+ { 0xF081, 197 },
+ { 0xF088, 199 },
+ { 0xF089, 201 },
+ { 0xF08A, 203 },
+ { 0xF090, 734 },
+ { 0xF099, 206 },
+ { 0xF100, 209 },
+ { 0xF102, 213 },
+ { 0xF200, 219 },
+ { 0xF201, 222 },
+ { 0xF208, 225 },
+ { 0xF288, 241 },
+ { 0xF289, 244 },
+ { 0xF290, 247 },
+ { 0xF300, 251 },
+ { 0xF510, 268 },
+ { 0xF518, 271 },
+ { 0xF528, 666 },
+ { 0xF600, 274 },
{ 0xF601, 47 },
- { 0xF602, 276 },
- { 0xF664, 538 },
- { 0xF665, 541 },
- { 0xF667, 544 },
- { 0xF682, 280 },
- { 0xFF10, 289 },
- { 0xFF11, 292 },
- { 0xFF12, 295 },
- { 0xFF90, 731 },
+ { 0xF602, 277 },
+ { 0xF664, 539 },
+ { 0xF665, 542 },
+ { 0xF667, 545 },
+ { 0xF682, 281 },
+ { 0xFF10, 290 },
+ { 0xFF11, 293 },
+ { 0xFF12, 296 },
+ { 0xFF90, 736 },
};
struct KeyType {
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/ARM/ARMGenInstrInfo.inc b/third_party/llvm-7.0/configs/common/lib/Target/ARM/ARMGenInstrInfo.inc
index 8317036..82af8c1 100644
--- a/third_party/llvm-7.0/configs/common/lib/Target/ARM/ARMGenInstrInfo.inc
+++ b/third_party/llvm-7.0/configs/common/lib/Target/ARM/ARMGenInstrInfo.inc
@@ -7542,7 +7542,7 @@
{ 2847, 7, 3, 4, 415, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo368, -1 ,nullptr }, // Inst #2847 = t2LDRD_POST
{ 2848, 7, 3, 4, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo368, -1 ,nullptr }, // Inst #2848 = t2LDRD_PRE
{ 2849, 6, 2, 4, 412, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo369, -1 ,nullptr }, // Inst #2849 = t2LDRDi8
- { 2850, 5, 1, 4, 684, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo370, -1 ,nullptr }, // Inst #2850 = t2LDREX
+ { 2850, 5, 1, 4, 684, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc92ULL, nullptr, nullptr, OperandInfo370, -1 ,nullptr }, // Inst #2850 = t2LDREX
{ 2851, 4, 1, 4, 684, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2851 = t2LDREXB
{ 2852, 5, 2, 4, 684, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2852 = t2LDREXD
{ 2853, 4, 1, 4, 684, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2853 = t2LDREXH
@@ -7747,7 +7747,7 @@
{ 3052, 7, 1, 4, 444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo392, -1 ,nullptr }, // Inst #3052 = t2STRD_POST
{ 3053, 7, 1, 4, 935, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo392, -1 ,nullptr }, // Inst #3053 = t2STRD_PRE
{ 3054, 6, 0, 4, 443, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo369, -1 ,nullptr }, // Inst #3054 = t2STRDi8
- { 3055, 6, 1, 4, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #3055 = t2STREX
+ { 3055, 6, 1, 4, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc92ULL, nullptr, nullptr, OperandInfo393, -1 ,nullptr }, // Inst #3055 = t2STREX
{ 3056, 5, 1, 4, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo388, -1 ,nullptr }, // Inst #3056 = t2STREXB
{ 3057, 6, 1, 4, 727, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo389, -1 ,nullptr }, // Inst #3057 = t2STREXD
{ 3058, 5, 1, 4, 727, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo388, -1 ,nullptr }, // Inst #3058 = t2STREXH
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenAsmMatcher.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenAsmMatcher.inc
new file mode 100644
index 0000000..50a8e31
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenAsmMatcher.inc
@@ -0,0 +1,11318 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Assembly Matcher Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_ASSEMBLER_HEADER
+#undef GET_ASSEMBLER_HEADER
+ // This should be included into the middle of the declaration of
+ // your subclasses implementation of MCTargetAsmParser.
+ uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
+ void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
+ const OperandVector &Operands);
+ void convertToMapAndConstraints(unsigned Kind,
+ const OperandVector &Operands) override;
+ unsigned MatchInstructionImpl(const OperandVector &Operands,
+ MCInst &Inst,
+ uint64_t &ErrorInfo,
+ bool matchingInlineAsm,
+ unsigned VariantID = 0);
+ OperandMatchResultTy MatchOperandParserImpl(
+ OperandVector &Operands,
+ StringRef Mnemonic,
+ bool ParseForAllFeatures = false);
+ OperandMatchResultTy tryCustomParseOperand(
+ OperandVector &Operands,
+ unsigned MCK);
+
+#endif // GET_ASSEMBLER_HEADER_INFO
+
+
+#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
+#undef GET_OPERAND_DIAGNOSTIC_TYPES
+
+ Match_Immz,
+ Match_MemSImm10,
+ Match_MemSImm10Lsl1,
+ Match_MemSImm10Lsl2,
+ Match_MemSImm10Lsl3,
+ Match_MemSImm11,
+ Match_MemSImm12,
+ Match_MemSImm16,
+ Match_MemSImm9,
+ Match_MemSImmPtr,
+ Match_SImm10_0,
+ Match_SImm10_Lsl1,
+ Match_SImm10_Lsl2,
+ Match_SImm10_Lsl3,
+ Match_SImm11_0,
+ Match_SImm16,
+ Match_SImm16_Relaxed,
+ Match_SImm19_Lsl2,
+ Match_SImm32,
+ Match_SImm32_Relaxed,
+ Match_SImm4_0,
+ Match_SImm5_0,
+ Match_SImm6_0,
+ Match_SImm7_Lsl2,
+ Match_SImm9_0,
+ Match_UImm10_0,
+ Match_UImm16,
+ Match_UImm16_AltRelaxed,
+ Match_UImm16_Relaxed,
+ Match_UImm1_0,
+ Match_UImm20_0,
+ Match_UImm26_0,
+ Match_UImm2_0,
+ Match_UImm2_1,
+ Match_UImm32_Coerced,
+ Match_UImm3_0,
+ Match_UImm4_0,
+ Match_UImm5_0,
+ Match_UImm5_0_Report_UImm6,
+ Match_UImm5_1,
+ Match_UImm5_32,
+ Match_UImm5_33,
+ Match_UImm5_Lsl2,
+ Match_UImm6_0,
+ Match_UImm6_Lsl2,
+ Match_UImm7_0,
+ Match_UImm7_N1,
+ Match_UImm8_0,
+ Match_UImmRange2_64,
+ END_OPERAND_DIAGNOSTIC_TYPES
+#endif // GET_OPERAND_DIAGNOSTIC_TYPES
+
+
+#ifdef GET_REGISTER_MATCHER
+#undef GET_REGISTER_MATCHER
+
+// Flags for subtarget features that participate in instruction matching.
+enum SubtargetFeatureFlag : uint64_t {
+ Feature_HasMips2 = (1ULL << 10),
+ Feature_HasMips3_32 = (1ULL << 16),
+ Feature_HasMips3_32r2 = (1ULL << 17),
+ Feature_HasMips3 = (1ULL << 11),
+ Feature_NotMips3 = (1ULL << 44),
+ Feature_HasMips4_32 = (1ULL << 18),
+ Feature_NotMips4_32 = (1ULL << 46),
+ Feature_HasMips4_32r2 = (1ULL << 19),
+ Feature_HasMips5_32r2 = (1ULL << 20),
+ Feature_HasMips32 = (1ULL << 12),
+ Feature_HasMips32r2 = (1ULL << 13),
+ Feature_HasMips32r5 = (1ULL << 14),
+ Feature_HasMips32r6 = (1ULL << 15),
+ Feature_NotMips32r6 = (1ULL << 45),
+ Feature_IsGP64bit = (1ULL << 31),
+ Feature_IsGP32bit = (1ULL << 30),
+ Feature_IsPTR64bit = (1ULL << 35),
+ Feature_IsPTR32bit = (1ULL << 34),
+ Feature_HasMips64 = (1ULL << 21),
+ Feature_NotMips64 = (1ULL << 47),
+ Feature_HasMips64r2 = (1ULL << 22),
+ Feature_HasMips64r5 = (1ULL << 23),
+ Feature_HasMips64r6 = (1ULL << 24),
+ Feature_NotMips64r6 = (1ULL << 48),
+ Feature_InMips16Mode = (1ULL << 28),
+ Feature_NotInMips16Mode = (1ULL << 43),
+ Feature_HasCnMips = (1ULL << 1),
+ Feature_NotCnMips = (1ULL << 40),
+ Feature_IsSym32 = (1ULL << 37),
+ Feature_IsSym64 = (1ULL << 38),
+ Feature_HasStdEnc = (1ULL << 25),
+ Feature_InMicroMips = (1ULL << 27),
+ Feature_NotInMicroMips = (1ULL << 42),
+ Feature_HasEVA = (1ULL << 5),
+ Feature_HasMSA = (1ULL << 7),
+ Feature_HasMadd4 = (1ULL << 9),
+ Feature_HasMT = (1ULL << 8),
+ Feature_UseIndirectJumpsHazard = (1ULL << 49),
+ Feature_NoIndirectJumpGuards = (1ULL << 39),
+ Feature_HasCRC = (1ULL << 0),
+ Feature_HasVirt = (1ULL << 26),
+ Feature_HasGINV = (1ULL << 6),
+ Feature_IsFP64bit = (1ULL << 29),
+ Feature_NotFP64bit = (1ULL << 41),
+ Feature_IsSingleFloat = (1ULL << 36),
+ Feature_IsNotSingleFloat = (1ULL << 32),
+ Feature_IsNotSoftFloat = (1ULL << 33),
+ Feature_HasDSP = (1ULL << 2),
+ Feature_HasDSPR2 = (1ULL << 3),
+ Feature_HasDSPR3 = (1ULL << 4),
+ Feature_None = 0
+};
+
+#endif // GET_REGISTER_MATCHER
+
+
+#ifdef GET_SUBTARGET_FEATURE_NAME
+#undef GET_SUBTARGET_FEATURE_NAME
+
+// User-level names for subtarget features that participate in
+// instruction matching.
+static const char *getSubtargetFeatureName(uint64_t Val) {
+ switch(Val) {
+ case Feature_HasMips2: return "";
+ case Feature_HasMips3_32: return "";
+ case Feature_HasMips3_32r2: return "";
+ case Feature_HasMips3: return "";
+ case Feature_NotMips3: return "";
+ case Feature_HasMips4_32: return "";
+ case Feature_NotMips4_32: return "";
+ case Feature_HasMips4_32r2: return "";
+ case Feature_HasMips5_32r2: return "";
+ case Feature_HasMips32: return "";
+ case Feature_HasMips32r2: return "";
+ case Feature_HasMips32r5: return "";
+ case Feature_HasMips32r6: return "";
+ case Feature_NotMips32r6: return "";
+ case Feature_IsGP64bit: return "";
+ case Feature_IsGP32bit: return "";
+ case Feature_IsPTR64bit: return "";
+ case Feature_IsPTR32bit: return "";
+ case Feature_HasMips64: return "";
+ case Feature_NotMips64: return "";
+ case Feature_HasMips64r2: return "";
+ case Feature_HasMips64r5: return "";
+ case Feature_HasMips64r6: return "";
+ case Feature_NotMips64r6: return "";
+ case Feature_InMips16Mode: return "";
+ case Feature_NotInMips16Mode: return "";
+ case Feature_HasCnMips: return "";
+ case Feature_NotCnMips: return "";
+ case Feature_IsSym32: return "";
+ case Feature_IsSym64: return "";
+ case Feature_HasStdEnc: return "";
+ case Feature_InMicroMips: return "";
+ case Feature_NotInMicroMips: return "";
+ case Feature_HasEVA: return "";
+ case Feature_HasMSA: return "";
+ case Feature_HasMadd4: return "";
+ case Feature_HasMT: return "";
+ case Feature_UseIndirectJumpsHazard: return "";
+ case Feature_NoIndirectJumpGuards: return "";
+ case Feature_HasCRC: return "";
+ case Feature_HasVirt: return "";
+ case Feature_HasGINV: return "";
+ case Feature_IsFP64bit: return "";
+ case Feature_NotFP64bit: return "";
+ case Feature_IsSingleFloat: return "";
+ case Feature_IsNotSingleFloat: return "";
+ case Feature_IsNotSoftFloat: return "";
+ case Feature_HasDSP: return "";
+ case Feature_HasDSPR2: return "";
+ case Feature_HasDSPR3: return "";
+ default: return "(unknown)";
+ }
+}
+
+#endif // GET_SUBTARGET_FEATURE_NAME
+
+
+#ifdef GET_MATCHER_IMPLEMENTATION
+#undef GET_MATCHER_IMPLEMENTATION
+
+enum {
+ Tie0_1_1,
+ Tie0_1_2,
+};
+
+static const uint8_t TiedAsmOperandTable[][3] = {
+ /* Tie0_1_1 */ { 0, 1, 1 },
+ /* Tie0_1_2 */ { 0, 1, 2 },
+};
+
+namespace {
+enum OperatorConversionKind {
+ CVT_Done,
+ CVT_Reg,
+ CVT_Tied,
+ CVT_95_addGPR32AsmRegOperands,
+ CVT_95_addAFGR64AsmRegOperands,
+ CVT_95_addFGR64AsmRegOperands,
+ CVT_95_addFGR32AsmRegOperands,
+ CVT_95_addSImmOperands_LT_32_GT_,
+ CVT_95_addMSA128AsmRegOperands,
+ CVT_95_addSImmOperands_LT_16_GT_,
+ CVT_95_Reg,
+ CVT_95_addImmOperands,
+ CVT_95_addGPRMM16AsmRegOperands,
+ CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
+ CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
+ CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
+ CVT_95_addUImmOperands_LT_16_GT_,
+ CVT_95_addGPR64AsmRegOperands,
+ CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
+ CVT_regZERO,
+ CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
+ CVT_regFCC0,
+ CVT_95_addFCCAsmRegOperands,
+ CVT_95_addCOP2AsmRegOperands,
+ CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
+ CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
+ CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
+ CVT_imm_95_0,
+ CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
+ CVT_95_addMemOperands,
+ CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
+ CVT_95_addCCRAsmRegOperands,
+ CVT_95_addMSACtrlAsmRegOperands,
+ CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
+ CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
+ CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
+ CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
+ CVT_95_addGPR32NonZeroAsmRegOperands,
+ CVT_95_addGPR32ZeroAsmRegOperands,
+ CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
+ CVT_95_addCOP0AsmRegOperands,
+ CVT_regZERO_64,
+ CVT_95_addACC64DSPAsmRegOperands,
+ CVT_95_addConstantUImmOperands_LT_1_GT_,
+ CVT_regRA,
+ CVT_regRA_64,
+ CVT_95_addMicroMipsMemOperands,
+ CVT_95_addCOP3AsmRegOperands,
+ CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
+ CVT_95_addConstantUImmOperands_LT_32_GT_,
+ CVT_95_addStrictlyAFGR64AsmRegOperands,
+ CVT_95_addStrictlyFGR64AsmRegOperands,
+ CVT_95_addStrictlyFGR32AsmRegOperands,
+ CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
+ CVT_95_addRegListOperands,
+ CVT_ConvertXWPOperands,
+ CVT_regAC0,
+ CVT_95_addMovePRegPairOperands,
+ CVT_95_addGPRMM16AsmRegMovePOperands,
+ CVT_95_addHI32DSPAsmRegOperands,
+ CVT_95_addLO32DSPAsmRegOperands,
+ CVT_regS0,
+ CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
+ CVT_95_addHWRegsAsmRegOperands,
+ CVT_95_addGPRMM16AsmRegZeroOperands,
+ CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
+ CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
+ CVT_imm_95_2,
+ CVT_imm_95_6,
+ CVT_imm_95_4,
+ CVT_imm_95_5,
+ CVT_imm_95_31,
+ CVT_NUM_CONVERTERS
+};
+
+enum InstructionConversionKind {
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
+ Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
+ Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
+ Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
+ Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
+ Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
+ Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
+ Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
+ Convert__SImm161_1,
+ Convert__Reg1_0__SImm161_1,
+ Convert__Reg1_0__SImm161_2,
+ Convert__Reg1_0__Reg1_1__SImm161_2,
+ Convert__Reg1_0__Tie0_1_1__SImm161_1,
+ Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
+ Convert__GPRMM16AsmReg1_0__Imm1_1,
+ Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
+ Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
+ Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
+ Convert__Imm1_0,
+ Convert__Reg1_0__Reg1_1__Reg1_2,
+ Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
+ Convert__GPR32AsmReg1_0__SImm161_1,
+ Convert__Reg1_0__Tie0_1_1__Reg1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
+ Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
+ Convert__regZERO__regZERO__JumpTarget1_0,
+ Convert__JumpTarget1_0,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
+ Convert__regZERO__JumpTarget1_0,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
+ Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
+ Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
+ Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
+ Convert__FGR64AsmReg1_0__JumpTarget1_1,
+ Convert__regFCC0__JumpTarget1_0,
+ Convert__FCCAsmReg1_0__JumpTarget1_1,
+ Convert__COP2AsmReg1_0__JumpTarget1_1,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
+ Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
+ Convert__Reg1_0__JumpTarget1_1,
+ Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
+ Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
+ Convert__GPR32AsmReg1_0__JumpTarget1_1,
+ Convert__GPR64AsmReg1_0__JumpTarget1_1,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
+ Convert__MSA128AsmReg1_0__JumpTarget1_1,
+ Convert__imm_95_0__imm_95_0,
+ Convert_NoOperands,
+ Convert__ConstantUImm10_01_0__imm_95_0,
+ Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
+ Convert__ConstantUImm4_01_0,
+ Convert__SImm161_0,
+ Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
+ Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
+ Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
+ Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
+ Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
+ Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
+ Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,
+ Convert__Mem2_1__ConstantUImm5_01_0,
+ Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
+ Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
+ Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
+ Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
+ Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
+ Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
+ Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
+ Convert__Reg1_0__Reg1_1,
+ Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
+ Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
+ Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
+ Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
+ Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
+ Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
+ Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
+ Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
+ Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
+ Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
+ Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
+ Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
+ Convert__regZERO,
+ Convert__GPR32AsmReg1_0,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
+ Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
+ Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
+ Convert__Reg1_1__Reg1_2,
+ Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
+ Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
+ Convert__GPR64AsmReg1_0__Imm1_1,
+ Convert__GPR64AsmReg1_0__Mem2_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
+ Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
+ Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
+ Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
+ Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
+ Convert__GPR64AsmReg1_0__UImm161_1,
+ Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
+ Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
+ Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
+ Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
+ Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
+ Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
+ Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
+ Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
+ Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
+ Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
+ Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
+ Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
+ Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
+ Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
+ Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
+ Convert__imm_95_0,
+ Convert__ConstantUImm10_01_0,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
+ Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
+ Convert__regRA__GPR32AsmReg1_0,
+ Convert__regRA_64__GPR64AsmReg1_0,
+ Convert__Reg1_0,
+ Convert__GPR32AsmReg1_0__imm_95_0,
+ Convert__GPR64AsmReg1_0__imm_95_0,
+ Convert__regZERO__GPR32AsmReg1_0,
+ Convert__GPR64AsmReg1_0,
+ Convert__regZERO_64__GPR64AsmReg1_0,
+ Convert__UImm5Lsl21_0,
+ Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1,
+ Convert__FGR64AsmReg1_0__MemOffsetSimm162_1,
+ Convert__FGR32AsmReg1_0__MemOffsetSimm162_1,
+ Convert__GPR32AsmReg1_0__Imm1_1,
+ Convert__GPR32AsmReg1_0__Mem2_1,
+ Convert__GPR32AsmReg1_0__MemOffsetSimm162_1,
+ Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
+ Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,
+ Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
+ Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
+ Convert__MSA128AsmReg1_0__MemOffsetSimm102_1,
+ Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
+ Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
+ Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
+ Convert__COP2AsmReg1_0__MemOffsetSimm112_1,
+ Convert__COP2AsmReg1_0__MemOffsetSimm162_1,
+ Convert__COP3AsmReg1_0__Mem2_1,
+ Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
+ Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
+ Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
+ Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
+ Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
+ Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
+ Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
+ Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
+ Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
+ Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
+ Convert__GPR32AsmReg1_0__UImm161_1,
+ Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
+ Convert__Reg1_0__Imm1_1__imm_95_0,
+ Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
+ Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
+ Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
+ Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1,
+ Convert__RegList1_0__Mem2_1,
+ Convert__RegList161_0__MemOffsetUimm42_1,
+ ConvertCustom_ConvertXWPOperands,
+ Convert__GPR32AsmReg1_0__MemOffsetSimm122_1,
+ Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
+ Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
+ Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
+ Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
+ Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
+ Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
+ Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
+ Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
+ Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
+ Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
+ Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
+ Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
+ Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
+ Convert__GPR32AsmReg1_0__regAC0,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
+ Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
+ Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
+ Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
+ Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
+ Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
+ Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
+ Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
+ Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
+ Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
+ Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
+ Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
+ Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
+ Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
+ Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
+ Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
+ Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
+ Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
+ Convert__regAC0__GPR32AsmReg1_0,
+ Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
+ Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
+ Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
+ Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
+ Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
+ Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
+ Convert__regZERO__regZERO__imm_95_0,
+ Convert__regZERO__regS0,
+ Convert__regZERO__regZERO,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
+ Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
+ Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
+ Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
+ Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
+ Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
+ Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
+ Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
+ Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
+ Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
+ Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
+ Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
+ Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
+ Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1,
+ Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
+ Convert__ConstantUImm20_01_0,
+ Convert__Reg1_0__Tie0_1_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
+ Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
+ Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
+ Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
+ Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
+ Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
+ Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
+ Convert__ConstantUImm5_01_0,
+ Convert__MemOffsetSimm162_0,
+ Convert__imm_95_2,
+ Convert__imm_95_6,
+ Convert__imm_95_4,
+ Convert__imm_95_5,
+ Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
+ Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
+ Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
+ Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
+ Convert__GPR32AsmReg1_0__imm_95_31,
+ CVT_NUM_SIGNATURES
+};
+
+} // end anonymous namespace
+
+static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
+ { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
+ // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
+ { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
+ // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
+ // Convert__SImm161_1
+ { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__Reg1_0__SImm161_1
+ { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__Reg1_0__SImm161_2
+ { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm161_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__SImm161_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__Imm1_1
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
+ // Convert__Imm1_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
+ // Convert__GPR32AsmReg1_0__SImm161_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__Reg1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__regZERO__regZERO__JumpTarget1_0
+ { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__JumpTarget1_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
+ // Convert__regZERO__JumpTarget1_0
+ { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__FGR64AsmReg1_0__JumpTarget1_1
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__regFCC0__JumpTarget1_0
+ { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__FCCAsmReg1_0__JumpTarget1_1
+ { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__COP2AsmReg1_0__JumpTarget1_1
+ { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__JumpTarget1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__JumpTarget1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__JumpTarget1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__JumpTarget1_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__imm_95_0__imm_95_0
+ { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
+ // Convert_NoOperands
+ { CVT_Done },
+ // Convert__ConstantUImm10_01_0__imm_95_0
+ { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
+ { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
+ // Convert__ConstantUImm4_01_0
+ { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
+ // Convert__SImm161_0
+ { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
+ // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
+ { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
+ { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
+ { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
+ // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
+ { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
+ // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
+ { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
+ // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
+ { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
+ // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0
+ { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
+ // Convert__Mem2_1__ConstantUImm5_01_0
+ { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
+ // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
+ // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
+ // Convert__Reg1_0__Reg1_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
+ // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
+ // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
+ { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
+ { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
+ { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
+ // Convert__regZERO
+ { CVT_regZERO, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
+ // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
+ { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
+ { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__Reg1_1__Reg1_2
+ { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
+ // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__Imm1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__Mem2_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
+ // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__GPR64AsmReg1_0__UImm161_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
+ { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
+ { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
+ { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
+ // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
+ { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
+ { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
+ // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
+ { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
+ // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
+ { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
+ // Convert__imm_95_0
+ { CVT_imm_95_0, 0, CVT_Done },
+ // Convert__ConstantUImm10_01_0
+ { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
+ // Convert__regRA__GPR32AsmReg1_0
+ { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__regRA_64__GPR64AsmReg1_0
+ { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
+ // Convert__Reg1_0
+ { CVT_95_Reg, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__imm_95_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__GPR64AsmReg1_0__imm_95_0
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__regZERO__GPR32AsmReg1_0
+ { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR64AsmReg1_0
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
+ // Convert__regZERO_64__GPR64AsmReg1_0
+ { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
+ // Convert__UImm5Lsl21_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1
+ { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Imm1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Mem2_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__COP2AsmReg1_0__MemOffsetSimm112_1
+ { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__COP2AsmReg1_0__MemOffsetSimm162_1
+ { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__COP3AsmReg1_0__Mem2_1
+ { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
+ { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
+ // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
+ { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
+ { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
+ { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
+ // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
+ { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
+ // Convert__GPR32AsmReg1_0__UImm161_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
+ // Convert__Reg1_0__Imm1_1__imm_95_0
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__RegList1_0__Mem2_1
+ { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__RegList161_0__MemOffsetUimm42_1
+ { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // ConvertCustom_ConvertXWPOperands
+ { CVT_ConvertXWPOperands, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
+ { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
+ // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
+ // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
+ // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__regAC0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
+ // Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2
+ { CVT_95_addMovePRegPairOperands, 1, CVT_95_addGPRMM16AsmRegMovePOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
+ { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
+ { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
+ { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
+ { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
+ { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
+ { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
+ { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
+ { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
+ { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
+ { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__regAC0__GPR32AsmReg1_0
+ { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
+ { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
+ // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__regZERO__regZERO__imm_95_0
+ { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__regZERO__regS0
+ { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
+ // Convert__regZERO__regZERO
+ { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
+ // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
+ { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
+ { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
+ { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
+ // Convert__ConstantUImm20_01_0
+ { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
+ // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
+ { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
+ // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
+ { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
+ { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
+ // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
+ // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
+ { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__ConstantUImm5_01_0
+ { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
+ // Convert__MemOffsetSimm162_0
+ { CVT_95_addMemOperands, 1, CVT_Done },
+ // Convert__imm_95_2
+ { CVT_imm_95_2, 0, CVT_Done },
+ // Convert__imm_95_6
+ { CVT_imm_95_6, 0, CVT_Done },
+ // Convert__imm_95_4
+ { CVT_imm_95_4, 0, CVT_Done },
+ // Convert__imm_95_5
+ { CVT_imm_95_5, 0, CVT_Done },
+ // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
+ // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
+ { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
+ // Convert__GPR32AsmReg1_0__imm_95_31
+ { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
+};
+
+void MipsAsmParser::
+convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
+ const OperandVector &Operands) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ const uint8_t *Converter = ConversionTable[Kind];
+ unsigned OpIdx;
+ Inst.setOpcode(Opcode);
+ for (const uint8_t *p = Converter; *p; p+= 2) {
+ OpIdx = *(p + 1);
+ switch (*p) {
+ default: llvm_unreachable("invalid conversion entry!");
+ case CVT_Reg:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
+ break;
+ case CVT_Tied: {
+ assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
+ std::begin(TiedAsmOperandTable)) &&
+ "Tied operand not found");
+ unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
+ if (TiedResOpnd != (uint8_t) -1)
+ Inst.addOperand(Inst.getOperand(TiedResOpnd));
+ break;
+ }
+ case CVT_95_addGPR32AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addAFGR64AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addFGR64AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addFGR32AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addSImmOperands_LT_32_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
+ break;
+ case CVT_95_addMSA128AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addSImmOperands_LT_16_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
+ break;
+ case CVT_95_Reg:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
+ break;
+ case CVT_95_addImmOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
+ break;
+ case CVT_95_addGPRMM16AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
+ break;
+ case CVT_95_addUImmOperands_LT_16_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
+ break;
+ case CVT_95_addGPR64AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
+ break;
+ case CVT_regZERO:
+ Inst.addOperand(MCOperand::createReg(Mips::ZERO));
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
+ break;
+ case CVT_regFCC0:
+ Inst.addOperand(MCOperand::createReg(Mips::FCC0));
+ break;
+ case CVT_95_addFCCAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addCOP2AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
+ break;
+ case CVT_imm_95_0:
+ Inst.addOperand(MCOperand::createImm(0));
+ break;
+ case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
+ break;
+ case CVT_95_addMemOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2);
+ break;
+ case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
+ break;
+ case CVT_95_addCCRAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addMSACtrlAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
+ break;
+ case CVT_95_addGPR32NonZeroAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addGPR32ZeroAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
+ break;
+ case CVT_95_addCOP0AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
+ break;
+ case CVT_regZERO_64:
+ Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
+ break;
+ case CVT_95_addACC64DSPAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_1_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
+ break;
+ case CVT_regRA:
+ Inst.addOperand(MCOperand::createReg(Mips::RA));
+ break;
+ case CVT_regRA_64:
+ Inst.addOperand(MCOperand::createReg(Mips::RA_64));
+ break;
+ case CVT_95_addMicroMipsMemOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
+ break;
+ case CVT_95_addCOP3AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_32_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
+ break;
+ case CVT_95_addStrictlyAFGR64AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addStrictlyFGR64AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addStrictlyFGR32AsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
+ break;
+ case CVT_95_addRegListOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
+ break;
+ case CVT_ConvertXWPOperands:
+ ConvertXWPOperands(Inst, Operands);
+ break;
+ case CVT_regAC0:
+ Inst.addOperand(MCOperand::createReg(Mips::AC0));
+ break;
+ case CVT_95_addMovePRegPairOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addMovePRegPairOperands(Inst, 2);
+ break;
+ case CVT_95_addGPRMM16AsmRegMovePOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
+ break;
+ case CVT_95_addHI32DSPAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addLO32DSPAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
+ break;
+ case CVT_regS0:
+ Inst.addOperand(MCOperand::createReg(Mips::S0));
+ break;
+ case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
+ break;
+ case CVT_95_addHWRegsAsmRegOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
+ break;
+ case CVT_95_addGPRMM16AsmRegZeroOperands:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
+ break;
+ case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
+ break;
+ case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
+ static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
+ break;
+ case CVT_imm_95_2:
+ Inst.addOperand(MCOperand::createImm(2));
+ break;
+ case CVT_imm_95_6:
+ Inst.addOperand(MCOperand::createImm(6));
+ break;
+ case CVT_imm_95_4:
+ Inst.addOperand(MCOperand::createImm(4));
+ break;
+ case CVT_imm_95_5:
+ Inst.addOperand(MCOperand::createImm(5));
+ break;
+ case CVT_imm_95_31:
+ Inst.addOperand(MCOperand::createImm(31));
+ break;
+ }
+ }
+}
+
+void MipsAsmParser::
+convertToMapAndConstraints(unsigned Kind,
+ const OperandVector &Operands) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ unsigned NumMCOperands = 0;
+ const uint8_t *Converter = ConversionTable[Kind];
+ for (const uint8_t *p = Converter; *p; p+= 2) {
+ switch (*p) {
+ default: llvm_unreachable("invalid conversion entry!");
+ case CVT_Reg:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("r");
+ ++NumMCOperands;
+ break;
+ case CVT_Tied:
+ ++NumMCOperands;
+ break;
+ case CVT_95_addGPR32AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addAFGR64AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addFGR64AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addFGR32AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addSImmOperands_LT_32_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addMSA128AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addSImmOperands_LT_16_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_Reg:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("r");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addImmOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addGPRMM16AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addUImmOperands_LT_16_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addGPR64AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_regZERO:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_regFCC0:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addFCCAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addCOP2AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_imm_95_0:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addMemOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 2;
+ break;
+ case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addCCRAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addMSACtrlAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addGPR32NonZeroAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addGPR32ZeroAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addCOP0AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_regZERO_64:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addACC64DSPAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_1_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_regRA:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_regRA_64:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addMicroMipsMemOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 2;
+ break;
+ case CVT_95_addCOP3AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_32_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addStrictlyAFGR64AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addStrictlyFGR64AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addStrictlyFGR32AsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addRegListOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_regAC0:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addMovePRegPairOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 2;
+ break;
+ case CVT_95_addGPRMM16AsmRegMovePOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addHI32DSPAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addLO32DSPAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_regS0:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addHWRegsAsmRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addGPRMM16AsmRegZeroOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_imm_95_2:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_6:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_4:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_5:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_31:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ }
+ }
+}
+
+namespace {
+
+/// MatchClassKind - The kinds of classes which participate in
+/// instruction matching.
+enum MatchClassKind {
+ InvalidMatchClass = 0,
+ OptionalMatchClass = 1,
+ MCK__35_, // '#'
+ MCK__40_, // '('
+ MCK__41_, // ')'
+ MCK_0, // '0'
+ MCK_16, // '16'
+ MCK__91_, // '['
+ MCK__93_, // ']'
+ MCK_bit, // 'bit'
+ MCK_inst, // 'inst'
+ MCK_LAST_TOKEN = MCK_inst,
+ MCK_Reg15, // derived register class
+ MCK_Reg29, // derived register class
+ MCK_ACC128, // register class 'ACC128'
+ MCK_ACC64, // register class 'ACC64'
+ MCK_CPURAReg, // register class 'CPURAReg,RA'
+ MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
+ MCK_DSPCC, // register class 'DSPCC'
+ MCK_GP32, // register class 'GP32'
+ MCK_GP64, // register class 'GP64'
+ MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
+ MCK_HI32, // register class 'HI32'
+ MCK_HI64, // register class 'HI64'
+ MCK_LO32, // register class 'LO32'
+ MCK_LO64, // register class 'LO64'
+ MCK_PC, // register class 'PC'
+ MCK_SP64, // register class 'SP64'
+ MCK_Reg11, // derived register class
+ MCK_Reg26, // derived register class
+ MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
+ MCK_OCTEON_P, // register class 'OCTEON_P'
+ MCK_Reg4, // derived register class
+ MCK_Reg9, // derived register class
+ MCK_Reg19, // derived register class
+ MCK_Reg24, // derived register class
+ MCK_ACC64DSP, // register class 'ACC64DSP'
+ MCK_HI32DSP, // register class 'HI32DSP'
+ MCK_LO32DSP, // register class 'LO32DSP'
+ MCK_Reg8, // derived register class
+ MCK_Reg10, // derived register class
+ MCK_Reg23, // derived register class
+ MCK_Reg25, // derived register class
+ MCK_Reg17, // derived register class
+ MCK_Reg18, // derived register class
+ MCK_Reg21, // derived register class
+ MCK_Reg36, // derived register class
+ MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
+ MCK_FCC, // register class 'FCC'
+ MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
+ MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
+ MCK_MSACtrl, // register class 'MSACtrl'
+ MCK_Reg22, // derived register class
+ MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
+ MCK_Reg31, // derived register class
+ MCK_Reg34, // derived register class
+ MCK_Reg39, // derived register class
+ MCK_Reg42, // derived register class
+ MCK_AFGR64, // register class 'AFGR64'
+ MCK_MSA128WEvens, // register class 'MSA128WEvens'
+ MCK_Reg37, // derived register class
+ MCK_Reg20, // derived register class
+ MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
+ MCK_CCR, // register class 'CCR'
+ MCK_COP0, // register class 'COP0'
+ MCK_COP2, // register class 'COP2'
+ MCK_COP3, // register class 'COP3'
+ MCK_DSPR, // register class 'DSPR,GPR32'
+ MCK_FGR32, // register class 'FGR32,FGRCC'
+ MCK_FGR64, // register class 'FGR64'
+ MCK_FGRH32, // register class 'FGRH32'
+ MCK_GPR64, // register class 'GPR64'
+ MCK_HWRegs, // register class 'HWRegs'
+ MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
+ MCK_OddSP, // register class 'OddSP'
+ MCK_LAST_REGISTER = MCK_OddSP,
+ MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
+ MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
+ MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
+ MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
+ MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
+ MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
+ MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
+ MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
+ MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
+ MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand'
+ MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
+ MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
+ MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
+ MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
+ MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
+ MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
+ MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
+ MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
+ MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
+ MCK_Imm, // user defined class 'ImmAsmOperand'
+ MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
+ MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
+ MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
+ MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
+ MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
+ MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
+ MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
+ MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
+ MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand'
+ MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand'
+ MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand'
+ MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand'
+ MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand'
+ MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand'
+ MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand'
+ MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand'
+ MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
+ MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
+ MCK_Mem, // user defined class 'MipsMemAsmOperand'
+ MCK_MovePRegPair, // user defined class 'MovePRegPairAsmOperand'
+ MCK_RegList16, // user defined class 'RegList16AsmOperand'
+ MCK_RegList, // user defined class 'RegListAsmOperand'
+ MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
+ MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
+ MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
+ MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
+ MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
+ MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
+ MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
+ MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
+ MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
+ MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
+ MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
+ MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
+ MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
+ MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
+ MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
+ MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
+ MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
+ MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
+ MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
+ MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
+ MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
+ MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
+ MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
+ MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
+ MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
+ MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
+ MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
+ MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
+ MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
+ MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
+ MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
+ MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
+ MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
+ MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
+ MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
+ MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
+ MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
+ MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
+ MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
+ MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
+ MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
+ MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
+ MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
+ MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
+ MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
+ MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
+ NumMatchClassKinds
+};
+
+}
+
+static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
+ return MCTargetAsmParser::Match_InvalidOperand;
+}
+
+static MatchClassKind matchTokenString(StringRef Name) {
+ switch (Name.size()) {
+ default: break;
+ case 1: // 6 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case '#': // 1 string to match.
+ return MCK__35_; // "#"
+ case '(': // 1 string to match.
+ return MCK__40_; // "("
+ case ')': // 1 string to match.
+ return MCK__41_; // ")"
+ case '0': // 1 string to match.
+ return MCK_0; // "0"
+ case '[': // 1 string to match.
+ return MCK__91_; // "["
+ case ']': // 1 string to match.
+ return MCK__93_; // "]"
+ }
+ break;
+ case 2: // 1 string to match.
+ if (memcmp(Name.data()+0, "16", 2) != 0)
+ break;
+ return MCK_16; // "16"
+ case 3: // 1 string to match.
+ if (memcmp(Name.data()+0, "bit", 3) != 0)
+ break;
+ return MCK_bit; // "bit"
+ case 4: // 1 string to match.
+ if (memcmp(Name.data()+0, "inst", 4) != 0)
+ break;
+ return MCK_inst; // "inst"
+ }
+ return InvalidMatchClass;
+}
+
+/// isSubclass - Compute whether \p A is a subclass of \p B.
+static bool isSubclass(MatchClassKind A, MatchClassKind B) {
+ if (A == B)
+ return true;
+
+ switch (A) {
+ default:
+ return false;
+
+ case MCK_Reg15:
+ switch (B) {
+ default: return false;
+ case MCK_Reg19: return true;
+ case MCK_Reg17: return true;
+ case MCK_Reg18: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_Reg29:
+ switch (B) {
+ default: return false;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_ACC64:
+ return B == MCK_ACC64DSP;
+
+ case MCK_CPURAReg:
+ switch (B) {
+ default: return false;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_CPUSPReg:
+ switch (B) {
+ default: return false;
+ case MCK_CPU16RegsPlusSP: return true;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_GP32:
+ switch (B) {
+ default: return false;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_GP64:
+ switch (B) {
+ default: return false;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_GPR32ZERO:
+ switch (B) {
+ default: return false;
+ case MCK_Reg4: return true;
+ case MCK_GPRMM16MoveP: return true;
+ case MCK_GPRMM16Zero: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_HI32:
+ return B == MCK_HI32DSP;
+
+ case MCK_LO32:
+ return B == MCK_LO32DSP;
+
+ case MCK_SP64:
+ switch (B) {
+ default: return false;
+ case MCK_Reg22: return true;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_Reg11:
+ switch (B) {
+ default: return false;
+ case MCK_Reg4: return true;
+ case MCK_Reg9: return true;
+ case MCK_Reg8: return true;
+ case MCK_Reg10: return true;
+ case MCK_CPU16Regs: return true;
+ case MCK_GPRMM16MoveP: return true;
+ case MCK_GPRMM16Zero: return true;
+ case MCK_CPU16RegsPlusSP: return true;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_Reg26:
+ switch (B) {
+ default: return false;
+ case MCK_Reg19: return true;
+ case MCK_Reg24: return true;
+ case MCK_Reg23: return true;
+ case MCK_Reg25: return true;
+ case MCK_Reg17: return true;
+ case MCK_Reg18: return true;
+ case MCK_Reg21: return true;
+ case MCK_Reg22: return true;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_Reg4:
+ switch (B) {
+ default: return false;
+ case MCK_GPRMM16MoveP: return true;
+ case MCK_GPRMM16Zero: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_Reg9:
+ switch (B) {
+ default: return false;
+ case MCK_Reg10: return true;
+ case MCK_CPU16Regs: return true;
+ case MCK_GPRMM16MoveP: return true;
+ case MCK_CPU16RegsPlusSP: return true;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_Reg19:
+ switch (B) {
+ default: return false;
+ case MCK_Reg17: return true;
+ case MCK_Reg18: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_Reg24:
+ switch (B) {
+ default: return false;
+ case MCK_Reg25: return true;
+ case MCK_Reg18: return true;
+ case MCK_Reg21: return true;
+ case MCK_Reg22: return true;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_Reg8:
+ switch (B) {
+ default: return false;
+ case MCK_CPU16Regs: return true;
+ case MCK_GPRMM16Zero: return true;
+ case MCK_CPU16RegsPlusSP: return true;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_Reg10:
+ switch (B) {
+ default: return false;
+ case MCK_GPRMM16MoveP: return true;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_Reg23:
+ switch (B) {
+ default: return false;
+ case MCK_Reg17: return true;
+ case MCK_Reg21: return true;
+ case MCK_Reg22: return true;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_Reg25:
+ switch (B) {
+ default: return false;
+ case MCK_Reg18: return true;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_Reg17:
+ return B == MCK_GPR64;
+
+ case MCK_Reg18:
+ return B == MCK_GPR64;
+
+ case MCK_Reg21:
+ switch (B) {
+ default: return false;
+ case MCK_Reg22: return true;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_Reg36:
+ switch (B) {
+ default: return false;
+ case MCK_AFGR64: return true;
+ case MCK_Reg37: return true;
+ case MCK_OddSP: return true;
+ }
+
+ case MCK_CPU16Regs:
+ switch (B) {
+ default: return false;
+ case MCK_CPU16RegsPlusSP: return true;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_GPRMM16MoveP:
+ return B == MCK_DSPR;
+
+ case MCK_GPRMM16Zero:
+ return B == MCK_DSPR;
+
+ case MCK_Reg22:
+ switch (B) {
+ default: return false;
+ case MCK_Reg20: return true;
+ case MCK_GPR64: return true;
+ }
+
+ case MCK_CPU16RegsPlusSP:
+ switch (B) {
+ default: return false;
+ case MCK_GPR32NONZERO: return true;
+ case MCK_DSPR: return true;
+ }
+
+ case MCK_Reg31:
+ switch (B) {
+ default: return false;
+ case MCK_FGR32: return true;
+ case MCK_OddSP: return true;
+ }
+
+ case MCK_Reg34:
+ switch (B) {
+ default: return false;
+ case MCK_FGRH32: return true;
+ case MCK_OddSP: return true;
+ }
+
+ case MCK_Reg39:
+ switch (B) {
+ default: return false;
+ case MCK_Reg37: return true;
+ case MCK_FGR64: return true;
+ case MCK_OddSP: return true;
+ }
+
+ case MCK_Reg42:
+ return B == MCK_MSA128F16;
+
+ case MCK_MSA128WEvens:
+ return B == MCK_MSA128F16;
+
+ case MCK_Reg37:
+ return B == MCK_OddSP;
+
+ case MCK_Reg20:
+ return B == MCK_GPR64;
+
+ case MCK_GPR32NONZERO:
+ return B == MCK_DSPR;
+
+ case MCK_MemOffsetSimm10:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetSimm10_1:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetSimm10_2:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetSimm10_3:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetSimm11:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetSimm12:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetSimm16:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetSimm9:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetSimmPtr:
+ return B == MCK_Mem;
+
+ case MCK_MemOffsetUimm4:
+ return B == MCK_Mem;
+
+ case MCK_ConstantImmz:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm1_0: return true;
+ case MCK_ConstantUImm2_0: return true;
+ case MCK_ConstantUImm3_0: return true;
+ case MCK_ConstantSImm4_0: return true;
+ case MCK_ConstantUImm4_0: return true;
+ case MCK_ConstantSImm5_0: return true;
+ case MCK_ConstantUImm5_0: return true;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm1_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm2_0: return true;
+ case MCK_ConstantUImm3_0: return true;
+ case MCK_ConstantSImm4_0: return true;
+ case MCK_ConstantUImm4_0: return true;
+ case MCK_ConstantSImm5_0: return true;
+ case MCK_ConstantUImm5_0: return true;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm2_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm3_0: return true;
+ case MCK_ConstantSImm4_0: return true;
+ case MCK_ConstantUImm4_0: return true;
+ case MCK_ConstantSImm5_0: return true;
+ case MCK_ConstantUImm5_0: return true;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm2_1:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm3_0: return true;
+ case MCK_ConstantSImm4_0: return true;
+ case MCK_ConstantUImm4_0: return true;
+ case MCK_ConstantSImm5_0: return true;
+ case MCK_ConstantUImm5_0: return true;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm3_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantSImm4_0: return true;
+ case MCK_ConstantUImm4_0: return true;
+ case MCK_ConstantSImm5_0: return true;
+ case MCK_ConstantUImm5_0: return true;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantSImm4_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm4_0: return true;
+ case MCK_ConstantSImm5_0: return true;
+ case MCK_ConstantUImm5_0: return true;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm4_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantSImm5_0: return true;
+ case MCK_ConstantUImm5_0: return true;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantSImm5_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm5_0: return true;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm5_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm5_1: return true;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm5_1:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm5_Plus1_Report_UImm6:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm5_32_Norm: return true;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm5_32_Norm:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm5_32: return true;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm5_32:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm5_0_Report_UImm6: return true;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm5_0_Report_UImm6:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm5_33: return true;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm5_33:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImmRange2_64: return true;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImmRange2_64:
+ switch (B) {
+ default: return false;
+ case MCK_UImm5Lsl2: return true;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_UImm5Lsl2:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantSImm6_0: return true;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantSImm6_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm6_0: return true;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm6_0:
+ switch (B) {
+ default: return false;
+ case MCK_UImm6Lsl2: return true;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_UImm6Lsl2:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm7_0: return true;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm7_0:
+ switch (B) {
+ default: return false;
+ case MCK_UImm7_N1: return true;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_UImm7_N1:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm8_0: return true;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm8_0:
+ switch (B) {
+ default: return false;
+ case MCK_SImm7Lsl2: return true;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm7Lsl2:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantSImm9_0: return true;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantSImm9_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantSImm10_0: return true;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantSImm10_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm10_0: return true;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm10_0:
+ switch (B) {
+ default: return false;
+ case MCK_SImm10Lsl1: return true;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm10Lsl1:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantSImm11_0: return true;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantSImm11_0:
+ switch (B) {
+ default: return false;
+ case MCK_SImm10Lsl2: return true;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm10Lsl2:
+ switch (B) {
+ default: return false;
+ case MCK_SImm10Lsl3: return true;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm10Lsl3:
+ switch (B) {
+ default: return false;
+ case MCK_SImm16: return true;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm16:
+ switch (B) {
+ default: return false;
+ case MCK_SImm16_Relaxed: return true;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm16_Relaxed:
+ switch (B) {
+ default: return false;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_UImm16_AltRelaxed:
+ switch (B) {
+ default: return false;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_UImm16:
+ switch (B) {
+ default: return false;
+ case MCK_UImm16_Relaxed: return true;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm19Lsl2:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_UImm16_Relaxed:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm20_0: return true;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm20_0:
+ switch (B) {
+ default: return false;
+ case MCK_ConstantUImm26_0: return true;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_ConstantUImm26_0:
+ switch (B) {
+ default: return false;
+ case MCK_SImm32: return true;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm32:
+ switch (B) {
+ default: return false;
+ case MCK_SImm32_Relaxed: return true;
+ case MCK_UImm32_Coerced: return true;
+ }
+
+ case MCK_SImm32_Relaxed:
+ return B == MCK_UImm32_Coerced;
+ }
+}
+
+static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
+ MipsOperand &Operand = (MipsOperand&)GOp;
+ if (Kind == InvalidMatchClass)
+ return MCTargetAsmParser::Match_InvalidOperand;
+
+ if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
+ return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
+ MCTargetAsmParser::Match_Success :
+ MCTargetAsmParser::Match_InvalidOperand;
+
+ switch (Kind) {
+ default: break;
+ // 'ACC64DSPAsmReg' class
+ case MCK_ACC64DSPAsmReg: {
+ DiagnosticPredicate DP(Operand.isACCAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'AFGR64AsmReg' class
+ case MCK_AFGR64AsmReg: {
+ DiagnosticPredicate DP(Operand.isFGRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'CCRAsmReg' class
+ case MCK_CCRAsmReg: {
+ DiagnosticPredicate DP(Operand.isCCRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'COP0AsmReg' class
+ case MCK_COP0AsmReg: {
+ DiagnosticPredicate DP(Operand.isCOP0AsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'COP2AsmReg' class
+ case MCK_COP2AsmReg: {
+ DiagnosticPredicate DP(Operand.isCOP2AsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'COP3AsmReg' class
+ case MCK_COP3AsmReg: {
+ DiagnosticPredicate DP(Operand.isCOP3AsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'FCCAsmReg' class
+ case MCK_FCCAsmReg: {
+ DiagnosticPredicate DP(Operand.isFCCAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'FGR32AsmReg' class
+ case MCK_FGR32AsmReg: {
+ DiagnosticPredicate DP(Operand.isFGRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'FGR64AsmReg' class
+ case MCK_FGR64AsmReg: {
+ DiagnosticPredicate DP(Operand.isFGRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'FGRH32AsmReg' class
+ case MCK_FGRH32AsmReg: {
+ DiagnosticPredicate DP(Operand.isFGRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'GPR32AsmReg' class
+ case MCK_GPR32AsmReg: {
+ DiagnosticPredicate DP(Operand.isGPRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'GPR32NonZeroAsmReg' class
+ case MCK_GPR32NonZeroAsmReg: {
+ DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'GPR32ZeroAsmReg' class
+ case MCK_GPR32ZeroAsmReg: {
+ DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'GPR64AsmReg' class
+ case MCK_GPR64AsmReg: {
+ DiagnosticPredicate DP(Operand.isGPRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'GPRMM16AsmReg' class
+ case MCK_GPRMM16AsmReg: {
+ DiagnosticPredicate DP(Operand.isMM16AsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'GPRMM16AsmRegMoveP' class
+ case MCK_GPRMM16AsmRegMoveP: {
+ DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'GPRMM16AsmRegZero' class
+ case MCK_GPRMM16AsmRegZero: {
+ DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'HI32DSPAsmReg' class
+ case MCK_HI32DSPAsmReg: {
+ DiagnosticPredicate DP(Operand.isACCAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'HWRegsAsmReg' class
+ case MCK_HWRegsAsmReg: {
+ DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'Imm' class
+ case MCK_Imm: {
+ DiagnosticPredicate DP(Operand.isImm());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'LO32DSPAsmReg' class
+ case MCK_LO32DSPAsmReg: {
+ DiagnosticPredicate DP(Operand.isACCAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'MSA128AsmReg' class
+ case MCK_MSA128AsmReg: {
+ DiagnosticPredicate DP(Operand.isMSA128AsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'MSACtrlAsmReg' class
+ case MCK_MSACtrlAsmReg: {
+ DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'MicroMipsMemGP' class
+ case MCK_MicroMipsMemGP: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'MicroMipsMem' class
+ case MCK_MicroMipsMem: {
+ DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'MicroMipsMemSP' class
+ case MCK_MicroMipsMemSP: {
+ DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'InvNum' class
+ case MCK_InvNum: {
+ DiagnosticPredicate DP(Operand.isInvNum());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'JumpTarget' class
+ case MCK_JumpTarget: {
+ DiagnosticPredicate DP(Operand.isImm());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'MemOffsetSimm10' class
+ case MCK_MemOffsetSimm10: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImm10;
+ break;
+ }
+ // 'MemOffsetSimm10_1' class
+ case MCK_MemOffsetSimm10_1: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImm10Lsl1;
+ break;
+ }
+ // 'MemOffsetSimm10_2' class
+ case MCK_MemOffsetSimm10_2: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImm10Lsl2;
+ break;
+ }
+ // 'MemOffsetSimm10_3' class
+ case MCK_MemOffsetSimm10_3: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImm10Lsl3;
+ break;
+ }
+ // 'MemOffsetSimm11' class
+ case MCK_MemOffsetSimm11: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImm11;
+ break;
+ }
+ // 'MemOffsetSimm12' class
+ case MCK_MemOffsetSimm12: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImm12;
+ break;
+ }
+ // 'MemOffsetSimm16' class
+ case MCK_MemOffsetSimm16: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImm16;
+ break;
+ }
+ // 'MemOffsetSimm9' class
+ case MCK_MemOffsetSimm9: {
+ DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImm9;
+ break;
+ }
+ // 'MemOffsetSimmPtr' class
+ case MCK_MemOffsetSimmPtr: {
+ DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_MemSImmPtr;
+ break;
+ }
+ // 'MemOffsetUimm4' class
+ case MCK_MemOffsetUimm4: {
+ DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'Mem' class
+ case MCK_Mem: {
+ DiagnosticPredicate DP(Operand.isMem());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'MovePRegPair' class
+ case MCK_MovePRegPair: {
+ DiagnosticPredicate DP(Operand.isMovePRegPair());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'RegList16' class
+ case MCK_RegList16: {
+ DiagnosticPredicate DP(Operand.isRegList16());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'RegList' class
+ case MCK_RegList: {
+ DiagnosticPredicate DP(Operand.isRegList());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'Simm19_Lsl2' class
+ case MCK_Simm19_Lsl2: {
+ DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm19_Lsl2;
+ break;
+ }
+ // 'StrictlyAFGR64AsmReg' class
+ case MCK_StrictlyAFGR64AsmReg: {
+ DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'StrictlyFGR32AsmReg' class
+ case MCK_StrictlyFGR32AsmReg: {
+ DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'StrictlyFGR64AsmReg' class
+ case MCK_StrictlyFGR64AsmReg: {
+ DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'ConstantImmz' class
+ case MCK_ConstantImmz: {
+ DiagnosticPredicate DP(Operand.isConstantImmz());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_Immz;
+ break;
+ }
+ // 'ConstantUImm1_0' class
+ case MCK_ConstantUImm1_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm1_0;
+ break;
+ }
+ // 'ConstantUImm2_0' class
+ case MCK_ConstantUImm2_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm2_0;
+ break;
+ }
+ // 'ConstantUImm2_1' class
+ case MCK_ConstantUImm2_1: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm2_1;
+ break;
+ }
+ // 'ConstantUImm3_0' class
+ case MCK_ConstantUImm3_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm3_0;
+ break;
+ }
+ // 'ConstantSImm4_0' class
+ case MCK_ConstantSImm4_0: {
+ DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm4_0;
+ break;
+ }
+ // 'ConstantUImm4_0' class
+ case MCK_ConstantUImm4_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm4_0;
+ break;
+ }
+ // 'ConstantSImm5_0' class
+ case MCK_ConstantSImm5_0: {
+ DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm5_0;
+ break;
+ }
+ // 'ConstantUImm5_0' class
+ case MCK_ConstantUImm5_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm5_0;
+ break;
+ }
+ // 'ConstantUImm5_1' class
+ case MCK_ConstantUImm5_1: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm5_1;
+ break;
+ }
+ // 'ConstantUImm5_Plus1_Report_UImm6' class
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm5_1;
+ break;
+ }
+ // 'ConstantUImm5_32_Norm' class
+ case MCK_ConstantUImm5_32_Norm: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm5_32;
+ break;
+ }
+ // 'ConstantUImm5_32' class
+ case MCK_ConstantUImm5_32: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm5_32;
+ break;
+ }
+ // 'ConstantUImm5_0_Report_UImm6' class
+ case MCK_ConstantUImm5_0_Report_UImm6: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm5_0_Report_UImm6;
+ break;
+ }
+ // 'ConstantUImm5_33' class
+ case MCK_ConstantUImm5_33: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm5_33;
+ break;
+ }
+ // 'ConstantUImmRange2_64' class
+ case MCK_ConstantUImmRange2_64: {
+ DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImmRange2_64;
+ break;
+ }
+ // 'UImm5Lsl2' class
+ case MCK_UImm5Lsl2: {
+ DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm5_Lsl2;
+ break;
+ }
+ // 'ConstantSImm6_0' class
+ case MCK_ConstantSImm6_0: {
+ DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm6_0;
+ break;
+ }
+ // 'ConstantUImm6_0' class
+ case MCK_ConstantUImm6_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm6_0;
+ break;
+ }
+ // 'UImm6Lsl2' class
+ case MCK_UImm6Lsl2: {
+ DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm6_Lsl2;
+ break;
+ }
+ // 'ConstantUImm7_0' class
+ case MCK_ConstantUImm7_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm7_0;
+ break;
+ }
+ // 'UImm7_N1' class
+ case MCK_UImm7_N1: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm7_N1;
+ break;
+ }
+ // 'ConstantUImm8_0' class
+ case MCK_ConstantUImm8_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm8_0;
+ break;
+ }
+ // 'SImm7Lsl2' class
+ case MCK_SImm7Lsl2: {
+ DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm7_Lsl2;
+ break;
+ }
+ // 'ConstantSImm9_0' class
+ case MCK_ConstantSImm9_0: {
+ DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm9_0;
+ break;
+ }
+ // 'ConstantSImm10_0' class
+ case MCK_ConstantSImm10_0: {
+ DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm10_0;
+ break;
+ }
+ // 'ConstantUImm10_0' class
+ case MCK_ConstantUImm10_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm10_0;
+ break;
+ }
+ // 'SImm10Lsl1' class
+ case MCK_SImm10Lsl1: {
+ DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm10_Lsl1;
+ break;
+ }
+ // 'ConstantSImm11_0' class
+ case MCK_ConstantSImm11_0: {
+ DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm11_0;
+ break;
+ }
+ // 'SImm10Lsl2' class
+ case MCK_SImm10Lsl2: {
+ DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm10_Lsl2;
+ break;
+ }
+ // 'SImm10Lsl3' class
+ case MCK_SImm10Lsl3: {
+ DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm10_Lsl3;
+ break;
+ }
+ // 'SImm16' class
+ case MCK_SImm16: {
+ DiagnosticPredicate DP(Operand.isSImm<16>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm16;
+ break;
+ }
+ // 'SImm16_Relaxed' class
+ case MCK_SImm16_Relaxed: {
+ DiagnosticPredicate DP(Operand.isAnyImm<16>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm16_Relaxed;
+ break;
+ }
+ // 'UImm16_AltRelaxed' class
+ case MCK_UImm16_AltRelaxed: {
+ DiagnosticPredicate DP(Operand.isUImm<16>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm16_AltRelaxed;
+ break;
+ }
+ // 'UImm16' class
+ case MCK_UImm16: {
+ DiagnosticPredicate DP(Operand.isUImm<16>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm16;
+ break;
+ }
+ // 'SImm19Lsl2' class
+ case MCK_SImm19Lsl2: {
+ DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm19_Lsl2;
+ break;
+ }
+ // 'UImm16_Relaxed' class
+ case MCK_UImm16_Relaxed: {
+ DiagnosticPredicate DP(Operand.isAnyImm<16>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm16_Relaxed;
+ break;
+ }
+ // 'ConstantUImm20_0' class
+ case MCK_ConstantUImm20_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm20_0;
+ break;
+ }
+ // 'ConstantUImm26_0' class
+ case MCK_ConstantUImm26_0: {
+ DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm26_0;
+ break;
+ }
+ // 'SImm32' class
+ case MCK_SImm32: {
+ DiagnosticPredicate DP(Operand.isSImm<32>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm32;
+ break;
+ }
+ // 'SImm32_Relaxed' class
+ case MCK_SImm32_Relaxed: {
+ DiagnosticPredicate DP(Operand.isAnyImm<33>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_SImm32_Relaxed;
+ break;
+ }
+ // 'UImm32_Coerced' class
+ case MCK_UImm32_Coerced: {
+ DiagnosticPredicate DP(Operand.isSImm<33>());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return MipsAsmParser::Match_UImm32_Coerced;
+ break;
+ }
+ } // end switch (Kind)
+
+ if (Operand.isReg()) {
+ MatchClassKind OpKind;
+ switch (Operand.getReg()) {
+ default: OpKind = InvalidMatchClass; break;
+ case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
+ case Mips::AT: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::V0: OpKind = MCK_Reg11; break;
+ case Mips::V1: OpKind = MCK_Reg11; break;
+ case Mips::A0: OpKind = MCK_Reg8; break;
+ case Mips::A1: OpKind = MCK_Reg8; break;
+ case Mips::A2: OpKind = MCK_Reg8; break;
+ case Mips::A3: OpKind = MCK_Reg8; break;
+ case Mips::T0: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T1: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T2: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T3: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T4: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T5: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T6: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T7: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::S0: OpKind = MCK_Reg9; break;
+ case Mips::S1: OpKind = MCK_Reg11; break;
+ case Mips::S2: OpKind = MCK_Reg10; break;
+ case Mips::S3: OpKind = MCK_Reg10; break;
+ case Mips::S4: OpKind = MCK_Reg10; break;
+ case Mips::S5: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::S6: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::S7: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T8: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::T9: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::K0: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::K1: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::GP: OpKind = MCK_GP32; break;
+ case Mips::SP: OpKind = MCK_CPUSPReg; break;
+ case Mips::FP: OpKind = MCK_GPR32NONZERO; break;
+ case Mips::RA: OpKind = MCK_CPURAReg; break;
+ case Mips::ZERO_64: OpKind = MCK_Reg15; break;
+ case Mips::AT_64: OpKind = MCK_Reg20; break;
+ case Mips::V0_64: OpKind = MCK_Reg26; break;
+ case Mips::V1_64: OpKind = MCK_Reg26; break;
+ case Mips::A0_64: OpKind = MCK_Reg23; break;
+ case Mips::A1_64: OpKind = MCK_Reg23; break;
+ case Mips::A2_64: OpKind = MCK_Reg23; break;
+ case Mips::A3_64: OpKind = MCK_Reg23; break;
+ case Mips::T0_64: OpKind = MCK_Reg20; break;
+ case Mips::T1_64: OpKind = MCK_Reg20; break;
+ case Mips::T2_64: OpKind = MCK_Reg20; break;
+ case Mips::T3_64: OpKind = MCK_Reg20; break;
+ case Mips::T4_64: OpKind = MCK_Reg20; break;
+ case Mips::T5_64: OpKind = MCK_Reg20; break;
+ case Mips::T6_64: OpKind = MCK_Reg20; break;
+ case Mips::T7_64: OpKind = MCK_Reg20; break;
+ case Mips::S0_64: OpKind = MCK_Reg24; break;
+ case Mips::S1_64: OpKind = MCK_Reg26; break;
+ case Mips::S2_64: OpKind = MCK_Reg25; break;
+ case Mips::S3_64: OpKind = MCK_Reg25; break;
+ case Mips::S4_64: OpKind = MCK_Reg25; break;
+ case Mips::S5_64: OpKind = MCK_Reg20; break;
+ case Mips::S6_64: OpKind = MCK_Reg20; break;
+ case Mips::S7_64: OpKind = MCK_Reg20; break;
+ case Mips::T8_64: OpKind = MCK_Reg20; break;
+ case Mips::T9_64: OpKind = MCK_Reg20; break;
+ case Mips::K0_64: OpKind = MCK_Reg20; break;
+ case Mips::K1_64: OpKind = MCK_Reg20; break;
+ case Mips::GP_64: OpKind = MCK_GP64; break;
+ case Mips::SP_64: OpKind = MCK_SP64; break;
+ case Mips::FP_64: OpKind = MCK_Reg20; break;
+ case Mips::RA_64: OpKind = MCK_Reg29; break;
+ case Mips::F0: OpKind = MCK_FGR32; break;
+ case Mips::F1: OpKind = MCK_Reg31; break;
+ case Mips::F2: OpKind = MCK_FGR32; break;
+ case Mips::F3: OpKind = MCK_Reg31; break;
+ case Mips::F4: OpKind = MCK_FGR32; break;
+ case Mips::F5: OpKind = MCK_Reg31; break;
+ case Mips::F6: OpKind = MCK_FGR32; break;
+ case Mips::F7: OpKind = MCK_Reg31; break;
+ case Mips::F8: OpKind = MCK_FGR32; break;
+ case Mips::F9: OpKind = MCK_Reg31; break;
+ case Mips::F10: OpKind = MCK_FGR32; break;
+ case Mips::F11: OpKind = MCK_Reg31; break;
+ case Mips::F12: OpKind = MCK_FGR32; break;
+ case Mips::F13: OpKind = MCK_Reg31; break;
+ case Mips::F14: OpKind = MCK_FGR32; break;
+ case Mips::F15: OpKind = MCK_Reg31; break;
+ case Mips::F16: OpKind = MCK_FGR32; break;
+ case Mips::F17: OpKind = MCK_Reg31; break;
+ case Mips::F18: OpKind = MCK_FGR32; break;
+ case Mips::F19: OpKind = MCK_Reg31; break;
+ case Mips::F20: OpKind = MCK_FGR32; break;
+ case Mips::F21: OpKind = MCK_Reg31; break;
+ case Mips::F22: OpKind = MCK_FGR32; break;
+ case Mips::F23: OpKind = MCK_Reg31; break;
+ case Mips::F24: OpKind = MCK_FGR32; break;
+ case Mips::F25: OpKind = MCK_Reg31; break;
+ case Mips::F26: OpKind = MCK_FGR32; break;
+ case Mips::F27: OpKind = MCK_Reg31; break;
+ case Mips::F28: OpKind = MCK_FGR32; break;
+ case Mips::F29: OpKind = MCK_Reg31; break;
+ case Mips::F30: OpKind = MCK_FGR32; break;
+ case Mips::F31: OpKind = MCK_Reg31; break;
+ case Mips::F_HI0: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI1: OpKind = MCK_Reg34; break;
+ case Mips::F_HI2: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI3: OpKind = MCK_Reg34; break;
+ case Mips::F_HI4: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI5: OpKind = MCK_Reg34; break;
+ case Mips::F_HI6: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI7: OpKind = MCK_Reg34; break;
+ case Mips::F_HI8: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI9: OpKind = MCK_Reg34; break;
+ case Mips::F_HI10: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI11: OpKind = MCK_Reg34; break;
+ case Mips::F_HI12: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI13: OpKind = MCK_Reg34; break;
+ case Mips::F_HI14: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI15: OpKind = MCK_Reg34; break;
+ case Mips::F_HI16: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI17: OpKind = MCK_Reg34; break;
+ case Mips::F_HI18: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI19: OpKind = MCK_Reg34; break;
+ case Mips::F_HI20: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI21: OpKind = MCK_Reg34; break;
+ case Mips::F_HI22: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI23: OpKind = MCK_Reg34; break;
+ case Mips::F_HI24: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI25: OpKind = MCK_Reg34; break;
+ case Mips::F_HI26: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI27: OpKind = MCK_Reg34; break;
+ case Mips::F_HI28: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI29: OpKind = MCK_Reg34; break;
+ case Mips::F_HI30: OpKind = MCK_FGRH32; break;
+ case Mips::F_HI31: OpKind = MCK_Reg34; break;
+ case Mips::D0: OpKind = MCK_AFGR64; break;
+ case Mips::D1: OpKind = MCK_Reg36; break;
+ case Mips::D2: OpKind = MCK_AFGR64; break;
+ case Mips::D3: OpKind = MCK_Reg36; break;
+ case Mips::D4: OpKind = MCK_AFGR64; break;
+ case Mips::D5: OpKind = MCK_Reg36; break;
+ case Mips::D6: OpKind = MCK_AFGR64; break;
+ case Mips::D7: OpKind = MCK_Reg36; break;
+ case Mips::D8: OpKind = MCK_AFGR64; break;
+ case Mips::D9: OpKind = MCK_Reg36; break;
+ case Mips::D10: OpKind = MCK_AFGR64; break;
+ case Mips::D11: OpKind = MCK_Reg36; break;
+ case Mips::D12: OpKind = MCK_AFGR64; break;
+ case Mips::D13: OpKind = MCK_Reg36; break;
+ case Mips::D14: OpKind = MCK_AFGR64; break;
+ case Mips::D15: OpKind = MCK_Reg36; break;
+ case Mips::D0_64: OpKind = MCK_FGR64; break;
+ case Mips::D1_64: OpKind = MCK_Reg39; break;
+ case Mips::D2_64: OpKind = MCK_FGR64; break;
+ case Mips::D3_64: OpKind = MCK_Reg39; break;
+ case Mips::D4_64: OpKind = MCK_FGR64; break;
+ case Mips::D5_64: OpKind = MCK_Reg39; break;
+ case Mips::D6_64: OpKind = MCK_FGR64; break;
+ case Mips::D7_64: OpKind = MCK_Reg39; break;
+ case Mips::D8_64: OpKind = MCK_FGR64; break;
+ case Mips::D9_64: OpKind = MCK_Reg39; break;
+ case Mips::D10_64: OpKind = MCK_FGR64; break;
+ case Mips::D11_64: OpKind = MCK_Reg39; break;
+ case Mips::D12_64: OpKind = MCK_FGR64; break;
+ case Mips::D13_64: OpKind = MCK_Reg39; break;
+ case Mips::D14_64: OpKind = MCK_FGR64; break;
+ case Mips::D15_64: OpKind = MCK_Reg39; break;
+ case Mips::D16_64: OpKind = MCK_FGR64; break;
+ case Mips::D17_64: OpKind = MCK_Reg39; break;
+ case Mips::D18_64: OpKind = MCK_FGR64; break;
+ case Mips::D19_64: OpKind = MCK_Reg39; break;
+ case Mips::D20_64: OpKind = MCK_FGR64; break;
+ case Mips::D21_64: OpKind = MCK_Reg39; break;
+ case Mips::D22_64: OpKind = MCK_FGR64; break;
+ case Mips::D23_64: OpKind = MCK_Reg39; break;
+ case Mips::D24_64: OpKind = MCK_FGR64; break;
+ case Mips::D25_64: OpKind = MCK_Reg39; break;
+ case Mips::D26_64: OpKind = MCK_FGR64; break;
+ case Mips::D27_64: OpKind = MCK_Reg39; break;
+ case Mips::D28_64: OpKind = MCK_FGR64; break;
+ case Mips::D29_64: OpKind = MCK_Reg39; break;
+ case Mips::D30_64: OpKind = MCK_FGR64; break;
+ case Mips::D31_64: OpKind = MCK_Reg39; break;
+ case Mips::W0: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W1: OpKind = MCK_Reg42; break;
+ case Mips::W2: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W3: OpKind = MCK_Reg42; break;
+ case Mips::W4: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W5: OpKind = MCK_Reg42; break;
+ case Mips::W6: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W7: OpKind = MCK_Reg42; break;
+ case Mips::W8: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W9: OpKind = MCK_Reg42; break;
+ case Mips::W10: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W11: OpKind = MCK_Reg42; break;
+ case Mips::W12: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W13: OpKind = MCK_Reg42; break;
+ case Mips::W14: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W15: OpKind = MCK_Reg42; break;
+ case Mips::W16: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W17: OpKind = MCK_Reg42; break;
+ case Mips::W18: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W19: OpKind = MCK_Reg42; break;
+ case Mips::W20: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W21: OpKind = MCK_Reg42; break;
+ case Mips::W22: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W23: OpKind = MCK_Reg42; break;
+ case Mips::W24: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W25: OpKind = MCK_Reg42; break;
+ case Mips::W26: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W27: OpKind = MCK_Reg42; break;
+ case Mips::W28: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W29: OpKind = MCK_Reg42; break;
+ case Mips::W30: OpKind = MCK_MSA128WEvens; break;
+ case Mips::W31: OpKind = MCK_Reg42; break;
+ case Mips::HI0: OpKind = MCK_HI32; break;
+ case Mips::HI1: OpKind = MCK_HI32DSP; break;
+ case Mips::HI2: OpKind = MCK_HI32DSP; break;
+ case Mips::HI3: OpKind = MCK_HI32DSP; break;
+ case Mips::LO0: OpKind = MCK_LO32; break;
+ case Mips::LO1: OpKind = MCK_LO32DSP; break;
+ case Mips::LO2: OpKind = MCK_LO32DSP; break;
+ case Mips::LO3: OpKind = MCK_LO32DSP; break;
+ case Mips::HI0_64: OpKind = MCK_HI64; break;
+ case Mips::LO0_64: OpKind = MCK_LO64; break;
+ case Mips::FCR0: OpKind = MCK_CCR; break;
+ case Mips::FCR1: OpKind = MCK_CCR; break;
+ case Mips::FCR2: OpKind = MCK_CCR; break;
+ case Mips::FCR3: OpKind = MCK_CCR; break;
+ case Mips::FCR4: OpKind = MCK_CCR; break;
+ case Mips::FCR5: OpKind = MCK_CCR; break;
+ case Mips::FCR6: OpKind = MCK_CCR; break;
+ case Mips::FCR7: OpKind = MCK_CCR; break;
+ case Mips::FCR8: OpKind = MCK_CCR; break;
+ case Mips::FCR9: OpKind = MCK_CCR; break;
+ case Mips::FCR10: OpKind = MCK_CCR; break;
+ case Mips::FCR11: OpKind = MCK_CCR; break;
+ case Mips::FCR12: OpKind = MCK_CCR; break;
+ case Mips::FCR13: OpKind = MCK_CCR; break;
+ case Mips::FCR14: OpKind = MCK_CCR; break;
+ case Mips::FCR15: OpKind = MCK_CCR; break;
+ case Mips::FCR16: OpKind = MCK_CCR; break;
+ case Mips::FCR17: OpKind = MCK_CCR; break;
+ case Mips::FCR18: OpKind = MCK_CCR; break;
+ case Mips::FCR19: OpKind = MCK_CCR; break;
+ case Mips::FCR20: OpKind = MCK_CCR; break;
+ case Mips::FCR21: OpKind = MCK_CCR; break;
+ case Mips::FCR22: OpKind = MCK_CCR; break;
+ case Mips::FCR23: OpKind = MCK_CCR; break;
+ case Mips::FCR24: OpKind = MCK_CCR; break;
+ case Mips::FCR25: OpKind = MCK_CCR; break;
+ case Mips::FCR26: OpKind = MCK_CCR; break;
+ case Mips::FCR27: OpKind = MCK_CCR; break;
+ case Mips::FCR28: OpKind = MCK_CCR; break;
+ case Mips::FCR29: OpKind = MCK_CCR; break;
+ case Mips::FCR30: OpKind = MCK_CCR; break;
+ case Mips::FCR31: OpKind = MCK_CCR; break;
+ case Mips::FCC0: OpKind = MCK_FCC; break;
+ case Mips::FCC1: OpKind = MCK_FCC; break;
+ case Mips::FCC2: OpKind = MCK_FCC; break;
+ case Mips::FCC3: OpKind = MCK_FCC; break;
+ case Mips::FCC4: OpKind = MCK_FCC; break;
+ case Mips::FCC5: OpKind = MCK_FCC; break;
+ case Mips::FCC6: OpKind = MCK_FCC; break;
+ case Mips::FCC7: OpKind = MCK_FCC; break;
+ case Mips::COP00: OpKind = MCK_COP0; break;
+ case Mips::COP01: OpKind = MCK_COP0; break;
+ case Mips::COP02: OpKind = MCK_COP0; break;
+ case Mips::COP03: OpKind = MCK_COP0; break;
+ case Mips::COP04: OpKind = MCK_COP0; break;
+ case Mips::COP05: OpKind = MCK_COP0; break;
+ case Mips::COP06: OpKind = MCK_COP0; break;
+ case Mips::COP07: OpKind = MCK_COP0; break;
+ case Mips::COP08: OpKind = MCK_COP0; break;
+ case Mips::COP09: OpKind = MCK_COP0; break;
+ case Mips::COP010: OpKind = MCK_COP0; break;
+ case Mips::COP011: OpKind = MCK_COP0; break;
+ case Mips::COP012: OpKind = MCK_COP0; break;
+ case Mips::COP013: OpKind = MCK_COP0; break;
+ case Mips::COP014: OpKind = MCK_COP0; break;
+ case Mips::COP015: OpKind = MCK_COP0; break;
+ case Mips::COP016: OpKind = MCK_COP0; break;
+ case Mips::COP017: OpKind = MCK_COP0; break;
+ case Mips::COP018: OpKind = MCK_COP0; break;
+ case Mips::COP019: OpKind = MCK_COP0; break;
+ case Mips::COP020: OpKind = MCK_COP0; break;
+ case Mips::COP021: OpKind = MCK_COP0; break;
+ case Mips::COP022: OpKind = MCK_COP0; break;
+ case Mips::COP023: OpKind = MCK_COP0; break;
+ case Mips::COP024: OpKind = MCK_COP0; break;
+ case Mips::COP025: OpKind = MCK_COP0; break;
+ case Mips::COP026: OpKind = MCK_COP0; break;
+ case Mips::COP027: OpKind = MCK_COP0; break;
+ case Mips::COP028: OpKind = MCK_COP0; break;
+ case Mips::COP029: OpKind = MCK_COP0; break;
+ case Mips::COP030: OpKind = MCK_COP0; break;
+ case Mips::COP031: OpKind = MCK_COP0; break;
+ case Mips::COP20: OpKind = MCK_COP2; break;
+ case Mips::COP21: OpKind = MCK_COP2; break;
+ case Mips::COP22: OpKind = MCK_COP2; break;
+ case Mips::COP23: OpKind = MCK_COP2; break;
+ case Mips::COP24: OpKind = MCK_COP2; break;
+ case Mips::COP25: OpKind = MCK_COP2; break;
+ case Mips::COP26: OpKind = MCK_COP2; break;
+ case Mips::COP27: OpKind = MCK_COP2; break;
+ case Mips::COP28: OpKind = MCK_COP2; break;
+ case Mips::COP29: OpKind = MCK_COP2; break;
+ case Mips::COP210: OpKind = MCK_COP2; break;
+ case Mips::COP211: OpKind = MCK_COP2; break;
+ case Mips::COP212: OpKind = MCK_COP2; break;
+ case Mips::COP213: OpKind = MCK_COP2; break;
+ case Mips::COP214: OpKind = MCK_COP2; break;
+ case Mips::COP215: OpKind = MCK_COP2; break;
+ case Mips::COP216: OpKind = MCK_COP2; break;
+ case Mips::COP217: OpKind = MCK_COP2; break;
+ case Mips::COP218: OpKind = MCK_COP2; break;
+ case Mips::COP219: OpKind = MCK_COP2; break;
+ case Mips::COP220: OpKind = MCK_COP2; break;
+ case Mips::COP221: OpKind = MCK_COP2; break;
+ case Mips::COP222: OpKind = MCK_COP2; break;
+ case Mips::COP223: OpKind = MCK_COP2; break;
+ case Mips::COP224: OpKind = MCK_COP2; break;
+ case Mips::COP225: OpKind = MCK_COP2; break;
+ case Mips::COP226: OpKind = MCK_COP2; break;
+ case Mips::COP227: OpKind = MCK_COP2; break;
+ case Mips::COP228: OpKind = MCK_COP2; break;
+ case Mips::COP229: OpKind = MCK_COP2; break;
+ case Mips::COP230: OpKind = MCK_COP2; break;
+ case Mips::COP231: OpKind = MCK_COP2; break;
+ case Mips::COP30: OpKind = MCK_COP3; break;
+ case Mips::COP31: OpKind = MCK_COP3; break;
+ case Mips::COP32: OpKind = MCK_COP3; break;
+ case Mips::COP33: OpKind = MCK_COP3; break;
+ case Mips::COP34: OpKind = MCK_COP3; break;
+ case Mips::COP35: OpKind = MCK_COP3; break;
+ case Mips::COP36: OpKind = MCK_COP3; break;
+ case Mips::COP37: OpKind = MCK_COP3; break;
+ case Mips::COP38: OpKind = MCK_COP3; break;
+ case Mips::COP39: OpKind = MCK_COP3; break;
+ case Mips::COP310: OpKind = MCK_COP3; break;
+ case Mips::COP311: OpKind = MCK_COP3; break;
+ case Mips::COP312: OpKind = MCK_COP3; break;
+ case Mips::COP313: OpKind = MCK_COP3; break;
+ case Mips::COP314: OpKind = MCK_COP3; break;
+ case Mips::COP315: OpKind = MCK_COP3; break;
+ case Mips::COP316: OpKind = MCK_COP3; break;
+ case Mips::COP317: OpKind = MCK_COP3; break;
+ case Mips::COP318: OpKind = MCK_COP3; break;
+ case Mips::COP319: OpKind = MCK_COP3; break;
+ case Mips::COP320: OpKind = MCK_COP3; break;
+ case Mips::COP321: OpKind = MCK_COP3; break;
+ case Mips::COP322: OpKind = MCK_COP3; break;
+ case Mips::COP323: OpKind = MCK_COP3; break;
+ case Mips::COP324: OpKind = MCK_COP3; break;
+ case Mips::COP325: OpKind = MCK_COP3; break;
+ case Mips::COP326: OpKind = MCK_COP3; break;
+ case Mips::COP327: OpKind = MCK_COP3; break;
+ case Mips::COP328: OpKind = MCK_COP3; break;
+ case Mips::COP329: OpKind = MCK_COP3; break;
+ case Mips::COP330: OpKind = MCK_COP3; break;
+ case Mips::COP331: OpKind = MCK_COP3; break;
+ case Mips::PC: OpKind = MCK_PC; break;
+ case Mips::HWR0: OpKind = MCK_HWRegs; break;
+ case Mips::HWR1: OpKind = MCK_HWRegs; break;
+ case Mips::HWR2: OpKind = MCK_HWRegs; break;
+ case Mips::HWR3: OpKind = MCK_HWRegs; break;
+ case Mips::HWR4: OpKind = MCK_HWRegs; break;
+ case Mips::HWR5: OpKind = MCK_HWRegs; break;
+ case Mips::HWR6: OpKind = MCK_HWRegs; break;
+ case Mips::HWR7: OpKind = MCK_HWRegs; break;
+ case Mips::HWR8: OpKind = MCK_HWRegs; break;
+ case Mips::HWR9: OpKind = MCK_HWRegs; break;
+ case Mips::HWR10: OpKind = MCK_HWRegs; break;
+ case Mips::HWR11: OpKind = MCK_HWRegs; break;
+ case Mips::HWR12: OpKind = MCK_HWRegs; break;
+ case Mips::HWR13: OpKind = MCK_HWRegs; break;
+ case Mips::HWR14: OpKind = MCK_HWRegs; break;
+ case Mips::HWR15: OpKind = MCK_HWRegs; break;
+ case Mips::HWR16: OpKind = MCK_HWRegs; break;
+ case Mips::HWR17: OpKind = MCK_HWRegs; break;
+ case Mips::HWR18: OpKind = MCK_HWRegs; break;
+ case Mips::HWR19: OpKind = MCK_HWRegs; break;
+ case Mips::HWR20: OpKind = MCK_HWRegs; break;
+ case Mips::HWR21: OpKind = MCK_HWRegs; break;
+ case Mips::HWR22: OpKind = MCK_HWRegs; break;
+ case Mips::HWR23: OpKind = MCK_HWRegs; break;
+ case Mips::HWR24: OpKind = MCK_HWRegs; break;
+ case Mips::HWR25: OpKind = MCK_HWRegs; break;
+ case Mips::HWR26: OpKind = MCK_HWRegs; break;
+ case Mips::HWR27: OpKind = MCK_HWRegs; break;
+ case Mips::HWR28: OpKind = MCK_HWRegs; break;
+ case Mips::HWR29: OpKind = MCK_HWRegs; break;
+ case Mips::HWR30: OpKind = MCK_HWRegs; break;
+ case Mips::HWR31: OpKind = MCK_HWRegs; break;
+ case Mips::AC0: OpKind = MCK_ACC64; break;
+ case Mips::AC1: OpKind = MCK_ACC64DSP; break;
+ case Mips::AC2: OpKind = MCK_ACC64DSP; break;
+ case Mips::AC3: OpKind = MCK_ACC64DSP; break;
+ case Mips::AC0_64: OpKind = MCK_ACC128; break;
+ case Mips::DSPCCond: OpKind = MCK_DSPCC; break;
+ case Mips::MSAIR: OpKind = MCK_MSACtrl; break;
+ case Mips::MSACSR: OpKind = MCK_MSACtrl; break;
+ case Mips::MSAAccess: OpKind = MCK_MSACtrl; break;
+ case Mips::MSASave: OpKind = MCK_MSACtrl; break;
+ case Mips::MSAModify: OpKind = MCK_MSACtrl; break;
+ case Mips::MSARequest: OpKind = MCK_MSACtrl; break;
+ case Mips::MSAMap: OpKind = MCK_MSACtrl; break;
+ case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break;
+ case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break;
+ case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break;
+ case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break;
+ case Mips::P0: OpKind = MCK_OCTEON_P; break;
+ case Mips::P1: OpKind = MCK_OCTEON_P; break;
+ case Mips::P2: OpKind = MCK_OCTEON_P; break;
+ }
+ return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
+ getDiagKindFromRegisterClass(Kind);
+ }
+
+ if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
+ return getDiagKindFromRegisterClass(Kind);
+
+ return MCTargetAsmParser::Match_InvalidOperand;
+}
+
+#ifndef NDEBUG
+const char *getMatchClassName(MatchClassKind Kind) {
+ switch (Kind) {
+ case InvalidMatchClass: return "InvalidMatchClass";
+ case OptionalMatchClass: return "OptionalMatchClass";
+ case MCK__35_: return "MCK__35_";
+ case MCK__40_: return "MCK__40_";
+ case MCK__41_: return "MCK__41_";
+ case MCK_0: return "MCK_0";
+ case MCK_16: return "MCK_16";
+ case MCK__91_: return "MCK__91_";
+ case MCK__93_: return "MCK__93_";
+ case MCK_bit: return "MCK_bit";
+ case MCK_inst: return "MCK_inst";
+ case MCK_Reg15: return "MCK_Reg15";
+ case MCK_Reg29: return "MCK_Reg29";
+ case MCK_ACC128: return "MCK_ACC128";
+ case MCK_ACC64: return "MCK_ACC64";
+ case MCK_CPURAReg: return "MCK_CPURAReg";
+ case MCK_CPUSPReg: return "MCK_CPUSPReg";
+ case MCK_DSPCC: return "MCK_DSPCC";
+ case MCK_GP32: return "MCK_GP32";
+ case MCK_GP64: return "MCK_GP64";
+ case MCK_GPR32ZERO: return "MCK_GPR32ZERO";
+ case MCK_HI32: return "MCK_HI32";
+ case MCK_HI64: return "MCK_HI64";
+ case MCK_LO32: return "MCK_LO32";
+ case MCK_LO64: return "MCK_LO64";
+ case MCK_PC: return "MCK_PC";
+ case MCK_SP64: return "MCK_SP64";
+ case MCK_Reg11: return "MCK_Reg11";
+ case MCK_Reg26: return "MCK_Reg26";
+ case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL";
+ case MCK_OCTEON_P: return "MCK_OCTEON_P";
+ case MCK_Reg4: return "MCK_Reg4";
+ case MCK_Reg9: return "MCK_Reg9";
+ case MCK_Reg19: return "MCK_Reg19";
+ case MCK_Reg24: return "MCK_Reg24";
+ case MCK_ACC64DSP: return "MCK_ACC64DSP";
+ case MCK_HI32DSP: return "MCK_HI32DSP";
+ case MCK_LO32DSP: return "MCK_LO32DSP";
+ case MCK_Reg8: return "MCK_Reg8";
+ case MCK_Reg10: return "MCK_Reg10";
+ case MCK_Reg23: return "MCK_Reg23";
+ case MCK_Reg25: return "MCK_Reg25";
+ case MCK_Reg17: return "MCK_Reg17";
+ case MCK_Reg18: return "MCK_Reg18";
+ case MCK_Reg21: return "MCK_Reg21";
+ case MCK_Reg36: return "MCK_Reg36";
+ case MCK_CPU16Regs: return "MCK_CPU16Regs";
+ case MCK_FCC: return "MCK_FCC";
+ case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP";
+ case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero";
+ case MCK_MSACtrl: return "MCK_MSACtrl";
+ case MCK_Reg22: return "MCK_Reg22";
+ case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP";
+ case MCK_Reg31: return "MCK_Reg31";
+ case MCK_Reg34: return "MCK_Reg34";
+ case MCK_Reg39: return "MCK_Reg39";
+ case MCK_Reg42: return "MCK_Reg42";
+ case MCK_AFGR64: return "MCK_AFGR64";
+ case MCK_MSA128WEvens: return "MCK_MSA128WEvens";
+ case MCK_Reg37: return "MCK_Reg37";
+ case MCK_Reg20: return "MCK_Reg20";
+ case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO";
+ case MCK_CCR: return "MCK_CCR";
+ case MCK_COP0: return "MCK_COP0";
+ case MCK_COP2: return "MCK_COP2";
+ case MCK_COP3: return "MCK_COP3";
+ case MCK_DSPR: return "MCK_DSPR";
+ case MCK_FGR32: return "MCK_FGR32";
+ case MCK_FGR64: return "MCK_FGR64";
+ case MCK_FGRH32: return "MCK_FGRH32";
+ case MCK_GPR64: return "MCK_GPR64";
+ case MCK_HWRegs: return "MCK_HWRegs";
+ case MCK_MSA128F16: return "MCK_MSA128F16";
+ case MCK_OddSP: return "MCK_OddSP";
+ case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg";
+ case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg";
+ case MCK_CCRAsmReg: return "MCK_CCRAsmReg";
+ case MCK_COP0AsmReg: return "MCK_COP0AsmReg";
+ case MCK_COP2AsmReg: return "MCK_COP2AsmReg";
+ case MCK_COP3AsmReg: return "MCK_COP3AsmReg";
+ case MCK_FCCAsmReg: return "MCK_FCCAsmReg";
+ case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg";
+ case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg";
+ case MCK_FGRH32AsmReg: return "MCK_FGRH32AsmReg";
+ case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg";
+ case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg";
+ case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg";
+ case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg";
+ case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg";
+ case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP";
+ case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero";
+ case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg";
+ case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg";
+ case MCK_Imm: return "MCK_Imm";
+ case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg";
+ case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg";
+ case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg";
+ case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP";
+ case MCK_MicroMipsMem: return "MCK_MicroMipsMem";
+ case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP";
+ case MCK_InvNum: return "MCK_InvNum";
+ case MCK_JumpTarget: return "MCK_JumpTarget";
+ case MCK_MemOffsetSimm10: return "MCK_MemOffsetSimm10";
+ case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1";
+ case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2";
+ case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3";
+ case MCK_MemOffsetSimm11: return "MCK_MemOffsetSimm11";
+ case MCK_MemOffsetSimm12: return "MCK_MemOffsetSimm12";
+ case MCK_MemOffsetSimm16: return "MCK_MemOffsetSimm16";
+ case MCK_MemOffsetSimm9: return "MCK_MemOffsetSimm9";
+ case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr";
+ case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4";
+ case MCK_Mem: return "MCK_Mem";
+ case MCK_MovePRegPair: return "MCK_MovePRegPair";
+ case MCK_RegList16: return "MCK_RegList16";
+ case MCK_RegList: return "MCK_RegList";
+ case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2";
+ case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg";
+ case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg";
+ case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg";
+ case MCK_ConstantImmz: return "MCK_ConstantImmz";
+ case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0";
+ case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0";
+ case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1";
+ case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0";
+ case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0";
+ case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0";
+ case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0";
+ case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0";
+ case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1";
+ case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6";
+ case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm";
+ case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32";
+ case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6";
+ case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33";
+ case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64";
+ case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2";
+ case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0";
+ case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0";
+ case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2";
+ case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0";
+ case MCK_UImm7_N1: return "MCK_UImm7_N1";
+ case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0";
+ case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2";
+ case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0";
+ case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0";
+ case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0";
+ case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1";
+ case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0";
+ case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2";
+ case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3";
+ case MCK_SImm16: return "MCK_SImm16";
+ case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed";
+ case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed";
+ case MCK_UImm16: return "MCK_UImm16";
+ case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2";
+ case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed";
+ case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0";
+ case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0";
+ case MCK_SImm32: return "MCK_SImm32";
+ case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed";
+ case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced";
+ case NumMatchClassKinds: return "NumMatchClassKinds";
+ }
+ llvm_unreachable("unhandled MatchClassKind!");
+}
+
+#endif // NDEBUG
+uint64_t MipsAsmParser::
+ComputeAvailableFeatures(const FeatureBitset& FB) const {
+ uint64_t Features = 0;
+ if ((FB[Mips::FeatureMips2]))
+ Features |= Feature_HasMips2;
+ if ((FB[Mips::FeatureMips3_32]))
+ Features |= Feature_HasMips3_32;
+ if ((FB[Mips::FeatureMips3_32r2]))
+ Features |= Feature_HasMips3_32r2;
+ if ((FB[Mips::FeatureMips3]))
+ Features |= Feature_HasMips3;
+ if ((!FB[Mips::FeatureMips3]))
+ Features |= Feature_NotMips3;
+ if ((FB[Mips::FeatureMips4_32]))
+ Features |= Feature_HasMips4_32;
+ if ((!FB[Mips::FeatureMips4_32]))
+ Features |= Feature_NotMips4_32;
+ if ((FB[Mips::FeatureMips4_32r2]))
+ Features |= Feature_HasMips4_32r2;
+ if ((FB[Mips::FeatureMips5_32r2]))
+ Features |= Feature_HasMips5_32r2;
+ if ((FB[Mips::FeatureMips32]))
+ Features |= Feature_HasMips32;
+ if ((FB[Mips::FeatureMips32r2]))
+ Features |= Feature_HasMips32r2;
+ if ((FB[Mips::FeatureMips32r5]))
+ Features |= Feature_HasMips32r5;
+ if ((FB[Mips::FeatureMips32r6]))
+ Features |= Feature_HasMips32r6;
+ if ((!FB[Mips::FeatureMips32r6]))
+ Features |= Feature_NotMips32r6;
+ if ((FB[Mips::FeatureGP64Bit]))
+ Features |= Feature_IsGP64bit;
+ if ((!FB[Mips::FeatureGP64Bit]))
+ Features |= Feature_IsGP32bit;
+ if ((FB[Mips::FeaturePTR64Bit]))
+ Features |= Feature_IsPTR64bit;
+ if ((!FB[Mips::FeaturePTR64Bit]))
+ Features |= Feature_IsPTR32bit;
+ if ((FB[Mips::FeatureMips64]))
+ Features |= Feature_HasMips64;
+ if ((!FB[Mips::FeatureMips64]))
+ Features |= Feature_NotMips64;
+ if ((FB[Mips::FeatureMips64r2]))
+ Features |= Feature_HasMips64r2;
+ if ((FB[Mips::FeatureMips64r5]))
+ Features |= Feature_HasMips64r5;
+ if ((FB[Mips::FeatureMips64r6]))
+ Features |= Feature_HasMips64r6;
+ if ((!FB[Mips::FeatureMips64r6]))
+ Features |= Feature_NotMips64r6;
+ if ((FB[Mips::FeatureMips16]))
+ Features |= Feature_InMips16Mode;
+ if ((!FB[Mips::FeatureMips16]))
+ Features |= Feature_NotInMips16Mode;
+ if ((FB[Mips::FeatureCnMips]))
+ Features |= Feature_HasCnMips;
+ if ((!FB[Mips::FeatureCnMips]))
+ Features |= Feature_NotCnMips;
+ if ((FB[Mips::FeatureSym32]))
+ Features |= Feature_IsSym32;
+ if ((!FB[Mips::FeatureSym32]))
+ Features |= Feature_IsSym64;
+ if ((!FB[Mips::FeatureMips16]))
+ Features |= Feature_HasStdEnc;
+ if ((FB[Mips::FeatureMicroMips]))
+ Features |= Feature_InMicroMips;
+ if ((!FB[Mips::FeatureMicroMips]))
+ Features |= Feature_NotInMicroMips;
+ if ((FB[Mips::FeatureEVA]))
+ Features |= Feature_HasEVA;
+ if ((FB[Mips::FeatureMSA]))
+ Features |= Feature_HasMSA;
+ if ((!FB[Mips::FeatureMadd4]))
+ Features |= Feature_HasMadd4;
+ if ((FB[Mips::FeatureMT]))
+ Features |= Feature_HasMT;
+ if ((FB[Mips::FeatureUseIndirectJumpsHazard]))
+ Features |= Feature_UseIndirectJumpsHazard;
+ if ((!FB[Mips::FeatureUseIndirectJumpsHazard]))
+ Features |= Feature_NoIndirectJumpGuards;
+ if ((FB[Mips::FeatureCRC]))
+ Features |= Feature_HasCRC;
+ if ((FB[Mips::FeatureVirt]))
+ Features |= Feature_HasVirt;
+ if ((FB[Mips::FeatureGINV]))
+ Features |= Feature_HasGINV;
+ if ((FB[Mips::FeatureFP64Bit]))
+ Features |= Feature_IsFP64bit;
+ if ((!FB[Mips::FeatureFP64Bit]))
+ Features |= Feature_NotFP64bit;
+ if ((FB[Mips::FeatureSingleFloat]))
+ Features |= Feature_IsSingleFloat;
+ if ((!FB[Mips::FeatureSingleFloat]))
+ Features |= Feature_IsNotSingleFloat;
+ if ((!FB[Mips::FeatureSoftFloat]))
+ Features |= Feature_IsNotSoftFloat;
+ if ((FB[Mips::FeatureDSP]))
+ Features |= Feature_HasDSP;
+ if ((FB[Mips::FeatureDSPR2]))
+ Features |= Feature_HasDSPR2;
+ if ((FB[Mips::FeatureDSPR3]))
+ Features |= Feature_HasDSPR3;
+ return Features;
+}
+
+static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser,
+ unsigned Kind,
+ const OperandVector &Operands,
+ uint64_t &ErrorInfo) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ const uint8_t *Converter = ConversionTable[Kind];
+ for (const uint8_t *p = Converter; *p; p+= 2) {
+ switch (*p) {
+ case CVT_Tied: {
+ unsigned OpIdx = *(p+1);
+ assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
+ std::begin(TiedAsmOperandTable)) &&
+ "Tied operand not found");
+ unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
+ unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
+ if (OpndNum1 != OpndNum2) {
+ auto &SrcOp1 = Operands[OpndNum1];
+ auto &SrcOp2 = Operands[OpndNum2];
+ if (SrcOp1->isReg() && SrcOp2->isReg()) {
+ if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
+ ErrorInfo = OpndNum2;
+ return false;
+ }
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ return true;
+}
+
+static const char *const MnemonicTable =
+ "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a"
+ "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad"
+ "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t"
+ "addq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddqh_r.w\010"
+ "adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010adds_s.b\010adds_s.d\010"
+ "adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010adds_u.h\010adds_u.w\005"
+ "addsc\004addu\007addu.ph\007addu.qb\006addu16\taddu_s.ph\taddu_s.qb\010"
+ "adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv.h\006addv.w\007addvi.b"
+ "\007addvi.d\007addvi.h\007addvi.w\005addwc\005align\006aluipc\003and\005"
+ "and.v\005and16\004andi\006andi.b\006andi16\006append\010asub_s.b\010asu"
+ "b_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asub_u.d\010asub_u.h\010as"
+ "ub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007ave_s.h\007ave_s.w\007a"
+ "ve_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_s.b\010aver_s.d\010aver"
+ "_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver_u.h\010aver_u.w\001b\003"
+ "b16\005baddu\003bal\004balc\006balign\005bbit0\007bbit032\005bbit1\007b"
+ "bit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004bc1f\005bc1fl\006bc1nez\007"
+ "bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc\006bc2nez\007bc2nezc\006b"
+ "clr.b\006bclr.d\006bclr.h\006bclr.w\007bclri.b\007bclri.d\007bclri.h\007"
+ "bclri.w\003beq\004beqc\004beql\004beqz\006beqz16\007beqzalc\005beqzc\007"
+ "beqzc16\005beqzl\003bge\004bgec\004bgel\004bgeu\005bgeuc\005bgeul\004bg"
+ "ez\006bgezal\007bgezalc\007bgezall\007bgezals\005bgezc\005bgezl\003bgt\004"
+ "bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc\005bgtzc\005bgtzl\007binsl.b\007"
+ "binsl.d\007binsl.h\007binsl.w\010binsli.b\010binsli.d\010binsli.h\010bi"
+ "nsli.w\007binsr.b\007binsr.d\007binsr.h\007binsr.w\010binsri.b\010binsr"
+ "i.d\010binsri.h\010binsri.w\006bitrev\007bitswap\003ble\004blel\004bleu"
+ "\005bleul\004blez\007blezalc\005blezc\005blezl\003blt\004bltc\004bltl\004"
+ "bltu\005bltuc\005bltul\004bltz\006bltzal\007bltzalc\007bltzall\007bltza"
+ "ls\005bltzc\005bltzl\006bmnz.v\007bmnzi.b\005bmz.v\006bmzi.b\003bne\004"
+ "bnec\006bneg.b\006bneg.d\006bneg.h\006bneg.w\007bnegi.b\007bnegi.d\007b"
+ "negi.h\007bnegi.w\004bnel\004bnez\006bnez16\007bnezalc\005bnezc\007bnez"
+ "c16\005bnezl\004bnvc\005bnz.b\005bnz.d\005bnz.h\005bnz.v\005bnz.w\004bo"
+ "vc\010bposge32\tbposge32c\005break\007break16\006bsel.v\007bseli.b\006b"
+ "set.b\006bset.d\006bset.h\006bset.w\007bseti.b\007bseti.d\007bseti.h\007"
+ "bseti.w\005bteqz\005btnez\004bz.b\004bz.d\004bz.h\004bz.v\004bz.w\006c."
+ "eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le.d\006c.le.s\006c.lt.d\006c.lt."
+ "s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.ngl.s\010c.ngle.d\010c.ngle.s\007"
+ "c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole.s\007c.olt.d\007c.olt.s\007c.seq"
+ ".d\007c.seq.s\006c.sf.d\006c.sf.s\007c.ueq.d\007c.ueq.s\007c.ule.d\007c"
+ ".ule.s\007c.ult.d\007c.ult.s\006c.un.d\006c.un.s\005cache\006cachee\010"
+ "ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w.s\005ceq.b\005ceq.d\005ceq.h"
+ "\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006ceqi.w\004cfc1\004cfc2\006cf"
+ "cmsa\005cftc1\004cins\006cins32\007class.d\007class.s\007cle_s.b\007cle"
+ "_s.d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u.d\007cle_u.h\007cle_u.w\010"
+ "clei_s.b\010clei_s.d\010clei_s.h\010clei_s.w\010clei_u.b\010clei_u.d\010"
+ "clei_u.h\010clei_u.w\003clo\007clt_s.b\007clt_s.d\007clt_s.h\007clt_s.w"
+ "\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u.w\010clti_s.b\010clti_s.d\010"
+ "clti_s.h\010clti_s.w\010clti_u.b\010clti_u.d\010clti_u.h\010clti_u.w\003"
+ "clz\003cmp\010cmp.af.d\010cmp.af.s\010cmp.eq.d\tcmp.eq.ph\010cmp.eq.s\010"
+ "cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp.lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp"
+ ".saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq.s\tcmp.sle.d\tcmp.sle.s\tcmp.slt."
+ "d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\ncmp.sule.d\ncmp.sule.s\ncmp.sult."
+ "d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tcmp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tc"
+ "mp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp.un.d\010cmp.un.s\014cmpgdu.eq.qb\014"
+ "cmpgdu.le.qb\014cmpgdu.lt.qb\013cmpgu.eq.qb\013cmpgu.le.qb\013cmpgu.lt."
+ "qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\ncmpu.lt.qb\010copy_s.b\010copy_s.d\010"
+ "copy_s.h\010copy_s.w\010copy_u.b\010copy_u.h\010copy_u.w\006crc32b\007c"
+ "rc32cb\007crc32cd\007crc32ch\007crc32cw\006crc32d\006crc32h\006crc32w\004"
+ "ctc1\004ctc2\006ctcmsa\005cttc1\007cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt"
+ ".l.d\007cvt.l.s\007cvt.s.d\007cvt.s.l\007cvt.s.w\007cvt.w.d\007cvt.w.s\004"
+ "dadd\005daddi\006daddiu\005daddu\004dahi\006dalign\004dati\004daui\010d"
+ "bitswap\004dclo\004dclz\004ddiv\005ddivu\005deret\004dext\005dextm\005d"
+ "extu\002di\004dins\005dinsm\005dinsu\003div\005div.d\005div.s\007div_s."
+ "b\007div_s.d\007div_s.h\007div_s.w\007div_u.b\007div_u.d\007div_u.h\007"
+ "div_u.w\004divu\003dla\003dli\004dlsa\005dmfc0\005dmfc1\005dmfc2\006dmf"
+ "gc0\004dmod\005dmodu\003dmt\005dmtc0\005dmtc1\005dmtc2\006dmtgc0\004dmu"
+ "h\005dmuhu\004dmul\005dmulo\006dmulou\005dmult\006dmultu\005dmulu\004dn"
+ "eg\005dnegu\010dotp_s.d\010dotp_s.h\010dotp_s.w\010dotp_u.d\010dotp_u.h"
+ "\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd_s.h\tdpadd_s.w\tdpadd_u.d\td"
+ "padd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq_sa.l.w\014dpaqx_s.w.ph\015dp"
+ "aqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax.w.ph\004dpop\010dps.w.ph\013d"
+ "psq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015dpsqx_sa.w.ph\ndpsu.h.qbl\n"
+ "dpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\tdpsub_u.d\tdpsub_u.h\tdpsu"
+ "b_u.w\tdpsx.w.ph\004drem\005dremu\004drol\004dror\005drotr\007drotr32\006"
+ "drotrv\004dsbh\004dshd\004dsll\006dsll32\005dsllv\004dsra\006dsra32\005"
+ "dsrav\004dsrl\006dsrl32\005dsrlv\004dsub\005dsubi\005dsubu\003dvp\004dv"
+ "pe\003ehb\002ei\003emt\004eret\006eretnc\003evp\004evpe\003ext\004extp\006"
+ "extpdp\007extpdpv\005extpv\006extr.w\010extr_r.w\textr_rs.w\010extr_s.h"
+ "\007extrv.w\textrv_r.w\nextrv_rs.w\textrv_s.h\004exts\006exts32\006fadd"
+ ".d\006fadd.w\006fcaf.d\006fcaf.w\006fceq.d\006fceq.w\010fclass.d\010fcl"
+ "ass.w\006fcle.d\006fcle.w\006fclt.d\006fclt.w\006fcne.d\006fcne.w\006fc"
+ "or.d\006fcor.w\007fcueq.d\007fcueq.w\007fcule.d\007fcule.w\007fcult.d\007"
+ "fcult.w\006fcun.d\006fcun.w\007fcune.d\007fcune.w\006fdiv.d\006fdiv.w\007"
+ "fexdo.h\007fexdo.w\007fexp2.d\007fexp2.w\010fexupl.d\010fexupl.w\010fex"
+ "upr.d\010fexupr.w\tffint_s.d\tffint_s.w\tffint_u.d\tffint_u.w\006ffql.d"
+ "\006ffql.w\006ffqr.d\006ffqr.w\006fill.b\006fill.d\006fill.h\006fill.w\007"
+ "flog2.d\007flog2.w\tfloor.l.d\tfloor.l.s\tfloor.w.d\tfloor.w.s\007fmadd"
+ ".d\007fmadd.w\006fmax.d\006fmax.w\010fmax_a.d\010fmax_a.w\006fmin.d\006"
+ "fmin.w\010fmin_a.d\010fmin_a.w\007fmsub.d\007fmsub.w\006fmul.d\006fmul."
+ "w\004fork\006frcp.d\006frcp.w\007frint.d\007frint.w\010frsqrt.d\010frsq"
+ "rt.w\006fsaf.d\006fsaf.w\006fseq.d\006fseq.w\006fsle.d\006fsle.w\006fsl"
+ "t.d\006fslt.w\006fsne.d\006fsne.w\006fsor.d\006fsor.w\007fsqrt.d\007fsq"
+ "rt.w\006fsub.d\006fsub.w\007fsueq.d\007fsueq.w\007fsule.d\007fsule.w\007"
+ "fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d\007fsune.w\tftint_s.d"
+ "\tftint_s.w\tftint_u.d\tftint_u.w\005ftq.h\005ftq.w\nftrunc_s.d\nftrunc"
+ "_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005ginvt\010hadd_s.d\010hadd_s.h\010"
+ "hadd_s.w\010hadd_u.d\010hadd_u.h\010hadd_u.w\010hsub_s.d\010hsub_s.h\010"
+ "hsub_s.w\010hsub_u.d\010hsub_u.h\010hsub_u.w\007hypcall\007ilvev.b\007i"
+ "lvev.d\007ilvev.h\007ilvev.w\006ilvl.b\006ilvl.d\006ilvl.h\006ilvl.w\007"
+ "ilvod.b\007ilvod.d\007ilvod.h\007ilvod.w\006ilvr.b\006ilvr.d\006ilvr.h\006"
+ "ilvr.w\003ins\010insert.b\010insert.d\010insert.h\010insert.w\004insv\007"
+ "insve.b\007insve.d\007insve.h\007insve.w\001j\003jal\004jalr\007jalr.hb"
+ "\005jalrc\010jalrc.hb\005jalrs\007jalrs16\004jals\004jalx\005jialc\003j"
+ "ic\002jr\005jr.hb\004jr16\tjraddiusp\003jrc\005jrc16\njrcaddiusp\003l.d"
+ "\003l.s\002la\004lapc\002lb\003lbe\003lbu\005lbu16\004lbue\004lbux\002l"
+ "d\004ld.b\004ld.d\004ld.h\004ld.w\004ldc1\004ldc2\004ldc3\005ldi.b\005l"
+ "di.d\005ldi.h\005ldi.w\003ldl\004ldpc\003ldr\005ldxc1\002lh\003lhe\003l"
+ "hu\005lhu16\004lhue\003lhx\002li\004li.d\004li.s\004li16\002ll\003lld\003"
+ "lle\003lsa\003lui\005luxc1\002lw\004lw16\004lwc1\004lwc2\004lwc3\003lwe"
+ "\003lwl\004lwle\003lwm\005lwm16\005lwm32\003lwp\004lwpc\003lwr\004lwre\003"
+ "lwu\005lwupc\003lwx\005lwxc1\004lwxs\004madd\006madd.d\006madd.s\010mad"
+ "d_q.h\010madd_q.w\007maddf.d\007maddf.s\tmaddr_q.h\tmaddr_q.w\005maddu\007"
+ "maddv.b\007maddv.d\007maddv.h\007maddv.w\013maq_s.w.phl\013maq_s.w.phr\014"
+ "maq_sa.w.phl\014maq_sa.w.phr\005max.d\005max.s\007max_a.b\007max_a.d\007"
+ "max_a.h\007max_a.w\007max_s.b\007max_s.d\007max_s.h\007max_s.w\007max_u"
+ ".b\007max_u.d\007max_u.h\007max_u.w\006maxa.d\006maxa.s\010maxi_s.b\010"
+ "maxi_s.d\010maxi_s.h\010maxi_s.w\010maxi_u.b\010maxi_u.d\010maxi_u.h\010"
+ "maxi_u.w\004mfc0\004mfc1\004mfc2\005mfgc0\005mfhc0\005mfhc1\005mfhc2\006"
+ "mfhgc0\004mfhi\006mfhi16\004mflo\006mflo16\006mftacx\005mftc0\005mftc1\006"
+ "mftdsp\006mftgpr\006mfthc1\005mfthi\005mftlo\004mftr\005min.d\005min.s\007"
+ "min_a.b\007min_a.d\007min_a.h\007min_a.w\007min_s.b\007min_s.d\007min_s"
+ ".h\007min_s.w\007min_u.b\007min_u.d\007min_u.h\007min_u.w\006mina.d\006"
+ "mina.s\010mini_s.b\010mini_s.d\010mini_s.h\010mini_s.w\010mini_u.b\010m"
+ "ini_u.d\010mini_u.h\010mini_u.w\003mod\007mod_s.b\007mod_s.d\007mod_s.h"
+ "\007mod_s.w\007mod_u.b\007mod_u.d\007mod_u.h\007mod_u.w\006modsub\004mo"
+ "du\005mov.d\005mov.s\004move\006move.v\006move16\005movep\004movf\006mo"
+ "vf.d\006movf.s\004movn\006movn.d\006movn.s\004movt\006movt.d\006movt.s\004"
+ "movz\006movz.d\006movz.s\004msub\006msub.d\006msub.s\010msub_q.h\010msu"
+ "b_q.w\007msubf.d\007msubf.s\tmsubr_q.h\tmsubr_q.w\005msubu\007msubv.b\007"
+ "msubv.d\007msubv.h\007msubv.w\004mtc0\004mtc1\004mtc2\005mtgc0\005mthc0"
+ "\005mthc1\005mthc2\006mthgc0\004mthi\006mthlip\004mtlo\004mtm0\004mtm1\004"
+ "mtm2\004mtp0\004mtp1\004mtp2\006mttacx\005mttc0\005mttc1\006mttdsp\006m"
+ "ttgpr\006mtthc1\005mtthi\005mttlo\004mttr\003muh\004muhu\003mul\005mul."
+ "d\006mul.ph\005mul.s\007mul_q.h\007mul_q.w\010mul_s.ph\015muleq_s.w.phl"
+ "\015muleq_s.w.phr\016muleu_s.ph.qbl\016muleu_s.ph.qbr\004mulo\005mulou\n"
+ "mulq_rs.ph\tmulq_rs.w\tmulq_s.ph\010mulq_s.w\010mulr_q.h\010mulr_q.w\nm"
+ "ulsa.w.ph\015mulsaq_s.w.ph\004mult\005multu\004mulu\006mulv.b\006mulv.d"
+ "\006mulv.h\006mulv.w\003neg\005neg.d\005neg.s\004negu\006nloc.b\006nloc"
+ ".d\006nloc.h\006nloc.w\006nlzc.b\006nlzc.d\006nlzc.h\006nlzc.w\007nmadd"
+ ".d\007nmadd.s\007nmsub.d\007nmsub.s\003nop\003nor\005nor.v\006nori.b\003"
+ "not\005not16\002or\004or.v\004or16\003ori\005ori.b\tpackrl.ph\005pause\007"
+ "pckev.b\007pckev.d\007pckev.h\007pckev.w\007pckod.b\007pckod.d\007pckod"
+ ".h\007pckod.w\006pcnt.b\006pcnt.d\006pcnt.h\006pcnt.w\007pick.ph\007pic"
+ "k.qb\003pop\014preceq.w.phl\014preceq.w.phr\016precequ.ph.qbl\017preceq"
+ "u.ph.qbla\016precequ.ph.qbr\017precequ.ph.qbra\015preceu.ph.qbl\016prec"
+ "eu.ph.qbla\015preceu.ph.qbr\016preceu.ph.qbra\013precr.qb.ph\016precr_s"
+ "ra.ph.w\020precr_sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016precrq_rs"
+ ".ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007prepend\nraddu.w."
+ "qb\005rddsp\005rdhwr\006rdpgpr\007recip.d\007recip.s\003rem\004remu\007"
+ "repl.ph\007repl.qb\010replv.ph\010replv.qb\006rint.d\006rint.s\003rol\003"
+ "ror\004rotr\005rotrv\tround.l.d\tround.l.s\tround.w.d\tround.w.s\007rsq"
+ "rt.d\007rsqrt.s\003s.d\003s.s\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s"
+ ".w\007sat_u.b\007sat_u.d\007sat_u.h\007sat_u.w\002sb\004sb16\003sbe\002"
+ "sc\003scd\003sce\002sd\005sdbbp\007sdbbp16\004sdc1\004sdc2\004sdc3\003s"
+ "dl\003sdr\005sdxc1\003seb\003seh\005sel.d\005sel.s\006seleqz\010seleqz."
+ "d\010seleqz.s\006selnez\010selnez.d\010selnez.s\003seq\004seqi\003sgt\004"
+ "sgtu\002sh\004sh16\003she\005shf.b\005shf.h\005shf.w\005shilo\006shilov"
+ "\007shll.ph\007shll.qb\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\n"
+ "shllv_s.ph\tshllv_s.w\007shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010sh"
+ "ra_r.w\010shrav.ph\010shrav.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007sh"
+ "rl.ph\007shrl.qb\010shrlv.ph\010shrlv.qb\005sld.b\005sld.d\005sld.h\005"
+ "sld.w\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003sll\005sll.b\005sll.d\005"
+ "sll.h\005sll.w\005sll16\006slli.b\006slli.d\006slli.h\006slli.w\004sllv"
+ "\003slt\004slti\005sltiu\004sltu\003sne\004snei\007splat.b\007splat.d\007"
+ "splat.h\007splat.w\010splati.b\010splati.d\010splati.h\010splati.w\006s"
+ "qrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sra.h\005sra.w\006srai.b\006"
+ "srai.d\006srai.h\006srai.w\006srar.b\006srar.d\006srar.h\006srar.w\007s"
+ "rari.b\007srari.d\007srari.h\007srari.w\004srav\003srl\005srl.b\005srl."
+ "d\005srl.h\005srl.w\005srl16\006srli.b\006srli.d\006srli.h\006srli.w\006"
+ "srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlri.b\007srlri.d\007srlri.h\007"
+ "srlri.w\004srlv\005ssnop\004st.b\004st.d\004st.h\004st.w\003sub\005sub."
+ "d\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w\010subqh.ph\007subqh.w\nsu"
+ "bqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010subs_s.h\010subs_s.w\010"
+ "subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\nsubsus_u.b\nsubsus_u.d\ns"
+ "ubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\nsubsuu_s.h\nsubsuu_s.w\004"
+ "subu\007subu.ph\007subu.qb\006subu16\tsubu_s.ph\tsubu_s.qb\010subuh.qb\n"
+ "subuh_r.qb\006subv.b\006subv.d\006subv.h\006subv.w\007subvi.b\007subvi."
+ "d\007subvi.h\007subvi.w\005suxc1\002sw\004sw16\004swc1\004swc2\004swc3\003"
+ "swe\003swl\004swle\003swm\005swm16\005swm32\003swp\003swr\004swre\005sw"
+ "xc1\004sync\005synci\nsynciobdma\005syncs\005syncw\006syncws\007syscall"
+ "\003teq\004teqi\003tge\004tgei\005tgeiu\004tgeu\007tlbginv\010tlbginvf\005"
+ "tlbgp\005tlbgr\006tlbgwi\006tlbgwr\006tlbinv\007tlbinvf\004tlbp\004tlbr"
+ "\005tlbwi\005tlbwr\003tlt\004tlti\005tltiu\004tltu\003tne\004tnei\ttrun"
+ "c.l.d\ttrunc.l.s\ttrunc.w.d\ttrunc.w.s\003ulh\004ulhu\003ulw\003ush\003"
+ "usw\006v3mulu\004vmm0\005vmulu\006vshf.b\006vshf.d\006vshf.h\006vshf.w\004"
+ "wait\005wrdsp\006wrpgpr\004wsbh\003xor\005xor.v\005xor16\004xori\006xor"
+ "i.b\005yield";
+
+namespace {
+ struct MatchEntry {
+ uint16_t Mnemonic;
+ uint16_t Opcode;
+ uint16_t ConvertFn;
+ uint64_t RequiredFeatures;
+ uint8_t Classes[8];
+ StringRef getMnemonic() const {
+ return StringRef(MnemonicTable + Mnemonic + 1,
+ MnemonicTable[Mnemonic]);
+ }
+ };
+
+ // Predicate for searching for an opcode.
+ struct LessOpcode {
+ bool operator()(const MatchEntry &LHS, StringRef RHS) {
+ return LHS.getMnemonic() < RHS;
+ }
+ bool operator()(StringRef LHS, const MatchEntry &RHS) {
+ return LHS < RHS.getMnemonic();
+ }
+ bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
+ return LHS.getMnemonic() < RHS.getMnemonic();
+ }
+ };
+} // end anonymous namespace.
+
+static const MatchEntry MatchTable0[] = {
+ { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 55 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 55 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
+ { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
+ { 98 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, },
+ { 98 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
+ { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
+ { 98 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, },
+ { 98 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
+ { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
+ { 98 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 98 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
+ { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
+ { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, },
+ { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, },
+ { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
+ { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, },
+ { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, },
+ { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 173 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 173 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 182 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 182 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 201 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 201 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 211 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 220 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 229 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 238 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 247 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 256 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 265 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 274 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 283 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 292 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 301 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 310 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 325 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 330 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 330 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 346 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 353 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 353 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 373 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 373 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 393 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 400 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 407 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 414 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 421 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 429 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
+ { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
+ { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 472 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
+ { 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 482 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 493 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
+ { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
+ { 507 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 507 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 514 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 523 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 532 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 541 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 550 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 559 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 568 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 577 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 596 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 604 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 612 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 620 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 628 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 636 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 644 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 652 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 660 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 669 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 678 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 687 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 696 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 705 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 714 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 723 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 732 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
+ { 732 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget }, },
+ { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, 0, { MCK_JumpTarget }, },
+ { 732 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 734 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
+ { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, },
+ { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 744 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
+ { 744 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_JumpTarget }, },
+ { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, },
+ { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
+ { 753 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
+ { 753 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
+ { 760 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
+ { 760 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
+ { 766 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
+ { 774 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
+ { 774 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
+ { 780 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
+ { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
+ { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
+ { 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
+ { 803 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
+ { 811 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 811 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
+ { 811 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
+ { 811 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
+ { 816 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 816 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
+ { 822 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
+ { 829 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
+ { 837 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 837 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, },
+ { 837 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
+ { 837 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
+ { 842 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 842 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
+ { 848 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
+ { 855 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
+ { 863 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
+ { 870 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
+ { 878 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 885 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 892 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 899 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 906 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 914 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 922 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 930 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 938 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 938 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 942 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 942 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 942 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 947 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 947 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 952 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
+ { 952 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 952 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 952 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 957 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
+ { 957 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
+ { 964 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 964 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 972 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 972 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 972 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 972 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 978 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
+ { 986 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 992 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 996 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 996 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 996 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1001 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1001 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1006 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1011 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1017 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1017 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1023 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1023 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1028 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1028 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1035 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1035 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1043 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1051 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1059 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1059 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1059 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1065 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1071 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1075 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1075 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1080 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1085 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1085 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1091 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1091 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1096 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1096 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1104 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1104 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1104 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1110 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1116 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1124 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1132 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1140 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1148 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 1157 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 1166 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 1175 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 1184 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1192 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1200 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1208 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1216 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 1225 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 1234 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 1243 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 1252 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 1252 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 1259 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 1259 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 1267 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1271 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1271 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1276 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1281 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1281 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1287 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1287 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1292 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1292 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1300 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1300 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1300 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1306 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1316 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1321 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1321 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1331 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1331 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1331 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1337 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1337 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1343 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1343 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1348 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1348 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1355 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1355 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1363 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1371 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1379 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1379 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1379 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1385 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1391 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1398 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 1406 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1412 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 1419 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1419 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1423 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1423 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1423 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1428 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1435 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1442 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1449 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1456 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 1464 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 1472 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 1480 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 1488 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1488 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
+ { 1493 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
+ { 1493 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1493 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1493 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 1498 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
+ { 1498 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
+ { 1505 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1505 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1513 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1513 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1513 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1513 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 1519 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
+ { 1527 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1533 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1533 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1538 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1544 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1550 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1556 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1562 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1568 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1568 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 1573 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasDSP, { MCK_JumpTarget }, },
+ { 1573 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, Feature_HasDSP|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 1582 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasDSPR3, { MCK_JumpTarget }, },
+ { 1592 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 1592 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, Feature_InMicroMips, { }, },
+ { 1592 /* break */, Mips::Break16, Convert_NoOperands, Feature_InMips16Mode, { MCK_0 }, },
+ { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
+ { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
+ { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
+ { 1592 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
+ { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
+ { 1598 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm4_0 }, },
+ { 1598 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm4_0 }, },
+ { 1606 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1613 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 1621 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1628 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1635 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1642 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 1649 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 1657 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 1665 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 1673 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 1681 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, },
+ { 1681 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 1687 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, },
+ { 1687 /* btnez */, Mips::Btnez16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 1693 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1698 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1703 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1708 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1713 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
+ { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1732 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1732 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1732 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1732 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1738 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1738 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1751 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1751 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1955 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1955 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
+ { 1962 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
+ { 1962 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
+ { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
+ { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
+ { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
+ { 1975 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1975 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 1984 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 1984 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 1993 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 1993 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 1993 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 1993 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 2002 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2011 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2017 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2023 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2029 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2035 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2042 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2049 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2056 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2063 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
+ { 2063 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
+ { 2068 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
+ { 2073 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, },
+ { 2080 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
+ { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
+ { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
+ { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
+ { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
+ { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
+ { 2098 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2098 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2106 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2106 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2114 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2122 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2130 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2138 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2146 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2154 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2162 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2170 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2178 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2187 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2196 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2205 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2214 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 2223 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 2232 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 2241 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 2250 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2250 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2250 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2250 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2254 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2262 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2270 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2278 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2286 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2294 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2302 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2310 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 2318 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2327 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2336 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2345 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 2354 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 2363 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 2372 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 2381 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 2390 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2390 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2390 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2390 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2394 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 2398 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2398 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2407 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2407 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2444 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2444 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2463 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2463 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2472 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2472 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2491 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2491 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2726 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2726 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 2735 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2735 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2819 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
+ { 2819 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2857 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
+ { 2866 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
+ { 2875 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
+ { 2884 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
+ { 2893 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
+ { 2902 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
+ { 2911 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
+ { 2920 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2927 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2935 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2943 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2951 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2959 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2966 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2973 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 2980 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
+ { 2980 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
+ { 2985 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
+ { 2990 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, },
+ { 2997 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3003 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3003 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3011 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3011 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3011 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3011 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3019 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3019 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3019 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3019 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3027 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3027 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3027 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3035 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3035 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3035 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3043 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 3043 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 3043 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 3043 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 3051 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 3051 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 3059 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3059 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3059 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3067 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 3067 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 3067 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 3067 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 3075 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3075 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3075 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3083 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3083 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
+ { 3083 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3083 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
+ { 3088 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
+ { 3088 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
+ { 3094 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
+ { 3094 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
+ { 3101 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3101 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
+ { 3101 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3101 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
+ { 3107 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
+ { 3112 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
+ { 3119 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
+ { 3124 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
+ { 3129 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3138 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3138 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3143 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3143 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3148 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3148 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 3148 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3148 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3148 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3148 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
+ { 3153 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3153 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 3153 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3153 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3153 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3153 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
+ { 3159 /* deret */, Mips::DERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { }, },
+ { 3159 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 3159 /* deret */, Mips::DERET_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 3165 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
+ { 3165 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
+ { 3165 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, },
+ { 3170 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
+ { 3176 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
+ { 3182 /* di */, Mips::DI, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, },
+ { 3182 /* di */, Mips::DI_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 3182 /* di */, Mips::DI_MM, Convert__regZERO, Feature_InMicroMips, { }, },
+ { 3182 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 3182 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 3182 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
+ { 3185 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
+ { 3185 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
+ { 3185 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, },
+ { 3190 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
+ { 3196 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
+ { 3202 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3202 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
+ { 3202 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
+ { 3202 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
+ { 3202 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 3202 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3202 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3202 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3202 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3202 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
+ { 3202 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3206 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 3206 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 3206 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3206 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3212 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3212 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3212 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 3218 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3226 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3234 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3242 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3250 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3258 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3266 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3274 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3282 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3282 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
+ { 3282 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
+ { 3282 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
+ { 3282 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 3282 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3282 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3282 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3282 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3282 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3282 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
+ { 3287 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 3287 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, 0, { MCK_GPR64AsmReg, MCK_Mem }, },
+ { 3291 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 3295 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
+ { 3295 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
+ { 3300 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
+ { 3300 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 3306 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3312 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
+ { 3312 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
+ { 3312 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
+ { 3318 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
+ { 3318 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 3325 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3330 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3336 /* dmt */, Mips::DMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, },
+ { 3336 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 3340 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
+ { 3340 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 3346 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
+ { 3352 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
+ { 3352 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
+ { 3352 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
+ { 3358 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
+ { 3358 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 3365 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3370 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3376 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3376 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3376 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3376 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3376 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
+ { 3381 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3387 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3394 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3400 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3407 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3413 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
+ { 3413 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3418 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
+ { 3418 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3424 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3433 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3442 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3451 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3460 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3469 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3478 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3478 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3487 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3497 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3507 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3517 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3527 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3537 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3547 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3547 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3559 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3559 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3571 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3571 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3584 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3584 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3598 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3598 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3609 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3609 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3620 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3620 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3630 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
+ { 3630 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3635 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3635 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3644 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3644 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3656 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3656 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3668 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3668 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3681 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3681 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3695 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3695 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3706 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3706 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3717 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3727 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3737 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3747 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3757 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3767 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 3777 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3777 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3787 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3787 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
+ { 3787 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3787 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
+ { 3792 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3792 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
+ { 3792 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3792 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
+ { 3798 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3798 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 3798 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3798 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 3803 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3803 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 3803 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 3803 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 3808 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
+ { 3808 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
+ { 3814 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
+ { 3814 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
+ { 3822 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3829 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3834 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3839 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3839 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
+ { 3839 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3839 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
+ { 3844 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
+ { 3844 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
+ { 3851 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3857 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
+ { 3857 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3857 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
+ { 3862 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
+ { 3862 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
+ { 3869 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3875 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3875 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
+ { 3875 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3875 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
+ { 3880 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
+ { 3880 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
+ { 3887 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
+ { 3893 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3893 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
+ { 3893 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3893 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
+ { 3898 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
+ { 3898 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
+ { 3904 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3904 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, },
+ { 3904 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 3904 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
+ { 3910 /* dvp */, Mips::DVP, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r6, { }, },
+ { 3910 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 3910 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 3910 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 3914 /* dvpe */, Mips::DVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, },
+ { 3914 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 3919 /* ehb */, Mips::EHB, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 3919 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 3919 /* ehb */, Mips::EHB_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 3923 /* ei */, Mips::EI, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, },
+ { 3923 /* ei */, Mips::EI_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 3923 /* ei */, Mips::EI_MM, Convert__regZERO, Feature_InMicroMips, { }, },
+ { 3923 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 3923 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 3923 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
+ { 3926 /* emt */, Mips::EMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, },
+ { 3926 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 3930 /* eret */, Mips::ERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, { }, },
+ { 3930 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 3930 /* eret */, Mips::ERET_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 3935 /* eretnc */, Mips::ERETNC, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_NotInMicroMips, { }, },
+ { 3935 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 3942 /* evp */, Mips::EVP, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r6, { }, },
+ { 3942 /* evp */, Mips::EVP_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 3942 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 3942 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 3946 /* evpe */, Mips::EVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, },
+ { 3946 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 3951 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
+ { 3951 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
+ { 3951 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
+ { 3955 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3955 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3960 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3960 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3967 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 3967 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 3975 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 3975 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 3981 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3981 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3988 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3988 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3997 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 3997 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 4007 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 4007 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
+ { 4016 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 4016 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 4024 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 4024 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 4034 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 4034 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 4045 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 4045 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 4055 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
+ { 4055 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
+ { 4055 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
+ { 4055 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
+ { 4060 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
+ { 4060 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
+ { 4067 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4074 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4081 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4088 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4095 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4102 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4109 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4118 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4127 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4134 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4141 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4148 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4155 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4162 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4169 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4176 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4183 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4191 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4199 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4207 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4215 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4223 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4231 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4238 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4245 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4253 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4261 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4268 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4275 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4283 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4291 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4299 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4307 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4316 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4325 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4334 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4343 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4353 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4363 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4373 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4383 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4390 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4397 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4404 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4411 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
+ { 4418 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, },
+ { 4425 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
+ { 4432 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
+ { 4439 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4447 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4455 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 4455 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 4465 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 4465 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 4475 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 4475 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 4475 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 4475 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 4485 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 4485 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 4485 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 4495 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4503 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4511 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4518 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4525 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4534 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4543 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4550 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4557 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4566 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4575 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4583 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4591 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4598 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4605 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 4610 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4617 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4624 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4632 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4640 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4649 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4658 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4665 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4672 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4679 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4686 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4693 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4700 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4707 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4714 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4721 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4728 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4735 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4742 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4750 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4758 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4765 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4772 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4780 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4788 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4796 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4804 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4812 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4820 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4827 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4834 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4842 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4850 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4860 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4870 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4880 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4890 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4896 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4902 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4913 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4924 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4935 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4946 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 4946 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, { MCK_GPR32AsmReg }, },
+ { 4952 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
+ { 4952 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
+ { 4958 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4967 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4976 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4985 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 4994 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5003 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5012 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5021 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5030 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5039 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5048 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5057 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5066 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
+ { 5066 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
+ { 5066 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
+ { 5066 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_ConstantUImm10_0 }, },
+ { 5074 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5082 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5090 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5098 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5106 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5113 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5120 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5127 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5134 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5142 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5150 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5158 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5166 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5173 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5180 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5187 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5194 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
+ { 5194 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
+ { 5194 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
+ { 5198 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, },
+ { 5207 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, },
+ { 5216 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, },
+ { 5225 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, },
+ { 5234 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5234 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5239 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
+ { 5247 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
+ { 5255 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
+ { 5263 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
+ { 5271 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 5271 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 5271 /* j */, Mips::J_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
+ { 5271 /* j */, Mips::J, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 5273 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, },
+ { 5273 /* jal */, Mips::JAL_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
+ { 5273 /* jal */, Mips::JAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 5273 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, },
+ { 5273 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5277 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 5277 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 5277 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 5277 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips|Feature_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5277 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5277 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_NotInMips16Mode, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 5282 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 5282 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips64|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
+ { 5282 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5282 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 5290 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
+ { 5290 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 5290 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 5290 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
+ { 5290 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5296 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 5296 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5305 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5311 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 5319 /* jals */, Mips::JALS_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, },
+ { 5324 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_JumpTarget }, },
+ { 5324 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_JumpTarget }, },
+ { 5329 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 5329 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 5329 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 5335 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 5335 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
+ { 5335 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 5339 /* jr */, Mips::JrRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
+ { 5339 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 5339 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 5339 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 5339 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, Feature_NotInMips16Mode|Feature_IsPTR64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
+ { 5339 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
+ { 5342 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, },
+ { 5342 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 5342 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, },
+ { 5342 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg }, },
+ { 5348 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 5353 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_UImm5Lsl2 }, },
+ { 5363 /* jrc */, Mips::JrcRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, },
+ { 5363 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
+ { 5363 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 5363 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 5363 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, },
+ { 5367 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 5373 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_UImm5Lsl2 }, },
+ { 5384 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5384 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5388 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5392 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
+ { 5392 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5395 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
+ { 5395 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
+ { 5400 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5400 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5400 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5403 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5403 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5407 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5407 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5407 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5411 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
+ { 5417 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5417 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5422 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5422 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5427 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5427 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5430 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, },
+ { 5435 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
+ { 5440 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
+ { 5445 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
+ { 5450 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5450 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5450 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5450 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5455 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
+ { 5455 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
+ { 5455 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5460 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
+ { 5465 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
+ { 5471 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
+ { 5477 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
+ { 5483 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
+ { 5489 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
+ { 5493 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
+ { 5498 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
+ { 5502 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5502 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5508 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5508 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5511 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5511 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5515 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5515 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5519 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
+ { 5525 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5525 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5530 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5530 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5534 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
+ { 5534 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, 0, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
+ { 5534 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 5537 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
+ { 5537 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, },
+ { 5537 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, },
+ { 5542 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, },
+ { 5542 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, Feature_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, },
+ { 5547 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
+ { 5547 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
+ { 5552 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5552 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5552 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5552 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5552 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5552 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5555 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5555 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 5559 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5559 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5563 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
+ { 5563 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
+ { 5563 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
+ { 5567 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 5567 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
+ { 5567 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
+ { 5571 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5571 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5571 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5577 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
+ { 5577 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
+ { 5577 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5577 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotInMips16Mode|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5577 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5577 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5577 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5577 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, },
+ { 5577 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
+ { 5577 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 5580 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
+ { 5585 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5585 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5590 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
+ { 5590 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
+ { 5590 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
+ { 5595 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
+ { 5600 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5600 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5604 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5604 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5608 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5608 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5613 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
+ { 5617 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
+ { 5617 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
+ { 5623 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
+ { 5629 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
+ { 5633 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
+ { 5633 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
+ { 5638 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5638 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 5642 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5642 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 5647 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm122_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
+ { 5647 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, },
+ { 5651 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
+ { 5657 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5657 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5661 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5661 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5667 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 5672 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5672 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5672 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5672 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5677 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 5677 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 5677 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 5684 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 5684 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 5691 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5700 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5709 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 5709 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 5717 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 5717 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 5725 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5735 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5745 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5745 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5745 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5745 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5751 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5759 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5767 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5775 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5783 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5783 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5795 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5795 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5807 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5807 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5820 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5820 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 5833 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 5833 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 5839 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 5839 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 5845 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5853 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5861 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5869 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5877 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5885 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5893 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5901 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5909 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5917 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5925 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5933 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 5941 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 5941 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 5948 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 5948 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 5955 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 5964 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 5973 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 5982 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 5991 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 6000 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 6009 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 6018 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 6027 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6027 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6027 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6027 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6032 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6032 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6032 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6032 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
+ { 6037 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
+ { 6037 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
+ { 6037 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6042 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6042 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6042 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6042 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6048 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6048 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6054 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 6054 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 6054 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
+ { 6054 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
+ { 6060 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
+ { 6066 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6066 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6066 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6066 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6073 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
+ { 6073 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6073 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 6073 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6073 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6078 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 6085 /* mflo */, Mips::Mflo16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, },
+ { 6085 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6085 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 6085 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6085 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6090 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 6097 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6097 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6104 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6104 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6110 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6116 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg }, },
+ { 6123 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6130 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6137 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6137 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6143 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6143 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6149 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
+ { 6154 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6154 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6160 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6160 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6166 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6174 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6182 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6190 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6198 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6206 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6214 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6222 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6230 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6238 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6246 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6254 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6262 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6262 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6269 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6269 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6276 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 6285 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 6294 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 6303 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
+ { 6312 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 6321 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 6330 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 6339 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 6348 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6348 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6352 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6360 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6368 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6376 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6384 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6392 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6400 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6408 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6416 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6416 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6423 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6423 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6428 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 6428 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 6428 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6428 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6434 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6434 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6434 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6440 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, },
+ { 6440 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, },
+ { 6440 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6440 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6440 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6440 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 6440 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 6445 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6452 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6459 /* movep */, Mips::MOVEP_MM, Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_MovePRegPair, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
+ { 6459 /* movep */, Mips::MOVEP_MMR6, Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_MovePRegPair, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
+ { 6465 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
+ { 6465 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
+ { 6470 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
+ { 6470 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
+ { 6470 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
+ { 6477 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
+ { 6477 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
+ { 6484 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6484 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6489 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
+ { 6489 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
+ { 6489 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
+ { 6496 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6496 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6503 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
+ { 6503 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
+ { 6508 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
+ { 6508 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
+ { 6508 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
+ { 6515 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
+ { 6515 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
+ { 6522 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6522 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6527 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
+ { 6527 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
+ { 6527 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
+ { 6534 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6534 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6541 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6541 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6541 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6541 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6546 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 6546 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 6546 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6553 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6553 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6560 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6569 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6578 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6578 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6586 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6586 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6594 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6604 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6614 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6614 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6614 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6614 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6620 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6628 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6636 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6644 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6652 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6652 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6652 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6652 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6657 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6657 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6657 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6657 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
+ { 6662 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
+ { 6662 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
+ { 6662 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6667 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6667 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6667 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6667 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6673 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6673 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6679 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 6679 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 6679 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
+ { 6679 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
+ { 6685 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
+ { 6691 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6691 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6691 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6691 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6698 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6698 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 6698 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
+ { 6698 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
+ { 6703 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6703 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6710 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6710 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 6710 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
+ { 6710 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
+ { 6715 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
+ { 6720 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
+ { 6725 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
+ { 6730 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
+ { 6735 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
+ { 6740 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, },
+ { 6745 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6745 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6752 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
+ { 6752 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
+ { 6758 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6764 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg }, },
+ { 6771 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6778 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6785 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6785 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6791 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 6791 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
+ { 6797 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
+ { 6802 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6802 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6802 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6806 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6806 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6806 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6811 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6811 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6811 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6811 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6811 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6811 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6811 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6811 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 6815 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 6815 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 6815 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6815 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 6821 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6821 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6828 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6828 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6828 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 6834 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6842 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6850 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6850 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6859 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6859 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6873 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6873 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6887 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6887 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6902 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6902 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6917 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6917 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6922 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6922 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6928 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6928 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6939 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6939 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6949 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6949 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6959 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6959 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6968 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6977 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 6986 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6986 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6997 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 6997 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7011 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7011 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7011 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7011 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7016 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7016 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7016 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7016 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7022 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7022 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7022 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7027 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7034 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7041 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7048 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7055 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 7055 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 7055 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 7055 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 7055 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7055 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7055 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7059 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7059 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7059 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7059 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7065 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7065 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7065 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7071 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 7071 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 7071 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 7071 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7071 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7071 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7076 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7083 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7090 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7097 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7104 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7111 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7118 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7125 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7132 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7132 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7132 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7140 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7140 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7148 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7148 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7148 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7156 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7156 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7164 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 7164 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 7164 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, Feature_InMips16Mode, { }, },
+ { 7164 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips, { }, },
+ { 7164 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, Feature_InMicroMips, { }, },
+ { 7168 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7168 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 7168 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7168 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7168 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7168 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7168 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
+ { 7172 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7178 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 7185 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 7185 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, },
+ { 7185 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, },
+ { 7185 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 7185 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7185 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7185 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7189 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 7189 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 7195 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 7195 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7195 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7195 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7195 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 7195 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7195 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7195 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 7195 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7195 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7195 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7195 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 7195 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7195 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7195 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
+ { 7198 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7203 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 7203 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 7208 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 7208 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 7208 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 7208 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 7208 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 7208 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 7212 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 7218 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7218 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7228 /* pause */, Mips::PAUSE, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, },
+ { 7228 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 7228 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 7234 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7242 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7250 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7258 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7266 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7274 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7282 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7290 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7298 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7305 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7312 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7319 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 7326 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7326 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7334 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7334 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7342 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasCnMips, { MCK_GPR32AsmReg }, },
+ { 7342 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7346 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7346 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7359 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7359 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7372 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7372 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7387 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7387 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7403 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7403 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7418 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7418 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7434 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7434 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7448 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7448 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7463 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7463 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7477 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7477 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7492 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7492 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7504 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7504 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7519 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7519 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7536 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7536 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7548 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7548 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7561 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7561 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7576 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7576 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7592 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
+ { 7592 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
+ { 7592 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
+ { 7592 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
+ { 7597 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
+ { 7597 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, },
+ { 7603 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 7609 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7609 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7617 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7617 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7628 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
+ { 7628 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
+ { 7634 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
+ { 7634 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
+ { 7634 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
+ { 7634 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
+ { 7634 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
+ { 7634 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
+ { 7640 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7647 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7647 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7647 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7647 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7655 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7655 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7663 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7663 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7663 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7663 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7667 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7667 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7667 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7667 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 7672 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
+ { 7672 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
+ { 7680 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
+ { 7680 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
+ { 7688 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7688 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7697 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7697 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7706 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7706 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7713 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7713 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7720 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7720 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 7720 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7720 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 7724 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7724 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 7724 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7724 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 7728 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7728 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7733 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7733 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7739 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7739 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7749 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 7749 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 7759 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 7759 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 7759 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 7759 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7769 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7769 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7769 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7779 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7779 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 7779 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7779 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7787 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7787 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotInMips16Mode|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7795 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7795 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7799 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7803 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 7811 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 7819 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 7827 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7835 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 7843 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 7851 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 7859 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 7867 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 7867 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 7867 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 7867 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
+ { 7870 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
+ { 7870 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
+ { 7875 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 7875 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 7879 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 7879 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 7879 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 7879 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 7879 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 7879 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 7882 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, },
+ { 7882 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
+ { 7886 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 7886 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 7890 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7890 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
+ { 7893 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { }, },
+ { 7893 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { }, },
+ { 7893 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 7893 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
+ { 7893 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
+ { 7893 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
+ { 7893 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm20_0 }, },
+ { 7899 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm4_0 }, },
+ { 7899 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm4_0 }, },
+ { 7907 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7907 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7907 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7907 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7912 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
+ { 7912 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
+ { 7912 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
+ { 7917 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
+ { 7922 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
+ { 7926 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
+ { 7930 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 7930 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 7936 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, Feature_InMips16Mode, { MCK_CPU16Regs }, },
+ { 7936 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 7936 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
+ { 7936 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7936 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7940 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, Feature_InMips16Mode, { MCK_CPU16Regs }, },
+ { 7940 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 7940 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, },
+ { 7940 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7940 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7944 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7944 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7950 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7950 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7956 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7956 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7956 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 7963 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7963 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7972 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7972 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7981 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7981 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 7981 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 7988 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7988 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 7997 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 7997 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 8006 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8006 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
+ { 8006 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 8006 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8006 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8006 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 8010 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
+ { 8010 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
+ { 8015 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8015 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8015 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8015 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8019 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8019 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8019 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8019 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8024 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 8024 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 8024 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 8024 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
+ { 8027 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
+ { 8027 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
+ { 8032 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 8032 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 8036 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 8042 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 8048 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 8054 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
+ { 8054 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
+ { 8060 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 8060 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
+ { 8067 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8067 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8075 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8075 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8083 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8083 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8093 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8093 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8102 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8102 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8111 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8111 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8120 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8120 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8131 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8131 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8141 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8141 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8149 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8149 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8157 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8157 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8167 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8167 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8177 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8177 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8186 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8186 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8195 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8195 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8204 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8204 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8215 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8215 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8226 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8226 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8236 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8236 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8244 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8244 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8252 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8252 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8261 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8261 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8270 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
+ { 8276 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
+ { 8282 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
+ { 8288 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
+ { 8294 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
+ { 8301 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
+ { 8308 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
+ { 8315 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
+ { 8322 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8322 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8322 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8322 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8322 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
+ { 8322 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8322 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8322 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8322 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8326 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8332 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8338 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8344 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8350 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
+ { 8350 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
+ { 8356 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8363 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 8370 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8377 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8384 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 8384 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8384 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8389 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 8389 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8389 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8389 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 8389 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8389 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8389 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8389 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8389 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
+ { 8393 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
+ { 8393 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 8393 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 8393 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 8398 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
+ { 8398 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 8398 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 8398 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, },
+ { 8404 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 8404 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8404 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8404 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 8404 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8404 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8404 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8404 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 8404 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
+ { 8409 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 8409 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 8413 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
+ { 8413 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
+ { 8418 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
+ { 8426 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
+ { 8434 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
+ { 8442 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
+ { 8450 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
+ { 8459 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
+ { 8468 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
+ { 8477 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
+ { 8486 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 8486 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 8486 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 8486 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 8493 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 8493 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 8500 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8500 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8500 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8500 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
+ { 8500 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8500 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8500 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8504 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8510 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8516 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8522 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8528 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8535 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 8542 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8549 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8556 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8563 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8570 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8577 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8584 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8592 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 8600 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8608 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8616 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 8616 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8616 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8621 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8621 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8621 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8621 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
+ { 8621 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8621 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8621 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8625 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8631 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8637 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8643 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8649 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
+ { 8649 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
+ { 8655 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8662 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 8669 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8676 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8683 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8690 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8697 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8704 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8711 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
+ { 8719 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
+ { 8727 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
+ { 8735 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 8743 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 8743 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8743 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8748 /* ssnop */, Mips::SSNOP, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 8748 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 8748 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 8754 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, },
+ { 8759 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
+ { 8764 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
+ { 8769 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
+ { 8774 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8774 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8774 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8774 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, },
+ { 8774 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8774 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8774 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8774 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
+ { 8778 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 8778 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
+ { 8778 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 8778 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 8784 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 8784 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 8784 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 8790 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8790 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8798 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8798 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8808 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8808 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8817 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8817 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8826 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8826 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8834 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8834 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8845 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8845 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 8855 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8864 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8873 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8882 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8891 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8900 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8909 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8918 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8927 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8938 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8949 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8960 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8971 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8982 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 8993 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9004 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9015 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9015 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9015 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9015 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, 0, { MCK_GPR32AsmReg, MCK_InvNum }, },
+ { 9015 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 9015 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9015 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9015 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9015 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
+ { 9020 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9020 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9028 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9028 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9036 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 9036 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 9043 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9043 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9053 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9053 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9063 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9063 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9072 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9072 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9083 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9090 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9097 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9104 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9111 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 9119 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 9127 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 9135 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
+ { 9143 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 9143 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 9143 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 9149 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
+ { 9149 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
+ { 9149 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9149 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotInMips16Mode|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9149 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9149 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9149 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9149 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
+ { 9149 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
+ { 9152 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
+ { 9152 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
+ { 9157 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 9157 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, },
+ { 9162 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
+ { 9162 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, },
+ { 9162 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, },
+ { 9167 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
+ { 9172 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 9172 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 9176 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9176 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9180 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 9180 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 9185 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
+ { 9189 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
+ { 9189 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
+ { 9195 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, },
+ { 9201 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, },
+ { 9205 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9205 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9209 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 9209 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, },
+ { 9214 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 9214 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
+ { 9220 /* sync */, Mips::SYNC, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { }, },
+ { 9220 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 9220 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, Feature_InMicroMips, { }, },
+ { 9220 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_ConstantUImm5_0 }, },
+ { 9220 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0 }, },
+ { 9220 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0 }, },
+ { 9225 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm162_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_MemOffsetSimm16 }, },
+ { 9225 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm162_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_MemOffsetSimm16 }, },
+ { 9225 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm162_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_MemOffsetSimm16 }, },
+ { 9231 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, Feature_HasMips64|Feature_HasCnMips, { }, },
+ { 9242 /* syncs */, Mips::SYNC, Convert__imm_95_6, Feature_HasMips64|Feature_HasCnMips, { }, },
+ { 9248 /* syncw */, Mips::SYNC, Convert__imm_95_4, Feature_HasMips64|Feature_HasCnMips, { }, },
+ { 9254 /* syncws */, Mips::SYNC, Convert__imm_95_5, Feature_HasMips64|Feature_HasCnMips, { }, },
+ { 9261 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 9261 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, Feature_InMicroMips, { }, },
+ { 9261 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
+ { 9261 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
+ { 9269 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9269 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9269 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 9269 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
+ { 9273 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9273 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9278 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9278 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9278 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 9278 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
+ { 9282 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9282 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9287 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9287 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9293 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9293 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9293 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 9293 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
+ { 9298 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
+ { 9298 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
+ { 9306 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
+ { 9306 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
+ { 9315 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
+ { 9315 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
+ { 9321 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
+ { 9321 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
+ { 9327 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
+ { 9327 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
+ { 9334 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, },
+ { 9334 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, },
+ { 9341 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { }, },
+ { 9341 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 9348 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { }, },
+ { 9348 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, },
+ { 9356 /* tlbp */, Mips::TLBP, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 9356 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 9361 /* tlbr */, Mips::TLBR, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 9361 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 9366 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 9366 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 9372 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, },
+ { 9372 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, Feature_InMicroMips, { }, },
+ { 9378 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9378 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9378 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 9378 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
+ { 9382 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9382 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9387 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9387 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9393 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9393 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9393 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 9393 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
+ { 9398 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9398 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9398 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
+ { 9398 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
+ { 9402 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9402 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
+ { 9407 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 9407 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
+ { 9417 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 9417 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
+ { 9427 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 9427 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 9427 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
+ { 9427 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
+ { 9427 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
+ { 9427 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
+ { 9437 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 9437 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 9437 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
+ { 9437 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9447 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9451 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9456 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9460 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9464 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, },
+ { 9468 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 9468 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 9475 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 9475 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 9480 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 9480 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
+ { 9486 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9493 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9500 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9507 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9514 /* wait */, Mips::WAIT, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, { }, },
+ { 9514 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, Feature_InMicroMips, { }, },
+ { 9514 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm10_0 }, },
+ { 9514 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, },
+ { 9519 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 9519 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg }, },
+ { 9519 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
+ { 9519 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
+ { 9525 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9532 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9532 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9532 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9537 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
+ { 9537 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9537 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9537 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9537 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 9537 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 9537 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 9537 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
+ { 9537 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9537 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9537 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+ { 9537 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 9537 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 9537 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
+ { 9537 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
+ { 9541 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
+ { 9547 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 9547 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
+ { 9553 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 9553 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 9553 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 9553 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 9553 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 9553 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
+ { 9558 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
+ { 9565 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, },
+ { 9565 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
+};
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Format.h"
+
+unsigned MipsAsmParser::
+MatchInstructionImpl(const OperandVector &Operands,
+ MCInst &Inst,
+ uint64_t &ErrorInfo,
+ bool matchingInlineAsm, unsigned VariantID) {
+ // Eliminate obvious mismatches.
+ if (Operands.size() > 9) {
+ ErrorInfo = 9;
+ return Match_InvalidOperand;
+ }
+
+ // Get the current feature set.
+ uint64_t AvailableFeatures = getAvailableFeatures();
+
+ // Get the instruction mnemonic, which is the first token.
+ StringRef Mnemonic = ((MipsOperand&)*Operands[0]).getToken();
+
+ // Some state to try to produce better error messages.
+ bool HadMatchOtherThanFeatures = false;
+ bool HadMatchOtherThanPredicate = false;
+ unsigned RetCode = Match_InvalidOperand;
+ uint64_t MissingFeatures = ~0ULL;
+ // Set ErrorInfo to the operand that mismatches if it is
+ // wrong for all instances of the instruction.
+ ErrorInfo = ~0ULL;
+ // Find the appropriate table for this asm variant.
+ const MatchEntry *Start, *End;
+ switch (VariantID) {
+ default: llvm_unreachable("invalid variant!");
+ case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
+ }
+ // Search the table.
+ auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
+
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
+ std::distance(MnemonicRange.first, MnemonicRange.second) <<
+ " encodings with mnemonic '" << Mnemonic << "'\n");
+
+ // Return a more specific error code if no mnemonics match.
+ if (MnemonicRange.first == MnemonicRange.second)
+ return Match_MnemonicFail;
+
+ for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
+ it != ie; ++it) {
+ bool HasRequiredFeatures =
+ (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures;
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
+ << MII.getName(it->Opcode) << "\n");
+ // equal_range guarantees that instruction mnemonic matches.
+ assert(Mnemonic == it->getMnemonic());
+ bool OperandsValid = true;
+ for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) {
+ auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
+ << " against actual operand at index " << ActualIdx);
+ if (ActualIdx < Operands.size())
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
+ Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
+ else
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
+ if (ActualIdx >= Operands.size()) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range ");
+ OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
+ if (!OperandsValid) ErrorInfo = ActualIdx;
+ break;
+ }
+ MCParsedAsmOperand &Actual = *Operands[ActualIdx];
+ unsigned Diag = validateOperandClass(Actual, Formal);
+ if (Diag == Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "match success using generic matcher\n");
+ ++ActualIdx;
+ continue;
+ }
+ // If the generic handler indicates an invalid operand
+ // failure, check for a special case.
+ if (Diag != Match_Success) {
+ unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
+ if (TargetDiag == Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "match success using target matcher\n");
+ ++ActualIdx;
+ continue;
+ }
+ // If the target matcher returned a specific error code use
+ // that, else use the one from the generic matcher.
+ if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
+ Diag = TargetDiag;
+ }
+ // If current formal operand wasn't matched and it is optional
+ // then try to match next formal operand
+ if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
+ continue;
+ }
+ // If this operand is broken for all of the instances of this
+ // mnemonic, keep track of it so we can report loc info.
+ // If we already had a match that only failed due to a
+ // target predicate, that diagnostic is preferred.
+ if (!HadMatchOtherThanPredicate &&
+ (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
+ if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
+ RetCode = Diag;
+ ErrorInfo = ActualIdx;
+ }
+ // Otherwise, just reject this instance of the mnemonic.
+ OperandsValid = false;
+ break;
+ }
+
+ if (!OperandsValid) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
+ "operand mismatches, ignoring "
+ "this opcode\n");
+ continue;
+ }
+ if (!HasRequiredFeatures) {
+ HadMatchOtherThanFeatures = true;
+ uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: "
+ << format_hex(NewMissingFeatures, 18)
+ << "\n");
+ if (countPopulation(NewMissingFeatures) <=
+ countPopulation(MissingFeatures))
+ MissingFeatures = NewMissingFeatures;
+ continue;
+ }
+
+ Inst.clear();
+
+ Inst.setOpcode(it->Opcode);
+ // We have a potential match but have not rendered the operands.
+ // Check the target predicate to handle any context sensitive
+ // constraints.
+ // For example, Ties that are referenced multiple times must be
+ // checked here to ensure the input is the same for each match
+ // constraints. If we leave it any later the ties will have been
+ // canonicalized
+ unsigned MatchResult;
+ if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
+ Inst.clear();
+ DEBUG_WITH_TYPE(
+ "asm-matcher",
+ dbgs() << "Early target match predicate failed with diag code "
+ << MatchResult << "\n");
+ RetCode = MatchResult;
+ HadMatchOtherThanPredicate = true;
+ continue;
+ }
+
+ if (matchingInlineAsm) {
+ convertToMapAndConstraints(it->ConvertFn, Operands);
+ if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
+ return Match_InvalidTiedOperand;
+
+ return Match_Success;
+ }
+
+ // We have selected a definite instruction, convert the parsed
+ // operands into the appropriate MCInst.
+ convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
+
+ // We have a potential match. Check the target predicate to
+ // handle any context sensitive constraints.
+ if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "Target match predicate failed with diag code "
+ << MatchResult << "\n");
+ Inst.clear();
+ RetCode = MatchResult;
+ HadMatchOtherThanPredicate = true;
+ continue;
+ }
+
+ if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
+ return Match_InvalidTiedOperand;
+
+ DEBUG_WITH_TYPE(
+ "asm-matcher",
+ dbgs() << "Opcode result: complete match, selecting this opcode\n");
+ return Match_Success;
+ }
+
+ // Okay, we had no match. Try to return a useful error code.
+ if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
+ return RetCode;
+
+ // Missing feature matches return which features were missing
+ ErrorInfo = MissingFeatures;
+ return Match_MissingFeature;
+}
+
+namespace {
+ struct OperandMatchEntry {
+ uint64_t RequiredFeatures;
+ uint16_t Mnemonic;
+ uint8_t Class;
+ uint8_t OperandMask;
+
+ StringRef getMnemonic() const {
+ return StringRef(MnemonicTable + Mnemonic + 1,
+ MnemonicTable[Mnemonic]);
+ }
+ };
+
+ // Predicate for searching for an opcode.
+ struct LessOpcodeOperand {
+ bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
+ return LHS.getMnemonic() < RHS;
+ }
+ bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
+ return LHS < RHS.getMnemonic();
+ }
+ bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
+ return LHS.getMnemonic() < RHS.getMnemonic();
+ }
+ };
+} // end anonymous namespace.
+
+static const OperandMatchEntry OperandMatchTable[3237] = {
+ /* Operand List Mask, Mnemonic, Operand Class, Features */
+ { 0, 0 /* abs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 61 /* add_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 69 /* add_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 77 /* add_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 85 /* add_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 104 /* addiupc */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 112 /* addiur1sp */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 122 /* addiur2 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 130 /* addius5 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 211 /* adds_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 220 /* adds_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 229 /* adds_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 238 /* adds_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 247 /* adds_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 256 /* adds_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 265 /* adds_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 274 /* adds_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 283 /* adds_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 292 /* adds_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 301 /* adds_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 310 /* adds_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 393 /* addv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 400 /* addv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 407 /* addv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 414 /* addv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 421 /* addvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 429 /* addvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 437 /* addvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 445 /* addvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 472 /* and */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 472 /* and */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 476 /* and.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 493 /* andi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 514 /* asub_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 523 /* asub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 532 /* asub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 541 /* asub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 550 /* asub_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 559 /* asub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 568 /* asub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 577 /* asub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 596 /* ave_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 604 /* ave_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 612 /* ave_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 620 /* ave_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 628 /* ave_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 636 /* ave_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 644 /* ave_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 652 /* ave_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 660 /* aver_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 669 /* aver_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 678 /* aver_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 687 /* aver_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 696 /* aver_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 705 /* aver_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 714 /* aver_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 723 /* aver_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
+ { 0, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasCnMips, 766 /* bbit032 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 766 /* bbit032 */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasCnMips, 780 /* bbit132 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 780 /* bbit132 */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 791 /* bc16 */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 796 /* bc1eqz */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 796 /* bc1eqz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 803 /* bc1eqzc */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 803 /* bc1eqzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 822 /* bc1nez */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 822 /* bc1nez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 829 /* bc1nezc */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 829 /* bc1nezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 848 /* bc2eqz */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 848 /* bc2eqz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 855 /* bc2eqzc */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 855 /* bc2eqzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 863 /* bc2nez */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 863 /* bc2nez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 870 /* bc2nezc */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 870 /* bc2nezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 878 /* bclr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 885 /* bclr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 892 /* bclr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 899 /* bclr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 906 /* bclri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 914 /* bclri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 922 /* bclri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 930 /* bclri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 938 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 938 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 938 /* beq */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 942 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 942 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 942 /* beqc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 947 /* beql */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 947 /* beql */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 947 /* beql */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 947 /* beql */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMips16Mode, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 952 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips, 952 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMips16Mode, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 957 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 957 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 957 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 957 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 964 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 964 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 964 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 964 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 972 /* beqzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 978 /* beqzc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 978 /* beqzc16 */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 986 /* beqzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 986 /* beqzl */, MCK_JumpTarget, 2 /* 1 */ },
+ { 0, 992 /* bge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 992 /* bge */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 992 /* bge */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 992 /* bge */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 996 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 996 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 996 /* bgec */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1006 /* bgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 1006 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1006 /* bgeu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 1006 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1023 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1023 /* bgez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1023 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1023 /* bgez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1028 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1028 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1028 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1028 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1035 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1035 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1035 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1035 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1043 /* bgezall */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1043 /* bgezall */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1051 /* bgezals */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1051 /* bgezals */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1059 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1059 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1059 /* bgezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1065 /* bgezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1065 /* bgezl */, MCK_JumpTarget, 2 /* 1 */ },
+ { 0, 1071 /* bgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 1071 /* bgt */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1071 /* bgt */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 1071 /* bgt */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1080 /* bgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 1080 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1080 /* bgtu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 1080 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1091 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1091 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1091 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1091 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1096 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1096 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1096 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1096 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1104 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1104 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1104 /* bgtzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1110 /* bgtzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1110 /* bgtzl */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1116 /* binsl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1124 /* binsl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1132 /* binsl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1140 /* binsl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1148 /* binsli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1157 /* binsli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1166 /* binsli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1175 /* binsli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1184 /* binsr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1192 /* binsr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1200 /* binsr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1208 /* binsr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1216 /* binsri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1225 /* binsri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1234 /* binsri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1243 /* binsri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 1252 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 1252 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 1259 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1259 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 1267 /* ble */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 1267 /* ble */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1267 /* ble */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 1267 /* ble */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1276 /* bleu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 1276 /* bleu */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1276 /* bleu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 1276 /* bleu */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1287 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1287 /* blez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1287 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1287 /* blez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1292 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1292 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1292 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1292 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1300 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1300 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1300 /* blezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1306 /* blezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1306 /* blezl */, MCK_JumpTarget, 2 /* 1 */ },
+ { 0, 1312 /* blt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 1312 /* blt */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1312 /* blt */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 1312 /* blt */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1326 /* bltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 1326 /* bltu */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1326 /* bltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 1326 /* bltu */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1331 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1331 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1331 /* bltuc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1343 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1343 /* bltz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1343 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1343 /* bltz */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1348 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1348 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1348 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1348 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1355 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1355 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1355 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1355 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1363 /* bltzall */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1363 /* bltzall */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1371 /* bltzals */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1371 /* bltzals */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1379 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1379 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1379 /* bltzc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1385 /* bltzl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1385 /* bltzl */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1391 /* bmnz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1398 /* bmnzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1406 /* bmz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1412 /* bmzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1419 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1419 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
+ { 0, 1419 /* bne */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1423 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1423 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1423 /* bnec */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1428 /* bneg.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1435 /* bneg.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1442 /* bneg.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1449 /* bneg.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1456 /* bnegi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1464 /* bnegi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1472 /* bnegi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1480 /* bnegi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1488 /* bnel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1488 /* bnel */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1488 /* bnel */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1488 /* bnel */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMips16Mode, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1493 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips, 1493 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMips16Mode, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1498 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1498 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1498 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1498 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1505 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1505 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1505 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1505 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1513 /* bnezc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1519 /* bnezc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1519 /* bnezc16 */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 1527 /* bnezl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 1527 /* bnezl */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1533 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1533 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1533 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1533 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1538 /* bnz.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1538 /* bnz.b */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1544 /* bnz.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1544 /* bnz.d */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1550 /* bnz.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1550 /* bnz.h */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1556 /* bnz.v */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1556 /* bnz.v */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1562 /* bnz.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1562 /* bnz.w */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1568 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1568 /* bovc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1568 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1568 /* bovc */, MCK_JumpTarget, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasDSP, 1573 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasDSP|Feature_NotInMicroMips, 1573 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR3, 1582 /* bposge32c */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1606 /* bsel.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1613 /* bseli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1621 /* bset.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1628 /* bset.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1635 /* bset.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1642 /* bset.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1649 /* bseti.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1657 /* bseti.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1665 /* bseti.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1673 /* bseti.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1693 /* bz.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1693 /* bz.b */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1698 /* bz.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1698 /* bz.d */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1703 /* bz.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1703 /* bz.h */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1708 /* bz.v */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1708 /* bz.v */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1713 /* bz.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 1713 /* bz.w */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FCCAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1962 /* cache */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 1962 /* cache */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 1968 /* cachee */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 1968 /* cachee */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1975 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1975 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1984 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1984 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1984 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1984 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2011 /* ceq.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2017 /* ceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2023 /* ceq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2029 /* ceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2035 /* ceqi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2042 /* ceqi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2049 /* ceqi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2056 /* ceqi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2063 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2063 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 2063 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 2063 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 2068 /* cfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips, 2068 /* cfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2073 /* cfcmsa */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2073 /* cfcmsa */, MCK_MSACtrlAsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 2080 /* cftc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 2080 /* cftc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2086 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64|Feature_HasCnMips, 2086 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2086 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasMips64|Feature_HasCnMips, 2086 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2091 /* cins32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2091 /* cins32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2098 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 2098 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2106 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 2106 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2114 /* cle_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2122 /* cle_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2130 /* cle_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2138 /* cle_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2146 /* cle_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2154 /* cle_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2162 /* cle_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2170 /* cle_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2178 /* clei_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2187 /* clei_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2196 /* clei_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2205 /* clei_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2214 /* clei_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2223 /* clei_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2232 /* clei_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2241 /* clei_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2254 /* clt_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2262 /* clt_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2270 /* clt_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2278 /* clt_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2286 /* clt_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2294 /* clt_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2302 /* clt_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2310 /* clt_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2318 /* clti_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2327 /* clti_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2336 /* clti_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2345 /* clti_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2354 /* clti_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2363 /* clti_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2372 /* clti_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2381 /* clti_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2398 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2398 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2398 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2398 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2407 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2407 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2416 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2416 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2416 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2416 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2425 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 2425 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2435 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2435 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2444 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2444 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2444 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2444 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2453 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 2453 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2463 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2463 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2472 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2472 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2472 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2472 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2481 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 2481 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2491 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2491 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2500 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2500 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2500 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2500 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2510 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2510 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2520 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2520 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2520 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2520 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2530 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2530 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2540 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2540 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2540 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2540 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2550 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2550 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2570 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2570 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2580 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2580 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2580 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2580 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2591 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2591 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2602 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2602 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2602 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2602 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2613 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2613 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2624 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2624 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2624 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2624 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2635 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2635 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2646 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2646 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2646 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2646 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2656 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2656 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2666 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2666 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2666 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2666 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2676 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2676 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2686 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2686 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2686 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2686 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2696 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2696 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2706 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2706 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2706 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2706 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2716 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2716 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2726 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2726 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2726 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2726 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2735 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2735 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 2744 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 2744 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 2757 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 2757 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 2770 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 2770 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2783 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 2783 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2795 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 2795 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2807 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 2807 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2824 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 2824 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2835 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 2835 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 2846 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 2846 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2857 /* copy_s.b */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2857 /* copy_s.b */, MCK_MSA128AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2866 /* copy_s.d */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2866 /* copy_s.d */, MCK_MSA128AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2875 /* copy_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2875 /* copy_s.h */, MCK_MSA128AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2884 /* copy_s.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2884 /* copy_s.w */, MCK_MSA128AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2893 /* copy_u.b */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2893 /* copy_u.b */, MCK_MSA128AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2902 /* copy_u.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2902 /* copy_u.h */, MCK_MSA128AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2911 /* copy_u.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2911 /* copy_u.w */, MCK_MSA128AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2920 /* crc32b */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2927 /* crc32cb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, 2935 /* crc32cd */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2943 /* crc32ch */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2951 /* crc32cw */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, 2959 /* crc32d */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2966 /* crc32h */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2973 /* crc32w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2980 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2980 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 2980 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 2980 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 2985 /* ctc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips, 2985 /* ctc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2990 /* ctcmsa */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 2990 /* ctcmsa */, MCK_MSACtrlAsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 2997 /* cttc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 2997 /* cttc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3003 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3003 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3051 /* cvt.s.l */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3051 /* cvt.s.l */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3051 /* cvt.s.l */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3051 /* cvt.s.l */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3088 /* daddi */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3088 /* daddi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3094 /* daddiu */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3094 /* daddiu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3107 /* dahi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3112 /* dalign */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3119 /* dati */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3124 /* daui */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3129 /* dbitswap */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, 3138 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3138 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, 3143 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3143 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3170 /* dextm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3176 /* dextu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3190 /* dinsm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3196 /* dinsu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32ZeroAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 3202 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3206 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3206 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3206 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3206 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3218 /* div_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3226 /* div_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3234 /* div_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3242 /* div_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3250 /* div_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3258 /* div_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3266 /* div_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3274 /* div_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32ZeroAsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3282 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 3287 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { 0, 3287 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { 0, 3287 /* dla */, MCK_Mem, 2 /* 1 */ },
+ { 0, 3291 /* dli */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 3295 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3295 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_NotInMicroMips, 3300 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_NotInMicroMips, 3300 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64, 3300 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasMips64, 3300 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3306 /* dmfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3306 /* dmfc1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { 0, 3312 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { 0, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64, 3312 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_HasMips64, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3318 /* dmfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3318 /* dmfgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3318 /* dmfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3318 /* dmfgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3325 /* dmod */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3330 /* dmodu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3336 /* dmt */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotInMicroMips, 3340 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_NotInMicroMips, 3340 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64, 3340 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasMips64, 3340 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3346 /* dmtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3346 /* dmtc1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { 0, 3352 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { 0, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64, 3352 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_HasMips64, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3358 /* dmtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3358 /* dmtgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3358 /* dmtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3358 /* dmtgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3365 /* dmuh */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3370 /* dmuhu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3376 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3381 /* dmulo */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3387 /* dmulou */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3394 /* dmult */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3400 /* dmultu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3407 /* dmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3413 /* dneg */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3413 /* dneg */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3418 /* dnegu */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3418 /* dnegu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3424 /* dotp_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3433 /* dotp_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3442 /* dotp_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3451 /* dotp_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3460 /* dotp_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3469 /* dotp_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3487 /* dpadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3497 /* dpadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3507 /* dpadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3517 /* dpadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3527 /* dpadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3537 /* dpadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasCnMips, 3630 /* dpop */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 3630 /* dpop */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3717 /* dpsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3727 /* dpsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3737 /* dpsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3747 /* dpsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3757 /* dpsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 3767 /* dpsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3808 /* drotr */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3808 /* drotr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3814 /* drotr32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3814 /* drotr32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3822 /* drotrv */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3822 /* drotrv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3829 /* dsbh */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3834 /* dshd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3844 /* dsll32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3844 /* dsll32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3851 /* dsllv */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3851 /* dsllv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3857 /* dsra */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3, 3857 /* dsra */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3, 3857 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3857 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3862 /* dsra32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3862 /* dsra32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3869 /* dsrav */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3869 /* dsrav */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3880 /* dsrl32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3880 /* dsrl32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3887 /* dsrlv */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3887 /* dsrlv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3893 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_InvNum, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3893 /* dsub */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_InvNum, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_InvNum, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_InvNum, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_InvNum, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_InvNum, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 3910 /* dvp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 3910 /* dvp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3914 /* dvpe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3926 /* emt */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 3942 /* evp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 3942 /* evp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3946 /* evpe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3955 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3955 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3955 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 3955 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3960 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3960 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3960 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 3960 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3967 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3967 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_HasDSP, 3967 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 3967 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3975 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3975 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_HasDSP, 3975 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 3975 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3981 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3981 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3981 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 3981 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3988 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3988 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3988 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 3988 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3997 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 3997 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 3997 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 3997 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4007 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4007 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 4007 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 4007 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4016 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4016 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_HasDSP, 4016 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 4016 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4024 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4024 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_HasDSP, 4024 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 4024 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4045 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 4045 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_HasDSP, 4045 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 4045 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ },
+ { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4055 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64|Feature_HasCnMips, 4055 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4055 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasMips64|Feature_HasCnMips, 4055 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4060 /* exts32 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4060 /* exts32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4067 /* fadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4074 /* fadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4081 /* fcaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4088 /* fcaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4095 /* fceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4102 /* fceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4109 /* fclass.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4118 /* fclass.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4127 /* fcle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4134 /* fcle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4141 /* fclt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4148 /* fclt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4155 /* fcne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4162 /* fcne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4169 /* fcor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4176 /* fcor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4183 /* fcueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4191 /* fcueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4199 /* fcule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4207 /* fcule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4215 /* fcult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4223 /* fcult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4231 /* fcun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4238 /* fcun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4245 /* fcune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4253 /* fcune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4261 /* fdiv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4268 /* fdiv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4275 /* fexdo.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4283 /* fexdo.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4291 /* fexp2.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4299 /* fexp2.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4307 /* fexupl.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4316 /* fexupl.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4325 /* fexupr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4334 /* fexupr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4343 /* ffint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4353 /* ffint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4363 /* ffint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4373 /* ffint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4383 /* ffql.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4390 /* ffql.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4397 /* ffqr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4404 /* ffqr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4411 /* fill.b */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4411 /* fill.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4418 /* fill.d */, MCK_GPR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4418 /* fill.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4425 /* fill.h */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4425 /* fill.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4432 /* fill.w */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4432 /* fill.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4439 /* flog2.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4447 /* flog2.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4455 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4455 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4465 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4465 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4465 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4465 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4495 /* fmadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4503 /* fmadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4511 /* fmax.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4518 /* fmax.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4525 /* fmax_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4534 /* fmax_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4543 /* fmin.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4550 /* fmin.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4557 /* fmin_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4566 /* fmin_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4575 /* fmsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4583 /* fmsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4591 /* fmul.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4598 /* fmul.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 4605 /* fork */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4610 /* frcp.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4617 /* frcp.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4624 /* frint.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4632 /* frint.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4640 /* frsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4649 /* frsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4658 /* fsaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4665 /* fsaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4672 /* fseq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4679 /* fseq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4686 /* fsle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4693 /* fsle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4700 /* fslt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4707 /* fslt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4714 /* fsne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4721 /* fsne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4728 /* fsor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4735 /* fsor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4742 /* fsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4750 /* fsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4758 /* fsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4765 /* fsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4772 /* fsueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4780 /* fsueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4788 /* fsule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4796 /* fsule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4804 /* fsult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4812 /* fsult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4820 /* fsun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4827 /* fsun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4834 /* fsune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4842 /* fsune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4850 /* ftint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4860 /* ftint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4870 /* ftint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4880 /* ftint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4890 /* ftq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4896 /* ftq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4902 /* ftrunc_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4913 /* ftrunc_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4924 /* ftrunc_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4935 /* ftrunc_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, 4946 /* ginvi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, 4946 /* ginvi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, 4952 /* ginvt */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, 4952 /* ginvt */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4958 /* hadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4967 /* hadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4976 /* hadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4985 /* hadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 4994 /* hadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5003 /* hadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5012 /* hsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5021 /* hsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5030 /* hsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5039 /* hsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5048 /* hsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5057 /* hsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5074 /* ilvev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5082 /* ilvev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5090 /* ilvev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5098 /* ilvev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5106 /* ilvl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5113 /* ilvl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5120 /* ilvl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5127 /* ilvl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5134 /* ilvod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5142 /* ilvod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5150 /* ilvod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5158 /* ilvod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5166 /* ilvr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5173 /* ilvr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5180 /* ilvr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5187 /* ilvr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5198 /* insert.b */, MCK_GPR32AsmReg, 16 /* 4 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5198 /* insert.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 5207 /* insert.d */, MCK_GPR64AsmReg, 16 /* 4 */ },
+ { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 5207 /* insert.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5216 /* insert.h */, MCK_GPR32AsmReg, 16 /* 4 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5216 /* insert.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5225 /* insert.w */, MCK_GPR32AsmReg, 16 /* 4 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5225 /* insert.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5234 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 5234 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5239 /* insve.b */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5247 /* insve.d */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5255 /* insve.h */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5263 /* insve.w */, MCK_MSA128AsmReg, 17 /* 0, 4 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5271 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5271 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5271 /* j */, MCK_JumpTarget, 1 /* 0 */ },
+ { 0, 5273 /* jal */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5273 /* jal */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5273 /* jal */, MCK_JumpTarget, 1 /* 0 */ },
+ { 0, 5273 /* jal */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotInMicroMips, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips|Feature_NoIndirectJumpGuards, 5277 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_NotInMips16Mode, 5277 /* jalr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32, 5282 /* jalr.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5290 /* jalrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5290 /* jalrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6, 5290 /* jalrc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5290 /* jalrc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5296 /* jalrc.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5296 /* jalrc.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5305 /* jalrs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5311 /* jalrs16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5324 /* jalx */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5324 /* jalx */, MCK_JumpTarget, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5329 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5329 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5329 /* jialc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5335 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5335 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5335 /* jic */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotInMips16Mode|Feature_IsPTR64bit|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6, 5339 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6, 5342 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5342 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5342 /* jr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5342 /* jr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5348 /* jr16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, 5363 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5363 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6, 5363 /* jrc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5367 /* jrc16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 5388 /* l.s */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 5388 /* l.s */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { 0, 5392 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 5392 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 5392 /* la */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5395 /* lapc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5395 /* lapc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5400 /* lb */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_InMicroMips, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5400 /* lb */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5400 /* lb */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5403 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5403 /* lbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5403 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5403 /* lbe */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5407 /* lbu */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_InMicroMips, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5407 /* lbu */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5407 /* lbu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_InMicroMips, 5411 /* lbu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5411 /* lbu16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5417 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5417 /* lbue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5417 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5417 /* lbue */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5422 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
+ { Feature_HasDSP, 5422 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
+ { Feature_HasStdEnc|Feature_NotMips3, 5427 /* ld */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips3, 5427 /* ld */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5427 /* ld */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5427 /* ld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5430 /* ld.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5430 /* ld.b */, MCK_MemOffsetSimm10, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5435 /* ld.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5435 /* ld.d */, MCK_MemOffsetSimm10_3, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5440 /* ld.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5440 /* ld.h */, MCK_MemOffsetSimm10_1, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5445 /* ld.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5445 /* ld.w */, MCK_MemOffsetSimm10_2, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5455 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 5460 /* ldc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 5460 /* ldc3 */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5465 /* ldi.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5471 /* ldi.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5477 /* ldi.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5483 /* ldi.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5489 /* ldl */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5489 /* ldl */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6, 5493 /* ldpc */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6, 5493 /* ldpc */, MCK_JumpTarget, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5498 /* ldr */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5498 /* ldr */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5502 /* ldxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5502 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5502 /* ldxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5502 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5508 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5508 /* lh */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_InMicroMips, 5508 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5508 /* lh */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5511 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5511 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5511 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5511 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5515 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5515 /* lhu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_InMicroMips, 5515 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5515 /* lhu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_InMicroMips, 5519 /* lhu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5519 /* lhu16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5525 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5525 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5525 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5525 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5530 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
+ { Feature_HasDSP, 5530 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
+ { 0, 5534 /* li */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 5537 /* li.d */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotFP64bit|Feature_IsNotSoftFloat, 5537 /* li.d */, MCK_StrictlyAFGR64AsmReg, 1 /* 0 */ },
+ { Feature_IsFP64bit|Feature_IsNotSoftFloat, 5537 /* li.d */, MCK_StrictlyFGR64AsmReg, 1 /* 0 */ },
+ { 0, 5542 /* li.s */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_IsNotSoftFloat, 5542 /* li.s */, MCK_StrictlyFGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5547 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5547 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5552 /* ll */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5559 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5559 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5559 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5559 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5571 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_InMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5577 /* lw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_NotInMips16Mode|Feature_HasDSP, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotInMips16Mode|Feature_HasDSP, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5577 /* lw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 5577 /* lw */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5577 /* lw */, MCK_MicroMipsMemGP, 2 /* 1 */ },
+ { Feature_InMicroMips, 5580 /* lw16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5580 /* lw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5585 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5585 /* lwc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 5585 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 5585 /* lwc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5590 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 5595 /* lwc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 5595 /* lwc3 */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5600 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5600 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5600 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 5600 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5604 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5604 /* lwl */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5604 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5604 /* lwl */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5608 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5608 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5608 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5608 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips, 5613 /* lwm */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 5613 /* lwm */, MCK_RegList, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5617 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5617 /* lwm16 */, MCK_RegList16, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5617 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5617 /* lwm16 */, MCK_RegList16, 1 /* 0 */ },
+ { Feature_InMicroMips, 5623 /* lwm32 */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 5623 /* lwm32 */, MCK_RegList, 1 /* 0 */ },
+ { Feature_InMicroMips, 5629 /* lwp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 5629 /* lwp */, MCK_MemOffsetSimm12, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 5633 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 5633 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5638 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5638 /* lwr */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5638 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5638 /* lwr */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5642 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5642 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5642 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5642 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5647 /* lwu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5647 /* lwu */, MCK_MemOffsetSimm12, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5647 /* lwu */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5647 /* lwu */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5651 /* lwupc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5657 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
+ { Feature_HasDSP, 5657 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_InMicroMips, 5667 /* lwxs */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5672 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5672 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5672 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5672 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 5672 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 5672 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5677 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 5677 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5677 /* madd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5684 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 5684 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5691 /* madd_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5700 /* madd_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5709 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5709 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5717 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5717 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5725 /* maddr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5735 /* maddr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5745 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 5745 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5745 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5745 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 5745 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 5745 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5751 /* maddv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5759 /* maddv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5767 /* maddv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5775 /* maddv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5833 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5833 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5839 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5839 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5845 /* max_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5853 /* max_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5861 /* max_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5869 /* max_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5877 /* max_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5885 /* max_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5893 /* max_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5901 /* max_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5909 /* max_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5917 /* max_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5925 /* max_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5933 /* max_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5941 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5941 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5948 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5948 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5955 /* maxi_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5964 /* maxi_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5973 /* maxi_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5982 /* maxi_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 5991 /* maxi_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6000 /* maxi_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6009 /* maxi_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6018 /* maxi_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6060 /* mfhc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6060 /* mfhc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6073 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 6073 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6078 /* mfhi16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6085 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 6085 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6090 /* mflo16 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6097 /* mftacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6097 /* mftacx */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6097 /* mftacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6104 /* mftc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6104 /* mftc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6104 /* mftc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6104 /* mftc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6110 /* mftc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6110 /* mftc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6116 /* mftdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6123 /* mftgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasMT, 6130 /* mfthc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6130 /* mfthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6137 /* mfthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6137 /* mfthi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6137 /* mfthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6143 /* mftlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6143 /* mftlo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6143 /* mftlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 6149 /* mftr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6154 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6154 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6160 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6160 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6166 /* min_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6174 /* min_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6182 /* min_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6190 /* min_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6198 /* min_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6206 /* min_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6214 /* min_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6222 /* min_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6230 /* min_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6238 /* min_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6246 /* min_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6254 /* min_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6262 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6262 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6269 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6269 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6276 /* mini_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6285 /* mini_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6294 /* mini_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6303 /* mini_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6312 /* mini_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6321 /* mini_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6330 /* mini_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6339 /* mini_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6348 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6348 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6352 /* mod_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6360 /* mod_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6368 /* mod_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6376 /* mod_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6384 /* mod_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6392 /* mod_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6400 /* mod_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6408 /* mod_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6416 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 6416 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6423 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6423 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6428 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6428 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6428 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6428 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_IsGP64bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_IsGP64bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6445 /* move.v */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6452 /* move16 */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6459 /* movep */, MCK_GPRMM16AsmRegMoveP, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6459 /* movep */, MCK_MovePRegPair, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6459 /* movep */, MCK_GPRMM16AsmRegMoveP, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6459 /* movep */, MCK_MovePRegPair, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6465 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6465 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6465 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6465 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6470 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6477 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6477 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6477 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6477 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6484 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6484 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6489 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6496 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6496 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6496 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6496 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6503 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6503 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6503 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6503 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6508 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6515 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6515 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6515 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6515 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6522 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6522 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6527 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6534 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6534 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6534 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6534 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6541 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6541 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6541 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6541 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 6541 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 6541 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6546 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 6546 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6546 /* msub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6553 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 6553 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6560 /* msub_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6569 /* msub_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6578 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6578 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6586 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6586 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6594 /* msubr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6604 /* msubr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6614 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6614 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6614 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6614 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 6614 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 6614 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6620 /* msubv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6628 /* msubv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6636 /* msubv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6644 /* msubv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6685 /* mthc2 */, MCK_COP2AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6685 /* mthc2 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6698 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 6698 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6703 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6703 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 6703 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 6703 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6710 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 6710 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasCnMips, 6715 /* mtm0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 6720 /* mtm1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 6725 /* mtm2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 6730 /* mtp0 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 6735 /* mtp1 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 6740 /* mtp2 */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6745 /* mttacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6745 /* mttacx */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6745 /* mttacx */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6752 /* mttc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6752 /* mttc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6752 /* mttc0 */, MCK_COP0AsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6752 /* mttc0 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6758 /* mttc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6758 /* mttc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6764 /* mttdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6771 /* mttgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasMT, 6778 /* mtthc1 */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6778 /* mtthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6785 /* mtthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6785 /* mtthi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6785 /* mtthi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 6791 /* mttlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasMT, 6791 /* mttlo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ },
+ { Feature_HasMT, 6791 /* mttlo */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 6797 /* mttr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6802 /* muh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6802 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6802 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6806 /* muhu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6806 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6806 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6815 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6815 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6815 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6815 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 6821 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 6821 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6834 /* mul_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6842 /* mul_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 6850 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 6850 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6859 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 6859 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6873 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 6873 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6887 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 6887 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6902 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 6902 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6917 /* mulo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6917 /* mulo */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6922 /* mulou */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6922 /* mulou */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6928 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 6928 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 6939 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 6939 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 6949 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 6949 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 6959 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 6959 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6968 /* mulr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 6977 /* mulr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7011 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7011 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7011 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7011 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 7011 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 7011 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7016 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7016 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7016 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7016 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_HasDSP, 7016 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 7016 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7022 /* mulu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7022 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7022 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7027 /* mulv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7034 /* mulv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7041 /* mulv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7048 /* mulv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7059 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7059 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7059 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7059 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7076 /* nloc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7083 /* nloc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7090 /* nloc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7097 /* nloc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7104 /* nlzc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7111 /* nlzc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7118 /* nlzc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7125 /* nlzc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7132 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7132 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7132 /* nmadd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7140 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7140 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7148 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7148 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7148 /* nmsub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7156 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7156 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ },
+ { Feature_IsGP32bit, 7168 /* nor */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_IsGP64bit, 7168 /* nor */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_IsGP32bit, 7168 /* nor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_IsGP64bit, 7168 /* nor */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7172 /* nor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7178 /* nori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7189 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7189 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7198 /* or.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7203 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7203 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7212 /* ori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7218 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 7218 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7234 /* pckev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7242 /* pckev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7250 /* pckev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7258 /* pckev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7266 /* pckod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7274 /* pckod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7282 /* pckod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7290 /* pckod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7298 /* pcnt.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7305 /* pcnt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7312 /* pcnt.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7319 /* pcnt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7326 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 7326 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7334 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 7334 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasCnMips, 7342 /* pop */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 7342 /* pop */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7346 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7346 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7359 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7359 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7372 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7372 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7387 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7387 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7403 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7403 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7418 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7418 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7434 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7434 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7448 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7448 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7463 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7463 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7477 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7477 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 7492 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 7492 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 7504 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 7504 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 7519 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 7519 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7536 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 7536 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7548 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 7548 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7561 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 7561 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7576 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 7576 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7592 /* pref */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7592 /* pref */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7592 /* pref */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7592 /* pref */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7597 /* prefe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 7597 /* prefe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7603 /* prefx */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 7609 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 7609 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7617 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7617 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7628 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 7628 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7640 /* rdpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7647 /* recip.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7647 /* recip.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7647 /* recip.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7647 /* recip.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7655 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 7655 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7672 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 7672 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7680 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 7680 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7688 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7688 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 7697 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 7697 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7706 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7706 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7713 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7713 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 7720 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 7720 /* rol */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 7720 /* rol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { 0, 7720 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 7724 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 7724 /* ror */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 7724 /* ror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { 0, 7724 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7733 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 7733 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7739 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7739 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7749 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7749 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7749 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7749 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7779 /* rsqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7779 /* rsqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7779 /* rsqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7779 /* rsqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7787 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_NotInMips16Mode|Feature_IsNotSoftFloat, 7787 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7799 /* s.s */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7799 /* s.s */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7803 /* sat_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7811 /* sat_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7819 /* sat_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7827 /* sat_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7835 /* sat_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7843 /* sat_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7851 /* sat_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 7859 /* sat_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 7867 /* sb */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7867 /* sb */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 7867 /* sb */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7870 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7870 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7870 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7870 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7875 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7875 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 7875 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 7875 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 7879 /* sc */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 7882 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6, 7882 /* scd */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7882 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7882 /* scd */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7886 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7886 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 7886 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 7886 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips3, 7890 /* sd */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips3, 7890 /* sd */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 7890 /* sd */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 7890 /* sd */, MCK_MemOffsetSimmPtr, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7912 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 7917 /* sdc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 7917 /* sdc3 */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7922 /* sdl */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7922 /* sdl */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7926 /* sdr */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7926 /* sdr */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7930 /* sdxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7930 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7930 /* sdxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7930 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7944 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7944 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7950 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7950 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7956 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7956 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7956 /* seleqz */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7963 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7963 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7972 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7972 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7981 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7981 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7981 /* selnez */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7988 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7988 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7997 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 7997 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 8006 /* seq */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasCnMips, 8006 /* seq */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasCnMips, 8010 /* seqi */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 8010 /* seqi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8024 /* sh */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8024 /* sh */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8024 /* sh */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 8027 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 8027 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8027 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8027 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 8032 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 8032 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 8032 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 8032 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8036 /* shf.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8042 /* shf.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8048 /* shf.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8054 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 8054 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8060 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8060 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_HasDSP, 8060 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ },
+ { Feature_HasDSP, 8060 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8067 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 8067 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8075 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 8075 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8083 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 8083 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8093 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 8093 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8102 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8102 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8111 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8111 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8120 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8120 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8131 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8131 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8141 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 8141 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8149 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 8149 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8157 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 8157 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8167 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 8167 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8177 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 8177 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8186 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8186 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8195 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 8195 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8204 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8204 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8215 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 8215 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8226 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8226 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8236 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSPR2, 8236 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8244 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasDSP, 8244 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8252 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 8252 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8261 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8261 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8270 /* sld.b */, MCK_GPR32AsmReg, 8 /* 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8270 /* sld.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8276 /* sld.d */, MCK_GPR32AsmReg, 8 /* 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8276 /* sld.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8282 /* sld.h */, MCK_GPR32AsmReg, 8 /* 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8282 /* sld.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8288 /* sld.w */, MCK_GPR32AsmReg, 8 /* 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8288 /* sld.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8294 /* sldi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8301 /* sldi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8308 /* sldi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8315 /* sldi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8326 /* sll.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8332 /* sll.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8338 /* sll.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8344 /* sll.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 8350 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8350 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8356 /* slli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8363 /* slli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8370 /* slli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8377 /* slli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8384 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8384 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_IsGP64bit, 8389 /* slt */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_IsGP64bit, 8389 /* slt */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8393 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8393 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8398 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8398 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_IsGP64bit, 8404 /* sltu */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_IsGP64bit, 8404 /* sltu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasCnMips, 8409 /* sne */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasCnMips, 8409 /* sne */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasCnMips, 8413 /* snei */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasCnMips, 8413 /* snei */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8418 /* splat.b */, MCK_GPR32AsmReg, 8 /* 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8418 /* splat.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8426 /* splat.d */, MCK_GPR32AsmReg, 8 /* 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8426 /* splat.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8434 /* splat.h */, MCK_GPR32AsmReg, 8 /* 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8434 /* splat.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8442 /* splat.w */, MCK_GPR32AsmReg, 8 /* 3 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8442 /* splat.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8450 /* splati.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8459 /* splati.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8468 /* splati.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8477 /* splati.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8486 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8486 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8486 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8486 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8493 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 8493 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8504 /* sra.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8510 /* sra.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8516 /* sra.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8522 /* sra.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8528 /* srai.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8535 /* srai.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8542 /* srai.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8549 /* srai.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8556 /* srar.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8563 /* srar.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8570 /* srar.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8577 /* srar.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8584 /* srari.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8592 /* srari.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8600 /* srari.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8608 /* srari.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8616 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8616 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8625 /* srl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8631 /* srl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8637 /* srl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8643 /* srl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 8649 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8649 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8655 /* srli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8662 /* srli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8669 /* srli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8676 /* srli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8683 /* srlr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8690 /* srlr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8697 /* srlr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8704 /* srlr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8711 /* srlri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8719 /* srlri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8727 /* srlri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8735 /* srlri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8743 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips, 8743 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8754 /* st.b */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8754 /* st.b */, MCK_MemOffsetSimm10, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8759 /* st.d */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8759 /* st.d */, MCK_MemOffsetSimm10_3, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8764 /* st.h */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8764 /* st.h */, MCK_MemOffsetSimm10_1, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8769 /* st.w */, MCK_MSA128AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8769 /* st.w */, MCK_MemOffsetSimm10_2, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_InvNum, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_InvNum, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8778 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8778 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8778 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8778 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8790 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8790 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8798 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8798 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 8808 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 8808 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8817 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 8817 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8826 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 8826 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8834 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 8834 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 8845 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 8845 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8855 /* subs_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8864 /* subs_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8873 /* subs_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8882 /* subs_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8891 /* subs_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8900 /* subs_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8909 /* subs_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8918 /* subs_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8927 /* subsus_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8938 /* subsus_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8949 /* subsus_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8960 /* subsus_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8971 /* subsuu_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8982 /* subsuu_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 8993 /* subsuu_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9004 /* subsuu_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 9015 /* subu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 9015 /* subu */, MCK_InvNum, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { 0, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 9015 /* subu */, MCK_InvNum, 4 /* 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 9020 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 9020 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 9028 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 9028 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9036 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9036 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 9043 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 9043 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 9053 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP, 9053 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 9063 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 9063 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasDSPR2, 9072 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSPR2, 9072 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9083 /* subv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9090 /* subv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9097 /* subv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9104 /* subv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9111 /* subvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9119 /* subvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9127 /* subvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9135 /* subvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9143 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9149 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_NotInMips16Mode|Feature_HasDSP, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_NotInMips16Mode|Feature_HasDSP, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 9149 /* sw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9152 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9152 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9152 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9152 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9157 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9157 /* swc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 9157 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 9157 /* swc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9162 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 9167 /* swc3 */, MCK_COP3AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 9167 /* swc3 */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 9172 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 9172 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 9172 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasEVA, 9172 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9176 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9176 /* swl */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9176 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9176 /* swl */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9180 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9180 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9180 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9180 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips, 9185 /* swm */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 9185 /* swm */, MCK_RegList, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9189 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9189 /* swm16 */, MCK_RegList16, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9189 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9189 /* swm16 */, MCK_RegList16, 1 /* 0 */ },
+ { Feature_InMicroMips, 9195 /* swm32 */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips, 9195 /* swm32 */, MCK_RegList, 1 /* 0 */ },
+ { Feature_InMicroMips, 9201 /* swp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 9201 /* swp */, MCK_MemOffsetSimm12, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9205 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9205 /* swr */, MCK_Mem, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9205 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9205 /* swr */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9209 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9209 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9209 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9209 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9273 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9273 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9282 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9282 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9287 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9287 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9382 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9382 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9387 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9387 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9402 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9402 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9407 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9407 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9417 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9417 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9417 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9417 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ },
+ { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ },
+ { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ },
+ { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_IsNotSoftFloat, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ },
+ { 0, 9437 /* trunc.w.s */, MCK_GPR32AsmReg, 4 /* 2 */ },
+ { 0, 9447 /* ulh */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 9447 /* ulh */, MCK_Mem, 2 /* 1 */ },
+ { 0, 9451 /* ulhu */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 9451 /* ulhu */, MCK_Mem, 2 /* 1 */ },
+ { 0, 9456 /* ulw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 9456 /* ulw */, MCK_Mem, 2 /* 1 */ },
+ { 0, 9460 /* ush */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 9460 /* ush */, MCK_Mem, 2 /* 1 */ },
+ { 0, 9464 /* usw */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { 0, 9464 /* usw */, MCK_Mem, 2 /* 1 */ },
+ { Feature_HasCnMips, 9468 /* v3mulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasCnMips, 9468 /* v3mulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasCnMips, 9475 /* vmm0 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasCnMips, 9475 /* vmm0 */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasCnMips, 9480 /* vmulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasCnMips, 9480 /* vmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9486 /* vshf.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9493 /* vshf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9500 /* vshf.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9507 /* vshf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_HasDSP|Feature_NotInMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP|Feature_InMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasDSP, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasDSP|Feature_NotInMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9525 /* wrpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR64AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR64AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9541 /* xor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9547 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9547 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_InMicroMips|Feature_HasMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_NotInMicroMips, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_InMicroMips|Feature_NotMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasStdEnc|Feature_HasMSA, 9558 /* xori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ },
+ { Feature_HasMT|Feature_NotInMicroMips, 9565 /* yield */, MCK_GPR32AsmReg, 1 /* 0 */ },
+ { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 9565 /* yield */, MCK_GPR32AsmReg, 3 /* 0, 1 */ },
+};
+
+OperandMatchResultTy MipsAsmParser::
+tryCustomParseOperand(OperandVector &Operands,
+ unsigned MCK) {
+
+ switch(MCK) {
+ case MCK_ACC64DSPAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_AFGR64AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_CCRAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_COP0AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_COP2AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_COP3AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_FCCAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_FGR32AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_FGR64AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_FGRH32AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_GPR32AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_GPR32NonZeroAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_GPR32ZeroAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_GPR64AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_GPRMM16AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_GPRMM16AsmRegMoveP:
+ return parseAnyRegister(Operands);
+ case MCK_GPRMM16AsmRegZero:
+ return parseAnyRegister(Operands);
+ case MCK_HI32DSPAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_HWRegsAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_LO32DSPAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_MSA128AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_MSACtrlAsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_MicroMipsMemGP:
+ return parseMemOperand(Operands);
+ case MCK_MicroMipsMem:
+ return parseMemOperand(Operands);
+ case MCK_MicroMipsMemSP:
+ return parseMemOperand(Operands);
+ case MCK_InvNum:
+ return parseInvNum(Operands);
+ case MCK_JumpTarget:
+ return parseJumpTarget(Operands);
+ case MCK_MemOffsetSimm10:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetSimm10_1:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetSimm10_2:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetSimm10_3:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetSimm11:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetSimm12:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetSimm16:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetSimm9:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetSimmPtr:
+ return parseMemOperand(Operands);
+ case MCK_MemOffsetUimm4:
+ return parseMemOperand(Operands);
+ case MCK_Mem:
+ return parseMemOperand(Operands);
+ case MCK_MovePRegPair:
+ return parseMovePRegPair(Operands);
+ case MCK_RegList16:
+ return parseRegisterList(Operands);
+ case MCK_RegList:
+ return parseRegisterList(Operands);
+ case MCK_StrictlyAFGR64AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_StrictlyFGR32AsmReg:
+ return parseAnyRegister(Operands);
+ case MCK_StrictlyFGR64AsmReg:
+ return parseAnyRegister(Operands);
+ default:
+ return MatchOperand_NoMatch;
+ }
+ return MatchOperand_NoMatch;
+}
+
+OperandMatchResultTy MipsAsmParser::
+MatchOperandParserImpl(OperandVector &Operands,
+ StringRef Mnemonic,
+ bool ParseForAllFeatures) {
+ // Get the current feature set.
+ uint64_t AvailableFeatures = getAvailableFeatures();
+
+ // Get the next operand index.
+ unsigned NextOpNum = Operands.size() - 1;
+ // Search the table.
+ auto MnemonicRange =
+ std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
+ Mnemonic, LessOpcodeOperand());
+
+ if (MnemonicRange.first == MnemonicRange.second)
+ return MatchOperand_NoMatch;
+
+ for (const OperandMatchEntry *it = MnemonicRange.first,
+ *ie = MnemonicRange.second; it != ie; ++it) {
+ // equal_range guarantees that instruction mnemonic matches.
+ assert(Mnemonic == it->getMnemonic());
+
+ // check if the available features match
+ if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures)
+ continue;
+
+ // check if the operand in question has a custom parser.
+ if (!(it->OperandMask & (1 << NextOpNum)))
+ continue;
+
+ // call custom parse method to handle the operand
+ OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
+ if (Result != MatchOperand_NoMatch)
+ return Result;
+ }
+
+ // Okay, we had no match.
+ return MatchOperand_NoMatch;
+}
+
+#endif // GET_MATCHER_IMPLEMENTATION
+
+
+#ifdef GET_MNEMONIC_SPELL_CHECKER
+#undef GET_MNEMONIC_SPELL_CHECKER
+
+static std::string MipsMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) {
+ const unsigned MaxEditDist = 2;
+ std::vector<StringRef> Candidates;
+ StringRef Prev = "";
+
+ // Find the appropriate table for this asm variant.
+ const MatchEntry *Start, *End;
+ switch (VariantID) {
+ default: llvm_unreachable("invalid variant!");
+ case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
+ }
+
+ for (auto I = Start; I < End; I++) {
+ // Ignore unsupported instructions.
+ if ((FBS & I->RequiredFeatures) != I->RequiredFeatures)
+ continue;
+
+ StringRef T = I->getMnemonic();
+ // Avoid recomputing the edit distance for the same string.
+ if (T.equals(Prev))
+ continue;
+
+ Prev = T;
+ unsigned Dist = S.edit_distance(T, false, MaxEditDist);
+ if (Dist <= MaxEditDist)
+ Candidates.push_back(T);
+ }
+
+ if (Candidates.empty())
+ return "";
+
+ std::string Res = ", did you mean: ";
+ unsigned i = 0;
+ for( ; i < Candidates.size() - 1; i++)
+ Res += Candidates[i].str() + ", ";
+ return Res + Candidates[i].str() + "?";
+}
+
+#endif // GET_MNEMONIC_SPELL_CHECKER
+
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenAsmWriter.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenAsmWriter.inc
new file mode 100644
index 0000000..c36dae6
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenAsmWriter.inc
@@ -0,0 +1,9561 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Assembly Writer Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+void MipsInstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {
+ static const char AsmStrs[] = {
+ /* 0 */ 'd', 'm', 'f', 'c', '0', 9, 0,
+ /* 7 */ 'd', 'm', 'f', 'g', 'c', '0', 9, 0,
+ /* 15 */ 'm', 'f', 'h', 'g', 'c', '0', 9, 0,
+ /* 23 */ 'm', 't', 'h', 'g', 'c', '0', 9, 0,
+ /* 31 */ 'd', 'm', 't', 'g', 'c', '0', 9, 0,
+ /* 39 */ 'm', 'f', 'h', 'c', '0', 9, 0,
+ /* 46 */ 'm', 't', 'h', 'c', '0', 9, 0,
+ /* 53 */ 'd', 'm', 't', 'c', '0', 9, 0,
+ /* 60 */ 'v', 'm', 'm', '0', 9, 0,
+ /* 66 */ 'm', 't', 'm', '0', 9, 0,
+ /* 72 */ 'm', 't', 'p', '0', 9, 0,
+ /* 78 */ 'b', 'b', 'i', 't', '0', 9, 0,
+ /* 85 */ 'l', 'd', 'c', '1', 9, 0,
+ /* 91 */ 's', 'd', 'c', '1', 9, 0,
+ /* 97 */ 'c', 'f', 'c', '1', 9, 0,
+ /* 103 */ 'd', 'm', 'f', 'c', '1', 9, 0,
+ /* 110 */ 'm', 'f', 'h', 'c', '1', 9, 0,
+ /* 117 */ 'm', 't', 'h', 'c', '1', 9, 0,
+ /* 124 */ 'c', 't', 'c', '1', 9, 0,
+ /* 130 */ 'd', 'm', 't', 'c', '1', 9, 0,
+ /* 137 */ 'l', 'w', 'c', '1', 9, 0,
+ /* 143 */ 's', 'w', 'c', '1', 9, 0,
+ /* 149 */ 'l', 'd', 'x', 'c', '1', 9, 0,
+ /* 156 */ 's', 'd', 'x', 'c', '1', 9, 0,
+ /* 163 */ 'l', 'u', 'x', 'c', '1', 9, 0,
+ /* 170 */ 's', 'u', 'x', 'c', '1', 9, 0,
+ /* 177 */ 'l', 'w', 'x', 'c', '1', 9, 0,
+ /* 184 */ 's', 'w', 'x', 'c', '1', 9, 0,
+ /* 191 */ 'm', 't', 'm', '1', 9, 0,
+ /* 197 */ 'm', 't', 'p', '1', 9, 0,
+ /* 203 */ 'b', 'b', 'i', 't', '1', 9, 0,
+ /* 210 */ 'b', 'b', 'i', 't', '0', '3', '2', 9, 0,
+ /* 219 */ 'b', 'b', 'i', 't', '1', '3', '2', 9, 0,
+ /* 228 */ 'd', 's', 'r', 'a', '3', '2', 9, 0,
+ /* 236 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 9, 0,
+ /* 246 */ 'd', 's', 'l', 'l', '3', '2', 9, 0,
+ /* 254 */ 'd', 's', 'r', 'l', '3', '2', 9, 0,
+ /* 262 */ 'l', 'w', 'm', '3', '2', 9, 0,
+ /* 269 */ 's', 'w', 'm', '3', '2', 9, 0,
+ /* 276 */ 'd', 'r', 'o', 't', 'r', '3', '2', 9, 0,
+ /* 285 */ 'c', 'i', 'n', 's', '3', '2', 9, 0,
+ /* 293 */ 'e', 'x', 't', 's', '3', '2', 9, 0,
+ /* 301 */ 'l', 'd', 'c', '2', 9, 0,
+ /* 307 */ 's', 'd', 'c', '2', 9, 0,
+ /* 313 */ 'c', 'f', 'c', '2', 9, 0,
+ /* 319 */ 'd', 'm', 'f', 'c', '2', 9, 0,
+ /* 326 */ 'm', 'f', 'h', 'c', '2', 9, 0,
+ /* 333 */ 'm', 't', 'h', 'c', '2', 9, 0,
+ /* 340 */ 'c', 't', 'c', '2', 9, 0,
+ /* 346 */ 'd', 'm', 't', 'c', '2', 9, 0,
+ /* 353 */ 'l', 'w', 'c', '2', 9, 0,
+ /* 359 */ 's', 'w', 'c', '2', 9, 0,
+ /* 365 */ 'm', 't', 'm', '2', 9, 0,
+ /* 371 */ 'm', 't', 'p', '2', 9, 0,
+ /* 377 */ 'a', 'd', 'd', 'i', 'u', 'r', '2', 9, 0,
+ /* 386 */ 'l', 'd', 'c', '3', 9, 0,
+ /* 392 */ 's', 'd', 'c', '3', 9, 0,
+ /* 398 */ 'l', 'w', 'c', '3', 9, 0,
+ /* 404 */ 's', 'w', 'c', '3', 9, 0,
+ /* 410 */ 'a', 'd', 'd', 'i', 'u', 's', '5', 9, 0,
+ /* 419 */ 's', 'b', '1', '6', 9, 0,
+ /* 425 */ 'b', 'c', '1', '6', 9, 0,
+ /* 431 */ 'j', 'r', 'c', '1', '6', 9, 0,
+ /* 438 */ 'b', 'n', 'e', 'z', 'c', '1', '6', 9, 0,
+ /* 447 */ 'b', 'e', 'q', 'z', 'c', '1', '6', 9, 0,
+ /* 456 */ 'a', 'n', 'd', '1', '6', 9, 0,
+ /* 463 */ 'm', 'o', 'v', 'e', '1', '6', 9, 0,
+ /* 471 */ 's', 'h', '1', '6', 9, 0,
+ /* 477 */ 'a', 'n', 'd', 'i', '1', '6', 9, 0,
+ /* 485 */ 'm', 'f', 'h', 'i', '1', '6', 9, 0,
+ /* 493 */ 'l', 'i', '1', '6', 9, 0,
+ /* 499 */ 'b', 'r', 'e', 'a', 'k', '1', '6', 9, 0,
+ /* 508 */ 's', 'l', 'l', '1', '6', 9, 0,
+ /* 515 */ 's', 'r', 'l', '1', '6', 9, 0,
+ /* 522 */ 'l', 'w', 'm', '1', '6', 9, 0,
+ /* 529 */ 's', 'w', 'm', '1', '6', 9, 0,
+ /* 536 */ 'm', 'f', 'l', 'o', '1', '6', 9, 0,
+ /* 544 */ 's', 'd', 'b', 'b', 'p', '1', '6', 9, 0,
+ /* 553 */ 'j', 'r', '1', '6', 9, 0,
+ /* 559 */ 'x', 'o', 'r', '1', '6', 9, 0,
+ /* 566 */ 'j', 'a', 'l', 'r', 's', '1', '6', 9, 0,
+ /* 575 */ 'n', 'o', 't', '1', '6', 9, 0,
+ /* 582 */ 'l', 'b', 'u', '1', '6', 9, 0,
+ /* 589 */ 's', 'u', 'b', 'u', '1', '6', 9, 0,
+ /* 597 */ 'a', 'd', 'd', 'u', '1', '6', 9, 0,
+ /* 605 */ 'l', 'h', 'u', '1', '6', 9, 0,
+ /* 612 */ 'l', 'w', '1', '6', 9, 0,
+ /* 618 */ 's', 'w', '1', '6', 9, 0,
+ /* 624 */ 'b', 'n', 'e', 'z', '1', '6', 9, 0,
+ /* 632 */ 'b', 'e', 'q', 'z', '1', '6', 9, 0,
+ /* 640 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0,
+ /* 656 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 'a', 9, 0,
+ /* 673 */ 'd', 'l', 'a', 9, 0,
+ /* 678 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0,
+ /* 694 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 'a', 9, 0,
+ /* 711 */ 'd', 's', 'r', 'a', 9, 0,
+ /* 717 */ 'd', 'l', 's', 'a', 9, 0,
+ /* 723 */ 'c', 'f', 'c', 'm', 's', 'a', 9, 0,
+ /* 731 */ 'c', 't', 'c', 'm', 's', 'a', 9, 0,
+ /* 739 */ 'a', 'd', 'd', '_', 'a', '.', 'b', 9, 0,
+ /* 748 */ 'm', 'i', 'n', '_', 'a', '.', 'b', 9, 0,
+ /* 757 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'b', 9, 0,
+ /* 767 */ 'm', 'a', 'x', '_', 'a', '.', 'b', 9, 0,
+ /* 776 */ 's', 'r', 'a', '.', 'b', 9, 0,
+ /* 783 */ 'n', 'l', 'o', 'c', '.', 'b', 9, 0,
+ /* 791 */ 'n', 'l', 'z', 'c', '.', 'b', 9, 0,
+ /* 799 */ 's', 'l', 'd', '.', 'b', 9, 0,
+ /* 806 */ 'p', 'c', 'k', 'o', 'd', '.', 'b', 9, 0,
+ /* 815 */ 'i', 'l', 'v', 'o', 'd', '.', 'b', 9, 0,
+ /* 824 */ 'i', 'n', 's', 'v', 'e', '.', 'b', 9, 0,
+ /* 833 */ 'v', 's', 'h', 'f', '.', 'b', 9, 0,
+ /* 841 */ 'b', 'n', 'e', 'g', '.', 'b', 9, 0,
+ /* 849 */ 's', 'r', 'a', 'i', '.', 'b', 9, 0,
+ /* 857 */ 's', 'l', 'd', 'i', '.', 'b', 9, 0,
+ /* 865 */ 'a', 'n', 'd', 'i', '.', 'b', 9, 0,
+ /* 873 */ 'b', 'n', 'e', 'g', 'i', '.', 'b', 9, 0,
+ /* 882 */ 'b', 's', 'e', 'l', 'i', '.', 'b', 9, 0,
+ /* 891 */ 's', 'l', 'l', 'i', '.', 'b', 9, 0,
+ /* 899 */ 's', 'r', 'l', 'i', '.', 'b', 9, 0,
+ /* 907 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'b', 9, 0,
+ /* 917 */ 'c', 'e', 'q', 'i', '.', 'b', 9, 0,
+ /* 925 */ 's', 'r', 'a', 'r', 'i', '.', 'b', 9, 0,
+ /* 934 */ 'b', 'c', 'l', 'r', 'i', '.', 'b', 9, 0,
+ /* 943 */ 's', 'r', 'l', 'r', 'i', '.', 'b', 9, 0,
+ /* 952 */ 'n', 'o', 'r', 'i', '.', 'b', 9, 0,
+ /* 960 */ 'x', 'o', 'r', 'i', '.', 'b', 9, 0,
+ /* 968 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'b', 9, 0,
+ /* 978 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'b', 9, 0,
+ /* 988 */ 'b', 's', 'e', 't', 'i', '.', 'b', 9, 0,
+ /* 997 */ 's', 'u', 'b', 'v', 'i', '.', 'b', 9, 0,
+ /* 1006 */ 'a', 'd', 'd', 'v', 'i', '.', 'b', 9, 0,
+ /* 1015 */ 'b', 'm', 'z', 'i', '.', 'b', 9, 0,
+ /* 1023 */ 'b', 'm', 'n', 'z', 'i', '.', 'b', 9, 0,
+ /* 1032 */ 'f', 'i', 'l', 'l', '.', 'b', 9, 0,
+ /* 1040 */ 's', 'l', 'l', '.', 'b', 9, 0,
+ /* 1047 */ 's', 'r', 'l', '.', 'b', 9, 0,
+ /* 1054 */ 'b', 'i', 'n', 's', 'l', '.', 'b', 9, 0,
+ /* 1063 */ 'i', 'l', 'v', 'l', '.', 'b', 9, 0,
+ /* 1071 */ 'c', 'e', 'q', '.', 'b', 9, 0,
+ /* 1078 */ 's', 'r', 'a', 'r', '.', 'b', 9, 0,
+ /* 1086 */ 'b', 'c', 'l', 'r', '.', 'b', 9, 0,
+ /* 1094 */ 's', 'r', 'l', 'r', '.', 'b', 9, 0,
+ /* 1102 */ 'b', 'i', 'n', 's', 'r', '.', 'b', 9, 0,
+ /* 1111 */ 'i', 'l', 'v', 'r', '.', 'b', 9, 0,
+ /* 1119 */ 'a', 's', 'u', 'b', '_', 's', '.', 'b', 9, 0,
+ /* 1129 */ 'm', 'o', 'd', '_', 's', '.', 'b', 9, 0,
+ /* 1138 */ 'c', 'l', 'e', '_', 's', '.', 'b', 9, 0,
+ /* 1147 */ 'a', 'v', 'e', '_', 's', '.', 'b', 9, 0,
+ /* 1156 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'b', 9, 0,
+ /* 1166 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'b', 9, 0,
+ /* 1176 */ 'c', 'l', 't', 'i', '_', 's', '.', 'b', 9, 0,
+ /* 1186 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'b', 9, 0,
+ /* 1196 */ 'm', 'i', 'n', '_', 's', '.', 'b', 9, 0,
+ /* 1205 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'b', 9, 0,
+ /* 1215 */ 's', 'u', 'b', 's', '_', 's', '.', 'b', 9, 0,
+ /* 1225 */ 'a', 'd', 'd', 's', '_', 's', '.', 'b', 9, 0,
+ /* 1235 */ 's', 'a', 't', '_', 's', '.', 'b', 9, 0,
+ /* 1244 */ 'c', 'l', 't', '_', 's', '.', 'b', 9, 0,
+ /* 1253 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'b', 9, 0,
+ /* 1265 */ 'd', 'i', 'v', '_', 's', '.', 'b', 9, 0,
+ /* 1274 */ 'm', 'a', 'x', '_', 's', '.', 'b', 9, 0,
+ /* 1283 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'b', 9, 0,
+ /* 1293 */ 's', 'p', 'l', 'a', 't', '.', 'b', 9, 0,
+ /* 1302 */ 'b', 's', 'e', 't', '.', 'b', 9, 0,
+ /* 1310 */ 'p', 'c', 'n', 't', '.', 'b', 9, 0,
+ /* 1318 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'b', 9, 0,
+ /* 1328 */ 's', 't', '.', 'b', 9, 0,
+ /* 1334 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'b', 9, 0,
+ /* 1344 */ 'm', 'o', 'd', '_', 'u', '.', 'b', 9, 0,
+ /* 1353 */ 'c', 'l', 'e', '_', 'u', '.', 'b', 9, 0,
+ /* 1362 */ 'a', 'v', 'e', '_', 'u', '.', 'b', 9, 0,
+ /* 1371 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'b', 9, 0,
+ /* 1381 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'b', 9, 0,
+ /* 1391 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'b', 9, 0,
+ /* 1401 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'b', 9, 0,
+ /* 1411 */ 'm', 'i', 'n', '_', 'u', '.', 'b', 9, 0,
+ /* 1420 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'b', 9, 0,
+ /* 1430 */ 's', 'u', 'b', 's', '_', 'u', '.', 'b', 9, 0,
+ /* 1440 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'b', 9, 0,
+ /* 1450 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'b', 9, 0,
+ /* 1462 */ 's', 'a', 't', '_', 'u', '.', 'b', 9, 0,
+ /* 1471 */ 'c', 'l', 't', '_', 'u', '.', 'b', 9, 0,
+ /* 1480 */ 'd', 'i', 'v', '_', 'u', '.', 'b', 9, 0,
+ /* 1489 */ 'm', 'a', 'x', '_', 'u', '.', 'b', 9, 0,
+ /* 1498 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'b', 9, 0,
+ /* 1508 */ 'm', 's', 'u', 'b', 'v', '.', 'b', 9, 0,
+ /* 1517 */ 'm', 'a', 'd', 'd', 'v', '.', 'b', 9, 0,
+ /* 1526 */ 'p', 'c', 'k', 'e', 'v', '.', 'b', 9, 0,
+ /* 1535 */ 'i', 'l', 'v', 'e', 'v', '.', 'b', 9, 0,
+ /* 1544 */ 'm', 'u', 'l', 'v', '.', 'b', 9, 0,
+ /* 1552 */ 'b', 'z', '.', 'b', 9, 0,
+ /* 1558 */ 'b', 'n', 'z', '.', 'b', 9, 0,
+ /* 1565 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0,
+ /* 1573 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0,
+ /* 1582 */ 's', 'e', 'b', 9, 0,
+ /* 1587 */ 'j', 'a', 'l', 'r', 'c', '.', 'h', 'b', 9, 0,
+ /* 1597 */ 'j', 'r', '.', 'h', 'b', 9, 0,
+ /* 1604 */ 'j', 'a', 'l', 'r', '.', 'h', 'b', 9, 0,
+ /* 1613 */ 'l', 'b', 9, 0,
+ /* 1617 */ 's', 'h', 'r', 'a', '.', 'q', 'b', 9, 0,
+ /* 1626 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0,
+ /* 1640 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0,
+ /* 1653 */ 'c', 'm', 'p', 'u', '.', 'l', 'e', '.', 'q', 'b', 9, 0,
+ /* 1665 */ 's', 'u', 'b', 'u', 'h', '.', 'q', 'b', 9, 0,
+ /* 1675 */ 'a', 'd', 'd', 'u', 'h', '.', 'q', 'b', 9, 0,
+ /* 1685 */ 'p', 'i', 'c', 'k', '.', 'q', 'b', 9, 0,
+ /* 1694 */ 's', 'h', 'l', 'l', '.', 'q', 'b', 9, 0,
+ /* 1703 */ 'r', 'e', 'p', 'l', '.', 'q', 'b', 9, 0,
+ /* 1712 */ 's', 'h', 'r', 'l', '.', 'q', 'b', 9, 0,
+ /* 1721 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0,
+ /* 1735 */ 'c', 'm', 'p', 'g', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0,
+ /* 1748 */ 'c', 'm', 'p', 'u', '.', 'e', 'q', '.', 'q', 'b', 9, 0,
+ /* 1760 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'q', 'b', 9, 0,
+ /* 1771 */ 's', 'u', 'b', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0,
+ /* 1783 */ 'a', 'd', 'd', 'u', 'h', '_', 'r', '.', 'q', 'b', 9, 0,
+ /* 1795 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'q', 'b', 9, 0,
+ /* 1807 */ 'a', 'b', 's', 'q', '_', 's', '.', 'q', 'b', 9, 0,
+ /* 1818 */ 's', 'u', 'b', 'u', '_', 's', '.', 'q', 'b', 9, 0,
+ /* 1829 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'q', 'b', 9, 0,
+ /* 1840 */ 'c', 'm', 'p', 'g', 'd', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0,
+ /* 1854 */ 'c', 'm', 'p', 'g', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0,
+ /* 1867 */ 'c', 'm', 'p', 'u', '.', 'l', 't', '.', 'q', 'b', 9, 0,
+ /* 1879 */ 's', 'u', 'b', 'u', '.', 'q', 'b', 9, 0,
+ /* 1888 */ 'a', 'd', 'd', 'u', '.', 'q', 'b', 9, 0,
+ /* 1897 */ 's', 'h', 'r', 'a', 'v', '.', 'q', 'b', 9, 0,
+ /* 1907 */ 's', 'h', 'l', 'l', 'v', '.', 'q', 'b', 9, 0,
+ /* 1917 */ 'r', 'e', 'p', 'l', 'v', '.', 'q', 'b', 9, 0,
+ /* 1927 */ 's', 'h', 'r', 'l', 'v', '.', 'q', 'b', 9, 0,
+ /* 1937 */ 'r', 'a', 'd', 'd', 'u', '.', 'w', '.', 'q', 'b', 9, 0,
+ /* 1949 */ 's', 'b', 9, 0,
+ /* 1953 */ 'm', 'o', 'd', 's', 'u', 'b', 9, 0,
+ /* 1961 */ 'm', 's', 'u', 'b', 9, 0,
+ /* 1967 */ 'b', 'p', 'o', 's', 'g', 'e', '3', '2', 'c', 9, 0,
+ /* 1978 */ 'b', 'c', 9, 0,
+ /* 1982 */ 'b', 'g', 'e', 'c', 9, 0,
+ /* 1988 */ 'b', 'n', 'e', 'c', 9, 0,
+ /* 1994 */ 'j', 'i', 'c', 9, 0,
+ /* 1999 */ 'b', 'a', 'l', 'c', 9, 0,
+ /* 2005 */ 'j', 'i', 'a', 'l', 'c', 9, 0,
+ /* 2012 */ 'b', 'g', 'e', 'z', 'a', 'l', 'c', 9, 0,
+ /* 2021 */ 'b', 'l', 'e', 'z', 'a', 'l', 'c', 9, 0,
+ /* 2030 */ 'b', 'n', 'e', 'z', 'a', 'l', 'c', 9, 0,
+ /* 2039 */ 'b', 'e', 'q', 'z', 'a', 'l', 'c', 9, 0,
+ /* 2048 */ 'b', 'g', 't', 'z', 'a', 'l', 'c', 9, 0,
+ /* 2057 */ 'b', 'l', 't', 'z', 'a', 'l', 'c', 9, 0,
+ /* 2066 */ 's', 'y', 'n', 'c', 9, 0,
+ /* 2072 */ 'l', 'd', 'p', 'c', 9, 0,
+ /* 2078 */ 'a', 'u', 'i', 'p', 'c', 9, 0,
+ /* 2085 */ 'a', 'l', 'u', 'i', 'p', 'c', 9, 0,
+ /* 2093 */ 'a', 'd', 'd', 'i', 'u', 'p', 'c', 9, 0,
+ /* 2102 */ 'l', 'w', 'u', 'p', 'c', 9, 0,
+ /* 2109 */ 'l', 'w', 'p', 'c', 9, 0,
+ /* 2115 */ 'b', 'e', 'q', 'c', 9, 0,
+ /* 2121 */ 'j', 'r', 'c', 9, 0,
+ /* 2126 */ 'j', 'a', 'l', 'r', 'c', 9, 0,
+ /* 2133 */ 'a', 'd', 'd', 's', 'c', 9, 0,
+ /* 2140 */ 'b', 'l', 't', 'c', 9, 0,
+ /* 2146 */ 'b', 'g', 'e', 'u', 'c', 9, 0,
+ /* 2153 */ 'b', 'l', 't', 'u', 'c', 9, 0,
+ /* 2160 */ 'b', 'n', 'v', 'c', 9, 0,
+ /* 2166 */ 'b', 'o', 'v', 'c', 9, 0,
+ /* 2172 */ 'a', 'd', 'd', 'w', 'c', 9, 0,
+ /* 2179 */ 'b', 'g', 'e', 'z', 'c', 9, 0,
+ /* 2186 */ 'b', 'l', 'e', 'z', 'c', 9, 0,
+ /* 2193 */ 'b', 'c', '1', 'n', 'e', 'z', 'c', 9, 0,
+ /* 2202 */ 'b', 'c', '2', 'n', 'e', 'z', 'c', 9, 0,
+ /* 2211 */ 'b', 'n', 'e', 'z', 'c', 9, 0,
+ /* 2218 */ 'b', 'c', '1', 'e', 'q', 'z', 'c', 9, 0,
+ /* 2227 */ 'b', 'c', '2', 'e', 'q', 'z', 'c', 9, 0,
+ /* 2236 */ 'b', 'e', 'q', 'z', 'c', 9, 0,
+ /* 2243 */ 'b', 'g', 't', 'z', 'c', 9, 0,
+ /* 2250 */ 'b', 'l', 't', 'z', 'c', 9, 0,
+ /* 2257 */ 'f', 'l', 'o', 'g', '2', '.', 'd', 9, 0,
+ /* 2266 */ 'f', 'e', 'x', 'p', '2', '.', 'd', 9, 0,
+ /* 2275 */ 'a', 'd', 'd', '_', 'a', '.', 'd', 9, 0,
+ /* 2284 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'd', 9, 0,
+ /* 2294 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'd', 9, 0,
+ /* 2304 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'd', 9, 0,
+ /* 2314 */ 'm', 'i', 'n', 'a', '.', 'd', 9, 0,
+ /* 2322 */ 's', 'r', 'a', '.', 'd', 9, 0,
+ /* 2329 */ 'm', 'a', 'x', 'a', '.', 'd', 9, 0,
+ /* 2337 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 2345 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 2354 */ 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 2363 */ 'n', 'l', 'o', 'c', '.', 'd', 9, 0,
+ /* 2371 */ 'n', 'l', 'z', 'c', '.', 'd', 9, 0,
+ /* 2379 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 2387 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 2396 */ 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 2405 */ 's', 'l', 'd', '.', 'd', 9, 0,
+ /* 2412 */ 'p', 'c', 'k', 'o', 'd', '.', 'd', 9, 0,
+ /* 2421 */ 'i', 'l', 'v', 'o', 'd', '.', 'd', 9, 0,
+ /* 2430 */ 'c', '.', 'n', 'g', 'e', '.', 'd', 9, 0,
+ /* 2439 */ 'c', '.', 'l', 'e', '.', 'd', 9, 0,
+ /* 2447 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'd', 9, 0,
+ /* 2457 */ 'f', 'c', 'l', 'e', '.', 'd', 9, 0,
+ /* 2465 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 'd', 9, 0,
+ /* 2475 */ 'c', '.', 'o', 'l', 'e', '.', 'd', 9, 0,
+ /* 2484 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 'd', 9, 0,
+ /* 2495 */ 'f', 's', 'l', 'e', '.', 'd', 9, 0,
+ /* 2503 */ 'c', '.', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2512 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2523 */ 'f', 'c', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2532 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2544 */ 'f', 's', 'u', 'l', 'e', '.', 'd', 9, 0,
+ /* 2553 */ 'f', 'c', 'n', 'e', '.', 'd', 9, 0,
+ /* 2561 */ 'f', 's', 'n', 'e', '.', 'd', 9, 0,
+ /* 2569 */ 'f', 'c', 'u', 'n', 'e', '.', 'd', 9, 0,
+ /* 2578 */ 'f', 's', 'u', 'n', 'e', '.', 'd', 9, 0,
+ /* 2587 */ 'i', 'n', 's', 'v', 'e', '.', 'd', 9, 0,
+ /* 2596 */ 'c', '.', 'f', '.', 'd', 9, 0,
+ /* 2603 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 'd', 9, 0,
+ /* 2613 */ 'f', 'c', 'a', 'f', '.', 'd', 9, 0,
+ /* 2621 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 'd', 9, 0,
+ /* 2632 */ 'f', 's', 'a', 'f', '.', 'd', 9, 0,
+ /* 2640 */ 'm', 's', 'u', 'b', 'f', '.', 'd', 9, 0,
+ /* 2649 */ 'm', 'a', 'd', 'd', 'f', '.', 'd', 9, 0,
+ /* 2658 */ 'v', 's', 'h', 'f', '.', 'd', 9, 0,
+ /* 2666 */ 'c', '.', 's', 'f', '.', 'd', 9, 0,
+ /* 2674 */ 'm', 'o', 'v', 'f', '.', 'd', 9, 0,
+ /* 2682 */ 'b', 'n', 'e', 'g', '.', 'd', 9, 0,
+ /* 2690 */ 's', 'r', 'a', 'i', '.', 'd', 9, 0,
+ /* 2698 */ 's', 'l', 'd', 'i', '.', 'd', 9, 0,
+ /* 2706 */ 'b', 'n', 'e', 'g', 'i', '.', 'd', 9, 0,
+ /* 2715 */ 's', 'l', 'l', 'i', '.', 'd', 9, 0,
+ /* 2723 */ 's', 'r', 'l', 'i', '.', 'd', 9, 0,
+ /* 2731 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'd', 9, 0,
+ /* 2741 */ 'c', 'e', 'q', 'i', '.', 'd', 9, 0,
+ /* 2749 */ 's', 'r', 'a', 'r', 'i', '.', 'd', 9, 0,
+ /* 2758 */ 'b', 'c', 'l', 'r', 'i', '.', 'd', 9, 0,
+ /* 2767 */ 's', 'r', 'l', 'r', 'i', '.', 'd', 9, 0,
+ /* 2776 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'd', 9, 0,
+ /* 2786 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'd', 9, 0,
+ /* 2796 */ 'b', 's', 'e', 't', 'i', '.', 'd', 9, 0,
+ /* 2805 */ 's', 'u', 'b', 'v', 'i', '.', 'd', 9, 0,
+ /* 2814 */ 'a', 'd', 'd', 'v', 'i', '.', 'd', 9, 0,
+ /* 2823 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 'd', 9, 0,
+ /* 2834 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 'd', 9, 0,
+ /* 2845 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 'd', 9, 0,
+ /* 2855 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 'd', 9, 0,
+ /* 2866 */ 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0,
+ /* 2875 */ 's', 'e', 'l', '.', 'd', 9, 0,
+ /* 2882 */ 'c', '.', 'n', 'g', 'l', '.', 'd', 9, 0,
+ /* 2891 */ 'f', 'i', 'l', 'l', '.', 'd', 9, 0,
+ /* 2899 */ 's', 'l', 'l', '.', 'd', 9, 0,
+ /* 2906 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'd', 9, 0,
+ /* 2916 */ 'f', 'f', 'q', 'l', '.', 'd', 9, 0,
+ /* 2924 */ 's', 'r', 'l', '.', 'd', 9, 0,
+ /* 2931 */ 'b', 'i', 'n', 's', 'l', '.', 'd', 9, 0,
+ /* 2940 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0,
+ /* 2948 */ 'i', 'l', 'v', 'l', '.', 'd', 9, 0,
+ /* 2956 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0,
+ /* 2964 */ 'c', '.', 'u', 'n', '.', 'd', 9, 0,
+ /* 2972 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 'd', 9, 0,
+ /* 2982 */ 'f', 'c', 'u', 'n', '.', 'd', 9, 0,
+ /* 2990 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 'd', 9, 0,
+ /* 3001 */ 'f', 's', 'u', 'n', '.', 'd', 9, 0,
+ /* 3009 */ 'm', 'o', 'v', 'n', '.', 'd', 9, 0,
+ /* 3017 */ 'f', 'r', 'c', 'p', '.', 'd', 9, 0,
+ /* 3025 */ 'r', 'e', 'c', 'i', 'p', '.', 'd', 9, 0,
+ /* 3034 */ 'c', '.', 'e', 'q', '.', 'd', 9, 0,
+ /* 3042 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'd', 9, 0,
+ /* 3052 */ 'f', 'c', 'e', 'q', '.', 'd', 9, 0,
+ /* 3060 */ 'c', '.', 's', 'e', 'q', '.', 'd', 9, 0,
+ /* 3069 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 'd', 9, 0,
+ /* 3080 */ 'f', 's', 'e', 'q', '.', 'd', 9, 0,
+ /* 3088 */ 'c', '.', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 3097 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 3108 */ 'f', 'c', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 3117 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 3129 */ 'f', 's', 'u', 'e', 'q', '.', 'd', 9, 0,
+ /* 3138 */ 's', 'r', 'a', 'r', '.', 'd', 9, 0,
+ /* 3146 */ 'b', 'c', 'l', 'r', '.', 'd', 9, 0,
+ /* 3154 */ 's', 'r', 'l', 'r', '.', 'd', 9, 0,
+ /* 3162 */ 'f', 'c', 'o', 'r', '.', 'd', 9, 0,
+ /* 3170 */ 'f', 's', 'o', 'r', '.', 'd', 9, 0,
+ /* 3178 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'd', 9, 0,
+ /* 3188 */ 'f', 'f', 'q', 'r', '.', 'd', 9, 0,
+ /* 3196 */ 'b', 'i', 'n', 's', 'r', '.', 'd', 9, 0,
+ /* 3205 */ 'i', 'l', 'v', 'r', '.', 'd', 9, 0,
+ /* 3213 */ 'c', 'v', 't', '.', 's', '.', 'd', 9, 0,
+ /* 3222 */ 'a', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0,
+ /* 3232 */ 'h', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0,
+ /* 3242 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'd', 9, 0,
+ /* 3253 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'd', 9, 0,
+ /* 3265 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0,
+ /* 3275 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'd', 9, 0,
+ /* 3286 */ 'm', 'o', 'd', '_', 's', '.', 'd', 9, 0,
+ /* 3295 */ 'c', 'l', 'e', '_', 's', '.', 'd', 9, 0,
+ /* 3304 */ 'a', 'v', 'e', '_', 's', '.', 'd', 9, 0,
+ /* 3313 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'd', 9, 0,
+ /* 3323 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'd', 9, 0,
+ /* 3333 */ 'c', 'l', 't', 'i', '_', 's', '.', 'd', 9, 0,
+ /* 3343 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'd', 9, 0,
+ /* 3353 */ 'm', 'i', 'n', '_', 's', '.', 'd', 9, 0,
+ /* 3362 */ 'd', 'o', 't', 'p', '_', 's', '.', 'd', 9, 0,
+ /* 3372 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'd', 9, 0,
+ /* 3382 */ 's', 'u', 'b', 's', '_', 's', '.', 'd', 9, 0,
+ /* 3392 */ 'a', 'd', 'd', 's', '_', 's', '.', 'd', 9, 0,
+ /* 3402 */ 's', 'a', 't', '_', 's', '.', 'd', 9, 0,
+ /* 3411 */ 'c', 'l', 't', '_', 's', '.', 'd', 9, 0,
+ /* 3420 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0,
+ /* 3431 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'd', 9, 0,
+ /* 3442 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'd', 9, 0,
+ /* 3454 */ 'd', 'i', 'v', '_', 's', '.', 'd', 9, 0,
+ /* 3463 */ 'm', 'a', 'x', '_', 's', '.', 'd', 9, 0,
+ /* 3472 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'd', 9, 0,
+ /* 3482 */ 'a', 'b', 's', '.', 'd', 9, 0,
+ /* 3489 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0,
+ /* 3499 */ 's', 'p', 'l', 'a', 't', '.', 'd', 9, 0,
+ /* 3508 */ 'b', 's', 'e', 't', '.', 'd', 9, 0,
+ /* 3516 */ 'c', '.', 'n', 'g', 't', '.', 'd', 9, 0,
+ /* 3525 */ 'c', '.', 'l', 't', '.', 'd', 9, 0,
+ /* 3533 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'd', 9, 0,
+ /* 3543 */ 'f', 'c', 'l', 't', '.', 'd', 9, 0,
+ /* 3551 */ 'c', '.', 'o', 'l', 't', '.', 'd', 9, 0,
+ /* 3560 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 'd', 9, 0,
+ /* 3571 */ 'f', 's', 'l', 't', '.', 'd', 9, 0,
+ /* 3579 */ 'c', '.', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3588 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3599 */ 'f', 'c', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3608 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3620 */ 'f', 's', 'u', 'l', 't', '.', 'd', 9, 0,
+ /* 3629 */ 'p', 'c', 'n', 't', '.', 'd', 9, 0,
+ /* 3637 */ 'f', 'r', 'i', 'n', 't', '.', 'd', 9, 0,
+ /* 3646 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'd', 9, 0,
+ /* 3656 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0,
+ /* 3665 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'd', 9, 0,
+ /* 3675 */ 's', 't', '.', 'd', 9, 0,
+ /* 3681 */ 'm', 'o', 'v', 't', '.', 'd', 9, 0,
+ /* 3689 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0,
+ /* 3699 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0,
+ /* 3709 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'd', 9, 0,
+ /* 3720 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'd', 9, 0,
+ /* 3732 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0,
+ /* 3742 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'd', 9, 0,
+ /* 3753 */ 'm', 'o', 'd', '_', 'u', '.', 'd', 9, 0,
+ /* 3762 */ 'c', 'l', 'e', '_', 'u', '.', 'd', 9, 0,
+ /* 3771 */ 'a', 'v', 'e', '_', 'u', '.', 'd', 9, 0,
+ /* 3780 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'd', 9, 0,
+ /* 3790 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'd', 9, 0,
+ /* 3800 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'd', 9, 0,
+ /* 3810 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'd', 9, 0,
+ /* 3820 */ 'm', 'i', 'n', '_', 'u', '.', 'd', 9, 0,
+ /* 3829 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'd', 9, 0,
+ /* 3839 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'd', 9, 0,
+ /* 3849 */ 's', 'u', 'b', 's', '_', 'u', '.', 'd', 9, 0,
+ /* 3859 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'd', 9, 0,
+ /* 3869 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'd', 9, 0,
+ /* 3881 */ 's', 'a', 't', '_', 'u', '.', 'd', 9, 0,
+ /* 3890 */ 'c', 'l', 't', '_', 'u', '.', 'd', 9, 0,
+ /* 3899 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0,
+ /* 3910 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'd', 9, 0,
+ /* 3921 */ 'd', 'i', 'v', '_', 'u', '.', 'd', 9, 0,
+ /* 3930 */ 'm', 'a', 'x', '_', 'u', '.', 'd', 9, 0,
+ /* 3939 */ 'm', 's', 'u', 'b', 'v', '.', 'd', 9, 0,
+ /* 3948 */ 'm', 'a', 'd', 'd', 'v', '.', 'd', 9, 0,
+ /* 3957 */ 'p', 'c', 'k', 'e', 'v', '.', 'd', 9, 0,
+ /* 3966 */ 'i', 'l', 'v', 'e', 'v', '.', 'd', 9, 0,
+ /* 3975 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0,
+ /* 3983 */ 'm', 'u', 'l', 'v', '.', 'd', 9, 0,
+ /* 3991 */ 'm', 'o', 'v', '.', 'd', 9, 0,
+ /* 3998 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 'd', 9, 0,
+ /* 4009 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 'd', 9, 0,
+ /* 4020 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 'd', 9, 0,
+ /* 4030 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 'd', 9, 0,
+ /* 4041 */ 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0,
+ /* 4050 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0,
+ /* 4058 */ 'b', 'z', '.', 'd', 9, 0,
+ /* 4064 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 'd', 9, 0,
+ /* 4074 */ 'b', 'n', 'z', '.', 'd', 9, 0,
+ /* 4081 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 'd', 9, 0,
+ /* 4091 */ 'm', 'o', 'v', 'z', '.', 'd', 9, 0,
+ /* 4099 */ 'c', 'r', 'c', '3', '2', 'd', 9, 0,
+ /* 4107 */ 'c', 'r', 'c', '3', '2', 'c', 'd', 9, 0,
+ /* 4116 */ 's', 'c', 'd', 9, 0,
+ /* 4121 */ 'd', 'a', 'd', 'd', 9, 0,
+ /* 4127 */ 'm', 'a', 'd', 'd', 9, 0,
+ /* 4133 */ 'd', 's', 'h', 'd', 9, 0,
+ /* 4139 */ 'y', 'i', 'e', 'l', 'd', 9, 0,
+ /* 4146 */ 'l', 'l', 'd', 9, 0,
+ /* 4151 */ 'a', 'n', 'd', 9, 0,
+ /* 4156 */ 'p', 'r', 'e', 'p', 'e', 'n', 'd', 9, 0,
+ /* 4165 */ 'a', 'p', 'p', 'e', 'n', 'd', 9, 0,
+ /* 4173 */ 'd', 'm', 'o', 'd', 9, 0,
+ /* 4179 */ 's', 'd', 9, 0,
+ /* 4183 */ 'l', 'b', 'e', 9, 0,
+ /* 4188 */ 's', 'b', 'e', 9, 0,
+ /* 4193 */ 's', 'c', 'e', 9, 0,
+ /* 4198 */ 'c', 'a', 'c', 'h', 'e', 'e', 9, 0,
+ /* 4206 */ 'p', 'r', 'e', 'f', 'e', 9, 0,
+ /* 4213 */ 'b', 'g', 'e', 9, 0,
+ /* 4218 */ 't', 'g', 'e', 9, 0,
+ /* 4223 */ 'c', 'a', 'c', 'h', 'e', 9, 0,
+ /* 4230 */ 'l', 'h', 'e', 9, 0,
+ /* 4235 */ 's', 'h', 'e', 9, 0,
+ /* 4240 */ 'b', 'l', 'e', 9, 0,
+ /* 4245 */ 'l', 'l', 'e', 9, 0,
+ /* 4250 */ 'l', 'w', 'l', 'e', 9, 0,
+ /* 4256 */ 's', 'w', 'l', 'e', 9, 0,
+ /* 4262 */ 'b', 'n', 'e', 9, 0,
+ /* 4267 */ 's', 'n', 'e', 9, 0,
+ /* 4272 */ 't', 'n', 'e', 9, 0,
+ /* 4277 */ 'd', 'v', 'p', 'e', 9, 0,
+ /* 4283 */ 'e', 'v', 'p', 'e', 9, 0,
+ /* 4289 */ 'l', 'w', 'r', 'e', 9, 0,
+ /* 4295 */ 's', 'w', 'r', 'e', 9, 0,
+ /* 4301 */ 'l', 'b', 'u', 'e', 9, 0,
+ /* 4307 */ 'l', 'h', 'u', 'e', 9, 0,
+ /* 4313 */ 'm', 'o', 'v', 'e', 9, 0,
+ /* 4319 */ 'l', 'w', 'e', 9, 0,
+ /* 4324 */ 's', 'w', 'e', 9, 0,
+ /* 4329 */ 'b', 'c', '1', 'f', 9, 0,
+ /* 4335 */ 'p', 'r', 'e', 'f', 9, 0,
+ /* 4341 */ 'm', 'o', 'v', 'f', 9, 0,
+ /* 4347 */ 'n', 'e', 'g', 9, 0,
+ /* 4352 */ 'a', 'd', 'd', '_', 'a', '.', 'h', 9, 0,
+ /* 4361 */ 'm', 'i', 'n', '_', 'a', '.', 'h', 9, 0,
+ /* 4370 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'h', 9, 0,
+ /* 4380 */ 'm', 'a', 'x', '_', 'a', '.', 'h', 9, 0,
+ /* 4389 */ 's', 'r', 'a', '.', 'h', 9, 0,
+ /* 4396 */ 'n', 'l', 'o', 'c', '.', 'h', 9, 0,
+ /* 4404 */ 'n', 'l', 'z', 'c', '.', 'h', 9, 0,
+ /* 4412 */ 's', 'l', 'd', '.', 'h', 9, 0,
+ /* 4419 */ 'p', 'c', 'k', 'o', 'd', '.', 'h', 9, 0,
+ /* 4428 */ 'i', 'l', 'v', 'o', 'd', '.', 'h', 9, 0,
+ /* 4437 */ 'i', 'n', 's', 'v', 'e', '.', 'h', 9, 0,
+ /* 4446 */ 'v', 's', 'h', 'f', '.', 'h', 9, 0,
+ /* 4454 */ 'b', 'n', 'e', 'g', '.', 'h', 9, 0,
+ /* 4462 */ 's', 'r', 'a', 'i', '.', 'h', 9, 0,
+ /* 4470 */ 's', 'l', 'd', 'i', '.', 'h', 9, 0,
+ /* 4478 */ 'b', 'n', 'e', 'g', 'i', '.', 'h', 9, 0,
+ /* 4487 */ 's', 'l', 'l', 'i', '.', 'h', 9, 0,
+ /* 4495 */ 's', 'r', 'l', 'i', '.', 'h', 9, 0,
+ /* 4503 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'h', 9, 0,
+ /* 4513 */ 'c', 'e', 'q', 'i', '.', 'h', 9, 0,
+ /* 4521 */ 's', 'r', 'a', 'r', 'i', '.', 'h', 9, 0,
+ /* 4530 */ 'b', 'c', 'l', 'r', 'i', '.', 'h', 9, 0,
+ /* 4539 */ 's', 'r', 'l', 'r', 'i', '.', 'h', 9, 0,
+ /* 4548 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'h', 9, 0,
+ /* 4558 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'h', 9, 0,
+ /* 4568 */ 'b', 's', 'e', 't', 'i', '.', 'h', 9, 0,
+ /* 4577 */ 's', 'u', 'b', 'v', 'i', '.', 'h', 9, 0,
+ /* 4586 */ 'a', 'd', 'd', 'v', 'i', '.', 'h', 9, 0,
+ /* 4595 */ 'f', 'i', 'l', 'l', '.', 'h', 9, 0,
+ /* 4603 */ 's', 'l', 'l', '.', 'h', 9, 0,
+ /* 4610 */ 's', 'r', 'l', '.', 'h', 9, 0,
+ /* 4617 */ 'b', 'i', 'n', 's', 'l', '.', 'h', 9, 0,
+ /* 4626 */ 'i', 'l', 'v', 'l', '.', 'h', 9, 0,
+ /* 4634 */ 'f', 'e', 'x', 'd', 'o', '.', 'h', 9, 0,
+ /* 4643 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'h', 9, 0,
+ /* 4653 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'h', 9, 0,
+ /* 4663 */ 'm', 'u', 'l', '_', 'q', '.', 'h', 9, 0,
+ /* 4672 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'h', 9, 0,
+ /* 4683 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'h', 9, 0,
+ /* 4694 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'h', 9, 0,
+ /* 4704 */ 'c', 'e', 'q', '.', 'h', 9, 0,
+ /* 4711 */ 'f', 't', 'q', '.', 'h', 9, 0,
+ /* 4718 */ 's', 'r', 'a', 'r', '.', 'h', 9, 0,
+ /* 4726 */ 'b', 'c', 'l', 'r', '.', 'h', 9, 0,
+ /* 4734 */ 's', 'r', 'l', 'r', '.', 'h', 9, 0,
+ /* 4742 */ 'b', 'i', 'n', 's', 'r', '.', 'h', 9, 0,
+ /* 4751 */ 'i', 'l', 'v', 'r', '.', 'h', 9, 0,
+ /* 4759 */ 'a', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0,
+ /* 4769 */ 'h', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0,
+ /* 4779 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'h', 9, 0,
+ /* 4790 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0,
+ /* 4800 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'h', 9, 0,
+ /* 4811 */ 'm', 'o', 'd', '_', 's', '.', 'h', 9, 0,
+ /* 4820 */ 'c', 'l', 'e', '_', 's', '.', 'h', 9, 0,
+ /* 4829 */ 'a', 'v', 'e', '_', 's', '.', 'h', 9, 0,
+ /* 4838 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'h', 9, 0,
+ /* 4848 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'h', 9, 0,
+ /* 4858 */ 'c', 'l', 't', 'i', '_', 's', '.', 'h', 9, 0,
+ /* 4868 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'h', 9, 0,
+ /* 4878 */ 'm', 'i', 'n', '_', 's', '.', 'h', 9, 0,
+ /* 4887 */ 'd', 'o', 't', 'p', '_', 's', '.', 'h', 9, 0,
+ /* 4897 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'h', 9, 0,
+ /* 4907 */ 'e', 'x', 't', 'r', '_', 's', '.', 'h', 9, 0,
+ /* 4917 */ 's', 'u', 'b', 's', '_', 's', '.', 'h', 9, 0,
+ /* 4927 */ 'a', 'd', 'd', 's', '_', 's', '.', 'h', 9, 0,
+ /* 4937 */ 's', 'a', 't', '_', 's', '.', 'h', 9, 0,
+ /* 4946 */ 'c', 'l', 't', '_', 's', '.', 'h', 9, 0,
+ /* 4955 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'h', 9, 0,
+ /* 4967 */ 'd', 'i', 'v', '_', 's', '.', 'h', 9, 0,
+ /* 4976 */ 'e', 'x', 't', 'r', 'v', '_', 's', '.', 'h', 9, 0,
+ /* 4987 */ 'm', 'a', 'x', '_', 's', '.', 'h', 9, 0,
+ /* 4996 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'h', 9, 0,
+ /* 5006 */ 's', 'p', 'l', 'a', 't', '.', 'h', 9, 0,
+ /* 5015 */ 'b', 's', 'e', 't', '.', 'h', 9, 0,
+ /* 5023 */ 'p', 'c', 'n', 't', '.', 'h', 9, 0,
+ /* 5031 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'h', 9, 0,
+ /* 5041 */ 's', 't', '.', 'h', 9, 0,
+ /* 5047 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0,
+ /* 5057 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0,
+ /* 5067 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'h', 9, 0,
+ /* 5078 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0,
+ /* 5088 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'h', 9, 0,
+ /* 5099 */ 'm', 'o', 'd', '_', 'u', '.', 'h', 9, 0,
+ /* 5108 */ 'c', 'l', 'e', '_', 'u', '.', 'h', 9, 0,
+ /* 5117 */ 'a', 'v', 'e', '_', 'u', '.', 'h', 9, 0,
+ /* 5126 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'h', 9, 0,
+ /* 5136 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'h', 9, 0,
+ /* 5146 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'h', 9, 0,
+ /* 5156 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'h', 9, 0,
+ /* 5166 */ 'm', 'i', 'n', '_', 'u', '.', 'h', 9, 0,
+ /* 5175 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'h', 9, 0,
+ /* 5185 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'h', 9, 0,
+ /* 5195 */ 's', 'u', 'b', 's', '_', 'u', '.', 'h', 9, 0,
+ /* 5205 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'h', 9, 0,
+ /* 5215 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'h', 9, 0,
+ /* 5227 */ 's', 'a', 't', '_', 'u', '.', 'h', 9, 0,
+ /* 5236 */ 'c', 'l', 't', '_', 'u', '.', 'h', 9, 0,
+ /* 5245 */ 'd', 'i', 'v', '_', 'u', '.', 'h', 9, 0,
+ /* 5254 */ 'm', 'a', 'x', '_', 'u', '.', 'h', 9, 0,
+ /* 5263 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'h', 9, 0,
+ /* 5273 */ 'm', 's', 'u', 'b', 'v', '.', 'h', 9, 0,
+ /* 5282 */ 'm', 'a', 'd', 'd', 'v', '.', 'h', 9, 0,
+ /* 5291 */ 'p', 'c', 'k', 'e', 'v', '.', 'h', 9, 0,
+ /* 5300 */ 'i', 'l', 'v', 'e', 'v', '.', 'h', 9, 0,
+ /* 5309 */ 'm', 'u', 'l', 'v', '.', 'h', 9, 0,
+ /* 5317 */ 'b', 'z', '.', 'h', 9, 0,
+ /* 5323 */ 'b', 'n', 'z', '.', 'h', 9, 0,
+ /* 5330 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0,
+ /* 5338 */ 'd', 's', 'b', 'h', 9, 0,
+ /* 5344 */ 'w', 's', 'b', 'h', 9, 0,
+ /* 5350 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0,
+ /* 5359 */ 's', 'e', 'h', 9, 0,
+ /* 5364 */ 'u', 'l', 'h', 9, 0,
+ /* 5369 */ 's', 'h', 'r', 'a', '.', 'p', 'h', 9, 0,
+ /* 5378 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'q', 'b', '.', 'p', 'h', 9, 0,
+ /* 5392 */ 'p', 'r', 'e', 'c', 'r', '.', 'q', 'b', '.', 'p', 'h', 9, 0,
+ /* 5405 */ 'p', 'r', 'e', 'c', 'r', 'q', 'u', '_', 's', '.', 'q', 'b', '.', 'p', 'h', 9, 0,
+ /* 5422 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 'p', 'h', 9, 0,
+ /* 5433 */ 's', 'u', 'b', 'q', 'h', '.', 'p', 'h', 9, 0,
+ /* 5443 */ 'a', 'd', 'd', 'q', 'h', '.', 'p', 'h', 9, 0,
+ /* 5453 */ 'p', 'i', 'c', 'k', '.', 'p', 'h', 9, 0,
+ /* 5462 */ 's', 'h', 'l', 'l', '.', 'p', 'h', 9, 0,
+ /* 5471 */ 'r', 'e', 'p', 'l', '.', 'p', 'h', 9, 0,
+ /* 5480 */ 's', 'h', 'r', 'l', '.', 'p', 'h', 9, 0,
+ /* 5489 */ 'p', 'a', 'c', 'k', 'r', 'l', '.', 'p', 'h', 9, 0,
+ /* 5500 */ 'm', 'u', 'l', '.', 'p', 'h', 9, 0,
+ /* 5508 */ 's', 'u', 'b', 'q', '.', 'p', 'h', 9, 0,
+ /* 5517 */ 'a', 'd', 'd', 'q', '.', 'p', 'h', 9, 0,
+ /* 5526 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 'p', 'h', 9, 0,
+ /* 5537 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'p', 'h', 9, 0,
+ /* 5548 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0,
+ /* 5560 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'p', 'h', 9, 0,
+ /* 5572 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'p', 'h', 9, 0,
+ /* 5584 */ 's', 'h', 'l', 'l', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5595 */ 'm', 'u', 'l', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5605 */ 's', 'u', 'b', 'q', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5616 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5627 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5638 */ 'a', 'b', 's', 'q', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5649 */ 's', 'u', 'b', 'u', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5660 */ 'a', 'd', 'd', 'u', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5671 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'p', 'h', 9, 0,
+ /* 5683 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'p', 'h', 9, 0,
+ /* 5695 */ 'c', 'm', 'p', '.', 'l', 't', '.', 'p', 'h', 9, 0,
+ /* 5706 */ 's', 'u', 'b', 'u', '.', 'p', 'h', 9, 0,
+ /* 5715 */ 'a', 'd', 'd', 'u', '.', 'p', 'h', 9, 0,
+ /* 5724 */ 's', 'h', 'r', 'a', 'v', '.', 'p', 'h', 9, 0,
+ /* 5734 */ 's', 'h', 'l', 'l', 'v', '.', 'p', 'h', 9, 0,
+ /* 5744 */ 'r', 'e', 'p', 'l', 'v', '.', 'p', 'h', 9, 0,
+ /* 5754 */ 's', 'h', 'r', 'l', 'v', '.', 'p', 'h', 9, 0,
+ /* 5764 */ 'd', 'p', 'a', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5774 */ 'd', 'p', 'a', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5789 */ 'd', 'p', 's', 'q', 'x', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5804 */ 'm', 'u', 'l', 's', 'a', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5816 */ 'd', 'p', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5829 */ 'm', 'u', 'l', 's', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5844 */ 'd', 'p', 's', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5857 */ 'd', 'p', 'a', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5871 */ 'd', 'p', 's', 'q', 'x', '_', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5885 */ 'd', 'p', 's', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5895 */ 'd', 'p', 'a', 'x', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5906 */ 'd', 'p', 's', 'x', '.', 'w', '.', 'p', 'h', 9, 0,
+ /* 5917 */ 'u', 's', 'h', 9, 0,
+ /* 5922 */ 'd', 'm', 'u', 'h', 9, 0,
+ /* 5928 */ 's', 'y', 'n', 'c', 'i', 9, 0,
+ /* 5935 */ 'd', 'a', 'd', 'd', 'i', 9, 0,
+ /* 5942 */ 'a', 'n', 'd', 'i', 9, 0,
+ /* 5948 */ 't', 'g', 'e', 'i', 9, 0,
+ /* 5954 */ 's', 'n', 'e', 'i', 9, 0,
+ /* 5960 */ 't', 'n', 'e', 'i', 9, 0,
+ /* 5966 */ 'd', 'a', 'h', 'i', 9, 0,
+ /* 5972 */ 'm', 'f', 'h', 'i', 9, 0,
+ /* 5978 */ 'm', 't', 'h', 'i', 9, 0,
+ /* 5984 */ '.', 'a', 'l', 'i', 'g', 'n', 32, '2', 10, 9, 'l', 'i', 9, 0,
+ /* 5998 */ 'd', 'l', 'i', 9, 0,
+ /* 6003 */ 'c', 'm', 'p', 'i', 9, 0,
+ /* 6009 */ 's', 'e', 'q', 'i', 9, 0,
+ /* 6015 */ 't', 'e', 'q', 'i', 9, 0,
+ /* 6021 */ 'x', 'o', 'r', 'i', 9, 0,
+ /* 6027 */ 'd', 'a', 't', 'i', 9, 0,
+ /* 6033 */ 's', 'l', 't', 'i', 9, 0,
+ /* 6039 */ 't', 'l', 't', 'i', 9, 0,
+ /* 6045 */ 'd', 'a', 'u', 'i', 9, 0,
+ /* 6051 */ 'l', 'u', 'i', 9, 0,
+ /* 6056 */ 'g', 'i', 'n', 'v', 'i', 9, 0,
+ /* 6063 */ 'j', 9, 0,
+ /* 6066 */ 'b', 'r', 'e', 'a', 'k', 9, 0,
+ /* 6073 */ 'f', 'o', 'r', 'k', 9, 0,
+ /* 6079 */ 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0,
+ /* 6088 */ 'c', 'v', 't', '.', 's', '.', 'l', 9, 0,
+ /* 6097 */ 'b', 'a', 'l', 9, 0,
+ /* 6102 */ 'j', 'a', 'l', 9, 0,
+ /* 6107 */ 'b', 'g', 'e', 'z', 'a', 'l', 9, 0,
+ /* 6115 */ 'b', 'l', 't', 'z', 'a', 'l', 9, 0,
+ /* 6123 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 6135 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 6147 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 6163 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 6178 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'l', 9, 0,
+ /* 6194 */ 'l', 'd', 'l', 9, 0,
+ /* 6199 */ 's', 'd', 'l', 9, 0,
+ /* 6204 */ 'b', 'g', 'e', 'l', 9, 0,
+ /* 6210 */ 'b', 'l', 'e', 'l', 9, 0,
+ /* 6216 */ 'b', 'n', 'e', 'l', 9, 0,
+ /* 6222 */ 'b', 'c', '1', 'f', 'l', 9, 0,
+ /* 6229 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'l', 9, 0,
+ /* 6243 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'l', 9, 0,
+ /* 6257 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0,
+ /* 6270 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'l', 9, 0,
+ /* 6285 */ 'h', 'y', 'p', 'c', 'a', 'l', 'l', 9, 0,
+ /* 6294 */ 's', 'y', 's', 'c', 'a', 'l', 'l', 9, 0,
+ /* 6303 */ 'b', 'g', 'e', 'z', 'a', 'l', 'l', 9, 0,
+ /* 6312 */ 'b', 'l', 't', 'z', 'a', 'l', 'l', 9, 0,
+ /* 6321 */ 'd', 's', 'l', 'l', 9, 0,
+ /* 6327 */ 'd', 'r', 'o', 'l', 9, 0,
+ /* 6333 */ 'b', 'e', 'q', 'l', 9, 0,
+ /* 6339 */ 'd', 's', 'r', 'l', 9, 0,
+ /* 6345 */ 'b', 'c', '1', 't', 'l', 9, 0,
+ /* 6352 */ 'b', 'g', 't', 'l', 9, 0,
+ /* 6358 */ 'b', 'l', 't', 'l', 9, 0,
+ /* 6364 */ 'b', 'g', 'e', 'u', 'l', 9, 0,
+ /* 6371 */ 'b', 'l', 'e', 'u', 'l', 9, 0,
+ /* 6378 */ 'd', 'm', 'u', 'l', 9, 0,
+ /* 6384 */ 'b', 'g', 't', 'u', 'l', 9, 0,
+ /* 6391 */ 'b', 'l', 't', 'u', 'l', 9, 0,
+ /* 6398 */ 'l', 'w', 'l', 9, 0,
+ /* 6403 */ 's', 'w', 'l', 9, 0,
+ /* 6408 */ 'b', 'g', 'e', 'z', 'l', 9, 0,
+ /* 6415 */ 'b', 'l', 'e', 'z', 'l', 9, 0,
+ /* 6422 */ 'b', 'g', 't', 'z', 'l', 9, 0,
+ /* 6429 */ 'b', 'l', 't', 'z', 'l', 9, 0,
+ /* 6436 */ 'd', 'r', 'e', 'm', 9, 0,
+ /* 6442 */ 'd', 'i', 'n', 's', 'm', 9, 0,
+ /* 6449 */ 'd', 'e', 'x', 't', 'm', 9, 0,
+ /* 6456 */ 'l', 'w', 'm', 9, 0,
+ /* 6461 */ 's', 'w', 'm', 9, 0,
+ /* 6466 */ 'b', 'a', 'l', 'i', 'g', 'n', 9, 0,
+ /* 6474 */ 'd', 'a', 'l', 'i', 'g', 'n', 9, 0,
+ /* 6482 */ 'm', 'o', 'v', 'n', 9, 0,
+ /* 6488 */ 'd', 'c', 'l', 'o', 9, 0,
+ /* 6494 */ 'm', 'f', 'l', 'o', 9, 0,
+ /* 6500 */ 's', 'h', 'i', 'l', 'o', 9, 0,
+ /* 6507 */ 'm', 't', 'l', 'o', 9, 0,
+ /* 6513 */ 'd', 'm', 'u', 'l', 'o', 9, 0,
+ /* 6520 */ 'd', 'b', 'i', 't', 's', 'w', 'a', 'p', 9, 0,
+ /* 6530 */ 's', 'd', 'b', 'b', 'p', 9, 0,
+ /* 6537 */ 'e', 'x', 't', 'p', 'd', 'p', 9, 0,
+ /* 6545 */ 'm', 'o', 'v', 'e', 'p', 9, 0,
+ /* 6552 */ 'm', 't', 'h', 'l', 'i', 'p', 9, 0,
+ /* 6560 */ 'c', 'm', 'p', 9, 0,
+ /* 6565 */ 'd', 'p', 'o', 'p', 9, 0,
+ /* 6571 */ 'a', 'd', 'd', 'i', 'u', 'r', '1', 's', 'p', 9, 0,
+ /* 6582 */ 'l', 'o', 'a', 'd', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0,
+ /* 6598 */ 's', 't', 'o', 'r', 'e', '_', 'c', 'c', 'o', 'n', 'd', '_', 'd', 's', 'p', 9, 0,
+ /* 6615 */ 'r', 'd', 'd', 's', 'p', 9, 0,
+ /* 6622 */ 'w', 'r', 'd', 's', 'p', 9, 0,
+ /* 6629 */ 'j', 'r', 'c', 'a', 'd', 'd', 'i', 'u', 's', 'p', 9, 0,
+ /* 6641 */ 'j', 'r', 'a', 'd', 'd', 'i', 'u', 's', 'p', 9, 0,
+ /* 6652 */ 'e', 'x', 't', 'p', 9, 0,
+ /* 6658 */ 'd', 'v', 'p', 9, 0,
+ /* 6663 */ 'e', 'v', 'p', 9, 0,
+ /* 6668 */ 'l', 'w', 'p', 9, 0,
+ /* 6673 */ 's', 'w', 'p', 9, 0,
+ /* 6678 */ 'b', 'e', 'q', 9, 0,
+ /* 6683 */ 's', 'e', 'q', 9, 0,
+ /* 6688 */ 't', 'e', 'q', 9, 0,
+ /* 6693 */ 'd', 'p', 'a', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6705 */ 'd', 'p', 's', 'u', '.', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6717 */ 'm', 'u', 'l', 'e', 'u', '_', 's', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6733 */ 'p', 'r', 'e', 'c', 'e', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6748 */ 'p', 'r', 'e', 'c', 'e', 'q', 'u', '.', 'p', 'h', '.', 'q', 'b', 'r', 9, 0,
+ /* 6764 */ 'l', 'd', 'r', 9, 0,
+ /* 6769 */ 's', 'd', 'r', 9, 0,
+ /* 6774 */ 'm', 'a', 'q', '_', 's', 'a', '.', 'w', '.', 'p', 'h', 'r', 9, 0,
+ /* 6788 */ 'p', 'r', 'e', 'c', 'e', 'q', '.', 'w', '.', 'p', 'h', 'r', 9, 0,
+ /* 6802 */ 'm', 'a', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0,
+ /* 6815 */ 'm', 'u', 'l', 'e', 'q', '_', 's', '.', 'w', '.', 'p', 'h', 'r', 9, 0,
+ /* 6830 */ 'j', 'r', 9, 0,
+ /* 6834 */ 'j', 'a', 'l', 'r', 9, 0,
+ /* 6840 */ 'n', 'o', 'r', 9, 0,
+ /* 6845 */ 'd', 'r', 'o', 'r', 9, 0,
+ /* 6851 */ 'x', 'o', 'r', 9, 0,
+ /* 6856 */ 'r', 'd', 'p', 'g', 'p', 'r', 9, 0,
+ /* 6864 */ 'w', 'r', 'p', 'g', 'p', 'r', 9, 0,
+ /* 6872 */ 'm', 'f', 't', 'r', 9, 0,
+ /* 6878 */ 'd', 'r', 'o', 't', 'r', 9, 0,
+ /* 6885 */ 'm', 't', 't', 'r', 9, 0,
+ /* 6891 */ 'r', 'd', 'h', 'w', 'r', 9, 0,
+ /* 6898 */ 'l', 'w', 'r', 9, 0,
+ /* 6903 */ 's', 'w', 'r', 9, 0,
+ /* 6908 */ 'm', 'i', 'n', 'a', '.', 's', 9, 0,
+ /* 6916 */ 'm', 'a', 'x', 'a', '.', 's', 9, 0,
+ /* 6924 */ 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0,
+ /* 6933 */ 'c', 'v', 't', '.', 'd', '.', 's', 9, 0,
+ /* 6942 */ 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0,
+ /* 6951 */ 'c', '.', 'n', 'g', 'e', '.', 's', 9, 0,
+ /* 6960 */ 'c', '.', 'l', 'e', '.', 's', 9, 0,
+ /* 6968 */ 'c', 'm', 'p', '.', 'l', 'e', '.', 's', 9, 0,
+ /* 6978 */ 'c', '.', 'n', 'g', 'l', 'e', '.', 's', 9, 0,
+ /* 6988 */ 'c', '.', 'o', 'l', 'e', '.', 's', 9, 0,
+ /* 6997 */ 'c', 'm', 'p', '.', 's', 'l', 'e', '.', 's', 9, 0,
+ /* 7008 */ 'c', '.', 'u', 'l', 'e', '.', 's', 9, 0,
+ /* 7017 */ 'c', 'm', 'p', '.', 'u', 'l', 'e', '.', 's', 9, 0,
+ /* 7028 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 'e', '.', 's', 9, 0,
+ /* 7040 */ 'c', '.', 'f', '.', 's', 9, 0,
+ /* 7047 */ 'c', 'm', 'p', '.', 'a', 'f', '.', 's', 9, 0,
+ /* 7057 */ 'c', 'm', 'p', '.', 's', 'a', 'f', '.', 's', 9, 0,
+ /* 7068 */ 'm', 's', 'u', 'b', 'f', '.', 's', 9, 0,
+ /* 7077 */ 'm', 'a', 'd', 'd', 'f', '.', 's', 9, 0,
+ /* 7086 */ 'c', '.', 's', 'f', '.', 's', 9, 0,
+ /* 7094 */ 'm', 'o', 'v', 'f', '.', 's', 9, 0,
+ /* 7102 */ 'n', 'e', 'g', '.', 's', 9, 0,
+ /* 7109 */ 'l', 'i', '.', 's', 9, 0,
+ /* 7115 */ 't', 'r', 'u', 'n', 'c', '.', 'l', '.', 's', 9, 0,
+ /* 7126 */ 'r', 'o', 'u', 'n', 'd', '.', 'l', '.', 's', 9, 0,
+ /* 7137 */ 'c', 'e', 'i', 'l', '.', 'l', '.', 's', 9, 0,
+ /* 7147 */ 'f', 'l', 'o', 'o', 'r', '.', 'l', '.', 's', 9, 0,
+ /* 7158 */ 'c', 'v', 't', '.', 'l', '.', 's', 9, 0,
+ /* 7167 */ 's', 'e', 'l', '.', 's', 9, 0,
+ /* 7174 */ 'c', '.', 'n', 'g', 'l', '.', 's', 9, 0,
+ /* 7183 */ 'm', 'u', 'l', '.', 's', 9, 0,
+ /* 7190 */ 'm', 'i', 'n', '.', 's', 9, 0,
+ /* 7197 */ 'c', '.', 'u', 'n', '.', 's', 9, 0,
+ /* 7205 */ 'c', 'm', 'p', '.', 'u', 'n', '.', 's', 9, 0,
+ /* 7215 */ 'c', 'm', 'p', '.', 's', 'u', 'n', '.', 's', 9, 0,
+ /* 7226 */ 'm', 'o', 'v', 'n', '.', 's', 9, 0,
+ /* 7234 */ 'r', 'e', 'c', 'i', 'p', '.', 's', 9, 0,
+ /* 7243 */ 'c', '.', 'e', 'q', '.', 's', 9, 0,
+ /* 7251 */ 'c', 'm', 'p', '.', 'e', 'q', '.', 's', 9, 0,
+ /* 7261 */ 'c', '.', 's', 'e', 'q', '.', 's', 9, 0,
+ /* 7270 */ 'c', 'm', 'p', '.', 's', 'e', 'q', '.', 's', 9, 0,
+ /* 7281 */ 'c', '.', 'u', 'e', 'q', '.', 's', 9, 0,
+ /* 7290 */ 'c', 'm', 'p', '.', 'u', 'e', 'q', '.', 's', 9, 0,
+ /* 7301 */ 'c', 'm', 'p', '.', 's', 'u', 'e', 'q', '.', 's', 9, 0,
+ /* 7313 */ 'a', 'b', 's', '.', 's', 9, 0,
+ /* 7320 */ 'c', 'l', 'a', 's', 's', '.', 's', 9, 0,
+ /* 7329 */ 'c', '.', 'n', 'g', 't', '.', 's', 9, 0,
+ /* 7338 */ 'c', '.', 'l', 't', '.', 's', 9, 0,
+ /* 7346 */ 'c', 'm', 'p', '.', 'l', 't', '.', 's', 9, 0,
+ /* 7356 */ 'c', '.', 'o', 'l', 't', '.', 's', 9, 0,
+ /* 7365 */ 'c', 'm', 'p', '.', 's', 'l', 't', '.', 's', 9, 0,
+ /* 7376 */ 'c', '.', 'u', 'l', 't', '.', 's', 9, 0,
+ /* 7385 */ 'c', 'm', 'p', '.', 'u', 'l', 't', '.', 's', 9, 0,
+ /* 7396 */ 'c', 'm', 'p', '.', 's', 'u', 'l', 't', '.', 's', 9, 0,
+ /* 7408 */ 'r', 'i', 'n', 't', '.', 's', 9, 0,
+ /* 7416 */ 'r', 's', 'q', 'r', 't', '.', 's', 9, 0,
+ /* 7425 */ 'm', 'o', 'v', 't', '.', 's', 9, 0,
+ /* 7433 */ 'd', 'i', 'v', '.', 's', 9, 0,
+ /* 7440 */ 'm', 'o', 'v', '.', 's', 9, 0,
+ /* 7447 */ 't', 'r', 'u', 'n', 'c', '.', 'w', '.', 's', 9, 0,
+ /* 7458 */ 'r', 'o', 'u', 'n', 'd', '.', 'w', '.', 's', 9, 0,
+ /* 7469 */ 'c', 'e', 'i', 'l', '.', 'w', '.', 's', 9, 0,
+ /* 7479 */ 'f', 'l', 'o', 'o', 'r', '.', 'w', '.', 's', 9, 0,
+ /* 7490 */ 'c', 'v', 't', '.', 'w', '.', 's', 9, 0,
+ /* 7499 */ 'm', 'a', 'x', '.', 's', 9, 0,
+ /* 7506 */ 's', 'e', 'l', 'n', 'e', 'z', '.', 's', 9, 0,
+ /* 7516 */ 's', 'e', 'l', 'e', 'q', 'z', '.', 's', 9, 0,
+ /* 7526 */ 'm', 'o', 'v', 'z', '.', 's', 9, 0,
+ /* 7534 */ 'a', 'b', 's', 9, 0,
+ /* 7539 */ 'j', 'a', 'l', 's', 9, 0,
+ /* 7545 */ 'b', 'g', 'e', 'z', 'a', 'l', 's', 9, 0,
+ /* 7554 */ 'b', 'l', 't', 'z', 'a', 'l', 's', 9, 0,
+ /* 7563 */ 'c', 'i', 'n', 's', 9, 0,
+ /* 7569 */ 'd', 'i', 'n', 's', 9, 0,
+ /* 7575 */ 'j', 'a', 'l', 'r', 's', 9, 0,
+ /* 7582 */ 'e', 'x', 't', 's', 9, 0,
+ /* 7588 */ 'l', 'w', 'x', 's', 9, 0,
+ /* 7594 */ 'b', 'c', '1', 't', 9, 0,
+ /* 7600 */ 'b', 'g', 't', 9, 0,
+ /* 7605 */ 'w', 'a', 'i', 't', 9, 0,
+ /* 7611 */ 'b', 'l', 't', 9, 0,
+ /* 7616 */ 's', 'l', 't', 9, 0,
+ /* 7621 */ 't', 'l', 't', 9, 0,
+ /* 7626 */ 'd', 'm', 'u', 'l', 't', 9, 0,
+ /* 7633 */ 'd', 'm', 't', 9, 0,
+ /* 7638 */ 'e', 'm', 't', 9, 0,
+ /* 7643 */ 'n', 'o', 't', 9, 0,
+ /* 7648 */ 'g', 'i', 'n', 'v', 't', 9, 0,
+ /* 7655 */ 'm', 'o', 'v', 't', 9, 0,
+ /* 7661 */ 'd', 'e', 'x', 't', 9, 0,
+ /* 7667 */ 'l', 'b', 'u', 9, 0,
+ /* 7672 */ 'd', 's', 'u', 'b', 'u', 9, 0,
+ /* 7679 */ 'm', 's', 'u', 'b', 'u', 9, 0,
+ /* 7686 */ 'b', 'a', 'd', 'd', 'u', 9, 0,
+ /* 7693 */ 'd', 'a', 'd', 'd', 'u', 9, 0,
+ /* 7700 */ 'm', 'a', 'd', 'd', 'u', 9, 0,
+ /* 7707 */ 'd', 'm', 'o', 'd', 'u', 9, 0,
+ /* 7714 */ 'b', 'g', 'e', 'u', 9, 0,
+ /* 7720 */ 't', 'g', 'e', 'u', 9, 0,
+ /* 7726 */ 'b', 'l', 'e', 'u', 9, 0,
+ /* 7732 */ 'u', 'l', 'h', 'u', 9, 0,
+ /* 7738 */ 'd', 'm', 'u', 'h', 'u', 9, 0,
+ /* 7745 */ 'd', 'a', 'd', 'd', 'i', 'u', 9, 0,
+ /* 7753 */ 't', 'g', 'e', 'i', 'u', 9, 0,
+ /* 7760 */ 's', 'l', 't', 'i', 'u', 9, 0,
+ /* 7767 */ 't', 'l', 't', 'i', 'u', 9, 0,
+ /* 7774 */ 'v', '3', 'm', 'u', 'l', 'u', 9, 0,
+ /* 7782 */ 'd', 'm', 'u', 'l', 'u', 9, 0,
+ /* 7789 */ 'v', 'm', 'u', 'l', 'u', 9, 0,
+ /* 7796 */ 'd', 'r', 'e', 'm', 'u', 9, 0,
+ /* 7803 */ 'd', 'm', 'u', 'l', 'o', 'u', 9, 0,
+ /* 7811 */ 'd', 'i', 'n', 's', 'u', 9, 0,
+ /* 7818 */ 'b', 'g', 't', 'u', 9, 0,
+ /* 7824 */ 'b', 'l', 't', 'u', 9, 0,
+ /* 7830 */ 's', 'l', 't', 'u', 9, 0,
+ /* 7836 */ 't', 'l', 't', 'u', 9, 0,
+ /* 7842 */ 'd', 'm', 'u', 'l', 't', 'u', 9, 0,
+ /* 7850 */ 'd', 'e', 'x', 't', 'u', 9, 0,
+ /* 7857 */ 'd', 'd', 'i', 'v', 'u', 9, 0,
+ /* 7864 */ 'l', 'w', 'u', 9, 0,
+ /* 7869 */ 'a', 'n', 'd', '.', 'v', 9, 0,
+ /* 7876 */ 'm', 'o', 'v', 'e', '.', 'v', 9, 0,
+ /* 7884 */ 'b', 's', 'e', 'l', '.', 'v', 9, 0,
+ /* 7892 */ 'n', 'o', 'r', '.', 'v', 9, 0,
+ /* 7899 */ 'x', 'o', 'r', '.', 'v', 9, 0,
+ /* 7906 */ 'b', 'z', '.', 'v', 9, 0,
+ /* 7912 */ 'b', 'm', 'z', '.', 'v', 9, 0,
+ /* 7919 */ 'b', 'n', 'z', '.', 'v', 9, 0,
+ /* 7926 */ 'b', 'm', 'n', 'z', '.', 'v', 9, 0,
+ /* 7934 */ 'd', 's', 'r', 'a', 'v', 9, 0,
+ /* 7941 */ 'b', 'i', 't', 'r', 'e', 'v', 9, 0,
+ /* 7949 */ 'd', 'd', 'i', 'v', 9, 0,
+ /* 7955 */ 'd', 's', 'l', 'l', 'v', 9, 0,
+ /* 7962 */ 'd', 's', 'r', 'l', 'v', 9, 0,
+ /* 7969 */ 's', 'h', 'i', 'l', 'o', 'v', 9, 0,
+ /* 7977 */ 'e', 'x', 't', 'p', 'd', 'p', 'v', 9, 0,
+ /* 7986 */ 'e', 'x', 't', 'p', 'v', 9, 0,
+ /* 7993 */ 'd', 'r', 'o', 't', 'r', 'v', 9, 0,
+ /* 8001 */ 'i', 'n', 's', 'v', 9, 0,
+ /* 8007 */ 'f', 'l', 'o', 'g', '2', '.', 'w', 9, 0,
+ /* 8016 */ 'f', 'e', 'x', 'p', '2', '.', 'w', 9, 0,
+ /* 8025 */ 'a', 'd', 'd', '_', 'a', '.', 'w', 9, 0,
+ /* 8034 */ 'f', 'm', 'i', 'n', '_', 'a', '.', 'w', 9, 0,
+ /* 8044 */ 'a', 'd', 'd', 's', '_', 'a', '.', 'w', 9, 0,
+ /* 8054 */ 'f', 'm', 'a', 'x', '_', 'a', '.', 'w', 9, 0,
+ /* 8064 */ 's', 'r', 'a', '.', 'w', 9, 0,
+ /* 8071 */ 'f', 's', 'u', 'b', '.', 'w', 9, 0,
+ /* 8079 */ 'f', 'm', 's', 'u', 'b', '.', 'w', 9, 0,
+ /* 8088 */ 'n', 'l', 'o', 'c', '.', 'w', 9, 0,
+ /* 8096 */ 'n', 'l', 'z', 'c', '.', 'w', 9, 0,
+ /* 8104 */ 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0,
+ /* 8113 */ 'f', 'a', 'd', 'd', '.', 'w', 9, 0,
+ /* 8121 */ 'f', 'm', 'a', 'd', 'd', '.', 'w', 9, 0,
+ /* 8130 */ 's', 'l', 'd', '.', 'w', 9, 0,
+ /* 8137 */ 'p', 'c', 'k', 'o', 'd', '.', 'w', 9, 0,
+ /* 8146 */ 'i', 'l', 'v', 'o', 'd', '.', 'w', 9, 0,
+ /* 8155 */ 'f', 'c', 'l', 'e', '.', 'w', 9, 0,
+ /* 8163 */ 'f', 's', 'l', 'e', '.', 'w', 9, 0,
+ /* 8171 */ 'f', 'c', 'u', 'l', 'e', '.', 'w', 9, 0,
+ /* 8180 */ 'f', 's', 'u', 'l', 'e', '.', 'w', 9, 0,
+ /* 8189 */ 'f', 'c', 'n', 'e', '.', 'w', 9, 0,
+ /* 8197 */ 'f', 's', 'n', 'e', '.', 'w', 9, 0,
+ /* 8205 */ 'f', 'c', 'u', 'n', 'e', '.', 'w', 9, 0,
+ /* 8214 */ 'f', 's', 'u', 'n', 'e', '.', 'w', 9, 0,
+ /* 8223 */ 'i', 'n', 's', 'v', 'e', '.', 'w', 9, 0,
+ /* 8232 */ 'f', 'c', 'a', 'f', '.', 'w', 9, 0,
+ /* 8240 */ 'f', 's', 'a', 'f', '.', 'w', 9, 0,
+ /* 8248 */ 'v', 's', 'h', 'f', '.', 'w', 9, 0,
+ /* 8256 */ 'b', 'n', 'e', 'g', '.', 'w', 9, 0,
+ /* 8264 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '.', 'p', 'h', '.', 'w', 9, 0,
+ /* 8280 */ 'p', 'r', 'e', 'c', 'r', 'q', '.', 'p', 'h', '.', 'w', 9, 0,
+ /* 8293 */ 'p', 'r', 'e', 'c', 'r', '_', 's', 'r', 'a', '_', 'r', '.', 'p', 'h', '.', 'w', 9, 0,
+ /* 8311 */ 'p', 'r', 'e', 'c', 'r', 'q', '_', 'r', 's', '.', 'p', 'h', '.', 'w', 9, 0,
+ /* 8327 */ 's', 'u', 'b', 'q', 'h', '.', 'w', 9, 0,
+ /* 8336 */ 'a', 'd', 'd', 'q', 'h', '.', 'w', 9, 0,
+ /* 8345 */ 's', 'r', 'a', 'i', '.', 'w', 9, 0,
+ /* 8353 */ 's', 'l', 'd', 'i', '.', 'w', 9, 0,
+ /* 8361 */ 'b', 'n', 'e', 'g', 'i', '.', 'w', 9, 0,
+ /* 8370 */ 's', 'l', 'l', 'i', '.', 'w', 9, 0,
+ /* 8378 */ 's', 'r', 'l', 'i', '.', 'w', 9, 0,
+ /* 8386 */ 'b', 'i', 'n', 's', 'l', 'i', '.', 'w', 9, 0,
+ /* 8396 */ 'c', 'e', 'q', 'i', '.', 'w', 9, 0,
+ /* 8404 */ 's', 'r', 'a', 'r', 'i', '.', 'w', 9, 0,
+ /* 8413 */ 'b', 'c', 'l', 'r', 'i', '.', 'w', 9, 0,
+ /* 8422 */ 's', 'r', 'l', 'r', 'i', '.', 'w', 9, 0,
+ /* 8431 */ 'b', 'i', 'n', 's', 'r', 'i', '.', 'w', 9, 0,
+ /* 8441 */ 's', 'p', 'l', 'a', 't', 'i', '.', 'w', 9, 0,
+ /* 8451 */ 'b', 's', 'e', 't', 'i', '.', 'w', 9, 0,
+ /* 8460 */ 's', 'u', 'b', 'v', 'i', '.', 'w', 9, 0,
+ /* 8469 */ 'a', 'd', 'd', 'v', 'i', '.', 'w', 9, 0,
+ /* 8478 */ 'd', 'p', 'a', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0,
+ /* 8491 */ 'd', 'p', 's', 'q', '_', 's', 'a', '.', 'l', '.', 'w', 9, 0,
+ /* 8504 */ 'f', 'i', 'l', 'l', '.', 'w', 9, 0,
+ /* 8512 */ 's', 'l', 'l', '.', 'w', 9, 0,
+ /* 8519 */ 'f', 'e', 'x', 'u', 'p', 'l', '.', 'w', 9, 0,
+ /* 8529 */ 'f', 'f', 'q', 'l', '.', 'w', 9, 0,
+ /* 8537 */ 's', 'r', 'l', '.', 'w', 9, 0,
+ /* 8544 */ 'b', 'i', 'n', 's', 'l', '.', 'w', 9, 0,
+ /* 8553 */ 'f', 'm', 'u', 'l', '.', 'w', 9, 0,
+ /* 8561 */ 'i', 'l', 'v', 'l', '.', 'w', 9, 0,
+ /* 8569 */ 'f', 'm', 'i', 'n', '.', 'w', 9, 0,
+ /* 8577 */ 'f', 'c', 'u', 'n', '.', 'w', 9, 0,
+ /* 8585 */ 'f', 's', 'u', 'n', '.', 'w', 9, 0,
+ /* 8593 */ 'f', 'e', 'x', 'd', 'o', '.', 'w', 9, 0,
+ /* 8602 */ 'f', 'r', 'c', 'p', '.', 'w', 9, 0,
+ /* 8610 */ 'm', 's', 'u', 'b', '_', 'q', '.', 'w', 9, 0,
+ /* 8620 */ 'm', 'a', 'd', 'd', '_', 'q', '.', 'w', 9, 0,
+ /* 8630 */ 'm', 'u', 'l', '_', 'q', '.', 'w', 9, 0,
+ /* 8639 */ 'm', 's', 'u', 'b', 'r', '_', 'q', '.', 'w', 9, 0,
+ /* 8650 */ 'm', 'a', 'd', 'd', 'r', '_', 'q', '.', 'w', 9, 0,
+ /* 8661 */ 'm', 'u', 'l', 'r', '_', 'q', '.', 'w', 9, 0,
+ /* 8671 */ 'f', 'c', 'e', 'q', '.', 'w', 9, 0,
+ /* 8679 */ 'f', 's', 'e', 'q', '.', 'w', 9, 0,
+ /* 8687 */ 'f', 'c', 'u', 'e', 'q', '.', 'w', 9, 0,
+ /* 8696 */ 'f', 's', 'u', 'e', 'q', '.', 'w', 9, 0,
+ /* 8705 */ 'f', 't', 'q', '.', 'w', 9, 0,
+ /* 8712 */ 's', 'h', 'r', 'a', '_', 'r', '.', 'w', 9, 0,
+ /* 8722 */ 's', 'u', 'b', 'q', 'h', '_', 'r', '.', 'w', 9, 0,
+ /* 8733 */ 'a', 'd', 'd', 'q', 'h', '_', 'r', '.', 'w', 9, 0,
+ /* 8744 */ 'e', 'x', 't', 'r', '_', 'r', '.', 'w', 9, 0,
+ /* 8754 */ 's', 'h', 'r', 'a', 'v', '_', 'r', '.', 'w', 9, 0,
+ /* 8765 */ 'e', 'x', 't', 'r', 'v', '_', 'r', '.', 'w', 9, 0,
+ /* 8776 */ 's', 'r', 'a', 'r', '.', 'w', 9, 0,
+ /* 8784 */ 'b', 'c', 'l', 'r', '.', 'w', 9, 0,
+ /* 8792 */ 's', 'r', 'l', 'r', '.', 'w', 9, 0,
+ /* 8800 */ 'f', 'c', 'o', 'r', '.', 'w', 9, 0,
+ /* 8808 */ 'f', 's', 'o', 'r', '.', 'w', 9, 0,
+ /* 8816 */ 'f', 'e', 'x', 'u', 'p', 'r', '.', 'w', 9, 0,
+ /* 8826 */ 'f', 'f', 'q', 'r', '.', 'w', 9, 0,
+ /* 8834 */ 'b', 'i', 'n', 's', 'r', '.', 'w', 9, 0,
+ /* 8843 */ 'e', 'x', 't', 'r', '.', 'w', 9, 0,
+ /* 8851 */ 'i', 'l', 'v', 'r', '.', 'w', 9, 0,
+ /* 8859 */ 'c', 'v', 't', '.', 's', '.', 'w', 9, 0,
+ /* 8868 */ 'a', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0,
+ /* 8878 */ 'h', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0,
+ /* 8888 */ 'd', 'p', 's', 'u', 'b', '_', 's', '.', 'w', 9, 0,
+ /* 8899 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 's', '.', 'w', 9, 0,
+ /* 8911 */ 'h', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0,
+ /* 8921 */ 'd', 'p', 'a', 'd', 'd', '_', 's', '.', 'w', 9, 0,
+ /* 8932 */ 'm', 'o', 'd', '_', 's', '.', 'w', 9, 0,
+ /* 8941 */ 'c', 'l', 'e', '_', 's', '.', 'w', 9, 0,
+ /* 8950 */ 'a', 'v', 'e', '_', 's', '.', 'w', 9, 0,
+ /* 8959 */ 'c', 'l', 'e', 'i', '_', 's', '.', 'w', 9, 0,
+ /* 8969 */ 'm', 'i', 'n', 'i', '_', 's', '.', 'w', 9, 0,
+ /* 8979 */ 'c', 'l', 't', 'i', '_', 's', '.', 'w', 9, 0,
+ /* 8989 */ 'm', 'a', 'x', 'i', '_', 's', '.', 'w', 9, 0,
+ /* 8999 */ 's', 'h', 'l', 'l', '_', 's', '.', 'w', 9, 0,
+ /* 9009 */ 'm', 'i', 'n', '_', 's', '.', 'w', 9, 0,
+ /* 9018 */ 'd', 'o', 't', 'p', '_', 's', '.', 'w', 9, 0,
+ /* 9028 */ 's', 'u', 'b', 'q', '_', 's', '.', 'w', 9, 0,
+ /* 9038 */ 'a', 'd', 'd', 'q', '_', 's', '.', 'w', 9, 0,
+ /* 9048 */ 'm', 'u', 'l', 'q', '_', 's', '.', 'w', 9, 0,
+ /* 9058 */ 'a', 'b', 's', 'q', '_', 's', '.', 'w', 9, 0,
+ /* 9068 */ 'a', 'v', 'e', 'r', '_', 's', '.', 'w', 9, 0,
+ /* 9078 */ 's', 'u', 'b', 's', '_', 's', '.', 'w', 9, 0,
+ /* 9088 */ 'a', 'd', 'd', 's', '_', 's', '.', 'w', 9, 0,
+ /* 9098 */ 's', 'a', 't', '_', 's', '.', 'w', 9, 0,
+ /* 9107 */ 'c', 'l', 't', '_', 's', '.', 'w', 9, 0,
+ /* 9116 */ 'f', 'f', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0,
+ /* 9127 */ 'f', 't', 'i', 'n', 't', '_', 's', '.', 'w', 9, 0,
+ /* 9138 */ 's', 'u', 'b', 's', 'u', 'u', '_', 's', '.', 'w', 9, 0,
+ /* 9150 */ 'd', 'i', 'v', '_', 's', '.', 'w', 9, 0,
+ /* 9159 */ 's', 'h', 'l', 'l', 'v', '_', 's', '.', 'w', 9, 0,
+ /* 9170 */ 'm', 'a', 'x', '_', 's', '.', 'w', 9, 0,
+ /* 9179 */ 'c', 'o', 'p', 'y', '_', 's', '.', 'w', 9, 0,
+ /* 9189 */ 'm', 'u', 'l', 'q', '_', 'r', 's', '.', 'w', 9, 0,
+ /* 9200 */ 'e', 'x', 't', 'r', '_', 'r', 's', '.', 'w', 9, 0,
+ /* 9211 */ 'e', 'x', 't', 'r', 'v', '_', 'r', 's', '.', 'w', 9, 0,
+ /* 9223 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'w', 9, 0,
+ /* 9233 */ 's', 'p', 'l', 'a', 't', '.', 'w', 9, 0,
+ /* 9242 */ 'b', 's', 'e', 't', '.', 'w', 9, 0,
+ /* 9250 */ 'f', 'c', 'l', 't', '.', 'w', 9, 0,
+ /* 9258 */ 'f', 's', 'l', 't', '.', 'w', 9, 0,
+ /* 9266 */ 'f', 'c', 'u', 'l', 't', '.', 'w', 9, 0,
+ /* 9275 */ 'f', 's', 'u', 'l', 't', '.', 'w', 9, 0,
+ /* 9284 */ 'p', 'c', 'n', 't', '.', 'w', 9, 0,
+ /* 9292 */ 'f', 'r', 'i', 'n', 't', '.', 'w', 9, 0,
+ /* 9301 */ 'i', 'n', 's', 'e', 'r', 't', '.', 'w', 9, 0,
+ /* 9311 */ 'f', 's', 'q', 'r', 't', '.', 'w', 9, 0,
+ /* 9320 */ 'f', 'r', 's', 'q', 'r', 't', '.', 'w', 9, 0,
+ /* 9330 */ 's', 't', '.', 'w', 9, 0,
+ /* 9336 */ 'a', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0,
+ /* 9346 */ 'h', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0,
+ /* 9356 */ 'd', 'p', 's', 'u', 'b', '_', 'u', '.', 'w', 9, 0,
+ /* 9367 */ 'f', 't', 'r', 'u', 'n', 'c', '_', 'u', '.', 'w', 9, 0,
+ /* 9379 */ 'h', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0,
+ /* 9389 */ 'd', 'p', 'a', 'd', 'd', '_', 'u', '.', 'w', 9, 0,
+ /* 9400 */ 'm', 'o', 'd', '_', 'u', '.', 'w', 9, 0,
+ /* 9409 */ 'c', 'l', 'e', '_', 'u', '.', 'w', 9, 0,
+ /* 9418 */ 'a', 'v', 'e', '_', 'u', '.', 'w', 9, 0,
+ /* 9427 */ 'c', 'l', 'e', 'i', '_', 'u', '.', 'w', 9, 0,
+ /* 9437 */ 'm', 'i', 'n', 'i', '_', 'u', '.', 'w', 9, 0,
+ /* 9447 */ 'c', 'l', 't', 'i', '_', 'u', '.', 'w', 9, 0,
+ /* 9457 */ 'm', 'a', 'x', 'i', '_', 'u', '.', 'w', 9, 0,
+ /* 9467 */ 'm', 'i', 'n', '_', 'u', '.', 'w', 9, 0,
+ /* 9476 */ 'd', 'o', 't', 'p', '_', 'u', '.', 'w', 9, 0,
+ /* 9486 */ 'a', 'v', 'e', 'r', '_', 'u', '.', 'w', 9, 0,
+ /* 9496 */ 's', 'u', 'b', 's', '_', 'u', '.', 'w', 9, 0,
+ /* 9506 */ 'a', 'd', 'd', 's', '_', 'u', '.', 'w', 9, 0,
+ /* 9516 */ 's', 'u', 'b', 's', 'u', 's', '_', 'u', '.', 'w', 9, 0,
+ /* 9528 */ 's', 'a', 't', '_', 'u', '.', 'w', 9, 0,
+ /* 9537 */ 'c', 'l', 't', '_', 'u', '.', 'w', 9, 0,
+ /* 9546 */ 'f', 'f', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0,
+ /* 9557 */ 'f', 't', 'i', 'n', 't', '_', 'u', '.', 'w', 9, 0,
+ /* 9568 */ 'd', 'i', 'v', '_', 'u', '.', 'w', 9, 0,
+ /* 9577 */ 'm', 'a', 'x', '_', 'u', '.', 'w', 9, 0,
+ /* 9586 */ 'c', 'o', 'p', 'y', '_', 'u', '.', 'w', 9, 0,
+ /* 9596 */ 'm', 's', 'u', 'b', 'v', '.', 'w', 9, 0,
+ /* 9605 */ 'm', 'a', 'd', 'd', 'v', '.', 'w', 9, 0,
+ /* 9614 */ 'p', 'c', 'k', 'e', 'v', '.', 'w', 9, 0,
+ /* 9623 */ 'i', 'l', 'v', 'e', 'v', '.', 'w', 9, 0,
+ /* 9632 */ 'f', 'd', 'i', 'v', '.', 'w', 9, 0,
+ /* 9640 */ 'm', 'u', 'l', 'v', '.', 'w', 9, 0,
+ /* 9648 */ 'e', 'x', 't', 'r', 'v', '.', 'w', 9, 0,
+ /* 9657 */ 'f', 'm', 'a', 'x', '.', 'w', 9, 0,
+ /* 9665 */ 'b', 'z', '.', 'w', 9, 0,
+ /* 9671 */ 'b', 'n', 'z', '.', 'w', 9, 0,
+ /* 9678 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0,
+ /* 9686 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0,
+ /* 9695 */ 'u', 'l', 'w', 9, 0,
+ /* 9700 */ 'u', 's', 'w', 9, 0,
+ /* 9705 */ 'p', 'r', 'e', 'f', 'x', 9, 0,
+ /* 9712 */ 'l', 'h', 'x', 9, 0,
+ /* 9717 */ 'j', 'a', 'l', 'x', 9, 0,
+ /* 9723 */ 'l', 'b', 'u', 'x', 9, 0,
+ /* 9729 */ 'l', 'w', 'x', 9, 0,
+ /* 9734 */ 'b', 'g', 'e', 'z', 9, 0,
+ /* 9740 */ 'b', 'l', 'e', 'z', 9, 0,
+ /* 9746 */ 'b', 'n', 'e', 'z', 9, 0,
+ /* 9752 */ 's', 'e', 'l', 'n', 'e', 'z', 9, 0,
+ /* 9760 */ 'b', 't', 'n', 'e', 'z', 9, 0,
+ /* 9767 */ 'd', 'c', 'l', 'z', 9, 0,
+ /* 9773 */ 'b', 'e', 'q', 'z', 9, 0,
+ /* 9779 */ 's', 'e', 'l', 'e', 'q', 'z', 9, 0,
+ /* 9787 */ 'b', 't', 'e', 'q', 'z', 9, 0,
+ /* 9794 */ 'b', 'g', 't', 'z', 9, 0,
+ /* 9800 */ 'b', 'l', 't', 'z', 9, 0,
+ /* 9806 */ 'm', 'o', 'v', 'z', 9, 0,
+ /* 9812 */ 's', 'e', 'b', 9, 32, 0,
+ /* 9818 */ 's', 'e', 'h', 9, 32, 0,
+ /* 9824 */ 'd', 'd', 'i', 'v', 'u', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0,
+ /* 9838 */ 'd', 'd', 'i', 'v', 9, '$', 'z', 'e', 'r', 'o', ',', 32, 0,
+ /* 9851 */ 'a', 'd', 'd', 'i', 'u', 9, '$', 's', 'p', ',', 32, 0,
+ /* 9863 */ 'm', 'f', 't', 'c', '0', 32, 0,
+ /* 9870 */ 'm', 't', 't', 'c', '0', 32, 0,
+ /* 9877 */ 'm', 'f', 't', 'h', 'c', '1', 32, 0,
+ /* 9885 */ 'm', 't', 't', 'h', 'c', '1', 32, 0,
+ /* 9893 */ 'c', 'f', 't', 'c', '1', 32, 0,
+ /* 9900 */ 'm', 'f', 't', 'c', '1', 32, 0,
+ /* 9907 */ 'c', 't', 't', 'c', '1', 32, 0,
+ /* 9914 */ 'm', 't', 't', 'c', '1', 32, 0,
+ /* 9921 */ 's', 'y', 'n', 'c', 32, 0,
+ /* 9927 */ 'l', 'd', 32, 0,
+ /* 9931 */ 9, '.', 'w', 'o', 'r', 'd', 32, 0,
+ /* 9939 */ 's', 'd', 32, 0,
+ /* 9943 */ 'm', 'f', 't', 'h', 'i', 32, 0,
+ /* 9950 */ 'm', 't', 't', 'h', 'i', 32, 0,
+ /* 9957 */ 'm', 'f', 't', 'l', 'o', 32, 0,
+ /* 9964 */ 'm', 't', 't', 'l', 'o', 32, 0,
+ /* 9971 */ 'm', 'f', 't', 'd', 's', 'p', 32, 0,
+ /* 9979 */ 'm', 't', 't', 'd', 's', 'p', 32, 0,
+ /* 9987 */ 's', 'e', 'q', 32, 0,
+ /* 9992 */ 'm', 'f', 't', 'g', 'p', 'r', 32, 0,
+ /* 10000 */ 'm', 't', 't', 'g', 'p', 'r', 32, 0,
+ /* 10008 */ 'd', 'e', 'x', 't', 32, 0,
+ /* 10014 */ 'm', 'f', 't', 'a', 'c', 'x', 32, 0,
+ /* 10022 */ 'm', 't', 't', 'a', 'c', 'x', 32, 0,
+ /* 10030 */ 'b', 'c', '1', 'n', 'e', 'z', 32, 0,
+ /* 10038 */ 'b', 'c', '2', 'n', 'e', 'z', 32, 0,
+ /* 10046 */ 'b', 'c', '1', 'e', 'q', 'z', 32, 0,
+ /* 10054 */ 'b', 'c', '2', 'e', 'q', 'z', 32, 0,
+ /* 10062 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0,
+ /* 10093 */ 'c', '.', 0,
+ /* 10096 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
+ /* 10120 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
+ /* 10145 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0,
+ /* 10168 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0,
+ /* 10191 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0,
+ /* 10213 */ 'b', 'r', 'e', 'a', 'k', 32, '0', 0,
+ /* 10221 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+ /* 10234 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+ /* 10241 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 10251 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 10261 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 10276 */ 'j', 'r', 'c', 9, '$', 'r', 'a', 0,
+ /* 10284 */ 'j', 'r', 9, '$', 'r', 'a', 0,
+ /* 10291 */ 'e', 'h', 'b', 0,
+ /* 10295 */ 'e', 'r', 'e', 't', 'n', 'c', 0,
+ /* 10302 */ 'p', 'a', 'u', 's', 'e', 0,
+ /* 10308 */ 't', 'l', 'b', 'i', 'n', 'v', 'f', 0,
+ /* 10316 */ 't', 'l', 'b', 'g', 'i', 'n', 'v', 'f', 0,
+ /* 10325 */ 't', 'l', 'b', 'w', 'i', 0,
+ /* 10331 */ 't', 'l', 'b', 'g', 'w', 'i', 0,
+ /* 10338 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0,
+ /* 10352 */ 'f', 'o', 'o', 0,
+ /* 10356 */ 't', 'l', 'b', 'p', 0,
+ /* 10361 */ 't', 'l', 'b', 'g', 'p', 0,
+ /* 10367 */ 's', 's', 'n', 'o', 'p', 0,
+ /* 10373 */ 't', 'l', 'b', 'r', 0,
+ /* 10378 */ 't', 'l', 'b', 'g', 'r', 0,
+ /* 10384 */ 't', 'l', 'b', 'w', 'r', 0,
+ /* 10390 */ 't', 'l', 'b', 'g', 'w', 'r', 0,
+ /* 10397 */ 'd', 'e', 'r', 'e', 't', 0,
+ /* 10403 */ 'w', 'a', 'i', 't', 0,
+ /* 10408 */ 't', 'l', 'b', 'i', 'n', 'v', 0,
+ /* 10415 */ 't', 'l', 'b', 'g', 'i', 'n', 'v', 0,
+ };
+
+ static const uint32_t OpInfo0[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // ANNOTATION_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 10242U, // DBG_VALUE
+ 10252U, // DBG_LABEL
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 10235U, // BUNDLE
+ 10262U, // LIFETIME_START
+ 10222U, // LIFETIME_END
+ 0U, // STACKMAP
+ 10339U, // FENTRY_CALL
+ 0U, // PATCHPOINT
+ 0U, // LOAD_STACK_GUARD
+ 0U, // STATEPOINT
+ 0U, // LOCAL_ESCAPE
+ 0U, // FAULTING_OP
+ 0U, // PATCHABLE_OP
+ 10146U, // PATCHABLE_FUNCTION_ENTER
+ 10063U, // PATCHABLE_RET
+ 10192U, // PATCHABLE_FUNCTION_EXIT
+ 10169U, // PATCHABLE_TAIL_CALL
+ 10121U, // PATCHABLE_EVENT_CALL
+ 10097U, // PATCHABLE_TYPED_EVENT_CALL
+ 0U, // ICALL_BRANCH_FUNNEL
+ 0U, // G_ADD
+ 0U, // G_SUB
+ 0U, // G_MUL
+ 0U, // G_SDIV
+ 0U, // G_UDIV
+ 0U, // G_SREM
+ 0U, // G_UREM
+ 0U, // G_AND
+ 0U, // G_OR
+ 0U, // G_XOR
+ 0U, // G_IMPLICIT_DEF
+ 0U, // G_PHI
+ 0U, // G_FRAME_INDEX
+ 0U, // G_GLOBAL_VALUE
+ 0U, // G_EXTRACT
+ 0U, // G_UNMERGE_VALUES
+ 0U, // G_INSERT
+ 0U, // G_MERGE_VALUES
+ 0U, // G_PTRTOINT
+ 0U, // G_INTTOPTR
+ 0U, // G_BITCAST
+ 0U, // G_LOAD
+ 0U, // G_SEXTLOAD
+ 0U, // G_ZEXTLOAD
+ 0U, // G_STORE
+ 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ 0U, // G_ATOMIC_CMPXCHG
+ 0U, // G_ATOMICRMW_XCHG
+ 0U, // G_ATOMICRMW_ADD
+ 0U, // G_ATOMICRMW_SUB
+ 0U, // G_ATOMICRMW_AND
+ 0U, // G_ATOMICRMW_NAND
+ 0U, // G_ATOMICRMW_OR
+ 0U, // G_ATOMICRMW_XOR
+ 0U, // G_ATOMICRMW_MAX
+ 0U, // G_ATOMICRMW_MIN
+ 0U, // G_ATOMICRMW_UMAX
+ 0U, // G_ATOMICRMW_UMIN
+ 0U, // G_BRCOND
+ 0U, // G_BRINDIRECT
+ 0U, // G_INTRINSIC
+ 0U, // G_INTRINSIC_W_SIDE_EFFECTS
+ 0U, // G_ANYEXT
+ 0U, // G_TRUNC
+ 0U, // G_CONSTANT
+ 0U, // G_FCONSTANT
+ 0U, // G_VASTART
+ 0U, // G_VAARG
+ 0U, // G_SEXT
+ 0U, // G_ZEXT
+ 0U, // G_SHL
+ 0U, // G_LSHR
+ 0U, // G_ASHR
+ 0U, // G_ICMP
+ 0U, // G_FCMP
+ 0U, // G_SELECT
+ 0U, // G_UADDE
+ 0U, // G_USUBE
+ 0U, // G_SADDO
+ 0U, // G_SSUBO
+ 0U, // G_UMULO
+ 0U, // G_SMULO
+ 0U, // G_UMULH
+ 0U, // G_SMULH
+ 0U, // G_FADD
+ 0U, // G_FSUB
+ 0U, // G_FMUL
+ 0U, // G_FMA
+ 0U, // G_FDIV
+ 0U, // G_FREM
+ 0U, // G_FPOW
+ 0U, // G_FEXP
+ 0U, // G_FEXP2
+ 0U, // G_FLOG
+ 0U, // G_FLOG2
+ 0U, // G_FNEG
+ 0U, // G_FPEXT
+ 0U, // G_FPTRUNC
+ 0U, // G_FPTOSI
+ 0U, // G_FPTOUI
+ 0U, // G_SITOFP
+ 0U, // G_UITOFP
+ 0U, // G_FABS
+ 0U, // G_GEP
+ 0U, // G_PTR_MASK
+ 0U, // G_BR
+ 0U, // G_INSERT_VECTOR_ELT
+ 0U, // G_EXTRACT_VECTOR_ELT
+ 0U, // G_SHUFFLE_VECTOR
+ 0U, // G_BSWAP
+ 0U, // G_ADDRSPACE_CAST
+ 0U, // G_BLOCK_ADDR
+ 23919U, // ABSMacro
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 0U, // AND_V_D_PSEUDO
+ 0U, // AND_V_H_PSEUDO
+ 0U, // AND_V_W_PSEUDO
+ 0U, // ATOMIC_CMP_SWAP_I16
+ 0U, // ATOMIC_CMP_SWAP_I16_POSTRA
+ 0U, // ATOMIC_CMP_SWAP_I32
+ 0U, // ATOMIC_CMP_SWAP_I32_POSTRA
+ 0U, // ATOMIC_CMP_SWAP_I64
+ 0U, // ATOMIC_CMP_SWAP_I64_POSTRA
+ 0U, // ATOMIC_CMP_SWAP_I8
+ 0U, // ATOMIC_CMP_SWAP_I8_POSTRA
+ 0U, // ATOMIC_LOAD_ADD_I16
+ 0U, // ATOMIC_LOAD_ADD_I16_POSTRA
+ 0U, // ATOMIC_LOAD_ADD_I32
+ 0U, // ATOMIC_LOAD_ADD_I32_POSTRA
+ 0U, // ATOMIC_LOAD_ADD_I64
+ 0U, // ATOMIC_LOAD_ADD_I64_POSTRA
+ 0U, // ATOMIC_LOAD_ADD_I8
+ 0U, // ATOMIC_LOAD_ADD_I8_POSTRA
+ 0U, // ATOMIC_LOAD_AND_I16
+ 0U, // ATOMIC_LOAD_AND_I16_POSTRA
+ 0U, // ATOMIC_LOAD_AND_I32
+ 0U, // ATOMIC_LOAD_AND_I32_POSTRA
+ 0U, // ATOMIC_LOAD_AND_I64
+ 0U, // ATOMIC_LOAD_AND_I64_POSTRA
+ 0U, // ATOMIC_LOAD_AND_I8
+ 0U, // ATOMIC_LOAD_AND_I8_POSTRA
+ 0U, // ATOMIC_LOAD_NAND_I16
+ 0U, // ATOMIC_LOAD_NAND_I16_POSTRA
+ 0U, // ATOMIC_LOAD_NAND_I32
+ 0U, // ATOMIC_LOAD_NAND_I32_POSTRA
+ 0U, // ATOMIC_LOAD_NAND_I64
+ 0U, // ATOMIC_LOAD_NAND_I64_POSTRA
+ 0U, // ATOMIC_LOAD_NAND_I8
+ 0U, // ATOMIC_LOAD_NAND_I8_POSTRA
+ 0U, // ATOMIC_LOAD_OR_I16
+ 0U, // ATOMIC_LOAD_OR_I16_POSTRA
+ 0U, // ATOMIC_LOAD_OR_I32
+ 0U, // ATOMIC_LOAD_OR_I32_POSTRA
+ 0U, // ATOMIC_LOAD_OR_I64
+ 0U, // ATOMIC_LOAD_OR_I64_POSTRA
+ 0U, // ATOMIC_LOAD_OR_I8
+ 0U, // ATOMIC_LOAD_OR_I8_POSTRA
+ 0U, // ATOMIC_LOAD_SUB_I16
+ 0U, // ATOMIC_LOAD_SUB_I16_POSTRA
+ 0U, // ATOMIC_LOAD_SUB_I32
+ 0U, // ATOMIC_LOAD_SUB_I32_POSTRA
+ 0U, // ATOMIC_LOAD_SUB_I64
+ 0U, // ATOMIC_LOAD_SUB_I64_POSTRA
+ 0U, // ATOMIC_LOAD_SUB_I8
+ 0U, // ATOMIC_LOAD_SUB_I8_POSTRA
+ 0U, // ATOMIC_LOAD_XOR_I16
+ 0U, // ATOMIC_LOAD_XOR_I16_POSTRA
+ 0U, // ATOMIC_LOAD_XOR_I32
+ 0U, // ATOMIC_LOAD_XOR_I32_POSTRA
+ 0U, // ATOMIC_LOAD_XOR_I64
+ 0U, // ATOMIC_LOAD_XOR_I64_POSTRA
+ 0U, // ATOMIC_LOAD_XOR_I8
+ 0U, // ATOMIC_LOAD_XOR_I8_POSTRA
+ 0U, // ATOMIC_SWAP_I16
+ 0U, // ATOMIC_SWAP_I16_POSTRA
+ 0U, // ATOMIC_SWAP_I32
+ 0U, // ATOMIC_SWAP_I32_POSTRA
+ 0U, // ATOMIC_SWAP_I64
+ 0U, // ATOMIC_SWAP_I64_POSTRA
+ 0U, // ATOMIC_SWAP_I8
+ 0U, // ATOMIC_SWAP_I8_POSTRA
+ 0U, // B
+ 0U, // BAL_BR
+ 0U, // BAL_BR_MM
+ 268458174U, // BEQLImmMacro
+ 268456054U, // BGE
+ 268456054U, // BGEImmMacro
+ 268458045U, // BGEL
+ 268458045U, // BGELImmMacro
+ 268459555U, // BGEU
+ 268459555U, // BGEUImmMacro
+ 268458205U, // BGEUL
+ 268458205U, // BGEULImmMacro
+ 268459441U, // BGT
+ 268459441U, // BGTImmMacro
+ 268458193U, // BGTL
+ 268458193U, // BGTLImmMacro
+ 268459659U, // BGTU
+ 268459659U, // BGTUImmMacro
+ 268458225U, // BGTUL
+ 268458225U, // BGTULImmMacro
+ 268456081U, // BLE
+ 268456081U, // BLEImmMacro
+ 268458051U, // BLEL
+ 268458051U, // BLELImmMacro
+ 268459567U, // BLEU
+ 268459567U, // BLEUImmMacro
+ 268458212U, // BLEUL
+ 268458212U, // BLEULImmMacro
+ 268459452U, // BLT
+ 268459452U, // BLTImmMacro
+ 268458199U, // BLTL
+ 268458199U, // BLTLImmMacro
+ 268459665U, // BLTU
+ 268459665U, // BLTUImmMacro
+ 268458232U, // BLTUL
+ 268458232U, // BLTULImmMacro
+ 268458057U, // BNELImmMacro
+ 0U, // BPOSGE32_PSEUDO
+ 0U, // BSEL_D_PSEUDO
+ 0U, // BSEL_FD_PSEUDO
+ 0U, // BSEL_FW_PSEUDO
+ 0U, // BSEL_H_PSEUDO
+ 0U, // BSEL_W_PSEUDO
+ 0U, // B_MM
+ 279274U, // B_MMR6_Pseudo
+ 279274U, // B_MM_Pseudo
+ 268458519U, // BeqImm
+ 268456103U, // BneImm
+ 536893857U, // BteqzT8CmpX16
+ 536893300U, // BteqzT8CmpiX16
+ 536894913U, // BteqzT8SltX16
+ 536893330U, // BteqzT8SltiX16
+ 536895057U, // BteqzT8SltiuX16
+ 536895127U, // BteqzT8SltuX16
+ 805329313U, // BtnezT8CmpX16
+ 805328756U, // BtnezT8CmpiX16
+ 805330369U, // BtnezT8SltX16
+ 805328786U, // BtnezT8SltiX16
+ 805330513U, // BtnezT8SltiuX16
+ 805330583U, // BtnezT8SltuX16
+ 0U, // BuildPairF64
+ 0U, // BuildPairF64_64
+ 26278U, // CFTC1
+ 10353U, // CONSTPOOL_ENTRY
+ 0U, // COPY_FD_PSEUDO
+ 0U, // COPY_FW_PSEUDO
+ 8955572U, // CTTC1
+ 288460U, // Constant32
+ 268458219U, // DMULImmMacro
+ 268458219U, // DMULMacro
+ 268458354U, // DMULOMacro
+ 268459644U, // DMULOUMacro
+ 268458168U, // DROL
+ 268458168U, // DROLImm
+ 268458686U, // DROR
+ 268458686U, // DRORImm
+ 268459790U, // DSDivIMacro
+ 268459790U, // DSDivMacro
+ 268458277U, // DSRemIMacro
+ 268458277U, // DSRemMacro
+ 268459698U, // DUDivIMacro
+ 268459698U, // DUDivMacro
+ 268459637U, // DURemIMacro
+ 268459637U, // DURemMacro
+ 0U, // ERet
+ 0U, // ExtractElementF64
+ 0U, // ExtractElementF64_64
+ 0U, // FABS_D
+ 0U, // FABS_W
+ 0U, // FEXP2_D_1_PSEUDO
+ 0U, // FEXP2_W_1_PSEUDO
+ 0U, // FILL_FD_PSEUDO
+ 0U, // FILL_FW_PSEUDO
+ 1090541419U, // GotPrologue16
+ 0U, // INSERT_B_VIDX64_PSEUDO
+ 0U, // INSERT_B_VIDX_PSEUDO
+ 0U, // INSERT_D_VIDX64_PSEUDO
+ 0U, // INSERT_D_VIDX_PSEUDO
+ 0U, // INSERT_FD_PSEUDO
+ 0U, // INSERT_FD_VIDX64_PSEUDO
+ 0U, // INSERT_FD_VIDX_PSEUDO
+ 0U, // INSERT_FW_PSEUDO
+ 0U, // INSERT_FW_VIDX64_PSEUDO
+ 0U, // INSERT_FW_VIDX_PSEUDO
+ 0U, // INSERT_H_VIDX64_PSEUDO
+ 0U, // INSERT_H_VIDX_PSEUDO
+ 0U, // INSERT_W_VIDX64_PSEUDO
+ 0U, // INSERT_W_VIDX_PSEUDO
+ 0U, // JALR64Pseudo
+ 0U, // JALRHB64Pseudo
+ 0U, // JALRHBPseudo
+ 0U, // JALRPseudo
+ 284631U, // JalOneReg
+ 22487U, // JalTwoReg
+ 25192136U, // LDMacro
+ 0U, // LD_F16
+ 25182214U, // LOAD_ACC128
+ 25182214U, // LOAD_ACC64
+ 25182214U, // LOAD_ACC64DSP
+ 25188791U, // LOAD_CCOND_DSP
+ 0U, // LONG_BRANCH_ADDiu
+ 0U, // LONG_BRANCH_DADDiu
+ 0U, // LONG_BRANCH_LUi
+ 842041U, // LWM_MM
+ 17037U, // LoadAddrImm32
+ 17058U, // LoadAddrImm64
+ 25182861U, // LoadAddrReg32
+ 25182882U, // LoadAddrReg64
+ 22379U, // LoadImm32
+ 22383U, // LoadImm64
+ 19102U, // LoadImmDoubleFGR
+ 19102U, // LoadImmDoubleFGR_32
+ 19102U, // LoadImmDoubleGPR
+ 23494U, // LoadImmSingleFGR
+ 23494U, // LoadImmSingleGPR
+ 1074657U, // LwConstant32
+ 26399U, // MFTACX
+ 268461704U, // MFTC0
+ 26285U, // MFTC1
+ 288500U, // MFTDSP
+ 26377U, // MFTGPR
+ 26262U, // MFTHC1
+ 26328U, // MFTHI
+ 26342U, // MFTLO
+ 0U, // MIPSeh_return32
+ 0U, // MIPSeh_return64
+ 0U, // MSA_FP_EXTEND_D_PSEUDO
+ 0U, // MSA_FP_EXTEND_W_PSEUDO
+ 0U, // MSA_FP_ROUND_D_PSEUDO
+ 0U, // MSA_FP_ROUND_W_PSEUDO
+ 8955687U, // MTTACX
+ 1376298639U, // MTTC0
+ 8955579U, // MTTC1
+ 288508U, // MTTDSP
+ 8955665U, // MTTGPR
+ 8955550U, // MTTHC1
+ 8955615U, // MTTHI
+ 8955629U, // MTTLO
+ 268458220U, // MULImmMacro
+ 268458355U, // MULOMacro
+ 268459645U, // MULOUMacro
+ 24012U, // MultRxRy16
+ 43294156U, // MultRxRyRz16
+ 24228U, // MultuRxRy16
+ 43294372U, // MultuRxRyRz16
+ 0U, // NOP
+ 268458681U, // NORImm
+ 268458681U, // NORImm64
+ 0U, // NOR_V_D_PSEUDO
+ 0U, // NOR_V_H_PSEUDO
+ 0U, // NOR_V_W_PSEUDO
+ 0U, // OR_V_D_PSEUDO
+ 0U, // OR_V_H_PSEUDO
+ 0U, // OR_V_W_PSEUDO
+ 0U, // PseudoCMPU_EQ_QB
+ 0U, // PseudoCMPU_LE_QB
+ 0U, // PseudoCMPU_LT_QB
+ 0U, // PseudoCMP_EQ_PH
+ 0U, // PseudoCMP_LE_PH
+ 0U, // PseudoCMP_LT_PH
+ 16390U, // PseudoCVT_D32_W
+ 16390U, // PseudoCVT_D64_L
+ 16390U, // PseudoCVT_D64_W
+ 16390U, // PseudoCVT_S_L
+ 16390U, // PseudoCVT_S_W
+ 0U, // PseudoDMULT
+ 0U, // PseudoDMULTu
+ 0U, // PseudoDSDIV
+ 0U, // PseudoDUDIV
+ 0U, // PseudoIndirectBranch
+ 0U, // PseudoIndirectBranch64
+ 0U, // PseudoIndirectBranch64R6
+ 0U, // PseudoIndirectBranchR6
+ 0U, // PseudoIndirectBranch_MM
+ 0U, // PseudoIndirectBranch_MMR6
+ 0U, // PseudoIndirectHazardBranch
+ 0U, // PseudoIndirectHazardBranch64
+ 0U, // PseudoIndrectHazardBranch64R6
+ 0U, // PseudoIndrectHazardBranchR6
+ 0U, // PseudoMADD
+ 0U, // PseudoMADDU
+ 0U, // PseudoMFHI
+ 0U, // PseudoMFHI64
+ 0U, // PseudoMFLO
+ 0U, // PseudoMFLO64
+ 0U, // PseudoMSUB
+ 0U, // PseudoMSUBU
+ 0U, // PseudoMTLOHI
+ 0U, // PseudoMTLOHI64
+ 0U, // PseudoMTLOHI_DSP
+ 0U, // PseudoMULT
+ 0U, // PseudoMULTu
+ 0U, // PseudoPICK_PH
+ 0U, // PseudoPICK_QB
+ 0U, // PseudoReturn
+ 0U, // PseudoReturn64
+ 0U, // PseudoSDIV
+ 0U, // PseudoSELECTFP_F_D32
+ 0U, // PseudoSELECTFP_F_D64
+ 0U, // PseudoSELECTFP_F_I
+ 0U, // PseudoSELECTFP_F_I64
+ 0U, // PseudoSELECTFP_F_S
+ 0U, // PseudoSELECTFP_T_D32
+ 0U, // PseudoSELECTFP_T_D64
+ 0U, // PseudoSELECTFP_T_I
+ 0U, // PseudoSELECTFP_T_I64
+ 0U, // PseudoSELECTFP_T_S
+ 0U, // PseudoSELECT_D32
+ 0U, // PseudoSELECT_D64
+ 0U, // PseudoSELECT_I
+ 0U, // PseudoSELECT_I64
+ 0U, // PseudoSELECT_S
+ 268455839U, // PseudoTRUNC_W_D
+ 268455839U, // PseudoTRUNC_W_D32
+ 268459288U, // PseudoTRUNC_W_S
+ 0U, // PseudoUDIV
+ 268458169U, // ROL
+ 268458169U, // ROLImm
+ 268458687U, // ROR
+ 268458687U, // RORImm
+ 0U, // RetRA
+ 0U, // RetRA16
+ 0U, // SDIV_MM_Pseudo
+ 25192148U, // SDMacro
+ 268459791U, // SDivIMacro
+ 268459791U, // SDivMacro
+ 268461828U, // SEQIMacro
+ 268461828U, // SEQMacro
+ 268459457U, // SLTImm64
+ 268459671U, // SLTUImm64
+ 0U, // SNZ_B_PSEUDO
+ 0U, // SNZ_D_PSEUDO
+ 0U, // SNZ_H_PSEUDO
+ 0U, // SNZ_V_PSEUDO
+ 0U, // SNZ_W_PSEUDO
+ 268458278U, // SRemIMacro
+ 268458278U, // SRemMacro
+ 25182214U, // STORE_ACC128
+ 25182214U, // STORE_ACC64
+ 25182214U, // STORE_ACC64DSP
+ 25188807U, // STORE_CCOND_DSP
+ 0U, // ST_F16
+ 842046U, // SWM_MM
+ 0U, // SZ_B_PSEUDO
+ 0U, // SZ_D_PSEUDO
+ 0U, // SZ_H_PSEUDO
+ 0U, // SZ_V_PSEUDO
+ 0U, // SZ_W_PSEUDO
+ 1648174U, // SelBeqZ
+ 1648147U, // SelBneZ
+ 1661016481U, // SelTBteqZCmp
+ 1661015924U, // SelTBteqZCmpi
+ 1661017537U, // SelTBteqZSlt
+ 1661015954U, // SelTBteqZSlti
+ 1661017681U, // SelTBteqZSltiu
+ 1661017751U, // SelTBteqZSltu
+ 1929451937U, // SelTBtneZCmp
+ 1929451380U, // SelTBtneZCmpi
+ 1929452993U, // SelTBtneZSlt
+ 1929451410U, // SelTBtneZSlti
+ 1929453137U, // SelTBtneZSltiu
+ 1929453207U, // SelTBtneZSltu
+ 60071361U, // SltCCRxRy16
+ 60069778U, // SltiCCRxImmX16
+ 60071505U, // SltiuCCRxImmX16
+ 60071575U, // SltuCCRxRy16
+ 60071575U, // SltuRxRyRz16
+ 0U, // TAILCALL
+ 0U, // TAILCALL64R6REG
+ 0U, // TAILCALLHB64R6REG
+ 0U, // TAILCALLHBR6REG
+ 0U, // TAILCALLR6REG
+ 0U, // TAILCALLREG
+ 0U, // TAILCALLREG64
+ 0U, // TAILCALLREGHB
+ 0U, // TAILCALLREGHB64
+ 0U, // TAILCALLREG_MM
+ 0U, // TAILCALLREG_MMR6
+ 0U, // TAILCALL_MM
+ 0U, // TAILCALL_MMR6
+ 0U, // TRAP
+ 0U, // TRAP_MM
+ 0U, // UDIV_MM_Pseudo
+ 268459699U, // UDivIMacro
+ 268459699U, // UDivMacro
+ 268459638U, // URemIMacro
+ 268459638U, // URemMacro
+ 25187573U, // Ulh
+ 25189941U, // Ulhu
+ 25191904U, // Ulw
+ 25188126U, // Ush
+ 25191909U, // Usw
+ 0U, // XOR_V_D_PSEUDO
+ 0U, // XOR_V_H_PSEUDO
+ 0U, // XOR_V_W_PSEUDO
+ 22023U, // ABSQ_S_PH
+ 22023U, // ABSQ_S_PH_MM
+ 18192U, // ABSQ_S_QB
+ 18192U, // ABSQ_S_QB_MMR2
+ 25443U, // ABSQ_S_W
+ 25443U, // ABSQ_S_W_MM
+ 268455963U, // ADD
+ 18478U, // ADDIUPC
+ 18478U, // ADDIUPC_MM
+ 18478U, // ADDIUPC_MMR6
+ 22956U, // ADDIUR1SP_MM
+ 268452218U, // ADDIUR2_MM
+ 9732507U, // ADDIUS5_MM
+ 285161U, // ADDIUSP_MM
+ 268459587U, // ADDIU_MMR6
+ 268457284U, // ADDQH_PH
+ 268457284U, // ADDQH_PH_MMR2
+ 268457401U, // ADDQH_R_PH
+ 268457401U, // ADDQH_R_PH_MMR2
+ 268460574U, // ADDQH_R_W
+ 268460574U, // ADDQH_R_W_MMR2
+ 268460177U, // ADDQH_W
+ 268460177U, // ADDQH_W_MMR2
+ 268457358U, // ADDQ_PH
+ 268457358U, // ADDQ_PH_MM
+ 268457457U, // ADDQ_S_PH
+ 268457457U, // ADDQ_S_PH_MM
+ 268460879U, // ADDQ_S_W
+ 268460879U, // ADDQ_S_W_MM
+ 268453974U, // ADDSC
+ 268453974U, // ADDSC_MM
+ 268452598U, // ADDS_A_B
+ 268454135U, // ADDS_A_D
+ 268456211U, // ADDS_A_H
+ 268459885U, // ADDS_A_W
+ 268453066U, // ADDS_S_B
+ 268455233U, // ADDS_S_D
+ 268456768U, // ADDS_S_H
+ 268460929U, // ADDS_S_W
+ 268453281U, // ADDS_U_B
+ 268455700U, // ADDS_U_D
+ 268457046U, // ADDS_U_H
+ 268461347U, // ADDS_U_W
+ 268452438U, // ADDU16_MM
+ 268452438U, // ADDU16_MMR6
+ 268453516U, // ADDUH_QB
+ 268453516U, // ADDUH_QB_MMR2
+ 268453624U, // ADDUH_R_QB
+ 268453624U, // ADDUH_R_QB_MMR2
+ 268459528U, // ADDU_MMR6
+ 268457556U, // ADDU_PH
+ 268457556U, // ADDU_PH_MMR2
+ 268453729U, // ADDU_QB
+ 268453729U, // ADDU_QB_MM
+ 268457501U, // ADDU_S_PH
+ 268457501U, // ADDU_S_PH_MMR2
+ 268453670U, // ADDU_S_QB
+ 268453670U, // ADDU_S_QB_MM
+ 268452847U, // ADDVI_B
+ 268454655U, // ADDVI_D
+ 268456427U, // ADDVI_H
+ 268460310U, // ADDVI_W
+ 268453359U, // ADDV_B
+ 268455790U, // ADDV_D
+ 268457124U, // ADDV_H
+ 268461447U, // ADDV_W
+ 268454013U, // ADDWC
+ 268454013U, // ADDWC_MM
+ 268452580U, // ADD_A_B
+ 268454116U, // ADD_A_D
+ 268456193U, // ADD_A_H
+ 268459866U, // ADD_A_W
+ 268455963U, // ADD_MM
+ 268455963U, // ADD_MMR6
+ 268457777U, // ADDi
+ 268457777U, // ADDi_MM
+ 268459587U, // ADDiu
+ 268459587U, // ADDiu_MM
+ 268459528U, // ADDu
+ 268459528U, // ADDu_MM
+ 268458308U, // ALIGN
+ 268458308U, // ALIGN_MMR6
+ 18470U, // ALUIPC
+ 18470U, // ALUIPC_MMR6
+ 268455992U, // AND
+ 10305993U, // AND16_MM
+ 10305993U, // AND16_MMR6
+ 268455992U, // AND64
+ 268452318U, // ANDI16_MM
+ 268452318U, // ANDI16_MMR6
+ 268452706U, // ANDI_B
+ 268457783U, // ANDI_MMR6
+ 268455992U, // AND_MM
+ 268455992U, // AND_MMR6
+ 268459710U, // AND_V
+ 268457783U, // ANDi
+ 268457783U, // ANDi64
+ 268457783U, // ANDi_MM
+ 268456006U, // APPEND
+ 268456006U, // APPEND_MMR2
+ 268452960U, // ASUB_S_B
+ 268455063U, // ASUB_S_D
+ 268456600U, // ASUB_S_H
+ 268460709U, // ASUB_S_W
+ 268453175U, // ASUB_U_B
+ 268455530U, // ASUB_U_D
+ 268456888U, // ASUB_U_H
+ 268461177U, // ASUB_U_W
+ 268457887U, // AUI
+ 18463U, // AUIPC
+ 18463U, // AUIPC_MMR6
+ 268457887U, // AUI_MMR6
+ 268453046U, // AVER_S_B
+ 268455213U, // AVER_S_D
+ 268456738U, // AVER_S_H
+ 268460909U, // AVER_S_W
+ 268453261U, // AVER_U_B
+ 268455680U, // AVER_U_D
+ 268457026U, // AVER_U_H
+ 268461327U, // AVER_U_W
+ 268452988U, // AVE_S_B
+ 268455145U, // AVE_S_D
+ 268456670U, // AVE_S_H
+ 268460791U, // AVE_S_W
+ 268453203U, // AVE_U_B
+ 268455612U, // AVE_U_D
+ 268456958U, // AVE_U_H
+ 268461259U, // AVE_U_W
+ 24131U, // AddiuRxImmX16
+ 2121283U, // AddiuRxPcImmX16
+ 2164284995U, // AddiuRxRxImm16
+ 16801347U, // AddiuRxRxImmX16
+ 67132995U, // AddiuRxRyOffMemX16
+ 2385532U, // AddiuSpImm16
+ 288380U, // AddiuSpImmX16
+ 268459528U, // AdduRxRyRz16
+ 16797752U, // AndRxRxRy16
+ 278949U, // B16_MM
+ 268459527U, // BADDu
+ 284626U, // BAL
+ 280528U, // BALC
+ 280528U, // BALC_MMR6
+ 268458307U, // BALIGN
+ 268458307U, // BALIGN_MMR2
+ 75513935U, // BBIT0
+ 75514067U, // BBIT032
+ 75514060U, // BBIT1
+ 75514076U, // BBIT132
+ 280507U, // BC
+ 278954U, // BC16_MMR6
+ 26431U, // BC1EQZ
+ 18603U, // BC1EQZC_MMR6
+ 20714U, // BC1F
+ 22607U, // BC1FL
+ 20714U, // BC1F_MM
+ 26415U, // BC1NEZ
+ 18578U, // BC1NEZC_MMR6
+ 23979U, // BC1T
+ 22730U, // BC1TL
+ 23979U, // BC1T_MM
+ 26439U, // BC2EQZ
+ 18612U, // BC2EQZC_MMR6
+ 26423U, // BC2NEZ
+ 18587U, // BC2NEZC_MMR6
+ 268452775U, // BCLRI_B
+ 268454599U, // BCLRI_D
+ 268456371U, // BCLRI_H
+ 268460254U, // BCLRI_W
+ 268452927U, // BCLR_B
+ 268454987U, // BCLR_D
+ 268456567U, // BCLR_H
+ 268460625U, // BCLR_W
+ 280507U, // BC_MMR6
+ 268458519U, // BEQ
+ 268458519U, // BEQ64
+ 268453956U, // BEQC
+ 268453956U, // BEQC64
+ 268453956U, // BEQC_MMR6
+ 268458174U, // BEQL
+ 17017U, // BEQZ16_MM
+ 18424U, // BEQZALC
+ 18424U, // BEQZALC_MMR6
+ 18621U, // BEQZC
+ 16832U, // BEQZC16_MMR6
+ 18621U, // BEQZC64
+ 18621U, // BEQZC_MM
+ 18621U, // BEQZC_MMR6
+ 268458519U, // BEQ_MM
+ 268453823U, // BGEC
+ 268453823U, // BGEC64
+ 268453823U, // BGEC_MMR6
+ 268453987U, // BGEUC
+ 268453987U, // BGEUC64
+ 268453987U, // BGEUC_MMR6
+ 26119U, // BGEZ
+ 26119U, // BGEZ64
+ 22492U, // BGEZAL
+ 18397U, // BGEZALC
+ 18397U, // BGEZALC_MMR6
+ 22688U, // BGEZALL
+ 23930U, // BGEZALS_MM
+ 22492U, // BGEZAL_MM
+ 18564U, // BGEZC
+ 18564U, // BGEZC64
+ 18564U, // BGEZC_MMR6
+ 22793U, // BGEZL
+ 26119U, // BGEZ_MM
+ 26179U, // BGTZ
+ 26179U, // BGTZ64
+ 18433U, // BGTZALC
+ 18433U, // BGTZALC_MMR6
+ 18628U, // BGTZC
+ 18628U, // BGTZC64
+ 18628U, // BGTZC_MMR6
+ 22807U, // BGTZL
+ 26179U, // BGTZ_MM
+ 285229964U, // BINSLI_B
+ 285231788U, // BINSLI_D
+ 285233560U, // BINSLI_H
+ 285237443U, // BINSLI_W
+ 285230111U, // BINSL_B
+ 285231988U, // BINSL_D
+ 285233674U, // BINSL_H
+ 285237601U, // BINSL_W
+ 285230025U, // BINSRI_B
+ 285231833U, // BINSRI_D
+ 285233605U, // BINSRI_H
+ 285237488U, // BINSRI_W
+ 285230159U, // BINSR_B
+ 285232253U, // BINSR_D
+ 285233799U, // BINSR_H
+ 285237891U, // BINSR_W
+ 24326U, // BITREV
+ 24326U, // BITREV_MM
+ 22906U, // BITSWAP
+ 22906U, // BITSWAP_MMR6
+ 26125U, // BLEZ
+ 26125U, // BLEZ64
+ 18406U, // BLEZALC
+ 18406U, // BLEZALC_MMR6
+ 18571U, // BLEZC
+ 18571U, // BLEZC64
+ 18571U, // BLEZC_MMR6
+ 22800U, // BLEZL
+ 26125U, // BLEZ_MM
+ 268453981U, // BLTC
+ 268453981U, // BLTC64
+ 268453981U, // BLTC_MMR6
+ 268453994U, // BLTUC
+ 268453994U, // BLTUC64
+ 268453994U, // BLTUC_MMR6
+ 26185U, // BLTZ
+ 26185U, // BLTZ64
+ 22500U, // BLTZAL
+ 18442U, // BLTZALC
+ 18442U, // BLTZALC_MMR6
+ 22697U, // BLTZALL
+ 23939U, // BLTZALS_MM
+ 22500U, // BLTZAL_MM
+ 18635U, // BLTZC
+ 18635U, // BLTZC64
+ 18635U, // BLTZC_MMR6
+ 22814U, // BLTZL
+ 26185U, // BLTZ_MM
+ 285230080U, // BMNZI_B
+ 285236983U, // BMNZ_V
+ 285230072U, // BMZI_B
+ 285236969U, // BMZ_V
+ 268456103U, // BNE
+ 268456103U, // BNE64
+ 268453829U, // BNEC
+ 268453829U, // BNEC64
+ 268453829U, // BNEC_MMR6
+ 268452714U, // BNEGI_B
+ 268454547U, // BNEGI_D
+ 268456319U, // BNEGI_H
+ 268460202U, // BNEGI_W
+ 268452682U, // BNEG_B
+ 268454523U, // BNEG_D
+ 268456295U, // BNEG_H
+ 268460097U, // BNEG_W
+ 268458057U, // BNEL
+ 17009U, // BNEZ16_MM
+ 18415U, // BNEZALC
+ 18415U, // BNEZALC_MMR6
+ 18596U, // BNEZC
+ 16823U, // BNEZC16_MMR6
+ 18596U, // BNEZC64
+ 18596U, // BNEZC_MM
+ 18596U, // BNEZC_MMR6
+ 268456103U, // BNE_MM
+ 268454001U, // BNVC
+ 268454001U, // BNVC_MMR6
+ 17943U, // BNZ_B
+ 20459U, // BNZ_D
+ 21708U, // BNZ_H
+ 24304U, // BNZ_V
+ 26056U, // BNZ_W
+ 268454007U, // BOVC
+ 268454007U, // BOVC_MMR6
+ 278765U, // BPOSGE32
+ 280496U, // BPOSGE32C_MMR3
+ 278765U, // BPOSGE32_MM
+ 83990451U, // BREAK
+ 115188U, // BREAK16_MM
+ 115188U, // BREAK16_MMR6
+ 83990451U, // BREAK_MM
+ 83990451U, // BREAK_MMR6
+ 285229939U, // BSELI_B
+ 285236941U, // BSEL_V
+ 268452829U, // BSETI_B
+ 268454637U, // BSETI_D
+ 268456409U, // BSETI_H
+ 268460292U, // BSETI_W
+ 268453143U, // BSET_B
+ 268455349U, // BSET_D
+ 268456856U, // BSET_H
+ 268461083U, // BSET_W
+ 17937U, // BZ_B
+ 20443U, // BZ_D
+ 21702U, // BZ_H
+ 24291U, // BZ_V
+ 26050U, // BZ_W
+ 2415945262U, // BeqzRxImm16
+ 26158U, // BeqzRxImmX16
+ 2376426U, // Bimm16
+ 279274U, // BimmX16
+ 2415945235U, // BnezRxImm16
+ 26131U, // BnezRxImmX16
+ 10214U, // Break16
+ 2647612U, // Bteqz16
+ 288316U, // BteqzX16
+ 2647585U, // Btnez16
+ 288289U, // BtnezX16
+ 3018880U, // CACHE
+ 3018855U, // CACHEE
+ 3018855U, // CACHEE_MM
+ 3018880U, // CACHE_MM
+ 3018880U, // CACHE_MMR6
+ 3018880U, // CACHE_R6
+ 19230U, // CEIL_L_D64
+ 19230U, // CEIL_L_D_MMR6
+ 23522U, // CEIL_L_S
+ 23522U, // CEIL_L_S_MMR6
+ 20405U, // CEIL_W_D32
+ 20405U, // CEIL_W_D64
+ 20405U, // CEIL_W_D_MMR6
+ 20405U, // CEIL_W_MM
+ 23854U, // CEIL_W_S
+ 23854U, // CEIL_W_S_MM
+ 23854U, // CEIL_W_S_MMR6
+ 268452758U, // CEQI_B
+ 268454582U, // CEQI_D
+ 268456354U, // CEQI_H
+ 268460237U, // CEQI_W
+ 268452912U, // CEQ_B
+ 268454894U, // CEQ_D
+ 268456545U, // CEQ_H
+ 268460513U, // CEQ_W
+ 16482U, // CFC1
+ 16482U, // CFC1_MM
+ 16698U, // CFC2_MM
+ 17108U, // CFCMSA
+ 268459404U, // CINS
+ 268452126U, // CINS32
+ 268459404U, // CINS64_32
+ 268459404U, // CINS_i32
+ 19875U, // CLASS_D
+ 19875U, // CLASS_D_MMR6
+ 23705U, // CLASS_S
+ 23705U, // CLASS_S_MMR6
+ 268452997U, // CLEI_S_B
+ 268455154U, // CLEI_S_D
+ 268456679U, // CLEI_S_H
+ 268460800U, // CLEI_S_W
+ 268453212U, // CLEI_U_B
+ 268455621U, // CLEI_U_D
+ 268456967U, // CLEI_U_H
+ 268461268U, // CLEI_U_W
+ 268452979U, // CLE_S_B
+ 268455136U, // CLE_S_D
+ 268456661U, // CLE_S_H
+ 268460782U, // CLE_S_W
+ 268453194U, // CLE_U_B
+ 268455603U, // CLE_U_D
+ 268456949U, // CLE_U_H
+ 268461250U, // CLE_U_W
+ 22874U, // CLO
+ 22874U, // CLO_MM
+ 22874U, // CLO_MMR6
+ 22874U, // CLO_R6
+ 268453017U, // CLTI_S_B
+ 268455174U, // CLTI_S_D
+ 268456699U, // CLTI_S_H
+ 268460820U, // CLTI_S_W
+ 268453232U, // CLTI_U_B
+ 268455641U, // CLTI_U_D
+ 268456987U, // CLTI_U_H
+ 268461288U, // CLTI_U_W
+ 268453085U, // CLT_S_B
+ 268455252U, // CLT_S_D
+ 268456787U, // CLT_S_H
+ 268460948U, // CLT_S_W
+ 268453312U, // CLT_U_B
+ 268455731U, // CLT_U_D
+ 268457077U, // CLT_U_H
+ 268461378U, // CLT_U_W
+ 26153U, // CLZ
+ 26153U, // CLZ_MM
+ 26153U, // CLZ_MMR6
+ 26153U, // CLZ_R6
+ 268453562U, // CMPGDU_EQ_QB
+ 268453562U, // CMPGDU_EQ_QB_MMR2
+ 268453467U, // CMPGDU_LE_QB
+ 268453467U, // CMPGDU_LE_QB_MMR2
+ 268453681U, // CMPGDU_LT_QB
+ 268453681U, // CMPGDU_LT_QB_MMR2
+ 268453576U, // CMPGU_EQ_QB
+ 268453576U, // CMPGU_EQ_QB_MM
+ 268453481U, // CMPGU_LE_QB
+ 268453481U, // CMPGU_LE_QB_MM
+ 268453695U, // CMPGU_LT_QB
+ 268453695U, // CMPGU_LT_QB_MM
+ 18133U, // CMPU_EQ_QB
+ 18133U, // CMPU_EQ_QB_MM
+ 18038U, // CMPU_LE_QB
+ 18038U, // CMPU_LE_QB_MM
+ 18252U, // CMPU_LT_QB
+ 18252U, // CMPU_LT_QB_MM
+ 268454444U, // CMP_AF_D_MMR6
+ 268458888U, // CMP_AF_S_MMR6
+ 268454883U, // CMP_EQ_D
+ 268454883U, // CMP_EQ_D_MMR6
+ 21911U, // CMP_EQ_PH
+ 21911U, // CMP_EQ_PH_MM
+ 268459092U, // CMP_EQ_S
+ 268459092U, // CMP_EQ_S_MMR6
+ 268454444U, // CMP_F_D
+ 268458888U, // CMP_F_S
+ 268454288U, // CMP_LE_D
+ 268454288U, // CMP_LE_D_MMR6
+ 21807U, // CMP_LE_PH
+ 21807U, // CMP_LE_PH_MM
+ 268458809U, // CMP_LE_S
+ 268458809U, // CMP_LE_S_MMR6
+ 268455374U, // CMP_LT_D
+ 268455374U, // CMP_LT_D_MMR6
+ 22080U, // CMP_LT_PH
+ 22080U, // CMP_LT_PH_MM
+ 268459187U, // CMP_LT_S
+ 268459187U, // CMP_LT_S_MMR6
+ 268454462U, // CMP_SAF_D
+ 268454462U, // CMP_SAF_D_MMR6
+ 268458898U, // CMP_SAF_S
+ 268458898U, // CMP_SAF_S_MMR6
+ 268454910U, // CMP_SEQ_D
+ 268454910U, // CMP_SEQ_D_MMR6
+ 268459111U, // CMP_SEQ_S
+ 268459111U, // CMP_SEQ_S_MMR6
+ 268454325U, // CMP_SLE_D
+ 268454325U, // CMP_SLE_D_MMR6
+ 268458838U, // CMP_SLE_S
+ 268458838U, // CMP_SLE_S_MMR6
+ 268455401U, // CMP_SLT_D
+ 268455401U, // CMP_SLT_D_MMR6
+ 268459206U, // CMP_SLT_S
+ 268459206U, // CMP_SLT_S_MMR6
+ 268454958U, // CMP_SUEQ_D
+ 268454958U, // CMP_SUEQ_D_MMR6
+ 268459142U, // CMP_SUEQ_S
+ 268459142U, // CMP_SUEQ_S_MMR6
+ 268454373U, // CMP_SULE_D
+ 268454373U, // CMP_SULE_D_MMR6
+ 268458869U, // CMP_SULE_S
+ 268458869U, // CMP_SULE_S_MMR6
+ 268455449U, // CMP_SULT_D
+ 268455449U, // CMP_SULT_D_MMR6
+ 268459237U, // CMP_SULT_S
+ 268459237U, // CMP_SULT_S_MMR6
+ 268454831U, // CMP_SUN_D
+ 268454831U, // CMP_SUN_D_MMR6
+ 268459056U, // CMP_SUN_S
+ 268459056U, // CMP_SUN_S_MMR6
+ 268454938U, // CMP_UEQ_D
+ 268454938U, // CMP_UEQ_D_MMR6
+ 268459131U, // CMP_UEQ_S
+ 268459131U, // CMP_UEQ_S_MMR6
+ 268454353U, // CMP_ULE_D
+ 268454353U, // CMP_ULE_D_MMR6
+ 268458858U, // CMP_ULE_S
+ 268458858U, // CMP_ULE_S_MMR6
+ 268455429U, // CMP_ULT_D
+ 268455429U, // CMP_ULT_D_MMR6
+ 268459226U, // CMP_ULT_S
+ 268459226U, // CMP_ULT_S_MMR6
+ 268454813U, // CMP_UN_D
+ 268454813U, // CMP_UN_D_MMR6
+ 268459046U, // CMP_UN_S
+ 268459046U, // CMP_UN_S_MMR6
+ 2684372228U, // COPY_S_B
+ 2684374417U, // COPY_S_D
+ 2684375941U, // COPY_S_H
+ 2684380124U, // COPY_S_W
+ 2684372443U, // COPY_U_B
+ 2684376208U, // COPY_U_H
+ 2684380531U, // COPY_U_W
+ 268453406U, // CRC32B
+ 268453414U, // CRC32CB
+ 268455948U, // CRC32CD
+ 268457191U, // CRC32CH
+ 268461527U, // CRC32CW
+ 268455940U, // CRC32D
+ 268457171U, // CRC32H
+ 268461519U, // CRC32W
+ 8945789U, // CTC1
+ 8945789U, // CTC1_MM
+ 8946005U, // CTC2_MM
+ 17116U, // CTCMSA
+ 23318U, // CVT_D32_S
+ 23318U, // CVT_D32_S_MM
+ 24489U, // CVT_D32_W
+ 24489U, // CVT_D32_W_MM
+ 22464U, // CVT_D64_L
+ 23318U, // CVT_D64_S
+ 23318U, // CVT_D64_S_MM
+ 24489U, // CVT_D64_W
+ 24489U, // CVT_D64_W_MM
+ 22464U, // CVT_D_L_MMR6
+ 19251U, // CVT_L_D64
+ 19251U, // CVT_L_D64_MM
+ 19251U, // CVT_L_D_MMR6
+ 23543U, // CVT_L_S
+ 23543U, // CVT_L_S_MM
+ 23543U, // CVT_L_S_MMR6
+ 19598U, // CVT_S_D32
+ 19598U, // CVT_S_D32_MM
+ 19598U, // CVT_S_D64
+ 19598U, // CVT_S_D64_MM
+ 22473U, // CVT_S_L
+ 22473U, // CVT_S_L_MMR6
+ 25244U, // CVT_S_W
+ 25244U, // CVT_S_W_MM
+ 25244U, // CVT_S_W_MMR6
+ 20426U, // CVT_W_D32
+ 20426U, // CVT_W_D32_MM
+ 20426U, // CVT_W_D64
+ 20426U, // CVT_W_D64_MM
+ 23875U, // CVT_W_S
+ 23875U, // CVT_W_S_MM
+ 23875U, // CVT_W_S_MMR6
+ 268454875U, // C_EQ_D32
+ 268454875U, // C_EQ_D32_MM
+ 268454875U, // C_EQ_D64
+ 268454875U, // C_EQ_D64_MM
+ 268459084U, // C_EQ_S
+ 268459084U, // C_EQ_S_MM
+ 268454437U, // C_F_D32
+ 268454437U, // C_F_D32_MM
+ 268454437U, // C_F_D64
+ 268454437U, // C_F_D64_MM
+ 268458881U, // C_F_S
+ 268458881U, // C_F_S_MM
+ 268454280U, // C_LE_D32
+ 268454280U, // C_LE_D32_MM
+ 268454280U, // C_LE_D64
+ 268454280U, // C_LE_D64_MM
+ 268458801U, // C_LE_S
+ 268458801U, // C_LE_S_MM
+ 268455366U, // C_LT_D32
+ 268455366U, // C_LT_D32_MM
+ 268455366U, // C_LT_D64
+ 268455366U, // C_LT_D64_MM
+ 268459179U, // C_LT_S
+ 268459179U, // C_LT_S_MM
+ 268454271U, // C_NGE_D32
+ 268454271U, // C_NGE_D32_MM
+ 268454271U, // C_NGE_D64
+ 268454271U, // C_NGE_D64_MM
+ 268458792U, // C_NGE_S
+ 268458792U, // C_NGE_S_MM
+ 268454306U, // C_NGLE_D32
+ 268454306U, // C_NGLE_D32_MM
+ 268454306U, // C_NGLE_D64
+ 268454306U, // C_NGLE_D64_MM
+ 268458819U, // C_NGLE_S
+ 268458819U, // C_NGLE_S_MM
+ 268454723U, // C_NGL_D32
+ 268454723U, // C_NGL_D32_MM
+ 268454723U, // C_NGL_D64
+ 268454723U, // C_NGL_D64_MM
+ 268459015U, // C_NGL_S
+ 268459015U, // C_NGL_S_MM
+ 268455357U, // C_NGT_D32
+ 268455357U, // C_NGT_D32_MM
+ 268455357U, // C_NGT_D64
+ 268455357U, // C_NGT_D64_MM
+ 268459170U, // C_NGT_S
+ 268459170U, // C_NGT_S_MM
+ 268454316U, // C_OLE_D32
+ 268454316U, // C_OLE_D32_MM
+ 268454316U, // C_OLE_D64
+ 268454316U, // C_OLE_D64_MM
+ 268458829U, // C_OLE_S
+ 268458829U, // C_OLE_S_MM
+ 268455392U, // C_OLT_D32
+ 268455392U, // C_OLT_D32_MM
+ 268455392U, // C_OLT_D64
+ 268455392U, // C_OLT_D64_MM
+ 268459197U, // C_OLT_S
+ 268459197U, // C_OLT_S_MM
+ 268454901U, // C_SEQ_D32
+ 268454901U, // C_SEQ_D32_MM
+ 268454901U, // C_SEQ_D64
+ 268454901U, // C_SEQ_D64_MM
+ 268459102U, // C_SEQ_S
+ 268459102U, // C_SEQ_S_MM
+ 268454507U, // C_SF_D32
+ 268454507U, // C_SF_D32_MM
+ 268454507U, // C_SF_D64
+ 268454507U, // C_SF_D64_MM
+ 268458927U, // C_SF_S
+ 268458927U, // C_SF_S_MM
+ 268454929U, // C_UEQ_D32
+ 268454929U, // C_UEQ_D32_MM
+ 268454929U, // C_UEQ_D64
+ 268454929U, // C_UEQ_D64_MM
+ 268459122U, // C_UEQ_S
+ 268459122U, // C_UEQ_S_MM
+ 268454344U, // C_ULE_D32
+ 268454344U, // C_ULE_D32_MM
+ 268454344U, // C_ULE_D64
+ 268454344U, // C_ULE_D64_MM
+ 268458849U, // C_ULE_S
+ 268458849U, // C_ULE_S_MM
+ 268455420U, // C_ULT_D32
+ 268455420U, // C_ULT_D32_MM
+ 268455420U, // C_ULT_D64
+ 268455420U, // C_ULT_D64_MM
+ 268459217U, // C_ULT_S
+ 268459217U, // C_ULT_S_MM
+ 268454805U, // C_UN_D32
+ 268454805U, // C_UN_D32_MM
+ 268454805U, // C_UN_D64
+ 268454805U, // C_UN_D64_MM
+ 268459038U, // C_UN_S
+ 268459038U, // C_UN_S_MM
+ 22945U, // CmpRxRy16
+ 2952812404U, // CmpiRxImm16
+ 22388U, // CmpiRxImmX16
+ 268455962U, // DADD
+ 268457776U, // DADDi
+ 268459586U, // DADDiu
+ 268459534U, // DADDu
+ 268457807U, // DAHI
+ 268458315U, // DALIGN
+ 268457868U, // DATI
+ 268457886U, // DAUI
+ 22905U, // DBITSWAP
+ 22873U, // DCLO
+ 22873U, // DCLO_R6
+ 26152U, // DCLZ
+ 26152U, // DCLZ_R6
+ 268459790U, // DDIV
+ 268459698U, // DDIVU
+ 10398U, // DERET
+ 10398U, // DERET_MM
+ 10398U, // DERET_MMR6
+ 268459502U, // DEXT
+ 268461849U, // DEXT64_32
+ 268458290U, // DEXTM
+ 268459691U, // DEXTU
+ 284467U, // DI
+ 268459410U, // DINS
+ 268458283U, // DINSM
+ 268459652U, // DINSU
+ 268459791U, // DIV
+ 268459699U, // DIVU
+ 268459699U, // DIVU_MMR6
+ 268459791U, // DIV_MMR6
+ 268453106U, // DIV_S_B
+ 268455295U, // DIV_S_D
+ 268456808U, // DIV_S_H
+ 268460991U, // DIV_S_W
+ 268453321U, // DIV_U_B
+ 268455762U, // DIV_U_D
+ 268457086U, // DIV_U_H
+ 268461409U, // DIV_U_W
+ 284467U, // DI_MM
+ 284467U, // DI_MMR6
+ 268452558U, // DLSA
+ 268452558U, // DLSA_R6
+ 268451841U, // DMFC0
+ 16488U, // DMFC1
+ 268452160U, // DMFC2
+ 92291392U, // DMFC2_OCTEON
+ 268451848U, // DMFGC0
+ 268456014U, // DMOD
+ 268459548U, // DMODU
+ 286162U, // DMT
+ 1376288822U, // DMTC0
+ 8945795U, // DMTC1
+ 1376289115U, // DMTC2
+ 92291419U, // DMTC2_OCTEON
+ 1376288800U, // DMTGC0
+ 268457763U, // DMUH
+ 268459579U, // DMUHU
+ 268458219U, // DMUL
+ 24011U, // DMULT
+ 24227U, // DMULTu
+ 268459623U, // DMULU
+ 268458219U, // DMUL_R6
+ 268455203U, // DOTP_S_D
+ 268456728U, // DOTP_S_H
+ 268460859U, // DOTP_S_W
+ 268455670U, // DOTP_U_D
+ 268457016U, // DOTP_U_H
+ 268461317U, // DOTP_U_W
+ 285232332U, // DPADD_S_D
+ 285233857U, // DPADD_S_H
+ 285237978U, // DPADD_S_W
+ 285232799U, // DPADD_U_D
+ 285234145U, // DPADD_U_H
+ 285238446U, // DPADD_U_W
+ 268457615U, // DPAQX_SA_W_PH
+ 268457615U, // DPAQX_SA_W_PH_MMR2
+ 268457698U, // DPAQX_S_W_PH
+ 268457698U, // DPAQX_S_W_PH_MMR2
+ 268460319U, // DPAQ_SA_L_W
+ 268460319U, // DPAQ_SA_L_W_MM
+ 268457657U, // DPAQ_S_W_PH
+ 268457657U, // DPAQ_S_W_PH_MM
+ 268457964U, // DPAU_H_QBL
+ 268457964U, // DPAU_H_QBL_MM
+ 268458534U, // DPAU_H_QBR
+ 268458534U, // DPAU_H_QBR_MM
+ 268457736U, // DPAX_W_PH
+ 268457736U, // DPAX_W_PH_MMR2
+ 268457605U, // DPA_W_PH
+ 268457605U, // DPA_W_PH_MMR2
+ 22950U, // DPOP
+ 268457630U, // DPSQX_SA_W_PH
+ 268457630U, // DPSQX_SA_W_PH_MMR2
+ 268457712U, // DPSQX_S_W_PH
+ 268457712U, // DPSQX_S_W_PH_MMR2
+ 268460332U, // DPSQ_SA_L_W
+ 268460332U, // DPSQ_SA_L_W_MM
+ 268457685U, // DPSQ_S_W_PH
+ 268457685U, // DPSQ_S_W_PH_MM
+ 285232299U, // DPSUB_S_D
+ 285233836U, // DPSUB_S_H
+ 285237945U, // DPSUB_S_W
+ 285232766U, // DPSUB_U_D
+ 285234124U, // DPSUB_U_H
+ 285238413U, // DPSUB_U_W
+ 268457976U, // DPSU_H_QBL
+ 268457976U, // DPSU_H_QBL_MM
+ 268458546U, // DPSU_H_QBR
+ 268458546U, // DPSU_H_QBR_MM
+ 268457747U, // DPSX_W_PH
+ 268457747U, // DPSX_W_PH_MMR2
+ 268457726U, // DPS_W_PH
+ 268457726U, // DPS_W_PH_MMR2
+ 268458719U, // DROTR
+ 268452117U, // DROTR32
+ 268459834U, // DROTRV
+ 21723U, // DSBH
+ 26223U, // DSDIV
+ 20518U, // DSHD
+ 268458162U, // DSLL
+ 268452087U, // DSLL32
+ 3221248178U, // DSLL64_32
+ 268459796U, // DSLLV
+ 268452552U, // DSRA
+ 268452069U, // DSRA32
+ 268459775U, // DSRAV
+ 268458180U, // DSRL
+ 268452095U, // DSRL32
+ 268459803U, // DSRLV
+ 268453796U, // DSUB
+ 268459513U, // DSUBu
+ 26209U, // DUDIV
+ 285187U, // DVP
+ 282806U, // DVPE
+ 285187U, // DVP_MMR6
+ 26224U, // DivRxRy16
+ 26210U, // DivuRxRy16
+ 10292U, // EHB
+ 10292U, // EHB_MM
+ 10292U, // EHB_MMR6
+ 284479U, // EI
+ 284479U, // EI_MM
+ 284479U, // EI_MMR6
+ 286167U, // EMT
+ 10399U, // ERET
+ 10296U, // ERETNC
+ 10296U, // ERETNC_MMR6
+ 10399U, // ERET_MM
+ 10399U, // ERET_MMR6
+ 285192U, // EVP
+ 282812U, // EVPE
+ 285192U, // EVP_MMR6
+ 268459503U, // EXT
+ 268458493U, // EXTP
+ 268458378U, // EXTPDP
+ 268459818U, // EXTPDPV
+ 268459818U, // EXTPDPV_MM
+ 268458378U, // EXTPDP_MM
+ 268459827U, // EXTPV
+ 268459827U, // EXTPV_MM
+ 268458493U, // EXTP_MM
+ 268461052U, // EXTRV_RS_W
+ 268461052U, // EXTRV_RS_W_MM
+ 268460606U, // EXTRV_R_W
+ 268460606U, // EXTRV_R_W_MM
+ 268456817U, // EXTRV_S_H
+ 268456817U, // EXTRV_S_H_MM
+ 268461489U, // EXTRV_W
+ 268461489U, // EXTRV_W_MM
+ 268461041U, // EXTR_RS_W
+ 268461041U, // EXTR_RS_W_MM
+ 268460585U, // EXTR_R_W
+ 268460585U, // EXTR_R_W_MM
+ 268456748U, // EXTR_S_H
+ 268456748U, // EXTR_S_H_MM
+ 268460684U, // EXTR_W
+ 268460684U, // EXTR_W_MM
+ 268459423U, // EXTS
+ 268452134U, // EXTS32
+ 268459503U, // EXT_MM
+ 268459503U, // EXT_MMR6
+ 19867U, // FABS_D32
+ 19867U, // FABS_D32_MM
+ 19867U, // FABS_D64
+ 19867U, // FABS_D64_MM
+ 23698U, // FABS_S
+ 23698U, // FABS_S_MM
+ 268454220U, // FADD_D
+ 268454221U, // FADD_D32
+ 268454221U, // FADD_D32_MM
+ 268454221U, // FADD_D64
+ 268454221U, // FADD_D64_MM
+ 268458785U, // FADD_S
+ 268458785U, // FADD_S_MM
+ 285236001U, // FADD_S_MMR6
+ 268459954U, // FADD_W
+ 268454454U, // FCAF_D
+ 268460073U, // FCAF_W
+ 268454893U, // FCEQ_D
+ 268460512U, // FCEQ_W
+ 19874U, // FCLASS_D
+ 25608U, // FCLASS_W
+ 268454298U, // FCLE_D
+ 268459996U, // FCLE_W
+ 268455384U, // FCLT_D
+ 268461091U, // FCLT_W
+ 3303278U, // FCMP_D32
+ 3303278U, // FCMP_D32_MM
+ 3303278U, // FCMP_D64
+ 3565422U, // FCMP_S32
+ 3565422U, // FCMP_S32_MM
+ 268454394U, // FCNE_D
+ 268460030U, // FCNE_W
+ 268455003U, // FCOR_D
+ 268460641U, // FCOR_W
+ 268454949U, // FCUEQ_D
+ 268460528U, // FCUEQ_W
+ 268454364U, // FCULE_D
+ 268460012U, // FCULE_W
+ 268455440U, // FCULT_D
+ 268461107U, // FCULT_W
+ 268454410U, // FCUNE_D
+ 268460046U, // FCUNE_W
+ 268454823U, // FCUN_D
+ 268460418U, // FCUN_W
+ 268455816U, // FDIV_D
+ 268455817U, // FDIV_D32
+ 268455817U, // FDIV_D32_MM
+ 268455817U, // FDIV_D64
+ 268455817U, // FDIV_D64_MM
+ 268459274U, // FDIV_S
+ 268459274U, // FDIV_S_MM
+ 285236490U, // FDIV_S_MMR6
+ 268461473U, // FDIV_W
+ 268456475U, // FEXDO_H
+ 268460434U, // FEXDO_W
+ 268454107U, // FEXP2_D
+ 268459857U, // FEXP2_W
+ 19291U, // FEXUPL_D
+ 24904U, // FEXUPL_W
+ 19563U, // FEXUPR_D
+ 25201U, // FEXUPR_W
+ 19805U, // FFINT_S_D
+ 25501U, // FFINT_S_W
+ 20284U, // FFINT_U_D
+ 25931U, // FFINT_U_W
+ 19301U, // FFQL_D
+ 24914U, // FFQL_W
+ 19573U, // FFQR_D
+ 25211U, // FFQR_W
+ 17417U, // FILL_B
+ 19276U, // FILL_D
+ 20980U, // FILL_H
+ 24889U, // FILL_W
+ 18642U, // FLOG2_D
+ 24392U, // FLOG2_W
+ 19240U, // FLOOR_L_D64
+ 19240U, // FLOOR_L_D_MMR6
+ 23532U, // FLOOR_L_S
+ 23532U, // FLOOR_L_S_MMR6
+ 20415U, // FLOOR_W_D32
+ 20415U, // FLOOR_W_D64
+ 20415U, // FLOOR_W_D_MMR6
+ 20415U, // FLOOR_W_MM
+ 23864U, // FLOOR_W_S
+ 23864U, // FLOOR_W_S_MM
+ 23864U, // FLOOR_W_S_MMR6
+ 285231444U, // FMADD_D
+ 285237178U, // FMADD_W
+ 268454145U, // FMAX_A_D
+ 268459895U, // FMAX_A_W
+ 268455891U, // FMAX_D
+ 268461498U, // FMAX_W
+ 268454125U, // FMIN_A_D
+ 268459875U, // FMIN_A_W
+ 268454797U, // FMIN_D
+ 268460410U, // FMIN_W
+ 20376U, // FMOV_D32
+ 20376U, // FMOV_D32_MM
+ 20376U, // FMOV_D64
+ 20376U, // FMOV_D64_MM
+ 23825U, // FMOV_S
+ 23825U, // FMOV_S_MM
+ 23825U, // FMOV_S_MMR6
+ 285231402U, // FMSUB_D
+ 285237136U, // FMSUB_W
+ 268454781U, // FMUL_D
+ 268454782U, // FMUL_D32
+ 268454782U, // FMUL_D32_MM
+ 268454782U, // FMUL_D64
+ 268454782U, // FMUL_D64_MM
+ 268459024U, // FMUL_S
+ 268459024U, // FMUL_S_MM
+ 285236240U, // FMUL_S_MMR6
+ 268460394U, // FMUL_W
+ 19068U, // FNEG_D32
+ 19068U, // FNEG_D32_MM
+ 19068U, // FNEG_D64
+ 19068U, // FNEG_D64_MM
+ 23487U, // FNEG_S
+ 23487U, // FNEG_S_MM
+ 23487U, // FNEG_S_MMR6
+ 3523778490U, // FORK
+ 19402U, // FRCP_D
+ 24987U, // FRCP_W
+ 20022U, // FRINT_D
+ 25677U, // FRINT_W
+ 20050U, // FRSQRT_D
+ 25705U, // FRSQRT_W
+ 268454473U, // FSAF_D
+ 268460081U, // FSAF_W
+ 268454921U, // FSEQ_D
+ 268460520U, // FSEQ_W
+ 268454336U, // FSLE_D
+ 268460004U, // FSLE_W
+ 268455412U, // FSLT_D
+ 268461099U, // FSLT_W
+ 268454402U, // FSNE_D
+ 268460038U, // FSNE_W
+ 268455011U, // FSOR_D
+ 268460649U, // FSOR_W
+ 20041U, // FSQRT_D
+ 20042U, // FSQRT_D32
+ 20042U, // FSQRT_D32_MM
+ 20042U, // FSQRT_D64
+ 20042U, // FSQRT_D64_MM
+ 23802U, // FSQRT_S
+ 23802U, // FSQRT_S_MM
+ 25696U, // FSQRT_W
+ 268454178U, // FSUB_D
+ 268454179U, // FSUB_D32
+ 268454179U, // FSUB_D32_MM
+ 268454179U, // FSUB_D64
+ 268454179U, // FSUB_D64_MM
+ 268458767U, // FSUB_S
+ 268458767U, // FSUB_S_MM
+ 285235983U, // FSUB_S_MMR6
+ 268459912U, // FSUB_W
+ 268454970U, // FSUEQ_D
+ 268460537U, // FSUEQ_W
+ 268454385U, // FSULE_D
+ 268460021U, // FSULE_W
+ 268455461U, // FSULT_D
+ 268461116U, // FSULT_W
+ 268454419U, // FSUNE_D
+ 268460055U, // FSUNE_W
+ 268454842U, // FSUN_D
+ 268460426U, // FSUN_W
+ 19816U, // FTINT_S_D
+ 25512U, // FTINT_S_W
+ 20295U, // FTINT_U_D
+ 25942U, // FTINT_U_W
+ 268456552U, // FTQ_H
+ 268460546U, // FTQ_W
+ 19638U, // FTRUNC_S_D
+ 25284U, // FTRUNC_S_W
+ 20105U, // FTRUNC_U_D
+ 25752U, // FTRUNC_U_W
+ 284585U, // GINVI
+ 284585U, // GINVI_MMR6
+ 100687329U, // GINVT
+ 100687329U, // GINVT_MMR6
+ 268455106U, // HADD_S_D
+ 268456631U, // HADD_S_H
+ 268460752U, // HADD_S_W
+ 268455573U, // HADD_U_D
+ 268456919U, // HADD_U_H
+ 268461220U, // HADD_U_W
+ 268455073U, // HSUB_S_D
+ 268456610U, // HSUB_S_H
+ 268460719U, // HSUB_S_W
+ 268455540U, // HSUB_U_D
+ 268456898U, // HSUB_U_H
+ 268461187U, // HSUB_U_W
+ 366734U, // HYPCALL
+ 366734U, // HYPCALL_MM
+ 268453376U, // ILVEV_B
+ 268455807U, // ILVEV_D
+ 268457141U, // ILVEV_H
+ 268461464U, // ILVEV_W
+ 268452904U, // ILVL_B
+ 268454789U, // ILVL_D
+ 268456467U, // ILVL_H
+ 268460402U, // ILVL_W
+ 268452656U, // ILVOD_B
+ 268454262U, // ILVOD_D
+ 268456269U, // ILVOD_H
+ 268459987U, // ILVOD_W
+ 268452952U, // ILVR_B
+ 268455046U, // ILVR_D
+ 268456592U, // ILVR_H
+ 268460692U, // ILVR_W
+ 268459405U, // INS
+ 112739623U, // INSERT_B
+ 121130559U, // INSERT_D
+ 129520552U, // INSERT_H
+ 137913430U, // INSERT_W
+ 16801602U, // INSV
+ 146293561U, // INSVE_B
+ 154683932U, // INSVE_D
+ 163074390U, // INSVE_H
+ 171466784U, // INSVE_W
+ 16801602U, // INSV_MM
+ 268459405U, // INS_MM
+ 268459405U, // INS_MMR6
+ 284592U, // J
+ 284631U, // JAL
+ 23219U, // JALR
+ 285363U, // JALR16_MM
+ 23219U, // JALR64
+ 285363U, // JALRC16_MMR6
+ 17972U, // JALRC_HB_MMR6
+ 18511U, // JALRC_MMR6
+ 279095U, // JALRS16_MM
+ 23960U, // JALRS_MM
+ 17989U, // JALR_HB
+ 17989U, // JALR_HB64
+ 23219U, // JALR_MM
+ 286068U, // JALS_MM
+ 288246U, // JALX
+ 288246U, // JALX_MM
+ 284631U, // JAL_MM
+ 18390U, // JIALC
+ 18390U, // JIALC64
+ 18390U, // JIALC_MMR6
+ 18379U, // JIC
+ 18379U, // JIC64
+ 18379U, // JIC_MMR6
+ 285359U, // JR
+ 279082U, // JR16_MM
+ 285359U, // JR64
+ 285170U, // JRADDIUSP
+ 280650U, // JRC16_MM
+ 278960U, // JRC16_MMR6
+ 285158U, // JRCADDIUSP_MMR6
+ 280126U, // JR_HB
+ 280126U, // JR_HB64
+ 280126U, // JR_HB64_R6
+ 280126U, // JR_HB_R6
+ 285359U, // JR_MM
+ 284592U, // J_MM
+ 4102103U, // Jal16
+ 4364247U, // JalB16
+ 10285U, // JrRa16
+ 10277U, // JrcRa16
+ 280650U, // JrcRx16
+ 280655U, // JumpLinkReg16
+ 25183822U, // LB
+ 25183822U, // LB64
+ 25186392U, // LBE
+ 25186392U, // LBE_MM
+ 25182791U, // LBU16_MM
+ 3774899708U, // LBUX
+ 3774899708U, // LBUX_MM
+ 25189876U, // LBU_MMR6
+ 25183822U, // LB_MM
+ 25183822U, // LB_MMR6
+ 25189876U, // LBu
+ 25189876U, // LBu64
+ 25186510U, // LBuE
+ 25186510U, // LBuE_MM
+ 25189876U, // LBu_MM
+ 25186351U, // LD
+ 25182294U, // LDC1
+ 25182294U, // LDC164
+ 25182294U, // LDC1_D64_MMR6
+ 25182294U, // LDC1_MM
+ 25182510U, // LDC2
+ 25182510U, // LDC2_MMR6
+ 25182510U, // LDC2_R6
+ 25182595U, // LDC3
+ 17243U, // LDI_B
+ 19084U, // LDI_D
+ 20856U, // LDI_H
+ 24739U, // LDI_W
+ 25188403U, // LDL
+ 18457U, // LDPC
+ 25188973U, // LDR
+ 3774890134U, // LDXC1
+ 3774890134U, // LDXC164
+ 25183009U, // LD_B
+ 25184615U, // LD_D
+ 25186622U, // LD_H
+ 25190340U, // LD_W
+ 67132995U, // LEA_ADDiu
+ 67132994U, // LEA_ADDiu64
+ 67132995U, // LEA_ADDiu_MM
+ 25187574U, // LH
+ 25187574U, // LH64
+ 25186439U, // LHE
+ 25186439U, // LHE_MM
+ 25182814U, // LHU16_MM
+ 3774899697U, // LHX
+ 3774899697U, // LHX_MM
+ 25187574U, // LH_MM
+ 25189942U, // LHu
+ 25189942U, // LHu64
+ 25186516U, // LHuE
+ 25186516U, // LHuE_MM
+ 25189942U, // LHu_MM
+ 16878U, // LI16_MM
+ 16878U, // LI16_MMR6
+ 25188499U, // LL
+ 25188499U, // LL64
+ 25188499U, // LL64_R6
+ 25186355U, // LLD
+ 25186355U, // LLD_R6
+ 25186454U, // LLE
+ 25186454U, // LLE_MM
+ 25188499U, // LL_MM
+ 25188499U, // LL_MMR6
+ 25188499U, // LL_R6
+ 268452559U, // LSA
+ 4062003919U, // LSA_MMR6
+ 268452559U, // LSA_R6
+ 92297124U, // LUI_MMR6
+ 3774890148U, // LUXC1
+ 3774890148U, // LUXC164
+ 3774890148U, // LUXC1_MM
+ 92297124U, // LUi
+ 92297124U, // LUi64
+ 92297124U, // LUi_MM
+ 25191905U, // LW
+ 25182821U, // LW16_MM
+ 25191905U, // LW64
+ 25182346U, // LWC1
+ 25182346U, // LWC1_MM
+ 25182562U, // LWC2
+ 25182562U, // LWC2_MMR6
+ 25182562U, // LWC2_R6
+ 25182607U, // LWC3
+ 25191905U, // LWDSP
+ 25191905U, // LWDSP_MM
+ 25186528U, // LWE
+ 25186528U, // LWE_MM
+ 25191905U, // LWGP_MM
+ 25188607U, // LWL
+ 25188607U, // LWL64
+ 25186459U, // LWLE
+ 25186459U, // LWLE_MM
+ 25188607U, // LWL_MM
+ 836107U, // LWM16_MM
+ 836107U, // LWM16_MMR6
+ 835847U, // LWM32_MM
+ 18494U, // LWPC
+ 18494U, // LWPC_MMR6
+ 176183821U, // LWP_MM
+ 25189107U, // LWR
+ 25189107U, // LWR64
+ 25186498U, // LWRE
+ 25186498U, // LWRE_MM
+ 25189107U, // LWR_MM
+ 25191905U, // LWSP_MM
+ 18487U, // LWUPC
+ 25190073U, // LWU_MM
+ 3774899714U, // LWX
+ 3774890162U, // LWXC1
+ 3774890162U, // LWXC1_MM
+ 3774897573U, // LWXS_MM
+ 3774899714U, // LWX_MM
+ 25191905U, // LW_MM
+ 25191905U, // LW_MMR6
+ 25190073U, // LWu
+ 25183822U, // LbRxRyOffMemX16
+ 25189876U, // LbuRxRyOffMemX16
+ 25187574U, // LhRxRyOffMemX16
+ 25189942U, // LhuRxRyOffMemX16
+ 2952812395U, // LiRxImm16
+ 22369U, // LiRxImmAlignX16
+ 22379U, // LiRxImmX16
+ 2147509729U, // LwRxPcTcp16
+ 26081U, // LwRxPcTcpX16
+ 25191905U, // LwRxRyOffMemX16
+ 25191905U, // LwRxSpImmX16
+ 20512U, // MADD
+ 285231706U, // MADDF_D
+ 285231706U, // MADDF_D_MMR6
+ 285236134U, // MADDF_S
+ 285236134U, // MADDF_S_MMR6
+ 285233740U, // MADDR_Q_H
+ 285237707U, // MADDR_Q_W
+ 24085U, // MADDU
+ 268459541U, // MADDU_DSP
+ 268459541U, // MADDU_DSP_MM
+ 24085U, // MADDU_MM
+ 285230574U, // MADDV_B
+ 285233005U, // MADDV_D
+ 285234339U, // MADDV_H
+ 285238662U, // MADDV_W
+ 268454229U, // MADD_D32
+ 268454229U, // MADD_D32_MM
+ 268454229U, // MADD_D64
+ 268455968U, // MADD_DSP
+ 268455968U, // MADD_DSP_MM
+ 20512U, // MADD_MM
+ 285233710U, // MADD_Q_H
+ 285237677U, // MADD_Q_W
+ 268458784U, // MADD_S
+ 268458784U, // MADD_S_MM
+ 268458070U, // MAQ_SA_W_PHL
+ 268458070U, // MAQ_SA_W_PHL_MM
+ 268458615U, // MAQ_SA_W_PHR
+ 268458615U, // MAQ_SA_W_PHR_MM
+ 268458098U, // MAQ_S_W_PHL
+ 268458098U, // MAQ_S_W_PHL_MM
+ 268458643U, // MAQ_S_W_PHR
+ 268458643U, // MAQ_S_W_PHR_MM
+ 268454170U, // MAXA_D
+ 268454170U, // MAXA_D_MMR6
+ 268458757U, // MAXA_S
+ 268458757U, // MAXA_S_MMR6
+ 268453027U, // MAXI_S_B
+ 268455184U, // MAXI_S_D
+ 268456709U, // MAXI_S_H
+ 268460830U, // MAXI_S_W
+ 268453242U, // MAXI_U_B
+ 268455651U, // MAXI_U_D
+ 268456997U, // MAXI_U_H
+ 268461298U, // MAXI_U_W
+ 268452608U, // MAX_A_B
+ 268454146U, // MAX_A_D
+ 268456221U, // MAX_A_H
+ 268459896U, // MAX_A_W
+ 268455892U, // MAX_D
+ 268455892U, // MAX_D_MMR6
+ 268459340U, // MAX_S
+ 268453115U, // MAX_S_B
+ 268455304U, // MAX_S_D
+ 268456828U, // MAX_S_H
+ 268459340U, // MAX_S_MMR6
+ 268461011U, // MAX_S_W
+ 268453330U, // MAX_U_B
+ 268455771U, // MAX_U_D
+ 268457095U, // MAX_U_H
+ 268461418U, // MAX_U_W
+ 268451842U, // MFC0
+ 268451842U, // MFC0_MMR6
+ 16489U, // MFC1
+ 16489U, // MFC1_D64
+ 16489U, // MFC1_MM
+ 16489U, // MFC1_MMR6
+ 268452161U, // MFC2
+ 16705U, // MFC2_MMR6
+ 268451849U, // MFGC0
+ 268451849U, // MFGC0_MM
+ 268451880U, // MFHC0_MMR6
+ 16495U, // MFHC1_D32
+ 16495U, // MFHC1_D32_MM
+ 16495U, // MFHC1_D64
+ 16495U, // MFHC1_D64_MM
+ 16711U, // MFHC2_MMR6
+ 268451856U, // MFHGC0
+ 268451856U, // MFHGC0_MM
+ 284501U, // MFHI
+ 279014U, // MFHI16_MM
+ 284501U, // MFHI64
+ 22357U, // MFHI_DSP
+ 22357U, // MFHI_DSP_MM
+ 284501U, // MFHI_MM
+ 285023U, // MFLO
+ 279065U, // MFLO16_MM
+ 285023U, // MFLO64
+ 22879U, // MFLO_DSP
+ 22879U, // MFLO_DSP_MM
+ 285023U, // MFLO_MM
+ 268458713U, // MFTR
+ 268454155U, // MINA_D
+ 268454155U, // MINA_D_MMR6
+ 268458749U, // MINA_S
+ 268458749U, // MINA_S_MMR6
+ 268453007U, // MINI_S_B
+ 268455164U, // MINI_S_D
+ 268456689U, // MINI_S_H
+ 268460810U, // MINI_S_W
+ 268453222U, // MINI_U_B
+ 268455631U, // MINI_U_D
+ 268456977U, // MINI_U_H
+ 268461278U, // MINI_U_W
+ 268452589U, // MIN_A_B
+ 268454126U, // MIN_A_D
+ 268456202U, // MIN_A_H
+ 268459876U, // MIN_A_W
+ 268454798U, // MIN_D
+ 268454798U, // MIN_D_MMR6
+ 268459031U, // MIN_S
+ 268453037U, // MIN_S_B
+ 268455194U, // MIN_S_D
+ 268456719U, // MIN_S_H
+ 268459031U, // MIN_S_MMR6
+ 268460850U, // MIN_S_W
+ 268453252U, // MIN_U_B
+ 268455661U, // MIN_U_D
+ 268457007U, // MIN_U_H
+ 268461308U, // MIN_U_W
+ 268456015U, // MOD
+ 268453794U, // MODSUB
+ 268453794U, // MODSUB_MM
+ 268459549U, // MODU
+ 268459549U, // MODU_MMR6
+ 268456015U, // MOD_MMR6
+ 268452970U, // MOD_S_B
+ 268455127U, // MOD_S_D
+ 268456652U, // MOD_S_H
+ 268460773U, // MOD_S_W
+ 268453185U, // MOD_U_B
+ 268455594U, // MOD_U_D
+ 268456940U, // MOD_U_H
+ 268461241U, // MOD_U_W
+ 20698U, // MOVE16_MM
+ 16848U, // MOVE16_MMR6
+ 34920850U, // MOVEP_MM
+ 34920850U, // MOVEP_MMR6
+ 24261U, // MOVE_V
+ 268454515U, // MOVF_D32
+ 268454515U, // MOVF_D32_MM
+ 268454515U, // MOVF_D64
+ 268456182U, // MOVF_I
+ 268456182U, // MOVF_I64
+ 268456182U, // MOVF_I_MM
+ 268458935U, // MOVF_S
+ 268458935U, // MOVF_S_MM
+ 268454850U, // MOVN_I64_D64
+ 268458323U, // MOVN_I64_I
+ 268458323U, // MOVN_I64_I64
+ 268459067U, // MOVN_I64_S
+ 268454850U, // MOVN_I_D32
+ 268454850U, // MOVN_I_D32_MM
+ 268454850U, // MOVN_I_D64
+ 268458323U, // MOVN_I_I
+ 268458323U, // MOVN_I_I64
+ 268458323U, // MOVN_I_MM
+ 268459067U, // MOVN_I_S
+ 268459067U, // MOVN_I_S_MM
+ 268455522U, // MOVT_D32
+ 268455522U, // MOVT_D32_MM
+ 268455522U, // MOVT_D64
+ 268459496U, // MOVT_I
+ 268459496U, // MOVT_I64
+ 268459496U, // MOVT_I_MM
+ 268459266U, // MOVT_S
+ 268459266U, // MOVT_S_MM
+ 268455932U, // MOVZ_I64_D64
+ 268461647U, // MOVZ_I64_I
+ 268461647U, // MOVZ_I64_I64
+ 268459367U, // MOVZ_I64_S
+ 268455932U, // MOVZ_I_D32
+ 268455932U, // MOVZ_I_D32_MM
+ 268455932U, // MOVZ_I_D64
+ 268461647U, // MOVZ_I_I
+ 268461647U, // MOVZ_I_I64
+ 268461647U, // MOVZ_I_MM
+ 268459367U, // MOVZ_I_S
+ 268459367U, // MOVZ_I_S_MM
+ 18346U, // MSUB
+ 285231697U, // MSUBF_D
+ 285231697U, // MSUBF_D_MMR6
+ 285236125U, // MSUBF_S
+ 285236125U, // MSUBF_S_MMR6
+ 285233729U, // MSUBR_Q_H
+ 285237696U, // MSUBR_Q_W
+ 24064U, // MSUBU
+ 268459520U, // MSUBU_DSP
+ 268459520U, // MSUBU_DSP_MM
+ 24064U, // MSUBU_MM
+ 285230565U, // MSUBV_B
+ 285232996U, // MSUBV_D
+ 285234330U, // MSUBV_H
+ 285238653U, // MSUBV_W
+ 268454187U, // MSUB_D32
+ 268454187U, // MSUB_D32_MM
+ 268454187U, // MSUB_D64
+ 268453802U, // MSUB_DSP
+ 268453802U, // MSUB_DSP_MM
+ 18346U, // MSUB_MM
+ 285233700U, // MSUB_Q_H
+ 285237667U, // MSUB_Q_W
+ 268458766U, // MSUB_S
+ 268458766U, // MSUB_S_MM
+ 1376288823U, // MTC0
+ 1376288823U, // MTC0_MMR6
+ 8945796U, // MTC1
+ 8945796U, // MTC1_D64
+ 8945796U, // MTC1_MM
+ 8945796U, // MTC1_MMR6
+ 1376289116U, // MTC2
+ 8946012U, // MTC2_MMR6
+ 1376288801U, // MTGC0
+ 1376288801U, // MTGC0_MM
+ 1376288815U, // MTHC0_MMR6
+ 8994934U, // MTHC1_D32
+ 8994934U, // MTHC1_D32_MM
+ 8994934U, // MTHC1_D64
+ 8994934U, // MTHC1_D64_MM
+ 8945998U, // MTHC2_MMR6
+ 1376288792U, // MTHGC0
+ 1376288792U, // MTHGC0_MM
+ 284507U, // MTHI
+ 284507U, // MTHI64
+ 8951643U, // MTHI_DSP
+ 8951643U, // MTHI_DSP_MM
+ 284507U, // MTHI_MM
+ 8952217U, // MTHLIP
+ 8952217U, // MTHLIP_MM
+ 285036U, // MTLO
+ 285036U, // MTLO64
+ 8952172U, // MTLO_DSP
+ 8952172U, // MTLO_DSP_MM
+ 285036U, // MTLO_MM
+ 278595U, // MTM0
+ 278720U, // MTM1
+ 278894U, // MTM2
+ 278601U, // MTP0
+ 278726U, // MTP1
+ 278900U, // MTP2
+ 302553830U, // MTTR
+ 268457764U, // MUH
+ 268459580U, // MUHU
+ 268459580U, // MUHU_MMR6
+ 268457764U, // MUH_MMR6
+ 268458220U, // MUL
+ 268458111U, // MULEQ_S_W_PHL
+ 268458111U, // MULEQ_S_W_PHL_MM
+ 268458656U, // MULEQ_S_W_PHR
+ 268458656U, // MULEQ_S_W_PHR_MM
+ 268457988U, // MULEU_S_PH_QBL
+ 268457988U, // MULEU_S_PH_QBL_MM
+ 268458558U, // MULEU_S_PH_QBR
+ 268458558U, // MULEU_S_PH_QBR_MM
+ 268457524U, // MULQ_RS_PH
+ 268457524U, // MULQ_RS_PH_MM
+ 268461030U, // MULQ_RS_W
+ 268461030U, // MULQ_RS_W_MMR2
+ 268457468U, // MULQ_S_PH
+ 268457468U, // MULQ_S_PH_MMR2
+ 268460889U, // MULQ_S_W
+ 268460889U, // MULQ_S_W_MMR2
+ 268456535U, // MULR_Q_H
+ 268460502U, // MULR_Q_W
+ 268457670U, // MULSAQ_S_W_PH
+ 268457670U, // MULSAQ_S_W_PH_MM
+ 268457645U, // MULSA_W_PH
+ 268457645U, // MULSA_W_PH_MMR2
+ 24012U, // MULT
+ 268459684U, // MULTU_DSP
+ 268459684U, // MULTU_DSP_MM
+ 268459468U, // MULT_DSP
+ 268459468U, // MULT_DSP_MM
+ 24012U, // MULT_MM
+ 24228U, // MULTu
+ 24228U, // MULTu_MM
+ 268459617U, // MULU
+ 268459617U, // MULU_MMR6
+ 268453385U, // MULV_B
+ 268455824U, // MULV_D
+ 268457150U, // MULV_H
+ 268461481U, // MULV_W
+ 268458220U, // MUL_MM
+ 268458220U, // MUL_MMR6
+ 268457341U, // MUL_PH
+ 268457341U, // MUL_PH_MMR2
+ 268456504U, // MUL_Q_H
+ 268460471U, // MUL_Q_W
+ 268458220U, // MUL_R6
+ 268457436U, // MUL_S_PH
+ 268457436U, // MUL_S_PH_MMR2
+ 284501U, // Mfhi16
+ 285023U, // Mflo16
+ 20698U, // Move32R16
+ 20698U, // MoveR3216
+ 17168U, // NLOC_B
+ 18748U, // NLOC_D
+ 20781U, // NLOC_H
+ 24473U, // NLOC_W
+ 17176U, // NLZC_B
+ 18756U, // NLZC_D
+ 20789U, // NLZC_H
+ 24481U, // NLZC_W
+ 268454237U, // NMADD_D32
+ 268454237U, // NMADD_D32_MM
+ 268454237U, // NMADD_D64
+ 268458783U, // NMADD_S
+ 268458783U, // NMADD_S_MM
+ 268454195U, // NMSUB_D32
+ 268454195U, // NMSUB_D32_MM
+ 268454195U, // NMSUB_D64
+ 268458765U, // NMSUB_S
+ 268458765U, // NMSUB_S_MM
+ 268458681U, // NOR
+ 268458681U, // NOR64
+ 268452793U, // NORI_B
+ 268458681U, // NOR_MM
+ 268458681U, // NOR_MMR6
+ 268459733U, // NOR_V
+ 16960U, // NOT16_MM
+ 16960U, // NOT16_MMR6
+ 20732U, // NegRxRy16
+ 24028U, // NotRxRy16
+ 268458682U, // OR
+ 10306097U, // OR16_MM
+ 10306097U, // OR16_MMR6
+ 268458682U, // OR64
+ 268452794U, // ORI_B
+ 268457863U, // ORI_MMR6
+ 268458682U, // OR_MM
+ 268458682U, // OR_MMR6
+ 268459734U, // OR_V
+ 268457863U, // ORi
+ 268457863U, // ORi64
+ 268457863U, // ORi_MM
+ 16800442U, // OrRxRxRy16
+ 268457330U, // PACKRL_PH
+ 268457330U, // PACKRL_PH_MM
+ 10303U, // PAUSE
+ 10303U, // PAUSE_MM
+ 10303U, // PAUSE_MMR6
+ 268453367U, // PCKEV_B
+ 268455798U, // PCKEV_D
+ 268457132U, // PCKEV_H
+ 268461455U, // PCKEV_W
+ 268452647U, // PCKOD_B
+ 268454253U, // PCKOD_D
+ 268456260U, // PCKOD_H
+ 268459978U, // PCKOD_W
+ 17695U, // PCNT_B
+ 20014U, // PCNT_D
+ 21408U, // PCNT_H
+ 25669U, // PCNT_W
+ 268457294U, // PICK_PH
+ 268457294U, // PICK_PH_MM
+ 268453526U, // PICK_QB
+ 268453526U, // PICK_QB_MM
+ 22951U, // POP
+ 22563U, // PRECEQU_PH_QBL
+ 17041U, // PRECEQU_PH_QBLA
+ 17041U, // PRECEQU_PH_QBLA_MM
+ 22563U, // PRECEQU_PH_QBL_MM
+ 23133U, // PRECEQU_PH_QBR
+ 17079U, // PRECEQU_PH_QBRA
+ 17079U, // PRECEQU_PH_QBRA_MM
+ 23133U, // PRECEQU_PH_QBR_MM
+ 22628U, // PRECEQ_W_PHL
+ 22628U, // PRECEQ_W_PHL_MM
+ 23173U, // PRECEQ_W_PHR
+ 23173U, // PRECEQ_W_PHR_MM
+ 22548U, // PRECEU_PH_QBL
+ 17025U, // PRECEU_PH_QBLA
+ 17025U, // PRECEU_PH_QBLA_MM
+ 22548U, // PRECEU_PH_QBL_MM
+ 23118U, // PRECEU_PH_QBR
+ 17063U, // PRECEU_PH_QBRA
+ 17063U, // PRECEU_PH_QBRA_MM
+ 23118U, // PRECEU_PH_QBR_MM
+ 268457246U, // PRECRQU_S_QB_PH
+ 268457246U, // PRECRQU_S_QB_PH_MM
+ 268460121U, // PRECRQ_PH_W
+ 268460121U, // PRECRQ_PH_W_MM
+ 268457219U, // PRECRQ_QB_PH
+ 268457219U, // PRECRQ_QB_PH_MM
+ 268460152U, // PRECRQ_RS_PH_W
+ 268460152U, // PRECRQ_RS_PH_W_MM
+ 268457233U, // PRECR_QB_PH
+ 268457233U, // PRECR_QB_PH_MMR2
+ 268460105U, // PRECR_SRA_PH_W
+ 268460105U, // PRECR_SRA_PH_W_MMR2
+ 268460134U, // PRECR_SRA_R_PH_W
+ 268460134U, // PRECR_SRA_R_PH_W_MMR2
+ 3018992U, // PREF
+ 3018863U, // PREFE
+ 3018863U, // PREFE_MM
+ 186525162U, // PREFX_MM
+ 3018992U, // PREF_MM
+ 3018992U, // PREF_MMR6
+ 3018992U, // PREF_R6
+ 268455997U, // PREPEND
+ 268455997U, // PREPEND_MMR2
+ 18322U, // RADDU_W_QB
+ 18322U, // RADDU_W_QB_MM
+ 83909080U, // RDDSP
+ 192960984U, // RDDSP_MM
+ 268458732U, // RDHWR
+ 268458732U, // RDHWR64
+ 268458732U, // RDHWR_MM
+ 268458732U, // RDHWR_MMR6
+ 23241U, // RDPGPR_MMR6
+ 19410U, // RECIP_D32
+ 19410U, // RECIP_D32_MM
+ 19410U, // RECIP_D64
+ 19410U, // RECIP_D64_MM
+ 23619U, // RECIP_S
+ 23619U, // RECIP_S_MM
+ 22129U, // REPLV_PH
+ 22129U, // REPLV_PH_MM
+ 18302U, // REPLV_QB
+ 18302U, // REPLV_QB_MM
+ 21856U, // REPL_PH
+ 21856U, // REPL_PH_MM
+ 201344680U, // REPL_QB
+ 201344680U, // REPL_QB_MM
+ 20023U, // RINT_D
+ 20023U, // RINT_D_MMR6
+ 23793U, // RINT_S
+ 23793U, // RINT_S_MMR6
+ 268458720U, // ROTR
+ 268459835U, // ROTRV
+ 268459835U, // ROTRV_MM
+ 268458720U, // ROTR_MM
+ 19219U, // ROUND_L_D64
+ 19219U, // ROUND_L_D_MMR6
+ 23511U, // ROUND_L_S
+ 23511U, // ROUND_L_S_MMR6
+ 20394U, // ROUND_W_D32
+ 20394U, // ROUND_W_D64
+ 20394U, // ROUND_W_D_MMR6
+ 20394U, // ROUND_W_MM
+ 23843U, // ROUND_W_S
+ 23843U, // ROUND_W_S_MM
+ 23843U, // ROUND_W_S_MMR6
+ 20051U, // RSQRT_D32
+ 20051U, // RSQRT_D32_MM
+ 20051U, // RSQRT_D64
+ 20051U, // RSQRT_D64_MM
+ 23801U, // RSQRT_S
+ 23801U, // RSQRT_S_MM
+ 0U, // Restore16
+ 0U, // RestoreX16
+ 268453076U, // SAT_S_B
+ 268455243U, // SAT_S_D
+ 268456778U, // SAT_S_H
+ 268460939U, // SAT_S_W
+ 268453303U, // SAT_U_B
+ 268455722U, // SAT_U_D
+ 268457068U, // SAT_U_H
+ 268461369U, // SAT_U_W
+ 25184158U, // SB
+ 25182628U, // SB16_MM
+ 25182628U, // SB16_MMR6
+ 25184158U, // SB64
+ 25186397U, // SBE
+ 25186397U, // SBE_MM
+ 25184158U, // SB_MM
+ 25184158U, // SB_MMR6
+ 4491353U, // SC
+ 4491353U, // SC64
+ 4491353U, // SC64_R6
+ 4493333U, // SCD
+ 4493333U, // SCD_R6
+ 4493410U, // SCE
+ 4493410U, // SCE_MM
+ 4491353U, // SC_MM
+ 4491353U, // SC_MMR6
+ 4491353U, // SC_R6
+ 25186388U, // SD
+ 186755U, // SDBBP
+ 115233U, // SDBBP16_MM
+ 115233U, // SDBBP16_MMR6
+ 366979U, // SDBBP_MM
+ 186755U, // SDBBP_MMR6
+ 186755U, // SDBBP_R6
+ 25182300U, // SDC1
+ 25182300U, // SDC164
+ 25182300U, // SDC1_D64_MMR6
+ 25182300U, // SDC1_MM
+ 25182516U, // SDC2
+ 25182516U, // SDC2_MMR6
+ 25182516U, // SDC2_R6
+ 25182601U, // SDC3
+ 26224U, // SDIV
+ 26224U, // SDIV_MM
+ 25188408U, // SDL
+ 25188978U, // SDR
+ 3774890141U, // SDXC1
+ 3774890141U, // SDXC164
+ 17967U, // SEB
+ 17967U, // SEB64
+ 17967U, // SEB_MM
+ 21744U, // SEH
+ 21744U, // SEH64
+ 21744U, // SEH_MM
+ 268461620U, // SELEQZ
+ 268461620U, // SELEQZ64
+ 268455922U, // SELEQZ_D
+ 268455922U, // SELEQZ_D_MMR6
+ 268461620U, // SELEQZ_MMR6
+ 268459357U, // SELEQZ_S
+ 268459357U, // SELEQZ_S_MMR6
+ 268461593U, // SELNEZ
+ 268461593U, // SELNEZ64
+ 268455905U, // SELNEZ_D
+ 268455905U, // SELNEZ_D_MMR6
+ 268461593U, // SELNEZ_MMR6
+ 268459347U, // SELNEZ_S
+ 268459347U, // SELNEZ_S_MMR6
+ 285231932U, // SEL_D
+ 285231932U, // SEL_D_MMR6
+ 285236224U, // SEL_S
+ 285236224U, // SEL_S_MMR6
+ 268458524U, // SEQ
+ 268457850U, // SEQi
+ 25188127U, // SH
+ 25182680U, // SH16_MM
+ 25182680U, // SH16_MMR6
+ 25188127U, // SH64
+ 25186444U, // SHE
+ 25186444U, // SHE_MM
+ 268452675U, // SHF_B
+ 268456288U, // SHF_H
+ 268460090U, // SHF_W
+ 22885U, // SHILO
+ 24354U, // SHILOV
+ 24354U, // SHILOV_MM
+ 22885U, // SHILO_MM
+ 268457575U, // SHLLV_PH
+ 268457575U, // SHLLV_PH_MM
+ 268453748U, // SHLLV_QB
+ 268453748U, // SHLLV_QB_MM
+ 268457512U, // SHLLV_S_PH
+ 268457512U, // SHLLV_S_PH_MM
+ 268461000U, // SHLLV_S_W
+ 268461000U, // SHLLV_S_W_MM
+ 268457303U, // SHLL_PH
+ 268457303U, // SHLL_PH_MM
+ 268453535U, // SHLL_QB
+ 268453535U, // SHLL_QB_MM
+ 268457425U, // SHLL_S_PH
+ 268457425U, // SHLL_S_PH_MM
+ 268460840U, // SHLL_S_W
+ 268460840U, // SHLL_S_W_MM
+ 268457565U, // SHRAV_PH
+ 268457565U, // SHRAV_PH_MM
+ 268453738U, // SHRAV_QB
+ 268453738U, // SHRAV_QB_MMR2
+ 268457413U, // SHRAV_R_PH
+ 268457413U, // SHRAV_R_PH_MM
+ 268453636U, // SHRAV_R_QB
+ 268453636U, // SHRAV_R_QB_MMR2
+ 268460595U, // SHRAV_R_W
+ 268460595U, // SHRAV_R_W_MM
+ 268457210U, // SHRA_PH
+ 268457210U, // SHRA_PH_MM
+ 268453458U, // SHRA_QB
+ 268453458U, // SHRA_QB_MMR2
+ 268457378U, // SHRA_R_PH
+ 268457378U, // SHRA_R_PH_MM
+ 268453601U, // SHRA_R_QB
+ 268453601U, // SHRA_R_QB_MMR2
+ 268460553U, // SHRA_R_W
+ 268460553U, // SHRA_R_W_MM
+ 268457595U, // SHRLV_PH
+ 268457595U, // SHRLV_PH_MMR2
+ 268453768U, // SHRLV_QB
+ 268453768U, // SHRLV_QB_MM
+ 268457321U, // SHRL_PH
+ 268457321U, // SHRL_PH_MMR2
+ 268453553U, // SHRL_QB
+ 268453553U, // SHRL_QB_MM
+ 25188127U, // SH_MM
+ 25188127U, // SH_MMR6
+ 2701149018U, // SLDI_B
+ 2701150859U, // SLDI_D
+ 2701152631U, // SLDI_H
+ 2701156514U, // SLDI_W
+ 2701148960U, // SLD_B
+ 2701150566U, // SLD_D
+ 2701152573U, // SLD_H
+ 2701156291U, // SLD_W
+ 268458163U, // SLL
+ 268452349U, // SLL16_MM
+ 268452349U, // SLL16_MMR6
+ 536893619U, // SLL64_32
+ 536893619U, // SLL64_64
+ 268452732U, // SLLI_B
+ 268454556U, // SLLI_D
+ 268456328U, // SLLI_H
+ 268460211U, // SLLI_W
+ 268459797U, // SLLV
+ 268459797U, // SLLV_MM
+ 268452881U, // SLL_B
+ 268454740U, // SLL_D
+ 268456444U, // SLL_H
+ 268458163U, // SLL_MM
+ 268458163U, // SLL_MMR6
+ 268460353U, // SLL_W
+ 268459457U, // SLT
+ 268459457U, // SLT64
+ 268459457U, // SLT_MM
+ 268457874U, // SLTi
+ 268457874U, // SLTi64
+ 268457874U, // SLTi_MM
+ 268459601U, // SLTiu
+ 268459601U, // SLTiu64
+ 268459601U, // SLTiu_MM
+ 268459671U, // SLTu
+ 268459671U, // SLTu64
+ 268459671U, // SLTu_MM
+ 268456108U, // SNE
+ 268457795U, // SNEi
+ 2684371923U, // SPLATI_B
+ 2684373731U, // SPLATI_D
+ 2684375503U, // SPLATI_H
+ 2684379386U, // SPLATI_W
+ 2684372238U, // SPLAT_B
+ 2684374444U, // SPLAT_D
+ 2684375951U, // SPLAT_H
+ 2684380178U, // SPLAT_W
+ 268452553U, // SRA
+ 268452690U, // SRAI_B
+ 268454531U, // SRAI_D
+ 268456303U, // SRAI_H
+ 268460186U, // SRAI_W
+ 268452766U, // SRARI_B
+ 268454590U, // SRARI_D
+ 268456362U, // SRARI_H
+ 268460245U, // SRARI_W
+ 268452919U, // SRAR_B
+ 268454979U, // SRAR_D
+ 268456559U, // SRAR_H
+ 268460617U, // SRAR_W
+ 268459776U, // SRAV
+ 268459776U, // SRAV_MM
+ 268452617U, // SRA_B
+ 268454163U, // SRA_D
+ 268456230U, // SRA_H
+ 268452553U, // SRA_MM
+ 268459905U, // SRA_W
+ 268458181U, // SRL
+ 268452356U, // SRL16_MM
+ 268452356U, // SRL16_MMR6
+ 268452740U, // SRLI_B
+ 268454564U, // SRLI_D
+ 268456336U, // SRLI_H
+ 268460219U, // SRLI_W
+ 268452784U, // SRLRI_B
+ 268454608U, // SRLRI_D
+ 268456380U, // SRLRI_H
+ 268460263U, // SRLRI_W
+ 268452935U, // SRLR_B
+ 268454995U, // SRLR_D
+ 268456575U, // SRLR_H
+ 268460633U, // SRLR_W
+ 268459804U, // SRLV
+ 268459804U, // SRLV_MM
+ 268452888U, // SRL_B
+ 268454765U, // SRL_D
+ 268456451U, // SRL_H
+ 268458181U, // SRL_MM
+ 268460378U, // SRL_W
+ 10368U, // SSNOP
+ 10368U, // SSNOP_MM
+ 10368U, // SSNOP_MMR6
+ 25183537U, // ST_B
+ 25185884U, // ST_D
+ 25187250U, // ST_H
+ 25191539U, // ST_W
+ 268453797U, // SUB
+ 268457274U, // SUBQH_PH
+ 268457274U, // SUBQH_PH_MMR2
+ 268457389U, // SUBQH_R_PH
+ 268457389U, // SUBQH_R_PH_MMR2
+ 268460563U, // SUBQH_R_W
+ 268460563U, // SUBQH_R_W_MMR2
+ 268460168U, // SUBQH_W
+ 268460168U, // SUBQH_W_MMR2
+ 268457349U, // SUBQ_PH
+ 268457349U, // SUBQ_PH_MM
+ 268457446U, // SUBQ_S_PH
+ 268457446U, // SUBQ_S_PH_MM
+ 268460869U, // SUBQ_S_W
+ 268460869U, // SUBQ_S_W_MM
+ 268453291U, // SUBSUS_U_B
+ 268455710U, // SUBSUS_U_D
+ 268457056U, // SUBSUS_U_H
+ 268461357U, // SUBSUS_U_W
+ 268453094U, // SUBSUU_S_B
+ 268455283U, // SUBSUU_S_D
+ 268456796U, // SUBSUU_S_H
+ 268460979U, // SUBSUU_S_W
+ 268453056U, // SUBS_S_B
+ 268455223U, // SUBS_S_D
+ 268456758U, // SUBS_S_H
+ 268460919U, // SUBS_S_W
+ 268453271U, // SUBS_U_B
+ 268455690U, // SUBS_U_D
+ 268457036U, // SUBS_U_H
+ 268461337U, // SUBS_U_W
+ 268452430U, // SUBU16_MM
+ 268452430U, // SUBU16_MMR6
+ 268453506U, // SUBUH_QB
+ 268453506U, // SUBUH_QB_MMR2
+ 268453612U, // SUBUH_R_QB
+ 268453612U, // SUBUH_R_QB_MMR2
+ 268459514U, // SUBU_MMR6
+ 268457547U, // SUBU_PH
+ 268457547U, // SUBU_PH_MMR2
+ 268453720U, // SUBU_QB
+ 268453720U, // SUBU_QB_MM
+ 268457490U, // SUBU_S_PH
+ 268457490U, // SUBU_S_PH_MMR2
+ 268453659U, // SUBU_S_QB
+ 268453659U, // SUBU_S_QB_MM
+ 268452838U, // SUBVI_B
+ 268454646U, // SUBVI_D
+ 268456418U, // SUBVI_H
+ 268460301U, // SUBVI_W
+ 268453350U, // SUBV_B
+ 268455781U, // SUBV_D
+ 268457115U, // SUBV_H
+ 268461438U, // SUBV_W
+ 268453797U, // SUB_MM
+ 268453797U, // SUB_MMR6
+ 268459514U, // SUBu
+ 268459514U, // SUBu_MM
+ 3774890155U, // SUXC1
+ 3774890155U, // SUXC164
+ 3774890155U, // SUXC1_MM
+ 25191910U, // SW
+ 25182827U, // SW16_MM
+ 25182827U, // SW16_MMR6
+ 25191910U, // SW64
+ 25182352U, // SWC1
+ 25182352U, // SWC1_MM
+ 25182568U, // SWC2
+ 25182568U, // SWC2_MMR6
+ 25182568U, // SWC2_R6
+ 25182613U, // SWC3
+ 25191910U, // SWDSP
+ 25191910U, // SWDSP_MM
+ 25186533U, // SWE
+ 25186533U, // SWE_MM
+ 25188612U, // SWL
+ 25188612U, // SWL64
+ 25186465U, // SWLE
+ 25186465U, // SWLE_MM
+ 25188612U, // SWL_MM
+ 836114U, // SWM16_MM
+ 836114U, // SWM16_MMR6
+ 835854U, // SWM32_MM
+ 176183826U, // SWP_MM
+ 25189112U, // SWR
+ 25189112U, // SWR64
+ 25186504U, // SWRE
+ 25186504U, // SWRE_MM
+ 25189112U, // SWR_MM
+ 25191910U, // SWSP_MM
+ 25191910U, // SWSP_MMR6
+ 3774890169U, // SWXC1
+ 3774890169U, // SWXC1_MM
+ 25191910U, // SW_MM
+ 25191910U, // SW_MMR6
+ 206530U, // SYNC
+ 218921U, // SYNCI
+ 218921U, // SYNCI_MM
+ 218921U, // SYNCI_MMR6
+ 206530U, // SYNC_MM
+ 198675U, // SYNC_MMR6
+ 186519U, // SYSCALL
+ 366743U, // SYSCALL_MM
+ 0U, // Save16
+ 0U, // SaveX16
+ 25184158U, // SbRxRyOffMemX16
+ 288341U, // SebRx16
+ 288347U, // SehRx16
+ 25188127U, // ShRxRyOffMemX16
+ 268458163U, // SllX16
+ 16801557U, // SllvRxRy16
+ 24001U, // SltRxRy16
+ 2952812434U, // SltiRxImm16
+ 22418U, // SltiRxImmX16
+ 2952814161U, // SltiuRxImm16
+ 24145U, // SltiuRxImmX16
+ 24215U, // SltuRxRy16
+ 268452553U, // SraX16
+ 16801536U, // SravRxRy16
+ 268458181U, // SrlX16
+ 16801564U, // SrlvRxRy16
+ 268459514U, // SubuRxRyRz16
+ 25191910U, // SwRxRyOffMemX16
+ 25191910U, // SwRxSpImmX16
+ 268458529U, // TEQ
+ 22400U, // TEQI
+ 22400U, // TEQI_MM
+ 268458529U, // TEQ_MM
+ 268456059U, // TGE
+ 22333U, // TGEI
+ 24138U, // TGEIU
+ 24138U, // TGEIU_MM
+ 22333U, // TGEI_MM
+ 268459561U, // TGEU
+ 268459561U, // TGEU_MM
+ 268456059U, // TGE_MM
+ 10416U, // TLBGINV
+ 10317U, // TLBGINVF
+ 10317U, // TLBGINVF_MM
+ 10416U, // TLBGINV_MM
+ 10362U, // TLBGP
+ 10362U, // TLBGP_MM
+ 10379U, // TLBGR
+ 10379U, // TLBGR_MM
+ 10332U, // TLBGWI
+ 10332U, // TLBGWI_MM
+ 10391U, // TLBGWR
+ 10391U, // TLBGWR_MM
+ 10409U, // TLBINV
+ 10309U, // TLBINVF
+ 10309U, // TLBINVF_MMR6
+ 10409U, // TLBINV_MMR6
+ 10357U, // TLBP
+ 10357U, // TLBP_MM
+ 10374U, // TLBR
+ 10374U, // TLBR_MM
+ 10326U, // TLBWI
+ 10326U, // TLBWI_MM
+ 10385U, // TLBWR
+ 10385U, // TLBWR_MM
+ 268459462U, // TLT
+ 22424U, // TLTI
+ 24152U, // TLTIU_MM
+ 22424U, // TLTI_MM
+ 268459677U, // TLTU
+ 268459677U, // TLTU_MM
+ 268459462U, // TLT_MM
+ 268456113U, // TNE
+ 22345U, // TNEI
+ 22345U, // TNEI_MM
+ 268456113U, // TNE_MM
+ 19208U, // TRUNC_L_D64
+ 19208U, // TRUNC_L_D_MMR6
+ 23500U, // TRUNC_L_S
+ 23500U, // TRUNC_L_S_MMR6
+ 20383U, // TRUNC_W_D32
+ 20383U, // TRUNC_W_D64
+ 20383U, // TRUNC_W_D_MMR6
+ 20383U, // TRUNC_W_MM
+ 23832U, // TRUNC_W_S
+ 23832U, // TRUNC_W_S_MM
+ 23832U, // TRUNC_W_S_MMR6
+ 24152U, // TTLTIU
+ 26210U, // UDIV
+ 26210U, // UDIV_MM
+ 268459615U, // V3MULU
+ 268451901U, // VMM0
+ 268459630U, // VMULU
+ 285229890U, // VSHF_B
+ 285231715U, // VSHF_D
+ 285233503U, // VSHF_H
+ 285237305U, // VSHF_W
+ 10404U, // WAIT
+ 368054U, // WAIT_MM
+ 368054U, // WAIT_MMR6
+ 83909087U, // WRDSP
+ 192960991U, // WRDSP_MM
+ 23249U, // WRPGPR_MMR6
+ 21729U, // WSBH
+ 21729U, // WSBH_MM
+ 21729U, // WSBH_MMR6
+ 268458692U, // XOR
+ 10306096U, // XOR16_MM
+ 10306096U, // XOR16_MMR6
+ 268458692U, // XOR64
+ 268452801U, // XORI_B
+ 268457862U, // XORI_MMR6
+ 268458692U, // XOR_MM
+ 268458692U, // XOR_MMR6
+ 268459740U, // XOR_V
+ 268457862U, // XORi
+ 268457862U, // XORi64
+ 268457862U, // XORi_MM
+ 16800452U, // XorRxRxRy16
+ 20524U, // YIELD
+ };
+
+ static const uint16_t OpInfo1[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // ANNOTATION_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 0U, // DBG_VALUE
+ 0U, // DBG_LABEL
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 0U, // BUNDLE
+ 0U, // LIFETIME_START
+ 0U, // LIFETIME_END
+ 0U, // STACKMAP
+ 0U, // FENTRY_CALL
+ 0U, // PATCHPOINT
+ 0U, // LOAD_STACK_GUARD
+ 0U, // STATEPOINT
+ 0U, // LOCAL_ESCAPE
+ 0U, // FAULTING_OP
+ 0U, // PATCHABLE_OP
+ 0U, // PATCHABLE_FUNCTION_ENTER
+ 0U, // PATCHABLE_RET
+ 0U, // PATCHABLE_FUNCTION_EXIT
+ 0U, // PATCHABLE_TAIL_CALL
+ 0U, // PATCHABLE_EVENT_CALL
+ 0U, // PATCHABLE_TYPED_EVENT_CALL
+ 0U, // ICALL_BRANCH_FUNNEL
+ 0U, // G_ADD
+ 0U, // G_SUB
+ 0U, // G_MUL
+ 0U, // G_SDIV
+ 0U, // G_UDIV
+ 0U, // G_SREM
+ 0U, // G_UREM
+ 0U, // G_AND
+ 0U, // G_OR
+ 0U, // G_XOR
+ 0U, // G_IMPLICIT_DEF
+ 0U, // G_PHI
+ 0U, // G_FRAME_INDEX
+ 0U, // G_GLOBAL_VALUE
+ 0U, // G_EXTRACT
+ 0U, // G_UNMERGE_VALUES
+ 0U, // G_INSERT
+ 0U, // G_MERGE_VALUES
+ 0U, // G_PTRTOINT
+ 0U, // G_INTTOPTR
+ 0U, // G_BITCAST
+ 0U, // G_LOAD
+ 0U, // G_SEXTLOAD
+ 0U, // G_ZEXTLOAD
+ 0U, // G_STORE
+ 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ 0U, // G_ATOMIC_CMPXCHG
+ 0U, // G_ATOMICRMW_XCHG
+ 0U, // G_ATOMICRMW_ADD
+ 0U, // G_ATOMICRMW_SUB
+ 0U, // G_ATOMICRMW_AND
+ 0U, // G_ATOMICRMW_NAND
+ 0U, // G_ATOMICRMW_OR
+ 0U, // G_ATOMICRMW_XOR
+ 0U, // G_ATOMICRMW_MAX
+ 0U, // G_ATOMICRMW_MIN
+ 0U, // G_ATOMICRMW_UMAX
+ 0U, // G_ATOMICRMW_UMIN
+ 0U, // G_BRCOND
+ 0U, // G_BRINDIRECT
+ 0U, // G_INTRINSIC
+ 0U, // G_INTRINSIC_W_SIDE_EFFECTS
+ 0U, // G_ANYEXT
+ 0U, // G_TRUNC
+ 0U, // G_CONSTANT
+ 0U, // G_FCONSTANT
+ 0U, // G_VASTART
+ 0U, // G_VAARG
+ 0U, // G_SEXT
+ 0U, // G_ZEXT
+ 0U, // G_SHL
+ 0U, // G_LSHR
+ 0U, // G_ASHR
+ 0U, // G_ICMP
+ 0U, // G_FCMP
+ 0U, // G_SELECT
+ 0U, // G_UADDE
+ 0U, // G_USUBE
+ 0U, // G_SADDO
+ 0U, // G_SSUBO
+ 0U, // G_UMULO
+ 0U, // G_SMULO
+ 0U, // G_UMULH
+ 0U, // G_SMULH
+ 0U, // G_FADD
+ 0U, // G_FSUB
+ 0U, // G_FMUL
+ 0U, // G_FMA
+ 0U, // G_FDIV
+ 0U, // G_FREM
+ 0U, // G_FPOW
+ 0U, // G_FEXP
+ 0U, // G_FEXP2
+ 0U, // G_FLOG
+ 0U, // G_FLOG2
+ 0U, // G_FNEG
+ 0U, // G_FPEXT
+ 0U, // G_FPTRUNC
+ 0U, // G_FPTOSI
+ 0U, // G_FPTOUI
+ 0U, // G_SITOFP
+ 0U, // G_UITOFP
+ 0U, // G_FABS
+ 0U, // G_GEP
+ 0U, // G_PTR_MASK
+ 0U, // G_BR
+ 0U, // G_INSERT_VECTOR_ELT
+ 0U, // G_EXTRACT_VECTOR_ELT
+ 0U, // G_SHUFFLE_VECTOR
+ 0U, // G_BSWAP
+ 0U, // G_ADDRSPACE_CAST
+ 0U, // G_BLOCK_ADDR
+ 0U, // ABSMacro
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 0U, // AND_V_D_PSEUDO
+ 0U, // AND_V_H_PSEUDO
+ 0U, // AND_V_W_PSEUDO
+ 0U, // ATOMIC_CMP_SWAP_I16
+ 0U, // ATOMIC_CMP_SWAP_I16_POSTRA
+ 0U, // ATOMIC_CMP_SWAP_I32
+ 0U, // ATOMIC_CMP_SWAP_I32_POSTRA
+ 0U, // ATOMIC_CMP_SWAP_I64
+ 0U, // ATOMIC_CMP_SWAP_I64_POSTRA
+ 0U, // ATOMIC_CMP_SWAP_I8
+ 0U, // ATOMIC_CMP_SWAP_I8_POSTRA
+ 0U, // ATOMIC_LOAD_ADD_I16
+ 0U, // ATOMIC_LOAD_ADD_I16_POSTRA
+ 0U, // ATOMIC_LOAD_ADD_I32
+ 0U, // ATOMIC_LOAD_ADD_I32_POSTRA
+ 0U, // ATOMIC_LOAD_ADD_I64
+ 0U, // ATOMIC_LOAD_ADD_I64_POSTRA
+ 0U, // ATOMIC_LOAD_ADD_I8
+ 0U, // ATOMIC_LOAD_ADD_I8_POSTRA
+ 0U, // ATOMIC_LOAD_AND_I16
+ 0U, // ATOMIC_LOAD_AND_I16_POSTRA
+ 0U, // ATOMIC_LOAD_AND_I32
+ 0U, // ATOMIC_LOAD_AND_I32_POSTRA
+ 0U, // ATOMIC_LOAD_AND_I64
+ 0U, // ATOMIC_LOAD_AND_I64_POSTRA
+ 0U, // ATOMIC_LOAD_AND_I8
+ 0U, // ATOMIC_LOAD_AND_I8_POSTRA
+ 0U, // ATOMIC_LOAD_NAND_I16
+ 0U, // ATOMIC_LOAD_NAND_I16_POSTRA
+ 0U, // ATOMIC_LOAD_NAND_I32
+ 0U, // ATOMIC_LOAD_NAND_I32_POSTRA
+ 0U, // ATOMIC_LOAD_NAND_I64
+ 0U, // ATOMIC_LOAD_NAND_I64_POSTRA
+ 0U, // ATOMIC_LOAD_NAND_I8
+ 0U, // ATOMIC_LOAD_NAND_I8_POSTRA
+ 0U, // ATOMIC_LOAD_OR_I16
+ 0U, // ATOMIC_LOAD_OR_I16_POSTRA
+ 0U, // ATOMIC_LOAD_OR_I32
+ 0U, // ATOMIC_LOAD_OR_I32_POSTRA
+ 0U, // ATOMIC_LOAD_OR_I64
+ 0U, // ATOMIC_LOAD_OR_I64_POSTRA
+ 0U, // ATOMIC_LOAD_OR_I8
+ 0U, // ATOMIC_LOAD_OR_I8_POSTRA
+ 0U, // ATOMIC_LOAD_SUB_I16
+ 0U, // ATOMIC_LOAD_SUB_I16_POSTRA
+ 0U, // ATOMIC_LOAD_SUB_I32
+ 0U, // ATOMIC_LOAD_SUB_I32_POSTRA
+ 0U, // ATOMIC_LOAD_SUB_I64
+ 0U, // ATOMIC_LOAD_SUB_I64_POSTRA
+ 0U, // ATOMIC_LOAD_SUB_I8
+ 0U, // ATOMIC_LOAD_SUB_I8_POSTRA
+ 0U, // ATOMIC_LOAD_XOR_I16
+ 0U, // ATOMIC_LOAD_XOR_I16_POSTRA
+ 0U, // ATOMIC_LOAD_XOR_I32
+ 0U, // ATOMIC_LOAD_XOR_I32_POSTRA
+ 0U, // ATOMIC_LOAD_XOR_I64
+ 0U, // ATOMIC_LOAD_XOR_I64_POSTRA
+ 0U, // ATOMIC_LOAD_XOR_I8
+ 0U, // ATOMIC_LOAD_XOR_I8_POSTRA
+ 0U, // ATOMIC_SWAP_I16
+ 0U, // ATOMIC_SWAP_I16_POSTRA
+ 0U, // ATOMIC_SWAP_I32
+ 0U, // ATOMIC_SWAP_I32_POSTRA
+ 0U, // ATOMIC_SWAP_I64
+ 0U, // ATOMIC_SWAP_I64_POSTRA
+ 0U, // ATOMIC_SWAP_I8
+ 0U, // ATOMIC_SWAP_I8_POSTRA
+ 0U, // B
+ 0U, // BAL_BR
+ 0U, // BAL_BR_MM
+ 0U, // BEQLImmMacro
+ 0U, // BGE
+ 0U, // BGEImmMacro
+ 0U, // BGEL
+ 0U, // BGELImmMacro
+ 0U, // BGEU
+ 0U, // BGEUImmMacro
+ 0U, // BGEUL
+ 0U, // BGEULImmMacro
+ 0U, // BGT
+ 0U, // BGTImmMacro
+ 0U, // BGTL
+ 0U, // BGTLImmMacro
+ 0U, // BGTU
+ 0U, // BGTUImmMacro
+ 0U, // BGTUL
+ 0U, // BGTULImmMacro
+ 0U, // BLE
+ 0U, // BLEImmMacro
+ 0U, // BLEL
+ 0U, // BLELImmMacro
+ 0U, // BLEU
+ 0U, // BLEUImmMacro
+ 0U, // BLEUL
+ 0U, // BLEULImmMacro
+ 0U, // BLT
+ 0U, // BLTImmMacro
+ 0U, // BLTL
+ 0U, // BLTLImmMacro
+ 0U, // BLTU
+ 0U, // BLTUImmMacro
+ 0U, // BLTUL
+ 0U, // BLTULImmMacro
+ 0U, // BNELImmMacro
+ 0U, // BPOSGE32_PSEUDO
+ 0U, // BSEL_D_PSEUDO
+ 0U, // BSEL_FD_PSEUDO
+ 0U, // BSEL_FW_PSEUDO
+ 0U, // BSEL_H_PSEUDO
+ 0U, // BSEL_W_PSEUDO
+ 0U, // B_MM
+ 0U, // B_MMR6_Pseudo
+ 0U, // B_MM_Pseudo
+ 0U, // BeqImm
+ 0U, // BneImm
+ 0U, // BteqzT8CmpX16
+ 0U, // BteqzT8CmpiX16
+ 0U, // BteqzT8SltX16
+ 0U, // BteqzT8SltiX16
+ 0U, // BteqzT8SltiuX16
+ 0U, // BteqzT8SltuX16
+ 0U, // BtnezT8CmpX16
+ 0U, // BtnezT8CmpiX16
+ 0U, // BtnezT8SltX16
+ 0U, // BtnezT8SltiX16
+ 0U, // BtnezT8SltiuX16
+ 0U, // BtnezT8SltuX16
+ 0U, // BuildPairF64
+ 0U, // BuildPairF64_64
+ 0U, // CFTC1
+ 0U, // CONSTPOOL_ENTRY
+ 0U, // COPY_FD_PSEUDO
+ 0U, // COPY_FW_PSEUDO
+ 0U, // CTTC1
+ 0U, // Constant32
+ 0U, // DMULImmMacro
+ 0U, // DMULMacro
+ 0U, // DMULOMacro
+ 0U, // DMULOUMacro
+ 0U, // DROL
+ 0U, // DROLImm
+ 0U, // DROR
+ 0U, // DRORImm
+ 0U, // DSDivIMacro
+ 0U, // DSDivMacro
+ 0U, // DSRemIMacro
+ 0U, // DSRemMacro
+ 0U, // DUDivIMacro
+ 0U, // DUDivMacro
+ 0U, // DURemIMacro
+ 0U, // DURemMacro
+ 0U, // ERet
+ 0U, // ExtractElementF64
+ 0U, // ExtractElementF64_64
+ 0U, // FABS_D
+ 0U, // FABS_W
+ 0U, // FEXP2_D_1_PSEUDO
+ 0U, // FEXP2_W_1_PSEUDO
+ 0U, // FILL_FD_PSEUDO
+ 0U, // FILL_FW_PSEUDO
+ 0U, // GotPrologue16
+ 0U, // INSERT_B_VIDX64_PSEUDO
+ 0U, // INSERT_B_VIDX_PSEUDO
+ 0U, // INSERT_D_VIDX64_PSEUDO
+ 0U, // INSERT_D_VIDX_PSEUDO
+ 0U, // INSERT_FD_PSEUDO
+ 0U, // INSERT_FD_VIDX64_PSEUDO
+ 0U, // INSERT_FD_VIDX_PSEUDO
+ 0U, // INSERT_FW_PSEUDO
+ 0U, // INSERT_FW_VIDX64_PSEUDO
+ 0U, // INSERT_FW_VIDX_PSEUDO
+ 0U, // INSERT_H_VIDX64_PSEUDO
+ 0U, // INSERT_H_VIDX_PSEUDO
+ 0U, // INSERT_W_VIDX64_PSEUDO
+ 0U, // INSERT_W_VIDX_PSEUDO
+ 0U, // JALR64Pseudo
+ 0U, // JALRHB64Pseudo
+ 0U, // JALRHBPseudo
+ 0U, // JALRPseudo
+ 0U, // JalOneReg
+ 0U, // JalTwoReg
+ 0U, // LDMacro
+ 0U, // LD_F16
+ 0U, // LOAD_ACC128
+ 0U, // LOAD_ACC64
+ 0U, // LOAD_ACC64DSP
+ 0U, // LOAD_CCOND_DSP
+ 0U, // LONG_BRANCH_ADDiu
+ 0U, // LONG_BRANCH_DADDiu
+ 0U, // LONG_BRANCH_LUi
+ 0U, // LWM_MM
+ 0U, // LoadAddrImm32
+ 0U, // LoadAddrImm64
+ 0U, // LoadAddrReg32
+ 0U, // LoadAddrReg64
+ 0U, // LoadImm32
+ 0U, // LoadImm64
+ 0U, // LoadImmDoubleFGR
+ 0U, // LoadImmDoubleFGR_32
+ 0U, // LoadImmDoubleGPR
+ 0U, // LoadImmSingleFGR
+ 0U, // LoadImmSingleGPR
+ 0U, // LwConstant32
+ 0U, // MFTACX
+ 2U, // MFTC0
+ 0U, // MFTC1
+ 0U, // MFTDSP
+ 0U, // MFTGPR
+ 0U, // MFTHC1
+ 0U, // MFTHI
+ 0U, // MFTLO
+ 0U, // MIPSeh_return32
+ 0U, // MIPSeh_return64
+ 0U, // MSA_FP_EXTEND_D_PSEUDO
+ 0U, // MSA_FP_EXTEND_W_PSEUDO
+ 0U, // MSA_FP_ROUND_D_PSEUDO
+ 0U, // MSA_FP_ROUND_W_PSEUDO
+ 0U, // MTTACX
+ 0U, // MTTC0
+ 0U, // MTTC1
+ 0U, // MTTDSP
+ 0U, // MTTGPR
+ 0U, // MTTHC1
+ 0U, // MTTHI
+ 0U, // MTTLO
+ 0U, // MULImmMacro
+ 0U, // MULOMacro
+ 0U, // MULOUMacro
+ 0U, // MultRxRy16
+ 0U, // MultRxRyRz16
+ 0U, // MultuRxRy16
+ 0U, // MultuRxRyRz16
+ 0U, // NOP
+ 0U, // NORImm
+ 0U, // NORImm64
+ 0U, // NOR_V_D_PSEUDO
+ 0U, // NOR_V_H_PSEUDO
+ 0U, // NOR_V_W_PSEUDO
+ 0U, // OR_V_D_PSEUDO
+ 0U, // OR_V_H_PSEUDO
+ 0U, // OR_V_W_PSEUDO
+ 0U, // PseudoCMPU_EQ_QB
+ 0U, // PseudoCMPU_LE_QB
+ 0U, // PseudoCMPU_LT_QB
+ 0U, // PseudoCMP_EQ_PH
+ 0U, // PseudoCMP_LE_PH
+ 0U, // PseudoCMP_LT_PH
+ 0U, // PseudoCVT_D32_W
+ 0U, // PseudoCVT_D64_L
+ 0U, // PseudoCVT_D64_W
+ 0U, // PseudoCVT_S_L
+ 0U, // PseudoCVT_S_W
+ 0U, // PseudoDMULT
+ 0U, // PseudoDMULTu
+ 0U, // PseudoDSDIV
+ 0U, // PseudoDUDIV
+ 0U, // PseudoIndirectBranch
+ 0U, // PseudoIndirectBranch64
+ 0U, // PseudoIndirectBranch64R6
+ 0U, // PseudoIndirectBranchR6
+ 0U, // PseudoIndirectBranch_MM
+ 0U, // PseudoIndirectBranch_MMR6
+ 0U, // PseudoIndirectHazardBranch
+ 0U, // PseudoIndirectHazardBranch64
+ 0U, // PseudoIndrectHazardBranch64R6
+ 0U, // PseudoIndrectHazardBranchR6
+ 0U, // PseudoMADD
+ 0U, // PseudoMADDU
+ 0U, // PseudoMFHI
+ 0U, // PseudoMFHI64
+ 0U, // PseudoMFLO
+ 0U, // PseudoMFLO64
+ 0U, // PseudoMSUB
+ 0U, // PseudoMSUBU
+ 0U, // PseudoMTLOHI
+ 0U, // PseudoMTLOHI64
+ 0U, // PseudoMTLOHI_DSP
+ 0U, // PseudoMULT
+ 0U, // PseudoMULTu
+ 0U, // PseudoPICK_PH
+ 0U, // PseudoPICK_QB
+ 0U, // PseudoReturn
+ 0U, // PseudoReturn64
+ 0U, // PseudoSDIV
+ 0U, // PseudoSELECTFP_F_D32
+ 0U, // PseudoSELECTFP_F_D64
+ 0U, // PseudoSELECTFP_F_I
+ 0U, // PseudoSELECTFP_F_I64
+ 0U, // PseudoSELECTFP_F_S
+ 0U, // PseudoSELECTFP_T_D32
+ 0U, // PseudoSELECTFP_T_D64
+ 0U, // PseudoSELECTFP_T_I
+ 0U, // PseudoSELECTFP_T_I64
+ 0U, // PseudoSELECTFP_T_S
+ 0U, // PseudoSELECT_D32
+ 0U, // PseudoSELECT_D64
+ 0U, // PseudoSELECT_I
+ 0U, // PseudoSELECT_I64
+ 0U, // PseudoSELECT_S
+ 0U, // PseudoTRUNC_W_D
+ 0U, // PseudoTRUNC_W_D32
+ 0U, // PseudoTRUNC_W_S
+ 0U, // PseudoUDIV
+ 0U, // ROL
+ 0U, // ROLImm
+ 0U, // ROR
+ 0U, // RORImm
+ 0U, // RetRA
+ 0U, // RetRA16
+ 0U, // SDIV_MM_Pseudo
+ 0U, // SDMacro
+ 0U, // SDivIMacro
+ 0U, // SDivMacro
+ 0U, // SEQIMacro
+ 0U, // SEQMacro
+ 0U, // SLTImm64
+ 0U, // SLTUImm64
+ 0U, // SNZ_B_PSEUDO
+ 0U, // SNZ_D_PSEUDO
+ 0U, // SNZ_H_PSEUDO
+ 0U, // SNZ_V_PSEUDO
+ 0U, // SNZ_W_PSEUDO
+ 0U, // SRemIMacro
+ 0U, // SRemMacro
+ 0U, // STORE_ACC128
+ 0U, // STORE_ACC64
+ 0U, // STORE_ACC64DSP
+ 0U, // STORE_CCOND_DSP
+ 0U, // ST_F16
+ 0U, // SWM_MM
+ 0U, // SZ_B_PSEUDO
+ 0U, // SZ_D_PSEUDO
+ 0U, // SZ_H_PSEUDO
+ 0U, // SZ_V_PSEUDO
+ 0U, // SZ_W_PSEUDO
+ 0U, // SelBeqZ
+ 0U, // SelBneZ
+ 0U, // SelTBteqZCmp
+ 0U, // SelTBteqZCmpi
+ 0U, // SelTBteqZSlt
+ 0U, // SelTBteqZSlti
+ 0U, // SelTBteqZSltiu
+ 0U, // SelTBteqZSltu
+ 0U, // SelTBtneZCmp
+ 0U, // SelTBtneZCmpi
+ 0U, // SelTBtneZSlt
+ 0U, // SelTBtneZSlti
+ 0U, // SelTBtneZSltiu
+ 0U, // SelTBtneZSltu
+ 0U, // SltCCRxRy16
+ 0U, // SltiCCRxImmX16
+ 0U, // SltiuCCRxImmX16
+ 0U, // SltuCCRxRy16
+ 0U, // SltuRxRyRz16
+ 0U, // TAILCALL
+ 0U, // TAILCALL64R6REG
+ 0U, // TAILCALLHB64R6REG
+ 0U, // TAILCALLHBR6REG
+ 0U, // TAILCALLR6REG
+ 0U, // TAILCALLREG
+ 0U, // TAILCALLREG64
+ 0U, // TAILCALLREGHB
+ 0U, // TAILCALLREGHB64
+ 0U, // TAILCALLREG_MM
+ 0U, // TAILCALLREG_MMR6
+ 0U, // TAILCALL_MM
+ 0U, // TAILCALL_MMR6
+ 0U, // TRAP
+ 0U, // TRAP_MM
+ 0U, // UDIV_MM_Pseudo
+ 0U, // UDivIMacro
+ 0U, // UDivMacro
+ 0U, // URemIMacro
+ 0U, // URemMacro
+ 0U, // Ulh
+ 0U, // Ulhu
+ 0U, // Ulw
+ 0U, // Ush
+ 0U, // Usw
+ 0U, // XOR_V_D_PSEUDO
+ 0U, // XOR_V_H_PSEUDO
+ 0U, // XOR_V_W_PSEUDO
+ 0U, // ABSQ_S_PH
+ 0U, // ABSQ_S_PH_MM
+ 0U, // ABSQ_S_QB
+ 0U, // ABSQ_S_QB_MMR2
+ 0U, // ABSQ_S_W
+ 0U, // ABSQ_S_W_MM
+ 0U, // ADD
+ 0U, // ADDIUPC
+ 0U, // ADDIUPC_MM
+ 0U, // ADDIUPC_MMR6
+ 0U, // ADDIUR1SP_MM
+ 0U, // ADDIUR2_MM
+ 0U, // ADDIUS5_MM
+ 0U, // ADDIUSP_MM
+ 0U, // ADDIU_MMR6
+ 0U, // ADDQH_PH
+ 0U, // ADDQH_PH_MMR2
+ 0U, // ADDQH_R_PH
+ 0U, // ADDQH_R_PH_MMR2
+ 0U, // ADDQH_R_W
+ 0U, // ADDQH_R_W_MMR2
+ 0U, // ADDQH_W
+ 0U, // ADDQH_W_MMR2
+ 0U, // ADDQ_PH
+ 0U, // ADDQ_PH_MM
+ 0U, // ADDQ_S_PH
+ 0U, // ADDQ_S_PH_MM
+ 0U, // ADDQ_S_W
+ 0U, // ADDQ_S_W_MM
+ 0U, // ADDSC
+ 0U, // ADDSC_MM
+ 0U, // ADDS_A_B
+ 0U, // ADDS_A_D
+ 0U, // ADDS_A_H
+ 0U, // ADDS_A_W
+ 0U, // ADDS_S_B
+ 0U, // ADDS_S_D
+ 0U, // ADDS_S_H
+ 0U, // ADDS_S_W
+ 0U, // ADDS_U_B
+ 0U, // ADDS_U_D
+ 0U, // ADDS_U_H
+ 0U, // ADDS_U_W
+ 0U, // ADDU16_MM
+ 0U, // ADDU16_MMR6
+ 0U, // ADDUH_QB
+ 0U, // ADDUH_QB_MMR2
+ 0U, // ADDUH_R_QB
+ 0U, // ADDUH_R_QB_MMR2
+ 0U, // ADDU_MMR6
+ 0U, // ADDU_PH
+ 0U, // ADDU_PH_MMR2
+ 0U, // ADDU_QB
+ 0U, // ADDU_QB_MM
+ 0U, // ADDU_S_PH
+ 0U, // ADDU_S_PH_MMR2
+ 0U, // ADDU_S_QB
+ 0U, // ADDU_S_QB_MM
+ 4U, // ADDVI_B
+ 4U, // ADDVI_D
+ 4U, // ADDVI_H
+ 4U, // ADDVI_W
+ 0U, // ADDV_B
+ 0U, // ADDV_D
+ 0U, // ADDV_H
+ 0U, // ADDV_W
+ 0U, // ADDWC
+ 0U, // ADDWC_MM
+ 0U, // ADD_A_B
+ 0U, // ADD_A_D
+ 0U, // ADD_A_H
+ 0U, // ADD_A_W
+ 0U, // ADD_MM
+ 0U, // ADD_MMR6
+ 0U, // ADDi
+ 0U, // ADDi_MM
+ 0U, // ADDiu
+ 0U, // ADDiu_MM
+ 0U, // ADDu
+ 0U, // ADDu_MM
+ 64U, // ALIGN
+ 64U, // ALIGN_MMR6
+ 0U, // ALUIPC
+ 0U, // ALUIPC_MMR6
+ 0U, // AND
+ 0U, // AND16_MM
+ 0U, // AND16_MMR6
+ 0U, // AND64
+ 0U, // ANDI16_MM
+ 0U, // ANDI16_MMR6
+ 6U, // ANDI_B
+ 8U, // ANDI_MMR6
+ 0U, // AND_MM
+ 0U, // AND_MMR6
+ 0U, // AND_V
+ 8U, // ANDi
+ 8U, // ANDi64
+ 8U, // ANDi_MM
+ 4U, // APPEND
+ 4U, // APPEND_MMR2
+ 0U, // ASUB_S_B
+ 0U, // ASUB_S_D
+ 0U, // ASUB_S_H
+ 0U, // ASUB_S_W
+ 0U, // ASUB_U_B
+ 0U, // ASUB_U_D
+ 0U, // ASUB_U_H
+ 0U, // ASUB_U_W
+ 8U, // AUI
+ 0U, // AUIPC
+ 0U, // AUIPC_MMR6
+ 8U, // AUI_MMR6
+ 0U, // AVER_S_B
+ 0U, // AVER_S_D
+ 0U, // AVER_S_H
+ 0U, // AVER_S_W
+ 0U, // AVER_U_B
+ 0U, // AVER_U_D
+ 0U, // AVER_U_H
+ 0U, // AVER_U_W
+ 0U, // AVE_S_B
+ 0U, // AVE_S_D
+ 0U, // AVE_S_H
+ 0U, // AVE_S_W
+ 0U, // AVE_U_B
+ 0U, // AVE_U_D
+ 0U, // AVE_U_H
+ 0U, // AVE_U_W
+ 0U, // AddiuRxImmX16
+ 0U, // AddiuRxPcImmX16
+ 0U, // AddiuRxRxImm16
+ 0U, // AddiuRxRxImmX16
+ 0U, // AddiuRxRyOffMemX16
+ 0U, // AddiuSpImm16
+ 0U, // AddiuSpImmX16
+ 0U, // AdduRxRyRz16
+ 0U, // AndRxRxRy16
+ 0U, // B16_MM
+ 0U, // BADDu
+ 0U, // BAL
+ 0U, // BALC
+ 0U, // BALC_MMR6
+ 10U, // BALIGN
+ 10U, // BALIGN_MMR2
+ 0U, // BBIT0
+ 0U, // BBIT032
+ 0U, // BBIT1
+ 0U, // BBIT132
+ 0U, // BC
+ 0U, // BC16_MMR6
+ 0U, // BC1EQZ
+ 0U, // BC1EQZC_MMR6
+ 0U, // BC1F
+ 0U, // BC1FL
+ 0U, // BC1F_MM
+ 0U, // BC1NEZ
+ 0U, // BC1NEZC_MMR6
+ 0U, // BC1T
+ 0U, // BC1TL
+ 0U, // BC1T_MM
+ 0U, // BC2EQZ
+ 0U, // BC2EQZC_MMR6
+ 0U, // BC2NEZ
+ 0U, // BC2NEZC_MMR6
+ 2U, // BCLRI_B
+ 12U, // BCLRI_D
+ 14U, // BCLRI_H
+ 4U, // BCLRI_W
+ 0U, // BCLR_B
+ 0U, // BCLR_D
+ 0U, // BCLR_H
+ 0U, // BCLR_W
+ 0U, // BC_MMR6
+ 0U, // BEQ
+ 0U, // BEQ64
+ 0U, // BEQC
+ 0U, // BEQC64
+ 0U, // BEQC_MMR6
+ 0U, // BEQL
+ 0U, // BEQZ16_MM
+ 0U, // BEQZALC
+ 0U, // BEQZALC_MMR6
+ 0U, // BEQZC
+ 0U, // BEQZC16_MMR6
+ 0U, // BEQZC64
+ 0U, // BEQZC_MM
+ 0U, // BEQZC_MMR6
+ 0U, // BEQ_MM
+ 0U, // BGEC
+ 0U, // BGEC64
+ 0U, // BGEC_MMR6
+ 0U, // BGEUC
+ 0U, // BGEUC64
+ 0U, // BGEUC_MMR6
+ 0U, // BGEZ
+ 0U, // BGEZ64
+ 0U, // BGEZAL
+ 0U, // BGEZALC
+ 0U, // BGEZALC_MMR6
+ 0U, // BGEZALL
+ 0U, // BGEZALS_MM
+ 0U, // BGEZAL_MM
+ 0U, // BGEZC
+ 0U, // BGEZC64
+ 0U, // BGEZC_MMR6
+ 0U, // BGEZL
+ 0U, // BGEZ_MM
+ 0U, // BGTZ
+ 0U, // BGTZ64
+ 0U, // BGTZALC
+ 0U, // BGTZALC_MMR6
+ 0U, // BGTZC
+ 0U, // BGTZC64
+ 0U, // BGTZC_MMR6
+ 0U, // BGTZL
+ 0U, // BGTZ_MM
+ 16U, // BINSLI_B
+ 18U, // BINSLI_D
+ 20U, // BINSLI_H
+ 22U, // BINSLI_W
+ 24U, // BINSL_B
+ 24U, // BINSL_D
+ 24U, // BINSL_H
+ 24U, // BINSL_W
+ 16U, // BINSRI_B
+ 18U, // BINSRI_D
+ 20U, // BINSRI_H
+ 22U, // BINSRI_W
+ 24U, // BINSR_B
+ 24U, // BINSR_D
+ 24U, // BINSR_H
+ 24U, // BINSR_W
+ 0U, // BITREV
+ 0U, // BITREV_MM
+ 0U, // BITSWAP
+ 0U, // BITSWAP_MMR6
+ 0U, // BLEZ
+ 0U, // BLEZ64
+ 0U, // BLEZALC
+ 0U, // BLEZALC_MMR6
+ 0U, // BLEZC
+ 0U, // BLEZC64
+ 0U, // BLEZC_MMR6
+ 0U, // BLEZL
+ 0U, // BLEZ_MM
+ 0U, // BLTC
+ 0U, // BLTC64
+ 0U, // BLTC_MMR6
+ 0U, // BLTUC
+ 0U, // BLTUC64
+ 0U, // BLTUC_MMR6
+ 0U, // BLTZ
+ 0U, // BLTZ64
+ 0U, // BLTZAL
+ 0U, // BLTZALC
+ 0U, // BLTZALC_MMR6
+ 0U, // BLTZALL
+ 0U, // BLTZALS_MM
+ 0U, // BLTZAL_MM
+ 0U, // BLTZC
+ 0U, // BLTZC64
+ 0U, // BLTZC_MMR6
+ 0U, // BLTZL
+ 0U, // BLTZ_MM
+ 26U, // BMNZI_B
+ 24U, // BMNZ_V
+ 26U, // BMZI_B
+ 24U, // BMZ_V
+ 0U, // BNE
+ 0U, // BNE64
+ 0U, // BNEC
+ 0U, // BNEC64
+ 0U, // BNEC_MMR6
+ 2U, // BNEGI_B
+ 12U, // BNEGI_D
+ 14U, // BNEGI_H
+ 4U, // BNEGI_W
+ 0U, // BNEG_B
+ 0U, // BNEG_D
+ 0U, // BNEG_H
+ 0U, // BNEG_W
+ 0U, // BNEL
+ 0U, // BNEZ16_MM
+ 0U, // BNEZALC
+ 0U, // BNEZALC_MMR6
+ 0U, // BNEZC
+ 0U, // BNEZC16_MMR6
+ 0U, // BNEZC64
+ 0U, // BNEZC_MM
+ 0U, // BNEZC_MMR6
+ 0U, // BNE_MM
+ 0U, // BNVC
+ 0U, // BNVC_MMR6
+ 0U, // BNZ_B
+ 0U, // BNZ_D
+ 0U, // BNZ_H
+ 0U, // BNZ_V
+ 0U, // BNZ_W
+ 0U, // BOVC
+ 0U, // BOVC_MMR6
+ 0U, // BPOSGE32
+ 0U, // BPOSGE32C_MMR3
+ 0U, // BPOSGE32_MM
+ 0U, // BREAK
+ 0U, // BREAK16_MM
+ 0U, // BREAK16_MMR6
+ 0U, // BREAK_MM
+ 0U, // BREAK_MMR6
+ 26U, // BSELI_B
+ 24U, // BSEL_V
+ 2U, // BSETI_B
+ 12U, // BSETI_D
+ 14U, // BSETI_H
+ 4U, // BSETI_W
+ 0U, // BSET_B
+ 0U, // BSET_D
+ 0U, // BSET_H
+ 0U, // BSET_W
+ 0U, // BZ_B
+ 0U, // BZ_D
+ 0U, // BZ_H
+ 0U, // BZ_V
+ 0U, // BZ_W
+ 0U, // BeqzRxImm16
+ 0U, // BeqzRxImmX16
+ 0U, // Bimm16
+ 0U, // BimmX16
+ 0U, // BnezRxImm16
+ 0U, // BnezRxImmX16
+ 0U, // Break16
+ 0U, // Bteqz16
+ 0U, // BteqzX16
+ 0U, // Btnez16
+ 0U, // BtnezX16
+ 0U, // CACHE
+ 0U, // CACHEE
+ 0U, // CACHEE_MM
+ 0U, // CACHE_MM
+ 0U, // CACHE_MMR6
+ 0U, // CACHE_R6
+ 0U, // CEIL_L_D64
+ 0U, // CEIL_L_D_MMR6
+ 0U, // CEIL_L_S
+ 0U, // CEIL_L_S_MMR6
+ 0U, // CEIL_W_D32
+ 0U, // CEIL_W_D64
+ 0U, // CEIL_W_D_MMR6
+ 0U, // CEIL_W_MM
+ 0U, // CEIL_W_S
+ 0U, // CEIL_W_S_MM
+ 0U, // CEIL_W_S_MMR6
+ 0U, // CEQI_B
+ 0U, // CEQI_D
+ 0U, // CEQI_H
+ 0U, // CEQI_W
+ 0U, // CEQ_B
+ 0U, // CEQ_D
+ 0U, // CEQ_H
+ 0U, // CEQ_W
+ 0U, // CFC1
+ 0U, // CFC1_MM
+ 0U, // CFC2_MM
+ 0U, // CFCMSA
+ 580U, // CINS
+ 580U, // CINS32
+ 580U, // CINS64_32
+ 580U, // CINS_i32
+ 0U, // CLASS_D
+ 0U, // CLASS_D_MMR6
+ 0U, // CLASS_S
+ 0U, // CLASS_S_MMR6
+ 0U, // CLEI_S_B
+ 0U, // CLEI_S_D
+ 0U, // CLEI_S_H
+ 0U, // CLEI_S_W
+ 4U, // CLEI_U_B
+ 4U, // CLEI_U_D
+ 4U, // CLEI_U_H
+ 4U, // CLEI_U_W
+ 0U, // CLE_S_B
+ 0U, // CLE_S_D
+ 0U, // CLE_S_H
+ 0U, // CLE_S_W
+ 0U, // CLE_U_B
+ 0U, // CLE_U_D
+ 0U, // CLE_U_H
+ 0U, // CLE_U_W
+ 0U, // CLO
+ 0U, // CLO_MM
+ 0U, // CLO_MMR6
+ 0U, // CLO_R6
+ 0U, // CLTI_S_B
+ 0U, // CLTI_S_D
+ 0U, // CLTI_S_H
+ 0U, // CLTI_S_W
+ 4U, // CLTI_U_B
+ 4U, // CLTI_U_D
+ 4U, // CLTI_U_H
+ 4U, // CLTI_U_W
+ 0U, // CLT_S_B
+ 0U, // CLT_S_D
+ 0U, // CLT_S_H
+ 0U, // CLT_S_W
+ 0U, // CLT_U_B
+ 0U, // CLT_U_D
+ 0U, // CLT_U_H
+ 0U, // CLT_U_W
+ 0U, // CLZ
+ 0U, // CLZ_MM
+ 0U, // CLZ_MMR6
+ 0U, // CLZ_R6
+ 0U, // CMPGDU_EQ_QB
+ 0U, // CMPGDU_EQ_QB_MMR2
+ 0U, // CMPGDU_LE_QB
+ 0U, // CMPGDU_LE_QB_MMR2
+ 0U, // CMPGDU_LT_QB
+ 0U, // CMPGDU_LT_QB_MMR2
+ 0U, // CMPGU_EQ_QB
+ 0U, // CMPGU_EQ_QB_MM
+ 0U, // CMPGU_LE_QB
+ 0U, // CMPGU_LE_QB_MM
+ 0U, // CMPGU_LT_QB
+ 0U, // CMPGU_LT_QB_MM
+ 0U, // CMPU_EQ_QB
+ 0U, // CMPU_EQ_QB_MM
+ 0U, // CMPU_LE_QB
+ 0U, // CMPU_LE_QB_MM
+ 0U, // CMPU_LT_QB
+ 0U, // CMPU_LT_QB_MM
+ 0U, // CMP_AF_D_MMR6
+ 0U, // CMP_AF_S_MMR6
+ 0U, // CMP_EQ_D
+ 0U, // CMP_EQ_D_MMR6
+ 0U, // CMP_EQ_PH
+ 0U, // CMP_EQ_PH_MM
+ 0U, // CMP_EQ_S
+ 0U, // CMP_EQ_S_MMR6
+ 0U, // CMP_F_D
+ 0U, // CMP_F_S
+ 0U, // CMP_LE_D
+ 0U, // CMP_LE_D_MMR6
+ 0U, // CMP_LE_PH
+ 0U, // CMP_LE_PH_MM
+ 0U, // CMP_LE_S
+ 0U, // CMP_LE_S_MMR6
+ 0U, // CMP_LT_D
+ 0U, // CMP_LT_D_MMR6
+ 0U, // CMP_LT_PH
+ 0U, // CMP_LT_PH_MM
+ 0U, // CMP_LT_S
+ 0U, // CMP_LT_S_MMR6
+ 0U, // CMP_SAF_D
+ 0U, // CMP_SAF_D_MMR6
+ 0U, // CMP_SAF_S
+ 0U, // CMP_SAF_S_MMR6
+ 0U, // CMP_SEQ_D
+ 0U, // CMP_SEQ_D_MMR6
+ 0U, // CMP_SEQ_S
+ 0U, // CMP_SEQ_S_MMR6
+ 0U, // CMP_SLE_D
+ 0U, // CMP_SLE_D_MMR6
+ 0U, // CMP_SLE_S
+ 0U, // CMP_SLE_S_MMR6
+ 0U, // CMP_SLT_D
+ 0U, // CMP_SLT_D_MMR6
+ 0U, // CMP_SLT_S
+ 0U, // CMP_SLT_S_MMR6
+ 0U, // CMP_SUEQ_D
+ 0U, // CMP_SUEQ_D_MMR6
+ 0U, // CMP_SUEQ_S
+ 0U, // CMP_SUEQ_S_MMR6
+ 0U, // CMP_SULE_D
+ 0U, // CMP_SULE_D_MMR6
+ 0U, // CMP_SULE_S
+ 0U, // CMP_SULE_S_MMR6
+ 0U, // CMP_SULT_D
+ 0U, // CMP_SULT_D_MMR6
+ 0U, // CMP_SULT_S
+ 0U, // CMP_SULT_S_MMR6
+ 0U, // CMP_SUN_D
+ 0U, // CMP_SUN_D_MMR6
+ 0U, // CMP_SUN_S
+ 0U, // CMP_SUN_S_MMR6
+ 0U, // CMP_UEQ_D
+ 0U, // CMP_UEQ_D_MMR6
+ 0U, // CMP_UEQ_S
+ 0U, // CMP_UEQ_S_MMR6
+ 0U, // CMP_ULE_D
+ 0U, // CMP_ULE_D_MMR6
+ 0U, // CMP_ULE_S
+ 0U, // CMP_ULE_S_MMR6
+ 0U, // CMP_ULT_D
+ 0U, // CMP_ULT_D_MMR6
+ 0U, // CMP_ULT_S
+ 0U, // CMP_ULT_S_MMR6
+ 0U, // CMP_UN_D
+ 0U, // CMP_UN_D_MMR6
+ 0U, // CMP_UN_S
+ 0U, // CMP_UN_S_MMR6
+ 142U, // COPY_S_B
+ 156U, // COPY_S_D
+ 130U, // COPY_S_H
+ 138U, // COPY_S_W
+ 142U, // COPY_U_B
+ 130U, // COPY_U_H
+ 138U, // COPY_U_W
+ 0U, // CRC32B
+ 0U, // CRC32CB
+ 0U, // CRC32CD
+ 0U, // CRC32CH
+ 0U, // CRC32CW
+ 0U, // CRC32D
+ 0U, // CRC32H
+ 0U, // CRC32W
+ 0U, // CTC1
+ 0U, // CTC1_MM
+ 0U, // CTC2_MM
+ 0U, // CTCMSA
+ 0U, // CVT_D32_S
+ 0U, // CVT_D32_S_MM
+ 0U, // CVT_D32_W
+ 0U, // CVT_D32_W_MM
+ 0U, // CVT_D64_L
+ 0U, // CVT_D64_S
+ 0U, // CVT_D64_S_MM
+ 0U, // CVT_D64_W
+ 0U, // CVT_D64_W_MM
+ 0U, // CVT_D_L_MMR6
+ 0U, // CVT_L_D64
+ 0U, // CVT_L_D64_MM
+ 0U, // CVT_L_D_MMR6
+ 0U, // CVT_L_S
+ 0U, // CVT_L_S_MM
+ 0U, // CVT_L_S_MMR6
+ 0U, // CVT_S_D32
+ 0U, // CVT_S_D32_MM
+ 0U, // CVT_S_D64
+ 0U, // CVT_S_D64_MM
+ 0U, // CVT_S_L
+ 0U, // CVT_S_L_MMR6
+ 0U, // CVT_S_W
+ 0U, // CVT_S_W_MM
+ 0U, // CVT_S_W_MMR6
+ 0U, // CVT_W_D32
+ 0U, // CVT_W_D32_MM
+ 0U, // CVT_W_D64
+ 0U, // CVT_W_D64_MM
+ 0U, // CVT_W_S
+ 0U, // CVT_W_S_MM
+ 0U, // CVT_W_S_MMR6
+ 0U, // C_EQ_D32
+ 0U, // C_EQ_D32_MM
+ 0U, // C_EQ_D64
+ 0U, // C_EQ_D64_MM
+ 0U, // C_EQ_S
+ 0U, // C_EQ_S_MM
+ 0U, // C_F_D32
+ 0U, // C_F_D32_MM
+ 0U, // C_F_D64
+ 0U, // C_F_D64_MM
+ 0U, // C_F_S
+ 0U, // C_F_S_MM
+ 0U, // C_LE_D32
+ 0U, // C_LE_D32_MM
+ 0U, // C_LE_D64
+ 0U, // C_LE_D64_MM
+ 0U, // C_LE_S
+ 0U, // C_LE_S_MM
+ 0U, // C_LT_D32
+ 0U, // C_LT_D32_MM
+ 0U, // C_LT_D64
+ 0U, // C_LT_D64_MM
+ 0U, // C_LT_S
+ 0U, // C_LT_S_MM
+ 0U, // C_NGE_D32
+ 0U, // C_NGE_D32_MM
+ 0U, // C_NGE_D64
+ 0U, // C_NGE_D64_MM
+ 0U, // C_NGE_S
+ 0U, // C_NGE_S_MM
+ 0U, // C_NGLE_D32
+ 0U, // C_NGLE_D32_MM
+ 0U, // C_NGLE_D64
+ 0U, // C_NGLE_D64_MM
+ 0U, // C_NGLE_S
+ 0U, // C_NGLE_S_MM
+ 0U, // C_NGL_D32
+ 0U, // C_NGL_D32_MM
+ 0U, // C_NGL_D64
+ 0U, // C_NGL_D64_MM
+ 0U, // C_NGL_S
+ 0U, // C_NGL_S_MM
+ 0U, // C_NGT_D32
+ 0U, // C_NGT_D32_MM
+ 0U, // C_NGT_D64
+ 0U, // C_NGT_D64_MM
+ 0U, // C_NGT_S
+ 0U, // C_NGT_S_MM
+ 0U, // C_OLE_D32
+ 0U, // C_OLE_D32_MM
+ 0U, // C_OLE_D64
+ 0U, // C_OLE_D64_MM
+ 0U, // C_OLE_S
+ 0U, // C_OLE_S_MM
+ 0U, // C_OLT_D32
+ 0U, // C_OLT_D32_MM
+ 0U, // C_OLT_D64
+ 0U, // C_OLT_D64_MM
+ 0U, // C_OLT_S
+ 0U, // C_OLT_S_MM
+ 0U, // C_SEQ_D32
+ 0U, // C_SEQ_D32_MM
+ 0U, // C_SEQ_D64
+ 0U, // C_SEQ_D64_MM
+ 0U, // C_SEQ_S
+ 0U, // C_SEQ_S_MM
+ 0U, // C_SF_D32
+ 0U, // C_SF_D32_MM
+ 0U, // C_SF_D64
+ 0U, // C_SF_D64_MM
+ 0U, // C_SF_S
+ 0U, // C_SF_S_MM
+ 0U, // C_UEQ_D32
+ 0U, // C_UEQ_D32_MM
+ 0U, // C_UEQ_D64
+ 0U, // C_UEQ_D64_MM
+ 0U, // C_UEQ_S
+ 0U, // C_UEQ_S_MM
+ 0U, // C_ULE_D32
+ 0U, // C_ULE_D32_MM
+ 0U, // C_ULE_D64
+ 0U, // C_ULE_D64_MM
+ 0U, // C_ULE_S
+ 0U, // C_ULE_S_MM
+ 0U, // C_ULT_D32
+ 0U, // C_ULT_D32_MM
+ 0U, // C_ULT_D64
+ 0U, // C_ULT_D64_MM
+ 0U, // C_ULT_S
+ 0U, // C_ULT_S_MM
+ 0U, // C_UN_D32
+ 0U, // C_UN_D32_MM
+ 0U, // C_UN_D64
+ 0U, // C_UN_D64_MM
+ 0U, // C_UN_S
+ 0U, // C_UN_S_MM
+ 0U, // CmpRxRy16
+ 0U, // CmpiRxImm16
+ 0U, // CmpiRxImmX16
+ 0U, // DADD
+ 0U, // DADDi
+ 0U, // DADDiu
+ 0U, // DADDu
+ 8U, // DAHI
+ 1088U, // DALIGN
+ 8U, // DATI
+ 8U, // DAUI
+ 0U, // DBITSWAP
+ 0U, // DCLO
+ 0U, // DCLO_R6
+ 0U, // DCLZ
+ 0U, // DCLZ_R6
+ 0U, // DDIV
+ 0U, // DDIVU
+ 0U, // DERET
+ 0U, // DERET_MM
+ 0U, // DERET_MMR6
+ 1612U, // DEXT
+ 2124U, // DEXT64_32
+ 2628U, // DEXTM
+ 222U, // DEXTU
+ 0U, // DI
+ 3148U, // DINS
+ 3652U, // DINSM
+ 286U, // DINSU
+ 0U, // DIV
+ 0U, // DIVU
+ 0U, // DIVU_MMR6
+ 0U, // DIV_MMR6
+ 0U, // DIV_S_B
+ 0U, // DIV_S_D
+ 0U, // DIV_S_H
+ 0U, // DIV_S_W
+ 0U, // DIV_U_B
+ 0U, // DIV_U_D
+ 0U, // DIV_U_H
+ 0U, // DIV_U_W
+ 0U, // DI_MM
+ 0U, // DI_MMR6
+ 4160U, // DLSA
+ 4160U, // DLSA_R6
+ 2U, // DMFC0
+ 0U, // DMFC1
+ 2U, // DMFC2
+ 0U, // DMFC2_OCTEON
+ 2U, // DMFGC0
+ 0U, // DMOD
+ 0U, // DMODU
+ 0U, // DMT
+ 0U, // DMTC0
+ 0U, // DMTC1
+ 0U, // DMTC2
+ 0U, // DMTC2_OCTEON
+ 0U, // DMTGC0
+ 0U, // DMUH
+ 0U, // DMUHU
+ 0U, // DMUL
+ 0U, // DMULT
+ 0U, // DMULTu
+ 0U, // DMULU
+ 0U, // DMUL_R6
+ 0U, // DOTP_S_D
+ 0U, // DOTP_S_H
+ 0U, // DOTP_S_W
+ 0U, // DOTP_U_D
+ 0U, // DOTP_U_H
+ 0U, // DOTP_U_W
+ 24U, // DPADD_S_D
+ 24U, // DPADD_S_H
+ 24U, // DPADD_S_W
+ 24U, // DPADD_U_D
+ 24U, // DPADD_U_H
+ 24U, // DPADD_U_W
+ 0U, // DPAQX_SA_W_PH
+ 0U, // DPAQX_SA_W_PH_MMR2
+ 0U, // DPAQX_S_W_PH
+ 0U, // DPAQX_S_W_PH_MMR2
+ 0U, // DPAQ_SA_L_W
+ 0U, // DPAQ_SA_L_W_MM
+ 0U, // DPAQ_S_W_PH
+ 0U, // DPAQ_S_W_PH_MM
+ 0U, // DPAU_H_QBL
+ 0U, // DPAU_H_QBL_MM
+ 0U, // DPAU_H_QBR
+ 0U, // DPAU_H_QBR_MM
+ 0U, // DPAX_W_PH
+ 0U, // DPAX_W_PH_MMR2
+ 0U, // DPA_W_PH
+ 0U, // DPA_W_PH_MMR2
+ 0U, // DPOP
+ 0U, // DPSQX_SA_W_PH
+ 0U, // DPSQX_SA_W_PH_MMR2
+ 0U, // DPSQX_S_W_PH
+ 0U, // DPSQX_S_W_PH_MMR2
+ 0U, // DPSQ_SA_L_W
+ 0U, // DPSQ_SA_L_W_MM
+ 0U, // DPSQ_S_W_PH
+ 0U, // DPSQ_S_W_PH_MM
+ 24U, // DPSUB_S_D
+ 24U, // DPSUB_S_H
+ 24U, // DPSUB_S_W
+ 24U, // DPSUB_U_D
+ 24U, // DPSUB_U_H
+ 24U, // DPSUB_U_W
+ 0U, // DPSU_H_QBL
+ 0U, // DPSU_H_QBL_MM
+ 0U, // DPSU_H_QBR
+ 0U, // DPSU_H_QBR_MM
+ 0U, // DPSX_W_PH
+ 0U, // DPSX_W_PH_MMR2
+ 0U, // DPS_W_PH
+ 0U, // DPS_W_PH_MMR2
+ 12U, // DROTR
+ 4U, // DROTR32
+ 0U, // DROTRV
+ 0U, // DSBH
+ 0U, // DSDIV
+ 0U, // DSHD
+ 12U, // DSLL
+ 4U, // DSLL32
+ 0U, // DSLL64_32
+ 0U, // DSLLV
+ 12U, // DSRA
+ 4U, // DSRA32
+ 0U, // DSRAV
+ 12U, // DSRL
+ 4U, // DSRL32
+ 0U, // DSRLV
+ 0U, // DSUB
+ 0U, // DSUBu
+ 0U, // DUDIV
+ 0U, // DVP
+ 0U, // DVPE
+ 0U, // DVP_MMR6
+ 0U, // DivRxRy16
+ 0U, // DivuRxRy16
+ 0U, // EHB
+ 0U, // EHB_MM
+ 0U, // EHB_MMR6
+ 0U, // EI
+ 0U, // EI_MM
+ 0U, // EI_MMR6
+ 0U, // EMT
+ 0U, // ERET
+ 0U, // ERETNC
+ 0U, // ERETNC_MMR6
+ 0U, // ERET_MM
+ 0U, // ERET_MMR6
+ 0U, // EVP
+ 0U, // EVPE
+ 0U, // EVP_MMR6
+ 2116U, // EXT
+ 4U, // EXTP
+ 4U, // EXTPDP
+ 0U, // EXTPDPV
+ 0U, // EXTPDPV_MM
+ 4U, // EXTPDP_MM
+ 0U, // EXTPV
+ 0U, // EXTPV_MM
+ 4U, // EXTP_MM
+ 0U, // EXTRV_RS_W
+ 0U, // EXTRV_RS_W_MM
+ 0U, // EXTRV_R_W
+ 0U, // EXTRV_R_W_MM
+ 0U, // EXTRV_S_H
+ 0U, // EXTRV_S_H_MM
+ 0U, // EXTRV_W
+ 0U, // EXTRV_W_MM
+ 4U, // EXTR_RS_W
+ 4U, // EXTR_RS_W_MM
+ 4U, // EXTR_R_W
+ 4U, // EXTR_R_W_MM
+ 4U, // EXTR_S_H
+ 4U, // EXTR_S_H_MM
+ 4U, // EXTR_W
+ 4U, // EXTR_W_MM
+ 580U, // EXTS
+ 580U, // EXTS32
+ 2116U, // EXT_MM
+ 2116U, // EXT_MMR6
+ 0U, // FABS_D32
+ 0U, // FABS_D32_MM
+ 0U, // FABS_D64
+ 0U, // FABS_D64_MM
+ 0U, // FABS_S
+ 0U, // FABS_S_MM
+ 0U, // FADD_D
+ 0U, // FADD_D32
+ 0U, // FADD_D32_MM
+ 0U, // FADD_D64
+ 0U, // FADD_D64_MM
+ 0U, // FADD_S
+ 0U, // FADD_S_MM
+ 32U, // FADD_S_MMR6
+ 0U, // FADD_W
+ 0U, // FCAF_D
+ 0U, // FCAF_W
+ 0U, // FCEQ_D
+ 0U, // FCEQ_W
+ 0U, // FCLASS_D
+ 0U, // FCLASS_W
+ 0U, // FCLE_D
+ 0U, // FCLE_W
+ 0U, // FCLT_D
+ 0U, // FCLT_W
+ 0U, // FCMP_D32
+ 0U, // FCMP_D32_MM
+ 0U, // FCMP_D64
+ 0U, // FCMP_S32
+ 0U, // FCMP_S32_MM
+ 0U, // FCNE_D
+ 0U, // FCNE_W
+ 0U, // FCOR_D
+ 0U, // FCOR_W
+ 0U, // FCUEQ_D
+ 0U, // FCUEQ_W
+ 0U, // FCULE_D
+ 0U, // FCULE_W
+ 0U, // FCULT_D
+ 0U, // FCULT_W
+ 0U, // FCUNE_D
+ 0U, // FCUNE_W
+ 0U, // FCUN_D
+ 0U, // FCUN_W
+ 0U, // FDIV_D
+ 0U, // FDIV_D32
+ 0U, // FDIV_D32_MM
+ 0U, // FDIV_D64
+ 0U, // FDIV_D64_MM
+ 0U, // FDIV_S
+ 0U, // FDIV_S_MM
+ 32U, // FDIV_S_MMR6
+ 0U, // FDIV_W
+ 0U, // FEXDO_H
+ 0U, // FEXDO_W
+ 0U, // FEXP2_D
+ 0U, // FEXP2_W
+ 0U, // FEXUPL_D
+ 0U, // FEXUPL_W
+ 0U, // FEXUPR_D
+ 0U, // FEXUPR_W
+ 0U, // FFINT_S_D
+ 0U, // FFINT_S_W
+ 0U, // FFINT_U_D
+ 0U, // FFINT_U_W
+ 0U, // FFQL_D
+ 0U, // FFQL_W
+ 0U, // FFQR_D
+ 0U, // FFQR_W
+ 0U, // FILL_B
+ 0U, // FILL_D
+ 0U, // FILL_H
+ 0U, // FILL_W
+ 0U, // FLOG2_D
+ 0U, // FLOG2_W
+ 0U, // FLOOR_L_D64
+ 0U, // FLOOR_L_D_MMR6
+ 0U, // FLOOR_L_S
+ 0U, // FLOOR_L_S_MMR6
+ 0U, // FLOOR_W_D32
+ 0U, // FLOOR_W_D64
+ 0U, // FLOOR_W_D_MMR6
+ 0U, // FLOOR_W_MM
+ 0U, // FLOOR_W_S
+ 0U, // FLOOR_W_S_MM
+ 0U, // FLOOR_W_S_MMR6
+ 24U, // FMADD_D
+ 24U, // FMADD_W
+ 0U, // FMAX_A_D
+ 0U, // FMAX_A_W
+ 0U, // FMAX_D
+ 0U, // FMAX_W
+ 0U, // FMIN_A_D
+ 0U, // FMIN_A_W
+ 0U, // FMIN_D
+ 0U, // FMIN_W
+ 0U, // FMOV_D32
+ 0U, // FMOV_D32_MM
+ 0U, // FMOV_D64
+ 0U, // FMOV_D64_MM
+ 0U, // FMOV_S
+ 0U, // FMOV_S_MM
+ 0U, // FMOV_S_MMR6
+ 24U, // FMSUB_D
+ 24U, // FMSUB_W
+ 0U, // FMUL_D
+ 0U, // FMUL_D32
+ 0U, // FMUL_D32_MM
+ 0U, // FMUL_D64
+ 0U, // FMUL_D64_MM
+ 0U, // FMUL_S
+ 0U, // FMUL_S_MM
+ 32U, // FMUL_S_MMR6
+ 0U, // FMUL_W
+ 0U, // FNEG_D32
+ 0U, // FNEG_D32_MM
+ 0U, // FNEG_D64
+ 0U, // FNEG_D64_MM
+ 0U, // FNEG_S
+ 0U, // FNEG_S_MM
+ 0U, // FNEG_S_MMR6
+ 0U, // FORK
+ 0U, // FRCP_D
+ 0U, // FRCP_W
+ 0U, // FRINT_D
+ 0U, // FRINT_W
+ 0U, // FRSQRT_D
+ 0U, // FRSQRT_W
+ 0U, // FSAF_D
+ 0U, // FSAF_W
+ 0U, // FSEQ_D
+ 0U, // FSEQ_W
+ 0U, // FSLE_D
+ 0U, // FSLE_W
+ 0U, // FSLT_D
+ 0U, // FSLT_W
+ 0U, // FSNE_D
+ 0U, // FSNE_W
+ 0U, // FSOR_D
+ 0U, // FSOR_W
+ 0U, // FSQRT_D
+ 0U, // FSQRT_D32
+ 0U, // FSQRT_D32_MM
+ 0U, // FSQRT_D64
+ 0U, // FSQRT_D64_MM
+ 0U, // FSQRT_S
+ 0U, // FSQRT_S_MM
+ 0U, // FSQRT_W
+ 0U, // FSUB_D
+ 0U, // FSUB_D32
+ 0U, // FSUB_D32_MM
+ 0U, // FSUB_D64
+ 0U, // FSUB_D64_MM
+ 0U, // FSUB_S
+ 0U, // FSUB_S_MM
+ 32U, // FSUB_S_MMR6
+ 0U, // FSUB_W
+ 0U, // FSUEQ_D
+ 0U, // FSUEQ_W
+ 0U, // FSULE_D
+ 0U, // FSULE_W
+ 0U, // FSULT_D
+ 0U, // FSULT_W
+ 0U, // FSUNE_D
+ 0U, // FSUNE_W
+ 0U, // FSUN_D
+ 0U, // FSUN_W
+ 0U, // FTINT_S_D
+ 0U, // FTINT_S_W
+ 0U, // FTINT_U_D
+ 0U, // FTINT_U_W
+ 0U, // FTQ_H
+ 0U, // FTQ_W
+ 0U, // FTRUNC_S_D
+ 0U, // FTRUNC_S_W
+ 0U, // FTRUNC_U_D
+ 0U, // FTRUNC_U_W
+ 0U, // GINVI
+ 0U, // GINVI_MMR6
+ 0U, // GINVT
+ 0U, // GINVT_MMR6
+ 0U, // HADD_S_D
+ 0U, // HADD_S_H
+ 0U, // HADD_S_W
+ 0U, // HADD_U_D
+ 0U, // HADD_U_H
+ 0U, // HADD_U_W
+ 0U, // HSUB_S_D
+ 0U, // HSUB_S_H
+ 0U, // HSUB_S_W
+ 0U, // HSUB_U_D
+ 0U, // HSUB_U_H
+ 0U, // HSUB_U_W
+ 0U, // HYPCALL
+ 0U, // HYPCALL_MM
+ 0U, // ILVEV_B
+ 0U, // ILVEV_D
+ 0U, // ILVEV_H
+ 0U, // ILVEV_W
+ 0U, // ILVL_B
+ 0U, // ILVL_D
+ 0U, // ILVL_H
+ 0U, // ILVL_W
+ 0U, // ILVOD_B
+ 0U, // ILVOD_D
+ 0U, // ILVOD_H
+ 0U, // ILVOD_W
+ 0U, // ILVR_B
+ 0U, // ILVR_D
+ 0U, // ILVR_H
+ 0U, // ILVR_W
+ 3140U, // INS
+ 0U, // INSERT_B
+ 0U, // INSERT_D
+ 0U, // INSERT_H
+ 0U, // INSERT_W
+ 0U, // INSV
+ 0U, // INSVE_B
+ 0U, // INSVE_D
+ 0U, // INSVE_H
+ 0U, // INSVE_W
+ 0U, // INSV_MM
+ 3140U, // INS_MM
+ 3140U, // INS_MMR6
+ 0U, // J
+ 0U, // JAL
+ 0U, // JALR
+ 0U, // JALR16_MM
+ 0U, // JALR64
+ 0U, // JALRC16_MMR6
+ 0U, // JALRC_HB_MMR6
+ 0U, // JALRC_MMR6
+ 0U, // JALRS16_MM
+ 0U, // JALRS_MM
+ 0U, // JALR_HB
+ 0U, // JALR_HB64
+ 0U, // JALR_MM
+ 0U, // JALS_MM
+ 0U, // JALX
+ 0U, // JALX_MM
+ 0U, // JAL_MM
+ 0U, // JIALC
+ 0U, // JIALC64
+ 0U, // JIALC_MMR6
+ 0U, // JIC
+ 0U, // JIC64
+ 0U, // JIC_MMR6
+ 0U, // JR
+ 0U, // JR16_MM
+ 0U, // JR64
+ 0U, // JRADDIUSP
+ 0U, // JRC16_MM
+ 0U, // JRC16_MMR6
+ 0U, // JRCADDIUSP_MMR6
+ 0U, // JR_HB
+ 0U, // JR_HB64
+ 0U, // JR_HB64_R6
+ 0U, // JR_HB_R6
+ 0U, // JR_MM
+ 0U, // J_MM
+ 0U, // Jal16
+ 0U, // JalB16
+ 0U, // JrRa16
+ 0U, // JrcRa16
+ 0U, // JrcRx16
+ 0U, // JumpLinkReg16
+ 0U, // LB
+ 0U, // LB64
+ 0U, // LBE
+ 0U, // LBE_MM
+ 0U, // LBU16_MM
+ 0U, // LBUX
+ 0U, // LBUX_MM
+ 0U, // LBU_MMR6
+ 0U, // LB_MM
+ 0U, // LB_MMR6
+ 0U, // LBu
+ 0U, // LBu64
+ 0U, // LBuE
+ 0U, // LBuE_MM
+ 0U, // LBu_MM
+ 0U, // LD
+ 0U, // LDC1
+ 0U, // LDC164
+ 0U, // LDC1_D64_MMR6
+ 0U, // LDC1_MM
+ 0U, // LDC2
+ 0U, // LDC2_MMR6
+ 0U, // LDC2_R6
+ 0U, // LDC3
+ 0U, // LDI_B
+ 0U, // LDI_D
+ 0U, // LDI_H
+ 0U, // LDI_W
+ 0U, // LDL
+ 0U, // LDPC
+ 0U, // LDR
+ 0U, // LDXC1
+ 0U, // LDXC164
+ 0U, // LD_B
+ 0U, // LD_D
+ 0U, // LD_H
+ 0U, // LD_W
+ 0U, // LEA_ADDiu
+ 0U, // LEA_ADDiu64
+ 0U, // LEA_ADDiu_MM
+ 0U, // LH
+ 0U, // LH64
+ 0U, // LHE
+ 0U, // LHE_MM
+ 0U, // LHU16_MM
+ 0U, // LHX
+ 0U, // LHX_MM
+ 0U, // LH_MM
+ 0U, // LHu
+ 0U, // LHu64
+ 0U, // LHuE
+ 0U, // LHuE_MM
+ 0U, // LHu_MM
+ 0U, // LI16_MM
+ 0U, // LI16_MMR6
+ 0U, // LL
+ 0U, // LL64
+ 0U, // LL64_R6
+ 0U, // LLD
+ 0U, // LLD_R6
+ 0U, // LLE
+ 0U, // LLE_MM
+ 0U, // LL_MM
+ 0U, // LL_MMR6
+ 0U, // LL_R6
+ 4160U, // LSA
+ 0U, // LSA_MMR6
+ 4160U, // LSA_R6
+ 0U, // LUI_MMR6
+ 0U, // LUXC1
+ 0U, // LUXC164
+ 0U, // LUXC1_MM
+ 0U, // LUi
+ 0U, // LUi64
+ 0U, // LUi_MM
+ 0U, // LW
+ 0U, // LW16_MM
+ 0U, // LW64
+ 0U, // LWC1
+ 0U, // LWC1_MM
+ 0U, // LWC2
+ 0U, // LWC2_MMR6
+ 0U, // LWC2_R6
+ 0U, // LWC3
+ 0U, // LWDSP
+ 0U, // LWDSP_MM
+ 0U, // LWE
+ 0U, // LWE_MM
+ 0U, // LWGP_MM
+ 0U, // LWL
+ 0U, // LWL64
+ 0U, // LWLE
+ 0U, // LWLE_MM
+ 0U, // LWL_MM
+ 0U, // LWM16_MM
+ 0U, // LWM16_MMR6
+ 0U, // LWM32_MM
+ 0U, // LWPC
+ 0U, // LWPC_MMR6
+ 0U, // LWP_MM
+ 0U, // LWR
+ 0U, // LWR64
+ 0U, // LWRE
+ 0U, // LWRE_MM
+ 0U, // LWR_MM
+ 0U, // LWSP_MM
+ 0U, // LWUPC
+ 0U, // LWU_MM
+ 0U, // LWX
+ 0U, // LWXC1
+ 0U, // LWXC1_MM
+ 0U, // LWXS_MM
+ 0U, // LWX_MM
+ 0U, // LW_MM
+ 0U, // LW_MMR6
+ 0U, // LWu
+ 0U, // LbRxRyOffMemX16
+ 0U, // LbuRxRyOffMemX16
+ 0U, // LhRxRyOffMemX16
+ 0U, // LhuRxRyOffMemX16
+ 0U, // LiRxImm16
+ 0U, // LiRxImmAlignX16
+ 0U, // LiRxImmX16
+ 0U, // LwRxPcTcp16
+ 0U, // LwRxPcTcpX16
+ 0U, // LwRxRyOffMemX16
+ 0U, // LwRxSpImmX16
+ 0U, // MADD
+ 24U, // MADDF_D
+ 24U, // MADDF_D_MMR6
+ 24U, // MADDF_S
+ 24U, // MADDF_S_MMR6
+ 24U, // MADDR_Q_H
+ 24U, // MADDR_Q_W
+ 0U, // MADDU
+ 0U, // MADDU_DSP
+ 0U, // MADDU_DSP_MM
+ 0U, // MADDU_MM
+ 24U, // MADDV_B
+ 24U, // MADDV_D
+ 24U, // MADDV_H
+ 24U, // MADDV_W
+ 4672U, // MADD_D32
+ 4672U, // MADD_D32_MM
+ 4672U, // MADD_D64
+ 0U, // MADD_DSP
+ 0U, // MADD_DSP_MM
+ 0U, // MADD_MM
+ 24U, // MADD_Q_H
+ 24U, // MADD_Q_W
+ 4672U, // MADD_S
+ 4672U, // MADD_S_MM
+ 0U, // MAQ_SA_W_PHL
+ 0U, // MAQ_SA_W_PHL_MM
+ 0U, // MAQ_SA_W_PHR
+ 0U, // MAQ_SA_W_PHR_MM
+ 0U, // MAQ_S_W_PHL
+ 0U, // MAQ_S_W_PHL_MM
+ 0U, // MAQ_S_W_PHR
+ 0U, // MAQ_S_W_PHR_MM
+ 0U, // MAXA_D
+ 0U, // MAXA_D_MMR6
+ 0U, // MAXA_S
+ 0U, // MAXA_S_MMR6
+ 0U, // MAXI_S_B
+ 0U, // MAXI_S_D
+ 0U, // MAXI_S_H
+ 0U, // MAXI_S_W
+ 4U, // MAXI_U_B
+ 4U, // MAXI_U_D
+ 4U, // MAXI_U_H
+ 4U, // MAXI_U_W
+ 0U, // MAX_A_B
+ 0U, // MAX_A_D
+ 0U, // MAX_A_H
+ 0U, // MAX_A_W
+ 0U, // MAX_D
+ 0U, // MAX_D_MMR6
+ 0U, // MAX_S
+ 0U, // MAX_S_B
+ 0U, // MAX_S_D
+ 0U, // MAX_S_H
+ 0U, // MAX_S_MMR6
+ 0U, // MAX_S_W
+ 0U, // MAX_U_B
+ 0U, // MAX_U_D
+ 0U, // MAX_U_H
+ 0U, // MAX_U_W
+ 2U, // MFC0
+ 2U, // MFC0_MMR6
+ 0U, // MFC1
+ 0U, // MFC1_D64
+ 0U, // MFC1_MM
+ 0U, // MFC1_MMR6
+ 2U, // MFC2
+ 0U, // MFC2_MMR6
+ 2U, // MFGC0
+ 2U, // MFGC0_MM
+ 2U, // MFHC0_MMR6
+ 0U, // MFHC1_D32
+ 0U, // MFHC1_D32_MM
+ 0U, // MFHC1_D64
+ 0U, // MFHC1_D64_MM
+ 0U, // MFHC2_MMR6
+ 2U, // MFHGC0
+ 2U, // MFHGC0_MM
+ 0U, // MFHI
+ 0U, // MFHI16_MM
+ 0U, // MFHI64
+ 0U, // MFHI_DSP
+ 0U, // MFHI_DSP_MM
+ 0U, // MFHI_MM
+ 0U, // MFLO
+ 0U, // MFLO16_MM
+ 0U, // MFLO64
+ 0U, // MFLO_DSP
+ 0U, // MFLO_DSP_MM
+ 0U, // MFLO_MM
+ 9308U, // MFTR
+ 0U, // MINA_D
+ 0U, // MINA_D_MMR6
+ 0U, // MINA_S
+ 0U, // MINA_S_MMR6
+ 0U, // MINI_S_B
+ 0U, // MINI_S_D
+ 0U, // MINI_S_H
+ 0U, // MINI_S_W
+ 4U, // MINI_U_B
+ 4U, // MINI_U_D
+ 4U, // MINI_U_H
+ 4U, // MINI_U_W
+ 0U, // MIN_A_B
+ 0U, // MIN_A_D
+ 0U, // MIN_A_H
+ 0U, // MIN_A_W
+ 0U, // MIN_D
+ 0U, // MIN_D_MMR6
+ 0U, // MIN_S
+ 0U, // MIN_S_B
+ 0U, // MIN_S_D
+ 0U, // MIN_S_H
+ 0U, // MIN_S_MMR6
+ 0U, // MIN_S_W
+ 0U, // MIN_U_B
+ 0U, // MIN_U_D
+ 0U, // MIN_U_H
+ 0U, // MIN_U_W
+ 0U, // MOD
+ 0U, // MODSUB
+ 0U, // MODSUB_MM
+ 0U, // MODU
+ 0U, // MODU_MMR6
+ 0U, // MOD_MMR6
+ 0U, // MOD_S_B
+ 0U, // MOD_S_D
+ 0U, // MOD_S_H
+ 0U, // MOD_S_W
+ 0U, // MOD_U_B
+ 0U, // MOD_U_D
+ 0U, // MOD_U_H
+ 0U, // MOD_U_W
+ 0U, // MOVE16_MM
+ 0U, // MOVE16_MMR6
+ 1U, // MOVEP_MM
+ 1U, // MOVEP_MMR6
+ 0U, // MOVE_V
+ 0U, // MOVF_D32
+ 0U, // MOVF_D32_MM
+ 0U, // MOVF_D64
+ 0U, // MOVF_I
+ 0U, // MOVF_I64
+ 0U, // MOVF_I_MM
+ 0U, // MOVF_S
+ 0U, // MOVF_S_MM
+ 0U, // MOVN_I64_D64
+ 0U, // MOVN_I64_I
+ 0U, // MOVN_I64_I64
+ 0U, // MOVN_I64_S
+ 0U, // MOVN_I_D32
+ 0U, // MOVN_I_D32_MM
+ 0U, // MOVN_I_D64
+ 0U, // MOVN_I_I
+ 0U, // MOVN_I_I64
+ 0U, // MOVN_I_MM
+ 0U, // MOVN_I_S
+ 0U, // MOVN_I_S_MM
+ 0U, // MOVT_D32
+ 0U, // MOVT_D32_MM
+ 0U, // MOVT_D64
+ 0U, // MOVT_I
+ 0U, // MOVT_I64
+ 0U, // MOVT_I_MM
+ 0U, // MOVT_S
+ 0U, // MOVT_S_MM
+ 0U, // MOVZ_I64_D64
+ 0U, // MOVZ_I64_I
+ 0U, // MOVZ_I64_I64
+ 0U, // MOVZ_I64_S
+ 0U, // MOVZ_I_D32
+ 0U, // MOVZ_I_D32_MM
+ 0U, // MOVZ_I_D64
+ 0U, // MOVZ_I_I
+ 0U, // MOVZ_I_I64
+ 0U, // MOVZ_I_MM
+ 0U, // MOVZ_I_S
+ 0U, // MOVZ_I_S_MM
+ 0U, // MSUB
+ 24U, // MSUBF_D
+ 24U, // MSUBF_D_MMR6
+ 24U, // MSUBF_S
+ 24U, // MSUBF_S_MMR6
+ 24U, // MSUBR_Q_H
+ 24U, // MSUBR_Q_W
+ 0U, // MSUBU
+ 0U, // MSUBU_DSP
+ 0U, // MSUBU_DSP_MM
+ 0U, // MSUBU_MM
+ 24U, // MSUBV_B
+ 24U, // MSUBV_D
+ 24U, // MSUBV_H
+ 24U, // MSUBV_W
+ 4672U, // MSUB_D32
+ 4672U, // MSUB_D32_MM
+ 4672U, // MSUB_D64
+ 0U, // MSUB_DSP
+ 0U, // MSUB_DSP_MM
+ 0U, // MSUB_MM
+ 24U, // MSUB_Q_H
+ 24U, // MSUB_Q_W
+ 4672U, // MSUB_S
+ 4672U, // MSUB_S_MM
+ 0U, // MTC0
+ 0U, // MTC0_MMR6
+ 0U, // MTC1
+ 0U, // MTC1_D64
+ 0U, // MTC1_MM
+ 0U, // MTC1_MMR6
+ 0U, // MTC2
+ 0U, // MTC2_MMR6
+ 0U, // MTGC0
+ 0U, // MTGC0_MM
+ 0U, // MTHC0_MMR6
+ 0U, // MTHC1_D32
+ 0U, // MTHC1_D32_MM
+ 0U, // MTHC1_D64
+ 0U, // MTHC1_D64_MM
+ 0U, // MTHC2_MMR6
+ 0U, // MTHGC0
+ 0U, // MTHGC0_MM
+ 0U, // MTHI
+ 0U, // MTHI64
+ 0U, // MTHI_DSP
+ 0U, // MTHI_DSP_MM
+ 0U, // MTHI_MM
+ 0U, // MTHLIP
+ 0U, // MTHLIP_MM
+ 0U, // MTLO
+ 0U, // MTLO64
+ 0U, // MTLO_DSP
+ 0U, // MTLO_DSP_MM
+ 0U, // MTLO_MM
+ 0U, // MTM0
+ 0U, // MTM1
+ 0U, // MTM2
+ 0U, // MTP0
+ 0U, // MTP1
+ 0U, // MTP2
+ 1U, // MTTR
+ 0U, // MUH
+ 0U, // MUHU
+ 0U, // MUHU_MMR6
+ 0U, // MUH_MMR6
+ 0U, // MUL
+ 0U, // MULEQ_S_W_PHL
+ 0U, // MULEQ_S_W_PHL_MM
+ 0U, // MULEQ_S_W_PHR
+ 0U, // MULEQ_S_W_PHR_MM
+ 0U, // MULEU_S_PH_QBL
+ 0U, // MULEU_S_PH_QBL_MM
+ 0U, // MULEU_S_PH_QBR
+ 0U, // MULEU_S_PH_QBR_MM
+ 0U, // MULQ_RS_PH
+ 0U, // MULQ_RS_PH_MM
+ 0U, // MULQ_RS_W
+ 0U, // MULQ_RS_W_MMR2
+ 0U, // MULQ_S_PH
+ 0U, // MULQ_S_PH_MMR2
+ 0U, // MULQ_S_W
+ 0U, // MULQ_S_W_MMR2
+ 0U, // MULR_Q_H
+ 0U, // MULR_Q_W
+ 0U, // MULSAQ_S_W_PH
+ 0U, // MULSAQ_S_W_PH_MM
+ 0U, // MULSA_W_PH
+ 0U, // MULSA_W_PH_MMR2
+ 0U, // MULT
+ 0U, // MULTU_DSP
+ 0U, // MULTU_DSP_MM
+ 0U, // MULT_DSP
+ 0U, // MULT_DSP_MM
+ 0U, // MULT_MM
+ 0U, // MULTu
+ 0U, // MULTu_MM
+ 0U, // MULU
+ 0U, // MULU_MMR6
+ 0U, // MULV_B
+ 0U, // MULV_D
+ 0U, // MULV_H
+ 0U, // MULV_W
+ 0U, // MUL_MM
+ 0U, // MUL_MMR6
+ 0U, // MUL_PH
+ 0U, // MUL_PH_MMR2
+ 0U, // MUL_Q_H
+ 0U, // MUL_Q_W
+ 0U, // MUL_R6
+ 0U, // MUL_S_PH
+ 0U, // MUL_S_PH_MMR2
+ 0U, // Mfhi16
+ 0U, // Mflo16
+ 0U, // Move32R16
+ 0U, // MoveR3216
+ 0U, // NLOC_B
+ 0U, // NLOC_D
+ 0U, // NLOC_H
+ 0U, // NLOC_W
+ 0U, // NLZC_B
+ 0U, // NLZC_D
+ 0U, // NLZC_H
+ 0U, // NLZC_W
+ 4672U, // NMADD_D32
+ 4672U, // NMADD_D32_MM
+ 4672U, // NMADD_D64
+ 4672U, // NMADD_S
+ 4672U, // NMADD_S_MM
+ 4672U, // NMSUB_D32
+ 4672U, // NMSUB_D32_MM
+ 4672U, // NMSUB_D64
+ 4672U, // NMSUB_S
+ 4672U, // NMSUB_S_MM
+ 0U, // NOR
+ 0U, // NOR64
+ 6U, // NORI_B
+ 0U, // NOR_MM
+ 0U, // NOR_MMR6
+ 0U, // NOR_V
+ 0U, // NOT16_MM
+ 0U, // NOT16_MMR6
+ 0U, // NegRxRy16
+ 0U, // NotRxRy16
+ 0U, // OR
+ 0U, // OR16_MM
+ 0U, // OR16_MMR6
+ 0U, // OR64
+ 6U, // ORI_B
+ 8U, // ORI_MMR6
+ 0U, // OR_MM
+ 0U, // OR_MMR6
+ 0U, // OR_V
+ 8U, // ORi
+ 8U, // ORi64
+ 8U, // ORi_MM
+ 0U, // OrRxRxRy16
+ 0U, // PACKRL_PH
+ 0U, // PACKRL_PH_MM
+ 0U, // PAUSE
+ 0U, // PAUSE_MM
+ 0U, // PAUSE_MMR6
+ 0U, // PCKEV_B
+ 0U, // PCKEV_D
+ 0U, // PCKEV_H
+ 0U, // PCKEV_W
+ 0U, // PCKOD_B
+ 0U, // PCKOD_D
+ 0U, // PCKOD_H
+ 0U, // PCKOD_W
+ 0U, // PCNT_B
+ 0U, // PCNT_D
+ 0U, // PCNT_H
+ 0U, // PCNT_W
+ 0U, // PICK_PH
+ 0U, // PICK_PH_MM
+ 0U, // PICK_QB
+ 0U, // PICK_QB_MM
+ 0U, // POP
+ 0U, // PRECEQU_PH_QBL
+ 0U, // PRECEQU_PH_QBLA
+ 0U, // PRECEQU_PH_QBLA_MM
+ 0U, // PRECEQU_PH_QBL_MM
+ 0U, // PRECEQU_PH_QBR
+ 0U, // PRECEQU_PH_QBRA
+ 0U, // PRECEQU_PH_QBRA_MM
+ 0U, // PRECEQU_PH_QBR_MM
+ 0U, // PRECEQ_W_PHL
+ 0U, // PRECEQ_W_PHL_MM
+ 0U, // PRECEQ_W_PHR
+ 0U, // PRECEQ_W_PHR_MM
+ 0U, // PRECEU_PH_QBL
+ 0U, // PRECEU_PH_QBLA
+ 0U, // PRECEU_PH_QBLA_MM
+ 0U, // PRECEU_PH_QBL_MM
+ 0U, // PRECEU_PH_QBR
+ 0U, // PRECEU_PH_QBRA
+ 0U, // PRECEU_PH_QBRA_MM
+ 0U, // PRECEU_PH_QBR_MM
+ 0U, // PRECRQU_S_QB_PH
+ 0U, // PRECRQU_S_QB_PH_MM
+ 0U, // PRECRQ_PH_W
+ 0U, // PRECRQ_PH_W_MM
+ 0U, // PRECRQ_QB_PH
+ 0U, // PRECRQ_QB_PH_MM
+ 0U, // PRECRQ_RS_PH_W
+ 0U, // PRECRQ_RS_PH_W_MM
+ 0U, // PRECR_QB_PH
+ 0U, // PRECR_QB_PH_MMR2
+ 4U, // PRECR_SRA_PH_W
+ 4U, // PRECR_SRA_PH_W_MMR2
+ 4U, // PRECR_SRA_R_PH_W
+ 4U, // PRECR_SRA_R_PH_W_MMR2
+ 0U, // PREF
+ 0U, // PREFE
+ 0U, // PREFE_MM
+ 0U, // PREFX_MM
+ 0U, // PREF_MM
+ 0U, // PREF_MMR6
+ 0U, // PREF_R6
+ 4U, // PREPEND
+ 4U, // PREPEND_MMR2
+ 0U, // RADDU_W_QB
+ 0U, // RADDU_W_QB_MM
+ 0U, // RDDSP
+ 0U, // RDDSP_MM
+ 6U, // RDHWR
+ 6U, // RDHWR64
+ 6U, // RDHWR_MM
+ 2U, // RDHWR_MMR6
+ 0U, // RDPGPR_MMR6
+ 0U, // RECIP_D32
+ 0U, // RECIP_D32_MM
+ 0U, // RECIP_D64
+ 0U, // RECIP_D64_MM
+ 0U, // RECIP_S
+ 0U, // RECIP_S_MM
+ 0U, // REPLV_PH
+ 0U, // REPLV_PH_MM
+ 0U, // REPLV_QB
+ 0U, // REPLV_QB_MM
+ 0U, // REPL_PH
+ 0U, // REPL_PH_MM
+ 0U, // REPL_QB
+ 0U, // REPL_QB_MM
+ 0U, // RINT_D
+ 0U, // RINT_D_MMR6
+ 0U, // RINT_S
+ 0U, // RINT_S_MMR6
+ 4U, // ROTR
+ 0U, // ROTRV
+ 0U, // ROTRV_MM
+ 4U, // ROTR_MM
+ 0U, // ROUND_L_D64
+ 0U, // ROUND_L_D_MMR6
+ 0U, // ROUND_L_S
+ 0U, // ROUND_L_S_MMR6
+ 0U, // ROUND_W_D32
+ 0U, // ROUND_W_D64
+ 0U, // ROUND_W_D_MMR6
+ 0U, // ROUND_W_MM
+ 0U, // ROUND_W_S
+ 0U, // ROUND_W_S_MM
+ 0U, // ROUND_W_S_MMR6
+ 0U, // RSQRT_D32
+ 0U, // RSQRT_D32_MM
+ 0U, // RSQRT_D64
+ 0U, // RSQRT_D64_MM
+ 0U, // RSQRT_S
+ 0U, // RSQRT_S_MM
+ 0U, // Restore16
+ 0U, // RestoreX16
+ 2U, // SAT_S_B
+ 12U, // SAT_S_D
+ 14U, // SAT_S_H
+ 4U, // SAT_S_W
+ 2U, // SAT_U_B
+ 12U, // SAT_U_D
+ 14U, // SAT_U_H
+ 4U, // SAT_U_W
+ 0U, // SB
+ 0U, // SB16_MM
+ 0U, // SB16_MMR6
+ 0U, // SB64
+ 0U, // SBE
+ 0U, // SBE_MM
+ 0U, // SB_MM
+ 0U, // SB_MMR6
+ 0U, // SC
+ 0U, // SC64
+ 0U, // SC64_R6
+ 0U, // SCD
+ 0U, // SCD_R6
+ 0U, // SCE
+ 0U, // SCE_MM
+ 0U, // SC_MM
+ 0U, // SC_MMR6
+ 0U, // SC_R6
+ 0U, // SD
+ 0U, // SDBBP
+ 0U, // SDBBP16_MM
+ 0U, // SDBBP16_MMR6
+ 0U, // SDBBP_MM
+ 0U, // SDBBP_MMR6
+ 0U, // SDBBP_R6
+ 0U, // SDC1
+ 0U, // SDC164
+ 0U, // SDC1_D64_MMR6
+ 0U, // SDC1_MM
+ 0U, // SDC2
+ 0U, // SDC2_MMR6
+ 0U, // SDC2_R6
+ 0U, // SDC3
+ 0U, // SDIV
+ 0U, // SDIV_MM
+ 0U, // SDL
+ 0U, // SDR
+ 0U, // SDXC1
+ 0U, // SDXC164
+ 0U, // SEB
+ 0U, // SEB64
+ 0U, // SEB_MM
+ 0U, // SEH
+ 0U, // SEH64
+ 0U, // SEH_MM
+ 0U, // SELEQZ
+ 0U, // SELEQZ64
+ 0U, // SELEQZ_D
+ 0U, // SELEQZ_D_MMR6
+ 0U, // SELEQZ_MMR6
+ 0U, // SELEQZ_S
+ 0U, // SELEQZ_S_MMR6
+ 0U, // SELNEZ
+ 0U, // SELNEZ64
+ 0U, // SELNEZ_D
+ 0U, // SELNEZ_D_MMR6
+ 0U, // SELNEZ_MMR6
+ 0U, // SELNEZ_S
+ 0U, // SELNEZ_S_MMR6
+ 24U, // SEL_D
+ 24U, // SEL_D_MMR6
+ 24U, // SEL_S
+ 24U, // SEL_S_MMR6
+ 0U, // SEQ
+ 0U, // SEQi
+ 0U, // SH
+ 0U, // SH16_MM
+ 0U, // SH16_MMR6
+ 0U, // SH64
+ 0U, // SHE
+ 0U, // SHE_MM
+ 6U, // SHF_B
+ 6U, // SHF_H
+ 6U, // SHF_W
+ 0U, // SHILO
+ 0U, // SHILOV
+ 0U, // SHILOV_MM
+ 0U, // SHILO_MM
+ 0U, // SHLLV_PH
+ 0U, // SHLLV_PH_MM
+ 0U, // SHLLV_QB
+ 0U, // SHLLV_QB_MM
+ 0U, // SHLLV_S_PH
+ 0U, // SHLLV_S_PH_MM
+ 0U, // SHLLV_S_W
+ 0U, // SHLLV_S_W_MM
+ 14U, // SHLL_PH
+ 14U, // SHLL_PH_MM
+ 2U, // SHLL_QB
+ 2U, // SHLL_QB_MM
+ 14U, // SHLL_S_PH
+ 14U, // SHLL_S_PH_MM
+ 4U, // SHLL_S_W
+ 4U, // SHLL_S_W_MM
+ 0U, // SHRAV_PH
+ 0U, // SHRAV_PH_MM
+ 0U, // SHRAV_QB
+ 0U, // SHRAV_QB_MMR2
+ 0U, // SHRAV_R_PH
+ 0U, // SHRAV_R_PH_MM
+ 0U, // SHRAV_R_QB
+ 0U, // SHRAV_R_QB_MMR2
+ 0U, // SHRAV_R_W
+ 0U, // SHRAV_R_W_MM
+ 14U, // SHRA_PH
+ 14U, // SHRA_PH_MM
+ 2U, // SHRA_QB
+ 2U, // SHRA_QB_MMR2
+ 14U, // SHRA_R_PH
+ 14U, // SHRA_R_PH_MM
+ 2U, // SHRA_R_QB
+ 2U, // SHRA_R_QB_MMR2
+ 4U, // SHRA_R_W
+ 4U, // SHRA_R_W_MM
+ 0U, // SHRLV_PH
+ 0U, // SHRLV_PH_MMR2
+ 0U, // SHRLV_QB
+ 0U, // SHRLV_QB_MM
+ 14U, // SHRL_PH
+ 14U, // SHRL_PH_MMR2
+ 2U, // SHRL_QB
+ 2U, // SHRL_QB_MM
+ 0U, // SH_MM
+ 0U, // SH_MMR6
+ 148U, // SLDI_B
+ 34U, // SLDI_D
+ 144U, // SLDI_H
+ 36U, // SLDI_W
+ 152U, // SLD_B
+ 152U, // SLD_D
+ 152U, // SLD_H
+ 152U, // SLD_W
+ 4U, // SLL
+ 0U, // SLL16_MM
+ 0U, // SLL16_MMR6
+ 1U, // SLL64_32
+ 1U, // SLL64_64
+ 2U, // SLLI_B
+ 12U, // SLLI_D
+ 14U, // SLLI_H
+ 4U, // SLLI_W
+ 0U, // SLLV
+ 0U, // SLLV_MM
+ 0U, // SLL_B
+ 0U, // SLL_D
+ 0U, // SLL_H
+ 4U, // SLL_MM
+ 4U, // SLL_MMR6
+ 0U, // SLL_W
+ 0U, // SLT
+ 0U, // SLT64
+ 0U, // SLT_MM
+ 0U, // SLTi
+ 0U, // SLTi64
+ 0U, // SLTi_MM
+ 0U, // SLTiu
+ 0U, // SLTiu64
+ 0U, // SLTiu_MM
+ 0U, // SLTu
+ 0U, // SLTu64
+ 0U, // SLTu_MM
+ 0U, // SNE
+ 0U, // SNEi
+ 142U, // SPLATI_B
+ 156U, // SPLATI_D
+ 130U, // SPLATI_H
+ 138U, // SPLATI_W
+ 128U, // SPLAT_B
+ 128U, // SPLAT_D
+ 128U, // SPLAT_H
+ 128U, // SPLAT_W
+ 4U, // SRA
+ 2U, // SRAI_B
+ 12U, // SRAI_D
+ 14U, // SRAI_H
+ 4U, // SRAI_W
+ 2U, // SRARI_B
+ 12U, // SRARI_D
+ 14U, // SRARI_H
+ 4U, // SRARI_W
+ 0U, // SRAR_B
+ 0U, // SRAR_D
+ 0U, // SRAR_H
+ 0U, // SRAR_W
+ 0U, // SRAV
+ 0U, // SRAV_MM
+ 0U, // SRA_B
+ 0U, // SRA_D
+ 0U, // SRA_H
+ 4U, // SRA_MM
+ 0U, // SRA_W
+ 4U, // SRL
+ 0U, // SRL16_MM
+ 0U, // SRL16_MMR6
+ 2U, // SRLI_B
+ 12U, // SRLI_D
+ 14U, // SRLI_H
+ 4U, // SRLI_W
+ 2U, // SRLRI_B
+ 12U, // SRLRI_D
+ 14U, // SRLRI_H
+ 4U, // SRLRI_W
+ 0U, // SRLR_B
+ 0U, // SRLR_D
+ 0U, // SRLR_H
+ 0U, // SRLR_W
+ 0U, // SRLV
+ 0U, // SRLV_MM
+ 0U, // SRL_B
+ 0U, // SRL_D
+ 0U, // SRL_H
+ 4U, // SRL_MM
+ 0U, // SRL_W
+ 0U, // SSNOP
+ 0U, // SSNOP_MM
+ 0U, // SSNOP_MMR6
+ 0U, // ST_B
+ 0U, // ST_D
+ 0U, // ST_H
+ 0U, // ST_W
+ 0U, // SUB
+ 0U, // SUBQH_PH
+ 0U, // SUBQH_PH_MMR2
+ 0U, // SUBQH_R_PH
+ 0U, // SUBQH_R_PH_MMR2
+ 0U, // SUBQH_R_W
+ 0U, // SUBQH_R_W_MMR2
+ 0U, // SUBQH_W
+ 0U, // SUBQH_W_MMR2
+ 0U, // SUBQ_PH
+ 0U, // SUBQ_PH_MM
+ 0U, // SUBQ_S_PH
+ 0U, // SUBQ_S_PH_MM
+ 0U, // SUBQ_S_W
+ 0U, // SUBQ_S_W_MM
+ 0U, // SUBSUS_U_B
+ 0U, // SUBSUS_U_D
+ 0U, // SUBSUS_U_H
+ 0U, // SUBSUS_U_W
+ 0U, // SUBSUU_S_B
+ 0U, // SUBSUU_S_D
+ 0U, // SUBSUU_S_H
+ 0U, // SUBSUU_S_W
+ 0U, // SUBS_S_B
+ 0U, // SUBS_S_D
+ 0U, // SUBS_S_H
+ 0U, // SUBS_S_W
+ 0U, // SUBS_U_B
+ 0U, // SUBS_U_D
+ 0U, // SUBS_U_H
+ 0U, // SUBS_U_W
+ 0U, // SUBU16_MM
+ 0U, // SUBU16_MMR6
+ 0U, // SUBUH_QB
+ 0U, // SUBUH_QB_MMR2
+ 0U, // SUBUH_R_QB
+ 0U, // SUBUH_R_QB_MMR2
+ 0U, // SUBU_MMR6
+ 0U, // SUBU_PH
+ 0U, // SUBU_PH_MMR2
+ 0U, // SUBU_QB
+ 0U, // SUBU_QB_MM
+ 0U, // SUBU_S_PH
+ 0U, // SUBU_S_PH_MMR2
+ 0U, // SUBU_S_QB
+ 0U, // SUBU_S_QB_MM
+ 4U, // SUBVI_B
+ 4U, // SUBVI_D
+ 4U, // SUBVI_H
+ 4U, // SUBVI_W
+ 0U, // SUBV_B
+ 0U, // SUBV_D
+ 0U, // SUBV_H
+ 0U, // SUBV_W
+ 0U, // SUB_MM
+ 0U, // SUB_MMR6
+ 0U, // SUBu
+ 0U, // SUBu_MM
+ 0U, // SUXC1
+ 0U, // SUXC164
+ 0U, // SUXC1_MM
+ 0U, // SW
+ 0U, // SW16_MM
+ 0U, // SW16_MMR6
+ 0U, // SW64
+ 0U, // SWC1
+ 0U, // SWC1_MM
+ 0U, // SWC2
+ 0U, // SWC2_MMR6
+ 0U, // SWC2_R6
+ 0U, // SWC3
+ 0U, // SWDSP
+ 0U, // SWDSP_MM
+ 0U, // SWE
+ 0U, // SWE_MM
+ 0U, // SWL
+ 0U, // SWL64
+ 0U, // SWLE
+ 0U, // SWLE_MM
+ 0U, // SWL_MM
+ 0U, // SWM16_MM
+ 0U, // SWM16_MMR6
+ 0U, // SWM32_MM
+ 0U, // SWP_MM
+ 0U, // SWR
+ 0U, // SWR64
+ 0U, // SWRE
+ 0U, // SWRE_MM
+ 0U, // SWR_MM
+ 0U, // SWSP_MM
+ 0U, // SWSP_MMR6
+ 0U, // SWXC1
+ 0U, // SWXC1_MM
+ 0U, // SW_MM
+ 0U, // SW_MMR6
+ 0U, // SYNC
+ 0U, // SYNCI
+ 0U, // SYNCI_MM
+ 0U, // SYNCI_MMR6
+ 0U, // SYNC_MM
+ 0U, // SYNC_MMR6
+ 0U, // SYSCALL
+ 0U, // SYSCALL_MM
+ 0U, // Save16
+ 0U, // SaveX16
+ 0U, // SbRxRyOffMemX16
+ 0U, // SebRx16
+ 0U, // SehRx16
+ 0U, // ShRxRyOffMemX16
+ 4U, // SllX16
+ 0U, // SllvRxRy16
+ 0U, // SltRxRy16
+ 0U, // SltiRxImm16
+ 0U, // SltiRxImmX16
+ 0U, // SltiuRxImm16
+ 0U, // SltiuRxImmX16
+ 0U, // SltuRxRy16
+ 4U, // SraX16
+ 0U, // SravRxRy16
+ 4U, // SrlX16
+ 0U, // SrlvRxRy16
+ 0U, // SubuRxRyRz16
+ 0U, // SwRxRyOffMemX16
+ 0U, // SwRxSpImmX16
+ 38U, // TEQ
+ 0U, // TEQI
+ 0U, // TEQI_MM
+ 14U, // TEQ_MM
+ 38U, // TGE
+ 0U, // TGEI
+ 0U, // TGEIU
+ 0U, // TGEIU_MM
+ 0U, // TGEI_MM
+ 38U, // TGEU
+ 14U, // TGEU_MM
+ 14U, // TGE_MM
+ 0U, // TLBGINV
+ 0U, // TLBGINVF
+ 0U, // TLBGINVF_MM
+ 0U, // TLBGINV_MM
+ 0U, // TLBGP
+ 0U, // TLBGP_MM
+ 0U, // TLBGR
+ 0U, // TLBGR_MM
+ 0U, // TLBGWI
+ 0U, // TLBGWI_MM
+ 0U, // TLBGWR
+ 0U, // TLBGWR_MM
+ 0U, // TLBINV
+ 0U, // TLBINVF
+ 0U, // TLBINVF_MMR6
+ 0U, // TLBINV_MMR6
+ 0U, // TLBP
+ 0U, // TLBP_MM
+ 0U, // TLBR
+ 0U, // TLBR_MM
+ 0U, // TLBWI
+ 0U, // TLBWI_MM
+ 0U, // TLBWR
+ 0U, // TLBWR_MM
+ 38U, // TLT
+ 0U, // TLTI
+ 0U, // TLTIU_MM
+ 0U, // TLTI_MM
+ 38U, // TLTU
+ 14U, // TLTU_MM
+ 14U, // TLT_MM
+ 38U, // TNE
+ 0U, // TNEI
+ 0U, // TNEI_MM
+ 14U, // TNE_MM
+ 0U, // TRUNC_L_D64
+ 0U, // TRUNC_L_D_MMR6
+ 0U, // TRUNC_L_S
+ 0U, // TRUNC_L_S_MMR6
+ 0U, // TRUNC_W_D32
+ 0U, // TRUNC_W_D64
+ 0U, // TRUNC_W_D_MMR6
+ 0U, // TRUNC_W_MM
+ 0U, // TRUNC_W_S
+ 0U, // TRUNC_W_S_MM
+ 0U, // TRUNC_W_S_MMR6
+ 0U, // TTLTIU
+ 0U, // UDIV
+ 0U, // UDIV_MM
+ 0U, // V3MULU
+ 0U, // VMM0
+ 0U, // VMULU
+ 24U, // VSHF_B
+ 24U, // VSHF_D
+ 24U, // VSHF_H
+ 24U, // VSHF_W
+ 0U, // WAIT
+ 0U, // WAIT_MM
+ 0U, // WAIT_MMR6
+ 0U, // WRDSP
+ 0U, // WRDSP_MM
+ 0U, // WRPGPR_MMR6
+ 0U, // WSBH
+ 0U, // WSBH_MM
+ 0U, // WSBH_MMR6
+ 0U, // XOR
+ 0U, // XOR16_MM
+ 0U, // XOR16_MMR6
+ 0U, // XOR64
+ 6U, // XORI_B
+ 8U, // XORI_MMR6
+ 0U, // XOR_MM
+ 0U, // XOR_MMR6
+ 0U, // XOR_V
+ 8U, // XORi
+ 8U, // XORi64
+ 8U, // XORi_MM
+ 0U, // XorRxRxRy16
+ 0U, // YIELD
+ };
+
+ O << "\t";
+
+ // Emit the opcode for the instruction.
+ uint64_t Bits = 0;
+ Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
+ Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
+ assert(Bits != 0 && "Cannot print this instruction.");
+ O << AsmStrs+(Bits & 16383)-1;
+
+
+ // Fragment 0 encoded into 4 bits for 14 unique commands.
+ switch ((Bits >> 14) & 15) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL...
+ return;
+ break;
+ case 1:
+ // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
+ printOperand(MI, 0, O);
+ break;
+ case 2:
+ // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, MultRxRyRz1...
+ printOperand(MI, 1, O);
+ O << ", ";
+ break;
+ case 3:
+ // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, MOVEP_MM, MOVEP_MMR6, ...
+ printRegisterList(MI, 0, O);
+ O << ", ";
+ break;
+ case 4:
+ // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ...
+ printOperand(MI, 3, O);
+ break;
+ case 5:
+ // AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT...
+ printOperand(MI, 2, O);
+ O << ", ";
+ break;
+ case 6:
+ // BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM...
+ printUImm<10>(MI, 0, O);
+ break;
+ case 7:
+ // BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6
+ printUImm<4>(MI, 0, O);
+ return;
+ break;
+ case 8:
+ // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,...
+ printUImm<5>(MI, 2, O);
+ O << ", ";
+ break;
+ case 9:
+ // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM
+ printFCCOperand(MI, 2, O);
+ break;
+ case 10:
+ // Jal16, JalB16
+ printUImm<26>(MI, 0, O);
+ break;
+ case 11:
+ // SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL
+ printUImm<20>(MI, 0, O);
+ return;
+ break;
+ case 12:
+ // SYNC, SYNC_MM, SYNC_MMR6
+ printUImm<5>(MI, 0, O);
+ return;
+ break;
+ case 13:
+ // SYNCI, SYNCI_MM, SYNCI_MMR6
+ printMemOperand(MI, 0, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 1 encoded into 5 bits for 18 unique commands.
+ switch ((Bits >> 18) & 31) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
+ O << ", ";
+ break;
+ case 1:
+ // B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MTTDSP, ADD...
+ return;
+ break;
+ case 2:
+ // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_...
+ printOperand(MI, 0, O);
+ break;
+ case 3:
+ // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ...
+ printMemOperand(MI, 1, O);
+ return;
+ break;
+ case 4:
+ // LwConstant32
+ O << ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t";
+ printOperand(MI, 1, O);
+ O << "\n2:";
+ return;
+ break;
+ case 5:
+ // MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm...
+ printOperand(MI, 2, O);
+ break;
+ case 6:
+ // SelBeqZ, SelBneZ
+ O << ", .+4\n\t\n\tmove ";
+ printOperand(MI, 1, O);
+ O << ", ";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 7:
+ // AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM...
+ printOperand(MI, 1, O);
+ break;
+ case 8:
+ // AddiuRxPcImmX16
+ O << ", $pc, ";
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 9:
+ // AddiuSpImm16, Bimm16
+ O << " # 16 bit inst";
+ return;
+ break;
+ case 10:
+ // Bteqz16, Btnez16
+ O << " # 16 bit inst";
+ return;
+ break;
+ case 11:
+ // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,...
+ printMemOperand(MI, 0, O);
+ return;
+ break;
+ case 12:
+ // FCMP_D32, FCMP_D32_MM, FCMP_D64
+ O << ".d\t";
+ printOperand(MI, 0, O);
+ O << ", ";
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 13:
+ // FCMP_S32, FCMP_S32_MM
+ O << ".s\t";
+ printOperand(MI, 0, O);
+ O << ", ";
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 14:
+ // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS...
+ O << '[';
+ break;
+ case 15:
+ // Jal16
+ O << "\n\tnop";
+ return;
+ break;
+ case 16:
+ // JalB16
+ O << "\t# branch\n\tnop";
+ return;
+ break;
+ case 17:
+ // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6
+ printMemOperand(MI, 2, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 2 encoded into 5 bits for 25 unique commands.
+ switch ((Bits >> 23) & 31) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
+ printOperand(MI, 1, O);
+ break;
+ case 1:
+ // CTTC1, MTTACX, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, ADDIUS5_MM, AND16_...
+ return;
+ break;
+ case 2:
+ // GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,...
+ printOperand(MI, 2, O);
+ break;
+ case 3:
+ // LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA...
+ printMemOperand(MI, 1, O);
+ return;
+ break;
+ case 4:
+ // MTTC0, DMTC0, DMTC2, DMTGC0, FORK, LSA_MMR6, MOVEP_MM, MOVEP_MMR6, MTC...
+ O << ", ";
+ break;
+ case 5:
+ // MultRxRyRz16, MultuRxRyRz16
+ O << "\n\tmflo\t";
+ printOperand(MI, 0, O);
+ return;
+ break;
+ case 6:
+ // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt...
+ printOperand(MI, 4, O);
+ break;
+ case 7:
+ // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz...
+ O << "\n\tmove\t";
+ printOperand(MI, 0, O);
+ O << ", $t8";
+ return;
+ break;
+ case 8:
+ // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM
+ printMemOperandEA(MI, 1, O);
+ return;
+ break;
+ case 9:
+ // BBIT0, BBIT032, BBIT1, BBIT132
+ printUImm<5>(MI, 1, O);
+ O << ", ";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 10:
+ // BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP
+ printUImm<10>(MI, 1, O);
+ return;
+ break;
+ case 11:
+ // DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM
+ printUImm<16>(MI, 1, O);
+ return;
+ break;
+ case 12:
+ // GINVT, GINVT_MMR6
+ printUImm<2>(MI, 1, O);
+ return;
+ break;
+ case 13:
+ // INSERT_B
+ printUImm<4>(MI, 3, O);
+ O << "], ";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 14:
+ // INSERT_D
+ printUImm<1>(MI, 3, O);
+ O << "], ";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 15:
+ // INSERT_H
+ printUImm<3>(MI, 3, O);
+ O << "], ";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 16:
+ // INSERT_W
+ printUImm<2>(MI, 3, O);
+ O << "], ";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 17:
+ // INSVE_B
+ printUImm<4>(MI, 2, O);
+ O << "], ";
+ printOperand(MI, 3, O);
+ O << '[';
+ printUImm<0>(MI, 4, O);
+ O << ']';
+ return;
+ break;
+ case 18:
+ // INSVE_D
+ printUImm<1>(MI, 2, O);
+ O << "], ";
+ printOperand(MI, 3, O);
+ O << '[';
+ printUImm<0>(MI, 4, O);
+ O << ']';
+ return;
+ break;
+ case 19:
+ // INSVE_H
+ printUImm<3>(MI, 2, O);
+ O << "], ";
+ printOperand(MI, 3, O);
+ O << '[';
+ printUImm<0>(MI, 4, O);
+ O << ']';
+ return;
+ break;
+ case 20:
+ // INSVE_W
+ printUImm<2>(MI, 2, O);
+ O << "], ";
+ printOperand(MI, 3, O);
+ O << '[';
+ printUImm<0>(MI, 4, O);
+ O << ']';
+ return;
+ break;
+ case 21:
+ // LWP_MM, SWP_MM
+ printMemOperand(MI, 2, O);
+ return;
+ break;
+ case 22:
+ // PREFX_MM
+ O << '(';
+ printOperand(MI, 0, O);
+ O << ')';
+ return;
+ break;
+ case 23:
+ // RDDSP_MM, WRDSP_MM
+ printUImm<7>(MI, 1, O);
+ return;
+ break;
+ case 24:
+ // REPL_QB, REPL_QB_MM
+ printUImm<8>(MI, 1, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 3 encoded into 5 bits for 19 unique commands.
+ switch ((Bits >> 28) & 31) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // ABSMacro, CFTC1, JalTwoReg, LoadAddrImm32, LoadAddrImm64, LoadImm32, L...
+ return;
+ break;
+ case 1:
+ // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro...
+ O << ", ";
+ break;
+ case 2:
+ // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S...
+ O << "\n\tbteqz\t";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 3:
+ // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S...
+ O << "\n\tbtnez\t";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 4:
+ // GotPrologue16
+ O << "\n\taddiu\t";
+ printOperand(MI, 1, O);
+ O << ", $pc, ";
+ printOperand(MI, 3, O);
+ O << "\n ";
+ return;
+ break;
+ case 5:
+ // MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M...
+ printUImm<3>(MI, 2, O);
+ return;
+ break;
+ case 6:
+ // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt...
+ O << "\n\tbteqz\t.+4\n\tmove ";
+ printOperand(MI, 1, O);
+ O << ", ";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 7:
+ // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt...
+ O << "\n\tbtnez\t.+4\n\tmove ";
+ printOperand(MI, 1, O);
+ O << ", ";
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 8:
+ // AddiuRxRxImm16, LwRxPcTcp16
+ O << "\t# 16 bit inst";
+ return;
+ break;
+ case 9:
+ // BeqzRxImm16, BnezRxImm16
+ O << " # 16 bit inst";
+ return;
+ break;
+ case 10:
+ // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ...
+ O << '[';
+ break;
+ case 11:
+ // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16
+ O << " \t# 16 bit inst";
+ return;
+ break;
+ case 12:
+ // DSLL64_32
+ O << ", 32";
+ return;
+ break;
+ case 13:
+ // FORK
+ printOperand(MI, 2, O);
+ return;
+ break;
+ case 14:
+ // LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ...
+ O << '(';
+ printOperand(MI, 1, O);
+ O << ')';
+ return;
+ break;
+ case 15:
+ // LSA_MMR6
+ printOperand(MI, 0, O);
+ O << ", ";
+ printUImm<2, 1>(MI, 3, O);
+ return;
+ break;
+ case 16:
+ // MOVEP_MM, MOVEP_MMR6
+ printOperand(MI, 3, O);
+ return;
+ break;
+ case 17:
+ // MTTR
+ printUImm<1>(MI, 2, O);
+ O << ", ";
+ printUImm<3>(MI, 3, O);
+ O << ", ";
+ printUImm<1>(MI, 4, O);
+ return;
+ break;
+ case 18:
+ // SLL64_32, SLL64_64
+ O << ", 0";
+ return;
+ break;
+ }
+
+
+ // Fragment 4 encoded into 5 bits for 20 unique commands.
+ switch ((Bits >> 33) & 31) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro...
+ printOperand(MI, 2, O);
+ break;
+ case 1:
+ // MFTC0, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0, DMFC2, DM...
+ printUImm<3>(MI, 2, O);
+ break;
+ case 2:
+ // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG...
+ printUImm<5>(MI, 2, O);
+ break;
+ case 3:
+ // ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, SHF_H, SHF_W, ...
+ printUImm<8>(MI, 2, O);
+ return;
+ break;
+ case 4:
+ // ANDI_MMR6, ANDi, ANDi64, ANDi_MM, AUI, AUI_MMR6, DAHI, DATI, DAUI, ORI...
+ printUImm<16>(MI, 2, O);
+ return;
+ break;
+ case 5:
+ // BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W
+ printUImm<2>(MI, 2, O);
+ break;
+ case 6:
+ // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D...
+ printUImm<6>(MI, 2, O);
+ break;
+ case 7:
+ // BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_...
+ printUImm<4>(MI, 2, O);
+ break;
+ case 8:
+ // BINSLI_B, BINSRI_B, SLDI_H
+ printUImm<3>(MI, 3, O);
+ break;
+ case 9:
+ // BINSLI_D, BINSRI_D
+ printUImm<6>(MI, 3, O);
+ return;
+ break;
+ case 10:
+ // BINSLI_H, BINSRI_H, SLDI_B
+ printUImm<4>(MI, 3, O);
+ break;
+ case 11:
+ // BINSLI_W, BINSRI_W
+ printUImm<5>(MI, 3, O);
+ return;
+ break;
+ case 12:
+ // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W...
+ printOperand(MI, 3, O);
+ break;
+ case 13:
+ // BMNZI_B, BMZI_B, BSELI_B
+ printUImm<8>(MI, 3, O);
+ return;
+ break;
+ case 14:
+ // COPY_S_D, MFTR, SPLATI_D
+ printUImm<1>(MI, 2, O);
+ break;
+ case 15:
+ // DEXTU, DINSU
+ printUImm<5, 32>(MI, 2, O);
+ O << ", ";
+ break;
+ case 16:
+ // FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6
+ printOperand(MI, 1, O);
+ return;
+ break;
+ case 17:
+ // SLDI_D
+ printUImm<1>(MI, 3, O);
+ O << ']';
+ return;
+ break;
+ case 18:
+ // SLDI_W
+ printUImm<2>(MI, 3, O);
+ O << ']';
+ return;
+ break;
+ case 19:
+ // TEQ, TGE, TGEU, TLT, TLTU, TNE
+ printUImm<10>(MI, 2, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 5 encoded into 3 bits for 5 unique commands.
+ switch ((Bits >> 38) & 7) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro...
+ return;
+ break;
+ case 1:
+ // ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE...
+ O << ", ";
+ break;
+ case 2:
+ // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ...
+ O << ']';
+ return;
+ break;
+ case 3:
+ // DEXTU
+ printUImm<5, 1>(MI, 3, O);
+ return;
+ break;
+ case 4:
+ // DINSU
+ printUImm<6>(MI, 3, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 6 encoded into 4 bits for 10 unique commands.
+ switch ((Bits >> 41) & 15) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // ALIGN, ALIGN_MMR6
+ printUImm<2>(MI, 3, O);
+ return;
+ break;
+ case 1:
+ // CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32
+ printUImm<5>(MI, 3, O);
+ return;
+ break;
+ case 2:
+ // DALIGN, MFTR
+ printUImm<3>(MI, 3, O);
+ break;
+ case 3:
+ // DEXT
+ printUImm<6, 1>(MI, 3, O);
+ return;
+ break;
+ case 4:
+ // DEXT64_32, EXT, EXT_MM, EXT_MMR6
+ printUImm<5, 1>(MI, 3, O);
+ return;
+ break;
+ case 5:
+ // DEXTM
+ printUImm<5, 33>(MI, 3, O);
+ return;
+ break;
+ case 6:
+ // DINS, INS, INS_MM, INS_MMR6
+ printUImm<6>(MI, 3, O);
+ return;
+ break;
+ case 7:
+ // DINSM
+ printUImm<6, 2>(MI, 3, O);
+ return;
+ break;
+ case 8:
+ // DLSA, DLSA_R6, LSA, LSA_R6
+ printUImm<2, 1>(MI, 3, O);
+ return;
+ break;
+ case 9:
+ // MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MSUB_D32, MSUB_D32...
+ printOperand(MI, 3, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 7 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 45) & 1) {
+ // MFTR
+ O << ", ";
+ printUImm<1>(MI, 4, O);
+ return;
+ } else {
+ // DALIGN
+ return;
+ }
+
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+const char *MipsInstPrinter::getRegisterName(unsigned RegNo) {
+ assert(RegNo && RegNo < 418 && "Invalid register number!");
+
+ static const char AsmStrs[] = {
+ /* 0 */ 'f', '1', '0', 0,
+ /* 4 */ 'w', '1', '0', 0,
+ /* 8 */ 'f', '2', '0', 0,
+ /* 12 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0,
+ /* 25 */ 'w', '2', '0', 0,
+ /* 29 */ 'f', '3', '0', 0,
+ /* 33 */ 'w', '3', '0', 0,
+ /* 37 */ 'a', 'c', '0', 0,
+ /* 41 */ 'f', 'c', 'c', '0', 0,
+ /* 46 */ 'f', '0', 0,
+ /* 49 */ 'm', 'p', 'l', '0', 0,
+ /* 54 */ 'p', '0', 0,
+ /* 57 */ 'w', '0', 0,
+ /* 60 */ 'f', '1', '1', 0,
+ /* 64 */ 'w', '1', '1', 0,
+ /* 68 */ 'f', '2', '1', 0,
+ /* 72 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0,
+ /* 85 */ 'w', '2', '1', 0,
+ /* 89 */ 'f', '3', '1', 0,
+ /* 93 */ 'w', '3', '1', 0,
+ /* 97 */ 'a', 'c', '1', 0,
+ /* 101 */ 'f', 'c', 'c', '1', 0,
+ /* 106 */ 'f', '1', 0,
+ /* 109 */ 'm', 'p', 'l', '1', 0,
+ /* 114 */ 'p', '1', 0,
+ /* 117 */ 'w', '1', 0,
+ /* 120 */ 'f', '1', '2', 0,
+ /* 124 */ 'w', '1', '2', 0,
+ /* 128 */ 'f', '2', '2', 0,
+ /* 132 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0,
+ /* 145 */ 'w', '2', '2', 0,
+ /* 149 */ 'a', 'c', '2', 0,
+ /* 153 */ 'f', 'c', 'c', '2', 0,
+ /* 158 */ 'f', '2', 0,
+ /* 161 */ 'm', 'p', 'l', '2', 0,
+ /* 166 */ 'p', '2', 0,
+ /* 169 */ 'w', '2', 0,
+ /* 172 */ 'f', '1', '3', 0,
+ /* 176 */ 'w', '1', '3', 0,
+ /* 180 */ 'f', '2', '3', 0,
+ /* 184 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0,
+ /* 197 */ 'w', '2', '3', 0,
+ /* 201 */ 'a', 'c', '3', 0,
+ /* 205 */ 'f', 'c', 'c', '3', 0,
+ /* 210 */ 'f', '3', 0,
+ /* 213 */ 'w', '3', 0,
+ /* 216 */ 'f', '1', '4', 0,
+ /* 220 */ 'w', '1', '4', 0,
+ /* 224 */ 'f', '2', '4', 0,
+ /* 228 */ 'w', '2', '4', 0,
+ /* 232 */ 'f', 'c', 'c', '4', 0,
+ /* 237 */ 'f', '4', 0,
+ /* 240 */ 'w', '4', 0,
+ /* 243 */ 'f', '1', '5', 0,
+ /* 247 */ 'w', '1', '5', 0,
+ /* 251 */ 'f', '2', '5', 0,
+ /* 255 */ 'w', '2', '5', 0,
+ /* 259 */ 'f', 'c', 'c', '5', 0,
+ /* 264 */ 'f', '5', 0,
+ /* 267 */ 'w', '5', 0,
+ /* 270 */ 'f', '1', '6', 0,
+ /* 274 */ 'w', '1', '6', 0,
+ /* 278 */ 'f', '2', '6', 0,
+ /* 282 */ 'w', '2', '6', 0,
+ /* 286 */ 'f', 'c', 'c', '6', 0,
+ /* 291 */ 'f', '6', 0,
+ /* 294 */ 'w', '6', 0,
+ /* 297 */ 'f', '1', '7', 0,
+ /* 301 */ 'w', '1', '7', 0,
+ /* 305 */ 'f', '2', '7', 0,
+ /* 309 */ 'w', '2', '7', 0,
+ /* 313 */ 'f', 'c', 'c', '7', 0,
+ /* 318 */ 'f', '7', 0,
+ /* 321 */ 'w', '7', 0,
+ /* 324 */ 'f', '1', '8', 0,
+ /* 328 */ 'w', '1', '8', 0,
+ /* 332 */ 'f', '2', '8', 0,
+ /* 336 */ 'w', '2', '8', 0,
+ /* 340 */ 'f', '8', 0,
+ /* 343 */ 'w', '8', 0,
+ /* 346 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0,
+ /* 362 */ 'f', '1', '9', 0,
+ /* 366 */ 'w', '1', '9', 0,
+ /* 370 */ 'f', '2', '9', 0,
+ /* 374 */ 'w', '2', '9', 0,
+ /* 378 */ 'f', '9', 0,
+ /* 381 */ 'w', '9', 0,
+ /* 384 */ 'D', 'S', 'P', 'E', 'F', 'I', 0,
+ /* 391 */ 'r', 'a', 0,
+ /* 394 */ 'h', 'w', 'r', '_', 'c', 'c', 0,
+ /* 401 */ 'p', 'c', 0,
+ /* 404 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0,
+ /* 413 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0,
+ /* 424 */ 'h', 'i', 0,
+ /* 427 */ 'h', 'w', 'r', '_', 'c', 'p', 'u', 'n', 'u', 'm', 0,
+ /* 438 */ 'l', 'o', 0,
+ /* 441 */ 'z', 'e', 'r', 'o', 0,
+ /* 446 */ 'h', 'w', 'r', '_', 's', 'y', 'n', 'c', 'i', '_', 's', 't', 'e', 'p', 0,
+ /* 461 */ 'f', 'p', 0,
+ /* 464 */ 'g', 'p', 0,
+ /* 467 */ 's', 'p', 0,
+ /* 470 */ 'h', 'w', 'r', '_', 'c', 'c', 'r', 'e', 's', 0,
+ /* 480 */ 'D', 'S', 'P', 'P', 'o', 's', 0,
+ /* 487 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0,
+ /* 497 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0,
+ };
+
+ static const uint16_t RegAsmOffset[] = {
+ 62, 404, 497, 384, 413, 480, 487, 461, 464, 122, 62, 2, 272, 218,
+ 245, 174, 299, 401, 391, 467, 441, 218, 245, 272, 299, 37, 97, 149,
+ 201, 62, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 2, 62,
+ 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, 245,
+ 272, 299, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 359,
+ 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 1, 61,
+ 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252,
+ 279, 306, 333, 371, 30, 90, 1, 61, 121, 173, 217, 244, 271, 298,
+ 325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90,
+ 46, 158, 237, 291, 340, 0, 120, 216, 270, 324, 8, 128, 224, 278,
+ 332, 29, 12, 72, 132, 184, 46, 106, 158, 210, 237, 264, 291, 318,
+ 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68,
+ 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 41, 101, 153, 205,
+ 232, 259, 286, 313, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360,
+ 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181,
+ 225, 252, 279, 306, 333, 371, 30, 90, 461, 46, 106, 158, 210, 237,
+ 264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324,
+ 362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 464,
+ 37, 97, 149, 201, 427, 446, 394, 470, 218, 245, 272, 299, 326, 360,
+ 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181,
+ 225, 252, 279, 306, 333, 371, 30, 90, 279, 306, 37, 97, 149, 201,
+ 49, 109, 161, 54, 114, 166, 391, 271, 298, 325, 359, 9, 69, 129,
+ 181, 467, 326, 360, 1, 61, 121, 173, 217, 244, 225, 252, 122, 174,
+ 57, 117, 169, 213, 240, 267, 294, 321, 343, 381, 4, 64, 124, 176,
+ 220, 247, 274, 301, 328, 366, 25, 85, 145, 197, 228, 255, 282, 309,
+ 336, 374, 33, 93, 441, 218, 245, 272, 299, 37, 46, 106, 158, 210,
+ 237, 264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297,
+ 324, 362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89,
+ 346, 424, 279, 306, 438, 271, 298, 325, 359, 9, 69, 129, 181, 326,
+ 360, 1, 61, 121, 173, 217, 244, 225, 252, 122, 174,
+ };
+
+ assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
+ "Invalid alt name index for register!");
+ return AsmStrs+RegAsmOffset[RegNo-1];
+}
+
+#ifdef PRINT_ALIAS_INSTR
+#undef PRINT_ALIAS_INSTR
+
+bool MipsInstPrinter::printAliasInstr(const MCInst *MI, raw_ostream &OS) {
+ const char *AsmString;
+ switch (MI->getOpcode()) {
+ default: return false;
+ case Mips::ADDIUPC:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg())) {
+ // (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm)
+ AsmString = "lapc $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::ADDIUPC_MMR6:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg())) {
+ // (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm)
+ AsmString = "lapc $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::ADDu:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).getReg() == Mips::ZERO) {
+ // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO)
+ AsmString = "move $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::BC1F:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::FCC0) {
+ // (BC1F FCC0, brtarget:$offset)
+ AsmString = "bc1f $\x02";
+ break;
+ }
+ return false;
+ case Mips::BC1FL:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::FCC0) {
+ // (BC1FL FCC0, brtarget:$offset)
+ AsmString = "bc1fl $\x02";
+ break;
+ }
+ return false;
+ case Mips::BC1F_MM:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::FCC0) {
+ // (BC1F_MM FCC0, brtarget:$offset)
+ AsmString = "bc1f $\x02";
+ break;
+ }
+ return false;
+ case Mips::BC1T:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::FCC0) {
+ // (BC1T FCC0, brtarget:$offset)
+ AsmString = "bc1t $\x02";
+ break;
+ }
+ return false;
+ case Mips::BC1TL:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::FCC0) {
+ // (BC1TL FCC0, brtarget:$offset)
+ AsmString = "bc1tl $\x02";
+ break;
+ }
+ return false;
+ case Mips::BC1T_MM:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::FCC0) {
+ // (BC1T_MM FCC0, brtarget:$offset)
+ AsmString = "bc1t $\x02";
+ break;
+ }
+ return false;
+ case Mips::BGEZAL:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (BGEZAL ZERO, brtarget:$offset)
+ AsmString = "bal $\x02";
+ break;
+ }
+ return false;
+ case Mips::BGEZAL_MM:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (BGEZAL_MM ZERO, brtarget_mm:$offset)
+ AsmString = "bal $\x02";
+ break;
+ }
+ return false;
+ case Mips::BREAK:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0 &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0) {
+ // (BREAK 0, 0)
+ AsmString = "break";
+ break;
+ }
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0) {
+ // (BREAK uimm10:$imm, 0)
+ AsmString = "break $\xFF\x01\x01";
+ break;
+ }
+ return false;
+ case Mips::BREAK_MM:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0 &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0) {
+ // (BREAK_MM 0, 0)
+ AsmString = "break";
+ break;
+ }
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0) {
+ // (BREAK_MM uimm10:$imm, 0)
+ AsmString = "break $\xFF\x01\x01";
+ break;
+ }
+ return false;
+ case Mips::C_EQ_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.eq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_EQ_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.eq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_EQ_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.eq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_EQ_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.eq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_EQ_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.eq.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_EQ_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.eq.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_F_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.f.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_F_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.f.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_F_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.f.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_F_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.f.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_F_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.f.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_F_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.f.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LE_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.le.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LE_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.le.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LE_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.le.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LE_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.le.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LE_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.le.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LE_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.le.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LT_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.lt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LT_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.lt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LT_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.lt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LT_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.lt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LT_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.lt.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_LT_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.lt.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGE_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.nge.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGE_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.nge.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGE_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.nge.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGE_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.nge.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGE_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.nge.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGE_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.nge.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGLE_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ngle.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGLE_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ngle.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGLE_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ngle.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGLE_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ngle.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGLE_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ngle.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGLE_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ngle.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGL_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ngl.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGL_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ngl.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGL_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ngl.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGL_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ngl.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGL_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ngl.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGL_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ngl.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGT_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ngt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGT_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ngt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGT_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ngt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGT_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ngt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGT_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ngt.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_NGT_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ngt.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLE_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ole.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLE_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ole.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLE_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ole.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLE_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ole.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLE_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ole.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLE_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ole.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLT_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.olt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLT_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.olt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLT_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.olt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLT_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.olt.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLT_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.olt.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_OLT_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.olt.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SEQ_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.seq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SEQ_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.seq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SEQ_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.seq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SEQ_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.seq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SEQ_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.seq.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SEQ_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.seq.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SF_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.sf.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SF_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.sf.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SF_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.sf.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SF_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.sf.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SF_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.sf.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_SF_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.sf.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UEQ_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ueq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UEQ_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ueq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UEQ_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ueq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UEQ_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ueq.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UEQ_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ueq.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UEQ_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ueq.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULE_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ule.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULE_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ule.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULE_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ule.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULE_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ule.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULE_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ule.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULE_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ule.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULT_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ult.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULT_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.ult.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULT_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ult.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULT_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.ult.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULT_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ult.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_ULT_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.ult.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UN_D32:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.un.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UN_D32_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::AFGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft)
+ AsmString = "c.un.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UN_D64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.un.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UN_D64_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft)
+ AsmString = "c.un.d $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UN_S:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.un.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::C_UN_S_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::FCC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::FGR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft)
+ AsmString = "c.un.s $\x02, $\x03";
+ break;
+ }
+ return false;
+ case Mips::DADDu:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).getReg() == Mips::ZERO_64) {
+ // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64)
+ AsmString = "move $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::DI:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (DI ZERO)
+ AsmString = "di";
+ break;
+ }
+ return false;
+ case Mips::DIV:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MI->getOperand(1).getReg() == MI->getOperand(0).getReg() &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt)
+ AsmString = "div $\x01, $\x03";
+ break;
+ }
+ return false;
+ case Mips::DIVU:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MI->getOperand(1).getReg() == MI->getOperand(0).getReg() &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt)
+ AsmString = "divu $\x01, $\x03";
+ break;
+ }
+ return false;
+ case Mips::DI_MM:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (DI_MM ZERO)
+ AsmString = "di";
+ break;
+ }
+ return false;
+ case Mips::DI_MMR6:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (DI_MMR6 ZERO)
+ AsmString = "di";
+ break;
+ }
+ return false;
+ case Mips::DMT:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (DMT ZERO)
+ AsmString = "dmt";
+ break;
+ }
+ return false;
+ case Mips::DSUB:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO_64 &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs)
+ AsmString = "dneg $\x01, $\x03";
+ break;
+ }
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO_64 &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(2).getReg() == MI->getOperand(0).getReg()) {
+ // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt)
+ AsmString = "dneg $\x01";
+ break;
+ }
+ return false;
+ case Mips::DSUBu:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO_64 &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs)
+ AsmString = "dnegu $\x01, $\x03";
+ break;
+ }
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO_64 &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(2).getReg() == MI->getOperand(0).getReg()) {
+ // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt)
+ AsmString = "dnegu $\x01";
+ break;
+ }
+ return false;
+ case Mips::DVPE:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (DVPE ZERO)
+ AsmString = "dvpe";
+ break;
+ }
+ return false;
+ case Mips::EI:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (EI ZERO)
+ AsmString = "ei";
+ break;
+ }
+ return false;
+ case Mips::EI_MM:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (EI_MM ZERO)
+ AsmString = "ei";
+ break;
+ }
+ return false;
+ case Mips::EI_MMR6:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (EI_MMR6 ZERO)
+ AsmString = "ei";
+ break;
+ }
+ return false;
+ case Mips::EMT:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (EMT ZERO)
+ AsmString = "emt";
+ break;
+ }
+ return false;
+ case Mips::EVPE:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).getReg() == Mips::ZERO) {
+ // (EVPE ZERO)
+ AsmString = "evpe";
+ break;
+ }
+ return false;
+ case Mips::HYPCALL:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (HYPCALL 0)
+ AsmString = "hypcall";
+ break;
+ }
+ return false;
+ case Mips::HYPCALL_MM:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (HYPCALL_MM 0)
+ AsmString = "hypcall";
+ break;
+ }
+ return false;
+ case Mips::JALR:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::ZERO &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (JALR ZERO, GPR32Opnd:$rs)
+ AsmString = "jr $\x02";
+ break;
+ }
+ return false;
+ case Mips::JALR64:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::ZERO_64 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (JALR64 ZERO_64, GPR64Opnd:$rs)
+ AsmString = "jr $\x02";
+ break;
+ }
+ return false;
+ case Mips::JALRC_HB_MMR6:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::RA &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (JALRC_HB_MMR6 RA, GPR32Opnd:$rs)
+ AsmString = "jalrc.hb $\x02";
+ break;
+ }
+ return false;
+ case Mips::JALRC_MMR6:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::RA &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (JALRC_MMR6 RA, GPR32Opnd:$rs)
+ AsmString = "jalrc $\x02";
+ break;
+ }
+ return false;
+ case Mips::JALR_HB:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::RA &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (JALR_HB RA, GPR32Opnd:$rs)
+ AsmString = "jalr.hb $\x02";
+ break;
+ }
+ return false;
+ case Mips::JALR_HB64:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::RA_64 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (JALR_HB64 RA_64, GPR64Opnd:$rs)
+ AsmString = "jalr.hb $\x02";
+ break;
+ }
+ return false;
+ case Mips::JIALC:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0) {
+ // (JIALC GPR32Opnd:$rs, 0)
+ AsmString = "jalrc $\x01";
+ break;
+ }
+ return false;
+ case Mips::JIALC64:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0) {
+ // (JIALC64 GPR64Opnd:$rs, 0)
+ AsmString = "jalrc $\x01";
+ break;
+ }
+ return false;
+ case Mips::JIC:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0) {
+ // (JIC GPR32Opnd:$rs, 0)
+ AsmString = "jrc $\x01";
+ break;
+ }
+ return false;
+ case Mips::JIC64:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 0) {
+ // (JIC64 GPR64Opnd:$rs, 0)
+ AsmString = "jrc $\x01";
+ break;
+ }
+ return false;
+ case Mips::MFTACX:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::AC0) {
+ // (MFTACX GPR32Opnd:$rt, AC0)
+ AsmString = "mftacx $\x01";
+ break;
+ }
+ return false;
+ case Mips::MFTC0:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::COP0RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0)
+ AsmString = "mftc0 $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::MFTHI:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::AC0) {
+ // (MFTHI GPR32Opnd:$rt, AC0)
+ AsmString = "mfthi $\x01";
+ break;
+ }
+ return false;
+ case Mips::MFTLO:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::AC0) {
+ // (MFTLO GPR32Opnd:$rt, AC0)
+ AsmString = "mftlo $\x01";
+ break;
+ }
+ return false;
+ case Mips::MOVE16_MM:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::ZERO &&
+ MI->getOperand(1).getReg() == Mips::ZERO) {
+ // (MOVE16_MM ZERO, ZERO)
+ AsmString = "nop";
+ break;
+ }
+ return false;
+ case Mips::MTTACX:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::AC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (MTTACX AC0, GPR32Opnd:$rt)
+ AsmString = "mttacx $\x02";
+ break;
+ }
+ return false;
+ case Mips::MTTC0:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::COP0RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0)
+ AsmString = "mttc0 $\x02, $\x01";
+ break;
+ }
+ return false;
+ case Mips::MTTHI:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::AC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (MTTHI AC0, GPR32Opnd:$rt)
+ AsmString = "mtthi $\x02";
+ break;
+ }
+ return false;
+ case Mips::MTTLO:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::AC0 &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (MTTLO AC0, GPR32Opnd:$rt)
+ AsmString = "mttlo $\x02";
+ break;
+ }
+ return false;
+ case Mips::Move32R16:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::ZERO &&
+ MI->getOperand(1).getReg() == Mips::S0) {
+ // (Move32R16 ZERO, S0)
+ AsmString = "nop";
+ break;
+ }
+ return false;
+ case Mips::NORImm:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MI->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
+ // (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm)
+ AsmString = "nor $\x01, $\x03";
+ break;
+ }
+ return false;
+ case Mips::NORImm64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MI->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
+ // (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm)
+ AsmString = "nor $\x01, $\x03";
+ break;
+ }
+ return false;
+ case Mips::OR:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).getReg() == Mips::ZERO) {
+ // (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO)
+ AsmString = "move $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::OR64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).getReg() == Mips::ZERO_64) {
+ // (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64)
+ AsmString = "move $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::RDHWR:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::HWRegsRegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0)
+ AsmString = "rdhwr $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::RDHWR_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::HWRegsRegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0)
+ AsmString = "rdhwr $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::RDHWR_MMR6:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::HWRegsRegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0)
+ AsmString = "rdhwr $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::SDBBP:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (SDBBP 0)
+ AsmString = "sdbbp";
+ break;
+ }
+ return false;
+ case Mips::SDBBP_MMR6:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (SDBBP_MMR6 0)
+ AsmString = "sdbbp";
+ break;
+ }
+ return false;
+ case Mips::SDBBP_R6:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (SDBBP_R6 0)
+ AsmString = "sdbbp";
+ break;
+ }
+ return false;
+ case Mips::SLL:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::ZERO &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (SLL ZERO, ZERO, 0)
+ AsmString = "nop";
+ break;
+ }
+ return false;
+ case Mips::SLL_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::ZERO &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (SLL_MM ZERO, ZERO, 0)
+ AsmString = "nop";
+ break;
+ }
+ return false;
+ case Mips::SLL_MMR6:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).getReg() == Mips::ZERO &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (SLL_MMR6 ZERO, ZERO, 0)
+ AsmString = "nop";
+ break;
+ }
+ return false;
+ case Mips::SLTImm64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MI->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
+ // (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm)
+ AsmString = "slt $\x01, $\x03";
+ break;
+ }
+ return false;
+ case Mips::SLTUImm64:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR64RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MI->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
+ // (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm)
+ AsmString = "sltu $\x01, $\x03";
+ break;
+ }
+ return false;
+ case Mips::SUB:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs)
+ AsmString = "neg $\x01, $\x03";
+ break;
+ }
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(2).getReg() == MI->getOperand(0).getReg()) {
+ // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt)
+ AsmString = "neg $\x01";
+ break;
+ }
+ return false;
+ case Mips::SUBU_MMR6:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs)
+ AsmString = "negu $\x01, $\x03";
+ break;
+ }
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(2).getReg() == MI->getOperand(0).getReg()) {
+ // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt)
+ AsmString = "negu $\x01";
+ break;
+ }
+ return false;
+ case Mips::SUB_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs)
+ AsmString = "neg $\x01, $\x03";
+ break;
+ }
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(2).getReg() == MI->getOperand(0).getReg()) {
+ // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt)
+ AsmString = "neg $\x01";
+ break;
+ }
+ return false;
+ case Mips::SUB_MMR6:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs)
+ AsmString = "neg $\x01, $\x03";
+ break;
+ }
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(2).getReg() == MI->getOperand(0).getReg()) {
+ // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt)
+ AsmString = "neg $\x01";
+ break;
+ }
+ return false;
+ case Mips::SUBu:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs)
+ AsmString = "negu $\x01, $\x03";
+ break;
+ }
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(2).getReg() == MI->getOperand(0).getReg()) {
+ // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt)
+ AsmString = "negu $\x01";
+ break;
+ }
+ return false;
+ case Mips::SUBu_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(2).getReg())) {
+ // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs)
+ AsmString = "negu $\x01, $\x03";
+ break;
+ }
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).getReg() == Mips::ZERO &&
+ MI->getOperand(2).isReg() &&
+ MI->getOperand(2).getReg() == MI->getOperand(0).getReg()) {
+ // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt)
+ AsmString = "negu $\x01";
+ break;
+ }
+ return false;
+ case Mips::SYNC:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (SYNC 0)
+ AsmString = "sync";
+ break;
+ }
+ return false;
+ case Mips::SYNC_MM:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (SYNC_MM 0)
+ AsmString = "sync";
+ break;
+ }
+ return false;
+ case Mips::SYNC_MMR6:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (SYNC_MMR6 0)
+ AsmString = "sync";
+ break;
+ }
+ return false;
+ case Mips::SYSCALL:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (SYSCALL 0)
+ AsmString = "syscall";
+ break;
+ }
+ return false;
+ case Mips::SYSCALL_MM:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (SYSCALL_MM 0)
+ AsmString = "syscall";
+ break;
+ }
+ return false;
+ case Mips::TEQ:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "teq $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TEQ_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "teq $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TGE:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tge $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TGEU:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tgeu $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TGEU_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tgeu $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TGE_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tge $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TLT:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tlt $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TLTU:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tltu $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TLTU_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tltu $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TLT_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tlt $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TNE:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tne $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::TNE_MM:
+ if (MI->getNumOperands() == 3 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
+ MI->getOperand(2).isImm() &&
+ MI->getOperand(2).getImm() == 0) {
+ // (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0)
+ AsmString = "tne $\x01, $\x02";
+ break;
+ }
+ return false;
+ case Mips::WAIT_MM:
+ if (MI->getNumOperands() == 1 &&
+ MI->getOperand(0).isImm() &&
+ MI->getOperand(0).getImm() == 0) {
+ // (WAIT_MM 0)
+ AsmString = "wait";
+ break;
+ }
+ return false;
+ case Mips::WRDSP:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 31) {
+ // (WRDSP GPR32Opnd:$rt, 31)
+ AsmString = "wrdsp $\x01";
+ break;
+ }
+ return false;
+ case Mips::WRDSP_MM:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(0).getReg()) &&
+ MI->getOperand(1).isImm() &&
+ MI->getOperand(1).getImm() == 31) {
+ // (WRDSP_MM GPR32Opnd:$rt, 31)
+ AsmString = "wrdsp $\x01";
+ break;
+ }
+ return false;
+ case Mips::YIELD:
+ if (MI->getNumOperands() == 2 &&
+ MI->getOperand(0).getReg() == Mips::ZERO &&
+ MI->getOperand(1).isReg() &&
+ MRI.getRegClass(Mips::GPR32RegClassID).contains(MI->getOperand(1).getReg())) {
+ // (YIELD ZERO, GPR32Opnd:$rs)
+ AsmString = "yield $\x02";
+ break;
+ }
+ return false;
+ }
+
+ unsigned I = 0;
+ while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
+ AsmString[I] != '$' && AsmString[I] != '\0')
+ ++I;
+ OS << '\t' << StringRef(AsmString, I);
+ if (AsmString[I] != '\0') {
+ if (AsmString[I] == ' ' || AsmString[I] == '\t') {
+ OS << '\t';
+ ++I;
+ }
+ do {
+ if (AsmString[I] == '$') {
+ ++I;
+ if (AsmString[I] == (char)0xff) {
+ ++I;
+ int OpIdx = AsmString[I++] - 1;
+ int PrintMethodIdx = AsmString[I++] - 1;
+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
+ } else
+ printOperand(MI, unsigned(AsmString[I++]) - 1, OS);
+ } else {
+ OS << AsmString[I++];
+ }
+ } while (AsmString[I] != '\0');
+ }
+
+ return true;
+}
+
+void MipsInstPrinter::printCustomAliasOperand(
+ const MCInst *MI, unsigned OpIdx,
+ unsigned PrintMethodIdx,
+ raw_ostream &OS) {
+ switch (PrintMethodIdx) {
+ default:
+ llvm_unreachable("Unknown PrintMethod kind");
+ break;
+ case 0:
+ printUImm<10>(MI, OpIdx, OS);
+ break;
+ }
+}
+
+#endif // PRINT_ALIAS_INSTR
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenCallingConv.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenCallingConv.inc
new file mode 100644
index 0000000..0dec034
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenCallingConv.inc
@@ -0,0 +1,841 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Calling Convention Implementation Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+static bool CC_Mips(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_Mips16RetHelper(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_MipsN(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_MipsN_FastCC(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_MipsN_SoftFloat(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_MipsN_VarArg(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_MipsO32_FP(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_MipsO32_FastCC(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_Mips_ByVal(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_Mips_FastCC(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_Mips_FixedArg(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_Mips_VarArg(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_F128(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_F128HardFloat(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_F128SoftFloat(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_Mips(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_MipsN(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool RetCC_MipsO32(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
+
+
+static bool CC_Mips(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (State.isVarArg()) {
+ if (!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)) {
+ if (!CC_Mips_VarArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+ }
+
+ if (!CC_Mips_FixedArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_Mips16RetHelper(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (ArgFlags.isByVal()) {
+ if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (LocVT == MVT::i32) {
+ static const MCPhysReg RegList1[] = {
+ Mips::V0, Mips::V1, Mips::A0, Mips::A1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_MipsN(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16 ||
+ LocVT == MVT::i32 ||
+ LocVT == MVT::i64) {
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
+ if (ArgFlags.isInReg()) {
+ LocVT = MVT::i64;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExtUpper;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExtUpper;
+ else
+ LocInfo = CCValAssign::AExtUpper;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16 ||
+ LocVT == MVT::i32) {
+ if (!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)) {
+ LocVT = MVT::i64;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+ }
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
+ if (LocVT == MVT::i32) {
+ if (!CC_MipsN_SoftFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64) {
+ static const MCPhysReg RegList1[] = {
+ Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
+ };
+ static const MCPhysReg RegList2[] = {
+ Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ static const MCPhysReg RegList3[] = {
+ Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19
+ };
+ static const MCPhysReg RegList4[] = {
+ Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ static const MCPhysReg RegList5[] = {
+ Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
+ };
+ static const MCPhysReg RegList6[] = {
+ Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ unsigned Offset7 = State.AllocateStack(4, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::i64 ||
+ LocVT == MVT::f64) {
+ unsigned Offset8 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_MipsN_FastCC(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i64) {
+ static const MCPhysReg RegList1[] = {
+ Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::T8_64, Mips::V1_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ static const MCPhysReg RegList2[] = {
+ Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64 ||
+ LocVT == MVT::f64) {
+ unsigned Offset3 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_MipsN_SoftFloat(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ static const MCPhysReg RegList1[] = {
+ Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3
+ };
+ static const MCPhysReg RegList2[] = {
+ Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+
+ unsigned Offset3 = State.AllocateStack(4, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_MipsN_VarArg(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16 ||
+ LocVT == MVT::i32 ||
+ LocVT == MVT::i64) {
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
+ if (ArgFlags.isInReg()) {
+ LocVT = MVT::i64;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExtUpper;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExtUpper;
+ else
+ LocInfo = CCValAssign::AExtUpper;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16 ||
+ LocVT == MVT::i32) {
+ LocVT = MVT::i64;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (LocVT == MVT::f32) {
+ static const MCPhysReg RegList1[] = {
+ Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::i64 ||
+ LocVT == MVT::f64) {
+ static const MCPhysReg RegList2[] = {
+ Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ unsigned Offset3 = State.AllocateStack(4, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::i64 ||
+ LocVT == MVT::f64) {
+ unsigned Offset4 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i1 ||
+ LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (LocVT == MVT::i32 ||
+ LocVT == MVT::f32) {
+ unsigned Offset1 = State.AllocateStack(4, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
+ return false;
+ }
+
+ if (LocVT == MVT::f64) {
+ unsigned Offset2 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_MipsO32_FP(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
+ if (!CC_MipsO32_FP32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
+ if (!CC_MipsO32_FP64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_MipsO32_FastCC(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::f64) {
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
+ static const MCPhysReg RegList1[] = {
+ Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useOddSPReg()) {
+ static const MCPhysReg RegList2[] = {
+ Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).noOddSPReg()) {
+ static const MCPhysReg RegList3[] = {
+ Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ unsigned Offset4 = State.AllocateStack(8, 8);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_Mips_ByVal(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
+ if (ArgFlags.isByVal()) {
+ State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
+ return false;
+ }
+ }
+
+ if (ArgFlags.isByVal()) {
+ State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_Mips_FastCC(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (ArgFlags.isByVal()) {
+ State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, 4, ArgFlags);
+ return false;
+ }
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (LocVT == MVT::i32) {
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isTargetNaCl()) {
+ static const MCPhysReg RegList1[] = {
+ Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::T8, Mips::V1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i32) {
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isTargetNaCl()) {
+ static const MCPhysReg RegList2[] = {
+ Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::V1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useOddSPReg()) {
+ static const MCPhysReg RegList3[] = {
+ Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).noOddSPReg()) {
+ static const MCPhysReg RegList4[] = {
+ Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18
+ };
+ if (unsigned Reg = State.AllocateReg(RegList4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i32 ||
+ LocVT == MVT::f32) {
+ unsigned Offset5 = State.AllocateStack(4, 4);
+ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
+ return false;
+ }
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
+ if (!CC_MipsO32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (!CC_MipsN_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_Mips_FixedArg(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (State.getCallingConv() != CallingConv::Fast) {
+ if (static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == MipsCCState::Mips16RetHelperConv) {
+ if (!CC_Mips16RetHelper(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+ }
+
+ if (ArgFlags.isByVal()) {
+ if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (LocVT == MVT::i64) {
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
+ if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) {
+ LocVT = MVT::f64;
+ LocInfo = CCValAssign::BCvt;
+ }
+ }
+ }
+
+ if (State.getCallingConv() == CallingConv::Fast) {
+ if (!CC_Mips_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
+ if (!CC_MipsO32_FP(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (!CC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool CC_Mips_VarArg(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (ArgFlags.isByVal()) {
+ if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) {
+ if (!CC_MipsO32_FP(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (!CC_MipsN_VarArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_F128(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
+ if (LocVT == MVT::i64) {
+ if (!RetCC_F128SoftFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+ }
+
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) {
+ if (LocVT == MVT::i64) {
+ if (!RetCC_F128HardFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_F128HardFloat(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ LocVT = MVT::f64;
+ LocInfo = CCValAssign::BCvt;
+
+ if (ArgFlags.isInReg()) {
+ static const MCPhysReg RegList1[] = {
+ Mips::D0_64, Mips::D1_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ static const MCPhysReg RegList2[] = {
+ Mips::D0_64, Mips::D2_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_F128SoftFloat(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ static const MCPhysReg RegList1[] = {
+ Mips::V0_64, Mips::A0_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_Mips(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N32()) {
+ if (!RetCC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N64()) {
+ if (!RetCC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+
+ if (!RetCC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_MipsN(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i64) {
+ if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) {
+ if (!RetCC_F128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
+ return false;
+ }
+ }
+
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16 ||
+ LocVT == MVT::i32 ||
+ LocVT == MVT::i64) {
+ if (ArgFlags.isInReg()) {
+ LocVT = MVT::i64;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+ }
+ }
+
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) {
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16 ||
+ LocVT == MVT::i32 ||
+ LocVT == MVT::i64) {
+ if (ArgFlags.isInReg()) {
+ LocVT = MVT::i64;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExtUpper;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExtUpper;
+ else
+ LocInfo = CCValAssign::AExtUpper;
+ }
+ }
+ }
+
+ if (LocVT == MVT::i64) {
+ static const MCPhysReg RegList1[] = {
+ Mips::V0_64, Mips::V1_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ static const MCPhysReg RegList2[] = {
+ Mips::F0, Mips::F2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ static const MCPhysReg RegList3[] = {
+ Mips::D0_64, Mips::D2_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ return true; // CC didn't match.
+}
+
+
+static bool RetCC_MipsO32(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i1 ||
+ LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (!static_cast<MipsCCState *>(&State)->WasOriginalRetVectorFloat(ValNo)) {
+ if (LocVT == MVT::i32) {
+ static const MCPhysReg RegList1[] = {
+ Mips::V0, Mips::V1, Mips::A0, Mips::A1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::f32) {
+ static const MCPhysReg RegList2[] = {
+ Mips::F0, Mips::F2
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
+ static const MCPhysReg RegList3[] = {
+ Mips::D0_64, Mips::D2_64
+ };
+ if (unsigned Reg = State.AllocateReg(RegList3)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ if (LocVT == MVT::f64) {
+ if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) {
+ static const MCPhysReg RegList4[] = {
+ Mips::D0, Mips::D1
+ };
+ if (unsigned Reg = State.AllocateReg(RegList4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ return true; // CC didn't match.
+}
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenDAGISel.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenDAGISel.inc
new file mode 100644
index 0000000..9d0b3d3
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenDAGISel.inc
@@ -0,0 +1,31140 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* DAG Instruction Selector for the Mips target *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+// *** NOTE: This file is #included into the middle of the target
+// *** instruction selector class. These functions are really methods.
+
+// If GET_DAGISEL_DECL is #defined with any value, only function
+// declarations will be included when this file is included.
+// If GET_DAGISEL_BODY is #defined, its value should be the name of
+// the instruction selector class. Function bodies will be emitted
+// and each function's name will be qualified with the name of the
+// class.
+//
+// When neither of the GET_DAGISEL* macros is defined, the functions
+// are emitted inline.
+
+#if defined(GET_DAGISEL_DECL) && defined(GET_DAGISEL_BODY)
+#error GET_DAGISEL_DECL and GET_DAGISEL_BODY cannot be both defined, undef both for inline definitions
+#endif
+
+#ifdef GET_DAGISEL_BODY
+#define LOCAL_DAGISEL_STRINGIZE(X) LOCAL_DAGISEL_STRINGIZE_(X)
+#define LOCAL_DAGISEL_STRINGIZE_(X) #X
+static_assert(sizeof(LOCAL_DAGISEL_STRINGIZE(GET_DAGISEL_BODY)) > 1,
+ "GET_DAGISEL_BODY is empty: it should be defined with the class name");
+#undef LOCAL_DAGISEL_STRINGIZE_
+#undef LOCAL_DAGISEL_STRINGIZE
+#endif
+
+#if !defined(GET_DAGISEL_DECL) && !defined(GET_DAGISEL_BODY)
+#define DAGISEL_INLINE 1
+#else
+#define DAGISEL_INLINE 0
+#endif
+
+#if !DAGISEL_INLINE
+#define DAGISEL_CLASS_COLONCOLON GET_DAGISEL_BODY ::
+#else
+#define DAGISEL_CLASS_COLONCOLON
+#endif
+
+#ifdef GET_DAGISEL_DECL
+void SelectCode(SDNode *N);
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+void DAGISEL_CLASS_COLONCOLON SelectCode(SDNode *N)
+{
+ // Some target values are emitted as 2 bytes, TARGET_VAL handles
+ // this.
+ #define TARGET_VAL(X) X & 255, unsigned(X) >> 8
+ static const unsigned char MatcherTable[] = {
+/* 0*/ OPC_SwitchOpcode /*177 cases */, 73|128,7/*969*/, TARGET_VAL(ISD::STORE),// ->974
+/* 5*/ OPC_RecordMemRef,
+/* 6*/ OPC_RecordNode, // #0 = 'st' chained node
+/* 7*/ OPC_Scope, 67|128,1/*195*/, /*->205*/ // 3 children in Scope
+/* 10*/ OPC_RecordChild1, // #1 = $v
+/* 11*/ OPC_Scope, 110, /*->123*/ // 2 children in Scope
+/* 13*/ OPC_CheckChild1Type, MVT::f64,
+/* 15*/ OPC_Scope, 67, /*->84*/ // 2 children in Scope
+/* 17*/ OPC_RecordChild2, // #2 = $a
+/* 18*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 20*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 22*/ OPC_Scope, 14, /*->38*/ // 4 children in Scope
+/* 24*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())
+/* 26*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // selectAddrRegImm:$a #3 #4
+/* 29*/ OPC_EmitMergeInputChains1_0,
+/* 30*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC1_D64_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st f64:{ *:[f64] }:$v, addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 54
+ // Dst: (SDC1_D64_MMR6 f64:{ *:[f64] }:$v, addrRegImm:{ *:[i32] }:$a)
+/* 38*/ /*Scope*/ 14, /*->53*/
+/* 39*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 41*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // selectAddrRegImm:$a #3 #4
+/* 44*/ OPC_EmitMergeInputChains1_0,
+/* 45*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC164), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st f64:{ *:[f64] }:$v, addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 53
+ // Dst: (SDC164 f64:{ *:[f64] }:$v, addrRegImm:{ *:[iPTR] }:$a)
+/* 53*/ /*Scope*/ 14, /*->68*/
+/* 54*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 56*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // selectAddrRegImm:$a #3 #4
+/* 59*/ OPC_EmitMergeInputChains1_0,
+/* 60*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC1), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st f64:{ *:[f64] }:$v, addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 53
+ // Dst: (SDC1 f64:{ *:[f64] }:$v, addrRegImm:{ *:[iPTR] }:$a)
+/* 68*/ /*Scope*/ 14, /*->83*/
+/* 69*/ OPC_CheckPatternPredicate, 3, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())
+/* 71*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // selectAddrRegImm:$a #3 #4
+/* 74*/ OPC_EmitMergeInputChains1_0,
+/* 75*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st f64:{ *:[f64] }:$v, addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 53
+ // Dst: (SDC1_MM f64:{ *:[f64] }:$v, addrRegImm:{ *:[i32] }:$a)
+/* 83*/ 0, /*End of Scope*/
+/* 84*/ /*Scope*/ 37, /*->122*/
+/* 85*/ OPC_MoveChild2,
+/* 86*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+/* 89*/ OPC_RecordChild0, // #2 = $base
+/* 90*/ OPC_RecordChild1, // #3 = $index
+/* 91*/ OPC_MoveParent,
+/* 92*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 94*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 96*/ OPC_Scope, 11, /*->109*/ // 2 children in Scope
+/* 98*/ OPC_CheckPatternPredicate, 4, // (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isTargetNaCl()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 100*/ OPC_EmitMergeInputChains1_0,
+/* 101*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDXC1), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st AFGR64Opnd:{ *:[f64] }:$fs, (add:{ *:[iPTR] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 27
+ // Dst: (SDXC1 AFGR64Opnd:{ *:[f64] }:$fs, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index)
+/* 109*/ /*Scope*/ 11, /*->121*/
+/* 110*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 112*/ OPC_EmitMergeInputChains1_0,
+/* 113*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDXC164), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FGR64Opnd:{ *:[f64] }:$fs, (add:{ *:[iPTR] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 27
+ // Dst: (SDXC164 FGR64Opnd:{ *:[f64] }:$fs, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index)
+/* 121*/ 0, /*End of Scope*/
+/* 122*/ 0, /*End of Scope*/
+/* 123*/ /*Scope*/ 80, /*->204*/
+/* 124*/ OPC_CheckChild1Type, MVT::f32,
+/* 126*/ OPC_Scope, 37, /*->165*/ // 2 children in Scope
+/* 128*/ OPC_RecordChild2, // #2 = $a
+/* 129*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 131*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 133*/ OPC_Scope, 14, /*->149*/ // 2 children in Scope
+/* 135*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 137*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // selectAddrRegImm:$a #3 #4
+/* 140*/ OPC_EmitMergeInputChains1_0,
+/* 141*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWC1), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st f32:{ *:[f32] }:$v, addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 53
+ // Dst: (SWC1 f32:{ *:[f32] }:$v, addrRegImm:{ *:[iPTR] }:$a)
+/* 149*/ /*Scope*/ 14, /*->164*/
+/* 150*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 152*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // selectAddrRegImm:$a #3 #4
+/* 155*/ OPC_EmitMergeInputChains1_0,
+/* 156*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st f32:{ *:[f32] }:$v, addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 53
+ // Dst: (SWC1_MM f32:{ *:[f32] }:$v, addrRegImm:{ *:[i32] }:$a)
+/* 164*/ 0, /*End of Scope*/
+/* 165*/ /*Scope*/ 37, /*->203*/
+/* 166*/ OPC_MoveChild2,
+/* 167*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+/* 170*/ OPC_RecordChild0, // #2 = $base
+/* 171*/ OPC_RecordChild1, // #3 = $index
+/* 172*/ OPC_MoveParent,
+/* 173*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 175*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 177*/ OPC_Scope, 11, /*->190*/ // 2 children in Scope
+/* 179*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isTargetNaCl()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 181*/ OPC_EmitMergeInputChains1_0,
+/* 182*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWXC1), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FGR32Opnd:{ *:[f32] }:$fs, (add:{ *:[iPTR] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 27
+ // Dst: (SWXC1 FGR32Opnd:{ *:[f32] }:$fs, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index)
+/* 190*/ /*Scope*/ 11, /*->202*/
+/* 191*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 193*/ OPC_EmitMergeInputChains1_0,
+/* 194*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWXC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FGR32Opnd:{ *:[f32] }:$fs, (add:{ *:[iPTR] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 27
+ // Dst: (SWXC1_MM FGR32Opnd:{ *:[f32] }:$fs, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index)
+/* 202*/ 0, /*End of Scope*/
+/* 203*/ 0, /*End of Scope*/
+/* 204*/ 0, /*End of Scope*/
+/* 205*/ /*Scope*/ 26, /*->232*/
+/* 206*/ OPC_CheckChild1Integer, 0,
+/* 208*/ OPC_CheckChild1Type, MVT::i32,
+/* 210*/ OPC_RecordChild2, // #1 = $dst
+/* 211*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 213*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 215*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 217*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$dst #2 #3
+/* 220*/ OPC_EmitMergeInputChains1_0,
+/* 221*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 224*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 4, 2, 3,
+ // Src: (st 0:{ *:[i32] }, addr:{ *:[iPTR] }:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (SW ZERO:{ *:[i32] }, addr:{ *:[iPTR] }:$dst)
+/* 232*/ /*Scope*/ 99|128,5/*739*/, /*->973*/
+/* 234*/ OPC_RecordChild1, // #1 = $rt
+/* 235*/ OPC_Scope, 44|128,2/*300*/, /*->538*/ // 14 children in Scope
+/* 238*/ OPC_CheckChild1Type, MVT::i32,
+/* 240*/ OPC_RecordChild2, // #2 = $addr
+/* 241*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 243*/ OPC_Scope, 38, /*->283*/ // 6 children in Scope
+/* 245*/ OPC_CheckPredicate, 2, // Predicate_truncstore
+/* 247*/ OPC_Scope, 16, /*->265*/ // 2 children in Scope
+/* 249*/ OPC_CheckPredicate, 3, // Predicate_truncstorei8
+/* 251*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 253*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 256*/ OPC_EmitMergeInputChains1_0,
+/* 257*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 13
+ // Dst: (SB GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 265*/ /*Scope*/ 16, /*->282*/
+/* 266*/ OPC_CheckPredicate, 4, // Predicate_truncstorei16
+/* 268*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 270*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 273*/ OPC_EmitMergeInputChains1_0,
+/* 274*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 13
+ // Dst: (SH GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 282*/ 0, /*End of Scope*/
+/* 283*/ /*Scope*/ 79, /*->363*/
+/* 284*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 286*/ OPC_Scope, 14, /*->302*/ // 5 children in Scope
+/* 288*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 290*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 293*/ OPC_EmitMergeInputChains1_0,
+/* 294*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SW GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 302*/ /*Scope*/ 14, /*->317*/
+/* 303*/ OPC_CheckPatternPredicate, 10, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 305*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 308*/ OPC_EmitMergeInputChains1_0,
+/* 309*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWC2), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st COP2Opnd:{ *:[i32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SWC2 COP2Opnd:{ *:[i32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)
+/* 317*/ /*Scope*/ 14, /*->332*/
+/* 318*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 320*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 323*/ OPC_EmitMergeInputChains1_0,
+/* 324*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC2), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st COP2Opnd:{ *:[i32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SDC2 COP2Opnd:{ *:[i32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)
+/* 332*/ /*Scope*/ 14, /*->347*/
+/* 333*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasCnMips()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 335*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 338*/ OPC_EmitMergeInputChains1_0,
+/* 339*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWC3), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st COP3Opnd:{ *:[i32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SWC3 COP3Opnd:{ *:[i32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)
+/* 347*/ /*Scope*/ 14, /*->362*/
+/* 348*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasCnMips()) && (!Subtarget->inMicroMipsMode())
+/* 350*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 353*/ OPC_EmitMergeInputChains1_0,
+/* 354*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC3), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st COP3Opnd:{ *:[i32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SDC3 COP3Opnd:{ *:[i32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)
+/* 362*/ 0, /*End of Scope*/
+/* 363*/ /*Scope*/ 38, /*->402*/
+/* 364*/ OPC_CheckPredicate, 2, // Predicate_truncstore
+/* 366*/ OPC_Scope, 16, /*->384*/ // 2 children in Scope
+/* 368*/ OPC_CheckPredicate, 3, // Predicate_truncstorei8
+/* 370*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 372*/ OPC_CheckComplexPat, /*CP*/3, /*#*/2, // selectAddr16:$addr #3 #4
+/* 375*/ OPC_EmitMergeInputChains1_0,
+/* 376*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SbRxRyOffMemX16), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st CPU16Regs:{ *:[i32] }:$r, addr16:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 13
+ // Dst: (SbRxRyOffMemX16 CPU16Regs:{ *:[i32] }:$r, addr16:{ *:[i32] }:$addr)
+/* 384*/ /*Scope*/ 16, /*->401*/
+/* 385*/ OPC_CheckPredicate, 4, // Predicate_truncstorei16
+/* 387*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 389*/ OPC_CheckComplexPat, /*CP*/3, /*#*/2, // selectAddr16:$addr #3 #4
+/* 392*/ OPC_EmitMergeInputChains1_0,
+/* 393*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ShRxRyOffMemX16), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st CPU16Regs:{ *:[i32] }:$r, addr16:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 13
+ // Dst: (ShRxRyOffMemX16 CPU16Regs:{ *:[i32] }:$r, addr16:{ *:[i32] }:$addr)
+/* 401*/ 0, /*End of Scope*/
+/* 402*/ /*Scope*/ 16, /*->419*/
+/* 403*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 405*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 407*/ OPC_CheckComplexPat, /*CP*/4, /*#*/2, // selectAddr16SP:$addr #3 #4
+/* 410*/ OPC_EmitMergeInputChains1_0,
+/* 411*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SwRxSpImmX16), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st CPU16Regs:{ *:[i32] }:$r, addr16sp:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SwRxSpImmX16 CPU16Regs:{ *:[i32] }:$r, addr16sp:{ *:[i32] }:$addr)
+/* 419*/ /*Scope*/ 38, /*->458*/
+/* 420*/ OPC_CheckPredicate, 2, // Predicate_truncstore
+/* 422*/ OPC_Scope, 16, /*->440*/ // 2 children in Scope
+/* 424*/ OPC_CheckPredicate, 3, // Predicate_truncstorei8
+/* 426*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 428*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 431*/ OPC_EmitMergeInputChains1_0,
+/* 432*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SB_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 13
+ // Dst: (SB_MM GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 440*/ /*Scope*/ 16, /*->457*/
+/* 441*/ OPC_CheckPredicate, 4, // Predicate_truncstorei16
+/* 443*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 445*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 448*/ OPC_EmitMergeInputChains1_0,
+/* 449*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SH_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 13
+ // Dst: (SH_MM GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 457*/ 0, /*End of Scope*/
+/* 458*/ /*Scope*/ 78, /*->537*/
+/* 459*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 461*/ OPC_Scope, 30, /*->493*/ // 2 children in Scope
+/* 463*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 465*/ OPC_Scope, 12, /*->479*/ // 2 children in Scope
+/* 467*/ OPC_CheckComplexPat, /*CP*/5, /*#*/2, // selectIntAddrLSL2MM:$addr #3 #4
+/* 470*/ OPC_EmitMergeInputChains1_0,
+/* 471*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW16_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPRMM16:{ *:[i32] }:$src, addrimm4lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SW16_MM GPRMM16:{ *:[i32] }:$src, addrimm4lsl2:{ *:[i32] }:$addr)
+/* 479*/ /*Scope*/ 12, /*->492*/
+/* 480*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 483*/ OPC_EmitMergeInputChains1_0,
+/* 484*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR32:{ *:[i32] }:$src, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SW_MM GPR32:{ *:[i32] }:$src, addr:{ *:[iPTR] }:$addr)
+/* 492*/ 0, /*End of Scope*/
+/* 493*/ /*Scope*/ 42, /*->536*/
+/* 494*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 496*/ OPC_Scope, 24, /*->522*/ // 2 children in Scope
+/* 498*/ OPC_CheckComplexPat, /*CP*/6, /*#*/2, // selectIntAddr11MM:$addr #3 #4
+/* 501*/ OPC_EmitMergeInputChains1_0,
+/* 502*/ OPC_Scope, 8, /*->512*/ // 2 children in Scope
+/* 504*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC2_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st COP2Opnd:{ *:[i32] }:$rt, addrimm11:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SDC2_MMR6 COP2Opnd:{ *:[i32] }:$rt, addrimm11:{ *:[i32] }:$addr)
+/* 512*/ /*Scope*/ 8, /*->521*/
+/* 513*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWC2_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st COP2Opnd:{ *:[i32] }:$rt, addrimm11:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SWC2_MMR6 COP2Opnd:{ *:[i32] }:$rt, addrimm11:{ *:[i32] }:$addr)
+/* 521*/ 0, /*End of Scope*/
+/* 522*/ /*Scope*/ 12, /*->535*/
+/* 523*/ OPC_CheckComplexPat, /*CP*/5, /*#*/2, // selectIntAddrLSL2MM:$addr #3 #4
+/* 526*/ OPC_EmitMergeInputChains1_0,
+/* 527*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW16_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPRMM16:{ *:[i32] }:$src, addrimm4lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SW16_MMR6 GPRMM16:{ *:[i32] }:$src, addrimm4lsl2:{ *:[i32] }:$addr)
+/* 535*/ 0, /*End of Scope*/
+/* 536*/ 0, /*End of Scope*/
+/* 537*/ 0, /*End of Scope*/
+/* 538*/ /*Scope*/ 39, /*->578*/
+/* 539*/ OPC_CheckChild1Type, MVT::f32,
+/* 541*/ OPC_RecordChild2, // #2 = $addr
+/* 542*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 544*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 546*/ OPC_Scope, 14, /*->562*/ // 2 children in Scope
+/* 548*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 550*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 553*/ OPC_EmitMergeInputChains1_0,
+/* 554*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWC1), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FGR32Opnd:{ *:[f32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SWC1 FGR32Opnd:{ *:[f32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)
+/* 562*/ /*Scope*/ 14, /*->577*/
+/* 563*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 565*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 568*/ OPC_EmitMergeInputChains1_0,
+/* 569*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FGR32Opnd:{ *:[f32] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SWC1_MM FGR32Opnd:{ *:[f32] }:$rt, addrDefault:{ *:[i32] }:$addr)
+/* 577*/ 0, /*End of Scope*/
+/* 578*/ /*Scope*/ 69, /*->648*/
+/* 579*/ OPC_CheckChild1Type, MVT::f64,
+/* 581*/ OPC_RecordChild2, // #2 = $addr
+/* 582*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 584*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 586*/ OPC_Scope, 14, /*->602*/ // 4 children in Scope
+/* 588*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 590*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 593*/ OPC_EmitMergeInputChains1_0,
+/* 594*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC164), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FGR64Opnd:{ *:[f64] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SDC164 FGR64Opnd:{ *:[f64] }:$rt, addrDefault:{ *:[iPTR] }:$addr)
+/* 602*/ /*Scope*/ 14, /*->617*/
+/* 603*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 605*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 608*/ OPC_EmitMergeInputChains1_0,
+/* 609*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC1), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st AFGR64Opnd:{ *:[f64] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SDC1 AFGR64Opnd:{ *:[f64] }:$rt, addrDefault:{ *:[iPTR] }:$addr)
+/* 617*/ /*Scope*/ 14, /*->632*/
+/* 618*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 620*/ OPC_CheckComplexPat, /*CP*/2, /*#*/2, // selectAddrDefault:$addr #3 #4
+/* 623*/ OPC_EmitMergeInputChains1_0,
+/* 624*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st AFGR64Opnd:{ *:[f64] }:$rt, addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SDC1_MM AFGR64Opnd:{ *:[f64] }:$rt, addrDefault:{ *:[i32] }:$addr)
+/* 632*/ /*Scope*/ 14, /*->647*/
+/* 633*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 635*/ OPC_CheckComplexPat, /*CP*/7, /*#*/2, // selectIntAddr16MM:$addr #3 #4
+/* 638*/ OPC_EmitMergeInputChains1_0,
+/* 639*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDC1_D64_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FGR64Opnd:{ *:[f64] }:$ft, addrimm16:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SDC1_D64_MMR6 FGR64Opnd:{ *:[f64] }:$ft, addrimm16:{ *:[i32] }:$addr)
+/* 647*/ 0, /*End of Scope*/
+/* 648*/ /*Scope*/ 80, /*->729*/
+/* 649*/ OPC_CheckChild1Type, MVT::i64,
+/* 651*/ OPC_RecordChild2, // #2 = $addr
+/* 652*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 654*/ OPC_Scope, 55, /*->711*/ // 2 children in Scope
+/* 656*/ OPC_CheckPredicate, 2, // Predicate_truncstore
+/* 658*/ OPC_Scope, 16, /*->676*/ // 3 children in Scope
+/* 660*/ OPC_CheckPredicate, 3, // Predicate_truncstorei8
+/* 662*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 664*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 667*/ OPC_EmitMergeInputChains1_0,
+/* 668*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SB64), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 13
+ // Dst: (SB64 GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 676*/ /*Scope*/ 16, /*->693*/
+/* 677*/ OPC_CheckPredicate, 4, // Predicate_truncstorei16
+/* 679*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 681*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 684*/ OPC_EmitMergeInputChains1_0,
+/* 685*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SH64), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 13
+ // Dst: (SH64 GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 693*/ /*Scope*/ 16, /*->710*/
+/* 694*/ OPC_CheckPredicate, 5, // Predicate_truncstorei32
+/* 696*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 698*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 701*/ OPC_EmitMergeInputChains1_0,
+/* 702*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW64), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 13
+ // Dst: (SW64 GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 710*/ 0, /*End of Scope*/
+/* 711*/ /*Scope*/ 16, /*->728*/
+/* 712*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 714*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 716*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 719*/ OPC_EmitMergeInputChains1_0,
+/* 720*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SD GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 728*/ 0, /*End of Scope*/
+/* 729*/ /*Scope*/ 21, /*->751*/
+/* 730*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 732*/ OPC_RecordChild2, // #2 = $addr
+/* 733*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 735*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 737*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 739*/ OPC_CheckComplexPat, /*CP*/8, /*#*/2, // selectIntAddrSImm10:$addr #3 #4
+/* 742*/ OPC_EmitMergeInputChains1_0,
+/* 743*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ST_B), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st MSA128BOpnd:{ *:[v16i8] }:$wd, addrimm10:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (ST_B MSA128BOpnd:{ *:[v16i8] }:$wd, addrimm10:{ *:[iPTR] }:$addr)
+/* 751*/ /*Scope*/ 21, /*->773*/
+/* 752*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 754*/ OPC_RecordChild2, // #2 = $addr
+/* 755*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 757*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 759*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 761*/ OPC_CheckComplexPat, /*CP*/9, /*#*/2, // selectIntAddrSImm10Lsl1:$addr #3 #4
+/* 764*/ OPC_EmitMergeInputChains1_0,
+/* 765*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st MSA128HOpnd:{ *:[v8i16] }:$wd, addrimm10lsl1:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (ST_H MSA128HOpnd:{ *:[v8i16] }:$wd, addrimm10lsl1:{ *:[iPTR] }:$addr)
+/* 773*/ /*Scope*/ 21, /*->795*/
+/* 774*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 776*/ OPC_RecordChild2, // #2 = $addr
+/* 777*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 779*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 781*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 783*/ OPC_CheckComplexPat, /*CP*/10, /*#*/2, // selectIntAddrSImm10Lsl2:$addr #3 #4
+/* 786*/ OPC_EmitMergeInputChains1_0,
+/* 787*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st MSA128WOpnd:{ *:[v4i32] }:$wd, addrimm10lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (ST_W MSA128WOpnd:{ *:[v4i32] }:$wd, addrimm10lsl2:{ *:[iPTR] }:$addr)
+/* 795*/ /*Scope*/ 21, /*->817*/
+/* 796*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 798*/ OPC_RecordChild2, // #2 = $addr
+/* 799*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 801*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 803*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 805*/ OPC_CheckComplexPat, /*CP*/11, /*#*/2, // selectIntAddrSImm10Lsl3:$addr #3 #4
+/* 808*/ OPC_EmitMergeInputChains1_0,
+/* 809*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st MSA128DOpnd:{ *:[v2i64] }:$wd, addrimm10lsl3:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (ST_D MSA128DOpnd:{ *:[v2i64] }:$wd, addrimm10lsl3:{ *:[iPTR] }:$addr)
+/* 817*/ /*Scope*/ 21, /*->839*/
+/* 818*/ OPC_CheckChild1Type, MVT::v8f16,
+/* 820*/ OPC_RecordChild2, // #2 = $addr
+/* 821*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 823*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 825*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 827*/ OPC_CheckComplexPat, /*CP*/9, /*#*/2, // selectIntAddrSImm10Lsl1:$addr #3 #4
+/* 830*/ OPC_EmitMergeInputChains1_0,
+/* 831*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ST_H), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st MSA128H:{ *:[v8f16] }:$ws, addrimm10lsl1:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (ST_H MSA128H:{ *:[v8f16] }:$ws, addrimm10lsl1:{ *:[iPTR] }:$addr)
+/* 839*/ /*Scope*/ 21, /*->861*/
+/* 840*/ OPC_CheckChild1Type, MVT::v4f32,
+/* 842*/ OPC_RecordChild2, // #2 = $addr
+/* 843*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 845*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 847*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 849*/ OPC_CheckComplexPat, /*CP*/10, /*#*/2, // selectIntAddrSImm10Lsl2:$addr #3 #4
+/* 852*/ OPC_EmitMergeInputChains1_0,
+/* 853*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ST_W), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st MSA128W:{ *:[v4f32] }:$ws, addrimm10lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (ST_W MSA128W:{ *:[v4f32] }:$ws, addrimm10lsl2:{ *:[iPTR] }:$addr)
+/* 861*/ /*Scope*/ 21, /*->883*/
+/* 862*/ OPC_CheckChild1Type, MVT::v2f64,
+/* 864*/ OPC_RecordChild2, // #2 = $addr
+/* 865*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 867*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 869*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 871*/ OPC_CheckComplexPat, /*CP*/11, /*#*/2, // selectIntAddrSImm10Lsl3:$addr #3 #4
+/* 874*/ OPC_EmitMergeInputChains1_0,
+/* 875*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ST_D), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st MSA128D:{ *:[v2f64] }:$ws, addrimm10lsl3:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (ST_D MSA128D:{ *:[v2f64] }:$ws, addrimm10lsl3:{ *:[iPTR] }:$addr)
+/* 883*/ /*Scope*/ 32, /*->916*/
+/* 884*/ OPC_CheckChild1Type, MVT::v2i16,
+/* 886*/ OPC_RecordChild2, // #2 = $a
+/* 887*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 889*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 891*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 893*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$a #3 #4
+/* 896*/ OPC_EmitMergeInputChains1_0,
+/* 897*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 900*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 908*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 6, 3, 4,
+ // Src: (st DSPR:{ *:[v2i16] }:$val, addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SW (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$val, GPR32:{ *:[i32] }), addr:{ *:[iPTR] }:$a)
+/* 916*/ /*Scope*/ 32, /*->949*/
+/* 917*/ OPC_CheckChild1Type, MVT::v4i8,
+/* 919*/ OPC_RecordChild2, // #2 = $a
+/* 920*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 922*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 924*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 926*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$a #3 #4
+/* 929*/ OPC_EmitMergeInputChains1_0,
+/* 930*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 933*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 941*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 6, 3, 4,
+ // Src: (st DSPR:{ *:[v4i8] }:$val, addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (SW (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$val, GPR32:{ *:[i32] }), addr:{ *:[iPTR] }:$a)
+/* 949*/ /*Scope*/ 22, /*->972*/
+/* 950*/ OPC_CheckChild1Type, MVT::f16,
+/* 952*/ OPC_RecordChild2, // #2 = $addr
+/* 953*/ OPC_RecordChild2, // #3 = $addrimm10
+/* 954*/ OPC_CheckPredicate, 0, // Predicate_unindexedstore
+/* 956*/ OPC_CheckPredicate, 1, // Predicate_store
+/* 958*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 960*/ OPC_CheckComplexPat, /*CP*/8, /*#*/3, // selectIntAddrSImm10:$addr #4 #5
+/* 963*/ OPC_EmitMergeInputChains1_0,
+/* 964*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ST_F16), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st MSA128F16:{ *:[f16] }:$ws, (addrimm10:{ *:[iPTR] }):$addr)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 13
+ // Dst: (ST_F16 MSA128F16:{ *:[f16] }:$ws, (addrimm10:{ *:[iPTR] }):$addr)
+/* 972*/ 0, /*End of Scope*/
+/* 973*/ 0, /*End of Scope*/
+/* 974*/ /*SwitchOpcode*/ 79|128,11/*1487*/, TARGET_VAL(ISD::LOAD),// ->2465
+/* 978*/ OPC_RecordMemRef,
+/* 979*/ OPC_RecordNode, // #0 = 'ld' chained node
+/* 980*/ OPC_Scope, 121, /*->1103*/ // 5 children in Scope
+/* 982*/ OPC_RecordChild1, // #1 = $a
+/* 983*/ OPC_CheckPredicate, 6, // Predicate_unindexedload
+/* 985*/ OPC_CheckType, MVT::i32,
+/* 987*/ OPC_Scope, 38, /*->1027*/ // 4 children in Scope
+/* 989*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 991*/ OPC_Scope, 16, /*->1009*/ // 2 children in Scope
+/* 993*/ OPC_CheckPredicate, 8, // Predicate_zextloadi8
+/* 995*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 997*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 1000*/ OPC_EmitMergeInputChains1_0,
+/* 1001*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBu), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 53
+ // Dst: (LBu:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)
+/* 1009*/ /*Scope*/ 16, /*->1026*/
+/* 1010*/ OPC_CheckPredicate, 9, // Predicate_zextloadi16
+/* 1012*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1014*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 1017*/ OPC_EmitMergeInputChains1_0,
+/* 1018*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHu), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 53
+ // Dst: (LHu:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)
+/* 1026*/ 0, /*End of Scope*/
+/* 1027*/ /*Scope*/ 38, /*->1066*/
+/* 1028*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1030*/ OPC_Scope, 16, /*->1048*/ // 2 children in Scope
+/* 1032*/ OPC_CheckPredicate, 8, // Predicate_sextloadi8
+/* 1034*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1036*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 1039*/ OPC_EmitMergeInputChains1_0,
+/* 1040*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 53
+ // Dst: (LB:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)
+/* 1048*/ /*Scope*/ 16, /*->1065*/
+/* 1049*/ OPC_CheckPredicate, 9, // Predicate_sextloadi16
+/* 1051*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1053*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 1056*/ OPC_EmitMergeInputChains1_0,
+/* 1057*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 53
+ // Dst: (LH:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)
+/* 1065*/ 0, /*End of Scope*/
+/* 1066*/ /*Scope*/ 16, /*->1083*/
+/* 1067*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 1069*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1071*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 1074*/ OPC_EmitMergeInputChains1_0,
+/* 1075*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 53
+ // Dst: (LW:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)
+/* 1083*/ /*Scope*/ 18, /*->1102*/
+/* 1084*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1086*/ OPC_CheckPredicate, 9, // Predicate_sextloadi16
+/* 1088*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1090*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 1093*/ OPC_EmitMergeInputChains1_0,
+/* 1094*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 53
+ // Dst: (LH_MM:{ *:[i32] } addrRegImm:{ *:[iPTR] }:$a)
+/* 1102*/ 0, /*End of Scope*/
+/* 1103*/ /*Scope*/ 61, /*->1165*/
+/* 1104*/ OPC_MoveChild1,
+/* 1105*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+/* 1108*/ OPC_RecordChild0, // #1 = $base
+/* 1109*/ OPC_RecordChild1, // #2 = $index
+/* 1110*/ OPC_CheckType, MVT::i32,
+/* 1112*/ OPC_MoveParent,
+/* 1113*/ OPC_CheckPredicate, 6, // Predicate_unindexedload
+/* 1115*/ OPC_CheckType, MVT::i32,
+/* 1117*/ OPC_Scope, 15, /*->1134*/ // 3 children in Scope
+/* 1119*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1121*/ OPC_CheckPredicate, 8, // Predicate_zextloadi8
+/* 1123*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 1125*/ OPC_EmitMergeInputChains1_0,
+/* 1126*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBUX), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 27
+ // Dst: (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
+/* 1134*/ /*Scope*/ 15, /*->1150*/
+/* 1135*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1137*/ OPC_CheckPredicate, 9, // Predicate_sextloadi16
+/* 1139*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 1141*/ OPC_EmitMergeInputChains1_0,
+/* 1142*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHX), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 27
+ // Dst: (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
+/* 1150*/ /*Scope*/ 13, /*->1164*/
+/* 1151*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 1153*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 1155*/ OPC_EmitMergeInputChains1_0,
+/* 1156*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWX), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 27
+ // Dst: (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
+/* 1164*/ 0, /*End of Scope*/
+/* 1165*/ /*Scope*/ 42|128,7/*938*/, /*->2105*/
+/* 1167*/ OPC_RecordChild1, // #1 = $addr
+/* 1168*/ OPC_CheckPredicate, 6, // Predicate_unindexedload
+/* 1170*/ OPC_Scope, 20, /*->1192*/ // 27 children in Scope
+/* 1172*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1174*/ OPC_CheckPredicate, 8, // Predicate_sextloadi8
+/* 1176*/ OPC_CheckType, MVT::i32,
+/* 1178*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1180*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1183*/ OPC_EmitMergeInputChains1_0,
+/* 1184*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 13
+ // Dst: (LB:{ *:[i32] } addr:{ *:[iPTR] }:$addr)
+/* 1192*/ /*Scope*/ 20, /*->1213*/
+/* 1193*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1195*/ OPC_CheckPredicate, 8, // Predicate_zextloadi8
+/* 1197*/ OPC_CheckType, MVT::i32,
+/* 1199*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1201*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1204*/ OPC_EmitMergeInputChains1_0,
+/* 1205*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBu), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 13
+ // Dst: (LBu:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1213*/ /*Scope*/ 20, /*->1234*/
+/* 1214*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1216*/ OPC_CheckPredicate, 9, // Predicate_sextloadi16
+/* 1218*/ OPC_CheckType, MVT::i32,
+/* 1220*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1222*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1225*/ OPC_EmitMergeInputChains1_0,
+/* 1226*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 13
+ // Dst: (LH:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1234*/ /*Scope*/ 20, /*->1255*/
+/* 1235*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1237*/ OPC_CheckPredicate, 9, // Predicate_zextloadi16
+/* 1239*/ OPC_CheckType, MVT::i32,
+/* 1241*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1243*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1246*/ OPC_EmitMergeInputChains1_0,
+/* 1247*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHu), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 13
+ // Dst: (LHu:{ *:[i32] } addr:{ *:[iPTR] }:$addr)
+/* 1255*/ /*Scope*/ 81, /*->1337*/
+/* 1256*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 1258*/ OPC_CheckType, MVT::i32,
+/* 1260*/ OPC_Scope, 14, /*->1276*/ // 5 children in Scope
+/* 1262*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1264*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1267*/ OPC_EmitMergeInputChains1_0,
+/* 1268*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LW:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1276*/ /*Scope*/ 14, /*->1291*/
+/* 1277*/ OPC_CheckPatternPredicate, 10, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 1279*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1282*/ OPC_EmitMergeInputChains1_0,
+/* 1283*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWC2), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LWC2:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1291*/ /*Scope*/ 14, /*->1306*/
+/* 1292*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 1294*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1297*/ OPC_EmitMergeInputChains1_0,
+/* 1298*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC2), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LDC2:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1306*/ /*Scope*/ 14, /*->1321*/
+/* 1307*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasCnMips()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 1309*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1312*/ OPC_EmitMergeInputChains1_0,
+/* 1313*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWC3), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LWC3:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1321*/ /*Scope*/ 14, /*->1336*/
+/* 1322*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasCnMips()) && (!Subtarget->inMicroMipsMode())
+/* 1324*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1327*/ OPC_EmitMergeInputChains1_0,
+/* 1328*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC3), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LDC3:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1336*/ 0, /*End of Scope*/
+/* 1337*/ /*Scope*/ 57, /*->1395*/
+/* 1338*/ OPC_CheckPredicate, 12, // Predicate_extload
+/* 1340*/ OPC_CheckType, MVT::i32,
+/* 1342*/ OPC_Scope, 16, /*->1360*/ // 3 children in Scope
+/* 1344*/ OPC_CheckPredicate, 13, // Predicate_extloadi1
+/* 1346*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1348*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1351*/ OPC_EmitMergeInputChains1_0,
+/* 1352*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBu), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> - Complexity = 13
+ // Dst: (LBu:{ *:[i32] } addr:{ *:[iPTR] }:$src)
+/* 1360*/ /*Scope*/ 16, /*->1377*/
+/* 1361*/ OPC_CheckPredicate, 8, // Predicate_extloadi8
+/* 1363*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1365*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1368*/ OPC_EmitMergeInputChains1_0,
+/* 1369*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBu), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 13
+ // Dst: (LBu:{ *:[i32] } addr:{ *:[iPTR] }:$src)
+/* 1377*/ /*Scope*/ 16, /*->1394*/
+/* 1378*/ OPC_CheckPredicate, 9, // Predicate_extloadi16
+/* 1380*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1382*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1385*/ OPC_EmitMergeInputChains1_0,
+/* 1386*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHu), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 13
+ // Dst: (LHu:{ *:[i32] } addr:{ *:[iPTR] }:$src)
+/* 1394*/ 0, /*End of Scope*/
+/* 1395*/ /*Scope*/ 20, /*->1416*/
+/* 1396*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1398*/ OPC_CheckPredicate, 8, // Predicate_sextloadi8
+/* 1400*/ OPC_CheckType, MVT::i64,
+/* 1402*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 1404*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1407*/ OPC_EmitMergeInputChains1_0,
+/* 1408*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 13
+ // Dst: (LB64:{ *:[i64] } addr:{ *:[iPTR] }:$addr)
+/* 1416*/ /*Scope*/ 20, /*->1437*/
+/* 1417*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1419*/ OPC_CheckPredicate, 8, // Predicate_zextloadi8
+/* 1421*/ OPC_CheckType, MVT::i64,
+/* 1423*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 1425*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1428*/ OPC_EmitMergeInputChains1_0,
+/* 1429*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBu64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 13
+ // Dst: (LBu64:{ *:[i64] } addr:{ *:[iPTR] }:$addr)
+/* 1437*/ /*Scope*/ 20, /*->1458*/
+/* 1438*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1440*/ OPC_CheckPredicate, 9, // Predicate_sextloadi16
+/* 1442*/ OPC_CheckType, MVT::i64,
+/* 1444*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 1446*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1449*/ OPC_EmitMergeInputChains1_0,
+/* 1450*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 13
+ // Dst: (LH64:{ *:[i64] } addr:{ *:[iPTR] }:$addr)
+/* 1458*/ /*Scope*/ 20, /*->1479*/
+/* 1459*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1461*/ OPC_CheckPredicate, 9, // Predicate_zextloadi16
+/* 1463*/ OPC_CheckType, MVT::i64,
+/* 1465*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 1467*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1470*/ OPC_EmitMergeInputChains1_0,
+/* 1471*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHu64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 13
+ // Dst: (LHu64:{ *:[i64] } addr:{ *:[iPTR] }:$addr)
+/* 1479*/ /*Scope*/ 20, /*->1500*/
+/* 1480*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1482*/ OPC_CheckPredicate, 14, // Predicate_sextloadi32
+/* 1484*/ OPC_CheckType, MVT::i64,
+/* 1486*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 1488*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1491*/ OPC_EmitMergeInputChains1_0,
+/* 1492*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 13
+ // Dst: (LW64:{ *:[i64] } addr:{ *:[iPTR] }:$addr)
+/* 1500*/ /*Scope*/ 20, /*->1521*/
+/* 1501*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1503*/ OPC_CheckPredicate, 14, // Predicate_zextloadi32
+/* 1505*/ OPC_CheckType, MVT::i64,
+/* 1507*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1509*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1512*/ OPC_EmitMergeInputChains1_0,
+/* 1513*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWu), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 13
+ // Dst: (LWu:{ *:[i64] } addr:{ *:[iPTR] }:$addr)
+/* 1521*/ /*Scope*/ 18, /*->1540*/
+/* 1522*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 1524*/ OPC_CheckType, MVT::i64,
+/* 1526*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 1528*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1531*/ OPC_EmitMergeInputChains1_0,
+/* 1532*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD:{ *:[i64] } addr:{ *:[iPTR] }:$addr)
+/* 1540*/ /*Scope*/ 74, /*->1615*/
+/* 1541*/ OPC_CheckPredicate, 12, // Predicate_extload
+/* 1543*/ OPC_CheckType, MVT::i64,
+/* 1545*/ OPC_Scope, 16, /*->1563*/ // 4 children in Scope
+/* 1547*/ OPC_CheckPredicate, 13, // Predicate_extloadi1
+/* 1549*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 1551*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1554*/ OPC_EmitMergeInputChains1_0,
+/* 1555*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> - Complexity = 13
+ // Dst: (LB64:{ *:[i64] } addr:{ *:[iPTR] }:$src)
+/* 1563*/ /*Scope*/ 16, /*->1580*/
+/* 1564*/ OPC_CheckPredicate, 8, // Predicate_extloadi8
+/* 1566*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 1568*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1571*/ OPC_EmitMergeInputChains1_0,
+/* 1572*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 13
+ // Dst: (LB64:{ *:[i64] } addr:{ *:[iPTR] }:$src)
+/* 1580*/ /*Scope*/ 16, /*->1597*/
+/* 1581*/ OPC_CheckPredicate, 9, // Predicate_extloadi16
+/* 1583*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 1585*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1588*/ OPC_EmitMergeInputChains1_0,
+/* 1589*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 13
+ // Dst: (LH64:{ *:[i64] } addr:{ *:[iPTR] }:$src)
+/* 1597*/ /*Scope*/ 16, /*->1614*/
+/* 1598*/ OPC_CheckPredicate, 14, // Predicate_extloadi32
+/* 1600*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 1602*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1605*/ OPC_EmitMergeInputChains1_0,
+/* 1606*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 13
+ // Dst: (LW64:{ *:[i64] } addr:{ *:[iPTR] }:$src)
+/* 1614*/ 0, /*End of Scope*/
+/* 1615*/ /*Scope*/ 20, /*->1636*/
+/* 1616*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1618*/ OPC_CheckPredicate, 8, // Predicate_sextloadi8
+/* 1620*/ OPC_CheckType, MVT::i32,
+/* 1622*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 1624*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // selectAddr16:$addr #2 #3
+/* 1627*/ OPC_EmitMergeInputChains1_0,
+/* 1628*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LbRxRyOffMemX16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr16:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 13
+ // Dst: (LbRxRyOffMemX16:{ *:[i32] } addr16:{ *:[i32] }:$addr)
+/* 1636*/ /*Scope*/ 20, /*->1657*/
+/* 1637*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1639*/ OPC_CheckPredicate, 8, // Predicate_zextloadi8
+/* 1641*/ OPC_CheckType, MVT::i32,
+/* 1643*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 1645*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // selectAddr16:$addr #2 #3
+/* 1648*/ OPC_EmitMergeInputChains1_0,
+/* 1649*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LbuRxRyOffMemX16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr16:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 13
+ // Dst: (LbuRxRyOffMemX16:{ *:[i32] } addr16:{ *:[i32] }:$addr)
+/* 1657*/ /*Scope*/ 20, /*->1678*/
+/* 1658*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1660*/ OPC_CheckPredicate, 9, // Predicate_sextloadi16
+/* 1662*/ OPC_CheckType, MVT::i32,
+/* 1664*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 1666*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // selectAddr16:$addr #2 #3
+/* 1669*/ OPC_EmitMergeInputChains1_0,
+/* 1670*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LhRxRyOffMemX16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr16:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 13
+ // Dst: (LhRxRyOffMemX16:{ *:[i32] } addr16:{ *:[i32] }:$addr)
+/* 1678*/ /*Scope*/ 20, /*->1699*/
+/* 1679*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1681*/ OPC_CheckPredicate, 9, // Predicate_zextloadi16
+/* 1683*/ OPC_CheckType, MVT::i32,
+/* 1685*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 1687*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // selectAddr16:$addr #2 #3
+/* 1690*/ OPC_EmitMergeInputChains1_0,
+/* 1691*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LhuRxRyOffMemX16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr16:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 13
+ // Dst: (LhuRxRyOffMemX16:{ *:[i32] } addr16:{ *:[i32] }:$addr)
+/* 1699*/ /*Scope*/ 18, /*->1718*/
+/* 1700*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 1702*/ OPC_CheckType, MVT::i32,
+/* 1704*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 1706*/ OPC_CheckComplexPat, /*CP*/4, /*#*/1, // selectAddr16SP:$addr #2 #3
+/* 1709*/ OPC_EmitMergeInputChains1_0,
+/* 1710*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LwRxSpImmX16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr16sp:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LwRxSpImmX16:{ *:[i32] } addr16sp:{ *:[i32] }:$addr)
+/* 1718*/ /*Scope*/ 40, /*->1759*/
+/* 1719*/ OPC_CheckPredicate, 12, // Predicate_extload
+/* 1721*/ OPC_CheckType, MVT::i32,
+/* 1723*/ OPC_Scope, 16, /*->1741*/ // 2 children in Scope
+/* 1725*/ OPC_CheckPredicate, 8, // Predicate_extloadi8
+/* 1727*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 1729*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // selectAddr16:$src #2 #3
+/* 1732*/ OPC_EmitMergeInputChains1_0,
+/* 1733*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LbuRxRyOffMemX16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr16:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 13
+ // Dst: (LbuRxRyOffMemX16:{ *:[i32] } addr16:{ *:[i32] }:$src)
+/* 1741*/ /*Scope*/ 16, /*->1758*/
+/* 1742*/ OPC_CheckPredicate, 9, // Predicate_extloadi16
+/* 1744*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 1746*/ OPC_CheckComplexPat, /*CP*/3, /*#*/1, // selectAddr16:$src #2 #3
+/* 1749*/ OPC_EmitMergeInputChains1_0,
+/* 1750*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LhuRxRyOffMemX16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr16:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 13
+ // Dst: (LhuRxRyOffMemX16:{ *:[i32] } addr16:{ *:[i32] }:$src)
+/* 1758*/ 0, /*End of Scope*/
+/* 1759*/ /*Scope*/ 20, /*->1780*/
+/* 1760*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1762*/ OPC_CheckPredicate, 8, // Predicate_sextloadi8
+/* 1764*/ OPC_CheckType, MVT::i32,
+/* 1766*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1768*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1771*/ OPC_EmitMergeInputChains1_0,
+/* 1772*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 13
+ // Dst: (LB_MM:{ *:[i32] } addr:{ *:[i32] }:$addr)
+/* 1780*/ /*Scope*/ 20, /*->1801*/
+/* 1781*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1783*/ OPC_CheckPredicate, 8, // Predicate_zextloadi8
+/* 1785*/ OPC_CheckType, MVT::i32,
+/* 1787*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1789*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1792*/ OPC_EmitMergeInputChains1_0,
+/* 1793*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBu_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 13
+ // Dst: (LBu_MM:{ *:[i32] } addr:{ *:[i32] }:$addr)
+/* 1801*/ /*Scope*/ 20, /*->1822*/
+/* 1802*/ OPC_CheckPredicate, 10, // Predicate_sextload
+/* 1804*/ OPC_CheckPredicate, 9, // Predicate_sextloadi16
+/* 1806*/ OPC_CheckType, MVT::i32,
+/* 1808*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1810*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1813*/ OPC_EmitMergeInputChains1_0,
+/* 1814*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 13
+ // Dst: (LH_MM:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1822*/ /*Scope*/ 40, /*->1863*/
+/* 1823*/ OPC_CheckPredicate, 7, // Predicate_zextload
+/* 1825*/ OPC_CheckType, MVT::i32,
+/* 1827*/ OPC_Scope, 16, /*->1845*/ // 2 children in Scope
+/* 1829*/ OPC_CheckPredicate, 9, // Predicate_zextloadi16
+/* 1831*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1833*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1836*/ OPC_EmitMergeInputChains1_0,
+/* 1837*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHu_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 13
+ // Dst: (LHu_MM:{ *:[i32] } addr:{ *:[iPTR] }:$addr)
+/* 1845*/ /*Scope*/ 16, /*->1862*/
+/* 1846*/ OPC_CheckPredicate, 14, // Predicate_zextloadi32
+/* 1848*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 1850*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // selectIntAddr12MM:$addr #2 #3
+/* 1853*/ OPC_EmitMergeInputChains1_0,
+/* 1854*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWU_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrimm12:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 13
+ // Dst: (LWU_MM:{ *:[i32] } addrimm12:{ *:[iPTR] }:$addr)
+/* 1862*/ 0, /*End of Scope*/
+/* 1863*/ /*Scope*/ 34, /*->1898*/
+/* 1864*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 1866*/ OPC_CheckType, MVT::i32,
+/* 1868*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1870*/ OPC_Scope, 12, /*->1884*/ // 2 children in Scope
+/* 1872*/ OPC_CheckComplexPat, /*CP*/5, /*#*/1, // selectIntAddrLSL2MM:$addr #2 #3
+/* 1875*/ OPC_EmitMergeInputChains1_0,
+/* 1876*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW16_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrimm4lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LW16_MM:{ *:[i32] } addrimm4lsl2:{ *:[i32] }:$addr)
+/* 1884*/ /*Scope*/ 12, /*->1897*/
+/* 1885*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #2 #3
+/* 1888*/ OPC_EmitMergeInputChains1_0,
+/* 1889*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LW_MM:{ *:[i32] } addr:{ *:[iPTR] }:$addr)
+/* 1897*/ 0, /*End of Scope*/
+/* 1898*/ /*Scope*/ 57, /*->1956*/
+/* 1899*/ OPC_CheckPredicate, 12, // Predicate_extload
+/* 1901*/ OPC_CheckType, MVT::i32,
+/* 1903*/ OPC_Scope, 16, /*->1921*/ // 3 children in Scope
+/* 1905*/ OPC_CheckPredicate, 13, // Predicate_extloadi1
+/* 1907*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1909*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1912*/ OPC_EmitMergeInputChains1_0,
+/* 1913*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBu_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>> - Complexity = 13
+ // Dst: (LBu_MM:{ *:[i32] } addr:{ *:[i32] }:$src)
+/* 1921*/ /*Scope*/ 16, /*->1938*/
+/* 1922*/ OPC_CheckPredicate, 8, // Predicate_extloadi8
+/* 1924*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1926*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1929*/ OPC_EmitMergeInputChains1_0,
+/* 1930*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBu_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 13
+ // Dst: (LBu_MM:{ *:[i32] } addr:{ *:[i32] }:$src)
+/* 1938*/ /*Scope*/ 16, /*->1955*/
+/* 1939*/ OPC_CheckPredicate, 9, // Predicate_extloadi16
+/* 1941*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 1943*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$src #2 #3
+/* 1946*/ OPC_EmitMergeInputChains1_0,
+/* 1947*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHu_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addr:{ *:[iPTR] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 13
+ // Dst: (LHu_MM:{ *:[i32] } addr:{ *:[iPTR] }:$src)
+/* 1955*/ 0, /*End of Scope*/
+/* 1956*/ /*Scope*/ 18|128,1/*146*/, /*->2104*/
+/* 1958*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 1960*/ OPC_SwitchType /*3 cases */, 42, MVT::i32,// ->2005
+/* 1963*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 1965*/ OPC_Scope, 12, /*->1979*/ // 2 children in Scope
+/* 1967*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 1970*/ OPC_EmitMergeInputChains1_0,
+/* 1971*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LW_MMR6:{ *:[i32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 1979*/ /*Scope*/ 24, /*->2004*/
+/* 1980*/ OPC_CheckComplexPat, /*CP*/6, /*#*/1, // selectIntAddr11MM:$addr #2 #3
+/* 1983*/ OPC_EmitMergeInputChains1_0,
+/* 1984*/ OPC_Scope, 8, /*->1994*/ // 2 children in Scope
+/* 1986*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC2_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrimm11:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LDC2_MMR6:{ *:[i32] } addrimm11:{ *:[i32] }:$addr)
+/* 1994*/ /*Scope*/ 8, /*->2003*/
+/* 1995*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWC2_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } addrimm11:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LWC2_MMR6:{ *:[i32] } addrimm11:{ *:[i32] }:$addr)
+/* 2003*/ 0, /*End of Scope*/
+/* 2004*/ 0, /*End of Scope*/
+/* 2005*/ /*SwitchType*/ 62, MVT::f64,// ->2069
+/* 2007*/ OPC_Scope, 14, /*->2023*/ // 4 children in Scope
+/* 2009*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())
+/* 2011*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 2014*/ OPC_EmitMergeInputChains1_0,
+/* 2015*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC1_D64_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 54
+ // Dst: (LDC1_D64_MMR6:{ *:[f64] } addrRegImm:{ *:[i32] }:$a)
+/* 2023*/ /*Scope*/ 14, /*->2038*/
+/* 2024*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 2026*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 2029*/ OPC_EmitMergeInputChains1_0,
+/* 2030*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC164), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 53
+ // Dst: (LDC164:{ *:[f64] } addrRegImm:{ *:[iPTR] }:$a)
+/* 2038*/ /*Scope*/ 14, /*->2053*/
+/* 2039*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 2041*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 2044*/ OPC_EmitMergeInputChains1_0,
+/* 2045*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC1), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 53
+ // Dst: (LDC1:{ *:[f64] } addrRegImm:{ *:[iPTR] }:$a)
+/* 2053*/ /*Scope*/ 14, /*->2068*/
+/* 2054*/ OPC_CheckPatternPredicate, 3, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())
+/* 2056*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 2059*/ OPC_EmitMergeInputChains1_0,
+/* 2060*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 53
+ // Dst: (LDC1_MM:{ *:[f64] } addrRegImm:{ *:[i32] }:$a)
+/* 2068*/ 0, /*End of Scope*/
+/* 2069*/ /*SwitchType*/ 32, MVT::f32,// ->2103
+/* 2071*/ OPC_Scope, 14, /*->2087*/ // 2 children in Scope
+/* 2073*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 2075*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 2078*/ OPC_EmitMergeInputChains1_0,
+/* 2079*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWC1), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f32] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 53
+ // Dst: (LWC1:{ *:[f32] } addrRegImm:{ *:[iPTR] }:$a)
+/* 2087*/ /*Scope*/ 14, /*->2102*/
+/* 2088*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 2090*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // selectAddrRegImm:$a #2 #3
+/* 2093*/ OPC_EmitMergeInputChains1_0,
+/* 2094*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f32] } addrRegImm:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 53
+ // Dst: (LWC1_MM:{ *:[f32] } addrRegImm:{ *:[i32] }:$a)
+/* 2102*/ 0, /*End of Scope*/
+/* 2103*/ 0, // EndSwitchType
+/* 2104*/ 0, /*End of Scope*/
+/* 2105*/ /*Scope*/ 69, /*->2175*/
+/* 2106*/ OPC_MoveChild1,
+/* 2107*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+/* 2110*/ OPC_RecordChild0, // #1 = $base
+/* 2111*/ OPC_RecordChild1, // #2 = $index
+/* 2112*/ OPC_MoveParent,
+/* 2113*/ OPC_CheckPredicate, 6, // Predicate_unindexedload
+/* 2115*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 2117*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->2146
+/* 2120*/ OPC_Scope, 11, /*->2133*/ // 2 children in Scope
+/* 2122*/ OPC_CheckPatternPredicate, 8, // (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isTargetNaCl()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 2124*/ OPC_EmitMergeInputChains1_0,
+/* 2125*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWXC1), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f32] } (add:{ *:[iPTR] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 27
+ // Dst: (LWXC1:{ *:[f32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index)
+/* 2133*/ /*Scope*/ 11, /*->2145*/
+/* 2134*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 2136*/ OPC_EmitMergeInputChains1_0,
+/* 2137*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWXC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f32] } (add:{ *:[iPTR] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 27
+ // Dst: (LWXC1_MM:{ *:[f32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index)
+/* 2145*/ 0, /*End of Scope*/
+/* 2146*/ /*SwitchType*/ 26, MVT::f64,// ->2174
+/* 2148*/ OPC_Scope, 11, /*->2161*/ // 2 children in Scope
+/* 2150*/ OPC_CheckPatternPredicate, 4, // (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isTargetNaCl()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 2152*/ OPC_EmitMergeInputChains1_0,
+/* 2153*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDXC1), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f64] } (add:{ *:[iPTR] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 27
+ // Dst: (LDXC1:{ *:[f64] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index)
+/* 2161*/ /*Scope*/ 11, /*->2173*/
+/* 2162*/ OPC_CheckPatternPredicate, 5, // (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 2164*/ OPC_EmitMergeInputChains1_0,
+/* 2165*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDXC164), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f64] } (add:{ *:[iPTR] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 27
+ // Dst: (LDXC164:{ *:[f64] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[iPTR] }:$index)
+/* 2173*/ 0, /*End of Scope*/
+/* 2174*/ 0, // EndSwitchType
+/* 2175*/ /*Scope*/ 31|128,2/*287*/, /*->2464*/
+/* 2177*/ OPC_RecordChild1, // #1 = $addr
+/* 2178*/ OPC_CheckPredicate, 6, // Predicate_unindexedload
+/* 2180*/ OPC_CheckPredicate, 11, // Predicate_load
+/* 2182*/ OPC_SwitchType /*12 cases */, 32, MVT::f32,// ->2217
+/* 2185*/ OPC_Scope, 14, /*->2201*/ // 2 children in Scope
+/* 2187*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 2189*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 2192*/ OPC_EmitMergeInputChains1_0,
+/* 2193*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWC1), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LWC1:{ *:[f32] } addrDefault:{ *:[iPTR] }:$addr)
+/* 2201*/ /*Scope*/ 14, /*->2216*/
+/* 2202*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 2204*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 2207*/ OPC_EmitMergeInputChains1_0,
+/* 2208*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f32] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LWC1_MM:{ *:[f32] } addrDefault:{ *:[i32] }:$addr)
+/* 2216*/ 0, /*End of Scope*/
+/* 2217*/ /*SwitchType*/ 62, MVT::f64,// ->2281
+/* 2219*/ OPC_Scope, 14, /*->2235*/ // 4 children in Scope
+/* 2221*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 2223*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 2226*/ OPC_EmitMergeInputChains1_0,
+/* 2227*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC164), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LDC164:{ *:[f64] } addrDefault:{ *:[iPTR] }:$addr)
+/* 2235*/ /*Scope*/ 14, /*->2250*/
+/* 2236*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 2238*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 2241*/ OPC_EmitMergeInputChains1_0,
+/* 2242*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC1), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LDC1:{ *:[f64] } addrDefault:{ *:[iPTR] }:$addr)
+/* 2250*/ /*Scope*/ 14, /*->2265*/
+/* 2251*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 2253*/ OPC_CheckComplexPat, /*CP*/2, /*#*/1, // selectAddrDefault:$addr #2 #3
+/* 2256*/ OPC_EmitMergeInputChains1_0,
+/* 2257*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC1_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } addrDefault:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LDC1_MM:{ *:[f64] } addrDefault:{ *:[i32] }:$addr)
+/* 2265*/ /*Scope*/ 14, /*->2280*/
+/* 2266*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 2268*/ OPC_CheckComplexPat, /*CP*/7, /*#*/1, // selectIntAddr16MM:$addr #2 #3
+/* 2271*/ OPC_EmitMergeInputChains1_0,
+/* 2272*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDC1_D64_MMR6), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } addrimm16:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LDC1_D64_MMR6:{ *:[f64] } addrimm16:{ *:[i32] }:$addr)
+/* 2280*/ 0, /*End of Scope*/
+/* 2281*/ /*SwitchType*/ 14, MVT::f16,// ->2297
+/* 2283*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 2285*/ OPC_CheckComplexPat, /*CP*/8, /*#*/1, // selectIntAddrSImm10:$addr #2 #3
+/* 2288*/ OPC_EmitMergeInputChains1_0,
+/* 2289*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_F16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f16, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f16] } addrimm10:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD_F16:{ *:[f16] } addrimm10:{ *:[iPTR] }:$addr)
+/* 2297*/ /*SwitchType*/ 14, MVT::v16i8,// ->2313
+/* 2299*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 2301*/ OPC_CheckComplexPat, /*CP*/8, /*#*/1, // selectIntAddrSImm10:$addr #2 #3
+/* 2304*/ OPC_EmitMergeInputChains1_0,
+/* 2305*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_B), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::v16i8, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[v16i8] } addrimm10:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD_B:{ *:[v16i8] } addrimm10:{ *:[iPTR] }:$addr)
+/* 2313*/ /*SwitchType*/ 14, MVT::v8i16,// ->2329
+/* 2315*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 2317*/ OPC_CheckComplexPat, /*CP*/9, /*#*/1, // selectIntAddrSImm10Lsl1:$addr #2 #3
+/* 2320*/ OPC_EmitMergeInputChains1_0,
+/* 2321*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::v8i16, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[v8i16] } addrimm10lsl1:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD_H:{ *:[v8i16] } addrimm10lsl1:{ *:[iPTR] }:$addr)
+/* 2329*/ /*SwitchType*/ 14, MVT::v4i32,// ->2345
+/* 2331*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 2333*/ OPC_CheckComplexPat, /*CP*/10, /*#*/1, // selectIntAddrSImm10Lsl2:$addr #2 #3
+/* 2336*/ OPC_EmitMergeInputChains1_0,
+/* 2337*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::v4i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[v4i32] } addrimm10lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD_W:{ *:[v4i32] } addrimm10lsl2:{ *:[iPTR] }:$addr)
+/* 2345*/ /*SwitchType*/ 14, MVT::v2i64,// ->2361
+/* 2347*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 2349*/ OPC_CheckComplexPat, /*CP*/11, /*#*/1, // selectIntAddrSImm10Lsl3:$addr #2 #3
+/* 2352*/ OPC_EmitMergeInputChains1_0,
+/* 2353*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::v2i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[v2i64] } addrimm10lsl3:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD_D:{ *:[v2i64] } addrimm10lsl3:{ *:[iPTR] }:$addr)
+/* 2361*/ /*SwitchType*/ 25, MVT::v2i16,// ->2388
+/* 2363*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 2365*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 2368*/ OPC_EmitMergeInputChains1_0,
+/* 2369*/ OPC_EmitNode1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 2377*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 2380*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 4, 5,
+ // Src: (ld:{ *:[v2i16] } addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i16] } (LW:{ *:[i32] } addr:{ *:[iPTR] }:$a), DSPR:{ *:[i32] })
+/* 2388*/ /*SwitchType*/ 25, MVT::v4i8,// ->2415
+/* 2390*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 2392*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 2395*/ OPC_EmitMergeInputChains1_0,
+/* 2396*/ OPC_EmitNode1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 2404*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 2407*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 4, 5,
+ // Src: (ld:{ *:[v4i8] } addr:{ *:[iPTR] }:$a)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i8] } (LW:{ *:[i32] } addr:{ *:[iPTR] }:$a), DSPR:{ *:[i32] })
+/* 2415*/ /*SwitchType*/ 14, MVT::v8f16,// ->2431
+/* 2417*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 2419*/ OPC_CheckComplexPat, /*CP*/9, /*#*/1, // selectIntAddrSImm10Lsl1:$addr #2 #3
+/* 2422*/ OPC_EmitMergeInputChains1_0,
+/* 2423*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_H), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::v8f16, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[v8f16] } addrimm10lsl1:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD_H:{ *:[v8f16] } addrimm10lsl1:{ *:[iPTR] }:$addr)
+/* 2431*/ /*SwitchType*/ 14, MVT::v4f32,// ->2447
+/* 2433*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 2435*/ OPC_CheckComplexPat, /*CP*/10, /*#*/1, // selectIntAddrSImm10Lsl2:$addr #2 #3
+/* 2438*/ OPC_EmitMergeInputChains1_0,
+/* 2439*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::v4f32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[v4f32] } addrimm10lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD_W:{ *:[v4f32] } addrimm10lsl2:{ *:[iPTR] }:$addr)
+/* 2447*/ /*SwitchType*/ 14, MVT::v2f64,// ->2463
+/* 2449*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 2451*/ OPC_CheckComplexPat, /*CP*/11, /*#*/1, // selectIntAddrSImm10Lsl3:$addr #2 #3
+/* 2454*/ OPC_EmitMergeInputChains1_0,
+/* 2455*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::v2f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[v2f64] } addrimm10lsl3:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 13
+ // Dst: (LD_D:{ *:[v2f64] } addrimm10lsl3:{ *:[iPTR] }:$addr)
+/* 2463*/ 0, // EndSwitchType
+/* 2464*/ 0, /*End of Scope*/
+/* 2465*/ /*SwitchOpcode*/ 104|128,23/*3048*/, TARGET_VAL(ISD::BRCOND),// ->5517
+/* 2469*/ OPC_RecordNode, // #0 = 'brcond' chained node
+/* 2470*/ OPC_Scope, 8|128,23/*2952*/, /*->5425*/ // 2 children in Scope
+/* 2473*/ OPC_MoveChild1,
+/* 2474*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
+/* 2477*/ OPC_Scope, 85|128,4/*597*/, /*->3077*/ // 2 children in Scope
+/* 2480*/ OPC_MoveChild0,
+/* 2481*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 2484*/ OPC_Scope, 31|128,1/*159*/, /*->2646*/ // 3 children in Scope
+/* 2487*/ OPC_RecordChild0, // #1 = $rs
+/* 2488*/ OPC_MoveChild1,
+/* 2489*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 2492*/ OPC_Scope, 73, /*->2567*/ // 2 children in Scope
+/* 2494*/ OPC_CheckChild0Integer, 1,
+/* 2496*/ OPC_RecordChild1, // #2 = $p
+/* 2497*/ OPC_MoveChild1,
+/* 2498*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 2501*/ OPC_CheckPredicate, 15, // Predicate_immZExt5_64
+/* 2503*/ OPC_CheckType, MVT::i64,
+/* 2505*/ OPC_MoveParent,
+/* 2506*/ OPC_MoveParent,
+/* 2507*/ OPC_CheckType, MVT::i64,
+/* 2509*/ OPC_MoveParent,
+/* 2510*/ OPC_CheckChild1Integer, 0,
+/* 2512*/ OPC_MoveChild2,
+/* 2513*/ OPC_Scope, 25, /*->2540*/ // 2 children in Scope
+/* 2515*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 2517*/ OPC_MoveParent,
+/* 2518*/ OPC_CheckType, MVT::i32,
+/* 2520*/ OPC_MoveParent,
+/* 2521*/ OPC_RecordChild2, // #3 = $offset
+/* 2522*/ OPC_MoveChild2,
+/* 2523*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2526*/ OPC_MoveParent,
+/* 2527*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 2529*/ OPC_EmitMergeInputChains1_0,
+/* 2530*/ OPC_EmitConvertToTarget, 2,
+/* 2532*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT0), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 26
+ // Dst: (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
+/* 2540*/ /*Scope*/ 25, /*->2566*/
+/* 2541*/ OPC_CheckCondCode, ISD::SETNE,
+/* 2543*/ OPC_MoveParent,
+/* 2544*/ OPC_CheckType, MVT::i32,
+/* 2546*/ OPC_MoveParent,
+/* 2547*/ OPC_RecordChild2, // #3 = $offset
+/* 2548*/ OPC_MoveChild2,
+/* 2549*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2552*/ OPC_MoveParent,
+/* 2553*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 2555*/ OPC_EmitMergeInputChains1_0,
+/* 2556*/ OPC_EmitConvertToTarget, 2,
+/* 2558*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT1), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 26
+ // Dst: (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
+/* 2566*/ 0, /*End of Scope*/
+/* 2567*/ /*Scope*/ 77, /*->2645*/
+/* 2568*/ OPC_CheckChild0Integer, 0|128,0|128,0|128,0|128,16/*4294967296*/,
+/* 2574*/ OPC_RecordChild1, // #2 = $p
+/* 2575*/ OPC_MoveChild1,
+/* 2576*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 2579*/ OPC_CheckPredicate, 15, // Predicate_immZExt5_64
+/* 2581*/ OPC_CheckType, MVT::i64,
+/* 2583*/ OPC_MoveParent,
+/* 2584*/ OPC_MoveParent,
+/* 2585*/ OPC_CheckType, MVT::i64,
+/* 2587*/ OPC_MoveParent,
+/* 2588*/ OPC_CheckChild1Integer, 0,
+/* 2590*/ OPC_MoveChild2,
+/* 2591*/ OPC_Scope, 25, /*->2618*/ // 2 children in Scope
+/* 2593*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 2595*/ OPC_MoveParent,
+/* 2596*/ OPC_CheckType, MVT::i32,
+/* 2598*/ OPC_MoveParent,
+/* 2599*/ OPC_RecordChild2, // #3 = $offset
+/* 2600*/ OPC_MoveChild2,
+/* 2601*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2604*/ OPC_MoveParent,
+/* 2605*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 2607*/ OPC_EmitMergeInputChains1_0,
+/* 2608*/ OPC_EmitConvertToTarget, 2,
+/* 2610*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT032), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 26
+ // Dst: (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
+/* 2618*/ /*Scope*/ 25, /*->2644*/
+/* 2619*/ OPC_CheckCondCode, ISD::SETNE,
+/* 2621*/ OPC_MoveParent,
+/* 2622*/ OPC_CheckType, MVT::i32,
+/* 2624*/ OPC_MoveParent,
+/* 2625*/ OPC_RecordChild2, // #3 = $offset
+/* 2626*/ OPC_MoveChild2,
+/* 2627*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2630*/ OPC_MoveParent,
+/* 2631*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 2633*/ OPC_EmitMergeInputChains1_0,
+/* 2634*/ OPC_EmitConvertToTarget, 2,
+/* 2636*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT132), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 26
+ // Dst: (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
+/* 2644*/ 0, /*End of Scope*/
+/* 2645*/ 0, /*End of Scope*/
+/* 2646*/ /*Scope*/ 32|128,1/*160*/, /*->2808*/
+/* 2648*/ OPC_MoveChild0,
+/* 2649*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 2652*/ OPC_Scope, 74, /*->2728*/ // 2 children in Scope
+/* 2654*/ OPC_CheckChild0Integer, 1,
+/* 2656*/ OPC_RecordChild1, // #1 = $p
+/* 2657*/ OPC_MoveChild1,
+/* 2658*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 2661*/ OPC_CheckPredicate, 15, // Predicate_immZExt5_64
+/* 2663*/ OPC_CheckType, MVT::i64,
+/* 2665*/ OPC_MoveParent,
+/* 2666*/ OPC_MoveParent,
+/* 2667*/ OPC_RecordChild1, // #2 = $rs
+/* 2668*/ OPC_CheckType, MVT::i64,
+/* 2670*/ OPC_MoveParent,
+/* 2671*/ OPC_CheckChild1Integer, 0,
+/* 2673*/ OPC_MoveChild2,
+/* 2674*/ OPC_Scope, 25, /*->2701*/ // 2 children in Scope
+/* 2676*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 2678*/ OPC_MoveParent,
+/* 2679*/ OPC_CheckType, MVT::i32,
+/* 2681*/ OPC_MoveParent,
+/* 2682*/ OPC_RecordChild2, // #3 = $offset
+/* 2683*/ OPC_MoveChild2,
+/* 2684*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2687*/ OPC_MoveParent,
+/* 2688*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 2690*/ OPC_EmitMergeInputChains1_0,
+/* 2691*/ OPC_EmitConvertToTarget, 1,
+/* 2693*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT0), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 26
+ // Dst: (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
+/* 2701*/ /*Scope*/ 25, /*->2727*/
+/* 2702*/ OPC_CheckCondCode, ISD::SETNE,
+/* 2704*/ OPC_MoveParent,
+/* 2705*/ OPC_CheckType, MVT::i32,
+/* 2707*/ OPC_MoveParent,
+/* 2708*/ OPC_RecordChild2, // #3 = $offset
+/* 2709*/ OPC_MoveChild2,
+/* 2710*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2713*/ OPC_MoveParent,
+/* 2714*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 2716*/ OPC_EmitMergeInputChains1_0,
+/* 2717*/ OPC_EmitConvertToTarget, 1,
+/* 2719*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT1), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 26
+ // Dst: (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
+/* 2727*/ 0, /*End of Scope*/
+/* 2728*/ /*Scope*/ 78, /*->2807*/
+/* 2729*/ OPC_CheckChild0Integer, 0|128,0|128,0|128,0|128,16/*4294967296*/,
+/* 2735*/ OPC_RecordChild1, // #1 = $p
+/* 2736*/ OPC_MoveChild1,
+/* 2737*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 2740*/ OPC_CheckPredicate, 15, // Predicate_immZExt5_64
+/* 2742*/ OPC_CheckType, MVT::i64,
+/* 2744*/ OPC_MoveParent,
+/* 2745*/ OPC_MoveParent,
+/* 2746*/ OPC_RecordChild1, // #2 = $rs
+/* 2747*/ OPC_CheckType, MVT::i64,
+/* 2749*/ OPC_MoveParent,
+/* 2750*/ OPC_CheckChild1Integer, 0,
+/* 2752*/ OPC_MoveChild2,
+/* 2753*/ OPC_Scope, 25, /*->2780*/ // 2 children in Scope
+/* 2755*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 2757*/ OPC_MoveParent,
+/* 2758*/ OPC_CheckType, MVT::i32,
+/* 2760*/ OPC_MoveParent,
+/* 2761*/ OPC_RecordChild2, // #3 = $offset
+/* 2762*/ OPC_MoveChild2,
+/* 2763*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2766*/ OPC_MoveParent,
+/* 2767*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 2769*/ OPC_EmitMergeInputChains1_0,
+/* 2770*/ OPC_EmitConvertToTarget, 1,
+/* 2772*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT032), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 26
+ // Dst: (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
+/* 2780*/ /*Scope*/ 25, /*->2806*/
+/* 2781*/ OPC_CheckCondCode, ISD::SETNE,
+/* 2783*/ OPC_MoveParent,
+/* 2784*/ OPC_CheckType, MVT::i32,
+/* 2786*/ OPC_MoveParent,
+/* 2787*/ OPC_RecordChild2, // #3 = $offset
+/* 2788*/ OPC_MoveChild2,
+/* 2789*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2792*/ OPC_MoveParent,
+/* 2793*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 2795*/ OPC_EmitMergeInputChains1_0,
+/* 2796*/ OPC_EmitConvertToTarget, 1,
+/* 2798*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT132), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 26
+ // Dst: (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
+/* 2806*/ 0, /*End of Scope*/
+/* 2807*/ 0, /*End of Scope*/
+/* 2808*/ /*Scope*/ 10|128,2/*266*/, /*->3076*/
+/* 2810*/ OPC_RecordChild0, // #1 = $lhs
+/* 2811*/ OPC_RecordChild1, // #2 = $mask
+/* 2812*/ OPC_MoveChild1,
+/* 2813*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 2816*/ OPC_Scope, 37, /*->2855*/ // 5 children in Scope
+/* 2818*/ OPC_CheckPredicate, 16, // Predicate_PowerOf2LO
+/* 2820*/ OPC_MoveParent,
+/* 2821*/ OPC_CheckType, MVT::i64,
+/* 2823*/ OPC_MoveParent,
+/* 2824*/ OPC_CheckChild1Integer, 0,
+/* 2826*/ OPC_MoveChild2,
+/* 2827*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 2829*/ OPC_MoveParent,
+/* 2830*/ OPC_CheckType, MVT::i32,
+/* 2832*/ OPC_MoveParent,
+/* 2833*/ OPC_RecordChild2, // #3 = $dst
+/* 2834*/ OPC_MoveChild2,
+/* 2835*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2838*/ OPC_MoveParent,
+/* 2839*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding())
+/* 2841*/ OPC_EmitMergeInputChains1_0,
+/* 2842*/ OPC_EmitConvertToTarget, 2,
+/* 2844*/ OPC_EmitNodeXForm, 0, 4, // Log2LO
+/* 2847*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT0), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } i64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_PowerOf2LO>>:$mask), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 18
+ // Dst: (BBIT0 i64:{ *:[i64] }:$lhs, (Log2LO:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_PowerOf2LO>>:$mask), (bb:{ *:[Other] }):$dst)
+/* 2855*/ /*Scope*/ 37, /*->2893*/
+/* 2856*/ OPC_CheckPredicate, 17, // Predicate_PowerOf2HI
+/* 2858*/ OPC_MoveParent,
+/* 2859*/ OPC_CheckType, MVT::i64,
+/* 2861*/ OPC_MoveParent,
+/* 2862*/ OPC_CheckChild1Integer, 0,
+/* 2864*/ OPC_MoveChild2,
+/* 2865*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 2867*/ OPC_MoveParent,
+/* 2868*/ OPC_CheckType, MVT::i32,
+/* 2870*/ OPC_MoveParent,
+/* 2871*/ OPC_RecordChild2, // #3 = $dst
+/* 2872*/ OPC_MoveChild2,
+/* 2873*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2876*/ OPC_MoveParent,
+/* 2877*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding())
+/* 2879*/ OPC_EmitMergeInputChains1_0,
+/* 2880*/ OPC_EmitConvertToTarget, 2,
+/* 2882*/ OPC_EmitNodeXForm, 1, 4, // Log2HI
+/* 2885*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT032), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } i64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_PowerOf2HI>>:$mask), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 18
+ // Dst: (BBIT032 i64:{ *:[i64] }:$lhs, (Log2HI:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_PowerOf2HI>>:$mask), (bb:{ *:[Other] }):$dst)
+/* 2893*/ /*Scope*/ 37, /*->2931*/
+/* 2894*/ OPC_CheckPredicate, 16, // Predicate_PowerOf2LO
+/* 2896*/ OPC_MoveParent,
+/* 2897*/ OPC_CheckType, MVT::i64,
+/* 2899*/ OPC_MoveParent,
+/* 2900*/ OPC_CheckChild1Integer, 0,
+/* 2902*/ OPC_MoveChild2,
+/* 2903*/ OPC_CheckCondCode, ISD::SETNE,
+/* 2905*/ OPC_MoveParent,
+/* 2906*/ OPC_CheckType, MVT::i32,
+/* 2908*/ OPC_MoveParent,
+/* 2909*/ OPC_RecordChild2, // #3 = $dst
+/* 2910*/ OPC_MoveChild2,
+/* 2911*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2914*/ OPC_MoveParent,
+/* 2915*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding())
+/* 2917*/ OPC_EmitMergeInputChains1_0,
+/* 2918*/ OPC_EmitConvertToTarget, 2,
+/* 2920*/ OPC_EmitNodeXForm, 0, 4, // Log2LO
+/* 2923*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT1), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } i64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_PowerOf2LO>>:$mask), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 18
+ // Dst: (BBIT1 i64:{ *:[i64] }:$lhs, (Log2LO:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_PowerOf2LO>>:$mask), (bb:{ *:[Other] }):$dst)
+/* 2931*/ /*Scope*/ 37, /*->2969*/
+/* 2932*/ OPC_CheckPredicate, 17, // Predicate_PowerOf2HI
+/* 2934*/ OPC_MoveParent,
+/* 2935*/ OPC_CheckType, MVT::i64,
+/* 2937*/ OPC_MoveParent,
+/* 2938*/ OPC_CheckChild1Integer, 0,
+/* 2940*/ OPC_MoveChild2,
+/* 2941*/ OPC_CheckCondCode, ISD::SETNE,
+/* 2943*/ OPC_MoveParent,
+/* 2944*/ OPC_CheckType, MVT::i32,
+/* 2946*/ OPC_MoveParent,
+/* 2947*/ OPC_RecordChild2, // #3 = $dst
+/* 2948*/ OPC_MoveChild2,
+/* 2949*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2952*/ OPC_MoveParent,
+/* 2953*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding())
+/* 2955*/ OPC_EmitMergeInputChains1_0,
+/* 2956*/ OPC_EmitConvertToTarget, 2,
+/* 2958*/ OPC_EmitNodeXForm, 1, 4, // Log2HI
+/* 2961*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT132), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } i64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_PowerOf2HI>>:$mask), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 18
+ // Dst: (BBIT132 i64:{ *:[i64] }:$lhs, (Log2HI:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_PowerOf2HI>>:$mask), (bb:{ *:[Other] }):$dst)
+/* 2969*/ /*Scope*/ 105, /*->3075*/
+/* 2970*/ OPC_CheckPredicate, 18, // Predicate_PowerOf2LO_i32
+/* 2972*/ OPC_MoveParent,
+/* 2973*/ OPC_CheckType, MVT::i32,
+/* 2975*/ OPC_MoveParent,
+/* 2976*/ OPC_CheckChild1Integer, 0,
+/* 2978*/ OPC_MoveChild2,
+/* 2979*/ OPC_Scope, 46, /*->3027*/ // 2 children in Scope
+/* 2981*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 2983*/ OPC_MoveParent,
+/* 2984*/ OPC_CheckType, MVT::i32,
+/* 2986*/ OPC_MoveParent,
+/* 2987*/ OPC_RecordChild2, // #3 = $dst
+/* 2988*/ OPC_MoveChild2,
+/* 2989*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 2992*/ OPC_MoveParent,
+/* 2993*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding())
+/* 2995*/ OPC_EmitMergeInputChains1_0,
+/* 2996*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #4
+/* 3002*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 3005*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 4, 1, 5, // Results = #6
+/* 3014*/ OPC_EmitConvertToTarget, 2,
+/* 3016*/ OPC_EmitNodeXForm, 0, 7, // Log2LO
+/* 3019*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT0), 0|OPFL_Chain,
+ 3/*#Ops*/, 6, 8, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_PowerOf2LO_i32>>:$mask), 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 18
+ // Dst: (BBIT0 (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), i32:{ *:[i32] }:$lhs, sub_32:{ *:[i32] }), (Log2LO:{ *:[i64] } (imm:{ *:[i32] })<<P:Predicate_PowerOf2LO_i32>>:$mask), (bb:{ *:[Other] }):$dst)
+/* 3027*/ /*Scope*/ 46, /*->3074*/
+/* 3028*/ OPC_CheckCondCode, ISD::SETNE,
+/* 3030*/ OPC_MoveParent,
+/* 3031*/ OPC_CheckType, MVT::i32,
+/* 3033*/ OPC_MoveParent,
+/* 3034*/ OPC_RecordChild2, // #3 = $dst
+/* 3035*/ OPC_MoveChild2,
+/* 3036*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3039*/ OPC_MoveParent,
+/* 3040*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding())
+/* 3042*/ OPC_EmitMergeInputChains1_0,
+/* 3043*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #4
+/* 3049*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 3052*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 4, 1, 5, // Results = #6
+/* 3061*/ OPC_EmitConvertToTarget, 2,
+/* 3063*/ OPC_EmitNodeXForm, 0, 7, // Log2LO
+/* 3066*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BBIT1), 0|OPFL_Chain,
+ 3/*#Ops*/, 6, 8, 3,
+ // Src: (brcond (setcc:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_PowerOf2LO_i32>>:$mask), 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 18
+ // Dst: (BBIT1 (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), i32:{ *:[i32] }:$lhs, sub_32:{ *:[i32] }), (Log2LO:{ *:[i64] } (imm:{ *:[i32] })<<P:Predicate_PowerOf2LO_i32>>:$mask), (bb:{ *:[Other] }):$dst)
+/* 3074*/ 0, /*End of Scope*/
+/* 3075*/ 0, /*End of Scope*/
+/* 3076*/ 0, /*End of Scope*/
+/* 3077*/ /*Scope*/ 41|128,18/*2345*/, /*->5424*/
+/* 3079*/ OPC_RecordChild0, // #1 = $rs
+/* 3080*/ OPC_Scope, 80|128,13/*1744*/, /*->4827*/ // 2 children in Scope
+/* 3083*/ OPC_CheckChild0Type, MVT::i32,
+/* 3085*/ OPC_Scope, 124|128,2/*380*/, /*->3468*/ // 4 children in Scope
+/* 3088*/ OPC_CheckChild1Integer, 0,
+/* 3090*/ OPC_MoveChild2,
+/* 3091*/ OPC_Scope, 22, /*->3115*/ // 15 children in Scope
+/* 3093*/ OPC_CheckCondCode, ISD::SETGE,
+/* 3095*/ OPC_MoveParent,
+/* 3096*/ OPC_CheckType, MVT::i32,
+/* 3098*/ OPC_MoveParent,
+/* 3099*/ OPC_RecordChild2, // #2 = $offset
+/* 3100*/ OPC_MoveChild2,
+/* 3101*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3104*/ OPC_MoveParent,
+/* 3105*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3107*/ OPC_EmitMergeInputChains1_0,
+/* 3108*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGEZ), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 3115*/ /*Scope*/ 22, /*->3138*/
+/* 3116*/ OPC_CheckCondCode, ISD::SETGT,
+/* 3118*/ OPC_MoveParent,
+/* 3119*/ OPC_CheckType, MVT::i32,
+/* 3121*/ OPC_MoveParent,
+/* 3122*/ OPC_RecordChild2, // #2 = $offset
+/* 3123*/ OPC_MoveChild2,
+/* 3124*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3127*/ OPC_MoveParent,
+/* 3128*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3130*/ OPC_EmitMergeInputChains1_0,
+/* 3131*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGTZ), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 3138*/ /*Scope*/ 22, /*->3161*/
+/* 3139*/ OPC_CheckCondCode, ISD::SETLE,
+/* 3141*/ OPC_MoveParent,
+/* 3142*/ OPC_CheckType, MVT::i32,
+/* 3144*/ OPC_MoveParent,
+/* 3145*/ OPC_RecordChild2, // #2 = $offset
+/* 3146*/ OPC_MoveChild2,
+/* 3147*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3150*/ OPC_MoveParent,
+/* 3151*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3153*/ OPC_EmitMergeInputChains1_0,
+/* 3154*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLEZ), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 3161*/ /*Scope*/ 22, /*->3184*/
+/* 3162*/ OPC_CheckCondCode, ISD::SETLT,
+/* 3164*/ OPC_MoveParent,
+/* 3165*/ OPC_CheckType, MVT::i32,
+/* 3167*/ OPC_MoveParent,
+/* 3168*/ OPC_RecordChild2, // #2 = $offset
+/* 3169*/ OPC_MoveChild2,
+/* 3170*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3173*/ OPC_MoveParent,
+/* 3174*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3176*/ OPC_EmitMergeInputChains1_0,
+/* 3177*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLTZ), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 3184*/ /*Scope*/ 26, /*->3211*/
+/* 3185*/ OPC_CheckCondCode, ISD::SETNE,
+/* 3187*/ OPC_MoveParent,
+/* 3188*/ OPC_CheckType, MVT::i32,
+/* 3190*/ OPC_MoveParent,
+/* 3191*/ OPC_RecordChild2, // #2 = $dst
+/* 3192*/ OPC_MoveChild2,
+/* 3193*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3196*/ OPC_MoveParent,
+/* 3197*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3199*/ OPC_EmitMergeInputChains1_0,
+/* 3200*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3203*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BNE GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3211*/ /*Scope*/ 40, /*->3252*/
+/* 3212*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 3214*/ OPC_MoveParent,
+/* 3215*/ OPC_CheckType, MVT::i32,
+/* 3217*/ OPC_MoveParent,
+/* 3218*/ OPC_RecordChild2, // #2 = $dst
+/* 3219*/ OPC_MoveChild2,
+/* 3220*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3223*/ OPC_MoveParent,
+/* 3224*/ OPC_Scope, 14, /*->3240*/ // 2 children in Scope
+/* 3226*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3228*/ OPC_EmitMergeInputChains1_0,
+/* 3229*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3232*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BEQ GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3240*/ /*Scope*/ 10, /*->3251*/
+/* 3241*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 3243*/ OPC_EmitMergeInputChains1_0,
+/* 3244*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BeqzRxImm16), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) - Complexity = 11
+ // Dst: (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
+/* 3251*/ 0, /*End of Scope*/
+/* 3252*/ /*Scope*/ 22, /*->3275*/
+/* 3253*/ OPC_CheckCondCode, ISD::SETNE,
+/* 3255*/ OPC_MoveParent,
+/* 3256*/ OPC_CheckType, MVT::i32,
+/* 3258*/ OPC_MoveParent,
+/* 3259*/ OPC_RecordChild2, // #2 = $targ16
+/* 3260*/ OPC_MoveChild2,
+/* 3261*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3264*/ OPC_MoveParent,
+/* 3265*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 3267*/ OPC_EmitMergeInputChains1_0,
+/* 3268*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BnezRxImm16), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) - Complexity = 11
+ // Dst: (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
+/* 3275*/ /*Scope*/ 22, /*->3298*/
+/* 3276*/ OPC_CheckCondCode, ISD::SETGE,
+/* 3278*/ OPC_MoveParent,
+/* 3279*/ OPC_CheckType, MVT::i32,
+/* 3281*/ OPC_MoveParent,
+/* 3282*/ OPC_RecordChild2, // #2 = $offset
+/* 3283*/ OPC_MoveChild2,
+/* 3284*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3287*/ OPC_MoveParent,
+/* 3288*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3290*/ OPC_EmitMergeInputChains1_0,
+/* 3291*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGEZ_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 3298*/ /*Scope*/ 22, /*->3321*/
+/* 3299*/ OPC_CheckCondCode, ISD::SETGT,
+/* 3301*/ OPC_MoveParent,
+/* 3302*/ OPC_CheckType, MVT::i32,
+/* 3304*/ OPC_MoveParent,
+/* 3305*/ OPC_RecordChild2, // #2 = $offset
+/* 3306*/ OPC_MoveChild2,
+/* 3307*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3310*/ OPC_MoveParent,
+/* 3311*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3313*/ OPC_EmitMergeInputChains1_0,
+/* 3314*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGTZ_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 3321*/ /*Scope*/ 22, /*->3344*/
+/* 3322*/ OPC_CheckCondCode, ISD::SETLE,
+/* 3324*/ OPC_MoveParent,
+/* 3325*/ OPC_CheckType, MVT::i32,
+/* 3327*/ OPC_MoveParent,
+/* 3328*/ OPC_RecordChild2, // #2 = $offset
+/* 3329*/ OPC_MoveChild2,
+/* 3330*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3333*/ OPC_MoveParent,
+/* 3334*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3336*/ OPC_EmitMergeInputChains1_0,
+/* 3337*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLEZ_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 3344*/ /*Scope*/ 22, /*->3367*/
+/* 3345*/ OPC_CheckCondCode, ISD::SETLT,
+/* 3347*/ OPC_MoveParent,
+/* 3348*/ OPC_CheckType, MVT::i32,
+/* 3350*/ OPC_MoveParent,
+/* 3351*/ OPC_RecordChild2, // #2 = $offset
+/* 3352*/ OPC_MoveChild2,
+/* 3353*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3356*/ OPC_MoveParent,
+/* 3357*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3359*/ OPC_EmitMergeInputChains1_0,
+/* 3360*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLTZ_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 3367*/ /*Scope*/ 26, /*->3394*/
+/* 3368*/ OPC_CheckCondCode, ISD::SETNE,
+/* 3370*/ OPC_MoveParent,
+/* 3371*/ OPC_CheckType, MVT::i32,
+/* 3373*/ OPC_MoveParent,
+/* 3374*/ OPC_RecordChild2, // #2 = $dst
+/* 3375*/ OPC_MoveChild2,
+/* 3376*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3379*/ OPC_MoveParent,
+/* 3380*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3382*/ OPC_EmitMergeInputChains1_0,
+/* 3383*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3386*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BNE_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3394*/ /*Scope*/ 26, /*->3421*/
+/* 3395*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 3397*/ OPC_MoveParent,
+/* 3398*/ OPC_CheckType, MVT::i32,
+/* 3400*/ OPC_MoveParent,
+/* 3401*/ OPC_RecordChild2, // #2 = $dst
+/* 3402*/ OPC_MoveChild2,
+/* 3403*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3406*/ OPC_MoveParent,
+/* 3407*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3409*/ OPC_EmitMergeInputChains1_0,
+/* 3410*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3413*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BEQ_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3421*/ /*Scope*/ 22, /*->3444*/
+/* 3422*/ OPC_CheckCondCode, ISD::SETNE,
+/* 3424*/ OPC_MoveParent,
+/* 3425*/ OPC_CheckType, MVT::i32,
+/* 3427*/ OPC_MoveParent,
+/* 3428*/ OPC_RecordChild2, // #2 = $dst
+/* 3429*/ OPC_MoveChild2,
+/* 3430*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3433*/ OPC_MoveParent,
+/* 3434*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 3436*/ OPC_EmitMergeInputChains1_0,
+/* 3437*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNEZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
+/* 3444*/ /*Scope*/ 22, /*->3467*/
+/* 3445*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 3447*/ OPC_MoveParent,
+/* 3448*/ OPC_CheckType, MVT::i32,
+/* 3450*/ OPC_MoveParent,
+/* 3451*/ OPC_RecordChild2, // #2 = $dst
+/* 3452*/ OPC_MoveChild2,
+/* 3453*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3456*/ OPC_MoveParent,
+/* 3457*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 3459*/ OPC_EmitMergeInputChains1_0,
+/* 3460*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
+/* 3467*/ 0, /*End of Scope*/
+/* 3468*/ /*Scope*/ 39, /*->3508*/
+/* 3469*/ OPC_CheckChild1Integer, 1,
+/* 3471*/ OPC_MoveChild2,
+/* 3472*/ OPC_CheckCondCode, ISD::SETLT,
+/* 3474*/ OPC_MoveParent,
+/* 3475*/ OPC_CheckType, MVT::i32,
+/* 3477*/ OPC_MoveParent,
+/* 3478*/ OPC_RecordChild2, // #2 = $dst
+/* 3479*/ OPC_MoveChild2,
+/* 3480*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3483*/ OPC_MoveParent,
+/* 3484*/ OPC_Scope, 10, /*->3496*/ // 2 children in Scope
+/* 3486*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3488*/ OPC_EmitMergeInputChains1_0,
+/* 3489*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLEZ), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
+/* 3496*/ /*Scope*/ 10, /*->3507*/
+/* 3497*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3499*/ OPC_EmitMergeInputChains1_0,
+/* 3500*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLEZ_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
+/* 3507*/ 0, /*End of Scope*/
+/* 3508*/ /*Scope*/ 48, /*->3557*/
+/* 3509*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 3520*/ OPC_MoveChild2,
+/* 3521*/ OPC_CheckCondCode, ISD::SETGT,
+/* 3523*/ OPC_MoveParent,
+/* 3524*/ OPC_CheckType, MVT::i32,
+/* 3526*/ OPC_MoveParent,
+/* 3527*/ OPC_RecordChild2, // #2 = $dst
+/* 3528*/ OPC_MoveChild2,
+/* 3529*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3532*/ OPC_MoveParent,
+/* 3533*/ OPC_Scope, 10, /*->3545*/ // 2 children in Scope
+/* 3535*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3537*/ OPC_EmitMergeInputChains1_0,
+/* 3538*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGEZ), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
+/* 3545*/ /*Scope*/ 10, /*->3556*/
+/* 3546*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3548*/ OPC_EmitMergeInputChains1_0,
+/* 3549*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGEZ_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
+/* 3556*/ 0, /*End of Scope*/
+/* 3557*/ /*Scope*/ 115|128,9/*1267*/, /*->4826*/
+/* 3559*/ OPC_RecordChild1, // #2 = $rhs
+/* 3560*/ OPC_Scope, 101|128,4/*613*/, /*->4176*/ // 2 children in Scope
+/* 3563*/ OPC_MoveChild1,
+/* 3564*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 3567*/ OPC_Scope, 80, /*->3649*/ // 9 children in Scope
+/* 3569*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 3571*/ OPC_MoveParent,
+/* 3572*/ OPC_MoveChild2,
+/* 3573*/ OPC_Scope, 36, /*->3611*/ // 2 children in Scope
+/* 3575*/ OPC_CheckCondCode, ISD::SETGE,
+/* 3577*/ OPC_MoveParent,
+/* 3578*/ OPC_CheckType, MVT::i32,
+/* 3580*/ OPC_MoveParent,
+/* 3581*/ OPC_RecordChild2, // #3 = $dst
+/* 3582*/ OPC_MoveChild2,
+/* 3583*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3586*/ OPC_MoveParent,
+/* 3587*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3589*/ OPC_EmitMergeInputChains1_0,
+/* 3590*/ OPC_EmitConvertToTarget, 2,
+/* 3592*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 1, 4, // Results = #5
+/* 3600*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3603*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 5, 6, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3611*/ /*Scope*/ 36, /*->3648*/
+/* 3612*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 3614*/ OPC_MoveParent,
+/* 3615*/ OPC_CheckType, MVT::i32,
+/* 3617*/ OPC_MoveParent,
+/* 3618*/ OPC_RecordChild2, // #3 = $dst
+/* 3619*/ OPC_MoveChild2,
+/* 3620*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3623*/ OPC_MoveParent,
+/* 3624*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3626*/ OPC_EmitMergeInputChains1_0,
+/* 3627*/ OPC_EmitConvertToTarget, 2,
+/* 3629*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 4, // Results = #5
+/* 3637*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3640*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 5, 6, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3648*/ 0, /*End of Scope*/
+/* 3649*/ /*Scope*/ 86, /*->3736*/
+/* 3650*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 3652*/ OPC_MoveParent,
+/* 3653*/ OPC_MoveChild2,
+/* 3654*/ OPC_Scope, 39, /*->3695*/ // 2 children in Scope
+/* 3656*/ OPC_CheckCondCode, ISD::SETGT,
+/* 3658*/ OPC_MoveParent,
+/* 3659*/ OPC_CheckType, MVT::i32,
+/* 3661*/ OPC_MoveParent,
+/* 3662*/ OPC_RecordChild2, // #3 = $dst
+/* 3663*/ OPC_MoveChild2,
+/* 3664*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3667*/ OPC_MoveParent,
+/* 3668*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3670*/ OPC_EmitMergeInputChains1_0,
+/* 3671*/ OPC_EmitConvertToTarget, 2,
+/* 3673*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 3676*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 3684*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3687*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 6, 7, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3695*/ /*Scope*/ 39, /*->3735*/
+/* 3696*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 3698*/ OPC_MoveParent,
+/* 3699*/ OPC_CheckType, MVT::i32,
+/* 3701*/ OPC_MoveParent,
+/* 3702*/ OPC_RecordChild2, // #3 = $dst
+/* 3703*/ OPC_MoveChild2,
+/* 3704*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3707*/ OPC_MoveParent,
+/* 3708*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 3710*/ OPC_EmitMergeInputChains1_0,
+/* 3711*/ OPC_EmitConvertToTarget, 2,
+/* 3713*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 3716*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 3724*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3727*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 6, 7, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3735*/ 0, /*End of Scope*/
+/* 3736*/ /*Scope*/ 80, /*->3817*/
+/* 3737*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 3739*/ OPC_MoveParent,
+/* 3740*/ OPC_MoveChild2,
+/* 3741*/ OPC_Scope, 36, /*->3779*/ // 2 children in Scope
+/* 3743*/ OPC_CheckCondCode, ISD::SETGE,
+/* 3745*/ OPC_MoveParent,
+/* 3746*/ OPC_CheckType, MVT::i32,
+/* 3748*/ OPC_MoveParent,
+/* 3749*/ OPC_RecordChild2, // #3 = $dst
+/* 3750*/ OPC_MoveChild2,
+/* 3751*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3754*/ OPC_MoveParent,
+/* 3755*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3757*/ OPC_EmitMergeInputChains1_0,
+/* 3758*/ OPC_EmitConvertToTarget, 2,
+/* 3760*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 4, // Results = #5
+/* 3768*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3771*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 5, 6, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ_MM (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3779*/ /*Scope*/ 36, /*->3816*/
+/* 3780*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 3782*/ OPC_MoveParent,
+/* 3783*/ OPC_CheckType, MVT::i32,
+/* 3785*/ OPC_MoveParent,
+/* 3786*/ OPC_RecordChild2, // #3 = $dst
+/* 3787*/ OPC_MoveChild2,
+/* 3788*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3791*/ OPC_MoveParent,
+/* 3792*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3794*/ OPC_EmitMergeInputChains1_0,
+/* 3795*/ OPC_EmitConvertToTarget, 2,
+/* 3797*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 4, // Results = #5
+/* 3805*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3808*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 5, 6, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ_MM (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3816*/ 0, /*End of Scope*/
+/* 3817*/ /*Scope*/ 86, /*->3904*/
+/* 3818*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 3820*/ OPC_MoveParent,
+/* 3821*/ OPC_MoveChild2,
+/* 3822*/ OPC_Scope, 39, /*->3863*/ // 2 children in Scope
+/* 3824*/ OPC_CheckCondCode, ISD::SETGT,
+/* 3826*/ OPC_MoveParent,
+/* 3827*/ OPC_CheckType, MVT::i32,
+/* 3829*/ OPC_MoveParent,
+/* 3830*/ OPC_RecordChild2, // #3 = $dst
+/* 3831*/ OPC_MoveChild2,
+/* 3832*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3835*/ OPC_MoveParent,
+/* 3836*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3838*/ OPC_EmitMergeInputChains1_0,
+/* 3839*/ OPC_EmitConvertToTarget, 2,
+/* 3841*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 3844*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 3852*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3855*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 6, 7, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ_MM (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3863*/ /*Scope*/ 39, /*->3903*/
+/* 3864*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 3866*/ OPC_MoveParent,
+/* 3867*/ OPC_CheckType, MVT::i32,
+/* 3869*/ OPC_MoveParent,
+/* 3870*/ OPC_RecordChild2, // #3 = $dst
+/* 3871*/ OPC_MoveChild2,
+/* 3872*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3875*/ OPC_MoveParent,
+/* 3876*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 3878*/ OPC_EmitMergeInputChains1_0,
+/* 3879*/ OPC_EmitConvertToTarget, 2,
+/* 3881*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 3884*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 3892*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 3895*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 6, 7, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ_MM (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 3903*/ 0, /*End of Scope*/
+/* 3904*/ /*Scope*/ 72, /*->3977*/
+/* 3905*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 3907*/ OPC_MoveParent,
+/* 3908*/ OPC_MoveChild2,
+/* 3909*/ OPC_Scope, 32, /*->3943*/ // 2 children in Scope
+/* 3911*/ OPC_CheckCondCode, ISD::SETGE,
+/* 3913*/ OPC_MoveParent,
+/* 3914*/ OPC_CheckType, MVT::i32,
+/* 3916*/ OPC_MoveParent,
+/* 3917*/ OPC_RecordChild2, // #3 = $dst
+/* 3918*/ OPC_MoveChild2,
+/* 3919*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3922*/ OPC_MoveParent,
+/* 3923*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 3925*/ OPC_EmitMergeInputChains1_0,
+/* 3926*/ OPC_EmitConvertToTarget, 2,
+/* 3928*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 4, // Results = #5
+/* 3936*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQZC_MMR6 (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), (bb:{ *:[Other] }):$dst)
+/* 3943*/ /*Scope*/ 32, /*->3976*/
+/* 3944*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 3946*/ OPC_MoveParent,
+/* 3947*/ OPC_CheckType, MVT::i32,
+/* 3949*/ OPC_MoveParent,
+/* 3950*/ OPC_RecordChild2, // #3 = $dst
+/* 3951*/ OPC_MoveChild2,
+/* 3952*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3955*/ OPC_MoveParent,
+/* 3956*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 3958*/ OPC_EmitMergeInputChains1_0,
+/* 3959*/ OPC_EmitConvertToTarget, 2,
+/* 3961*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 4, // Results = #5
+/* 3969*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQZC_MMR6 (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), (bb:{ *:[Other] }):$dst)
+/* 3976*/ 0, /*End of Scope*/
+/* 3977*/ /*Scope*/ 78, /*->4056*/
+/* 3978*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 3980*/ OPC_MoveParent,
+/* 3981*/ OPC_MoveChild2,
+/* 3982*/ OPC_Scope, 35, /*->4019*/ // 2 children in Scope
+/* 3984*/ OPC_CheckCondCode, ISD::SETGT,
+/* 3986*/ OPC_MoveParent,
+/* 3987*/ OPC_CheckType, MVT::i32,
+/* 3989*/ OPC_MoveParent,
+/* 3990*/ OPC_RecordChild2, // #3 = $dst
+/* 3991*/ OPC_MoveChild2,
+/* 3992*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 3995*/ OPC_MoveParent,
+/* 3996*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 3998*/ OPC_EmitMergeInputChains1_0,
+/* 3999*/ OPC_EmitConvertToTarget, 2,
+/* 4001*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 4004*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 4012*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 6, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQZC_MMR6 (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), (bb:{ *:[Other] }):$dst)
+/* 4019*/ /*Scope*/ 35, /*->4055*/
+/* 4020*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 4022*/ OPC_MoveParent,
+/* 4023*/ OPC_CheckType, MVT::i32,
+/* 4025*/ OPC_MoveParent,
+/* 4026*/ OPC_RecordChild2, // #3 = $dst
+/* 4027*/ OPC_MoveChild2,
+/* 4028*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4031*/ OPC_MoveParent,
+/* 4032*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 4034*/ OPC_EmitMergeInputChains1_0,
+/* 4035*/ OPC_EmitConvertToTarget, 2,
+/* 4037*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 4040*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 4048*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 6, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQZC_MMR6 (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), (bb:{ *:[Other] }):$dst)
+/* 4055*/ 0, /*End of Scope*/
+/* 4056*/ /*Scope*/ 29, /*->4086*/
+/* 4057*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 4059*/ OPC_MoveParent,
+/* 4060*/ OPC_MoveChild2,
+/* 4061*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 4063*/ OPC_MoveParent,
+/* 4064*/ OPC_CheckType, MVT::i32,
+/* 4066*/ OPC_MoveParent,
+/* 4067*/ OPC_RecordChild2, // #3 = $targ16
+/* 4068*/ OPC_MoveChild2,
+/* 4069*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4072*/ OPC_MoveParent,
+/* 4073*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4075*/ OPC_EmitMergeInputChains1_0,
+/* 4076*/ OPC_EmitConvertToTarget, 2,
+/* 4078*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BteqzT8CmpiX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) - Complexity = 10
+ // Dst: (BteqzT8CmpiX16 CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm, (bb:{ *:[Other] }):$targ16)
+/* 4086*/ /*Scope*/ 58, /*->4145*/
+/* 4087*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 4089*/ OPC_MoveParent,
+/* 4090*/ OPC_MoveChild2,
+/* 4091*/ OPC_Scope, 25, /*->4118*/ // 2 children in Scope
+/* 4093*/ OPC_CheckCondCode, ISD::SETGE,
+/* 4095*/ OPC_MoveParent,
+/* 4096*/ OPC_CheckType, MVT::i32,
+/* 4098*/ OPC_MoveParent,
+/* 4099*/ OPC_RecordChild2, // #3 = $imm16
+/* 4100*/ OPC_MoveChild2,
+/* 4101*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4104*/ OPC_MoveParent,
+/* 4105*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4107*/ OPC_EmitMergeInputChains1_0,
+/* 4108*/ OPC_EmitConvertToTarget, 2,
+/* 4110*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BteqzT8SltiX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) - Complexity = 10
+ // Dst: (BteqzT8SltiX16 CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm, (bb:{ *:[Other] }):$imm16)
+/* 4118*/ /*Scope*/ 25, /*->4144*/
+/* 4119*/ OPC_CheckCondCode, ISD::SETLT,
+/* 4121*/ OPC_MoveParent,
+/* 4122*/ OPC_CheckType, MVT::i32,
+/* 4124*/ OPC_MoveParent,
+/* 4125*/ OPC_RecordChild2, // #3 = $imm16
+/* 4126*/ OPC_MoveChild2,
+/* 4127*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4130*/ OPC_MoveParent,
+/* 4131*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4133*/ OPC_EmitMergeInputChains1_0,
+/* 4134*/ OPC_EmitConvertToTarget, 2,
+/* 4136*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BtnezT8SltiX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) - Complexity = 10
+ // Dst: (BtnezT8SltiX16 CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm, (bb:{ *:[Other] }):$imm16)
+/* 4144*/ 0, /*End of Scope*/
+/* 4145*/ /*Scope*/ 29, /*->4175*/
+/* 4146*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 4148*/ OPC_MoveParent,
+/* 4149*/ OPC_MoveChild2,
+/* 4150*/ OPC_CheckCondCode, ISD::SETNE,
+/* 4152*/ OPC_MoveParent,
+/* 4153*/ OPC_CheckType, MVT::i32,
+/* 4155*/ OPC_MoveParent,
+/* 4156*/ OPC_RecordChild2, // #3 = $targ16
+/* 4157*/ OPC_MoveChild2,
+/* 4158*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4161*/ OPC_MoveParent,
+/* 4162*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4164*/ OPC_EmitMergeInputChains1_0,
+/* 4165*/ OPC_EmitConvertToTarget, 2,
+/* 4167*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BtnezT8CmpiX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16) - Complexity = 10
+ // Dst: (BtnezT8CmpiX16 CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm, (bb:{ *:[Other] }):$targ16)
+/* 4175*/ 0, /*End of Scope*/
+/* 4176*/ /*Scope*/ 7|128,5/*647*/, /*->4825*/
+/* 4178*/ OPC_MoveChild2,
+/* 4179*/ OPC_Scope, 23, /*->4204*/ // 22 children in Scope
+/* 4181*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 4183*/ OPC_MoveParent,
+/* 4184*/ OPC_CheckType, MVT::i32,
+/* 4186*/ OPC_MoveParent,
+/* 4187*/ OPC_RecordChild2, // #3 = $offset
+/* 4188*/ OPC_MoveChild2,
+/* 4189*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4192*/ OPC_MoveParent,
+/* 4193*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 4195*/ OPC_EmitMergeInputChains1_0,
+/* 4196*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 6
+ // Dst: (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
+/* 4204*/ /*Scope*/ 23, /*->4228*/
+/* 4205*/ OPC_CheckCondCode, ISD::SETNE,
+/* 4207*/ OPC_MoveParent,
+/* 4208*/ OPC_CheckType, MVT::i32,
+/* 4210*/ OPC_MoveParent,
+/* 4211*/ OPC_RecordChild2, // #3 = $offset
+/* 4212*/ OPC_MoveChild2,
+/* 4213*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4216*/ OPC_MoveParent,
+/* 4217*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 4219*/ OPC_EmitMergeInputChains1_0,
+/* 4220*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 6
+ // Dst: (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
+/* 4228*/ /*Scope*/ 23, /*->4252*/
+/* 4229*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 4231*/ OPC_MoveParent,
+/* 4232*/ OPC_CheckType, MVT::i32,
+/* 4234*/ OPC_MoveParent,
+/* 4235*/ OPC_RecordChild2, // #3 = $offset
+/* 4236*/ OPC_MoveChild2,
+/* 4237*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4240*/ OPC_MoveParent,
+/* 4241*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 4243*/ OPC_EmitMergeInputChains1_0,
+/* 4244*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 6
+ // Dst: (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
+/* 4252*/ /*Scope*/ 23, /*->4276*/
+/* 4253*/ OPC_CheckCondCode, ISD::SETNE,
+/* 4255*/ OPC_MoveParent,
+/* 4256*/ OPC_CheckType, MVT::i32,
+/* 4258*/ OPC_MoveParent,
+/* 4259*/ OPC_RecordChild2, // #3 = $offset
+/* 4260*/ OPC_MoveChild2,
+/* 4261*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4264*/ OPC_MoveParent,
+/* 4265*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 4267*/ OPC_EmitMergeInputChains1_0,
+/* 4268*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 6
+ // Dst: (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
+/* 4276*/ /*Scope*/ 34, /*->4311*/
+/* 4277*/ OPC_CheckCondCode, ISD::SETGE,
+/* 4279*/ OPC_MoveParent,
+/* 4280*/ OPC_CheckType, MVT::i32,
+/* 4282*/ OPC_MoveParent,
+/* 4283*/ OPC_RecordChild2, // #3 = $dst
+/* 4284*/ OPC_MoveChild2,
+/* 4285*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4288*/ OPC_MoveParent,
+/* 4289*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 4291*/ OPC_EmitMergeInputChains1_0,
+/* 4292*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #4
+/* 4300*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 4303*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 4311*/ /*Scope*/ 34, /*->4346*/
+/* 4312*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 4314*/ OPC_MoveParent,
+/* 4315*/ OPC_CheckType, MVT::i32,
+/* 4317*/ OPC_MoveParent,
+/* 4318*/ OPC_RecordChild2, // #3 = $dst
+/* 4319*/ OPC_MoveChild2,
+/* 4320*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4323*/ OPC_MoveParent,
+/* 4324*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 4326*/ OPC_EmitMergeInputChains1_0,
+/* 4327*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #4
+/* 4335*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 4338*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 4346*/ /*Scope*/ 34, /*->4381*/
+/* 4347*/ OPC_CheckCondCode, ISD::SETLE,
+/* 4349*/ OPC_MoveParent,
+/* 4350*/ OPC_CheckType, MVT::i32,
+/* 4352*/ OPC_MoveParent,
+/* 4353*/ OPC_RecordChild2, // #3 = $dst
+/* 4354*/ OPC_MoveChild2,
+/* 4355*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4358*/ OPC_MoveParent,
+/* 4359*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 4361*/ OPC_EmitMergeInputChains1_0,
+/* 4362*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 2, 1, // Results = #4
+/* 4370*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 4373*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 4381*/ /*Scope*/ 34, /*->4416*/
+/* 4382*/ OPC_CheckCondCode, ISD::SETULE,
+/* 4384*/ OPC_MoveParent,
+/* 4385*/ OPC_CheckType, MVT::i32,
+/* 4387*/ OPC_MoveParent,
+/* 4388*/ OPC_RecordChild2, // #3 = $dst
+/* 4389*/ OPC_MoveChild2,
+/* 4390*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4393*/ OPC_MoveParent,
+/* 4394*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 4396*/ OPC_EmitMergeInputChains1_0,
+/* 4397*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 2, 1, // Results = #4
+/* 4405*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 4408*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 4416*/ /*Scope*/ 34, /*->4451*/
+/* 4417*/ OPC_CheckCondCode, ISD::SETGE,
+/* 4419*/ OPC_MoveParent,
+/* 4420*/ OPC_CheckType, MVT::i32,
+/* 4422*/ OPC_MoveParent,
+/* 4423*/ OPC_RecordChild2, // #3 = $dst
+/* 4424*/ OPC_MoveChild2,
+/* 4425*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4428*/ OPC_MoveParent,
+/* 4429*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 4431*/ OPC_EmitMergeInputChains1_0,
+/* 4432*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #4
+/* 4440*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 4443*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 4451*/ /*Scope*/ 34, /*->4486*/
+/* 4452*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 4454*/ OPC_MoveParent,
+/* 4455*/ OPC_CheckType, MVT::i32,
+/* 4457*/ OPC_MoveParent,
+/* 4458*/ OPC_RecordChild2, // #3 = $dst
+/* 4459*/ OPC_MoveChild2,
+/* 4460*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4463*/ OPC_MoveParent,
+/* 4464*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 4466*/ OPC_EmitMergeInputChains1_0,
+/* 4467*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #4
+/* 4475*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 4478*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 4486*/ /*Scope*/ 34, /*->4521*/
+/* 4487*/ OPC_CheckCondCode, ISD::SETLE,
+/* 4489*/ OPC_MoveParent,
+/* 4490*/ OPC_CheckType, MVT::i32,
+/* 4492*/ OPC_MoveParent,
+/* 4493*/ OPC_RecordChild2, // #3 = $dst
+/* 4494*/ OPC_MoveChild2,
+/* 4495*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4498*/ OPC_MoveParent,
+/* 4499*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 4501*/ OPC_EmitMergeInputChains1_0,
+/* 4502*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 1, // Results = #4
+/* 4510*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 4513*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 4521*/ /*Scope*/ 34, /*->4556*/
+/* 4522*/ OPC_CheckCondCode, ISD::SETULE,
+/* 4524*/ OPC_MoveParent,
+/* 4525*/ OPC_CheckType, MVT::i32,
+/* 4527*/ OPC_MoveParent,
+/* 4528*/ OPC_RecordChild2, // #3 = $dst
+/* 4529*/ OPC_MoveChild2,
+/* 4530*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4533*/ OPC_MoveParent,
+/* 4534*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 4536*/ OPC_EmitMergeInputChains1_0,
+/* 4537*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 1, // Results = #4
+/* 4545*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 4548*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 4556*/ /*Scope*/ 30, /*->4587*/
+/* 4557*/ OPC_CheckCondCode, ISD::SETGE,
+/* 4559*/ OPC_MoveParent,
+/* 4560*/ OPC_CheckType, MVT::i32,
+/* 4562*/ OPC_MoveParent,
+/* 4563*/ OPC_RecordChild2, // #3 = $dst
+/* 4564*/ OPC_MoveChild2,
+/* 4565*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4568*/ OPC_MoveParent,
+/* 4569*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 4571*/ OPC_EmitMergeInputChains1_0,
+/* 4572*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #4
+/* 4580*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
+/* 4587*/ /*Scope*/ 30, /*->4618*/
+/* 4588*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 4590*/ OPC_MoveParent,
+/* 4591*/ OPC_CheckType, MVT::i32,
+/* 4593*/ OPC_MoveParent,
+/* 4594*/ OPC_RecordChild2, // #3 = $dst
+/* 4595*/ OPC_MoveChild2,
+/* 4596*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4599*/ OPC_MoveParent,
+/* 4600*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 4602*/ OPC_EmitMergeInputChains1_0,
+/* 4603*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #4
+/* 4611*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
+/* 4618*/ /*Scope*/ 30, /*->4649*/
+/* 4619*/ OPC_CheckCondCode, ISD::SETLE,
+/* 4621*/ OPC_MoveParent,
+/* 4622*/ OPC_CheckType, MVT::i32,
+/* 4624*/ OPC_MoveParent,
+/* 4625*/ OPC_RecordChild2, // #3 = $dst
+/* 4626*/ OPC_MoveChild2,
+/* 4627*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4630*/ OPC_MoveParent,
+/* 4631*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 4633*/ OPC_EmitMergeInputChains1_0,
+/* 4634*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 1, // Results = #4
+/* 4642*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
+/* 4649*/ /*Scope*/ 30, /*->4680*/
+/* 4650*/ OPC_CheckCondCode, ISD::SETULE,
+/* 4652*/ OPC_MoveParent,
+/* 4653*/ OPC_CheckType, MVT::i32,
+/* 4655*/ OPC_MoveParent,
+/* 4656*/ OPC_RecordChild2, // #3 = $dst
+/* 4657*/ OPC_MoveChild2,
+/* 4658*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4661*/ OPC_MoveParent,
+/* 4662*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 4664*/ OPC_EmitMergeInputChains1_0,
+/* 4665*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 1, // Results = #4
+/* 4673*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 4, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
+/* 4680*/ /*Scope*/ 23, /*->4704*/
+/* 4681*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 4683*/ OPC_MoveParent,
+/* 4684*/ OPC_CheckType, MVT::i32,
+/* 4686*/ OPC_MoveParent,
+/* 4687*/ OPC_RecordChild2, // #3 = $imm16
+/* 4688*/ OPC_MoveChild2,
+/* 4689*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4692*/ OPC_MoveParent,
+/* 4693*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4695*/ OPC_EmitMergeInputChains1_0,
+/* 4696*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BteqzT8CmpX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) - Complexity = 6
+ // Dst: (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
+/* 4704*/ /*Scope*/ 23, /*->4728*/
+/* 4705*/ OPC_CheckCondCode, ISD::SETGT,
+/* 4707*/ OPC_MoveParent,
+/* 4708*/ OPC_CheckType, MVT::i32,
+/* 4710*/ OPC_MoveParent,
+/* 4711*/ OPC_RecordChild2, // #3 = $imm16
+/* 4712*/ OPC_MoveChild2,
+/* 4713*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4716*/ OPC_MoveParent,
+/* 4717*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4719*/ OPC_EmitMergeInputChains1_0,
+/* 4720*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BtnezT8SltX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) - Complexity = 6
+ // Dst: (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
+/* 4728*/ /*Scope*/ 23, /*->4752*/
+/* 4729*/ OPC_CheckCondCode, ISD::SETGE,
+/* 4731*/ OPC_MoveParent,
+/* 4732*/ OPC_CheckType, MVT::i32,
+/* 4734*/ OPC_MoveParent,
+/* 4735*/ OPC_RecordChild2, // #3 = $imm16
+/* 4736*/ OPC_MoveChild2,
+/* 4737*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4740*/ OPC_MoveParent,
+/* 4741*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4743*/ OPC_EmitMergeInputChains1_0,
+/* 4744*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BteqzT8SltX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) - Complexity = 6
+ // Dst: (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
+/* 4752*/ /*Scope*/ 23, /*->4776*/
+/* 4753*/ OPC_CheckCondCode, ISD::SETLT,
+/* 4755*/ OPC_MoveParent,
+/* 4756*/ OPC_CheckType, MVT::i32,
+/* 4758*/ OPC_MoveParent,
+/* 4759*/ OPC_RecordChild2, // #3 = $imm16
+/* 4760*/ OPC_MoveChild2,
+/* 4761*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4764*/ OPC_MoveParent,
+/* 4765*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4767*/ OPC_EmitMergeInputChains1_0,
+/* 4768*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BtnezT8SltX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) - Complexity = 6
+ // Dst: (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
+/* 4776*/ /*Scope*/ 23, /*->4800*/
+/* 4777*/ OPC_CheckCondCode, ISD::SETLE,
+/* 4779*/ OPC_MoveParent,
+/* 4780*/ OPC_CheckType, MVT::i32,
+/* 4782*/ OPC_MoveParent,
+/* 4783*/ OPC_RecordChild2, // #3 = $imm16
+/* 4784*/ OPC_MoveChild2,
+/* 4785*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4788*/ OPC_MoveParent,
+/* 4789*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4791*/ OPC_EmitMergeInputChains1_0,
+/* 4792*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BteqzT8SltX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) - Complexity = 6
+ // Dst: (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
+/* 4800*/ /*Scope*/ 23, /*->4824*/
+/* 4801*/ OPC_CheckCondCode, ISD::SETNE,
+/* 4803*/ OPC_MoveParent,
+/* 4804*/ OPC_CheckType, MVT::i32,
+/* 4806*/ OPC_MoveParent,
+/* 4807*/ OPC_RecordChild2, // #3 = $imm16
+/* 4808*/ OPC_MoveChild2,
+/* 4809*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4812*/ OPC_MoveParent,
+/* 4813*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 4815*/ OPC_EmitMergeInputChains1_0,
+/* 4816*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BtnezT8CmpX16), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16) - Complexity = 6
+ // Dst: (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
+/* 4824*/ 0, /*End of Scope*/
+/* 4825*/ 0, /*End of Scope*/
+/* 4826*/ 0, /*End of Scope*/
+/* 4827*/ /*Scope*/ 82|128,4/*594*/, /*->5423*/
+/* 4829*/ OPC_CheckChild0Type, MVT::i64,
+/* 4831*/ OPC_Scope, 25|128,1/*153*/, /*->4987*/ // 4 children in Scope
+/* 4834*/ OPC_CheckChild1Integer, 0,
+/* 4836*/ OPC_MoveChild2,
+/* 4837*/ OPC_Scope, 22, /*->4861*/ // 6 children in Scope
+/* 4839*/ OPC_CheckCondCode, ISD::SETGE,
+/* 4841*/ OPC_MoveParent,
+/* 4842*/ OPC_CheckType, MVT::i32,
+/* 4844*/ OPC_MoveParent,
+/* 4845*/ OPC_RecordChild2, // #2 = $offset
+/* 4846*/ OPC_MoveChild2,
+/* 4847*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4850*/ OPC_MoveParent,
+/* 4851*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 4853*/ OPC_EmitMergeInputChains1_0,
+/* 4854*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGEZ64), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 4861*/ /*Scope*/ 22, /*->4884*/
+/* 4862*/ OPC_CheckCondCode, ISD::SETGT,
+/* 4864*/ OPC_MoveParent,
+/* 4865*/ OPC_CheckType, MVT::i32,
+/* 4867*/ OPC_MoveParent,
+/* 4868*/ OPC_RecordChild2, // #2 = $offset
+/* 4869*/ OPC_MoveChild2,
+/* 4870*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4873*/ OPC_MoveParent,
+/* 4874*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 4876*/ OPC_EmitMergeInputChains1_0,
+/* 4877*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGTZ64), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 4884*/ /*Scope*/ 22, /*->4907*/
+/* 4885*/ OPC_CheckCondCode, ISD::SETLE,
+/* 4887*/ OPC_MoveParent,
+/* 4888*/ OPC_CheckType, MVT::i32,
+/* 4890*/ OPC_MoveParent,
+/* 4891*/ OPC_RecordChild2, // #2 = $offset
+/* 4892*/ OPC_MoveChild2,
+/* 4893*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4896*/ OPC_MoveParent,
+/* 4897*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 4899*/ OPC_EmitMergeInputChains1_0,
+/* 4900*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLEZ64), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 4907*/ /*Scope*/ 22, /*->4930*/
+/* 4908*/ OPC_CheckCondCode, ISD::SETLT,
+/* 4910*/ OPC_MoveParent,
+/* 4911*/ OPC_CheckType, MVT::i32,
+/* 4913*/ OPC_MoveParent,
+/* 4914*/ OPC_RecordChild2, // #2 = $offset
+/* 4915*/ OPC_MoveChild2,
+/* 4916*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4919*/ OPC_MoveParent,
+/* 4920*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 4922*/ OPC_EmitMergeInputChains1_0,
+/* 4923*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLTZ64), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 11
+ // Dst: (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
+/* 4930*/ /*Scope*/ 27, /*->4958*/
+/* 4931*/ OPC_CheckCondCode, ISD::SETNE,
+/* 4933*/ OPC_MoveParent,
+/* 4934*/ OPC_CheckType, MVT::i32,
+/* 4936*/ OPC_MoveParent,
+/* 4937*/ OPC_RecordChild2, // #2 = $dst
+/* 4938*/ OPC_MoveChild2,
+/* 4939*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4942*/ OPC_MoveParent,
+/* 4943*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 4945*/ OPC_EmitMergeInputChains1_0,
+/* 4946*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 4950*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE64), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BNE64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
+/* 4958*/ /*Scope*/ 27, /*->4986*/
+/* 4959*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 4961*/ OPC_MoveParent,
+/* 4962*/ OPC_CheckType, MVT::i32,
+/* 4964*/ OPC_MoveParent,
+/* 4965*/ OPC_RecordChild2, // #2 = $dst
+/* 4966*/ OPC_MoveChild2,
+/* 4967*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 4970*/ OPC_MoveParent,
+/* 4971*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 4973*/ OPC_EmitMergeInputChains1_0,
+/* 4974*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 4978*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ64), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BEQ64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
+/* 4986*/ 0, /*End of Scope*/
+/* 4987*/ /*Scope*/ 25, /*->5013*/
+/* 4988*/ OPC_CheckChild1Integer, 1,
+/* 4990*/ OPC_MoveChild2,
+/* 4991*/ OPC_CheckCondCode, ISD::SETLT,
+/* 4993*/ OPC_MoveParent,
+/* 4994*/ OPC_CheckType, MVT::i32,
+/* 4996*/ OPC_MoveParent,
+/* 4997*/ OPC_RecordChild2, // #2 = $dst
+/* 4998*/ OPC_MoveChild2,
+/* 4999*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5002*/ OPC_MoveParent,
+/* 5003*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5005*/ OPC_EmitMergeInputChains1_0,
+/* 5006*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BLEZ64), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
+/* 5013*/ /*Scope*/ 34, /*->5048*/
+/* 5014*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 5025*/ OPC_MoveChild2,
+/* 5026*/ OPC_CheckCondCode, ISD::SETGT,
+/* 5028*/ OPC_MoveParent,
+/* 5029*/ OPC_CheckType, MVT::i32,
+/* 5031*/ OPC_MoveParent,
+/* 5032*/ OPC_RecordChild2, // #2 = $dst
+/* 5033*/ OPC_MoveChild2,
+/* 5034*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5037*/ OPC_MoveParent,
+/* 5038*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5040*/ OPC_EmitMergeInputChains1_0,
+/* 5041*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BGEZ64), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 11
+ // Dst: (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
+/* 5048*/ /*Scope*/ 116|128,2/*372*/, /*->5422*/
+/* 5050*/ OPC_RecordChild1, // #2 = $rhs
+/* 5051*/ OPC_Scope, 46|128,1/*174*/, /*->5228*/ // 2 children in Scope
+/* 5054*/ OPC_MoveChild1,
+/* 5055*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5058*/ OPC_Scope, 80, /*->5140*/ // 2 children in Scope
+/* 5060*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 5062*/ OPC_MoveParent,
+/* 5063*/ OPC_MoveChild2,
+/* 5064*/ OPC_Scope, 36, /*->5102*/ // 2 children in Scope
+/* 5066*/ OPC_CheckCondCode, ISD::SETGE,
+/* 5068*/ OPC_MoveParent,
+/* 5069*/ OPC_CheckType, MVT::i32,
+/* 5071*/ OPC_MoveParent,
+/* 5072*/ OPC_RecordChild2, // #3 = $dst
+/* 5073*/ OPC_MoveChild2,
+/* 5074*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5077*/ OPC_MoveParent,
+/* 5078*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5080*/ OPC_EmitMergeInputChains1_0,
+/* 5081*/ OPC_EmitConvertToTarget, 2,
+/* 5083*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 4, // Results = #5
+/* 5091*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5094*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 5, 6, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5102*/ /*Scope*/ 36, /*->5139*/
+/* 5103*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 5105*/ OPC_MoveParent,
+/* 5106*/ OPC_CheckType, MVT::i32,
+/* 5108*/ OPC_MoveParent,
+/* 5109*/ OPC_RecordChild2, // #3 = $dst
+/* 5110*/ OPC_MoveChild2,
+/* 5111*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5114*/ OPC_MoveParent,
+/* 5115*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5117*/ OPC_EmitMergeInputChains1_0,
+/* 5118*/ OPC_EmitConvertToTarget, 2,
+/* 5120*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 4, // Results = #5
+/* 5128*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5131*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 5, 6, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5139*/ 0, /*End of Scope*/
+/* 5140*/ /*Scope*/ 86, /*->5227*/
+/* 5141*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 5143*/ OPC_MoveParent,
+/* 5144*/ OPC_MoveChild2,
+/* 5145*/ OPC_Scope, 39, /*->5186*/ // 2 children in Scope
+/* 5147*/ OPC_CheckCondCode, ISD::SETGT,
+/* 5149*/ OPC_MoveParent,
+/* 5150*/ OPC_CheckType, MVT::i32,
+/* 5152*/ OPC_MoveParent,
+/* 5153*/ OPC_RecordChild2, // #3 = $dst
+/* 5154*/ OPC_MoveChild2,
+/* 5155*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5158*/ OPC_MoveParent,
+/* 5159*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5161*/ OPC_EmitMergeInputChains1_0,
+/* 5162*/ OPC_EmitConvertToTarget, 2,
+/* 5164*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 5167*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 5175*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5178*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 6, 7, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5186*/ /*Scope*/ 39, /*->5226*/
+/* 5187*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 5189*/ OPC_MoveParent,
+/* 5190*/ OPC_CheckType, MVT::i32,
+/* 5192*/ OPC_MoveParent,
+/* 5193*/ OPC_RecordChild2, // #3 = $dst
+/* 5194*/ OPC_MoveChild2,
+/* 5195*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5198*/ OPC_MoveParent,
+/* 5199*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5201*/ OPC_EmitMergeInputChains1_0,
+/* 5202*/ OPC_EmitConvertToTarget, 2,
+/* 5204*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 5207*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 5, // Results = #6
+/* 5215*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5218*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 6, 7, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 10
+ // Dst: (BEQ (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5226*/ 0, /*End of Scope*/
+/* 5227*/ 0, /*End of Scope*/
+/* 5228*/ /*Scope*/ 63|128,1/*191*/, /*->5421*/
+/* 5230*/ OPC_MoveChild2,
+/* 5231*/ OPC_Scope, 23, /*->5256*/ // 6 children in Scope
+/* 5233*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5235*/ OPC_MoveParent,
+/* 5236*/ OPC_CheckType, MVT::i32,
+/* 5238*/ OPC_MoveParent,
+/* 5239*/ OPC_RecordChild2, // #3 = $offset
+/* 5240*/ OPC_MoveChild2,
+/* 5241*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5244*/ OPC_MoveParent,
+/* 5245*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 5247*/ OPC_EmitMergeInputChains1_0,
+/* 5248*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ64), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 6
+ // Dst: (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
+/* 5256*/ /*Scope*/ 23, /*->5280*/
+/* 5257*/ OPC_CheckCondCode, ISD::SETNE,
+/* 5259*/ OPC_MoveParent,
+/* 5260*/ OPC_CheckType, MVT::i32,
+/* 5262*/ OPC_MoveParent,
+/* 5263*/ OPC_RecordChild2, // #3 = $offset
+/* 5264*/ OPC_MoveChild2,
+/* 5265*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5268*/ OPC_MoveParent,
+/* 5269*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 5271*/ OPC_EmitMergeInputChains1_0,
+/* 5272*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE64), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset) - Complexity = 6
+ // Dst: (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
+/* 5280*/ /*Scope*/ 34, /*->5315*/
+/* 5281*/ OPC_CheckCondCode, ISD::SETGE,
+/* 5283*/ OPC_MoveParent,
+/* 5284*/ OPC_CheckType, MVT::i32,
+/* 5286*/ OPC_MoveParent,
+/* 5287*/ OPC_RecordChild2, // #3 = $dst
+/* 5288*/ OPC_MoveChild2,
+/* 5289*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5292*/ OPC_MoveParent,
+/* 5293*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5295*/ OPC_EmitMergeInputChains1_0,
+/* 5296*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #4
+/* 5304*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5307*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5315*/ /*Scope*/ 34, /*->5350*/
+/* 5316*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 5318*/ OPC_MoveParent,
+/* 5319*/ OPC_CheckType, MVT::i32,
+/* 5321*/ OPC_MoveParent,
+/* 5322*/ OPC_RecordChild2, // #3 = $dst
+/* 5323*/ OPC_MoveChild2,
+/* 5324*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5327*/ OPC_MoveParent,
+/* 5328*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5330*/ OPC_EmitMergeInputChains1_0,
+/* 5331*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #4
+/* 5339*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5342*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5350*/ /*Scope*/ 34, /*->5385*/
+/* 5351*/ OPC_CheckCondCode, ISD::SETLE,
+/* 5353*/ OPC_MoveParent,
+/* 5354*/ OPC_CheckType, MVT::i32,
+/* 5356*/ OPC_MoveParent,
+/* 5357*/ OPC_RecordChild2, // #3 = $dst
+/* 5358*/ OPC_MoveChild2,
+/* 5359*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5362*/ OPC_MoveParent,
+/* 5363*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5365*/ OPC_EmitMergeInputChains1_0,
+/* 5366*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 2, 1, // Results = #4
+/* 5374*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5377*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5385*/ /*Scope*/ 34, /*->5420*/
+/* 5386*/ OPC_CheckCondCode, ISD::SETULE,
+/* 5388*/ OPC_MoveParent,
+/* 5389*/ OPC_CheckType, MVT::i32,
+/* 5391*/ OPC_MoveParent,
+/* 5392*/ OPC_RecordChild2, // #3 = $dst
+/* 5393*/ OPC_MoveChild2,
+/* 5394*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5397*/ OPC_MoveParent,
+/* 5398*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5400*/ OPC_EmitMergeInputChains1_0,
+/* 5401*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 2, 1, // Results = #4
+/* 5409*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5412*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 4, 5, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst) - Complexity = 6
+ // Dst: (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5420*/ 0, /*End of Scope*/
+/* 5421*/ 0, /*End of Scope*/
+/* 5422*/ 0, /*End of Scope*/
+/* 5423*/ 0, /*End of Scope*/
+/* 5424*/ 0, /*End of Scope*/
+/* 5425*/ /*Scope*/ 90, /*->5516*/
+/* 5426*/ OPC_RecordChild1, // #1 = $cond
+/* 5427*/ OPC_Scope, 62, /*->5491*/ // 2 children in Scope
+/* 5429*/ OPC_CheckChild1Type, MVT::i32,
+/* 5431*/ OPC_RecordChild2, // #2 = $dst
+/* 5432*/ OPC_MoveChild2,
+/* 5433*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5436*/ OPC_MoveParent,
+/* 5437*/ OPC_Scope, 14, /*->5453*/ // 4 children in Scope
+/* 5439*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 5441*/ OPC_EmitMergeInputChains1_0,
+/* 5442*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5445*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) - Complexity = 3
+ // Dst: (BNE GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5453*/ /*Scope*/ 10, /*->5464*/
+/* 5454*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 5456*/ OPC_EmitMergeInputChains1_0,
+/* 5457*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BnezRxImm16), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16) - Complexity = 3
+ // Dst: (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
+/* 5464*/ /*Scope*/ 14, /*->5479*/
+/* 5465*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 5467*/ OPC_EmitMergeInputChains1_0,
+/* 5468*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 5471*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE_MM), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) - Complexity = 3
+ // Dst: (BNE_MM GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
+/* 5479*/ /*Scope*/ 10, /*->5490*/
+/* 5480*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 5482*/ OPC_EmitMergeInputChains1_0,
+/* 5483*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNEZC_MMR6), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst) - Complexity = 3
+ // Dst: (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
+/* 5490*/ 0, /*End of Scope*/
+/* 5491*/ /*Scope*/ 23, /*->5515*/
+/* 5492*/ OPC_CheckChild1Type, MVT::i64,
+/* 5494*/ OPC_RecordChild2, // #2 = $dst
+/* 5495*/ OPC_MoveChild2,
+/* 5496*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 5499*/ OPC_MoveParent,
+/* 5500*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 5502*/ OPC_EmitMergeInputChains1_0,
+/* 5503*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 5507*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BNE64), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst) - Complexity = 3
+ // Dst: (BNE64 GPR64:{ *:[i64] }:$cond, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
+/* 5515*/ 0, /*End of Scope*/
+/* 5516*/ 0, /*End of Scope*/
+/* 5517*/ /*SwitchOpcode*/ 5|128,62/*7941*/, TARGET_VAL(ISD::SELECT),// ->13462
+/* 5521*/ OPC_Scope, 83|128,26/*3411*/, /*->8935*/ // 6 children in Scope
+/* 5524*/ OPC_MoveChild0,
+/* 5525*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
+/* 5528*/ OPC_RecordChild0, // #0 = $cond
+/* 5529*/ OPC_Scope, 112|128,18/*2416*/, /*->7948*/ // 2 children in Scope
+/* 5532*/ OPC_CheckChild0Type, MVT::i32,
+/* 5534*/ OPC_Scope, 103|128,2/*359*/, /*->5896*/ // 7 children in Scope
+/* 5537*/ OPC_MoveChild1,
+/* 5538*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5541*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5543*/ OPC_MoveParent,
+/* 5544*/ OPC_MoveChild2,
+/* 5545*/ OPC_Scope, 26, /*->5573*/ // 11 children in Scope
+/* 5547*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5549*/ OPC_MoveParent,
+/* 5550*/ OPC_CheckType, MVT::i32,
+/* 5552*/ OPC_MoveParent,
+/* 5553*/ OPC_RecordChild1, // #1 = $t
+/* 5554*/ OPC_MoveChild2,
+/* 5555*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5558*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5560*/ OPC_MoveParent,
+/* 5561*/ OPC_CheckType, MVT::i32,
+/* 5563*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 5565*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), i32:{ *:[i32] }:$t, (imm:{ *:[i32] })<<P:Predicate_immz>>) - Complexity = 14
+ // Dst: (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond)
+/* 5573*/ /*Scope*/ 26, /*->5600*/
+/* 5574*/ OPC_CheckCondCode, ISD::SETNE,
+/* 5576*/ OPC_MoveParent,
+/* 5577*/ OPC_CheckType, MVT::i32,
+/* 5579*/ OPC_MoveParent,
+/* 5580*/ OPC_RecordChild1, // #1 = $t
+/* 5581*/ OPC_MoveChild2,
+/* 5582*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5585*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5587*/ OPC_MoveParent,
+/* 5588*/ OPC_CheckType, MVT::i32,
+/* 5590*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 5592*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), i32:{ *:[i32] }:$t, (imm:{ *:[i32] })<<P:Predicate_immz>>) - Complexity = 14
+ // Dst: (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond)
+/* 5600*/ /*Scope*/ 26, /*->5627*/
+/* 5601*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5603*/ OPC_MoveParent,
+/* 5604*/ OPC_CheckType, MVT::i32,
+/* 5606*/ OPC_MoveParent,
+/* 5607*/ OPC_MoveChild1,
+/* 5608*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5611*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5613*/ OPC_MoveParent,
+/* 5614*/ OPC_RecordChild2, // #1 = $f
+/* 5615*/ OPC_CheckType, MVT::i32,
+/* 5617*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 5619*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), (imm:{ *:[i32] })<<P:Predicate_immz>>, i32:{ *:[i32] }:$f) - Complexity = 14
+ // Dst: (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)
+/* 5627*/ /*Scope*/ 26, /*->5654*/
+/* 5628*/ OPC_CheckCondCode, ISD::SETNE,
+/* 5630*/ OPC_MoveParent,
+/* 5631*/ OPC_CheckType, MVT::i32,
+/* 5633*/ OPC_MoveParent,
+/* 5634*/ OPC_MoveChild1,
+/* 5635*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5638*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5640*/ OPC_MoveParent,
+/* 5641*/ OPC_RecordChild2, // #1 = $f
+/* 5642*/ OPC_CheckType, MVT::i32,
+/* 5644*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 5646*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), (imm:{ *:[i32] })<<P:Predicate_immz>>, i32:{ *:[i32] }:$f) - Complexity = 14
+ // Dst: (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)
+/* 5654*/ /*Scope*/ 26, /*->5681*/
+/* 5655*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5657*/ OPC_MoveParent,
+/* 5658*/ OPC_CheckType, MVT::i32,
+/* 5660*/ OPC_MoveParent,
+/* 5661*/ OPC_RecordChild1, // #1 = $t
+/* 5662*/ OPC_MoveChild2,
+/* 5663*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5666*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5668*/ OPC_MoveParent,
+/* 5669*/ OPC_CheckType, MVT::i32,
+/* 5671*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 5673*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), i32:{ *:[i32] }:$t, (imm:{ *:[i32] })<<P:Predicate_immz>>) - Complexity = 14
+ // Dst: (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond)
+/* 5681*/ /*Scope*/ 26, /*->5708*/
+/* 5682*/ OPC_CheckCondCode, ISD::SETNE,
+/* 5684*/ OPC_MoveParent,
+/* 5685*/ OPC_CheckType, MVT::i32,
+/* 5687*/ OPC_MoveParent,
+/* 5688*/ OPC_RecordChild1, // #1 = $t
+/* 5689*/ OPC_MoveChild2,
+/* 5690*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5693*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5695*/ OPC_MoveParent,
+/* 5696*/ OPC_CheckType, MVT::i32,
+/* 5698*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 5700*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), i32:{ *:[i32] }:$t, (imm:{ *:[i32] })<<P:Predicate_immz>>) - Complexity = 14
+ // Dst: (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond)
+/* 5708*/ /*Scope*/ 26, /*->5735*/
+/* 5709*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5711*/ OPC_MoveParent,
+/* 5712*/ OPC_CheckType, MVT::i32,
+/* 5714*/ OPC_MoveParent,
+/* 5715*/ OPC_MoveChild1,
+/* 5716*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5719*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5721*/ OPC_MoveParent,
+/* 5722*/ OPC_RecordChild2, // #1 = $f
+/* 5723*/ OPC_CheckType, MVT::i32,
+/* 5725*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 5727*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), (imm:{ *:[i32] })<<P:Predicate_immz>>, i32:{ *:[i32] }:$f) - Complexity = 14
+ // Dst: (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)
+/* 5735*/ /*Scope*/ 57, /*->5793*/
+/* 5736*/ OPC_CheckCondCode, ISD::SETNE,
+/* 5738*/ OPC_MoveParent,
+/* 5739*/ OPC_CheckType, MVT::i32,
+/* 5741*/ OPC_MoveParent,
+/* 5742*/ OPC_Scope, 20, /*->5764*/ // 2 children in Scope
+/* 5744*/ OPC_MoveChild1,
+/* 5745*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5748*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5750*/ OPC_MoveParent,
+/* 5751*/ OPC_RecordChild2, // #1 = $f
+/* 5752*/ OPC_CheckType, MVT::i32,
+/* 5754*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 5756*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), (imm:{ *:[i32] })<<P:Predicate_immz>>, i32:{ *:[i32] }:$f) - Complexity = 14
+ // Dst: (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)
+/* 5764*/ /*Scope*/ 27, /*->5792*/
+/* 5765*/ OPC_RecordChild1, // #1 = $t
+/* 5766*/ OPC_MoveChild2,
+/* 5767*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5770*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5772*/ OPC_MoveParent,
+/* 5773*/ OPC_CheckType, MVT::i64,
+/* 5775*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 5777*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #2
+/* 5784*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), i64:{ *:[i64] }:$t, (imm:{ *:[i64] })<<P:Predicate_immz>>) - Complexity = 14
+ // Dst: (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))
+/* 5792*/ 0, /*End of Scope*/
+/* 5793*/ /*Scope*/ 33, /*->5827*/
+/* 5794*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5796*/ OPC_MoveParent,
+/* 5797*/ OPC_CheckType, MVT::i32,
+/* 5799*/ OPC_MoveParent,
+/* 5800*/ OPC_RecordChild1, // #1 = $t
+/* 5801*/ OPC_MoveChild2,
+/* 5802*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5805*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5807*/ OPC_MoveParent,
+/* 5808*/ OPC_CheckType, MVT::i64,
+/* 5810*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 5812*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #2
+/* 5819*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), i64:{ *:[i64] }:$t, (imm:{ *:[i64] })<<P:Predicate_immz>>) - Complexity = 14
+ // Dst: (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))
+/* 5827*/ /*Scope*/ 33, /*->5861*/
+/* 5828*/ OPC_CheckCondCode, ISD::SETNE,
+/* 5830*/ OPC_MoveParent,
+/* 5831*/ OPC_CheckType, MVT::i32,
+/* 5833*/ OPC_MoveParent,
+/* 5834*/ OPC_MoveChild1,
+/* 5835*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5838*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5840*/ OPC_MoveParent,
+/* 5841*/ OPC_RecordChild2, // #1 = $f
+/* 5842*/ OPC_CheckType, MVT::i64,
+/* 5844*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 5846*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #2
+/* 5853*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_immz>>, i64:{ *:[i64] }:$f) - Complexity = 14
+ // Dst: (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))
+/* 5861*/ /*Scope*/ 33, /*->5895*/
+/* 5862*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5864*/ OPC_MoveParent,
+/* 5865*/ OPC_CheckType, MVT::i32,
+/* 5867*/ OPC_MoveParent,
+/* 5868*/ OPC_MoveChild1,
+/* 5869*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5872*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 5874*/ OPC_MoveParent,
+/* 5875*/ OPC_RecordChild2, // #1 = $f
+/* 5876*/ OPC_CheckType, MVT::i64,
+/* 5878*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 5880*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #2
+/* 5887*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_immz>>, i64:{ *:[i64] }:$f) - Complexity = 14
+ // Dst: (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))
+/* 5895*/ 0, /*End of Scope*/
+/* 5896*/ /*Scope*/ 83|128,1/*211*/, /*->6109*/
+/* 5898*/ OPC_CheckChild1Integer, 0,
+/* 5900*/ OPC_MoveChild2,
+/* 5901*/ OPC_Scope, 36, /*->5939*/ // 8 children in Scope
+/* 5903*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5905*/ OPC_MoveParent,
+/* 5906*/ OPC_CheckType, MVT::i32,
+/* 5908*/ OPC_MoveParent,
+/* 5909*/ OPC_RecordChild1, // #1 = $T
+/* 5910*/ OPC_RecordChild2, // #2 = $F
+/* 5911*/ OPC_SwitchType /*2 cases */, 11, MVT::i32,// ->5925
+/* 5914*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 5916*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
+/* 5925*/ /*SwitchType*/ 11, MVT::i64,// ->5938
+/* 5927*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 5929*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
+/* 5938*/ 0, // EndSwitchType
+/* 5939*/ /*Scope*/ 36, /*->5976*/
+/* 5940*/ OPC_CheckCondCode, ISD::SETNE,
+/* 5942*/ OPC_MoveParent,
+/* 5943*/ OPC_CheckType, MVT::i32,
+/* 5945*/ OPC_MoveParent,
+/* 5946*/ OPC_RecordChild1, // #1 = $T
+/* 5947*/ OPC_RecordChild2, // #2 = $F
+/* 5948*/ OPC_SwitchType /*2 cases */, 11, MVT::i32,// ->5962
+/* 5951*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 5953*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
+/* 5962*/ /*SwitchType*/ 11, MVT::i64,// ->5975
+/* 5964*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 5966*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
+/* 5975*/ 0, // EndSwitchType
+/* 5976*/ /*Scope*/ 21, /*->5998*/
+/* 5977*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 5979*/ OPC_MoveParent,
+/* 5980*/ OPC_CheckType, MVT::i32,
+/* 5982*/ OPC_MoveParent,
+/* 5983*/ OPC_RecordChild1, // #1 = $T
+/* 5984*/ OPC_RecordChild2, // #2 = $F
+/* 5985*/ OPC_CheckType, MVT::i32,
+/* 5987*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 5989*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
+/* 5998*/ /*Scope*/ 21, /*->6020*/
+/* 5999*/ OPC_CheckCondCode, ISD::SETNE,
+/* 6001*/ OPC_MoveParent,
+/* 6002*/ OPC_CheckType, MVT::i32,
+/* 6004*/ OPC_MoveParent,
+/* 6005*/ OPC_RecordChild1, // #1 = $T
+/* 6006*/ OPC_RecordChild2, // #2 = $F
+/* 6007*/ OPC_CheckType, MVT::i32,
+/* 6009*/ OPC_CheckPatternPredicate, 35, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6011*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
+/* 6020*/ /*Scope*/ 21, /*->6042*/
+/* 6021*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 6023*/ OPC_MoveParent,
+/* 6024*/ OPC_CheckType, MVT::i32,
+/* 6026*/ OPC_MoveParent,
+/* 6027*/ OPC_RecordChild1, // #1 = $T
+/* 6028*/ OPC_RecordChild2, // #2 = $F
+/* 6029*/ OPC_CheckType, MVT::i32,
+/* 6031*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6033*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
+/* 6042*/ /*Scope*/ 21, /*->6064*/
+/* 6043*/ OPC_CheckCondCode, ISD::SETNE,
+/* 6045*/ OPC_MoveParent,
+/* 6046*/ OPC_CheckType, MVT::i32,
+/* 6048*/ OPC_MoveParent,
+/* 6049*/ OPC_RecordChild1, // #1 = $T
+/* 6050*/ OPC_RecordChild2, // #2 = $F
+/* 6051*/ OPC_CheckType, MVT::i32,
+/* 6053*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6055*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
+/* 6064*/ /*Scope*/ 21, /*->6086*/
+/* 6065*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 6067*/ OPC_MoveParent,
+/* 6068*/ OPC_CheckType, MVT::i32,
+/* 6070*/ OPC_MoveParent,
+/* 6071*/ OPC_RecordChild1, // #1 = $x
+/* 6072*/ OPC_RecordChild2, // #2 = $y
+/* 6073*/ OPC_CheckType, MVT::i32,
+/* 6075*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 6077*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelBeqZ), 0,
+ MVT::i32, 3/*#Ops*/, 1, 2, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 11
+ // Dst: (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
+/* 6086*/ /*Scope*/ 21, /*->6108*/
+/* 6087*/ OPC_CheckCondCode, ISD::SETNE,
+/* 6089*/ OPC_MoveParent,
+/* 6090*/ OPC_CheckType, MVT::i32,
+/* 6092*/ OPC_MoveParent,
+/* 6093*/ OPC_RecordChild1, // #1 = $x
+/* 6094*/ OPC_RecordChild2, // #2 = $y
+/* 6095*/ OPC_CheckType, MVT::i32,
+/* 6097*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 6099*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelBneZ), 0,
+ MVT::i32, 3/*#Ops*/, 1, 2, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 11
+ // Dst: (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
+/* 6108*/ 0, /*End of Scope*/
+/* 6109*/ /*Scope*/ 115|128,5/*755*/, /*->6866*/
+/* 6111*/ OPC_RecordChild1, // #1 = $rhs
+/* 6112*/ OPC_MoveChild1,
+/* 6113*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 6116*/ OPC_Scope, 70, /*->6188*/ // 12 children in Scope
+/* 6118*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 6120*/ OPC_MoveParent,
+/* 6121*/ OPC_MoveChild2,
+/* 6122*/ OPC_Scope, 31, /*->6155*/ // 2 children in Scope
+/* 6124*/ OPC_CheckCondCode, ISD::SETGE,
+/* 6126*/ OPC_MoveParent,
+/* 6127*/ OPC_CheckType, MVT::i32,
+/* 6129*/ OPC_MoveParent,
+/* 6130*/ OPC_RecordChild1, // #2 = $T
+/* 6131*/ OPC_RecordChild2, // #3 = $F
+/* 6132*/ OPC_CheckType, MVT::i32,
+/* 6134*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6136*/ OPC_EmitConvertToTarget, 1,
+/* 6138*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 6146*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), GPR32:{ *:[i32] }:$F)
+/* 6155*/ /*Scope*/ 31, /*->6187*/
+/* 6156*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 6158*/ OPC_MoveParent,
+/* 6159*/ OPC_CheckType, MVT::i32,
+/* 6161*/ OPC_MoveParent,
+/* 6162*/ OPC_RecordChild1, // #2 = $T
+/* 6163*/ OPC_RecordChild2, // #3 = $F
+/* 6164*/ OPC_CheckType, MVT::i32,
+/* 6166*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6168*/ OPC_EmitConvertToTarget, 1,
+/* 6170*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 6178*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), GPR32:{ *:[i32] }:$F)
+/* 6187*/ 0, /*End of Scope*/
+/* 6188*/ /*Scope*/ 76, /*->6265*/
+/* 6189*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 6191*/ OPC_MoveParent,
+/* 6192*/ OPC_MoveChild2,
+/* 6193*/ OPC_Scope, 34, /*->6229*/ // 2 children in Scope
+/* 6195*/ OPC_CheckCondCode, ISD::SETGT,
+/* 6197*/ OPC_MoveParent,
+/* 6198*/ OPC_CheckType, MVT::i32,
+/* 6200*/ OPC_MoveParent,
+/* 6201*/ OPC_RecordChild1, // #2 = $T
+/* 6202*/ OPC_RecordChild2, // #3 = $F
+/* 6203*/ OPC_CheckType, MVT::i32,
+/* 6205*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6207*/ OPC_EmitConvertToTarget, 1,
+/* 6209*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 6212*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6220*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), GPR32:{ *:[i32] }:$F)
+/* 6229*/ /*Scope*/ 34, /*->6264*/
+/* 6230*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 6232*/ OPC_MoveParent,
+/* 6233*/ OPC_CheckType, MVT::i32,
+/* 6235*/ OPC_MoveParent,
+/* 6236*/ OPC_RecordChild1, // #2 = $T
+/* 6237*/ OPC_RecordChild2, // #3 = $F
+/* 6238*/ OPC_CheckType, MVT::i32,
+/* 6240*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6242*/ OPC_EmitConvertToTarget, 1,
+/* 6244*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 6247*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6255*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), GPR32:{ *:[i32] }:$F)
+/* 6264*/ 0, /*End of Scope*/
+/* 6265*/ /*Scope*/ 38, /*->6304*/
+/* 6266*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 6268*/ OPC_MoveParent,
+/* 6269*/ OPC_MoveChild2,
+/* 6270*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 6272*/ OPC_MoveParent,
+/* 6273*/ OPC_CheckType, MVT::i32,
+/* 6275*/ OPC_MoveParent,
+/* 6276*/ OPC_RecordChild1, // #2 = $T
+/* 6277*/ OPC_RecordChild2, // #3 = $F
+/* 6278*/ OPC_CheckType, MVT::i32,
+/* 6280*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6282*/ OPC_EmitConvertToTarget, 1,
+/* 6284*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 6287*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6295*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$uimm16, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XORi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$uimm16)), GPR32:{ *:[i32] }:$F)
+/* 6304*/ /*Scope*/ 70, /*->6375*/
+/* 6305*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 6307*/ OPC_MoveParent,
+/* 6308*/ OPC_MoveChild2,
+/* 6309*/ OPC_Scope, 31, /*->6342*/ // 2 children in Scope
+/* 6311*/ OPC_CheckCondCode, ISD::SETGE,
+/* 6313*/ OPC_MoveParent,
+/* 6314*/ OPC_CheckType, MVT::i32,
+/* 6316*/ OPC_MoveParent,
+/* 6317*/ OPC_RecordChild1, // #2 = $T
+/* 6318*/ OPC_RecordChild2, // #3 = $F
+/* 6319*/ OPC_CheckType, MVT::i64,
+/* 6321*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6323*/ OPC_EmitConvertToTarget, 1,
+/* 6325*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 6333*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), GPR64:{ *:[i64] }:$F)
+/* 6342*/ /*Scope*/ 31, /*->6374*/
+/* 6343*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 6345*/ OPC_MoveParent,
+/* 6346*/ OPC_CheckType, MVT::i32,
+/* 6348*/ OPC_MoveParent,
+/* 6349*/ OPC_RecordChild1, // #2 = $T
+/* 6350*/ OPC_RecordChild2, // #3 = $F
+/* 6351*/ OPC_CheckType, MVT::i64,
+/* 6353*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6355*/ OPC_EmitConvertToTarget, 1,
+/* 6357*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 6365*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), GPR64:{ *:[i64] }:$F)
+/* 6374*/ 0, /*End of Scope*/
+/* 6375*/ /*Scope*/ 76, /*->6452*/
+/* 6376*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 6378*/ OPC_MoveParent,
+/* 6379*/ OPC_MoveChild2,
+/* 6380*/ OPC_Scope, 34, /*->6416*/ // 2 children in Scope
+/* 6382*/ OPC_CheckCondCode, ISD::SETGT,
+/* 6384*/ OPC_MoveParent,
+/* 6385*/ OPC_CheckType, MVT::i32,
+/* 6387*/ OPC_MoveParent,
+/* 6388*/ OPC_RecordChild1, // #2 = $T
+/* 6389*/ OPC_RecordChild2, // #3 = $F
+/* 6390*/ OPC_CheckType, MVT::i64,
+/* 6392*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6394*/ OPC_EmitConvertToTarget, 1,
+/* 6396*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 6399*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6407*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), GPR64:{ *:[i64] }:$F)
+/* 6416*/ /*Scope*/ 34, /*->6451*/
+/* 6417*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 6419*/ OPC_MoveParent,
+/* 6420*/ OPC_CheckType, MVT::i32,
+/* 6422*/ OPC_MoveParent,
+/* 6423*/ OPC_RecordChild1, // #2 = $T
+/* 6424*/ OPC_RecordChild2, // #3 = $F
+/* 6425*/ OPC_CheckType, MVT::i64,
+/* 6427*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6429*/ OPC_EmitConvertToTarget, 1,
+/* 6431*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 6434*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6442*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), GPR64:{ *:[i64] }:$F)
+/* 6451*/ 0, /*End of Scope*/
+/* 6452*/ /*Scope*/ 38, /*->6491*/
+/* 6453*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 6455*/ OPC_MoveParent,
+/* 6456*/ OPC_MoveChild2,
+/* 6457*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 6459*/ OPC_MoveParent,
+/* 6460*/ OPC_CheckType, MVT::i32,
+/* 6462*/ OPC_MoveParent,
+/* 6463*/ OPC_RecordChild1, // #2 = $T
+/* 6464*/ OPC_RecordChild2, // #3 = $F
+/* 6465*/ OPC_CheckType, MVT::i64,
+/* 6467*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 6469*/ OPC_EmitConvertToTarget, 1,
+/* 6471*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 6474*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6482*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$uimm16, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XORi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$uimm16)), GPR64:{ *:[i64] }:$F)
+/* 6491*/ /*Scope*/ 70, /*->6562*/
+/* 6492*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 6494*/ OPC_MoveParent,
+/* 6495*/ OPC_MoveChild2,
+/* 6496*/ OPC_Scope, 31, /*->6529*/ // 2 children in Scope
+/* 6498*/ OPC_CheckCondCode, ISD::SETGE,
+/* 6500*/ OPC_MoveParent,
+/* 6501*/ OPC_CheckType, MVT::i32,
+/* 6503*/ OPC_MoveParent,
+/* 6504*/ OPC_RecordChild1, // #2 = $T
+/* 6505*/ OPC_RecordChild2, // #3 = $F
+/* 6506*/ OPC_CheckType, MVT::i32,
+/* 6508*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6510*/ OPC_EmitConvertToTarget, 1,
+/* 6512*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 6520*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), GPR32:{ *:[i32] }:$F)
+/* 6529*/ /*Scope*/ 31, /*->6561*/
+/* 6530*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 6532*/ OPC_MoveParent,
+/* 6533*/ OPC_CheckType, MVT::i32,
+/* 6535*/ OPC_MoveParent,
+/* 6536*/ OPC_RecordChild1, // #2 = $T
+/* 6537*/ OPC_RecordChild2, // #3 = $F
+/* 6538*/ OPC_CheckType, MVT::i32,
+/* 6540*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6542*/ OPC_EmitConvertToTarget, 1,
+/* 6544*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 6552*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), GPR32:{ *:[i32] }:$F)
+/* 6561*/ 0, /*End of Scope*/
+/* 6562*/ /*Scope*/ 76, /*->6639*/
+/* 6563*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 6565*/ OPC_MoveParent,
+/* 6566*/ OPC_MoveChild2,
+/* 6567*/ OPC_Scope, 34, /*->6603*/ // 2 children in Scope
+/* 6569*/ OPC_CheckCondCode, ISD::SETGT,
+/* 6571*/ OPC_MoveParent,
+/* 6572*/ OPC_CheckType, MVT::i32,
+/* 6574*/ OPC_MoveParent,
+/* 6575*/ OPC_RecordChild1, // #2 = $T
+/* 6576*/ OPC_RecordChild2, // #3 = $F
+/* 6577*/ OPC_CheckType, MVT::i32,
+/* 6579*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6581*/ OPC_EmitConvertToTarget, 1,
+/* 6583*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 6586*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6594*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), GPR32:{ *:[i32] }:$F)
+/* 6603*/ /*Scope*/ 34, /*->6638*/
+/* 6604*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 6606*/ OPC_MoveParent,
+/* 6607*/ OPC_CheckType, MVT::i32,
+/* 6609*/ OPC_MoveParent,
+/* 6610*/ OPC_RecordChild1, // #2 = $T
+/* 6611*/ OPC_RecordChild2, // #3 = $F
+/* 6612*/ OPC_CheckType, MVT::i32,
+/* 6614*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6616*/ OPC_EmitConvertToTarget, 1,
+/* 6618*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 6621*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6629*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), GPR32:{ *:[i32] }:$F)
+/* 6638*/ 0, /*End of Scope*/
+/* 6639*/ /*Scope*/ 38, /*->6678*/
+/* 6640*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 6642*/ OPC_MoveParent,
+/* 6643*/ OPC_MoveChild2,
+/* 6644*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 6646*/ OPC_MoveParent,
+/* 6647*/ OPC_CheckType, MVT::i32,
+/* 6649*/ OPC_MoveParent,
+/* 6650*/ OPC_RecordChild1, // #2 = $T
+/* 6651*/ OPC_RecordChild2, // #3 = $F
+/* 6652*/ OPC_CheckType, MVT::i32,
+/* 6654*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6656*/ OPC_EmitConvertToTarget, 1,
+/* 6658*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 6661*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6669*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$uimm16, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XORi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$uimm16)), GPR32:{ *:[i32] }:$F)
+/* 6678*/ /*Scope*/ 70, /*->6749*/
+/* 6679*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 6681*/ OPC_MoveParent,
+/* 6682*/ OPC_MoveChild2,
+/* 6683*/ OPC_Scope, 31, /*->6716*/ // 2 children in Scope
+/* 6685*/ OPC_CheckCondCode, ISD::SETGE,
+/* 6687*/ OPC_MoveParent,
+/* 6688*/ OPC_CheckType, MVT::i32,
+/* 6690*/ OPC_MoveParent,
+/* 6691*/ OPC_RecordChild1, // #2 = $T
+/* 6692*/ OPC_RecordChild2, // #3 = $F
+/* 6693*/ OPC_CheckType, MVT::i32,
+/* 6695*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6697*/ OPC_EmitConvertToTarget, 1,
+/* 6699*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 6707*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), GPR32:{ *:[i32] }:$F)
+/* 6716*/ /*Scope*/ 31, /*->6748*/
+/* 6717*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 6719*/ OPC_MoveParent,
+/* 6720*/ OPC_CheckType, MVT::i32,
+/* 6722*/ OPC_MoveParent,
+/* 6723*/ OPC_RecordChild1, // #2 = $T
+/* 6724*/ OPC_RecordChild2, // #3 = $F
+/* 6725*/ OPC_CheckType, MVT::i32,
+/* 6727*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6729*/ OPC_EmitConvertToTarget, 1,
+/* 6731*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 6739*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), GPR32:{ *:[i32] }:$F)
+/* 6748*/ 0, /*End of Scope*/
+/* 6749*/ /*Scope*/ 76, /*->6826*/
+/* 6750*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 6752*/ OPC_MoveParent,
+/* 6753*/ OPC_MoveChild2,
+/* 6754*/ OPC_Scope, 34, /*->6790*/ // 2 children in Scope
+/* 6756*/ OPC_CheckCondCode, ISD::SETGT,
+/* 6758*/ OPC_MoveParent,
+/* 6759*/ OPC_CheckType, MVT::i32,
+/* 6761*/ OPC_MoveParent,
+/* 6762*/ OPC_RecordChild1, // #2 = $T
+/* 6763*/ OPC_RecordChild2, // #3 = $F
+/* 6764*/ OPC_CheckType, MVT::i32,
+/* 6766*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6768*/ OPC_EmitConvertToTarget, 1,
+/* 6770*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 6773*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6781*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), GPR32:{ *:[i32] }:$F)
+/* 6790*/ /*Scope*/ 34, /*->6825*/
+/* 6791*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 6793*/ OPC_MoveParent,
+/* 6794*/ OPC_CheckType, MVT::i32,
+/* 6796*/ OPC_MoveParent,
+/* 6797*/ OPC_RecordChild1, // #2 = $T
+/* 6798*/ OPC_RecordChild2, // #3 = $F
+/* 6799*/ OPC_CheckType, MVT::i32,
+/* 6801*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6803*/ OPC_EmitConvertToTarget, 1,
+/* 6805*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 6808*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6816*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), GPR32:{ *:[i32] }:$F)
+/* 6825*/ 0, /*End of Scope*/
+/* 6826*/ /*Scope*/ 38, /*->6865*/
+/* 6827*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 6829*/ OPC_MoveParent,
+/* 6830*/ OPC_MoveChild2,
+/* 6831*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 6833*/ OPC_MoveParent,
+/* 6834*/ OPC_CheckType, MVT::i32,
+/* 6836*/ OPC_MoveParent,
+/* 6837*/ OPC_RecordChild1, // #2 = $T
+/* 6838*/ OPC_RecordChild2, // #3 = $F
+/* 6839*/ OPC_CheckType, MVT::i32,
+/* 6841*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 6843*/ OPC_EmitConvertToTarget, 1,
+/* 6845*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 6848*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 6856*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$uimm16, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XORi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$uimm16)), GPR32:{ *:[i32] }:$F)
+/* 6865*/ 0, /*End of Scope*/
+/* 6866*/ /*Scope*/ 30|128,1/*158*/, /*->7026*/
+/* 6868*/ OPC_MoveChild1,
+/* 6869*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 6872*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 6874*/ OPC_MoveParent,
+/* 6875*/ OPC_MoveChild2,
+/* 6876*/ OPC_Scope, 36, /*->6914*/ // 4 children in Scope
+/* 6878*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 6880*/ OPC_MoveParent,
+/* 6881*/ OPC_CheckType, MVT::i32,
+/* 6883*/ OPC_MoveParent,
+/* 6884*/ OPC_RecordChild1, // #1 = $t
+/* 6885*/ OPC_RecordChild2, // #2 = $f
+/* 6886*/ OPC_CheckType, MVT::i32,
+/* 6888*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 6890*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #3
+/* 6898*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 2, 0, // Results = #4
+/* 6906*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR:{ *:[i32] } (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
+/* 6914*/ /*Scope*/ 36, /*->6951*/
+/* 6915*/ OPC_CheckCondCode, ISD::SETNE,
+/* 6917*/ OPC_MoveParent,
+/* 6918*/ OPC_CheckType, MVT::i32,
+/* 6920*/ OPC_MoveParent,
+/* 6921*/ OPC_RecordChild1, // #1 = $t
+/* 6922*/ OPC_RecordChild2, // #2 = $f
+/* 6923*/ OPC_CheckType, MVT::i32,
+/* 6925*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 6927*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #3
+/* 6935*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 2, 0, // Results = #4
+/* 6943*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
+/* 6951*/ /*Scope*/ 36, /*->6988*/
+/* 6952*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 6954*/ OPC_MoveParent,
+/* 6955*/ OPC_CheckType, MVT::i32,
+/* 6957*/ OPC_MoveParent,
+/* 6958*/ OPC_RecordChild1, // #1 = $t
+/* 6959*/ OPC_RecordChild2, // #2 = $f
+/* 6960*/ OPC_CheckType, MVT::i32,
+/* 6962*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 6964*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #3
+/* 6972*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 0, // Results = #4
+/* 6980*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR_MM:{ *:[i32] } (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
+/* 6988*/ /*Scope*/ 36, /*->7025*/
+/* 6989*/ OPC_CheckCondCode, ISD::SETNE,
+/* 6991*/ OPC_MoveParent,
+/* 6992*/ OPC_CheckType, MVT::i32,
+/* 6994*/ OPC_MoveParent,
+/* 6995*/ OPC_RecordChild1, // #1 = $t
+/* 6996*/ OPC_RecordChild2, // #2 = $f
+/* 6997*/ OPC_CheckType, MVT::i32,
+/* 6999*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 7001*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #3
+/* 7009*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 0, // Results = #4
+/* 7017*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
+/* 7025*/ 0, /*End of Scope*/
+/* 7026*/ /*Scope*/ 19|128,2/*275*/, /*->7303*/
+/* 7028*/ OPC_RecordChild1, // #1 = $imm
+/* 7029*/ OPC_MoveChild1,
+/* 7030*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 7033*/ OPC_Scope, 4|128,1/*132*/, /*->7168*/ // 2 children in Scope
+/* 7036*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 7038*/ OPC_MoveParent,
+/* 7039*/ OPC_MoveChild2,
+/* 7040*/ OPC_Scope, 62, /*->7104*/ // 2 children in Scope
+/* 7042*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 7044*/ OPC_MoveParent,
+/* 7045*/ OPC_CheckType, MVT::i32,
+/* 7047*/ OPC_MoveParent,
+/* 7048*/ OPC_RecordChild1, // #2 = $t
+/* 7049*/ OPC_RecordChild2, // #3 = $f
+/* 7050*/ OPC_CheckType, MVT::i32,
+/* 7052*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 7054*/ OPC_EmitConvertToTarget, 1,
+/* 7056*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 7059*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7067*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 2, 6, // Results = #7
+/* 7075*/ OPC_EmitConvertToTarget, 1,
+/* 7077*/ OPC_EmitNodeXForm, 3, 8, // LO16
+/* 7080*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
+/* 7088*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 3, 10, // Results = #11
+/* 7096*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
+ MVT::i32, 2/*#Ops*/, 7, 11,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETEQ:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR:{ *:[i32] } (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$t, (XORi:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))), (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$f, (XORi:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))))
+/* 7104*/ /*Scope*/ 62, /*->7167*/
+/* 7105*/ OPC_CheckCondCode, ISD::SETNE,
+/* 7107*/ OPC_MoveParent,
+/* 7108*/ OPC_CheckType, MVT::i32,
+/* 7110*/ OPC_MoveParent,
+/* 7111*/ OPC_RecordChild1, // #2 = $t
+/* 7112*/ OPC_RecordChild2, // #3 = $f
+/* 7113*/ OPC_CheckType, MVT::i32,
+/* 7115*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 7117*/ OPC_EmitConvertToTarget, 1,
+/* 7119*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 7122*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7130*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 2, 6, // Results = #7
+/* 7138*/ OPC_EmitConvertToTarget, 1,
+/* 7140*/ OPC_EmitNodeXForm, 3, 8, // LO16
+/* 7143*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
+/* 7151*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 3, 10, // Results = #11
+/* 7159*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
+ MVT::i32, 2/*#Ops*/, 7, 11,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETNE:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, (XORi:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, (XORi:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))))
+/* 7167*/ 0, /*End of Scope*/
+/* 7168*/ /*Scope*/ 4|128,1/*132*/, /*->7302*/
+/* 7170*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 7172*/ OPC_MoveParent,
+/* 7173*/ OPC_MoveChild2,
+/* 7174*/ OPC_Scope, 62, /*->7238*/ // 2 children in Scope
+/* 7176*/ OPC_CheckCondCode, ISD::SETGT,
+/* 7178*/ OPC_MoveParent,
+/* 7179*/ OPC_CheckType, MVT::i32,
+/* 7181*/ OPC_MoveParent,
+/* 7182*/ OPC_RecordChild1, // #2 = $t
+/* 7183*/ OPC_RecordChild2, // #3 = $f
+/* 7184*/ OPC_CheckType, MVT::i32,
+/* 7186*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 7188*/ OPC_EmitConvertToTarget, 1,
+/* 7190*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 7193*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7201*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 2, 6, // Results = #7
+/* 7209*/ OPC_EmitConvertToTarget, 1,
+/* 7211*/ OPC_EmitNodeXForm, 2, 8, // Plus1
+/* 7214*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
+/* 7222*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 3, 10, // Results = #11
+/* 7230*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
+ MVT::i32, 2/*#Ops*/, 7, 11,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$imm, SETGT:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR:{ *:[i32] } (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$t, (SLTi:{ *:[i32] } i32:{ *:[i32] }:$cond, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$imm))), (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$f, (SLTi:{ *:[i32] } i32:{ *:[i32] }:$cond, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$imm))))
+/* 7238*/ /*Scope*/ 62, /*->7301*/
+/* 7239*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 7241*/ OPC_MoveParent,
+/* 7242*/ OPC_CheckType, MVT::i32,
+/* 7244*/ OPC_MoveParent,
+/* 7245*/ OPC_RecordChild1, // #2 = $t
+/* 7246*/ OPC_RecordChild2, // #3 = $f
+/* 7247*/ OPC_CheckType, MVT::i32,
+/* 7249*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 7251*/ OPC_EmitConvertToTarget, 1,
+/* 7253*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 7256*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7264*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 2, 6, // Results = #7
+/* 7272*/ OPC_EmitConvertToTarget, 1,
+/* 7274*/ OPC_EmitNodeXForm, 2, 8, // Plus1
+/* 7277*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
+/* 7285*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 3, 10, // Results = #11
+/* 7293*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
+ MVT::i32, 2/*#Ops*/, 7, 11,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$imm, SETUGT:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR:{ *:[i32] } (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$t, (SLTiu:{ *:[i32] } i32:{ *:[i32] }:$cond, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$imm))), (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$f, (SLTiu:{ *:[i32] } i32:{ *:[i32] }:$cond, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$imm))))
+/* 7301*/ 0, /*End of Scope*/
+/* 7302*/ 0, /*End of Scope*/
+/* 7303*/ /*Scope*/ 112, /*->7416*/
+/* 7304*/ OPC_MoveChild1,
+/* 7305*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 7308*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 7310*/ OPC_MoveParent,
+/* 7311*/ OPC_MoveChild2,
+/* 7312*/ OPC_Scope, 50, /*->7364*/ // 2 children in Scope
+/* 7314*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 7316*/ OPC_MoveParent,
+/* 7317*/ OPC_CheckType, MVT::i32,
+/* 7319*/ OPC_MoveParent,
+/* 7320*/ OPC_RecordChild1, // #1 = $t
+/* 7321*/ OPC_RecordChild2, // #2 = $f
+/* 7322*/ OPC_CheckType, MVT::i64,
+/* 7324*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 7326*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #3
+/* 7333*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 3, // Results = #4
+/* 7341*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #5
+/* 7348*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 5, // Results = #6
+/* 7356*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 4, 6,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
+/* 7364*/ /*Scope*/ 50, /*->7415*/
+/* 7365*/ OPC_CheckCondCode, ISD::SETNE,
+/* 7367*/ OPC_MoveParent,
+/* 7368*/ OPC_CheckType, MVT::i32,
+/* 7370*/ OPC_MoveParent,
+/* 7371*/ OPC_RecordChild1, // #1 = $t
+/* 7372*/ OPC_RecordChild2, // #2 = $f
+/* 7373*/ OPC_CheckType, MVT::i64,
+/* 7375*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 7377*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #3
+/* 7384*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 3, // Results = #4
+/* 7392*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #5
+/* 7399*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 5, // Results = #6
+/* 7407*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 4, 6,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
+/* 7415*/ 0, /*End of Scope*/
+/* 7416*/ /*Scope*/ 17|128,4/*529*/, /*->7947*/
+/* 7418*/ OPC_RecordChild1, // #1 = $imm
+/* 7419*/ OPC_MoveChild1,
+/* 7420*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 7423*/ OPC_Scope, 4|128,1/*132*/, /*->7558*/ // 5 children in Scope
+/* 7426*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 7428*/ OPC_MoveParent,
+/* 7429*/ OPC_MoveChild2,
+/* 7430*/ OPC_Scope, 62, /*->7494*/ // 2 children in Scope
+/* 7432*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 7434*/ OPC_MoveParent,
+/* 7435*/ OPC_CheckType, MVT::i32,
+/* 7437*/ OPC_MoveParent,
+/* 7438*/ OPC_RecordChild1, // #2 = $t
+/* 7439*/ OPC_RecordChild2, // #3 = $f
+/* 7440*/ OPC_CheckType, MVT::i32,
+/* 7442*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 7444*/ OPC_EmitConvertToTarget, 1,
+/* 7446*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 7449*/ OPC_EmitNode1, TARGET_VAL(Mips::XORI_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7457*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 6, // Results = #7
+/* 7465*/ OPC_EmitConvertToTarget, 1,
+/* 7467*/ OPC_EmitNodeXForm, 3, 8, // LO16
+/* 7470*/ OPC_EmitNode1, TARGET_VAL(Mips::XORI_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
+/* 7478*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 3, 10, // Results = #11
+/* 7486*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 7, 11,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETEQ:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR_MM:{ *:[i32] } (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, (XORI_MMR6:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))), (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, (XORI_MMR6:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))))
+/* 7494*/ /*Scope*/ 62, /*->7557*/
+/* 7495*/ OPC_CheckCondCode, ISD::SETNE,
+/* 7497*/ OPC_MoveParent,
+/* 7498*/ OPC_CheckType, MVT::i32,
+/* 7500*/ OPC_MoveParent,
+/* 7501*/ OPC_RecordChild1, // #2 = $t
+/* 7502*/ OPC_RecordChild2, // #3 = $f
+/* 7503*/ OPC_CheckType, MVT::i32,
+/* 7505*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 7507*/ OPC_EmitConvertToTarget, 1,
+/* 7509*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 7512*/ OPC_EmitNode1, TARGET_VAL(Mips::XORI_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7520*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 6, // Results = #7
+/* 7528*/ OPC_EmitConvertToTarget, 1,
+/* 7530*/ OPC_EmitNodeXForm, 3, 8, // LO16
+/* 7533*/ OPC_EmitNode1, TARGET_VAL(Mips::XORI_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
+/* 7541*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 3, 10, // Results = #11
+/* 7549*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 7, 11,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETNE:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, (XORI_MMR6:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, (XORI_MMR6:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))))
+/* 7557*/ 0, /*End of Scope*/
+/* 7558*/ /*Scope*/ 4|128,1/*132*/, /*->7692*/
+/* 7560*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 7562*/ OPC_MoveParent,
+/* 7563*/ OPC_MoveChild2,
+/* 7564*/ OPC_Scope, 62, /*->7628*/ // 2 children in Scope
+/* 7566*/ OPC_CheckCondCode, ISD::SETGT,
+/* 7568*/ OPC_MoveParent,
+/* 7569*/ OPC_CheckType, MVT::i32,
+/* 7571*/ OPC_MoveParent,
+/* 7572*/ OPC_RecordChild1, // #2 = $t
+/* 7573*/ OPC_RecordChild2, // #3 = $f
+/* 7574*/ OPC_CheckType, MVT::i32,
+/* 7576*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 7578*/ OPC_EmitConvertToTarget, 1,
+/* 7580*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 7583*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7591*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 6, // Results = #7
+/* 7599*/ OPC_EmitConvertToTarget, 1,
+/* 7601*/ OPC_EmitNodeXForm, 2, 8, // Plus1
+/* 7604*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
+/* 7612*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 3, 10, // Results = #11
+/* 7620*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 7, 11,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$imm, SETGT:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR_MM:{ *:[i32] } (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, (SLTi_MM:{ *:[i32] } i32:{ *:[i32] }:$cond, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$imm))), (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, (SLTi_MM:{ *:[i32] } i32:{ *:[i32] }:$cond, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$imm))))
+/* 7628*/ /*Scope*/ 62, /*->7691*/
+/* 7629*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 7631*/ OPC_MoveParent,
+/* 7632*/ OPC_CheckType, MVT::i32,
+/* 7634*/ OPC_MoveParent,
+/* 7635*/ OPC_RecordChild1, // #2 = $t
+/* 7636*/ OPC_RecordChild2, // #3 = $f
+/* 7637*/ OPC_CheckType, MVT::i32,
+/* 7639*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 7641*/ OPC_EmitConvertToTarget, 1,
+/* 7643*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 7646*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7654*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 6, // Results = #7
+/* 7662*/ OPC_EmitConvertToTarget, 1,
+/* 7664*/ OPC_EmitNodeXForm, 2, 8, // Plus1
+/* 7667*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 9, // Results = #10
+/* 7675*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 3, 10, // Results = #11
+/* 7683*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 7, 11,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$imm, SETUGT:{ *:[Other] }), i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 10
+ // Dst: (OR_MM:{ *:[i32] } (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, (SLTiu_MM:{ *:[i32] } i32:{ *:[i32] }:$cond, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$imm))), (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, (SLTiu_MM:{ *:[i32] } i32:{ *:[i32] }:$cond, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$imm))))
+/* 7691*/ 0, /*End of Scope*/
+/* 7692*/ /*Scope*/ 32|128,1/*160*/, /*->7854*/
+/* 7694*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 7696*/ OPC_MoveParent,
+/* 7697*/ OPC_MoveChild2,
+/* 7698*/ OPC_Scope, 76, /*->7776*/ // 2 children in Scope
+/* 7700*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 7702*/ OPC_MoveParent,
+/* 7703*/ OPC_CheckType, MVT::i32,
+/* 7705*/ OPC_MoveParent,
+/* 7706*/ OPC_RecordChild1, // #2 = $t
+/* 7707*/ OPC_RecordChild2, // #3 = $f
+/* 7708*/ OPC_CheckType, MVT::i64,
+/* 7710*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 7712*/ OPC_EmitConvertToTarget, 1,
+/* 7714*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 7717*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7725*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 6, // Results = #7
+/* 7732*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 7, // Results = #8
+/* 7740*/ OPC_EmitConvertToTarget, 1,
+/* 7742*/ OPC_EmitNodeXForm, 3, 9, // LO16
+/* 7745*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 10, // Results = #11
+/* 7753*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 11, // Results = #12
+/* 7760*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 12, // Results = #13
+/* 7768*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 8, 13,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETEQ:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } (XORi:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm)))), (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } (XORi:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm)))))
+/* 7776*/ /*Scope*/ 76, /*->7853*/
+/* 7777*/ OPC_CheckCondCode, ISD::SETNE,
+/* 7779*/ OPC_MoveParent,
+/* 7780*/ OPC_CheckType, MVT::i32,
+/* 7782*/ OPC_MoveParent,
+/* 7783*/ OPC_RecordChild1, // #2 = $t
+/* 7784*/ OPC_RecordChild2, // #3 = $f
+/* 7785*/ OPC_CheckType, MVT::i64,
+/* 7787*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 7789*/ OPC_EmitConvertToTarget, 1,
+/* 7791*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 7794*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 7802*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 6, // Results = #7
+/* 7809*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 7, // Results = #8
+/* 7817*/ OPC_EmitConvertToTarget, 1,
+/* 7819*/ OPC_EmitNodeXForm, 3, 9, // LO16
+/* 7822*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 10, // Results = #11
+/* 7830*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 11, // Results = #12
+/* 7837*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 12, // Results = #13
+/* 7845*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 8, 13,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm, SETNE:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } (XORi:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm)))), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } (XORi:{ *:[i32] } i32:{ *:[i32] }:$cond, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm)))))
+/* 7853*/ 0, /*End of Scope*/
+/* 7854*/ /*Scope*/ 28, /*->7883*/
+/* 7855*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 7857*/ OPC_MoveParent,
+/* 7858*/ OPC_MoveChild2,
+/* 7859*/ OPC_CheckCondCode, ISD::SETLT,
+/* 7861*/ OPC_MoveParent,
+/* 7862*/ OPC_CheckType, MVT::i32,
+/* 7864*/ OPC_MoveParent,
+/* 7865*/ OPC_RecordChild1, // #2 = $x
+/* 7866*/ OPC_RecordChild2, // #3 = $y
+/* 7867*/ OPC_CheckType, MVT::i32,
+/* 7869*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 7871*/ OPC_EmitConvertToTarget, 1,
+/* 7873*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBtneZSlti), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 0, 4,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$b, SETLT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 10
+ // Dst: (SelTBtneZSlti:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$b)
+/* 7883*/ /*Scope*/ 62, /*->7946*/
+/* 7884*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 7886*/ OPC_MoveParent,
+/* 7887*/ OPC_MoveChild2,
+/* 7888*/ OPC_Scope, 27, /*->7917*/ // 2 children in Scope
+/* 7890*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 7892*/ OPC_MoveParent,
+/* 7893*/ OPC_CheckType, MVT::i32,
+/* 7895*/ OPC_MoveParent,
+/* 7896*/ OPC_RecordChild1, // #2 = $x
+/* 7897*/ OPC_RecordChild2, // #3 = $y
+/* 7898*/ OPC_CheckType, MVT::i32,
+/* 7900*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 7902*/ OPC_EmitConvertToTarget, 1,
+/* 7904*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 7907*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBteqZCmpi), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 0, 5,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$k, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 10
+ // Dst: (SelTBteqZCmpi:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$k))
+/* 7917*/ /*Scope*/ 27, /*->7945*/
+/* 7918*/ OPC_CheckCondCode, ISD::SETNE,
+/* 7920*/ OPC_MoveParent,
+/* 7921*/ OPC_CheckType, MVT::i32,
+/* 7923*/ OPC_MoveParent,
+/* 7924*/ OPC_RecordChild1, // #2 = $x
+/* 7925*/ OPC_RecordChild2, // #3 = $y
+/* 7926*/ OPC_CheckType, MVT::i32,
+/* 7928*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 7930*/ OPC_EmitConvertToTarget, 1,
+/* 7932*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 7935*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBtneZCmpi), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 0, 5,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$k, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 10
+ // Dst: (SelTBtneZCmpi:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$k))
+/* 7945*/ 0, /*End of Scope*/
+/* 7946*/ 0, /*End of Scope*/
+/* 7947*/ 0, /*End of Scope*/
+/* 7948*/ /*Scope*/ 88|128,7/*984*/, /*->8934*/
+/* 7950*/ OPC_CheckChild0Type, MVT::i64,
+/* 7952*/ OPC_Scope, 118, /*->8072*/ // 5 children in Scope
+/* 7954*/ OPC_MoveChild1,
+/* 7955*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 7958*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 7960*/ OPC_MoveParent,
+/* 7961*/ OPC_MoveChild2,
+/* 7962*/ OPC_Scope, 26, /*->7990*/ // 4 children in Scope
+/* 7964*/ OPC_CheckCondCode, ISD::SETNE,
+/* 7966*/ OPC_MoveParent,
+/* 7967*/ OPC_CheckType, MVT::i32,
+/* 7969*/ OPC_MoveParent,
+/* 7970*/ OPC_RecordChild1, // #1 = $t
+/* 7971*/ OPC_MoveChild2,
+/* 7972*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 7975*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 7977*/ OPC_MoveParent,
+/* 7978*/ OPC_CheckType, MVT::i64,
+/* 7980*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 7982*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), i64:{ *:[i64] }:$t, (imm:{ *:[i64] })<<P:Predicate_immz>>) - Complexity = 14
+ // Dst: (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond)
+/* 7990*/ /*Scope*/ 26, /*->8017*/
+/* 7991*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 7993*/ OPC_MoveParent,
+/* 7994*/ OPC_CheckType, MVT::i32,
+/* 7996*/ OPC_MoveParent,
+/* 7997*/ OPC_RecordChild1, // #1 = $t
+/* 7998*/ OPC_MoveChild2,
+/* 7999*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8002*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 8004*/ OPC_MoveParent,
+/* 8005*/ OPC_CheckType, MVT::i64,
+/* 8007*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8009*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), i64:{ *:[i64] }:$t, (imm:{ *:[i64] })<<P:Predicate_immz>>) - Complexity = 14
+ // Dst: (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond)
+/* 8017*/ /*Scope*/ 26, /*->8044*/
+/* 8018*/ OPC_CheckCondCode, ISD::SETNE,
+/* 8020*/ OPC_MoveParent,
+/* 8021*/ OPC_CheckType, MVT::i32,
+/* 8023*/ OPC_MoveParent,
+/* 8024*/ OPC_MoveChild1,
+/* 8025*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8028*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 8030*/ OPC_MoveParent,
+/* 8031*/ OPC_RecordChild2, // #1 = $f
+/* 8032*/ OPC_CheckType, MVT::i64,
+/* 8034*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8036*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_immz>>, i64:{ *:[i64] }:$f) - Complexity = 14
+ // Dst: (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond)
+/* 8044*/ /*Scope*/ 26, /*->8071*/
+/* 8045*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 8047*/ OPC_MoveParent,
+/* 8048*/ OPC_CheckType, MVT::i32,
+/* 8050*/ OPC_MoveParent,
+/* 8051*/ OPC_MoveChild1,
+/* 8052*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8055*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 8057*/ OPC_MoveParent,
+/* 8058*/ OPC_RecordChild2, // #1 = $f
+/* 8059*/ OPC_CheckType, MVT::i64,
+/* 8061*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8063*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_immz>>, i64:{ *:[i64] }:$f) - Complexity = 14
+ // Dst: (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond)
+/* 8071*/ 0, /*End of Scope*/
+/* 8072*/ /*Scope*/ 79, /*->8152*/
+/* 8073*/ OPC_CheckChild1Integer, 0,
+/* 8075*/ OPC_MoveChild2,
+/* 8076*/ OPC_Scope, 36, /*->8114*/ // 2 children in Scope
+/* 8078*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 8080*/ OPC_MoveParent,
+/* 8081*/ OPC_CheckType, MVT::i32,
+/* 8083*/ OPC_MoveParent,
+/* 8084*/ OPC_RecordChild1, // #1 = $T
+/* 8085*/ OPC_RecordChild2, // #2 = $F
+/* 8086*/ OPC_SwitchType /*2 cases */, 11, MVT::i32,// ->8100
+/* 8089*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8091*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_I), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
+/* 8100*/ /*SwitchType*/ 11, MVT::i64,// ->8113
+/* 8102*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8104*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_I64), 0,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
+/* 8113*/ 0, // EndSwitchType
+/* 8114*/ /*Scope*/ 36, /*->8151*/
+/* 8115*/ OPC_CheckCondCode, ISD::SETNE,
+/* 8117*/ OPC_MoveParent,
+/* 8118*/ OPC_CheckType, MVT::i32,
+/* 8120*/ OPC_MoveParent,
+/* 8121*/ OPC_RecordChild1, // #1 = $T
+/* 8122*/ OPC_RecordChild2, // #2 = $F
+/* 8123*/ OPC_SwitchType /*2 cases */, 11, MVT::i32,// ->8137
+/* 8126*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8128*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_I), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 11
+ // Dst: (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
+/* 8137*/ /*SwitchType*/ 11, MVT::i64,// ->8150
+/* 8139*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8141*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_I64), 0,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 11
+ // Dst: (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
+/* 8150*/ 0, // EndSwitchType
+/* 8151*/ 0, /*End of Scope*/
+/* 8152*/ /*Scope*/ 114|128,2/*370*/, /*->8524*/
+/* 8154*/ OPC_RecordChild1, // #1 = $rhs
+/* 8155*/ OPC_MoveChild1,
+/* 8156*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8159*/ OPC_Scope, 70, /*->8231*/ // 5 children in Scope
+/* 8161*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 8163*/ OPC_MoveParent,
+/* 8164*/ OPC_MoveChild2,
+/* 8165*/ OPC_Scope, 31, /*->8198*/ // 2 children in Scope
+/* 8167*/ OPC_CheckCondCode, ISD::SETGE,
+/* 8169*/ OPC_MoveParent,
+/* 8170*/ OPC_CheckType, MVT::i32,
+/* 8172*/ OPC_MoveParent,
+/* 8173*/ OPC_RecordChild1, // #2 = $T
+/* 8174*/ OPC_RecordChild2, // #3 = $F
+/* 8175*/ OPC_CheckType, MVT::i32,
+/* 8177*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8179*/ OPC_EmitConvertToTarget, 1,
+/* 8181*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 8189*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs), GPR32:{ *:[i32] }:$F)
+/* 8198*/ /*Scope*/ 31, /*->8230*/
+/* 8199*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 8201*/ OPC_MoveParent,
+/* 8202*/ OPC_CheckType, MVT::i32,
+/* 8204*/ OPC_MoveParent,
+/* 8205*/ OPC_RecordChild1, // #2 = $T
+/* 8206*/ OPC_RecordChild2, // #3 = $F
+/* 8207*/ OPC_CheckType, MVT::i32,
+/* 8209*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8211*/ OPC_EmitConvertToTarget, 1,
+/* 8213*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 8221*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lh, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lh, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rh), GPR32:{ *:[i32] }:$F)
+/* 8230*/ 0, /*End of Scope*/
+/* 8231*/ /*Scope*/ 76, /*->8308*/
+/* 8232*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 8234*/ OPC_MoveParent,
+/* 8235*/ OPC_MoveChild2,
+/* 8236*/ OPC_Scope, 34, /*->8272*/ // 2 children in Scope
+/* 8238*/ OPC_CheckCondCode, ISD::SETGT,
+/* 8240*/ OPC_MoveParent,
+/* 8241*/ OPC_CheckType, MVT::i32,
+/* 8243*/ OPC_MoveParent,
+/* 8244*/ OPC_RecordChild1, // #2 = $T
+/* 8245*/ OPC_RecordChild2, // #3 = $F
+/* 8246*/ OPC_CheckType, MVT::i32,
+/* 8248*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8250*/ OPC_EmitConvertToTarget, 1,
+/* 8252*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 8255*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 8263*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), GPR32:{ *:[i32] }:$F)
+/* 8272*/ /*Scope*/ 34, /*->8307*/
+/* 8273*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 8275*/ OPC_MoveParent,
+/* 8276*/ OPC_CheckType, MVT::i32,
+/* 8278*/ OPC_MoveParent,
+/* 8279*/ OPC_RecordChild1, // #2 = $T
+/* 8280*/ OPC_RecordChild2, // #3 = $F
+/* 8281*/ OPC_CheckType, MVT::i32,
+/* 8283*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8285*/ OPC_EmitConvertToTarget, 1,
+/* 8287*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 8290*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 8298*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), GPR32:{ *:[i32] }:$F)
+/* 8307*/ 0, /*End of Scope*/
+/* 8308*/ /*Scope*/ 70, /*->8379*/
+/* 8309*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 8311*/ OPC_MoveParent,
+/* 8312*/ OPC_MoveChild2,
+/* 8313*/ OPC_Scope, 31, /*->8346*/ // 2 children in Scope
+/* 8315*/ OPC_CheckCondCode, ISD::SETGE,
+/* 8317*/ OPC_MoveParent,
+/* 8318*/ OPC_CheckType, MVT::i32,
+/* 8320*/ OPC_MoveParent,
+/* 8321*/ OPC_RecordChild1, // #2 = $T
+/* 8322*/ OPC_RecordChild2, // #3 = $F
+/* 8323*/ OPC_CheckType, MVT::i64,
+/* 8325*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8327*/ OPC_EmitConvertToTarget, 1,
+/* 8329*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 8337*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs), GPR64:{ *:[i64] }:$F)
+/* 8346*/ /*Scope*/ 31, /*->8378*/
+/* 8347*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 8349*/ OPC_MoveParent,
+/* 8350*/ OPC_CheckType, MVT::i32,
+/* 8352*/ OPC_MoveParent,
+/* 8353*/ OPC_RecordChild1, // #2 = $T
+/* 8354*/ OPC_RecordChild2, // #3 = $F
+/* 8355*/ OPC_CheckType, MVT::i64,
+/* 8357*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8359*/ OPC_EmitConvertToTarget, 1,
+/* 8361*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 8369*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lh, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lh, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rh), GPR64:{ *:[i64] }:$F)
+/* 8378*/ 0, /*End of Scope*/
+/* 8379*/ /*Scope*/ 76, /*->8456*/
+/* 8380*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 8382*/ OPC_MoveParent,
+/* 8383*/ OPC_MoveChild2,
+/* 8384*/ OPC_Scope, 34, /*->8420*/ // 2 children in Scope
+/* 8386*/ OPC_CheckCondCode, ISD::SETGT,
+/* 8388*/ OPC_MoveParent,
+/* 8389*/ OPC_CheckType, MVT::i32,
+/* 8391*/ OPC_MoveParent,
+/* 8392*/ OPC_RecordChild1, // #2 = $T
+/* 8393*/ OPC_RecordChild2, // #3 = $F
+/* 8394*/ OPC_CheckType, MVT::i64,
+/* 8396*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8398*/ OPC_EmitConvertToTarget, 1,
+/* 8400*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 8403*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 8411*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), GPR64:{ *:[i64] }:$F)
+/* 8420*/ /*Scope*/ 34, /*->8455*/
+/* 8421*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 8423*/ OPC_MoveParent,
+/* 8424*/ OPC_CheckType, MVT::i32,
+/* 8426*/ OPC_MoveParent,
+/* 8427*/ OPC_RecordChild1, // #2 = $T
+/* 8428*/ OPC_RecordChild2, // #3 = $F
+/* 8429*/ OPC_CheckType, MVT::i64,
+/* 8431*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8433*/ OPC_EmitConvertToTarget, 1,
+/* 8435*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 8438*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 8446*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), GPR64:{ *:[i64] }:$F)
+/* 8455*/ 0, /*End of Scope*/
+/* 8456*/ /*Scope*/ 66, /*->8523*/
+/* 8457*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 8459*/ OPC_MoveParent,
+/* 8460*/ OPC_MoveChild2,
+/* 8461*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 8463*/ OPC_MoveParent,
+/* 8464*/ OPC_CheckType, MVT::i32,
+/* 8466*/ OPC_MoveParent,
+/* 8467*/ OPC_RecordChild1, // #2 = $T
+/* 8468*/ OPC_RecordChild2, // #3 = $F
+/* 8469*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->8496
+/* 8472*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8474*/ OPC_EmitConvertToTarget, 1,
+/* 8476*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 8479*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 5, // Results = #6
+/* 8487*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immZExt16>><<X:LO16>>:$uimm16, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XORi64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, (LO16:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_immZExt16>>:$uimm16)), GPR32:{ *:[i32] }:$F)
+/* 8496*/ /*SwitchType*/ 24, MVT::i64,// ->8522
+/* 8498*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 8500*/ OPC_EmitConvertToTarget, 1,
+/* 8502*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 8505*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 5, // Results = #6
+/* 8513*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immZExt16>><<X:LO16>>:$uimm16, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XORi64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, (LO16:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_immZExt16>>:$uimm16)), GPR64:{ *:[i64] }:$F)
+/* 8522*/ 0, // EndSwitchType
+/* 8523*/ 0, /*End of Scope*/
+/* 8524*/ /*Scope*/ 84, /*->8609*/
+/* 8525*/ OPC_MoveChild1,
+/* 8526*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8529*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 8531*/ OPC_MoveParent,
+/* 8532*/ OPC_MoveChild2,
+/* 8533*/ OPC_Scope, 36, /*->8571*/ // 2 children in Scope
+/* 8535*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 8537*/ OPC_MoveParent,
+/* 8538*/ OPC_CheckType, MVT::i32,
+/* 8540*/ OPC_MoveParent,
+/* 8541*/ OPC_RecordChild1, // #1 = $t
+/* 8542*/ OPC_RecordChild2, // #2 = $f
+/* 8543*/ OPC_CheckType, MVT::i64,
+/* 8545*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8547*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0, // Results = #3
+/* 8555*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 0, // Results = #4
+/* 8563*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immz>>, SETEQ:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
+/* 8571*/ /*Scope*/ 36, /*->8608*/
+/* 8572*/ OPC_CheckCondCode, ISD::SETNE,
+/* 8574*/ OPC_MoveParent,
+/* 8575*/ OPC_CheckType, MVT::i32,
+/* 8577*/ OPC_MoveParent,
+/* 8578*/ OPC_RecordChild1, // #1 = $t
+/* 8579*/ OPC_RecordChild2, // #2 = $f
+/* 8580*/ OPC_CheckType, MVT::i64,
+/* 8582*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8584*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0, // Results = #3
+/* 8592*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 0, // Results = #4
+/* 8600*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immz>>, SETNE:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
+/* 8608*/ 0, /*End of Scope*/
+/* 8609*/ /*Scope*/ 66|128,2/*322*/, /*->8933*/
+/* 8611*/ OPC_RecordChild1, // #1 = $imm
+/* 8612*/ OPC_MoveChild1,
+/* 8613*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8616*/ OPC_Scope, 120, /*->8738*/ // 2 children in Scope
+/* 8618*/ OPC_CheckPredicate, 23, // Predicate_immZExt16_64
+/* 8620*/ OPC_MoveParent,
+/* 8621*/ OPC_MoveChild2,
+/* 8622*/ OPC_Scope, 56, /*->8680*/ // 2 children in Scope
+/* 8624*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 8626*/ OPC_MoveParent,
+/* 8627*/ OPC_CheckType, MVT::i32,
+/* 8629*/ OPC_MoveParent,
+/* 8630*/ OPC_RecordChild1, // #2 = $t
+/* 8631*/ OPC_RecordChild2, // #3 = $f
+/* 8632*/ OPC_CheckType, MVT::i64,
+/* 8634*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8636*/ OPC_EmitConvertToTarget, 1,
+/* 8638*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 4, // Results = #5
+/* 8646*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 5, // Results = #6
+/* 8654*/ OPC_EmitConvertToTarget, 1,
+/* 8656*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 7, // Results = #8
+/* 8664*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 8, // Results = #9
+/* 8672*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 6, 9,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immZExt16_64>>:$imm, SETEQ:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (XORi64:{ *:[i64] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immZExt16_64>>:$imm)), (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (XORi64:{ *:[i64] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immZExt16_64>>:$imm)))
+/* 8680*/ /*Scope*/ 56, /*->8737*/
+/* 8681*/ OPC_CheckCondCode, ISD::SETNE,
+/* 8683*/ OPC_MoveParent,
+/* 8684*/ OPC_CheckType, MVT::i32,
+/* 8686*/ OPC_MoveParent,
+/* 8687*/ OPC_RecordChild1, // #2 = $t
+/* 8688*/ OPC_RecordChild2, // #3 = $f
+/* 8689*/ OPC_CheckType, MVT::i64,
+/* 8691*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8693*/ OPC_EmitConvertToTarget, 1,
+/* 8695*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 4, // Results = #5
+/* 8703*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 5, // Results = #6
+/* 8711*/ OPC_EmitConvertToTarget, 1,
+/* 8713*/ OPC_EmitNode1, TARGET_VAL(Mips::XORi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 7, // Results = #8
+/* 8721*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 8, // Results = #9
+/* 8729*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 6, 9,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immZExt16_64>>:$imm, SETNE:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (XORi64:{ *:[i64] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immZExt16_64>>:$imm)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (XORi64:{ *:[i64] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immZExt16_64>>:$imm)))
+/* 8737*/ 0, /*End of Scope*/
+/* 8738*/ /*Scope*/ 64|128,1/*192*/, /*->8932*/
+/* 8740*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 8742*/ OPC_MoveParent,
+/* 8743*/ OPC_MoveChild2,
+/* 8744*/ OPC_Scope, 92, /*->8838*/ // 2 children in Scope
+/* 8746*/ OPC_CheckCondCode, ISD::SETGT,
+/* 8748*/ OPC_MoveParent,
+/* 8749*/ OPC_CheckType, MVT::i32,
+/* 8751*/ OPC_MoveParent,
+/* 8752*/ OPC_RecordChild1, // #2 = $t
+/* 8753*/ OPC_RecordChild2, // #3 = $f
+/* 8754*/ OPC_CheckType, MVT::i64,
+/* 8756*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8758*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8761*/ OPC_EmitConvertToTarget, 1,
+/* 8763*/ OPC_EmitNodeXForm, 2, 5, // Plus1
+/* 8766*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 6, // Results = #7
+/* 8774*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 8777*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::SUBREG_TO_REG), 0,
+ MVT::i64, 3/*#Ops*/, 4, 7, 8, // Results = #9
+/* 8786*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 9, // Results = #10
+/* 8794*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8797*/ OPC_EmitConvertToTarget, 1,
+/* 8799*/ OPC_EmitNodeXForm, 2, 12, // Plus1
+/* 8802*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 13, // Results = #14
+/* 8810*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 8813*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::SUBREG_TO_REG), 0,
+ MVT::i64, 3/*#Ops*/, 11, 14, 15, // Results = #16
+/* 8822*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 16, // Results = #17
+/* 8830*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 10, 17,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$imm, SETGT:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (SLTi64:{ *:[i32] } i64:{ *:[i64] }:$cond, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$imm)), sub_32:{ *:[i32] })), (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (SLTi64:{ *:[i32] } i64:{ *:[i64] }:$cond, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$imm)), sub_32:{ *:[i32] })))
+/* 8838*/ /*Scope*/ 92, /*->8931*/
+/* 8839*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 8841*/ OPC_MoveParent,
+/* 8842*/ OPC_CheckType, MVT::i32,
+/* 8844*/ OPC_MoveParent,
+/* 8845*/ OPC_RecordChild1, // #2 = $t
+/* 8846*/ OPC_RecordChild2, // #3 = $f
+/* 8847*/ OPC_CheckType, MVT::i64,
+/* 8849*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 8851*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8854*/ OPC_EmitConvertToTarget, 1,
+/* 8856*/ OPC_EmitNodeXForm, 2, 5, // Plus1
+/* 8859*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 6, // Results = #7
+/* 8867*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 8870*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::SUBREG_TO_REG), 0,
+ MVT::i64, 3/*#Ops*/, 4, 7, 8, // Results = #9
+/* 8879*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 9, // Results = #10
+/* 8887*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8890*/ OPC_EmitConvertToTarget, 1,
+/* 8892*/ OPC_EmitNodeXForm, 2, 12, // Plus1
+/* 8895*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 13, // Results = #14
+/* 8903*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 8906*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::SUBREG_TO_REG), 0,
+ MVT::i64, 3/*#Ops*/, 11, 14, 15, // Results = #16
+/* 8915*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 16, // Results = #17
+/* 8923*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 10, 17,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } i64:{ *:[i64] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$imm, SETUGT:{ *:[Other] }), i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 10
+ // Dst: (OR64:{ *:[i64] } (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (SLTiu64:{ *:[i32] } i64:{ *:[i64] }:$cond, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$imm)), sub_32:{ *:[i32] })), (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (SLTiu64:{ *:[i32] } i64:{ *:[i64] }:$cond, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$imm)), sub_32:{ *:[i32] })))
+/* 8931*/ 0, /*End of Scope*/
+/* 8932*/ 0, /*End of Scope*/
+/* 8933*/ 0, /*End of Scope*/
+/* 8934*/ 0, /*End of Scope*/
+/* 8935*/ /*Scope*/ 17|128,1/*145*/, /*->9082*/
+/* 8937*/ OPC_RecordChild0, // #0 = $cond
+/* 8938*/ OPC_CheckChild0Type, MVT::i32,
+/* 8940*/ OPC_Scope, 20, /*->8962*/ // 6 children in Scope
+/* 8942*/ OPC_RecordChild1, // #1 = $t
+/* 8943*/ OPC_MoveChild2,
+/* 8944*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8947*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 8949*/ OPC_MoveParent,
+/* 8950*/ OPC_CheckType, MVT::i32,
+/* 8952*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 8954*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, (imm:{ *:[i32] })<<P:Predicate_immz>>) - Complexity = 7
+ // Dst: (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond)
+/* 8962*/ /*Scope*/ 20, /*->8983*/
+/* 8963*/ OPC_MoveChild1,
+/* 8964*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8967*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 8969*/ OPC_MoveParent,
+/* 8970*/ OPC_RecordChild2, // #1 = $f
+/* 8971*/ OPC_CheckType, MVT::i32,
+/* 8973*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 8975*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, i32:{ *:[i32] }:$f) - Complexity = 7
+ // Dst: (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)
+/* 8983*/ /*Scope*/ 20, /*->9004*/
+/* 8984*/ OPC_RecordChild1, // #1 = $t
+/* 8985*/ OPC_MoveChild2,
+/* 8986*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8989*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 8991*/ OPC_MoveParent,
+/* 8992*/ OPC_CheckType, MVT::i32,
+/* 8994*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 8996*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, (imm:{ *:[i32] })<<P:Predicate_immz>>) - Complexity = 7
+ // Dst: (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond)
+/* 9004*/ /*Scope*/ 20, /*->9025*/
+/* 9005*/ OPC_MoveChild1,
+/* 9006*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 9009*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 9011*/ OPC_MoveParent,
+/* 9012*/ OPC_RecordChild2, // #1 = $f
+/* 9013*/ OPC_CheckType, MVT::i32,
+/* 9015*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 9017*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (select:{ *:[i32] } i32:{ *:[i32] }:$cond, (imm:{ *:[i32] })<<P:Predicate_immz>>, i32:{ *:[i32] }:$f) - Complexity = 7
+ // Dst: (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond)
+/* 9025*/ /*Scope*/ 27, /*->9053*/
+/* 9026*/ OPC_RecordChild1, // #1 = $t
+/* 9027*/ OPC_MoveChild2,
+/* 9028*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 9031*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 9033*/ OPC_MoveParent,
+/* 9034*/ OPC_CheckType, MVT::i64,
+/* 9036*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 9038*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #2
+/* 9045*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, (imm:{ *:[i64] })<<P:Predicate_immz>>) - Complexity = 7
+ // Dst: (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))
+/* 9053*/ /*Scope*/ 27, /*->9081*/
+/* 9054*/ OPC_MoveChild1,
+/* 9055*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 9058*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 9060*/ OPC_MoveParent,
+/* 9061*/ OPC_RecordChild2, // #1 = $f
+/* 9062*/ OPC_CheckType, MVT::i64,
+/* 9064*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 9066*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #2
+/* 9073*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (select:{ *:[i64] } i32:{ *:[i32] }:$cond, (imm:{ *:[i64] })<<P:Predicate_immz>>, i64:{ *:[i64] }:$f) - Complexity = 7
+ // Dst: (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond))
+/* 9081*/ 0, /*End of Scope*/
+/* 9082*/ /*Scope*/ 114|128,9/*1266*/, /*->10350*/
+/* 9084*/ OPC_MoveChild0,
+/* 9085*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
+/* 9088*/ OPC_RecordChild0, // #0 = $lhs
+/* 9089*/ OPC_Scope, 7|128,7/*903*/, /*->9995*/ // 2 children in Scope
+/* 9092*/ OPC_CheckChild0Type, MVT::i32,
+/* 9094*/ OPC_RecordChild1, // #1 = $rhs
+/* 9095*/ OPC_MoveChild2,
+/* 9096*/ OPC_Scope, 29, /*->9127*/ // 31 children in Scope
+/* 9098*/ OPC_CheckCondCode, ISD::SETGE,
+/* 9100*/ OPC_MoveParent,
+/* 9101*/ OPC_CheckType, MVT::i32,
+/* 9103*/ OPC_MoveParent,
+/* 9104*/ OPC_RecordChild1, // #2 = $T
+/* 9105*/ OPC_RecordChild2, // #3 = $F
+/* 9106*/ OPC_CheckType, MVT::i32,
+/* 9108*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9110*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9118*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9127*/ /*Scope*/ 29, /*->9157*/
+/* 9128*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 9130*/ OPC_MoveParent,
+/* 9131*/ OPC_CheckType, MVT::i32,
+/* 9133*/ OPC_MoveParent,
+/* 9134*/ OPC_RecordChild1, // #2 = $T
+/* 9135*/ OPC_RecordChild2, // #3 = $F
+/* 9136*/ OPC_CheckType, MVT::i32,
+/* 9138*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9140*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9148*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9157*/ /*Scope*/ 29, /*->9187*/
+/* 9158*/ OPC_CheckCondCode, ISD::SETLE,
+/* 9160*/ OPC_MoveParent,
+/* 9161*/ OPC_CheckType, MVT::i32,
+/* 9163*/ OPC_MoveParent,
+/* 9164*/ OPC_RecordChild1, // #2 = $T
+/* 9165*/ OPC_RecordChild2, // #3 = $F
+/* 9166*/ OPC_CheckType, MVT::i32,
+/* 9168*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9170*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 9178*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
+/* 9187*/ /*Scope*/ 29, /*->9217*/
+/* 9188*/ OPC_CheckCondCode, ISD::SETULE,
+/* 9190*/ OPC_MoveParent,
+/* 9191*/ OPC_CheckType, MVT::i32,
+/* 9193*/ OPC_MoveParent,
+/* 9194*/ OPC_RecordChild1, // #2 = $T
+/* 9195*/ OPC_RecordChild2, // #3 = $F
+/* 9196*/ OPC_CheckType, MVT::i32,
+/* 9198*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9200*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 9208*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
+/* 9217*/ /*Scope*/ 29, /*->9247*/
+/* 9218*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 9220*/ OPC_MoveParent,
+/* 9221*/ OPC_CheckType, MVT::i32,
+/* 9223*/ OPC_MoveParent,
+/* 9224*/ OPC_RecordChild1, // #2 = $T
+/* 9225*/ OPC_RecordChild2, // #3 = $F
+/* 9226*/ OPC_CheckType, MVT::i32,
+/* 9228*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9230*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9238*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9247*/ /*Scope*/ 29, /*->9277*/
+/* 9248*/ OPC_CheckCondCode, ISD::SETGE,
+/* 9250*/ OPC_MoveParent,
+/* 9251*/ OPC_CheckType, MVT::i32,
+/* 9253*/ OPC_MoveParent,
+/* 9254*/ OPC_RecordChild1, // #2 = $T
+/* 9255*/ OPC_RecordChild2, // #3 = $F
+/* 9256*/ OPC_CheckType, MVT::i64,
+/* 9258*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9260*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9268*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
+/* 9277*/ /*Scope*/ 29, /*->9307*/
+/* 9278*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 9280*/ OPC_MoveParent,
+/* 9281*/ OPC_CheckType, MVT::i32,
+/* 9283*/ OPC_MoveParent,
+/* 9284*/ OPC_RecordChild1, // #2 = $T
+/* 9285*/ OPC_RecordChild2, // #3 = $F
+/* 9286*/ OPC_CheckType, MVT::i64,
+/* 9288*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9290*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9298*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
+/* 9307*/ /*Scope*/ 29, /*->9337*/
+/* 9308*/ OPC_CheckCondCode, ISD::SETLE,
+/* 9310*/ OPC_MoveParent,
+/* 9311*/ OPC_CheckType, MVT::i32,
+/* 9313*/ OPC_MoveParent,
+/* 9314*/ OPC_RecordChild1, // #2 = $T
+/* 9315*/ OPC_RecordChild2, // #3 = $F
+/* 9316*/ OPC_CheckType, MVT::i64,
+/* 9318*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9320*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 9328*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
+/* 9337*/ /*Scope*/ 29, /*->9367*/
+/* 9338*/ OPC_CheckCondCode, ISD::SETULE,
+/* 9340*/ OPC_MoveParent,
+/* 9341*/ OPC_CheckType, MVT::i32,
+/* 9343*/ OPC_MoveParent,
+/* 9344*/ OPC_RecordChild1, // #2 = $T
+/* 9345*/ OPC_RecordChild2, // #3 = $F
+/* 9346*/ OPC_CheckType, MVT::i64,
+/* 9348*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9350*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 9358*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
+/* 9367*/ /*Scope*/ 29, /*->9397*/
+/* 9368*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 9370*/ OPC_MoveParent,
+/* 9371*/ OPC_CheckType, MVT::i32,
+/* 9373*/ OPC_MoveParent,
+/* 9374*/ OPC_RecordChild1, // #2 = $T
+/* 9375*/ OPC_RecordChild2, // #3 = $F
+/* 9376*/ OPC_CheckType, MVT::i64,
+/* 9378*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9380*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9388*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
+/* 9397*/ /*Scope*/ 52, /*->9450*/
+/* 9398*/ OPC_CheckCondCode, ISD::SETNE,
+/* 9400*/ OPC_MoveParent,
+/* 9401*/ OPC_CheckType, MVT::i32,
+/* 9403*/ OPC_MoveParent,
+/* 9404*/ OPC_RecordChild1, // #2 = $T
+/* 9405*/ OPC_RecordChild2, // #3 = $F
+/* 9406*/ OPC_SwitchType /*2 cases */, 19, MVT::i32,// ->9428
+/* 9409*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9411*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9419*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9428*/ /*SwitchType*/ 19, MVT::i64,// ->9449
+/* 9430*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9432*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9440*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
+/* 9449*/ 0, // EndSwitchType
+/* 9450*/ /*Scope*/ 29, /*->9480*/
+/* 9451*/ OPC_CheckCondCode, ISD::SETGE,
+/* 9453*/ OPC_MoveParent,
+/* 9454*/ OPC_CheckType, MVT::i32,
+/* 9456*/ OPC_MoveParent,
+/* 9457*/ OPC_RecordChild1, // #2 = $T
+/* 9458*/ OPC_RecordChild2, // #3 = $F
+/* 9459*/ OPC_CheckType, MVT::i32,
+/* 9461*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9463*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9471*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9480*/ /*Scope*/ 29, /*->9510*/
+/* 9481*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 9483*/ OPC_MoveParent,
+/* 9484*/ OPC_CheckType, MVT::i32,
+/* 9486*/ OPC_MoveParent,
+/* 9487*/ OPC_RecordChild1, // #2 = $T
+/* 9488*/ OPC_RecordChild2, // #3 = $F
+/* 9489*/ OPC_CheckType, MVT::i32,
+/* 9491*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9493*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9501*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9510*/ /*Scope*/ 29, /*->9540*/
+/* 9511*/ OPC_CheckCondCode, ISD::SETLE,
+/* 9513*/ OPC_MoveParent,
+/* 9514*/ OPC_CheckType, MVT::i32,
+/* 9516*/ OPC_MoveParent,
+/* 9517*/ OPC_RecordChild1, // #2 = $T
+/* 9518*/ OPC_RecordChild2, // #3 = $F
+/* 9519*/ OPC_CheckType, MVT::i32,
+/* 9521*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9523*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 9531*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
+/* 9540*/ /*Scope*/ 29, /*->9570*/
+/* 9541*/ OPC_CheckCondCode, ISD::SETULE,
+/* 9543*/ OPC_MoveParent,
+/* 9544*/ OPC_CheckType, MVT::i32,
+/* 9546*/ OPC_MoveParent,
+/* 9547*/ OPC_RecordChild1, // #2 = $T
+/* 9548*/ OPC_RecordChild2, // #3 = $F
+/* 9549*/ OPC_CheckType, MVT::i32,
+/* 9551*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9553*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 9561*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
+/* 9570*/ /*Scope*/ 29, /*->9600*/
+/* 9571*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 9573*/ OPC_MoveParent,
+/* 9574*/ OPC_CheckType, MVT::i32,
+/* 9576*/ OPC_MoveParent,
+/* 9577*/ OPC_RecordChild1, // #2 = $T
+/* 9578*/ OPC_RecordChild2, // #3 = $F
+/* 9579*/ OPC_CheckType, MVT::i32,
+/* 9581*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9583*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9591*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9600*/ /*Scope*/ 29, /*->9630*/
+/* 9601*/ OPC_CheckCondCode, ISD::SETNE,
+/* 9603*/ OPC_MoveParent,
+/* 9604*/ OPC_CheckType, MVT::i32,
+/* 9606*/ OPC_MoveParent,
+/* 9607*/ OPC_RecordChild1, // #2 = $T
+/* 9608*/ OPC_RecordChild2, // #3 = $F
+/* 9609*/ OPC_CheckType, MVT::i32,
+/* 9611*/ OPC_CheckPatternPredicate, 35, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 9613*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9621*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9630*/ /*Scope*/ 29, /*->9660*/
+/* 9631*/ OPC_CheckCondCode, ISD::SETGE,
+/* 9633*/ OPC_MoveParent,
+/* 9634*/ OPC_CheckType, MVT::i32,
+/* 9636*/ OPC_MoveParent,
+/* 9637*/ OPC_RecordChild1, // #2 = $T
+/* 9638*/ OPC_RecordChild2, // #3 = $F
+/* 9639*/ OPC_CheckType, MVT::i32,
+/* 9641*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9643*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9651*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9660*/ /*Scope*/ 29, /*->9690*/
+/* 9661*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 9663*/ OPC_MoveParent,
+/* 9664*/ OPC_CheckType, MVT::i32,
+/* 9666*/ OPC_MoveParent,
+/* 9667*/ OPC_RecordChild1, // #2 = $T
+/* 9668*/ OPC_RecordChild2, // #3 = $F
+/* 9669*/ OPC_CheckType, MVT::i32,
+/* 9671*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9673*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9681*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9690*/ /*Scope*/ 29, /*->9720*/
+/* 9691*/ OPC_CheckCondCode, ISD::SETLE,
+/* 9693*/ OPC_MoveParent,
+/* 9694*/ OPC_CheckType, MVT::i32,
+/* 9696*/ OPC_MoveParent,
+/* 9697*/ OPC_RecordChild1, // #2 = $T
+/* 9698*/ OPC_RecordChild2, // #3 = $F
+/* 9699*/ OPC_CheckType, MVT::i32,
+/* 9701*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9703*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 9711*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
+/* 9720*/ /*Scope*/ 29, /*->9750*/
+/* 9721*/ OPC_CheckCondCode, ISD::SETULE,
+/* 9723*/ OPC_MoveParent,
+/* 9724*/ OPC_CheckType, MVT::i32,
+/* 9726*/ OPC_MoveParent,
+/* 9727*/ OPC_RecordChild1, // #2 = $T
+/* 9728*/ OPC_RecordChild2, // #3 = $F
+/* 9729*/ OPC_CheckType, MVT::i32,
+/* 9731*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9733*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 9741*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
+/* 9750*/ /*Scope*/ 29, /*->9780*/
+/* 9751*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 9753*/ OPC_MoveParent,
+/* 9754*/ OPC_CheckType, MVT::i32,
+/* 9756*/ OPC_MoveParent,
+/* 9757*/ OPC_RecordChild1, // #2 = $T
+/* 9758*/ OPC_RecordChild2, // #3 = $F
+/* 9759*/ OPC_CheckType, MVT::i32,
+/* 9761*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9763*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9771*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9780*/ /*Scope*/ 29, /*->9810*/
+/* 9781*/ OPC_CheckCondCode, ISD::SETNE,
+/* 9783*/ OPC_MoveParent,
+/* 9784*/ OPC_CheckType, MVT::i32,
+/* 9786*/ OPC_MoveParent,
+/* 9787*/ OPC_RecordChild1, // #2 = $T
+/* 9788*/ OPC_RecordChild2, // #3 = $F
+/* 9789*/ OPC_CheckType, MVT::i32,
+/* 9791*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 9793*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 9801*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 9810*/ /*Scope*/ 22, /*->9833*/
+/* 9811*/ OPC_CheckCondCode, ISD::SETGE,
+/* 9813*/ OPC_MoveParent,
+/* 9814*/ OPC_CheckType, MVT::i32,
+/* 9816*/ OPC_MoveParent,
+/* 9817*/ OPC_RecordChild1, // #2 = $x
+/* 9818*/ OPC_RecordChild2, // #3 = $y
+/* 9819*/ OPC_CheckType, MVT::i32,
+/* 9821*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 9823*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBteqZSlt), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 0, 1,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 6
+ // Dst: (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
+/* 9833*/ /*Scope*/ 22, /*->9856*/
+/* 9834*/ OPC_CheckCondCode, ISD::SETGT,
+/* 9836*/ OPC_MoveParent,
+/* 9837*/ OPC_CheckType, MVT::i32,
+/* 9839*/ OPC_MoveParent,
+/* 9840*/ OPC_RecordChild1, // #2 = $x
+/* 9841*/ OPC_RecordChild2, // #3 = $y
+/* 9842*/ OPC_CheckType, MVT::i32,
+/* 9844*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 9846*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBtneZSlt), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 6
+ // Dst: (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
+/* 9856*/ /*Scope*/ 22, /*->9879*/
+/* 9857*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 9859*/ OPC_MoveParent,
+/* 9860*/ OPC_CheckType, MVT::i32,
+/* 9862*/ OPC_MoveParent,
+/* 9863*/ OPC_RecordChild1, // #2 = $x
+/* 9864*/ OPC_RecordChild2, // #3 = $y
+/* 9865*/ OPC_CheckType, MVT::i32,
+/* 9867*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 9869*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBteqZSltu), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 0, 1,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 6
+ // Dst: (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
+/* 9879*/ /*Scope*/ 22, /*->9902*/
+/* 9880*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 9882*/ OPC_MoveParent,
+/* 9883*/ OPC_CheckType, MVT::i32,
+/* 9885*/ OPC_MoveParent,
+/* 9886*/ OPC_RecordChild1, // #2 = $x
+/* 9887*/ OPC_RecordChild2, // #3 = $y
+/* 9888*/ OPC_CheckType, MVT::i32,
+/* 9890*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 9892*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBtneZSltu), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 6
+ // Dst: (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
+/* 9902*/ /*Scope*/ 22, /*->9925*/
+/* 9903*/ OPC_CheckCondCode, ISD::SETLE,
+/* 9905*/ OPC_MoveParent,
+/* 9906*/ OPC_CheckType, MVT::i32,
+/* 9908*/ OPC_MoveParent,
+/* 9909*/ OPC_RecordChild1, // #2 = $x
+/* 9910*/ OPC_RecordChild2, // #3 = $y
+/* 9911*/ OPC_CheckType, MVT::i32,
+/* 9913*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 9915*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBteqZSlt), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 6
+ // Dst: (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
+/* 9925*/ /*Scope*/ 22, /*->9948*/
+/* 9926*/ OPC_CheckCondCode, ISD::SETULE,
+/* 9928*/ OPC_MoveParent,
+/* 9929*/ OPC_CheckType, MVT::i32,
+/* 9931*/ OPC_MoveParent,
+/* 9932*/ OPC_RecordChild1, // #2 = $x
+/* 9933*/ OPC_RecordChild2, // #3 = $y
+/* 9934*/ OPC_CheckType, MVT::i32,
+/* 9936*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 9938*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBteqZSltu), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 6
+ // Dst: (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
+/* 9948*/ /*Scope*/ 22, /*->9971*/
+/* 9949*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 9951*/ OPC_MoveParent,
+/* 9952*/ OPC_CheckType, MVT::i32,
+/* 9954*/ OPC_MoveParent,
+/* 9955*/ OPC_RecordChild1, // #2 = $x
+/* 9956*/ OPC_RecordChild2, // #3 = $y
+/* 9957*/ OPC_CheckType, MVT::i32,
+/* 9959*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 9961*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBteqZCmp), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 6
+ // Dst: (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
+/* 9971*/ /*Scope*/ 22, /*->9994*/
+/* 9972*/ OPC_CheckCondCode, ISD::SETNE,
+/* 9974*/ OPC_MoveParent,
+/* 9975*/ OPC_CheckType, MVT::i32,
+/* 9977*/ OPC_MoveParent,
+/* 9978*/ OPC_RecordChild1, // #2 = $x
+/* 9979*/ OPC_RecordChild2, // #3 = $y
+/* 9980*/ OPC_CheckType, MVT::i32,
+/* 9982*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 9984*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelTBtneZCmp), 0,
+ MVT::i32, 4/*#Ops*/, 2, 3, 1, 0,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 6
+ // Dst: (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
+/* 9994*/ 0, /*End of Scope*/
+/* 9995*/ /*Scope*/ 96|128,2/*352*/, /*->10349*/
+/* 9997*/ OPC_CheckChild0Type, MVT::i64,
+/* 9999*/ OPC_RecordChild1, // #1 = $rhs
+/* 10000*/ OPC_MoveChild2,
+/* 10001*/ OPC_Scope, 29, /*->10032*/ // 10 children in Scope
+/* 10003*/ OPC_CheckCondCode, ISD::SETGE,
+/* 10005*/ OPC_MoveParent,
+/* 10006*/ OPC_CheckType, MVT::i32,
+/* 10008*/ OPC_MoveParent,
+/* 10009*/ OPC_RecordChild1, // #2 = $T
+/* 10010*/ OPC_RecordChild2, // #3 = $F
+/* 10011*/ OPC_CheckType, MVT::i32,
+/* 10013*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10015*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 10023*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 10032*/ /*Scope*/ 29, /*->10062*/
+/* 10033*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 10035*/ OPC_MoveParent,
+/* 10036*/ OPC_CheckType, MVT::i32,
+/* 10038*/ OPC_MoveParent,
+/* 10039*/ OPC_RecordChild1, // #2 = $T
+/* 10040*/ OPC_RecordChild2, // #3 = $F
+/* 10041*/ OPC_CheckType, MVT::i32,
+/* 10043*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10045*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 10053*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 10062*/ /*Scope*/ 29, /*->10092*/
+/* 10063*/ OPC_CheckCondCode, ISD::SETLE,
+/* 10065*/ OPC_MoveParent,
+/* 10066*/ OPC_CheckType, MVT::i32,
+/* 10068*/ OPC_MoveParent,
+/* 10069*/ OPC_RecordChild1, // #2 = $T
+/* 10070*/ OPC_RecordChild2, // #3 = $F
+/* 10071*/ OPC_CheckType, MVT::i32,
+/* 10073*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10075*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 10083*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
+/* 10092*/ /*Scope*/ 29, /*->10122*/
+/* 10093*/ OPC_CheckCondCode, ISD::SETULE,
+/* 10095*/ OPC_MoveParent,
+/* 10096*/ OPC_CheckType, MVT::i32,
+/* 10098*/ OPC_MoveParent,
+/* 10099*/ OPC_RecordChild1, // #2 = $T
+/* 10100*/ OPC_RecordChild2, // #3 = $F
+/* 10101*/ OPC_CheckType, MVT::i32,
+/* 10103*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10105*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 10113*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
+/* 10122*/ /*Scope*/ 29, /*->10152*/
+/* 10123*/ OPC_CheckCondCode, ISD::SETGE,
+/* 10125*/ OPC_MoveParent,
+/* 10126*/ OPC_CheckType, MVT::i32,
+/* 10128*/ OPC_MoveParent,
+/* 10129*/ OPC_RecordChild1, // #2 = $T
+/* 10130*/ OPC_RecordChild2, // #3 = $F
+/* 10131*/ OPC_CheckType, MVT::i64,
+/* 10133*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10135*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 10143*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
+/* 10152*/ /*Scope*/ 29, /*->10182*/
+/* 10153*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 10155*/ OPC_MoveParent,
+/* 10156*/ OPC_CheckType, MVT::i32,
+/* 10158*/ OPC_MoveParent,
+/* 10159*/ OPC_RecordChild1, // #2 = $T
+/* 10160*/ OPC_RecordChild2, // #3 = $F
+/* 10161*/ OPC_CheckType, MVT::i64,
+/* 10163*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10165*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 10173*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
+/* 10182*/ /*Scope*/ 29, /*->10212*/
+/* 10183*/ OPC_CheckCondCode, ISD::SETLE,
+/* 10185*/ OPC_MoveParent,
+/* 10186*/ OPC_CheckType, MVT::i32,
+/* 10188*/ OPC_MoveParent,
+/* 10189*/ OPC_RecordChild1, // #2 = $T
+/* 10190*/ OPC_RecordChild2, // #3 = $F
+/* 10191*/ OPC_CheckType, MVT::i64,
+/* 10193*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10195*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 10203*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
+/* 10212*/ /*Scope*/ 29, /*->10242*/
+/* 10213*/ OPC_CheckCondCode, ISD::SETULE,
+/* 10215*/ OPC_MoveParent,
+/* 10216*/ OPC_CheckType, MVT::i32,
+/* 10218*/ OPC_MoveParent,
+/* 10219*/ OPC_RecordChild1, // #2 = $T
+/* 10220*/ OPC_RecordChild2, // #3 = $F
+/* 10221*/ OPC_CheckType, MVT::i64,
+/* 10223*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10225*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 10233*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
+/* 10242*/ /*Scope*/ 52, /*->10295*/
+/* 10243*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 10245*/ OPC_MoveParent,
+/* 10246*/ OPC_CheckType, MVT::i32,
+/* 10248*/ OPC_MoveParent,
+/* 10249*/ OPC_RecordChild1, // #2 = $T
+/* 10250*/ OPC_RecordChild2, // #3 = $F
+/* 10251*/ OPC_SwitchType /*2 cases */, 19, MVT::i32,// ->10273
+/* 10254*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10256*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #4
+/* 10264*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 10273*/ /*SwitchType*/ 19, MVT::i64,// ->10294
+/* 10275*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10277*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #4
+/* 10285*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
+/* 10294*/ 0, // EndSwitchType
+/* 10295*/ /*Scope*/ 52, /*->10348*/
+/* 10296*/ OPC_CheckCondCode, ISD::SETNE,
+/* 10298*/ OPC_MoveParent,
+/* 10299*/ OPC_CheckType, MVT::i32,
+/* 10301*/ OPC_MoveParent,
+/* 10302*/ OPC_RecordChild1, // #2 = $T
+/* 10303*/ OPC_RecordChild2, // #3 = $F
+/* 10304*/ OPC_SwitchType /*2 cases */, 19, MVT::i32,// ->10326
+/* 10307*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10309*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #4
+/* 10317*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_I), 0,
+ MVT::i32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 6
+ // Dst: (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
+/* 10326*/ /*SwitchType*/ 19, MVT::i64,// ->10347
+/* 10328*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10330*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #4
+/* 10338*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_I64), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 6
+ // Dst: (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
+/* 10347*/ 0, // EndSwitchType
+/* 10348*/ 0, /*End of Scope*/
+/* 10349*/ 0, /*End of Scope*/
+/* 10350*/ /*Scope*/ 5|128,2/*261*/, /*->10613*/
+/* 10352*/ OPC_RecordChild0, // #0 = $cond
+/* 10353*/ OPC_Scope, 65|128,1/*193*/, /*->10549*/ // 2 children in Scope
+/* 10356*/ OPC_CheckChild0Type, MVT::i32,
+/* 10358*/ OPC_RecordChild1, // #1 = $T
+/* 10359*/ OPC_RecordChild2, // #2 = $F
+/* 10360*/ OPC_SwitchType /*2 cases */, 116, MVT::i32,// ->10479
+/* 10363*/ OPC_Scope, 11, /*->10376*/ // 7 children in Scope
+/* 10365*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10367*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_I), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
+/* 10376*/ /*Scope*/ 11, /*->10388*/
+/* 10377*/ OPC_CheckPatternPredicate, 35, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10379*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
+/* 10388*/ /*Scope*/ 11, /*->10400*/
+/* 10389*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 10391*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_MM), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
+/* 10400*/ /*Scope*/ 26, /*->10427*/
+/* 10401*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 10403*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #3
+/* 10411*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ), 0,
+ MVT::i32, 2/*#Ops*/, 2, 0, // Results = #4
+/* 10419*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 3
+ // Dst: (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
+/* 10427*/ /*Scope*/ 26, /*->10454*/
+/* 10428*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 10430*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #3
+/* 10438*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 0, // Results = #4
+/* 10446*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) - Complexity = 3
+ // Dst: (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
+/* 10454*/ /*Scope*/ 11, /*->10466*/
+/* 10455*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 10457*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECT_I), 0,
+ MVT::i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
+/* 10466*/ /*Scope*/ 11, /*->10478*/
+/* 10467*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 10469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SelBneZ), 0,
+ MVT::i32, 3/*#Ops*/, 1, 2, 0,
+ // Src: (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) - Complexity = 3
+ // Dst: (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
+/* 10478*/ 0, /*End of Scope*/
+/* 10479*/ /*SwitchType*/ 67, MVT::i64,// ->10548
+/* 10481*/ OPC_Scope, 11, /*->10494*/ // 3 children in Scope
+/* 10483*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10485*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_I64), 0,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
+/* 10494*/ /*Scope*/ 40, /*->10535*/
+/* 10495*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 10497*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #3
+/* 10504*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 3, // Results = #4
+/* 10512*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #5
+/* 10519*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 5, // Results = #6
+/* 10527*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 4, 6,
+ // Src: (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 3
+ // Dst: (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
+/* 10535*/ /*Scope*/ 11, /*->10547*/
+/* 10536*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 10538*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECT_I64), 0,
+ MVT::i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
+/* 10547*/ 0, /*End of Scope*/
+/* 10548*/ 0, // EndSwitchType
+/* 10549*/ /*Scope*/ 62, /*->10612*/
+/* 10550*/ OPC_CheckChild0Type, MVT::i64,
+/* 10552*/ OPC_RecordChild1, // #1 = $T
+/* 10553*/ OPC_RecordChild2, // #2 = $F
+/* 10554*/ OPC_SwitchType /*2 cases */, 11, MVT::i32,// ->10568
+/* 10557*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10559*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_I), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
+/* 10568*/ /*SwitchType*/ 41, MVT::i64,// ->10611
+/* 10570*/ OPC_Scope, 11, /*->10583*/ // 2 children in Scope
+/* 10572*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10574*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_I64), 0,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) - Complexity = 3
+ // Dst: (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
+/* 10583*/ /*Scope*/ 26, /*->10610*/
+/* 10584*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 10586*/ OPC_EmitNode1, TARGET_VAL(Mips::SELNEZ64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0, // Results = #3
+/* 10594*/ OPC_EmitNode1, TARGET_VAL(Mips::SELEQZ64), 0,
+ MVT::i64, 2/*#Ops*/, 2, 0, // Results = #4
+/* 10602*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) - Complexity = 3
+ // Dst: (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
+/* 10610*/ 0, /*End of Scope*/
+/* 10611*/ 0, // EndSwitchType
+/* 10612*/ 0, /*End of Scope*/
+/* 10613*/ /*Scope*/ 112|128,20/*2672*/, /*->13287*/
+/* 10615*/ OPC_MoveChild0,
+/* 10616*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
+/* 10619*/ OPC_RecordChild0, // #0 = $lhs
+/* 10620*/ OPC_Scope, 97|128,14/*1889*/, /*->12512*/ // 2 children in Scope
+/* 10623*/ OPC_CheckChild0Type, MVT::i32,
+/* 10625*/ OPC_Scope, 97|128,1/*225*/, /*->10853*/ // 2 children in Scope
+/* 10628*/ OPC_CheckChild1Integer, 0,
+/* 10630*/ OPC_MoveChild2,
+/* 10631*/ OPC_Scope, 21, /*->10654*/ // 10 children in Scope
+/* 10633*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 10635*/ OPC_MoveParent,
+/* 10636*/ OPC_CheckType, MVT::i32,
+/* 10638*/ OPC_MoveParent,
+/* 10639*/ OPC_RecordChild1, // #1 = $T
+/* 10640*/ OPC_RecordChild2, // #2 = $F
+/* 10641*/ OPC_CheckType, MVT::f32,
+/* 10643*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10645*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
+/* 10654*/ /*Scope*/ 21, /*->10676*/
+/* 10655*/ OPC_CheckCondCode, ISD::SETNE,
+/* 10657*/ OPC_MoveParent,
+/* 10658*/ OPC_CheckType, MVT::i32,
+/* 10660*/ OPC_MoveParent,
+/* 10661*/ OPC_RecordChild1, // #1 = $T
+/* 10662*/ OPC_RecordChild2, // #2 = $F
+/* 10663*/ OPC_CheckType, MVT::f32,
+/* 10665*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10667*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
+/* 10676*/ /*Scope*/ 21, /*->10698*/
+/* 10677*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 10679*/ OPC_MoveParent,
+/* 10680*/ OPC_CheckType, MVT::i32,
+/* 10682*/ OPC_MoveParent,
+/* 10683*/ OPC_RecordChild1, // #1 = $T
+/* 10684*/ OPC_RecordChild2, // #2 = $F
+/* 10685*/ OPC_CheckType, MVT::f64,
+/* 10687*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10689*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
+/* 10698*/ /*Scope*/ 21, /*->10720*/
+/* 10699*/ OPC_CheckCondCode, ISD::SETNE,
+/* 10701*/ OPC_MoveParent,
+/* 10702*/ OPC_CheckType, MVT::i32,
+/* 10704*/ OPC_MoveParent,
+/* 10705*/ OPC_RecordChild1, // #1 = $T
+/* 10706*/ OPC_RecordChild2, // #2 = $F
+/* 10707*/ OPC_CheckType, MVT::f64,
+/* 10709*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10711*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
+/* 10720*/ /*Scope*/ 21, /*->10742*/
+/* 10721*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 10723*/ OPC_MoveParent,
+/* 10724*/ OPC_CheckType, MVT::i32,
+/* 10726*/ OPC_MoveParent,
+/* 10727*/ OPC_RecordChild1, // #1 = $T
+/* 10728*/ OPC_RecordChild2, // #2 = $F
+/* 10729*/ OPC_CheckType, MVT::f64,
+/* 10731*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10733*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
+/* 10742*/ /*Scope*/ 21, /*->10764*/
+/* 10743*/ OPC_CheckCondCode, ISD::SETNE,
+/* 10745*/ OPC_MoveParent,
+/* 10746*/ OPC_CheckType, MVT::i32,
+/* 10748*/ OPC_MoveParent,
+/* 10749*/ OPC_RecordChild1, // #1 = $T
+/* 10750*/ OPC_RecordChild2, // #2 = $F
+/* 10751*/ OPC_CheckType, MVT::f64,
+/* 10753*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10755*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
+/* 10764*/ /*Scope*/ 21, /*->10786*/
+/* 10765*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 10767*/ OPC_MoveParent,
+/* 10768*/ OPC_CheckType, MVT::i32,
+/* 10770*/ OPC_MoveParent,
+/* 10771*/ OPC_RecordChild1, // #1 = $T
+/* 10772*/ OPC_RecordChild2, // #2 = $F
+/* 10773*/ OPC_CheckType, MVT::f32,
+/* 10775*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 10777*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
+/* 10786*/ /*Scope*/ 21, /*->10808*/
+/* 10787*/ OPC_CheckCondCode, ISD::SETNE,
+/* 10789*/ OPC_MoveParent,
+/* 10790*/ OPC_CheckType, MVT::i32,
+/* 10792*/ OPC_MoveParent,
+/* 10793*/ OPC_RecordChild1, // #1 = $T
+/* 10794*/ OPC_RecordChild2, // #2 = $F
+/* 10795*/ OPC_CheckType, MVT::f32,
+/* 10797*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 10799*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
+/* 10808*/ /*Scope*/ 21, /*->10830*/
+/* 10809*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 10811*/ OPC_MoveParent,
+/* 10812*/ OPC_CheckType, MVT::i32,
+/* 10814*/ OPC_MoveParent,
+/* 10815*/ OPC_RecordChild1, // #1 = $T
+/* 10816*/ OPC_RecordChild2, // #2 = $F
+/* 10817*/ OPC_CheckType, MVT::f64,
+/* 10819*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 10821*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
+/* 10830*/ /*Scope*/ 21, /*->10852*/
+/* 10831*/ OPC_CheckCondCode, ISD::SETNE,
+/* 10833*/ OPC_MoveParent,
+/* 10834*/ OPC_CheckType, MVT::i32,
+/* 10836*/ OPC_MoveParent,
+/* 10837*/ OPC_RecordChild1, // #1 = $T
+/* 10838*/ OPC_RecordChild2, // #2 = $F
+/* 10839*/ OPC_CheckType, MVT::f64,
+/* 10841*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 10843*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 11
+ // Dst: (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
+/* 10852*/ 0, /*End of Scope*/
+/* 10853*/ /*Scope*/ 120|128,12/*1656*/, /*->12511*/
+/* 10855*/ OPC_RecordChild1, // #1 = $rhs
+/* 10856*/ OPC_Scope, 106|128,5/*746*/, /*->11605*/ // 2 children in Scope
+/* 10859*/ OPC_MoveChild1,
+/* 10860*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 10863*/ OPC_Scope, 70, /*->10935*/ // 10 children in Scope
+/* 10865*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 10867*/ OPC_MoveParent,
+/* 10868*/ OPC_MoveChild2,
+/* 10869*/ OPC_Scope, 31, /*->10902*/ // 2 children in Scope
+/* 10871*/ OPC_CheckCondCode, ISD::SETGE,
+/* 10873*/ OPC_MoveParent,
+/* 10874*/ OPC_CheckType, MVT::i32,
+/* 10876*/ OPC_MoveParent,
+/* 10877*/ OPC_RecordChild1, // #2 = $T
+/* 10878*/ OPC_RecordChild2, // #3 = $F
+/* 10879*/ OPC_CheckType, MVT::f32,
+/* 10881*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10883*/ OPC_EmitConvertToTarget, 1,
+/* 10885*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 10893*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), FGR32:{ *:[f32] }:$F)
+/* 10902*/ /*Scope*/ 31, /*->10934*/
+/* 10903*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 10905*/ OPC_MoveParent,
+/* 10906*/ OPC_CheckType, MVT::i32,
+/* 10908*/ OPC_MoveParent,
+/* 10909*/ OPC_RecordChild1, // #2 = $T
+/* 10910*/ OPC_RecordChild2, // #3 = $F
+/* 10911*/ OPC_CheckType, MVT::f32,
+/* 10913*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10915*/ OPC_EmitConvertToTarget, 1,
+/* 10917*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 10925*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), FGR32:{ *:[f32] }:$F)
+/* 10934*/ 0, /*End of Scope*/
+/* 10935*/ /*Scope*/ 76, /*->11012*/
+/* 10936*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 10938*/ OPC_MoveParent,
+/* 10939*/ OPC_MoveChild2,
+/* 10940*/ OPC_Scope, 34, /*->10976*/ // 2 children in Scope
+/* 10942*/ OPC_CheckCondCode, ISD::SETGT,
+/* 10944*/ OPC_MoveParent,
+/* 10945*/ OPC_CheckType, MVT::i32,
+/* 10947*/ OPC_MoveParent,
+/* 10948*/ OPC_RecordChild1, // #2 = $T
+/* 10949*/ OPC_RecordChild2, // #3 = $F
+/* 10950*/ OPC_CheckType, MVT::f32,
+/* 10952*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10954*/ OPC_EmitConvertToTarget, 1,
+/* 10956*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 10959*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 10967*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), FGR32:{ *:[f32] }:$F)
+/* 10976*/ /*Scope*/ 34, /*->11011*/
+/* 10977*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 10979*/ OPC_MoveParent,
+/* 10980*/ OPC_CheckType, MVT::i32,
+/* 10982*/ OPC_MoveParent,
+/* 10983*/ OPC_RecordChild1, // #2 = $T
+/* 10984*/ OPC_RecordChild2, // #3 = $F
+/* 10985*/ OPC_CheckType, MVT::f32,
+/* 10987*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 10989*/ OPC_EmitConvertToTarget, 1,
+/* 10991*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 10994*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11002*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), FGR32:{ *:[f32] }:$F)
+/* 11011*/ 0, /*End of Scope*/
+/* 11012*/ /*Scope*/ 70, /*->11083*/
+/* 11013*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 11015*/ OPC_MoveParent,
+/* 11016*/ OPC_MoveChild2,
+/* 11017*/ OPC_Scope, 31, /*->11050*/ // 2 children in Scope
+/* 11019*/ OPC_CheckCondCode, ISD::SETGE,
+/* 11021*/ OPC_MoveParent,
+/* 11022*/ OPC_CheckType, MVT::i32,
+/* 11024*/ OPC_MoveParent,
+/* 11025*/ OPC_RecordChild1, // #2 = $T
+/* 11026*/ OPC_RecordChild2, // #3 = $F
+/* 11027*/ OPC_CheckType, MVT::f64,
+/* 11029*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11031*/ OPC_EmitConvertToTarget, 1,
+/* 11033*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 11041*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 11050*/ /*Scope*/ 31, /*->11082*/
+/* 11051*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 11053*/ OPC_MoveParent,
+/* 11054*/ OPC_CheckType, MVT::i32,
+/* 11056*/ OPC_MoveParent,
+/* 11057*/ OPC_RecordChild1, // #2 = $T
+/* 11058*/ OPC_RecordChild2, // #3 = $F
+/* 11059*/ OPC_CheckType, MVT::f64,
+/* 11061*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11063*/ OPC_EmitConvertToTarget, 1,
+/* 11065*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 11073*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), AFGR64:{ *:[f64] }:$F)
+/* 11082*/ 0, /*End of Scope*/
+/* 11083*/ /*Scope*/ 76, /*->11160*/
+/* 11084*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 11086*/ OPC_MoveParent,
+/* 11087*/ OPC_MoveChild2,
+/* 11088*/ OPC_Scope, 34, /*->11124*/ // 2 children in Scope
+/* 11090*/ OPC_CheckCondCode, ISD::SETGT,
+/* 11092*/ OPC_MoveParent,
+/* 11093*/ OPC_CheckType, MVT::i32,
+/* 11095*/ OPC_MoveParent,
+/* 11096*/ OPC_RecordChild1, // #2 = $T
+/* 11097*/ OPC_RecordChild2, // #3 = $F
+/* 11098*/ OPC_CheckType, MVT::f64,
+/* 11100*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11102*/ OPC_EmitConvertToTarget, 1,
+/* 11104*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 11107*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11115*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), AFGR64:{ *:[f64] }:$F)
+/* 11124*/ /*Scope*/ 34, /*->11159*/
+/* 11125*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 11127*/ OPC_MoveParent,
+/* 11128*/ OPC_CheckType, MVT::i32,
+/* 11130*/ OPC_MoveParent,
+/* 11131*/ OPC_RecordChild1, // #2 = $T
+/* 11132*/ OPC_RecordChild2, // #3 = $F
+/* 11133*/ OPC_CheckType, MVT::f64,
+/* 11135*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11137*/ OPC_EmitConvertToTarget, 1,
+/* 11139*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 11142*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11150*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), AFGR64:{ *:[f64] }:$F)
+/* 11159*/ 0, /*End of Scope*/
+/* 11160*/ /*Scope*/ 70, /*->11231*/
+/* 11161*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 11163*/ OPC_MoveParent,
+/* 11164*/ OPC_MoveChild2,
+/* 11165*/ OPC_Scope, 31, /*->11198*/ // 2 children in Scope
+/* 11167*/ OPC_CheckCondCode, ISD::SETGE,
+/* 11169*/ OPC_MoveParent,
+/* 11170*/ OPC_CheckType, MVT::i32,
+/* 11172*/ OPC_MoveParent,
+/* 11173*/ OPC_RecordChild1, // #2 = $T
+/* 11174*/ OPC_RecordChild2, // #3 = $F
+/* 11175*/ OPC_CheckType, MVT::f64,
+/* 11177*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11179*/ OPC_EmitConvertToTarget, 1,
+/* 11181*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 11189*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), FGR64:{ *:[f64] }:$F)
+/* 11198*/ /*Scope*/ 31, /*->11230*/
+/* 11199*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 11201*/ OPC_MoveParent,
+/* 11202*/ OPC_CheckType, MVT::i32,
+/* 11204*/ OPC_MoveParent,
+/* 11205*/ OPC_RecordChild1, // #2 = $T
+/* 11206*/ OPC_RecordChild2, // #3 = $F
+/* 11207*/ OPC_CheckType, MVT::f64,
+/* 11209*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11211*/ OPC_EmitConvertToTarget, 1,
+/* 11213*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 11221*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), FGR64:{ *:[f64] }:$F)
+/* 11230*/ 0, /*End of Scope*/
+/* 11231*/ /*Scope*/ 76, /*->11308*/
+/* 11232*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 11234*/ OPC_MoveParent,
+/* 11235*/ OPC_MoveChild2,
+/* 11236*/ OPC_Scope, 34, /*->11272*/ // 2 children in Scope
+/* 11238*/ OPC_CheckCondCode, ISD::SETGT,
+/* 11240*/ OPC_MoveParent,
+/* 11241*/ OPC_CheckType, MVT::i32,
+/* 11243*/ OPC_MoveParent,
+/* 11244*/ OPC_RecordChild1, // #2 = $T
+/* 11245*/ OPC_RecordChild2, // #3 = $F
+/* 11246*/ OPC_CheckType, MVT::f64,
+/* 11248*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11250*/ OPC_EmitConvertToTarget, 1,
+/* 11252*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 11255*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11263*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), FGR64:{ *:[f64] }:$F)
+/* 11272*/ /*Scope*/ 34, /*->11307*/
+/* 11273*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 11275*/ OPC_MoveParent,
+/* 11276*/ OPC_CheckType, MVT::i32,
+/* 11278*/ OPC_MoveParent,
+/* 11279*/ OPC_RecordChild1, // #2 = $T
+/* 11280*/ OPC_RecordChild2, // #3 = $F
+/* 11281*/ OPC_CheckType, MVT::f64,
+/* 11283*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11285*/ OPC_EmitConvertToTarget, 1,
+/* 11287*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 11290*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11298*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), FGR64:{ *:[f64] }:$F)
+/* 11307*/ 0, /*End of Scope*/
+/* 11308*/ /*Scope*/ 70, /*->11379*/
+/* 11309*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 11311*/ OPC_MoveParent,
+/* 11312*/ OPC_MoveChild2,
+/* 11313*/ OPC_Scope, 31, /*->11346*/ // 2 children in Scope
+/* 11315*/ OPC_CheckCondCode, ISD::SETGE,
+/* 11317*/ OPC_MoveParent,
+/* 11318*/ OPC_CheckType, MVT::i32,
+/* 11320*/ OPC_MoveParent,
+/* 11321*/ OPC_RecordChild1, // #2 = $T
+/* 11322*/ OPC_RecordChild2, // #3 = $F
+/* 11323*/ OPC_CheckType, MVT::f32,
+/* 11325*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 11327*/ OPC_EmitConvertToTarget, 1,
+/* 11329*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 11337*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), FGR32:{ *:[f32] }:$F)
+/* 11346*/ /*Scope*/ 31, /*->11378*/
+/* 11347*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 11349*/ OPC_MoveParent,
+/* 11350*/ OPC_CheckType, MVT::i32,
+/* 11352*/ OPC_MoveParent,
+/* 11353*/ OPC_RecordChild1, // #2 = $T
+/* 11354*/ OPC_RecordChild2, // #3 = $F
+/* 11355*/ OPC_CheckType, MVT::f32,
+/* 11357*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 11359*/ OPC_EmitConvertToTarget, 1,
+/* 11361*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 11369*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), FGR32:{ *:[f32] }:$F)
+/* 11378*/ 0, /*End of Scope*/
+/* 11379*/ /*Scope*/ 76, /*->11456*/
+/* 11380*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 11382*/ OPC_MoveParent,
+/* 11383*/ OPC_MoveChild2,
+/* 11384*/ OPC_Scope, 34, /*->11420*/ // 2 children in Scope
+/* 11386*/ OPC_CheckCondCode, ISD::SETGT,
+/* 11388*/ OPC_MoveParent,
+/* 11389*/ OPC_CheckType, MVT::i32,
+/* 11391*/ OPC_MoveParent,
+/* 11392*/ OPC_RecordChild1, // #2 = $T
+/* 11393*/ OPC_RecordChild2, // #3 = $F
+/* 11394*/ OPC_CheckType, MVT::f32,
+/* 11396*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 11398*/ OPC_EmitConvertToTarget, 1,
+/* 11400*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 11403*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11411*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), FGR32:{ *:[f32] }:$F)
+/* 11420*/ /*Scope*/ 34, /*->11455*/
+/* 11421*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 11423*/ OPC_MoveParent,
+/* 11424*/ OPC_CheckType, MVT::i32,
+/* 11426*/ OPC_MoveParent,
+/* 11427*/ OPC_RecordChild1, // #2 = $T
+/* 11428*/ OPC_RecordChild2, // #3 = $F
+/* 11429*/ OPC_CheckType, MVT::f32,
+/* 11431*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 11433*/ OPC_EmitConvertToTarget, 1,
+/* 11435*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 11438*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11446*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), FGR32:{ *:[f32] }:$F)
+/* 11455*/ 0, /*End of Scope*/
+/* 11456*/ /*Scope*/ 70, /*->11527*/
+/* 11457*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 11459*/ OPC_MoveParent,
+/* 11460*/ OPC_MoveChild2,
+/* 11461*/ OPC_Scope, 31, /*->11494*/ // 2 children in Scope
+/* 11463*/ OPC_CheckCondCode, ISD::SETGE,
+/* 11465*/ OPC_MoveParent,
+/* 11466*/ OPC_CheckType, MVT::i32,
+/* 11468*/ OPC_MoveParent,
+/* 11469*/ OPC_RecordChild1, // #2 = $T
+/* 11470*/ OPC_RecordChild2, // #3 = $F
+/* 11471*/ OPC_CheckType, MVT::f64,
+/* 11473*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 11475*/ OPC_EmitConvertToTarget, 1,
+/* 11477*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 11485*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 11494*/ /*Scope*/ 31, /*->11526*/
+/* 11495*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 11497*/ OPC_MoveParent,
+/* 11498*/ OPC_CheckType, MVT::i32,
+/* 11500*/ OPC_MoveParent,
+/* 11501*/ OPC_RecordChild1, // #2 = $T
+/* 11502*/ OPC_RecordChild2, // #3 = $F
+/* 11503*/ OPC_CheckType, MVT::f64,
+/* 11505*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 11507*/ OPC_EmitConvertToTarget, 1,
+/* 11509*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 11517*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lh, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rh), AFGR64:{ *:[f64] }:$F)
+/* 11526*/ 0, /*End of Scope*/
+/* 11527*/ /*Scope*/ 76, /*->11604*/
+/* 11528*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 11530*/ OPC_MoveParent,
+/* 11531*/ OPC_MoveChild2,
+/* 11532*/ OPC_Scope, 34, /*->11568*/ // 2 children in Scope
+/* 11534*/ OPC_CheckCondCode, ISD::SETGT,
+/* 11536*/ OPC_MoveParent,
+/* 11537*/ OPC_CheckType, MVT::i32,
+/* 11539*/ OPC_MoveParent,
+/* 11540*/ OPC_RecordChild1, // #2 = $T
+/* 11541*/ OPC_RecordChild2, // #3 = $F
+/* 11542*/ OPC_CheckType, MVT::f64,
+/* 11544*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 11546*/ OPC_EmitConvertToTarget, 1,
+/* 11548*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 11551*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11559*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), AFGR64:{ *:[f64] }:$F)
+/* 11568*/ /*Scope*/ 34, /*->11603*/
+/* 11569*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 11571*/ OPC_MoveParent,
+/* 11572*/ OPC_CheckType, MVT::i32,
+/* 11574*/ OPC_MoveParent,
+/* 11575*/ OPC_RecordChild1, // #2 = $T
+/* 11576*/ OPC_RecordChild2, // #3 = $F
+/* 11577*/ OPC_CheckType, MVT::f64,
+/* 11579*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 11581*/ OPC_EmitConvertToTarget, 1,
+/* 11583*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 11586*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 11594*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (Plus1:{ *:[i32] } (imm:{ *:[i32] }):$rhs)), AFGR64:{ *:[f64] }:$F)
+/* 11603*/ 0, /*End of Scope*/
+/* 11604*/ 0, /*End of Scope*/
+/* 11605*/ /*Scope*/ 7|128,7/*903*/, /*->12510*/
+/* 11607*/ OPC_MoveChild2,
+/* 11608*/ OPC_Scope, 29, /*->11639*/ // 30 children in Scope
+/* 11610*/ OPC_CheckCondCode, ISD::SETGE,
+/* 11612*/ OPC_MoveParent,
+/* 11613*/ OPC_CheckType, MVT::i32,
+/* 11615*/ OPC_MoveParent,
+/* 11616*/ OPC_RecordChild1, // #2 = $T
+/* 11617*/ OPC_RecordChild2, // #3 = $F
+/* 11618*/ OPC_CheckType, MVT::f32,
+/* 11620*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11622*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11630*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 11639*/ /*Scope*/ 29, /*->11669*/
+/* 11640*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 11642*/ OPC_MoveParent,
+/* 11643*/ OPC_CheckType, MVT::i32,
+/* 11645*/ OPC_MoveParent,
+/* 11646*/ OPC_RecordChild1, // #2 = $T
+/* 11647*/ OPC_RecordChild2, // #3 = $F
+/* 11648*/ OPC_CheckType, MVT::f32,
+/* 11650*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11652*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11660*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 11669*/ /*Scope*/ 29, /*->11699*/
+/* 11670*/ OPC_CheckCondCode, ISD::SETLE,
+/* 11672*/ OPC_MoveParent,
+/* 11673*/ OPC_CheckType, MVT::i32,
+/* 11675*/ OPC_MoveParent,
+/* 11676*/ OPC_RecordChild1, // #2 = $T
+/* 11677*/ OPC_RecordChild2, // #3 = $F
+/* 11678*/ OPC_CheckType, MVT::f32,
+/* 11680*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11682*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 11690*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
+/* 11699*/ /*Scope*/ 29, /*->11729*/
+/* 11700*/ OPC_CheckCondCode, ISD::SETULE,
+/* 11702*/ OPC_MoveParent,
+/* 11703*/ OPC_CheckType, MVT::i32,
+/* 11705*/ OPC_MoveParent,
+/* 11706*/ OPC_RecordChild1, // #2 = $T
+/* 11707*/ OPC_RecordChild2, // #3 = $F
+/* 11708*/ OPC_CheckType, MVT::f32,
+/* 11710*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11712*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 11720*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
+/* 11729*/ /*Scope*/ 29, /*->11759*/
+/* 11730*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 11732*/ OPC_MoveParent,
+/* 11733*/ OPC_CheckType, MVT::i32,
+/* 11735*/ OPC_MoveParent,
+/* 11736*/ OPC_RecordChild1, // #2 = $T
+/* 11737*/ OPC_RecordChild2, // #3 = $F
+/* 11738*/ OPC_CheckType, MVT::f32,
+/* 11740*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11742*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11750*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 11759*/ /*Scope*/ 29, /*->11789*/
+/* 11760*/ OPC_CheckCondCode, ISD::SETNE,
+/* 11762*/ OPC_MoveParent,
+/* 11763*/ OPC_CheckType, MVT::i32,
+/* 11765*/ OPC_MoveParent,
+/* 11766*/ OPC_RecordChild1, // #2 = $T
+/* 11767*/ OPC_RecordChild2, // #3 = $F
+/* 11768*/ OPC_CheckType, MVT::f32,
+/* 11770*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11772*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11780*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 11789*/ /*Scope*/ 29, /*->11819*/
+/* 11790*/ OPC_CheckCondCode, ISD::SETGE,
+/* 11792*/ OPC_MoveParent,
+/* 11793*/ OPC_CheckType, MVT::i32,
+/* 11795*/ OPC_MoveParent,
+/* 11796*/ OPC_RecordChild1, // #2 = $T
+/* 11797*/ OPC_RecordChild2, // #3 = $F
+/* 11798*/ OPC_CheckType, MVT::f64,
+/* 11800*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11802*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11810*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 11819*/ /*Scope*/ 29, /*->11849*/
+/* 11820*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 11822*/ OPC_MoveParent,
+/* 11823*/ OPC_CheckType, MVT::i32,
+/* 11825*/ OPC_MoveParent,
+/* 11826*/ OPC_RecordChild1, // #2 = $T
+/* 11827*/ OPC_RecordChild2, // #3 = $F
+/* 11828*/ OPC_CheckType, MVT::f64,
+/* 11830*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11832*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11840*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 11849*/ /*Scope*/ 29, /*->11879*/
+/* 11850*/ OPC_CheckCondCode, ISD::SETLE,
+/* 11852*/ OPC_MoveParent,
+/* 11853*/ OPC_CheckType, MVT::i32,
+/* 11855*/ OPC_MoveParent,
+/* 11856*/ OPC_RecordChild1, // #2 = $T
+/* 11857*/ OPC_RecordChild2, // #3 = $F
+/* 11858*/ OPC_CheckType, MVT::f64,
+/* 11860*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11862*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 11870*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
+/* 11879*/ /*Scope*/ 29, /*->11909*/
+/* 11880*/ OPC_CheckCondCode, ISD::SETULE,
+/* 11882*/ OPC_MoveParent,
+/* 11883*/ OPC_CheckType, MVT::i32,
+/* 11885*/ OPC_MoveParent,
+/* 11886*/ OPC_RecordChild1, // #2 = $T
+/* 11887*/ OPC_RecordChild2, // #3 = $F
+/* 11888*/ OPC_CheckType, MVT::f64,
+/* 11890*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11892*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 11900*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
+/* 11909*/ /*Scope*/ 29, /*->11939*/
+/* 11910*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 11912*/ OPC_MoveParent,
+/* 11913*/ OPC_CheckType, MVT::i32,
+/* 11915*/ OPC_MoveParent,
+/* 11916*/ OPC_RecordChild1, // #2 = $T
+/* 11917*/ OPC_RecordChild2, // #3 = $F
+/* 11918*/ OPC_CheckType, MVT::f64,
+/* 11920*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11922*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11930*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 11939*/ /*Scope*/ 29, /*->11969*/
+/* 11940*/ OPC_CheckCondCode, ISD::SETNE,
+/* 11942*/ OPC_MoveParent,
+/* 11943*/ OPC_CheckType, MVT::i32,
+/* 11945*/ OPC_MoveParent,
+/* 11946*/ OPC_RecordChild1, // #2 = $T
+/* 11947*/ OPC_RecordChild2, // #3 = $F
+/* 11948*/ OPC_CheckType, MVT::f64,
+/* 11950*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11952*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11960*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 11969*/ /*Scope*/ 29, /*->11999*/
+/* 11970*/ OPC_CheckCondCode, ISD::SETGE,
+/* 11972*/ OPC_MoveParent,
+/* 11973*/ OPC_CheckType, MVT::i32,
+/* 11975*/ OPC_MoveParent,
+/* 11976*/ OPC_RecordChild1, // #2 = $T
+/* 11977*/ OPC_RecordChild2, // #3 = $F
+/* 11978*/ OPC_CheckType, MVT::f64,
+/* 11980*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 11982*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 11990*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
+/* 11999*/ /*Scope*/ 29, /*->12029*/
+/* 12000*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 12002*/ OPC_MoveParent,
+/* 12003*/ OPC_CheckType, MVT::i32,
+/* 12005*/ OPC_MoveParent,
+/* 12006*/ OPC_RecordChild1, // #2 = $T
+/* 12007*/ OPC_RecordChild2, // #3 = $F
+/* 12008*/ OPC_CheckType, MVT::f64,
+/* 12010*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12012*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12020*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
+/* 12029*/ /*Scope*/ 29, /*->12059*/
+/* 12030*/ OPC_CheckCondCode, ISD::SETLE,
+/* 12032*/ OPC_MoveParent,
+/* 12033*/ OPC_CheckType, MVT::i32,
+/* 12035*/ OPC_MoveParent,
+/* 12036*/ OPC_RecordChild1, // #2 = $T
+/* 12037*/ OPC_RecordChild2, // #3 = $F
+/* 12038*/ OPC_CheckType, MVT::f64,
+/* 12040*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12042*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 12050*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
+/* 12059*/ /*Scope*/ 29, /*->12089*/
+/* 12060*/ OPC_CheckCondCode, ISD::SETULE,
+/* 12062*/ OPC_MoveParent,
+/* 12063*/ OPC_CheckType, MVT::i32,
+/* 12065*/ OPC_MoveParent,
+/* 12066*/ OPC_RecordChild1, // #2 = $T
+/* 12067*/ OPC_RecordChild2, // #3 = $F
+/* 12068*/ OPC_CheckType, MVT::f64,
+/* 12070*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12072*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 12080*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
+/* 12089*/ /*Scope*/ 29, /*->12119*/
+/* 12090*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 12092*/ OPC_MoveParent,
+/* 12093*/ OPC_CheckType, MVT::i32,
+/* 12095*/ OPC_MoveParent,
+/* 12096*/ OPC_RecordChild1, // #2 = $T
+/* 12097*/ OPC_RecordChild2, // #3 = $F
+/* 12098*/ OPC_CheckType, MVT::f64,
+/* 12100*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12102*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12110*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
+/* 12119*/ /*Scope*/ 29, /*->12149*/
+/* 12120*/ OPC_CheckCondCode, ISD::SETNE,
+/* 12122*/ OPC_MoveParent,
+/* 12123*/ OPC_CheckType, MVT::i32,
+/* 12125*/ OPC_MoveParent,
+/* 12126*/ OPC_RecordChild1, // #2 = $T
+/* 12127*/ OPC_RecordChild2, // #3 = $F
+/* 12128*/ OPC_CheckType, MVT::f64,
+/* 12130*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12132*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12140*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
+/* 12149*/ /*Scope*/ 29, /*->12179*/
+/* 12150*/ OPC_CheckCondCode, ISD::SETGE,
+/* 12152*/ OPC_MoveParent,
+/* 12153*/ OPC_CheckType, MVT::i32,
+/* 12155*/ OPC_MoveParent,
+/* 12156*/ OPC_RecordChild1, // #2 = $T
+/* 12157*/ OPC_RecordChild2, // #3 = $F
+/* 12158*/ OPC_CheckType, MVT::f32,
+/* 12160*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 12162*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12170*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 12179*/ /*Scope*/ 29, /*->12209*/
+/* 12180*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 12182*/ OPC_MoveParent,
+/* 12183*/ OPC_CheckType, MVT::i32,
+/* 12185*/ OPC_MoveParent,
+/* 12186*/ OPC_RecordChild1, // #2 = $T
+/* 12187*/ OPC_RecordChild2, // #3 = $F
+/* 12188*/ OPC_CheckType, MVT::f32,
+/* 12190*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 12192*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12200*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 12209*/ /*Scope*/ 29, /*->12239*/
+/* 12210*/ OPC_CheckCondCode, ISD::SETLE,
+/* 12212*/ OPC_MoveParent,
+/* 12213*/ OPC_CheckType, MVT::i32,
+/* 12215*/ OPC_MoveParent,
+/* 12216*/ OPC_RecordChild1, // #2 = $T
+/* 12217*/ OPC_RecordChild2, // #3 = $F
+/* 12218*/ OPC_CheckType, MVT::f32,
+/* 12220*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 12222*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 12230*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
+/* 12239*/ /*Scope*/ 29, /*->12269*/
+/* 12240*/ OPC_CheckCondCode, ISD::SETULE,
+/* 12242*/ OPC_MoveParent,
+/* 12243*/ OPC_CheckType, MVT::i32,
+/* 12245*/ OPC_MoveParent,
+/* 12246*/ OPC_RecordChild1, // #2 = $T
+/* 12247*/ OPC_RecordChild2, // #3 = $F
+/* 12248*/ OPC_CheckType, MVT::f32,
+/* 12250*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 12252*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 12260*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
+/* 12269*/ /*Scope*/ 29, /*->12299*/
+/* 12270*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 12272*/ OPC_MoveParent,
+/* 12273*/ OPC_CheckType, MVT::i32,
+/* 12275*/ OPC_MoveParent,
+/* 12276*/ OPC_RecordChild1, // #2 = $T
+/* 12277*/ OPC_RecordChild2, // #3 = $F
+/* 12278*/ OPC_CheckType, MVT::f32,
+/* 12280*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 12282*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12290*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 12299*/ /*Scope*/ 29, /*->12329*/
+/* 12300*/ OPC_CheckCondCode, ISD::SETNE,
+/* 12302*/ OPC_MoveParent,
+/* 12303*/ OPC_CheckType, MVT::i32,
+/* 12305*/ OPC_MoveParent,
+/* 12306*/ OPC_RecordChild1, // #2 = $T
+/* 12307*/ OPC_RecordChild2, // #3 = $F
+/* 12308*/ OPC_CheckType, MVT::f32,
+/* 12310*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 12312*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12320*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 12329*/ /*Scope*/ 29, /*->12359*/
+/* 12330*/ OPC_CheckCondCode, ISD::SETGE,
+/* 12332*/ OPC_MoveParent,
+/* 12333*/ OPC_CheckType, MVT::i32,
+/* 12335*/ OPC_MoveParent,
+/* 12336*/ OPC_RecordChild1, // #2 = $T
+/* 12337*/ OPC_RecordChild2, // #3 = $F
+/* 12338*/ OPC_CheckType, MVT::f64,
+/* 12340*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 12342*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12350*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 12359*/ /*Scope*/ 29, /*->12389*/
+/* 12360*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 12362*/ OPC_MoveParent,
+/* 12363*/ OPC_CheckType, MVT::i32,
+/* 12365*/ OPC_MoveParent,
+/* 12366*/ OPC_RecordChild1, // #2 = $T
+/* 12367*/ OPC_RecordChild2, // #3 = $F
+/* 12368*/ OPC_CheckType, MVT::f64,
+/* 12370*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 12372*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12380*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 12389*/ /*Scope*/ 29, /*->12419*/
+/* 12390*/ OPC_CheckCondCode, ISD::SETLE,
+/* 12392*/ OPC_MoveParent,
+/* 12393*/ OPC_CheckType, MVT::i32,
+/* 12395*/ OPC_MoveParent,
+/* 12396*/ OPC_RecordChild1, // #2 = $T
+/* 12397*/ OPC_RecordChild2, // #3 = $F
+/* 12398*/ OPC_CheckType, MVT::f64,
+/* 12400*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 12402*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 12410*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
+/* 12419*/ /*Scope*/ 29, /*->12449*/
+/* 12420*/ OPC_CheckCondCode, ISD::SETULE,
+/* 12422*/ OPC_MoveParent,
+/* 12423*/ OPC_CheckType, MVT::i32,
+/* 12425*/ OPC_MoveParent,
+/* 12426*/ OPC_RecordChild1, // #2 = $T
+/* 12427*/ OPC_RecordChild2, // #3 = $F
+/* 12428*/ OPC_CheckType, MVT::f64,
+/* 12430*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 12432*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 12440*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
+/* 12449*/ /*Scope*/ 29, /*->12479*/
+/* 12450*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 12452*/ OPC_MoveParent,
+/* 12453*/ OPC_CheckType, MVT::i32,
+/* 12455*/ OPC_MoveParent,
+/* 12456*/ OPC_RecordChild1, // #2 = $T
+/* 12457*/ OPC_RecordChild2, // #3 = $F
+/* 12458*/ OPC_CheckType, MVT::f64,
+/* 12460*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 12462*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12470*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 12479*/ /*Scope*/ 29, /*->12509*/
+/* 12480*/ OPC_CheckCondCode, ISD::SETNE,
+/* 12482*/ OPC_MoveParent,
+/* 12483*/ OPC_CheckType, MVT::i32,
+/* 12485*/ OPC_MoveParent,
+/* 12486*/ OPC_RecordChild1, // #2 = $T
+/* 12487*/ OPC_RecordChild2, // #3 = $F
+/* 12488*/ OPC_CheckType, MVT::f64,
+/* 12490*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 12492*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12500*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
+/* 12509*/ 0, /*End of Scope*/
+/* 12510*/ 0, /*End of Scope*/
+/* 12511*/ 0, /*End of Scope*/
+/* 12512*/ /*Scope*/ 4|128,6/*772*/, /*->13286*/
+/* 12514*/ OPC_CheckChild0Type, MVT::i64,
+/* 12516*/ OPC_Scope, 93, /*->12611*/ // 2 children in Scope
+/* 12518*/ OPC_CheckChild1Integer, 0,
+/* 12520*/ OPC_MoveChild2,
+/* 12521*/ OPC_Scope, 21, /*->12544*/ // 4 children in Scope
+/* 12523*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 12525*/ OPC_MoveParent,
+/* 12526*/ OPC_CheckType, MVT::i32,
+/* 12528*/ OPC_MoveParent,
+/* 12529*/ OPC_RecordChild1, // #1 = $T
+/* 12530*/ OPC_RecordChild2, // #2 = $F
+/* 12531*/ OPC_CheckType, MVT::f32,
+/* 12533*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12535*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_S), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
+/* 12544*/ /*Scope*/ 21, /*->12566*/
+/* 12545*/ OPC_CheckCondCode, ISD::SETNE,
+/* 12547*/ OPC_MoveParent,
+/* 12548*/ OPC_CheckType, MVT::i32,
+/* 12550*/ OPC_MoveParent,
+/* 12551*/ OPC_RecordChild1, // #1 = $T
+/* 12552*/ OPC_RecordChild2, // #2 = $F
+/* 12553*/ OPC_CheckType, MVT::f32,
+/* 12555*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12557*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_S), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 11
+ // Dst: (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
+/* 12566*/ /*Scope*/ 21, /*->12588*/
+/* 12567*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 12569*/ OPC_MoveParent,
+/* 12570*/ OPC_CheckType, MVT::i32,
+/* 12572*/ OPC_MoveParent,
+/* 12573*/ OPC_RecordChild1, // #1 = $T
+/* 12574*/ OPC_RecordChild2, // #2 = $F
+/* 12575*/ OPC_CheckType, MVT::f64,
+/* 12577*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12579*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_D64), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 11
+ // Dst: (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
+/* 12588*/ /*Scope*/ 21, /*->12610*/
+/* 12589*/ OPC_CheckCondCode, ISD::SETNE,
+/* 12591*/ OPC_MoveParent,
+/* 12592*/ OPC_CheckType, MVT::i32,
+/* 12594*/ OPC_MoveParent,
+/* 12595*/ OPC_RecordChild1, // #1 = $T
+/* 12596*/ OPC_RecordChild2, // #2 = $F
+/* 12597*/ OPC_CheckType, MVT::f64,
+/* 12599*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12601*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_D64), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 11
+ // Dst: (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
+/* 12610*/ 0, /*End of Scope*/
+/* 12611*/ /*Scope*/ 32|128,5/*672*/, /*->13285*/
+/* 12613*/ OPC_RecordChild1, // #1 = $rhs
+/* 12614*/ OPC_Scope, 46|128,2/*302*/, /*->12919*/ // 2 children in Scope
+/* 12617*/ OPC_MoveChild1,
+/* 12618*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 12621*/ OPC_Scope, 70, /*->12693*/ // 4 children in Scope
+/* 12623*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 12625*/ OPC_MoveParent,
+/* 12626*/ OPC_MoveChild2,
+/* 12627*/ OPC_Scope, 31, /*->12660*/ // 2 children in Scope
+/* 12629*/ OPC_CheckCondCode, ISD::SETGE,
+/* 12631*/ OPC_MoveParent,
+/* 12632*/ OPC_CheckType, MVT::i32,
+/* 12634*/ OPC_MoveParent,
+/* 12635*/ OPC_RecordChild1, // #2 = $T
+/* 12636*/ OPC_RecordChild2, // #3 = $F
+/* 12637*/ OPC_CheckType, MVT::f32,
+/* 12639*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12641*/ OPC_EmitConvertToTarget, 1,
+/* 12643*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 12651*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs), FGR32:{ *:[f32] }:$F)
+/* 12660*/ /*Scope*/ 31, /*->12692*/
+/* 12661*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 12663*/ OPC_MoveParent,
+/* 12664*/ OPC_CheckType, MVT::i32,
+/* 12666*/ OPC_MoveParent,
+/* 12667*/ OPC_RecordChild1, // #2 = $T
+/* 12668*/ OPC_RecordChild2, // #3 = $F
+/* 12669*/ OPC_CheckType, MVT::f32,
+/* 12671*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12673*/ OPC_EmitConvertToTarget, 1,
+/* 12675*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 12683*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lh, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lh, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rh), FGR32:{ *:[f32] }:$F)
+/* 12692*/ 0, /*End of Scope*/
+/* 12693*/ /*Scope*/ 76, /*->12770*/
+/* 12694*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 12696*/ OPC_MoveParent,
+/* 12697*/ OPC_MoveChild2,
+/* 12698*/ OPC_Scope, 34, /*->12734*/ // 2 children in Scope
+/* 12700*/ OPC_CheckCondCode, ISD::SETGT,
+/* 12702*/ OPC_MoveParent,
+/* 12703*/ OPC_CheckType, MVT::i32,
+/* 12705*/ OPC_MoveParent,
+/* 12706*/ OPC_RecordChild1, // #2 = $T
+/* 12707*/ OPC_RecordChild2, // #3 = $F
+/* 12708*/ OPC_CheckType, MVT::f32,
+/* 12710*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12712*/ OPC_EmitConvertToTarget, 1,
+/* 12714*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 12717*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 12725*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), FGR32:{ *:[f32] }:$F)
+/* 12734*/ /*Scope*/ 34, /*->12769*/
+/* 12735*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 12737*/ OPC_MoveParent,
+/* 12738*/ OPC_CheckType, MVT::i32,
+/* 12740*/ OPC_MoveParent,
+/* 12741*/ OPC_RecordChild1, // #2 = $T
+/* 12742*/ OPC_RecordChild2, // #3 = $F
+/* 12743*/ OPC_CheckType, MVT::f32,
+/* 12745*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12747*/ OPC_EmitConvertToTarget, 1,
+/* 12749*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 12752*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 12760*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), FGR32:{ *:[f32] }:$F)
+/* 12769*/ 0, /*End of Scope*/
+/* 12770*/ /*Scope*/ 70, /*->12841*/
+/* 12771*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 12773*/ OPC_MoveParent,
+/* 12774*/ OPC_MoveChild2,
+/* 12775*/ OPC_Scope, 31, /*->12808*/ // 2 children in Scope
+/* 12777*/ OPC_CheckCondCode, ISD::SETGE,
+/* 12779*/ OPC_MoveParent,
+/* 12780*/ OPC_CheckType, MVT::i32,
+/* 12782*/ OPC_MoveParent,
+/* 12783*/ OPC_RecordChild1, // #2 = $T
+/* 12784*/ OPC_RecordChild2, // #3 = $F
+/* 12785*/ OPC_CheckType, MVT::f64,
+/* 12787*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12789*/ OPC_EmitConvertToTarget, 1,
+/* 12791*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 12799*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs), FGR64:{ *:[f64] }:$F)
+/* 12808*/ /*Scope*/ 31, /*->12840*/
+/* 12809*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 12811*/ OPC_MoveParent,
+/* 12812*/ OPC_CheckType, MVT::i32,
+/* 12814*/ OPC_MoveParent,
+/* 12815*/ OPC_RecordChild1, // #2 = $T
+/* 12816*/ OPC_RecordChild2, // #3 = $F
+/* 12817*/ OPC_CheckType, MVT::f64,
+/* 12819*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12821*/ OPC_EmitConvertToTarget, 1,
+/* 12823*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 4, // Results = #5
+/* 12831*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 5, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lh, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rh, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lh, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rh), FGR64:{ *:[f64] }:$F)
+/* 12840*/ 0, /*End of Scope*/
+/* 12841*/ /*Scope*/ 76, /*->12918*/
+/* 12842*/ OPC_CheckPredicate, 20, // Predicate_immSExt16Plus1
+/* 12844*/ OPC_MoveParent,
+/* 12845*/ OPC_MoveChild2,
+/* 12846*/ OPC_Scope, 34, /*->12882*/ // 2 children in Scope
+/* 12848*/ OPC_CheckCondCode, ISD::SETGT,
+/* 12850*/ OPC_MoveParent,
+/* 12851*/ OPC_CheckType, MVT::i32,
+/* 12853*/ OPC_MoveParent,
+/* 12854*/ OPC_RecordChild1, // #2 = $T
+/* 12855*/ OPC_RecordChild2, // #3 = $F
+/* 12856*/ OPC_CheckType, MVT::f64,
+/* 12858*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12860*/ OPC_EmitConvertToTarget, 1,
+/* 12862*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 12865*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 12873*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETGT:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), FGR64:{ *:[f64] }:$F)
+/* 12882*/ /*Scope*/ 34, /*->12917*/
+/* 12883*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 12885*/ OPC_MoveParent,
+/* 12886*/ OPC_CheckType, MVT::i32,
+/* 12888*/ OPC_MoveParent,
+/* 12889*/ OPC_RecordChild1, // #2 = $T
+/* 12890*/ OPC_RecordChild2, // #3 = $F
+/* 12891*/ OPC_CheckType, MVT::f64,
+/* 12893*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12895*/ OPC_EmitConvertToTarget, 1,
+/* 12897*/ OPC_EmitNodeXForm, 2, 4, // Plus1
+/* 12900*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 12908*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 6, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16Plus1>>:$rhs, SETUGT:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 10
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (Plus1:{ *:[i64] } (imm:{ *:[i64] }):$rhs)), FGR64:{ *:[f64] }:$F)
+/* 12917*/ 0, /*End of Scope*/
+/* 12918*/ 0, /*End of Scope*/
+/* 12919*/ /*Scope*/ 107|128,2/*363*/, /*->13284*/
+/* 12921*/ OPC_MoveChild2,
+/* 12922*/ OPC_Scope, 29, /*->12953*/ // 12 children in Scope
+/* 12924*/ OPC_CheckCondCode, ISD::SETGE,
+/* 12926*/ OPC_MoveParent,
+/* 12927*/ OPC_CheckType, MVT::i32,
+/* 12929*/ OPC_MoveParent,
+/* 12930*/ OPC_RecordChild1, // #2 = $T
+/* 12931*/ OPC_RecordChild2, // #3 = $F
+/* 12932*/ OPC_CheckType, MVT::f32,
+/* 12934*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12936*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12944*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 12953*/ /*Scope*/ 29, /*->12983*/
+/* 12954*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 12956*/ OPC_MoveParent,
+/* 12957*/ OPC_CheckType, MVT::i32,
+/* 12959*/ OPC_MoveParent,
+/* 12960*/ OPC_RecordChild1, // #2 = $T
+/* 12961*/ OPC_RecordChild2, // #3 = $F
+/* 12962*/ OPC_CheckType, MVT::f32,
+/* 12964*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12966*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 12974*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 12983*/ /*Scope*/ 29, /*->13013*/
+/* 12984*/ OPC_CheckCondCode, ISD::SETLE,
+/* 12986*/ OPC_MoveParent,
+/* 12987*/ OPC_CheckType, MVT::i32,
+/* 12989*/ OPC_MoveParent,
+/* 12990*/ OPC_RecordChild1, // #2 = $T
+/* 12991*/ OPC_RecordChild2, // #3 = $F
+/* 12992*/ OPC_CheckType, MVT::f32,
+/* 12994*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 12996*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 13004*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
+/* 13013*/ /*Scope*/ 29, /*->13043*/
+/* 13014*/ OPC_CheckCondCode, ISD::SETULE,
+/* 13016*/ OPC_MoveParent,
+/* 13017*/ OPC_CheckType, MVT::i32,
+/* 13019*/ OPC_MoveParent,
+/* 13020*/ OPC_RecordChild1, // #2 = $T
+/* 13021*/ OPC_RecordChild2, // #3 = $F
+/* 13022*/ OPC_CheckType, MVT::f32,
+/* 13024*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13026*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 13034*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
+/* 13043*/ /*Scope*/ 29, /*->13073*/
+/* 13044*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 13046*/ OPC_MoveParent,
+/* 13047*/ OPC_CheckType, MVT::i32,
+/* 13049*/ OPC_MoveParent,
+/* 13050*/ OPC_RecordChild1, // #2 = $T
+/* 13051*/ OPC_RecordChild2, // #3 = $F
+/* 13052*/ OPC_CheckType, MVT::f32,
+/* 13054*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13056*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #4
+/* 13064*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 13073*/ /*Scope*/ 29, /*->13103*/
+/* 13074*/ OPC_CheckCondCode, ISD::SETNE,
+/* 13076*/ OPC_MoveParent,
+/* 13077*/ OPC_CheckType, MVT::i32,
+/* 13079*/ OPC_MoveParent,
+/* 13080*/ OPC_RecordChild1, // #2 = $T
+/* 13081*/ OPC_RecordChild2, // #3 = $F
+/* 13082*/ OPC_CheckType, MVT::f32,
+/* 13084*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13086*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #4
+/* 13094*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 6
+ // Dst: (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
+/* 13103*/ /*Scope*/ 29, /*->13133*/
+/* 13104*/ OPC_CheckCondCode, ISD::SETGE,
+/* 13106*/ OPC_MoveParent,
+/* 13107*/ OPC_CheckType, MVT::i32,
+/* 13109*/ OPC_MoveParent,
+/* 13110*/ OPC_RecordChild1, // #2 = $T
+/* 13111*/ OPC_RecordChild2, // #3 = $F
+/* 13112*/ OPC_CheckType, MVT::f64,
+/* 13114*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13116*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 13124*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
+/* 13133*/ /*Scope*/ 29, /*->13163*/
+/* 13134*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 13136*/ OPC_MoveParent,
+/* 13137*/ OPC_CheckType, MVT::i32,
+/* 13139*/ OPC_MoveParent,
+/* 13140*/ OPC_RecordChild1, // #2 = $T
+/* 13141*/ OPC_RecordChild2, // #3 = $F
+/* 13142*/ OPC_CheckType, MVT::f64,
+/* 13144*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13146*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 13154*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
+/* 13163*/ /*Scope*/ 29, /*->13193*/
+/* 13164*/ OPC_CheckCondCode, ISD::SETLE,
+/* 13166*/ OPC_MoveParent,
+/* 13167*/ OPC_CheckType, MVT::i32,
+/* 13169*/ OPC_MoveParent,
+/* 13170*/ OPC_RecordChild1, // #2 = $T
+/* 13171*/ OPC_RecordChild2, // #3 = $F
+/* 13172*/ OPC_CheckType, MVT::f64,
+/* 13174*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13176*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 13184*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
+/* 13193*/ /*Scope*/ 29, /*->13223*/
+/* 13194*/ OPC_CheckCondCode, ISD::SETULE,
+/* 13196*/ OPC_MoveParent,
+/* 13197*/ OPC_CheckType, MVT::i32,
+/* 13199*/ OPC_MoveParent,
+/* 13200*/ OPC_RecordChild1, // #2 = $T
+/* 13201*/ OPC_RecordChild2, // #3 = $F
+/* 13202*/ OPC_CheckType, MVT::f64,
+/* 13204*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13206*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #4
+/* 13214*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
+/* 13223*/ /*Scope*/ 29, /*->13253*/
+/* 13224*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 13226*/ OPC_MoveParent,
+/* 13227*/ OPC_CheckType, MVT::i32,
+/* 13229*/ OPC_MoveParent,
+/* 13230*/ OPC_RecordChild1, // #2 = $T
+/* 13231*/ OPC_RecordChild2, // #3 = $F
+/* 13232*/ OPC_CheckType, MVT::f64,
+/* 13234*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13236*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #4
+/* 13244*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVZ_I64_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
+/* 13253*/ /*Scope*/ 29, /*->13283*/
+/* 13254*/ OPC_CheckCondCode, ISD::SETNE,
+/* 13256*/ OPC_MoveParent,
+/* 13257*/ OPC_CheckType, MVT::i32,
+/* 13259*/ OPC_MoveParent,
+/* 13260*/ OPC_RecordChild1, // #2 = $T
+/* 13261*/ OPC_RecordChild2, // #3 = $F
+/* 13262*/ OPC_CheckType, MVT::f64,
+/* 13264*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13266*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #4
+/* 13274*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 4, 3,
+ // Src: (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 6
+ // Dst: (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
+/* 13283*/ 0, /*End of Scope*/
+/* 13284*/ 0, /*End of Scope*/
+/* 13285*/ 0, /*End of Scope*/
+/* 13286*/ 0, /*End of Scope*/
+/* 13287*/ /*Scope*/ 44|128,1/*172*/, /*->13461*/
+/* 13289*/ OPC_RecordChild0, // #0 = $cond
+/* 13290*/ OPC_Scope, 6|128,1/*134*/, /*->13427*/ // 2 children in Scope
+/* 13293*/ OPC_CheckChild0Type, MVT::i32,
+/* 13295*/ OPC_RecordChild1, // #1 = $T
+/* 13296*/ OPC_RecordChild2, // #2 = $F
+/* 13297*/ OPC_SwitchType /*2 cases */, 62, MVT::f32,// ->13362
+/* 13300*/ OPC_Scope, 11, /*->13313*/ // 5 children in Scope
+/* 13302*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13304*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_S), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
+/* 13313*/ /*Scope*/ 11, /*->13325*/
+/* 13314*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 13316*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEL_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 2, 1,
+ // Src: (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 13325*/ /*Scope*/ 11, /*->13337*/
+/* 13326*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 13328*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
+/* 13337*/ /*Scope*/ 11, /*->13349*/
+/* 13338*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 13340*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEL_S_MMR6), 0,
+ MVT::f32, 3/*#Ops*/, 0, 2, 1,
+ // Src: (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 13349*/ /*Scope*/ 11, /*->13361*/
+/* 13350*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 13352*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECT_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
+/* 13361*/ 0, /*End of Scope*/
+/* 13362*/ /*SwitchType*/ 62, MVT::f64,// ->13426
+/* 13364*/ OPC_Scope, 11, /*->13377*/ // 5 children in Scope
+/* 13366*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13368*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D32), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
+/* 13377*/ /*Scope*/ 11, /*->13389*/
+/* 13378*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13380*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D64), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
+/* 13389*/ /*Scope*/ 11, /*->13401*/
+/* 13390*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 13392*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
+/* 13401*/ /*Scope*/ 11, /*->13413*/
+/* 13402*/ OPC_CheckPatternPredicate, 41, // (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips4_32())
+/* 13404*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECT_D32), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
+/* 13413*/ /*Scope*/ 11, /*->13425*/
+/* 13414*/ OPC_CheckPatternPredicate, 42, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips4_32())
+/* 13416*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECT_D64), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
+/* 13425*/ 0, /*End of Scope*/
+/* 13426*/ 0, // EndSwitchType
+/* 13427*/ /*Scope*/ 32, /*->13460*/
+/* 13428*/ OPC_CheckChild0Type, MVT::i64,
+/* 13430*/ OPC_RecordChild1, // #1 = $T
+/* 13431*/ OPC_RecordChild2, // #2 = $F
+/* 13432*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->13446
+/* 13435*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13437*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_S), 0,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
+/* 13446*/ /*SwitchType*/ 11, MVT::f64,// ->13459
+/* 13448*/ OPC_CheckPatternPredicate, 38, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13450*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVN_I64_D64), 0,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
+/* 13459*/ 0, // EndSwitchType
+/* 13460*/ 0, /*End of Scope*/
+/* 13461*/ 0, /*End of Scope*/
+/* 13462*/ /*SwitchOpcode*/ 55|128,1/*183*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->13649
+/* 13466*/ OPC_RecordMemRef,
+/* 13467*/ OPC_RecordNode, // #0 = 'atomic_load' chained node
+/* 13468*/ OPC_RecordChild1, // #1 = $a
+/* 13469*/ OPC_SwitchType /*2 cases */, 104, MVT::i32,// ->13576
+/* 13472*/ OPC_Scope, 16, /*->13490*/ // 6 children in Scope
+/* 13474*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_8
+/* 13476*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 13478*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13481*/ OPC_EmitMergeInputChains1_0,
+/* 13482*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_8>> - Complexity = 13
+ // Dst: (LB:{ *:[i32] } addr:{ *:[iPTR] }:$a)
+/* 13490*/ /*Scope*/ 16, /*->13507*/
+/* 13491*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_16
+/* 13493*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 13495*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13498*/ OPC_EmitMergeInputChains1_0,
+/* 13499*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_16>> - Complexity = 13
+ // Dst: (LH:{ *:[i32] } addr:{ *:[iPTR] }:$a)
+/* 13507*/ /*Scope*/ 16, /*->13524*/
+/* 13508*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_32
+/* 13510*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 13512*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13515*/ OPC_EmitMergeInputChains1_0,
+/* 13516*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_32>> - Complexity = 13
+ // Dst: (LW:{ *:[i32] } addr:{ *:[iPTR] }:$a)
+/* 13524*/ /*Scope*/ 16, /*->13541*/
+/* 13525*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_8
+/* 13527*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 13529*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13532*/ OPC_EmitMergeInputChains1_0,
+/* 13533*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_8>> - Complexity = 13
+ // Dst: (LB_MM:{ *:[i32] } addr:{ *:[i32] }:$a)
+/* 13541*/ /*Scope*/ 16, /*->13558*/
+/* 13542*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_16
+/* 13544*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 13546*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13549*/ OPC_EmitMergeInputChains1_0,
+/* 13550*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_16>> - Complexity = 13
+ // Dst: (LH_MM:{ *:[i32] } addr:{ *:[iPTR] }:$a)
+/* 13558*/ /*Scope*/ 16, /*->13575*/
+/* 13559*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_32
+/* 13561*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 13563*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13566*/ OPC_EmitMergeInputChains1_0,
+/* 13567*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_32>> - Complexity = 13
+ // Dst: (LW_MM:{ *:[i32] } addr:{ *:[iPTR] }:$a)
+/* 13575*/ 0, /*End of Scope*/
+/* 13576*/ /*SwitchType*/ 70, MVT::i64,// ->13648
+/* 13578*/ OPC_Scope, 16, /*->13596*/ // 4 children in Scope
+/* 13580*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_8
+/* 13582*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 13584*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13587*/ OPC_EmitMergeInputChains1_0,
+/* 13588*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LB64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i64] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_8>> - Complexity = 13
+ // Dst: (LB64:{ *:[i64] } addr:{ *:[iPTR] }:$a)
+/* 13596*/ /*Scope*/ 16, /*->13613*/
+/* 13597*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_16
+/* 13599*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 13601*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13604*/ OPC_EmitMergeInputChains1_0,
+/* 13605*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LH64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i64] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_16>> - Complexity = 13
+ // Dst: (LH64:{ *:[i64] } addr:{ *:[iPTR] }:$a)
+/* 13613*/ /*Scope*/ 16, /*->13630*/
+/* 13614*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_32
+/* 13616*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 13618*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13621*/ OPC_EmitMergeInputChains1_0,
+/* 13622*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LW64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i64] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_32>> - Complexity = 13
+ // Dst: (LW64:{ *:[i64] } addr:{ *:[iPTR] }:$a)
+/* 13630*/ /*Scope*/ 16, /*->13647*/
+/* 13631*/ OPC_CheckPredicate, 27, // Predicate_atomic_load_64
+/* 13633*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 13635*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #2 #3
+/* 13638*/ OPC_EmitMergeInputChains1_0,
+/* 13639*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i64] } addr:{ *:[iPTR] }:$a)<<P:Predicate_atomic_load_64>> - Complexity = 13
+ // Dst: (LD:{ *:[i64] } addr:{ *:[iPTR] }:$a)
+/* 13647*/ 0, /*End of Scope*/
+/* 13648*/ 0, // EndSwitchType
+/* 13649*/ /*SwitchOpcode*/ 7|128,1/*135*/, TARGET_VAL(ISD::ATOMIC_STORE),// ->13788
+/* 13653*/ OPC_RecordMemRef,
+/* 13654*/ OPC_RecordNode, // #0 = 'atomic_store' chained node
+/* 13655*/ OPC_RecordChild1, // #1 = $a
+/* 13656*/ OPC_RecordChild2, // #2 = $v
+/* 13657*/ OPC_Scope, 55, /*->13714*/ // 2 children in Scope
+/* 13659*/ OPC_CheckChild2Type, MVT::i32,
+/* 13661*/ OPC_Scope, 16, /*->13679*/ // 3 children in Scope
+/* 13663*/ OPC_CheckPredicate, 24, // Predicate_atomic_store_8
+/* 13665*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 13667*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #3 #4
+/* 13670*/ OPC_EmitMergeInputChains1_0,
+/* 13671*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store addr:{ *:[iPTR] }:$a, GPR32:{ *:[i32] }:$v)<<P:Predicate_atomic_store_8>> - Complexity = 13
+ // Dst: (SB GPR32:{ *:[i32] }:$v, addr:{ *:[iPTR] }:$a)
+/* 13679*/ /*Scope*/ 16, /*->13696*/
+/* 13680*/ OPC_CheckPredicate, 25, // Predicate_atomic_store_16
+/* 13682*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 13684*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #3 #4
+/* 13687*/ OPC_EmitMergeInputChains1_0,
+/* 13688*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store addr:{ *:[iPTR] }:$a, GPR32:{ *:[i32] }:$v)<<P:Predicate_atomic_store_16>> - Complexity = 13
+ // Dst: (SH GPR32:{ *:[i32] }:$v, addr:{ *:[iPTR] }:$a)
+/* 13696*/ /*Scope*/ 16, /*->13713*/
+/* 13697*/ OPC_CheckPredicate, 26, // Predicate_atomic_store_32
+/* 13699*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 13701*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #3 #4
+/* 13704*/ OPC_EmitMergeInputChains1_0,
+/* 13705*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store addr:{ *:[iPTR] }:$a, GPR32:{ *:[i32] }:$v)<<P:Predicate_atomic_store_32>> - Complexity = 13
+ // Dst: (SW GPR32:{ *:[i32] }:$v, addr:{ *:[iPTR] }:$a)
+/* 13713*/ 0, /*End of Scope*/
+/* 13714*/ /*Scope*/ 72, /*->13787*/
+/* 13715*/ OPC_CheckChild2Type, MVT::i64,
+/* 13717*/ OPC_Scope, 16, /*->13735*/ // 4 children in Scope
+/* 13719*/ OPC_CheckPredicate, 24, // Predicate_atomic_store_8
+/* 13721*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 13723*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #3 #4
+/* 13726*/ OPC_EmitMergeInputChains1_0,
+/* 13727*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SB64), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store addr:{ *:[iPTR] }:$a, GPR64:{ *:[i64] }:$v)<<P:Predicate_atomic_store_8>> - Complexity = 13
+ // Dst: (SB64 GPR64:{ *:[i64] }:$v, addr:{ *:[iPTR] }:$a)
+/* 13735*/ /*Scope*/ 16, /*->13752*/
+/* 13736*/ OPC_CheckPredicate, 25, // Predicate_atomic_store_16
+/* 13738*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 13740*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #3 #4
+/* 13743*/ OPC_EmitMergeInputChains1_0,
+/* 13744*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SH64), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store addr:{ *:[iPTR] }:$a, GPR64:{ *:[i64] }:$v)<<P:Predicate_atomic_store_16>> - Complexity = 13
+ // Dst: (SH64 GPR64:{ *:[i64] }:$v, addr:{ *:[iPTR] }:$a)
+/* 13752*/ /*Scope*/ 16, /*->13769*/
+/* 13753*/ OPC_CheckPredicate, 26, // Predicate_atomic_store_32
+/* 13755*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 13757*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #3 #4
+/* 13760*/ OPC_EmitMergeInputChains1_0,
+/* 13761*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SW64), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store addr:{ *:[iPTR] }:$a, GPR64:{ *:[i64] }:$v)<<P:Predicate_atomic_store_32>> - Complexity = 13
+ // Dst: (SW64 GPR64:{ *:[i64] }:$v, addr:{ *:[iPTR] }:$a)
+/* 13769*/ /*Scope*/ 16, /*->13786*/
+/* 13770*/ OPC_CheckPredicate, 27, // Predicate_atomic_store_64
+/* 13772*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 13774*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$a #3 #4
+/* 13777*/ OPC_EmitMergeInputChains1_0,
+/* 13778*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store addr:{ *:[iPTR] }:$a, GPR64:{ *:[i64] }:$v)<<P:Predicate_atomic_store_64>> - Complexity = 13
+ // Dst: (SD GPR64:{ *:[i64] }:$v, addr:{ *:[iPTR] }:$a)
+/* 13786*/ 0, /*End of Scope*/
+/* 13787*/ 0, /*End of Scope*/
+/* 13788*/ /*SwitchOpcode*/ 75, TARGET_VAL(MipsISD::LWL),// ->13866
+/* 13791*/ OPC_RecordMemRef,
+/* 13792*/ OPC_RecordNode, // #0 = 'MipsLWL' chained node
+/* 13793*/ OPC_RecordChild1, // #1 = $addr
+/* 13794*/ OPC_RecordChild2, // #2 = $src
+/* 13795*/ OPC_SwitchType /*2 cases */, 50, MVT::i32,// ->13848
+/* 13798*/ OPC_Scope, 15, /*->13815*/ // 3 children in Scope
+/* 13800*/ OPC_CheckPatternPredicate, 10, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13802*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #3 #4
+/* 13805*/ OPC_EmitMergeInputChains1_0,
+/* 13806*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLWL:{ *:[i32] } addr:{ *:[iPTR] }:$addr, GPR32Opnd:{ *:[i32] }:$src) - Complexity = 12
+ // Dst: (LWL:{ *:[i32] } addr:{ *:[iPTR] }:$addr, GPR32Opnd:{ *:[i32] }:$src)
+/* 13815*/ /*Scope*/ 15, /*->13831*/
+/* 13816*/ OPC_CheckPatternPredicate, 43, // (Subtarget->hasEVA()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 13818*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // selectIntAddr12MM:$addr #3 #4
+/* 13821*/ OPC_EmitMergeInputChains1_0,
+/* 13822*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWLE_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLWL:{ *:[i32] } addrimm12:{ *:[iPTR] }:$addr, GPR32Opnd:{ *:[i32] }:$src) - Complexity = 12
+ // Dst: (LWLE_MM:{ *:[i32] } addrimm12:{ *:[i32] }:$addr, GPR32Opnd:{ *:[i32] }:$src)
+/* 13831*/ /*Scope*/ 15, /*->13847*/
+/* 13832*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 13834*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // selectIntAddr12MM:$addr #3 #4
+/* 13837*/ OPC_EmitMergeInputChains1_0,
+/* 13838*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWL_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLWL:{ *:[i32] } addrimm12:{ *:[iPTR] }:$addr, GPR32Opnd:{ *:[i32] }:$src) - Complexity = 12
+ // Dst: (LWL_MM:{ *:[i32] } addrimm12:{ *:[i32] }:$addr, GPR32Opnd:{ *:[i32] }:$src)
+/* 13847*/ 0, /*End of Scope*/
+/* 13848*/ /*SwitchType*/ 15, MVT::i64,// ->13865
+/* 13850*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 13852*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #3 #4
+/* 13855*/ OPC_EmitMergeInputChains1_0,
+/* 13856*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWL64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLWL:{ *:[i64] } addr:{ *:[iPTR] }:$addr, GPR64Opnd:{ *:[i64] }:$src) - Complexity = 12
+ // Dst: (LWL64:{ *:[i64] } addr:{ *:[iPTR] }:$addr, GPR64Opnd:{ *:[i64] }:$src)
+/* 13865*/ 0, // EndSwitchType
+/* 13866*/ /*SwitchOpcode*/ 75, TARGET_VAL(MipsISD::LWR),// ->13944
+/* 13869*/ OPC_RecordMemRef,
+/* 13870*/ OPC_RecordNode, // #0 = 'MipsLWR' chained node
+/* 13871*/ OPC_RecordChild1, // #1 = $addr
+/* 13872*/ OPC_RecordChild2, // #2 = $src
+/* 13873*/ OPC_SwitchType /*2 cases */, 50, MVT::i32,// ->13926
+/* 13876*/ OPC_Scope, 15, /*->13893*/ // 3 children in Scope
+/* 13878*/ OPC_CheckPatternPredicate, 10, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13880*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #3 #4
+/* 13883*/ OPC_EmitMergeInputChains1_0,
+/* 13884*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWR), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLWR:{ *:[i32] } addr:{ *:[iPTR] }:$addr, GPR32Opnd:{ *:[i32] }:$src) - Complexity = 12
+ // Dst: (LWR:{ *:[i32] } addr:{ *:[iPTR] }:$addr, GPR32Opnd:{ *:[i32] }:$src)
+/* 13893*/ /*Scope*/ 15, /*->13909*/
+/* 13894*/ OPC_CheckPatternPredicate, 43, // (Subtarget->hasEVA()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 13896*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // selectIntAddr12MM:$addr #3 #4
+/* 13899*/ OPC_EmitMergeInputChains1_0,
+/* 13900*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWRE_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLWR:{ *:[i32] } addrimm12:{ *:[iPTR] }:$addr, GPR32Opnd:{ *:[i32] }:$src) - Complexity = 12
+ // Dst: (LWRE_MM:{ *:[i32] } addrimm12:{ *:[i32] }:$addr, GPR32Opnd:{ *:[i32] }:$src)
+/* 13909*/ /*Scope*/ 15, /*->13925*/
+/* 13910*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 13912*/ OPC_CheckComplexPat, /*CP*/12, /*#*/1, // selectIntAddr12MM:$addr #3 #4
+/* 13915*/ OPC_EmitMergeInputChains1_0,
+/* 13916*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWR_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLWR:{ *:[i32] } addrimm12:{ *:[iPTR] }:$addr, GPR32Opnd:{ *:[i32] }:$src) - Complexity = 12
+ // Dst: (LWR_MM:{ *:[i32] } addrimm12:{ *:[i32] }:$addr, GPR32Opnd:{ *:[i32] }:$src)
+/* 13925*/ 0, /*End of Scope*/
+/* 13926*/ /*SwitchType*/ 15, MVT::i64,// ->13943
+/* 13928*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 13930*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #3 #4
+/* 13933*/ OPC_EmitMergeInputChains1_0,
+/* 13934*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWR64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLWR:{ *:[i64] } addr:{ *:[iPTR] }:$addr, GPR64Opnd:{ *:[i64] }:$src) - Complexity = 12
+ // Dst: (LWR64:{ *:[i64] } addr:{ *:[iPTR] }:$addr, GPR64Opnd:{ *:[i64] }:$src)
+/* 13943*/ 0, // EndSwitchType
+/* 13944*/ /*SwitchOpcode*/ 74, TARGET_VAL(MipsISD::SWL),// ->14021
+/* 13947*/ OPC_RecordMemRef,
+/* 13948*/ OPC_RecordNode, // #0 = 'MipsSWL' chained node
+/* 13949*/ OPC_RecordChild1, // #1 = $rt
+/* 13950*/ OPC_Scope, 50, /*->14002*/ // 2 children in Scope
+/* 13952*/ OPC_CheckChild1Type, MVT::i32,
+/* 13954*/ OPC_RecordChild2, // #2 = $addr
+/* 13955*/ OPC_Scope, 14, /*->13971*/ // 3 children in Scope
+/* 13957*/ OPC_CheckPatternPredicate, 10, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 13959*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 13962*/ OPC_EmitMergeInputChains1_0,
+/* 13963*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWL), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSWL GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SWL GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 13971*/ /*Scope*/ 14, /*->13986*/
+/* 13972*/ OPC_CheckPatternPredicate, 43, // (Subtarget->hasEVA()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 13974*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // selectIntAddr12MM:$addr #3 #4
+/* 13977*/ OPC_EmitMergeInputChains1_0,
+/* 13978*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWLE_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSWL GPR32Opnd:{ *:[i32] }:$rt, addrimm12:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SWLE_MM GPR32Opnd:{ *:[i32] }:$rt, addrimm12:{ *:[i32] }:$addr)
+/* 13986*/ /*Scope*/ 14, /*->14001*/
+/* 13987*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 13989*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // selectIntAddr12MM:$addr #3 #4
+/* 13992*/ OPC_EmitMergeInputChains1_0,
+/* 13993*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWL_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSWL GPR32Opnd:{ *:[i32] }:$rt, addrimm12:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SWL_MM GPR32Opnd:{ *:[i32] }:$rt, addrimm12:{ *:[i32] }:$addr)
+/* 14001*/ 0, /*End of Scope*/
+/* 14002*/ /*Scope*/ 17, /*->14020*/
+/* 14003*/ OPC_CheckChild1Type, MVT::i64,
+/* 14005*/ OPC_RecordChild2, // #2 = $addr
+/* 14006*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 14008*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 14011*/ OPC_EmitMergeInputChains1_0,
+/* 14012*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWL64), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSWL GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SWL64 GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 14020*/ 0, /*End of Scope*/
+/* 14021*/ /*SwitchOpcode*/ 74, TARGET_VAL(MipsISD::SWR),// ->14098
+/* 14024*/ OPC_RecordMemRef,
+/* 14025*/ OPC_RecordNode, // #0 = 'MipsSWR' chained node
+/* 14026*/ OPC_RecordChild1, // #1 = $rt
+/* 14027*/ OPC_Scope, 50, /*->14079*/ // 2 children in Scope
+/* 14029*/ OPC_CheckChild1Type, MVT::i32,
+/* 14031*/ OPC_RecordChild2, // #2 = $addr
+/* 14032*/ OPC_Scope, 14, /*->14048*/ // 3 children in Scope
+/* 14034*/ OPC_CheckPatternPredicate, 10, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 14036*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 14039*/ OPC_EmitMergeInputChains1_0,
+/* 14040*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWR), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSWR GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SWR GPR32Opnd:{ *:[i32] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 14048*/ /*Scope*/ 14, /*->14063*/
+/* 14049*/ OPC_CheckPatternPredicate, 43, // (Subtarget->hasEVA()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 14051*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // selectIntAddr12MM:$addr #3 #4
+/* 14054*/ OPC_EmitMergeInputChains1_0,
+/* 14055*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWRE_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSWR GPR32Opnd:{ *:[i32] }:$rt, addrimm12:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SWRE_MM GPR32Opnd:{ *:[i32] }:$rt, addrimm12:{ *:[i32] }:$addr)
+/* 14063*/ /*Scope*/ 14, /*->14078*/
+/* 14064*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 14066*/ OPC_CheckComplexPat, /*CP*/12, /*#*/2, // selectIntAddr12MM:$addr #3 #4
+/* 14069*/ OPC_EmitMergeInputChains1_0,
+/* 14070*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWR_MM), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSWR GPR32Opnd:{ *:[i32] }:$rt, addrimm12:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SWR_MM GPR32Opnd:{ *:[i32] }:$rt, addrimm12:{ *:[i32] }:$addr)
+/* 14078*/ 0, /*End of Scope*/
+/* 14079*/ /*Scope*/ 17, /*->14097*/
+/* 14080*/ OPC_CheckChild1Type, MVT::i64,
+/* 14082*/ OPC_RecordChild2, // #2 = $addr
+/* 14083*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 14085*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 14088*/ OPC_EmitMergeInputChains1_0,
+/* 14089*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SWR64), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSWR GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SWR64 GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 14097*/ 0, /*End of Scope*/
+/* 14098*/ /*SwitchOpcode*/ 21, TARGET_VAL(MipsISD::LDL),// ->14122
+/* 14101*/ OPC_RecordMemRef,
+/* 14102*/ OPC_RecordNode, // #0 = 'MipsLDL' chained node
+/* 14103*/ OPC_RecordChild1, // #1 = $addr
+/* 14104*/ OPC_RecordChild2, // #2 = $src
+/* 14105*/ OPC_CheckType, MVT::i64,
+/* 14107*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 14109*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #3 #4
+/* 14112*/ OPC_EmitMergeInputChains1_0,
+/* 14113*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLDL:{ *:[i64] } addr:{ *:[iPTR] }:$addr, GPR64Opnd:{ *:[i64] }:$src) - Complexity = 12
+ // Dst: (LDL:{ *:[i64] } addr:{ *:[iPTR] }:$addr, GPR64Opnd:{ *:[i64] }:$src)
+/* 14122*/ /*SwitchOpcode*/ 21, TARGET_VAL(MipsISD::LDR),// ->14146
+/* 14125*/ OPC_RecordMemRef,
+/* 14126*/ OPC_RecordNode, // #0 = 'MipsLDR' chained node
+/* 14127*/ OPC_RecordChild1, // #1 = $addr
+/* 14128*/ OPC_RecordChild2, // #2 = $src
+/* 14129*/ OPC_CheckType, MVT::i64,
+/* 14131*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 14133*/ OPC_CheckComplexPat, /*CP*/1, /*#*/1, // selectIntAddr:$addr #3 #4
+/* 14136*/ OPC_EmitMergeInputChains1_0,
+/* 14137*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LDR), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 3/*#Ops*/, 3, 4, 2,
+ // Src: (MipsLDR:{ *:[i64] } addr:{ *:[iPTR] }:$addr, GPR64Opnd:{ *:[i64] }:$src) - Complexity = 12
+ // Dst: (LDR:{ *:[i64] } addr:{ *:[iPTR] }:$addr, GPR64Opnd:{ *:[i64] }:$src)
+/* 14146*/ /*SwitchOpcode*/ 20, TARGET_VAL(MipsISD::SDL),// ->14169
+/* 14149*/ OPC_RecordMemRef,
+/* 14150*/ OPC_RecordNode, // #0 = 'MipsSDL' chained node
+/* 14151*/ OPC_RecordChild1, // #1 = $rt
+/* 14152*/ OPC_CheckChild1Type, MVT::i64,
+/* 14154*/ OPC_RecordChild2, // #2 = $addr
+/* 14155*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 14157*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 14160*/ OPC_EmitMergeInputChains1_0,
+/* 14161*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDL), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSDL GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SDL GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 14169*/ /*SwitchOpcode*/ 20, TARGET_VAL(MipsISD::SDR),// ->14192
+/* 14172*/ OPC_RecordMemRef,
+/* 14173*/ OPC_RecordNode, // #0 = 'MipsSDR' chained node
+/* 14174*/ OPC_RecordChild1, // #1 = $rt
+/* 14175*/ OPC_CheckChild1Type, MVT::i64,
+/* 14177*/ OPC_RecordChild2, // #2 = $addr
+/* 14178*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 14180*/ OPC_CheckComplexPat, /*CP*/1, /*#*/2, // selectIntAddr:$addr #3 #4
+/* 14183*/ OPC_EmitMergeInputChains1_0,
+/* 14184*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SDR), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (MipsSDR GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr) - Complexity = 12
+ // Dst: (SDR GPR64Opnd:{ *:[i64] }:$rt, addr:{ *:[iPTR] }:$addr)
+/* 14192*/ /*SwitchOpcode*/ 121|128,10/*1401*/, TARGET_VAL(ISD::INTRINSIC_W_CHAIN),// ->15597
+/* 14196*/ OPC_RecordNode, // #0 = 'intrinsic_w_chain' chained node
+/* 14197*/ OPC_Scope, 69, /*->14268*/ // 42 children in Scope
+/* 14199*/ OPC_CheckChild1Integer, 31|128,27/*3487*/,
+/* 14202*/ OPC_RecordChild2, // #1 = $rt
+/* 14203*/ OPC_RecordChild3, // #2 = $rs_sa
+/* 14204*/ OPC_Scope, 37, /*->14243*/ // 3 children in Scope
+/* 14206*/ OPC_MoveChild3,
+/* 14207*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 14210*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 14212*/ OPC_MoveParent,
+/* 14213*/ OPC_Scope, 13, /*->14228*/ // 2 children in Scope
+/* 14215*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14217*/ OPC_EmitMergeInputChains1_0,
+/* 14218*/ OPC_EmitConvertToTarget, 2,
+/* 14220*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLL_S_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) - Complexity = 12
+ // Dst: (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+/* 14228*/ /*Scope*/ 13, /*->14242*/
+/* 14229*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14231*/ OPC_EmitMergeInputChains1_0,
+/* 14232*/ OPC_EmitConvertToTarget, 2,
+/* 14234*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLL_S_W_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
+/* 14242*/ 0, /*End of Scope*/
+/* 14243*/ /*Scope*/ 11, /*->14255*/
+/* 14244*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14246*/ OPC_EmitMergeInputChains1_0,
+/* 14247*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLLV_S_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 14255*/ /*Scope*/ 11, /*->14267*/
+/* 14256*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14258*/ OPC_EmitMergeInputChains1_0,
+/* 14259*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLLV_S_W_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 14267*/ 0, /*End of Scope*/
+/* 14268*/ /*Scope*/ 42, /*->14311*/
+/* 14269*/ OPC_CheckChild1Integer, 13|128,27/*3469*/,
+/* 14272*/ OPC_RecordChild2, // #1 = $mask
+/* 14273*/ OPC_MoveChild2,
+/* 14274*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 14277*/ OPC_Scope, 15, /*->14294*/ // 2 children in Scope
+/* 14279*/ OPC_CheckPredicate, 29, // Predicate_immZExt10
+/* 14281*/ OPC_MoveParent,
+/* 14282*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14284*/ OPC_EmitMergeInputChains1_0,
+/* 14285*/ OPC_EmitConvertToTarget, 1,
+/* 14287*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::RDDSP), 0|OPFL_Chain,
+ MVT::i32, 1/*#Ops*/, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3469:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt10>>:$mask) - Complexity = 12
+ // Dst: (RDDSP:{ *:[i32] } (imm:{ *:[i32] }):$mask)
+/* 14294*/ /*Scope*/ 15, /*->14310*/
+/* 14295*/ OPC_CheckPredicate, 30, // Predicate_immZExt7
+/* 14297*/ OPC_MoveParent,
+/* 14298*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14300*/ OPC_EmitMergeInputChains1_0,
+/* 14301*/ OPC_EmitConvertToTarget, 1,
+/* 14303*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::RDDSP_MM), 0|OPFL_Chain,
+ MVT::i32, 1/*#Ops*/, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3469:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt7>>:$mask) - Complexity = 12
+ // Dst: (RDDSP_MM:{ *:[i32] } (imm:{ *:[i32] }):$mask)
+/* 14310*/ 0, /*End of Scope*/
+/* 14311*/ /*Scope*/ 31, /*->14343*/
+/* 14312*/ OPC_CheckChild1Integer, 125|128,22/*2941*/,
+/* 14315*/ OPC_RecordChild2, // #1 = $rs
+/* 14316*/ OPC_RecordChild3, // #2 = $rt
+/* 14317*/ OPC_Scope, 11, /*->14330*/ // 2 children in Scope
+/* 14319*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14321*/ OPC_EmitMergeInputChains1_0,
+/* 14322*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQ_S_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 2941:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 14330*/ /*Scope*/ 11, /*->14342*/
+/* 14331*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14333*/ OPC_EmitMergeInputChains1_0,
+/* 14334*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQ_S_W_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 2941:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 14342*/ 0, /*End of Scope*/
+/* 14343*/ /*Scope*/ 31, /*->14375*/
+/* 14344*/ OPC_CheckChild1Integer, 101|128,27/*3557*/,
+/* 14347*/ OPC_RecordChild2, // #1 = $rs
+/* 14348*/ OPC_RecordChild3, // #2 = $rt
+/* 14349*/ OPC_Scope, 11, /*->14362*/ // 2 children in Scope
+/* 14351*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14353*/ OPC_EmitMergeInputChains1_0,
+/* 14354*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQ_S_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3557:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 14362*/ /*Scope*/ 11, /*->14374*/
+/* 14363*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14365*/ OPC_EmitMergeInputChains1_0,
+/* 14366*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQ_S_W_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3557:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 14374*/ 0, /*End of Scope*/
+/* 14375*/ /*Scope*/ 28, /*->14404*/
+/* 14376*/ OPC_CheckChild1Integer, 118|128,22/*2934*/,
+/* 14379*/ OPC_RecordChild2, // #1 = $rt
+/* 14380*/ OPC_Scope, 10, /*->14392*/ // 2 children in Scope
+/* 14382*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14384*/ OPC_EmitMergeInputChains1_0,
+/* 14385*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ABSQ_S_W), 0|OPFL_Chain,
+ MVT::i32, 1/*#Ops*/, 1,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 2934:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 14392*/ /*Scope*/ 10, /*->14403*/
+/* 14393*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14395*/ OPC_EmitMergeInputChains1_0,
+/* 14396*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ABSQ_S_W_MM), 0|OPFL_Chain,
+ MVT::i32, 1/*#Ops*/, 1,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 2934:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 14403*/ 0, /*End of Scope*/
+/* 14404*/ /*Scope*/ 31, /*->14436*/
+/* 14405*/ OPC_CheckChild1Integer, 77|128,26/*3405*/,
+/* 14408*/ OPC_RecordChild2, // #1 = $rs
+/* 14409*/ OPC_RecordChild3, // #2 = $rt
+/* 14410*/ OPC_Scope, 11, /*->14423*/ // 2 children in Scope
+/* 14412*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14414*/ OPC_EmitMergeInputChains1_0,
+/* 14415*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULEQ_S_W_PHL), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3405:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 14423*/ /*Scope*/ 11, /*->14435*/
+/* 14424*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14426*/ OPC_EmitMergeInputChains1_0,
+/* 14427*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULEQ_S_W_PHL_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3405:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 14435*/ 0, /*End of Scope*/
+/* 14436*/ /*Scope*/ 31, /*->14468*/
+/* 14437*/ OPC_CheckChild1Integer, 78|128,26/*3406*/,
+/* 14440*/ OPC_RecordChild2, // #1 = $rs
+/* 14441*/ OPC_RecordChild3, // #2 = $rt
+/* 14442*/ OPC_Scope, 11, /*->14455*/ // 2 children in Scope
+/* 14444*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14446*/ OPC_EmitMergeInputChains1_0,
+/* 14447*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULEQ_S_W_PHR), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3406:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 14455*/ /*Scope*/ 11, /*->14467*/
+/* 14456*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14458*/ OPC_EmitMergeInputChains1_0,
+/* 14459*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULEQ_S_W_PHR_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3406:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 14467*/ 0, /*End of Scope*/
+/* 14468*/ /*Scope*/ 31, /*->14500*/
+/* 14469*/ OPC_CheckChild1Integer, 35|128,24/*3107*/,
+/* 14472*/ OPC_RecordChild2, // #1 = $rs
+/* 14473*/ OPC_RecordChild3, // #2 = $rt
+/* 14474*/ OPC_Scope, 11, /*->14487*/ // 2 children in Scope
+/* 14476*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14478*/ OPC_EmitMergeInputChains1_0,
+/* 14479*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGU_EQ_QB), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3107:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14487*/ /*Scope*/ 11, /*->14499*/
+/* 14488*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14490*/ OPC_EmitMergeInputChains1_0,
+/* 14491*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGU_EQ_QB_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3107:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14499*/ 0, /*End of Scope*/
+/* 14500*/ /*Scope*/ 31, /*->14532*/
+/* 14501*/ OPC_CheckChild1Integer, 37|128,24/*3109*/,
+/* 14504*/ OPC_RecordChild2, // #1 = $rs
+/* 14505*/ OPC_RecordChild3, // #2 = $rt
+/* 14506*/ OPC_Scope, 11, /*->14519*/ // 2 children in Scope
+/* 14508*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14510*/ OPC_EmitMergeInputChains1_0,
+/* 14511*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGU_LT_QB), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3109:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14519*/ /*Scope*/ 11, /*->14531*/
+/* 14520*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14522*/ OPC_EmitMergeInputChains1_0,
+/* 14523*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGU_LT_QB_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3109:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14531*/ 0, /*End of Scope*/
+/* 14532*/ /*Scope*/ 31, /*->14564*/
+/* 14533*/ OPC_CheckChild1Integer, 36|128,24/*3108*/,
+/* 14536*/ OPC_RecordChild2, // #1 = $rs
+/* 14537*/ OPC_RecordChild3, // #2 = $rt
+/* 14538*/ OPC_Scope, 11, /*->14551*/ // 2 children in Scope
+/* 14540*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14542*/ OPC_EmitMergeInputChains1_0,
+/* 14543*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGU_LE_QB), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3108:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14551*/ /*Scope*/ 11, /*->14563*/
+/* 14552*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14554*/ OPC_EmitMergeInputChains1_0,
+/* 14555*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGU_LE_QB_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3108:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14563*/ 0, /*End of Scope*/
+/* 14564*/ /*Scope*/ 31, /*->14596*/
+/* 14565*/ OPC_CheckChild1Integer, 125|128,25/*3325*/,
+/* 14568*/ OPC_RecordChild2, // #1 = $base
+/* 14569*/ OPC_RecordChild3, // #2 = $index
+/* 14570*/ OPC_Scope, 11, /*->14583*/ // 2 children in Scope
+/* 14572*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14574*/ OPC_EmitMergeInputChains1_0,
+/* 14575*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWX), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3325:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) - Complexity = 8
+ // Dst: (LWX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
+/* 14583*/ /*Scope*/ 11, /*->14595*/
+/* 14584*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14586*/ OPC_EmitMergeInputChains1_0,
+/* 14587*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LWX_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3325:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) - Complexity = 8
+ // Dst: (LWX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
+/* 14595*/ 0, /*End of Scope*/
+/* 14596*/ /*Scope*/ 31, /*->14628*/
+/* 14597*/ OPC_CheckChild1Integer, 123|128,25/*3323*/,
+/* 14600*/ OPC_RecordChild2, // #1 = $base
+/* 14601*/ OPC_RecordChild3, // #2 = $index
+/* 14602*/ OPC_Scope, 11, /*->14615*/ // 2 children in Scope
+/* 14604*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14606*/ OPC_EmitMergeInputChains1_0,
+/* 14607*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHX), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3323:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) - Complexity = 8
+ // Dst: (LHX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
+/* 14615*/ /*Scope*/ 11, /*->14627*/
+/* 14616*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14618*/ OPC_EmitMergeInputChains1_0,
+/* 14619*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LHX_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3323:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) - Complexity = 8
+ // Dst: (LHX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
+/* 14627*/ 0, /*End of Scope*/
+/* 14628*/ /*Scope*/ 31, /*->14660*/
+/* 14629*/ OPC_CheckChild1Integer, 114|128,25/*3314*/,
+/* 14632*/ OPC_RecordChild2, // #1 = $base
+/* 14633*/ OPC_RecordChild3, // #2 = $index
+/* 14634*/ OPC_Scope, 11, /*->14647*/ // 2 children in Scope
+/* 14636*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14638*/ OPC_EmitMergeInputChains1_0,
+/* 14639*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBUX), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3314:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) - Complexity = 8
+ // Dst: (LBUX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
+/* 14647*/ /*Scope*/ 11, /*->14659*/
+/* 14648*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14650*/ OPC_EmitMergeInputChains1_0,
+/* 14651*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LBUX_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3314:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index) - Complexity = 8
+ // Dst: (LBUX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
+/* 14659*/ 0, /*End of Scope*/
+/* 14660*/ /*Scope*/ 31, /*->14692*/
+/* 14661*/ OPC_CheckChild1Integer, 109|128,25/*3309*/,
+/* 14664*/ OPC_RecordChild2, // #1 = $src
+/* 14665*/ OPC_RecordChild3, // #2 = $rs
+/* 14666*/ OPC_Scope, 11, /*->14679*/ // 2 children in Scope
+/* 14668*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14670*/ OPC_EmitMergeInputChains1_0,
+/* 14671*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSV), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3309:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
+/* 14679*/ /*Scope*/ 11, /*->14691*/
+/* 14680*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14682*/ OPC_EmitMergeInputChains1_0,
+/* 14683*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSV_MM), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3309:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
+/* 14691*/ 0, /*End of Scope*/
+/* 14692*/ /*Scope*/ 31, /*->14724*/
+/* 14693*/ OPC_CheckChild1Integer, 32|128,24/*3104*/,
+/* 14696*/ OPC_RecordChild2, // #1 = $rs
+/* 14697*/ OPC_RecordChild3, // #2 = $rt
+/* 14698*/ OPC_Scope, 11, /*->14711*/ // 2 children in Scope
+/* 14700*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 14702*/ OPC_EmitMergeInputChains1_0,
+/* 14703*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGDU_EQ_QB), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3104:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14711*/ /*Scope*/ 11, /*->14723*/
+/* 14712*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 14714*/ OPC_EmitMergeInputChains1_0,
+/* 14715*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGDU_EQ_QB_MMR2), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3104:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14723*/ 0, /*End of Scope*/
+/* 14724*/ /*Scope*/ 31, /*->14756*/
+/* 14725*/ OPC_CheckChild1Integer, 34|128,24/*3106*/,
+/* 14728*/ OPC_RecordChild2, // #1 = $rs
+/* 14729*/ OPC_RecordChild3, // #2 = $rt
+/* 14730*/ OPC_Scope, 11, /*->14743*/ // 2 children in Scope
+/* 14732*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 14734*/ OPC_EmitMergeInputChains1_0,
+/* 14735*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGDU_LT_QB), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3106:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14743*/ /*Scope*/ 11, /*->14755*/
+/* 14744*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 14746*/ OPC_EmitMergeInputChains1_0,
+/* 14747*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGDU_LT_QB_MMR2), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3106:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14755*/ 0, /*End of Scope*/
+/* 14756*/ /*Scope*/ 31, /*->14788*/
+/* 14757*/ OPC_CheckChild1Integer, 33|128,24/*3105*/,
+/* 14760*/ OPC_RecordChild2, // #1 = $rs
+/* 14761*/ OPC_RecordChild3, // #2 = $rt
+/* 14762*/ OPC_Scope, 11, /*->14775*/ // 2 children in Scope
+/* 14764*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 14766*/ OPC_EmitMergeInputChains1_0,
+/* 14767*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGDU_LE_QB), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3105:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14775*/ /*Scope*/ 11, /*->14787*/
+/* 14776*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 14778*/ OPC_EmitMergeInputChains1_0,
+/* 14779*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMPGDU_LE_QB_MMR2), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3105:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 14787*/ 0, /*End of Scope*/
+/* 14788*/ /*Scope*/ 31, /*->14820*/
+/* 14789*/ OPC_CheckChild1Integer, 84|128,26/*3412*/,
+/* 14792*/ OPC_RecordChild2, // #1 = $rs
+/* 14793*/ OPC_RecordChild3, // #2 = $rt
+/* 14794*/ OPC_Scope, 11, /*->14807*/ // 2 children in Scope
+/* 14796*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 14798*/ OPC_EmitMergeInputChains1_0,
+/* 14799*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULQ_S_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3412:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 14807*/ /*Scope*/ 11, /*->14819*/
+/* 14808*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 14810*/ OPC_EmitMergeInputChains1_0,
+/* 14811*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULQ_S_W_MMR2), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3412:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 14819*/ 0, /*End of Scope*/
+/* 14820*/ /*Scope*/ 31, /*->14852*/
+/* 14821*/ OPC_CheckChild1Integer, 82|128,26/*3410*/,
+/* 14824*/ OPC_RecordChild2, // #1 = $rs
+/* 14825*/ OPC_RecordChild3, // #2 = $rt
+/* 14826*/ OPC_Scope, 11, /*->14839*/ // 2 children in Scope
+/* 14828*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 14830*/ OPC_EmitMergeInputChains1_0,
+/* 14831*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULQ_RS_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3410:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 14839*/ /*Scope*/ 11, /*->14851*/
+/* 14840*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 14842*/ OPC_EmitMergeInputChains1_0,
+/* 14843*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULQ_RS_W_MMR2), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3410:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 14851*/ 0, /*End of Scope*/
+/* 14852*/ /*Scope*/ 16, /*->14869*/
+/* 14853*/ OPC_CheckChild1Integer, 14|128,23/*2958*/,
+/* 14856*/ OPC_RecordChild2, // #1 = $a
+/* 14857*/ OPC_RecordChild3, // #2 = $b
+/* 14858*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14860*/ OPC_EmitMergeInputChains1_0,
+/* 14861*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDSC), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 2958:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) - Complexity = 8
+ // Dst: (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
+/* 14869*/ /*Scope*/ 16, /*->14886*/
+/* 14870*/ OPC_CheckChild1Integer, 29|128,23/*2973*/,
+/* 14873*/ OPC_RecordChild2, // #1 = $a
+/* 14874*/ OPC_RecordChild3, // #2 = $b
+/* 14875*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14877*/ OPC_EmitMergeInputChains1_0,
+/* 14878*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDWC), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 2973:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) - Complexity = 8
+ // Dst: (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
+/* 14886*/ /*Scope*/ 10, /*->14897*/
+/* 14887*/ OPC_CheckChild1Integer, 100|128,23/*3044*/,
+/* 14890*/ OPC_EmitMergeInputChains1_0,
+/* 14891*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BPOSGE32_PSEUDO), 0|OPFL_Chain,
+ MVT::i32, 0/*#Ops*/,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 3044:{ *:[iPTR] }) - Complexity = 8
+ // Dst: (BPOSGE32_PSEUDO:{ *:[i32] })
+/* 14897*/ /*Scope*/ 69, /*->14967*/
+/* 14898*/ OPC_CheckChild1Integer, 30|128,27/*3486*/,
+/* 14901*/ OPC_RecordChild2, // #1 = $rt
+/* 14902*/ OPC_RecordChild3, // #2 = $rs_sa
+/* 14903*/ OPC_Scope, 37, /*->14942*/ // 3 children in Scope
+/* 14905*/ OPC_MoveChild3,
+/* 14906*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 14909*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 14911*/ OPC_MoveParent,
+/* 14912*/ OPC_Scope, 13, /*->14927*/ // 2 children in Scope
+/* 14914*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14916*/ OPC_EmitMergeInputChains1_0,
+/* 14917*/ OPC_EmitConvertToTarget, 2,
+/* 14919*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLL_S_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 3,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) - Complexity = 12
+ // Dst: (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+/* 14927*/ /*Scope*/ 13, /*->14941*/
+/* 14928*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14930*/ OPC_EmitMergeInputChains1_0,
+/* 14931*/ OPC_EmitConvertToTarget, 2,
+/* 14933*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLL_S_PH_MM), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 3,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) - Complexity = 12
+ // Dst: (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
+/* 14941*/ 0, /*End of Scope*/
+/* 14942*/ /*Scope*/ 11, /*->14954*/
+/* 14943*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14945*/ OPC_EmitMergeInputChains1_0,
+/* 14946*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLLV_S_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 14954*/ /*Scope*/ 11, /*->14966*/
+/* 14955*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 14957*/ OPC_EmitMergeInputChains1_0,
+/* 14958*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLLV_S_PH_MM), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 14966*/ 0, /*End of Scope*/
+/* 14967*/ /*Scope*/ 52, /*->15020*/
+/* 14968*/ OPC_CheckChild1Integer, 28|128,27/*3484*/,
+/* 14971*/ OPC_RecordChild2, // #1 = $a
+/* 14972*/ OPC_RecordChild3, // #2 = $shamt
+/* 14973*/ OPC_Scope, 20, /*->14995*/ // 3 children in Scope
+/* 14975*/ OPC_MoveChild3,
+/* 14976*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 14979*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 14981*/ OPC_MoveParent,
+/* 14982*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14984*/ OPC_EmitMergeInputChains1_0,
+/* 14985*/ OPC_EmitConvertToTarget, 2,
+/* 14987*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLL_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 3,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) - Complexity = 12
+ // Dst: (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
+/* 14995*/ /*Scope*/ 11, /*->15007*/
+/* 14996*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 14998*/ OPC_EmitMergeInputChains1_0,
+/* 14999*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLLV_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 15007*/ /*Scope*/ 11, /*->15019*/
+/* 15008*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15010*/ OPC_EmitMergeInputChains1_0,
+/* 15011*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLLV_PH_MM), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 15019*/ 0, /*End of Scope*/
+/* 15020*/ /*Scope*/ 52, /*->15073*/
+/* 15021*/ OPC_CheckChild1Integer, 29|128,27/*3485*/,
+/* 15024*/ OPC_RecordChild2, // #1 = $a
+/* 15025*/ OPC_RecordChild3, // #2 = $shamt
+/* 15026*/ OPC_Scope, 20, /*->15048*/ // 3 children in Scope
+/* 15028*/ OPC_MoveChild3,
+/* 15029*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 15032*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 15034*/ OPC_MoveParent,
+/* 15035*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15037*/ OPC_EmitMergeInputChains1_0,
+/* 15038*/ OPC_EmitConvertToTarget, 2,
+/* 15040*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLL_QB), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 3,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) - Complexity = 12
+ // Dst: (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
+/* 15048*/ /*Scope*/ 11, /*->15060*/
+/* 15049*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15051*/ OPC_EmitMergeInputChains1_0,
+/* 15052*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLLV_QB), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 15060*/ /*Scope*/ 11, /*->15072*/
+/* 15061*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15063*/ OPC_EmitMergeInputChains1_0,
+/* 15064*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLLV_QB_MM), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 15072*/ 0, /*End of Scope*/
+/* 15073*/ /*Scope*/ 28, /*->15102*/
+/* 15074*/ OPC_CheckChild1Integer, 116|128,22/*2932*/,
+/* 15077*/ OPC_RecordChild2, // #1 = $rt
+/* 15078*/ OPC_Scope, 10, /*->15090*/ // 2 children in Scope
+/* 15080*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15082*/ OPC_EmitMergeInputChains1_0,
+/* 15083*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ABSQ_S_PH), 0|OPFL_Chain,
+ MVT::v2i16, 1/*#Ops*/, 1,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 2932:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15090*/ /*Scope*/ 10, /*->15101*/
+/* 15091*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15093*/ OPC_EmitMergeInputChains1_0,
+/* 15094*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ABSQ_S_PH_MM), 0|OPFL_Chain,
+ MVT::v2i16, 1/*#Ops*/, 1,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 2932:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) - Complexity = 8
+ // Dst: (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
+/* 15101*/ 0, /*End of Scope*/
+/* 15102*/ /*Scope*/ 31, /*->15134*/
+/* 15103*/ OPC_CheckChild1Integer, 9|128,27/*3465*/,
+/* 15106*/ OPC_RecordChild2, // #1 = $rs
+/* 15107*/ OPC_RecordChild3, // #2 = $rt
+/* 15108*/ OPC_Scope, 11, /*->15121*/ // 2 children in Scope
+/* 15110*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15112*/ OPC_EmitMergeInputChains1_0,
+/* 15113*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECRQ_RS_PH_W), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3465:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 15121*/ /*Scope*/ 11, /*->15133*/
+/* 15122*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15124*/ OPC_EmitMergeInputChains1_0,
+/* 15125*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECRQ_RS_PH_W_MM), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3465:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 15133*/ 0, /*End of Scope*/
+/* 15134*/ /*Scope*/ 31, /*->15166*/
+/* 15135*/ OPC_CheckChild1Integer, 10|128,27/*3466*/,
+/* 15138*/ OPC_RecordChild2, // #1 = $rs
+/* 15139*/ OPC_RecordChild3, // #2 = $rt
+/* 15140*/ OPC_Scope, 11, /*->15153*/ // 2 children in Scope
+/* 15142*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15144*/ OPC_EmitMergeInputChains1_0,
+/* 15145*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECRQU_S_QB_PH), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15153*/ /*Scope*/ 11, /*->15165*/
+/* 15154*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15156*/ OPC_EmitMergeInputChains1_0,
+/* 15157*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECRQU_S_QB_PH_MM), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15165*/ 0, /*End of Scope*/
+/* 15166*/ /*Scope*/ 31, /*->15198*/
+/* 15167*/ OPC_CheckChild1Integer, 79|128,26/*3407*/,
+/* 15170*/ OPC_RecordChild2, // #1 = $rs
+/* 15171*/ OPC_RecordChild3, // #2 = $rt
+/* 15172*/ OPC_Scope, 11, /*->15185*/ // 2 children in Scope
+/* 15174*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15176*/ OPC_EmitMergeInputChains1_0,
+/* 15177*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULEU_S_PH_QBL), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15185*/ /*Scope*/ 11, /*->15197*/
+/* 15186*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15188*/ OPC_EmitMergeInputChains1_0,
+/* 15189*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULEU_S_PH_QBL_MM), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15197*/ 0, /*End of Scope*/
+/* 15198*/ /*Scope*/ 31, /*->15230*/
+/* 15199*/ OPC_CheckChild1Integer, 80|128,26/*3408*/,
+/* 15202*/ OPC_RecordChild2, // #1 = $rs
+/* 15203*/ OPC_RecordChild3, // #2 = $rt
+/* 15204*/ OPC_Scope, 11, /*->15217*/ // 2 children in Scope
+/* 15206*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15208*/ OPC_EmitMergeInputChains1_0,
+/* 15209*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULEU_S_PH_QBR), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15217*/ /*Scope*/ 11, /*->15229*/
+/* 15218*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15220*/ OPC_EmitMergeInputChains1_0,
+/* 15221*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULEU_S_PH_QBR_MM), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15229*/ 0, /*End of Scope*/
+/* 15230*/ /*Scope*/ 31, /*->15262*/
+/* 15231*/ OPC_CheckChild1Integer, 81|128,26/*3409*/,
+/* 15234*/ OPC_RecordChild2, // #1 = $rs
+/* 15235*/ OPC_RecordChild3, // #2 = $rt
+/* 15236*/ OPC_Scope, 11, /*->15249*/ // 2 children in Scope
+/* 15238*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15240*/ OPC_EmitMergeInputChains1_0,
+/* 15241*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULQ_RS_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3409:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15249*/ /*Scope*/ 11, /*->15261*/
+/* 15250*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15252*/ OPC_EmitMergeInputChains1_0,
+/* 15253*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULQ_RS_PH_MM), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3409:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15261*/ 0, /*End of Scope*/
+/* 15262*/ /*Scope*/ 31, /*->15294*/
+/* 15263*/ OPC_CheckChild1Integer, 121|128,26/*3449*/,
+/* 15266*/ OPC_RecordChild2, // #1 = $rs
+/* 15267*/ OPC_RecordChild3, // #2 = $rt
+/* 15268*/ OPC_Scope, 11, /*->15281*/ // 2 children in Scope
+/* 15270*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15272*/ OPC_EmitMergeInputChains1_0,
+/* 15273*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PICK_QB), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 15281*/ /*Scope*/ 11, /*->15293*/
+/* 15282*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15284*/ OPC_EmitMergeInputChains1_0,
+/* 15285*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PICK_QB_MM), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 15293*/ 0, /*End of Scope*/
+/* 15294*/ /*Scope*/ 31, /*->15326*/
+/* 15295*/ OPC_CheckChild1Integer, 120|128,26/*3448*/,
+/* 15298*/ OPC_RecordChild2, // #1 = $rs
+/* 15299*/ OPC_RecordChild3, // #2 = $rt
+/* 15300*/ OPC_Scope, 11, /*->15313*/ // 2 children in Scope
+/* 15302*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15304*/ OPC_EmitMergeInputChains1_0,
+/* 15305*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PICK_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3448:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15313*/ /*Scope*/ 11, /*->15325*/
+/* 15314*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15316*/ OPC_EmitMergeInputChains1_0,
+/* 15317*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PICK_PH_MM), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3448:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15325*/ 0, /*End of Scope*/
+/* 15326*/ /*Scope*/ 31, /*->15358*/
+/* 15327*/ OPC_CheckChild1Integer, 15|128,23/*2959*/,
+/* 15330*/ OPC_RecordChild2, // #1 = $rs
+/* 15331*/ OPC_RecordChild3, // #2 = $rt
+/* 15332*/ OPC_Scope, 11, /*->15345*/ // 2 children in Scope
+/* 15334*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15336*/ OPC_EmitMergeInputChains1_0,
+/* 15337*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 2959:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15345*/ /*Scope*/ 11, /*->15357*/
+/* 15346*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15348*/ OPC_EmitMergeInputChains1_0,
+/* 15349*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU_PH_MMR2), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 2959:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15357*/ 0, /*End of Scope*/
+/* 15358*/ /*Scope*/ 31, /*->15390*/
+/* 15359*/ OPC_CheckChild1Integer, 17|128,23/*2961*/,
+/* 15362*/ OPC_RecordChild2, // #1 = $rs
+/* 15363*/ OPC_RecordChild3, // #2 = $rt
+/* 15364*/ OPC_Scope, 11, /*->15377*/ // 2 children in Scope
+/* 15366*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15368*/ OPC_EmitMergeInputChains1_0,
+/* 15369*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU_S_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 2961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15377*/ /*Scope*/ 11, /*->15389*/
+/* 15378*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15380*/ OPC_EmitMergeInputChains1_0,
+/* 15381*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU_S_PH_MMR2), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 2961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15389*/ 0, /*End of Scope*/
+/* 15390*/ /*Scope*/ 31, /*->15422*/
+/* 15391*/ OPC_CheckChild1Integer, 122|128,27/*3578*/,
+/* 15394*/ OPC_RecordChild2, // #1 = $rs
+/* 15395*/ OPC_RecordChild3, // #2 = $rt
+/* 15396*/ OPC_Scope, 11, /*->15409*/ // 2 children in Scope
+/* 15398*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15400*/ OPC_EmitMergeInputChains1_0,
+/* 15401*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3578:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15409*/ /*Scope*/ 11, /*->15421*/
+/* 15410*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15412*/ OPC_EmitMergeInputChains1_0,
+/* 15413*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_PH_MMR2), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3578:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15421*/ 0, /*End of Scope*/
+/* 15422*/ /*Scope*/ 31, /*->15454*/
+/* 15423*/ OPC_CheckChild1Integer, 124|128,27/*3580*/,
+/* 15426*/ OPC_RecordChild2, // #1 = $rs
+/* 15427*/ OPC_RecordChild3, // #2 = $rt
+/* 15428*/ OPC_Scope, 11, /*->15441*/ // 2 children in Scope
+/* 15430*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15432*/ OPC_EmitMergeInputChains1_0,
+/* 15433*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_S_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3580:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15441*/ /*Scope*/ 11, /*->15453*/
+/* 15442*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15444*/ OPC_EmitMergeInputChains1_0,
+/* 15445*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_S_PH_MMR2), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3580:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15453*/ 0, /*End of Scope*/
+/* 15454*/ /*Scope*/ 28, /*->15483*/
+/* 15455*/ OPC_CheckChild1Integer, 117|128,22/*2933*/,
+/* 15458*/ OPC_RecordChild2, // #1 = $rt
+/* 15459*/ OPC_Scope, 10, /*->15471*/ // 2 children in Scope
+/* 15461*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15463*/ OPC_EmitMergeInputChains1_0,
+/* 15464*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ABSQ_S_QB), 0|OPFL_Chain,
+ MVT::v4i8, 1/*#Ops*/, 1,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 2933:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 15471*/ /*Scope*/ 10, /*->15482*/
+/* 15472*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15474*/ OPC_EmitMergeInputChains1_0,
+/* 15475*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ABSQ_S_QB_MMR2), 0|OPFL_Chain,
+ MVT::v4i8, 1/*#Ops*/, 1,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 2933:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 15482*/ 0, /*End of Scope*/
+/* 15483*/ /*Scope*/ 31, /*->15515*/
+/* 15484*/ OPC_CheckChild1Integer, 76|128,26/*3404*/,
+/* 15487*/ OPC_RecordChild2, // #1 = $rs
+/* 15488*/ OPC_RecordChild3, // #2 = $rt
+/* 15489*/ OPC_Scope, 11, /*->15502*/ // 2 children in Scope
+/* 15491*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15493*/ OPC_EmitMergeInputChains1_0,
+/* 15494*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUL_S_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3404:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15502*/ /*Scope*/ 11, /*->15514*/
+/* 15503*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15505*/ OPC_EmitMergeInputChains1_0,
+/* 15506*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUL_S_PH_MMR2), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3404:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15514*/ 0, /*End of Scope*/
+/* 15515*/ /*Scope*/ 31, /*->15547*/
+/* 15516*/ OPC_CheckChild1Integer, 83|128,26/*3411*/,
+/* 15519*/ OPC_RecordChild2, // #1 = $rs
+/* 15520*/ OPC_RecordChild3, // #2 = $rt
+/* 15521*/ OPC_Scope, 11, /*->15534*/ // 2 children in Scope
+/* 15523*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15525*/ OPC_EmitMergeInputChains1_0,
+/* 15526*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULQ_S_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3411:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15534*/ /*Scope*/ 11, /*->15546*/
+/* 15535*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15537*/ OPC_EmitMergeInputChains1_0,
+/* 15538*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULQ_S_PH_MMR2), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3411:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15546*/ 0, /*End of Scope*/
+/* 15547*/ /*Scope*/ 31, /*->15579*/
+/* 15548*/ OPC_CheckChild1Integer, 4|128,27/*3460*/,
+/* 15551*/ OPC_RecordChild2, // #1 = $rs
+/* 15552*/ OPC_RecordChild3, // #2 = $rt
+/* 15553*/ OPC_Scope, 11, /*->15566*/ // 2 children in Scope
+/* 15555*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15557*/ OPC_EmitMergeInputChains1_0,
+/* 15558*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECR_QB_PH), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3460:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15566*/ /*Scope*/ 11, /*->15578*/
+/* 15567*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15569*/ OPC_EmitMergeInputChains1_0,
+/* 15570*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECR_QB_PH_MMR2), 0|OPFL_Chain,
+ MVT::v4i8, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v4i8] } 3460:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15578*/ 0, /*End of Scope*/
+/* 15579*/ /*Scope*/ 16, /*->15596*/
+/* 15580*/ OPC_CheckChild1Integer, 73|128,26/*3401*/,
+/* 15583*/ OPC_RecordChild2, // #1 = $a
+/* 15584*/ OPC_RecordChild3, // #2 = $b
+/* 15585*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15587*/ OPC_EmitMergeInputChains1_0,
+/* 15588*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUL_PH), 0|OPFL_Chain,
+ MVT::v2i16, 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_w_chain:{ *:[v2i16] } 3401:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) - Complexity = 8
+ // Dst: (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+/* 15596*/ 0, /*End of Scope*/
+/* 15597*/ /*SwitchOpcode*/ 82|128,40/*5202*/, TARGET_VAL(ISD::INTRINSIC_WO_CHAIN),// ->20803
+/* 15601*/ OPC_Scope, 65, /*->15668*/ // 254 children in Scope
+/* 15603*/ OPC_CheckChild0Integer, 36|128,27/*3492*/,
+/* 15606*/ OPC_RecordChild1, // #0 = $rt
+/* 15607*/ OPC_RecordChild2, // #1 = $rs_sa
+/* 15608*/ OPC_Scope, 35, /*->15645*/ // 3 children in Scope
+/* 15610*/ OPC_MoveChild2,
+/* 15611*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 15614*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 15616*/ OPC_MoveParent,
+/* 15617*/ OPC_Scope, 12, /*->15631*/ // 2 children in Scope
+/* 15619*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15621*/ OPC_EmitConvertToTarget, 1,
+/* 15623*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_R_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) - Complexity = 12
+ // Dst: (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+/* 15631*/ /*Scope*/ 12, /*->15644*/
+/* 15632*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15634*/ OPC_EmitConvertToTarget, 1,
+/* 15636*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_R_W_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
+/* 15644*/ 0, /*End of Scope*/
+/* 15645*/ /*Scope*/ 10, /*->15656*/
+/* 15646*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15648*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_R_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 15656*/ /*Scope*/ 10, /*->15667*/
+/* 15657*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15659*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_R_W_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 15667*/ 0, /*End of Scope*/
+/* 15668*/ /*Scope*/ 43, /*->15712*/
+/* 15669*/ OPC_CheckChild0Integer, 32|128,23/*2976*/,
+/* 15672*/ OPC_RecordChild1, // #0 = $src
+/* 15673*/ OPC_RecordChild2, // #1 = $rs
+/* 15674*/ OPC_RecordChild3, // #2 = $sa
+/* 15675*/ OPC_MoveChild3,
+/* 15676*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 15679*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 15681*/ OPC_MoveParent,
+/* 15682*/ OPC_Scope, 13, /*->15697*/ // 2 children in Scope
+/* 15684*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15686*/ OPC_EmitConvertToTarget, 2,
+/* 15688*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::APPEND), 0,
+ MVT::i32, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 2976:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 15697*/ /*Scope*/ 13, /*->15711*/
+/* 15698*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15700*/ OPC_EmitConvertToTarget, 2,
+/* 15702*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::APPEND_MMR2), 0,
+ MVT::i32, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 2976:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 15711*/ 0, /*End of Scope*/
+/* 15712*/ /*Scope*/ 43, /*->15756*/
+/* 15713*/ OPC_CheckChild0Integer, 57|128,23/*3001*/,
+/* 15716*/ OPC_RecordChild1, // #0 = $src
+/* 15717*/ OPC_RecordChild2, // #1 = $rs
+/* 15718*/ OPC_RecordChild3, // #2 = $sa
+/* 15719*/ OPC_MoveChild3,
+/* 15720*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 15723*/ OPC_CheckPredicate, 33, // Predicate_immZExt2
+/* 15725*/ OPC_MoveParent,
+/* 15726*/ OPC_Scope, 13, /*->15741*/ // 2 children in Scope
+/* 15728*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15730*/ OPC_EmitConvertToTarget, 2,
+/* 15732*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BALIGN), 0,
+ MVT::i32, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3001:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$sa) - Complexity = 12
+ // Dst: (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 15741*/ /*Scope*/ 13, /*->15755*/
+/* 15742*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15744*/ OPC_EmitConvertToTarget, 2,
+/* 15746*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BALIGN_MMR2), 0,
+ MVT::i32, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3001:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) - Complexity = 12
+ // Dst: (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
+/* 15755*/ 0, /*End of Scope*/
+/* 15756*/ /*Scope*/ 43, /*->15800*/
+/* 15757*/ OPC_CheckChild0Integer, 11|128,27/*3467*/,
+/* 15760*/ OPC_RecordChild1, // #0 = $src
+/* 15761*/ OPC_RecordChild2, // #1 = $rs
+/* 15762*/ OPC_RecordChild3, // #2 = $sa
+/* 15763*/ OPC_MoveChild3,
+/* 15764*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 15767*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 15769*/ OPC_MoveParent,
+/* 15770*/ OPC_Scope, 13, /*->15785*/ // 2 children in Scope
+/* 15772*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15774*/ OPC_EmitConvertToTarget, 2,
+/* 15776*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PREPEND), 0,
+ MVT::i32, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3467:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 15785*/ /*Scope*/ 13, /*->15799*/
+/* 15786*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15788*/ OPC_EmitConvertToTarget, 2,
+/* 15790*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PREPEND_MMR2), 0,
+ MVT::i32, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3467:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 15799*/ 0, /*End of Scope*/
+/* 15800*/ /*Scope*/ 29, /*->15830*/
+/* 15801*/ OPC_CheckChild0Integer, 60|128,26/*3388*/,
+/* 15804*/ OPC_RecordChild1, // #0 = $rs
+/* 15805*/ OPC_RecordChild2, // #1 = $rt
+/* 15806*/ OPC_Scope, 10, /*->15818*/ // 2 children in Scope
+/* 15808*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15810*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MODSUB), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3388:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 15818*/ /*Scope*/ 10, /*->15829*/
+/* 15819*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15821*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MODSUB_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3388:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 15829*/ 0, /*End of Scope*/
+/* 15830*/ /*Scope*/ 26, /*->15857*/
+/* 15831*/ OPC_CheckChild0Integer, 12|128,27/*3468*/,
+/* 15834*/ OPC_RecordChild1, // #0 = $rs
+/* 15835*/ OPC_Scope, 9, /*->15846*/ // 2 children in Scope
+/* 15837*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15839*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::RADDU_W_QB), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3468:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 15846*/ /*Scope*/ 9, /*->15856*/
+/* 15847*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15849*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::RADDU_W_QB_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3468:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 15856*/ 0, /*End of Scope*/
+/* 15857*/ /*Scope*/ 26, /*->15884*/
+/* 15858*/ OPC_CheckChild0Integer, 122|128,26/*3450*/,
+/* 15861*/ OPC_RecordChild1, // #0 = $rt
+/* 15862*/ OPC_Scope, 9, /*->15873*/ // 2 children in Scope
+/* 15864*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15866*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQ_W_PHL), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3450:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15873*/ /*Scope*/ 9, /*->15883*/
+/* 15874*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15876*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQ_W_PHL_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3450:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) - Complexity = 8
+ // Dst: (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
+/* 15883*/ 0, /*End of Scope*/
+/* 15884*/ /*Scope*/ 26, /*->15911*/
+/* 15885*/ OPC_CheckChild0Integer, 123|128,26/*3451*/,
+/* 15888*/ OPC_RecordChild1, // #0 = $rt
+/* 15889*/ OPC_Scope, 9, /*->15900*/ // 2 children in Scope
+/* 15891*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15893*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQ_W_PHR), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
+/* 15900*/ /*Scope*/ 9, /*->15910*/
+/* 15901*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15903*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQ_W_PHR_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) - Complexity = 8
+ // Dst: (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
+/* 15910*/ 0, /*End of Scope*/
+/* 15911*/ /*Scope*/ 26, /*->15938*/
+/* 15912*/ OPC_CheckChild0Integer, 82|128,23/*3026*/,
+/* 15915*/ OPC_RecordChild1, // #0 = $rt
+/* 15916*/ OPC_Scope, 9, /*->15927*/ // 2 children in Scope
+/* 15918*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 15920*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BITREV), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3026:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 15927*/ /*Scope*/ 9, /*->15937*/
+/* 15928*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 15930*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BITREV_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3026:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 15937*/ 0, /*End of Scope*/
+/* 15938*/ /*Scope*/ 29, /*->15968*/
+/* 15939*/ OPC_CheckChild0Integer, 1|128,23/*2945*/,
+/* 15942*/ OPC_RecordChild1, // #0 = $rs
+/* 15943*/ OPC_RecordChild2, // #1 = $rt
+/* 15944*/ OPC_Scope, 10, /*->15956*/ // 2 children in Scope
+/* 15946*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15948*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQH_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 2945:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 15956*/ /*Scope*/ 10, /*->15967*/
+/* 15957*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15959*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQH_W_MMR2), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 2945:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 15967*/ 0, /*End of Scope*/
+/* 15968*/ /*Scope*/ 29, /*->15998*/
+/* 15969*/ OPC_CheckChild0Integer, 0|128,23/*2944*/,
+/* 15972*/ OPC_RecordChild1, // #0 = $rs
+/* 15973*/ OPC_RecordChild2, // #1 = $rt
+/* 15974*/ OPC_Scope, 10, /*->15986*/ // 2 children in Scope
+/* 15976*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 15978*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQH_R_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 2944:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 15986*/ /*Scope*/ 10, /*->15997*/
+/* 15987*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 15989*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQH_R_W_MMR2), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 2944:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 15997*/ 0, /*End of Scope*/
+/* 15998*/ /*Scope*/ 29, /*->16028*/
+/* 15999*/ OPC_CheckChild0Integer, 105|128,27/*3561*/,
+/* 16002*/ OPC_RecordChild1, // #0 = $rs
+/* 16003*/ OPC_RecordChild2, // #1 = $rt
+/* 16004*/ OPC_Scope, 10, /*->16016*/ // 2 children in Scope
+/* 16006*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16008*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQH_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 16016*/ /*Scope*/ 10, /*->16027*/
+/* 16017*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 16019*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQH_W_MMR2), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 16027*/ 0, /*End of Scope*/
+/* 16028*/ /*Scope*/ 29, /*->16058*/
+/* 16029*/ OPC_CheckChild0Integer, 104|128,27/*3560*/,
+/* 16032*/ OPC_RecordChild1, // #0 = $rs
+/* 16033*/ OPC_RecordChild2, // #1 = $rt
+/* 16034*/ OPC_Scope, 10, /*->16046*/ // 2 children in Scope
+/* 16036*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16038*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQH_R_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3560:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 16046*/ /*Scope*/ 10, /*->16057*/
+/* 16047*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 16049*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQH_R_W_MMR2), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[i32] } 3560:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 16057*/ 0, /*End of Scope*/
+/* 16058*/ /*Scope*/ 65, /*->16124*/
+/* 16059*/ OPC_CheckChild0Integer, 34|128,27/*3490*/,
+/* 16062*/ OPC_RecordChild1, // #0 = $rt
+/* 16063*/ OPC_RecordChild2, // #1 = $rs_sa
+/* 16064*/ OPC_Scope, 35, /*->16101*/ // 3 children in Scope
+/* 16066*/ OPC_MoveChild2,
+/* 16067*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16070*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 16072*/ OPC_MoveParent,
+/* 16073*/ OPC_Scope, 12, /*->16087*/ // 2 children in Scope
+/* 16075*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16077*/ OPC_EmitConvertToTarget, 1,
+/* 16079*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_R_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) - Complexity = 12
+ // Dst: (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+/* 16087*/ /*Scope*/ 12, /*->16100*/
+/* 16088*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 16090*/ OPC_EmitConvertToTarget, 1,
+/* 16092*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_R_PH_MM), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) - Complexity = 12
+ // Dst: (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
+/* 16100*/ 0, /*End of Scope*/
+/* 16101*/ /*Scope*/ 10, /*->16112*/
+/* 16102*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16104*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_R_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 16112*/ /*Scope*/ 10, /*->16123*/
+/* 16113*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 16115*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_R_PH_MM), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 16123*/ 0, /*End of Scope*/
+/* 16124*/ /*Scope*/ 60, /*->16185*/
+/* 16125*/ OPC_CheckChild0Integer, 15|128,27/*3471*/,
+/* 16128*/ OPC_RecordChild1, // #0 = $imm
+/* 16129*/ OPC_Scope, 33, /*->16164*/ // 3 children in Scope
+/* 16131*/ OPC_MoveChild1,
+/* 16132*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16135*/ OPC_CheckPredicate, 34, // Predicate_immZExt8
+/* 16137*/ OPC_MoveParent,
+/* 16138*/ OPC_Scope, 11, /*->16151*/ // 2 children in Scope
+/* 16140*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16142*/ OPC_EmitConvertToTarget, 0,
+/* 16144*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::REPL_QB), 0,
+ MVT::v4i8, 1/*#Ops*/, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) - Complexity = 12
+ // Dst: (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
+/* 16151*/ /*Scope*/ 11, /*->16163*/
+/* 16152*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 16154*/ OPC_EmitConvertToTarget, 0,
+/* 16156*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::REPL_QB_MM), 0,
+ MVT::v4i8, 1/*#Ops*/, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) - Complexity = 12
+ // Dst: (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
+/* 16163*/ 0, /*End of Scope*/
+/* 16164*/ /*Scope*/ 9, /*->16174*/
+/* 16165*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16167*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::REPLV_QB), 0,
+ MVT::v4i8, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 16174*/ /*Scope*/ 9, /*->16184*/
+/* 16175*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 16177*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::REPLV_QB_MM), 0,
+ MVT::v4i8, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 16184*/ 0, /*End of Scope*/
+/* 16185*/ /*Scope*/ 60, /*->16246*/
+/* 16186*/ OPC_CheckChild0Integer, 14|128,27/*3470*/,
+/* 16189*/ OPC_RecordChild1, // #0 = $imm
+/* 16190*/ OPC_Scope, 33, /*->16225*/ // 3 children in Scope
+/* 16192*/ OPC_MoveChild1,
+/* 16193*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16196*/ OPC_CheckPredicate, 35, // Predicate_immSExt10
+/* 16198*/ OPC_MoveParent,
+/* 16199*/ OPC_Scope, 11, /*->16212*/ // 2 children in Scope
+/* 16201*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16203*/ OPC_EmitConvertToTarget, 0,
+/* 16205*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::REPL_PH), 0,
+ MVT::v2i16, 1/*#Ops*/, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) - Complexity = 12
+ // Dst: (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
+/* 16212*/ /*Scope*/ 11, /*->16224*/
+/* 16213*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 16215*/ OPC_EmitConvertToTarget, 0,
+/* 16217*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::REPL_PH_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) - Complexity = 12
+ // Dst: (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
+/* 16224*/ 0, /*End of Scope*/
+/* 16225*/ /*Scope*/ 9, /*->16235*/
+/* 16226*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16228*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::REPLV_PH), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 16235*/ /*Scope*/ 9, /*->16245*/
+/* 16236*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 16238*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::REPLV_PH_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 16245*/ 0, /*End of Scope*/
+/* 16246*/ /*Scope*/ 43, /*->16290*/
+/* 16247*/ OPC_CheckChild0Integer, 5|128,27/*3461*/,
+/* 16250*/ OPC_RecordChild1, // #0 = $src
+/* 16251*/ OPC_RecordChild2, // #1 = $rs
+/* 16252*/ OPC_RecordChild3, // #2 = $sa
+/* 16253*/ OPC_MoveChild3,
+/* 16254*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16257*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 16259*/ OPC_MoveParent,
+/* 16260*/ OPC_Scope, 13, /*->16275*/ // 2 children in Scope
+/* 16262*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16264*/ OPC_EmitConvertToTarget, 2,
+/* 16266*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECR_SRA_PH_W), 0,
+ MVT::v2i16, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3461:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 16275*/ /*Scope*/ 13, /*->16289*/
+/* 16276*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 16278*/ OPC_EmitConvertToTarget, 2,
+/* 16280*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECR_SRA_PH_W_MMR2), 0,
+ MVT::v2i16, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3461:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 16289*/ 0, /*End of Scope*/
+/* 16290*/ /*Scope*/ 43, /*->16334*/
+/* 16291*/ OPC_CheckChild0Integer, 6|128,27/*3462*/,
+/* 16294*/ OPC_RecordChild1, // #0 = $src
+/* 16295*/ OPC_RecordChild2, // #1 = $rs
+/* 16296*/ OPC_RecordChild3, // #2 = $sa
+/* 16297*/ OPC_MoveChild3,
+/* 16298*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16301*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 16303*/ OPC_MoveParent,
+/* 16304*/ OPC_Scope, 13, /*->16319*/ // 2 children in Scope
+/* 16306*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16308*/ OPC_EmitConvertToTarget, 2,
+/* 16310*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECR_SRA_R_PH_W), 0,
+ MVT::v2i16, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3462:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 16319*/ /*Scope*/ 13, /*->16333*/
+/* 16320*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 16322*/ OPC_EmitConvertToTarget, 2,
+/* 16324*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECR_SRA_R_PH_W_MMR2), 0,
+ MVT::v2i16, 3/*#Ops*/, 1, 3, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3462:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) - Complexity = 12
+ // Dst: (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+/* 16333*/ 0, /*End of Scope*/
+/* 16334*/ /*Scope*/ 65, /*->16400*/
+/* 16335*/ OPC_CheckChild0Integer, 35|128,27/*3491*/,
+/* 16338*/ OPC_RecordChild1, // #0 = $rt
+/* 16339*/ OPC_RecordChild2, // #1 = $rs_sa
+/* 16340*/ OPC_Scope, 35, /*->16377*/ // 3 children in Scope
+/* 16342*/ OPC_MoveChild2,
+/* 16343*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16346*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 16348*/ OPC_MoveParent,
+/* 16349*/ OPC_Scope, 12, /*->16363*/ // 2 children in Scope
+/* 16351*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16353*/ OPC_EmitConvertToTarget, 1,
+/* 16355*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_R_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) - Complexity = 12
+ // Dst: (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+/* 16363*/ /*Scope*/ 12, /*->16376*/
+/* 16364*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 16366*/ OPC_EmitConvertToTarget, 1,
+/* 16368*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_R_QB_MMR2), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) - Complexity = 12
+ // Dst: (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
+/* 16376*/ 0, /*End of Scope*/
+/* 16377*/ /*Scope*/ 10, /*->16388*/
+/* 16378*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16380*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_R_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 16388*/ /*Scope*/ 10, /*->16399*/
+/* 16389*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 16391*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_R_QB_MMR2), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 16399*/ 0, /*End of Scope*/
+/* 16400*/ /*Scope*/ 49, /*->16450*/
+/* 16401*/ OPC_CheckChild0Integer, 32|128,27/*3488*/,
+/* 16404*/ OPC_RecordChild1, // #0 = $a
+/* 16405*/ OPC_RecordChild2, // #1 = $shamt
+/* 16406*/ OPC_Scope, 19, /*->16427*/ // 3 children in Scope
+/* 16408*/ OPC_MoveChild2,
+/* 16409*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16412*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 16414*/ OPC_MoveParent,
+/* 16415*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16417*/ OPC_EmitConvertToTarget, 1,
+/* 16419*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) - Complexity = 12
+ // Dst: (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
+/* 16427*/ /*Scope*/ 10, /*->16438*/
+/* 16428*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16430*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 16438*/ /*Scope*/ 10, /*->16449*/
+/* 16439*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 16441*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_PH_MM), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 16449*/ 0, /*End of Scope*/
+/* 16450*/ /*Scope*/ 49, /*->16500*/
+/* 16451*/ OPC_CheckChild0Integer, 37|128,27/*3493*/,
+/* 16454*/ OPC_RecordChild1, // #0 = $a
+/* 16455*/ OPC_RecordChild2, // #1 = $shamt
+/* 16456*/ OPC_Scope, 19, /*->16477*/ // 3 children in Scope
+/* 16458*/ OPC_MoveChild2,
+/* 16459*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16462*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 16464*/ OPC_MoveParent,
+/* 16465*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16467*/ OPC_EmitConvertToTarget, 1,
+/* 16469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRL_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) - Complexity = 12
+ // Dst: (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
+/* 16477*/ /*Scope*/ 10, /*->16488*/
+/* 16478*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16480*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRLV_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 16488*/ /*Scope*/ 10, /*->16499*/
+/* 16489*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 16491*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRLV_PH_MMR2), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 16499*/ 0, /*End of Scope*/
+/* 16500*/ /*Scope*/ 49, /*->16550*/
+/* 16501*/ OPC_CheckChild0Integer, 33|128,27/*3489*/,
+/* 16504*/ OPC_RecordChild1, // #0 = $a
+/* 16505*/ OPC_RecordChild2, // #1 = $shamt
+/* 16506*/ OPC_Scope, 19, /*->16527*/ // 3 children in Scope
+/* 16508*/ OPC_MoveChild2,
+/* 16509*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16512*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 16514*/ OPC_MoveParent,
+/* 16515*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16517*/ OPC_EmitConvertToTarget, 1,
+/* 16519*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) - Complexity = 12
+ // Dst: (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
+/* 16527*/ /*Scope*/ 10, /*->16538*/
+/* 16528*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 16530*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 16538*/ /*Scope*/ 10, /*->16549*/
+/* 16539*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 16541*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRAV_QB_MMR2), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 16549*/ 0, /*End of Scope*/
+/* 16550*/ /*Scope*/ 49, /*->16600*/
+/* 16551*/ OPC_CheckChild0Integer, 38|128,27/*3494*/,
+/* 16554*/ OPC_RecordChild1, // #0 = $a
+/* 16555*/ OPC_RecordChild2, // #1 = $shamt
+/* 16556*/ OPC_Scope, 19, /*->16577*/ // 3 children in Scope
+/* 16558*/ OPC_MoveChild2,
+/* 16559*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16562*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 16564*/ OPC_MoveParent,
+/* 16565*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16567*/ OPC_EmitConvertToTarget, 1,
+/* 16569*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRL_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) - Complexity = 12
+ // Dst: (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
+/* 16577*/ /*Scope*/ 10, /*->16588*/
+/* 16578*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 16580*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRLV_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) - Complexity = 8
+ // Dst: (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+/* 16588*/ /*Scope*/ 10, /*->16599*/
+/* 16589*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 16591*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRLV_QB_MM), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 8
+ // Dst: (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 16599*/ 0, /*End of Scope*/
+/* 16600*/ /*Scope*/ 24, /*->16625*/
+/* 16601*/ OPC_CheckChild0Integer, 16|128,27/*3472*/,
+/* 16604*/ OPC_RecordChild1, // #0 = $ws
+/* 16605*/ OPC_RecordChild2, // #1 = $m
+/* 16606*/ OPC_MoveChild2,
+/* 16607*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16610*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 16612*/ OPC_MoveParent,
+/* 16613*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16615*/ OPC_EmitConvertToTarget, 1,
+/* 16617*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SAT_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3472:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) - Complexity = 12
+ // Dst: (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16625*/ /*Scope*/ 24, /*->16650*/
+/* 16626*/ OPC_CheckChild0Integer, 18|128,27/*3474*/,
+/* 16629*/ OPC_RecordChild1, // #0 = $ws
+/* 16630*/ OPC_RecordChild2, // #1 = $m
+/* 16631*/ OPC_MoveChild2,
+/* 16632*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16635*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 16637*/ OPC_MoveParent,
+/* 16638*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16640*/ OPC_EmitConvertToTarget, 1,
+/* 16642*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SAT_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3474:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) - Complexity = 12
+ // Dst: (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16650*/ /*Scope*/ 24, /*->16675*/
+/* 16651*/ OPC_CheckChild0Integer, 19|128,27/*3475*/,
+/* 16654*/ OPC_RecordChild1, // #0 = $ws
+/* 16655*/ OPC_RecordChild2, // #1 = $m
+/* 16656*/ OPC_MoveChild2,
+/* 16657*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16660*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 16662*/ OPC_MoveParent,
+/* 16663*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16665*/ OPC_EmitConvertToTarget, 1,
+/* 16667*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SAT_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3475:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) - Complexity = 12
+ // Dst: (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16675*/ /*Scope*/ 24, /*->16700*/
+/* 16676*/ OPC_CheckChild0Integer, 17|128,27/*3473*/,
+/* 16679*/ OPC_RecordChild1, // #0 = $ws
+/* 16680*/ OPC_RecordChild2, // #1 = $m
+/* 16681*/ OPC_MoveChild2,
+/* 16682*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16685*/ OPC_CheckPredicate, 36, // Predicate_immZExt6
+/* 16687*/ OPC_MoveParent,
+/* 16688*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16690*/ OPC_EmitConvertToTarget, 1,
+/* 16692*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SAT_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3473:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) - Complexity = 12
+ // Dst: (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16700*/ /*Scope*/ 24, /*->16725*/
+/* 16701*/ OPC_CheckChild0Integer, 20|128,27/*3476*/,
+/* 16704*/ OPC_RecordChild1, // #0 = $ws
+/* 16705*/ OPC_RecordChild2, // #1 = $m
+/* 16706*/ OPC_MoveChild2,
+/* 16707*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16710*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 16712*/ OPC_MoveParent,
+/* 16713*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16715*/ OPC_EmitConvertToTarget, 1,
+/* 16717*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SAT_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3476:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) - Complexity = 12
+ // Dst: (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16725*/ /*Scope*/ 24, /*->16750*/
+/* 16726*/ OPC_CheckChild0Integer, 22|128,27/*3478*/,
+/* 16729*/ OPC_RecordChild1, // #0 = $ws
+/* 16730*/ OPC_RecordChild2, // #1 = $m
+/* 16731*/ OPC_MoveChild2,
+/* 16732*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16735*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 16737*/ OPC_MoveParent,
+/* 16738*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16740*/ OPC_EmitConvertToTarget, 1,
+/* 16742*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SAT_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3478:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) - Complexity = 12
+ // Dst: (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16750*/ /*Scope*/ 24, /*->16775*/
+/* 16751*/ OPC_CheckChild0Integer, 23|128,27/*3479*/,
+/* 16754*/ OPC_RecordChild1, // #0 = $ws
+/* 16755*/ OPC_RecordChild2, // #1 = $m
+/* 16756*/ OPC_MoveChild2,
+/* 16757*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16760*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 16762*/ OPC_MoveParent,
+/* 16763*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16765*/ OPC_EmitConvertToTarget, 1,
+/* 16767*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SAT_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3479:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) - Complexity = 12
+ // Dst: (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16775*/ /*Scope*/ 24, /*->16800*/
+/* 16776*/ OPC_CheckChild0Integer, 21|128,27/*3477*/,
+/* 16779*/ OPC_RecordChild1, // #0 = $ws
+/* 16780*/ OPC_RecordChild2, // #1 = $m
+/* 16781*/ OPC_MoveChild2,
+/* 16782*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16785*/ OPC_CheckPredicate, 36, // Predicate_immZExt6
+/* 16787*/ OPC_MoveParent,
+/* 16788*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16790*/ OPC_EmitConvertToTarget, 1,
+/* 16792*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SAT_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3477:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) - Complexity = 12
+ // Dst: (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16800*/ /*Scope*/ 26, /*->16827*/
+/* 16801*/ OPC_CheckChild0Integer, 43|128,27/*3499*/,
+/* 16804*/ OPC_RecordChild1, // #0 = $wd_in
+/* 16805*/ OPC_RecordChild2, // #1 = $ws
+/* 16806*/ OPC_RecordChild3, // #2 = $n
+/* 16807*/ OPC_MoveChild3,
+/* 16808*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16811*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 16813*/ OPC_MoveParent,
+/* 16814*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16816*/ OPC_EmitConvertToTarget, 2,
+/* 16818*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLDI_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 1, 3,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3499:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$n) - Complexity = 12
+ // Dst: (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$n)
+/* 16827*/ /*Scope*/ 26, /*->16854*/
+/* 16828*/ OPC_CheckChild0Integer, 45|128,27/*3501*/,
+/* 16831*/ OPC_RecordChild1, // #0 = $wd_in
+/* 16832*/ OPC_RecordChild2, // #1 = $ws
+/* 16833*/ OPC_RecordChild3, // #2 = $n
+/* 16834*/ OPC_MoveChild3,
+/* 16835*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16838*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 16840*/ OPC_MoveParent,
+/* 16841*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16843*/ OPC_EmitConvertToTarget, 2,
+/* 16845*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLDI_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 3,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3501:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$n) - Complexity = 12
+ // Dst: (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$n)
+/* 16854*/ /*Scope*/ 26, /*->16881*/
+/* 16855*/ OPC_CheckChild0Integer, 46|128,27/*3502*/,
+/* 16858*/ OPC_RecordChild1, // #0 = $wd_in
+/* 16859*/ OPC_RecordChild2, // #1 = $ws
+/* 16860*/ OPC_RecordChild3, // #2 = $n
+/* 16861*/ OPC_MoveChild3,
+/* 16862*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16865*/ OPC_CheckPredicate, 33, // Predicate_immZExt2
+/* 16867*/ OPC_MoveParent,
+/* 16868*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16870*/ OPC_EmitConvertToTarget, 2,
+/* 16872*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLDI_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 3,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3502:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$n) - Complexity = 12
+ // Dst: (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$n)
+/* 16881*/ /*Scope*/ 26, /*->16908*/
+/* 16882*/ OPC_CheckChild0Integer, 44|128,27/*3500*/,
+/* 16885*/ OPC_RecordChild1, // #0 = $wd_in
+/* 16886*/ OPC_RecordChild2, // #1 = $ws
+/* 16887*/ OPC_RecordChild3, // #2 = $n
+/* 16888*/ OPC_MoveChild3,
+/* 16889*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16892*/ OPC_CheckPredicate, 37, // Predicate_immZExt1
+/* 16894*/ OPC_MoveParent,
+/* 16895*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16897*/ OPC_EmitConvertToTarget, 2,
+/* 16899*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLDI_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 3,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3500:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt1>>:$n) - Complexity = 12
+ // Dst: (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$n)
+/* 16908*/ /*Scope*/ 24, /*->16933*/
+/* 16909*/ OPC_CheckChild0Integer, 75|128,27/*3531*/,
+/* 16912*/ OPC_RecordChild1, // #0 = $ws
+/* 16913*/ OPC_RecordChild2, // #1 = $m
+/* 16914*/ OPC_MoveChild2,
+/* 16915*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16918*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 16920*/ OPC_MoveParent,
+/* 16921*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16923*/ OPC_EmitConvertToTarget, 1,
+/* 16925*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRARI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3531:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) - Complexity = 12
+ // Dst: (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16933*/ /*Scope*/ 24, /*->16958*/
+/* 16934*/ OPC_CheckChild0Integer, 77|128,27/*3533*/,
+/* 16937*/ OPC_RecordChild1, // #0 = $ws
+/* 16938*/ OPC_RecordChild2, // #1 = $m
+/* 16939*/ OPC_MoveChild2,
+/* 16940*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16943*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 16945*/ OPC_MoveParent,
+/* 16946*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16948*/ OPC_EmitConvertToTarget, 1,
+/* 16950*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRARI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3533:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) - Complexity = 12
+ // Dst: (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16958*/ /*Scope*/ 24, /*->16983*/
+/* 16959*/ OPC_CheckChild0Integer, 78|128,27/*3534*/,
+/* 16962*/ OPC_RecordChild1, // #0 = $ws
+/* 16963*/ OPC_RecordChild2, // #1 = $m
+/* 16964*/ OPC_MoveChild2,
+/* 16965*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16968*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 16970*/ OPC_MoveParent,
+/* 16971*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16973*/ OPC_EmitConvertToTarget, 1,
+/* 16975*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRARI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3534:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) - Complexity = 12
+ // Dst: (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
+/* 16983*/ /*Scope*/ 24, /*->17008*/
+/* 16984*/ OPC_CheckChild0Integer, 76|128,27/*3532*/,
+/* 16987*/ OPC_RecordChild1, // #0 = $ws
+/* 16988*/ OPC_RecordChild2, // #1 = $m
+/* 16989*/ OPC_MoveChild2,
+/* 16990*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 16993*/ OPC_CheckPredicate, 36, // Predicate_immZExt6
+/* 16995*/ OPC_MoveParent,
+/* 16996*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 16998*/ OPC_EmitConvertToTarget, 1,
+/* 17000*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRARI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3532:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) - Complexity = 12
+ // Dst: (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
+/* 17008*/ /*Scope*/ 24, /*->17033*/
+/* 17009*/ OPC_CheckChild0Integer, 91|128,27/*3547*/,
+/* 17012*/ OPC_RecordChild1, // #0 = $ws
+/* 17013*/ OPC_RecordChild2, // #1 = $m
+/* 17014*/ OPC_MoveChild2,
+/* 17015*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 17018*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 17020*/ OPC_MoveParent,
+/* 17021*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17023*/ OPC_EmitConvertToTarget, 1,
+/* 17025*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLRI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3547:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) - Complexity = 12
+ // Dst: (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
+/* 17033*/ /*Scope*/ 24, /*->17058*/
+/* 17034*/ OPC_CheckChild0Integer, 93|128,27/*3549*/,
+/* 17037*/ OPC_RecordChild1, // #0 = $ws
+/* 17038*/ OPC_RecordChild2, // #1 = $m
+/* 17039*/ OPC_MoveChild2,
+/* 17040*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 17043*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 17045*/ OPC_MoveParent,
+/* 17046*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17048*/ OPC_EmitConvertToTarget, 1,
+/* 17050*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLRI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3549:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) - Complexity = 12
+ // Dst: (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
+/* 17058*/ /*Scope*/ 24, /*->17083*/
+/* 17059*/ OPC_CheckChild0Integer, 94|128,27/*3550*/,
+/* 17062*/ OPC_RecordChild1, // #0 = $ws
+/* 17063*/ OPC_RecordChild2, // #1 = $m
+/* 17064*/ OPC_MoveChild2,
+/* 17065*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 17068*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 17070*/ OPC_MoveParent,
+/* 17071*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17073*/ OPC_EmitConvertToTarget, 1,
+/* 17075*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLRI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3550:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) - Complexity = 12
+ // Dst: (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
+/* 17083*/ /*Scope*/ 24, /*->17108*/
+/* 17084*/ OPC_CheckChild0Integer, 92|128,27/*3548*/,
+/* 17087*/ OPC_RecordChild1, // #0 = $ws
+/* 17088*/ OPC_RecordChild2, // #1 = $m
+/* 17089*/ OPC_MoveChild2,
+/* 17090*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 17093*/ OPC_CheckPredicate, 36, // Predicate_immZExt6
+/* 17095*/ OPC_MoveParent,
+/* 17096*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17098*/ OPC_EmitConvertToTarget, 1,
+/* 17100*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLRI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3548:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) - Complexity = 12
+ // Dst: (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
+/* 17108*/ /*Scope*/ 29, /*->17138*/
+/* 17109*/ OPC_CheckChild0Integer, 18|128,23/*2962*/,
+/* 17112*/ OPC_RecordChild1, // #0 = $rs
+/* 17113*/ OPC_RecordChild2, // #1 = $rt
+/* 17114*/ OPC_Scope, 10, /*->17126*/ // 2 children in Scope
+/* 17116*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17118*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU_S_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 2962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17126*/ /*Scope*/ 10, /*->17137*/
+/* 17127*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17129*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU_S_QB_MM), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 2962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17137*/ 0, /*End of Scope*/
+/* 17138*/ /*Scope*/ 29, /*->17168*/
+/* 17139*/ OPC_CheckChild0Integer, 125|128,27/*3581*/,
+/* 17142*/ OPC_RecordChild1, // #0 = $rs
+/* 17143*/ OPC_RecordChild2, // #1 = $rt
+/* 17144*/ OPC_Scope, 10, /*->17156*/ // 2 children in Scope
+/* 17146*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17148*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_S_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3581:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17156*/ /*Scope*/ 10, /*->17167*/
+/* 17157*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17159*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_S_QB_MM), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3581:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17167*/ 0, /*End of Scope*/
+/* 17168*/ /*Scope*/ 29, /*->17198*/
+/* 17169*/ OPC_CheckChild0Integer, 124|128,22/*2940*/,
+/* 17172*/ OPC_RecordChild1, // #0 = $rs
+/* 17173*/ OPC_RecordChild2, // #1 = $rt
+/* 17174*/ OPC_Scope, 10, /*->17186*/ // 2 children in Scope
+/* 17176*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17178*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQ_S_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 2940:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17186*/ /*Scope*/ 10, /*->17197*/
+/* 17187*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17189*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQ_S_PH_MM), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 2940:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17197*/ 0, /*End of Scope*/
+/* 17198*/ /*Scope*/ 29, /*->17228*/
+/* 17199*/ OPC_CheckChild0Integer, 100|128,27/*3556*/,
+/* 17202*/ OPC_RecordChild1, // #0 = $rs
+/* 17203*/ OPC_RecordChild2, // #1 = $rt
+/* 17204*/ OPC_Scope, 10, /*->17216*/ // 2 children in Scope
+/* 17206*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17208*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQ_S_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3556:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17216*/ /*Scope*/ 10, /*->17227*/
+/* 17217*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17219*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQ_S_PH_MM), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3556:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17227*/ 0, /*End of Scope*/
+/* 17228*/ /*Scope*/ 29, /*->17258*/
+/* 17229*/ OPC_CheckChild0Integer, 8|128,27/*3464*/,
+/* 17232*/ OPC_RecordChild1, // #0 = $rs
+/* 17233*/ OPC_RecordChild2, // #1 = $rt
+/* 17234*/ OPC_Scope, 10, /*->17246*/ // 2 children in Scope
+/* 17236*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17238*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECRQ_QB_PH), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3464:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17246*/ /*Scope*/ 10, /*->17257*/
+/* 17247*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17249*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECRQ_QB_PH_MM), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3464:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17257*/ 0, /*End of Scope*/
+/* 17258*/ /*Scope*/ 29, /*->17288*/
+/* 17259*/ OPC_CheckChild0Integer, 7|128,27/*3463*/,
+/* 17262*/ OPC_RecordChild1, // #0 = $rs
+/* 17263*/ OPC_RecordChild2, // #1 = $rt
+/* 17264*/ OPC_Scope, 10, /*->17276*/ // 2 children in Scope
+/* 17266*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17268*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECRQ_PH_W), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 17276*/ /*Scope*/ 10, /*->17287*/
+/* 17277*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17279*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECRQ_PH_W_MM), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 17287*/ 0, /*End of Scope*/
+/* 17288*/ /*Scope*/ 26, /*->17315*/
+/* 17289*/ OPC_CheckChild0Integer, 124|128,26/*3452*/,
+/* 17292*/ OPC_RecordChild1, // #0 = $rt
+/* 17293*/ OPC_Scope, 9, /*->17304*/ // 2 children in Scope
+/* 17295*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17297*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQU_PH_QBL), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17304*/ /*Scope*/ 9, /*->17314*/
+/* 17305*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17307*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQU_PH_QBL_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 17314*/ 0, /*End of Scope*/
+/* 17315*/ /*Scope*/ 26, /*->17342*/
+/* 17316*/ OPC_CheckChild0Integer, 126|128,26/*3454*/,
+/* 17319*/ OPC_RecordChild1, // #0 = $rt
+/* 17320*/ OPC_Scope, 9, /*->17331*/ // 2 children in Scope
+/* 17322*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17324*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQU_PH_QBR), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3454:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17331*/ /*Scope*/ 9, /*->17341*/
+/* 17332*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17334*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQU_PH_QBR_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3454:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 17341*/ 0, /*End of Scope*/
+/* 17342*/ /*Scope*/ 26, /*->17369*/
+/* 17343*/ OPC_CheckChild0Integer, 125|128,26/*3453*/,
+/* 17346*/ OPC_RecordChild1, // #0 = $rt
+/* 17347*/ OPC_Scope, 9, /*->17358*/ // 2 children in Scope
+/* 17349*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17351*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQU_PH_QBLA), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3453:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17358*/ /*Scope*/ 9, /*->17368*/
+/* 17359*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17361*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQU_PH_QBLA_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3453:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 17368*/ 0, /*End of Scope*/
+/* 17369*/ /*Scope*/ 26, /*->17396*/
+/* 17370*/ OPC_CheckChild0Integer, 127|128,26/*3455*/,
+/* 17373*/ OPC_RecordChild1, // #0 = $rt
+/* 17374*/ OPC_Scope, 9, /*->17385*/ // 2 children in Scope
+/* 17376*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17378*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQU_PH_QBRA), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3455:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17385*/ /*Scope*/ 9, /*->17395*/
+/* 17386*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17388*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEQU_PH_QBRA_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3455:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 17395*/ 0, /*End of Scope*/
+/* 17396*/ /*Scope*/ 26, /*->17423*/
+/* 17397*/ OPC_CheckChild0Integer, 0|128,27/*3456*/,
+/* 17400*/ OPC_RecordChild1, // #0 = $rt
+/* 17401*/ OPC_Scope, 9, /*->17412*/ // 2 children in Scope
+/* 17403*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17405*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEU_PH_QBL), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3456:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17412*/ /*Scope*/ 9, /*->17422*/
+/* 17413*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17415*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEU_PH_QBL_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3456:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 17422*/ 0, /*End of Scope*/
+/* 17423*/ /*Scope*/ 26, /*->17450*/
+/* 17424*/ OPC_CheckChild0Integer, 2|128,27/*3458*/,
+/* 17427*/ OPC_RecordChild1, // #0 = $rt
+/* 17428*/ OPC_Scope, 9, /*->17439*/ // 2 children in Scope
+/* 17430*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17432*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEU_PH_QBR), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3458:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17439*/ /*Scope*/ 9, /*->17449*/
+/* 17440*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17442*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEU_PH_QBR_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3458:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 17449*/ 0, /*End of Scope*/
+/* 17450*/ /*Scope*/ 26, /*->17477*/
+/* 17451*/ OPC_CheckChild0Integer, 1|128,27/*3457*/,
+/* 17454*/ OPC_RecordChild1, // #0 = $rt
+/* 17455*/ OPC_Scope, 9, /*->17466*/ // 2 children in Scope
+/* 17457*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17459*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEU_PH_QBLA), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3457:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17466*/ /*Scope*/ 9, /*->17476*/
+/* 17467*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEU_PH_QBLA_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3457:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 17476*/ 0, /*End of Scope*/
+/* 17477*/ /*Scope*/ 26, /*->17504*/
+/* 17478*/ OPC_CheckChild0Integer, 3|128,27/*3459*/,
+/* 17481*/ OPC_RecordChild1, // #0 = $rt
+/* 17482*/ OPC_Scope, 9, /*->17493*/ // 2 children in Scope
+/* 17484*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17486*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEU_PH_QBRA), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3459:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17493*/ /*Scope*/ 9, /*->17503*/
+/* 17494*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17496*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PRECEU_PH_QBRA_MM), 0,
+ MVT::v2i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3459:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) - Complexity = 8
+ // Dst: (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+/* 17503*/ 0, /*End of Scope*/
+/* 17504*/ /*Scope*/ 29, /*->17534*/
+/* 17505*/ OPC_CheckChild0Integer, 107|128,26/*3435*/,
+/* 17508*/ OPC_RecordChild1, // #0 = $rs
+/* 17509*/ OPC_RecordChild2, // #1 = $rt
+/* 17510*/ OPC_Scope, 10, /*->17522*/ // 2 children in Scope
+/* 17512*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17514*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PACKRL_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17522*/ /*Scope*/ 10, /*->17533*/
+/* 17523*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 17525*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PACKRL_PH_MM), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17533*/ 0, /*End of Scope*/
+/* 17534*/ /*Scope*/ 29, /*->17564*/
+/* 17535*/ OPC_CheckChild0Integer, 19|128,23/*2963*/,
+/* 17538*/ OPC_RecordChild1, // #0 = $rs
+/* 17539*/ OPC_RecordChild2, // #1 = $rt
+/* 17540*/ OPC_Scope, 10, /*->17552*/ // 2 children in Scope
+/* 17542*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 17544*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDUH_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 2963:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17552*/ /*Scope*/ 10, /*->17563*/
+/* 17553*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 17555*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDUH_QB_MMR2), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 2963:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17563*/ 0, /*End of Scope*/
+/* 17564*/ /*Scope*/ 29, /*->17594*/
+/* 17565*/ OPC_CheckChild0Integer, 20|128,23/*2964*/,
+/* 17568*/ OPC_RecordChild1, // #0 = $rs
+/* 17569*/ OPC_RecordChild2, // #1 = $rt
+/* 17570*/ OPC_Scope, 10, /*->17582*/ // 2 children in Scope
+/* 17572*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 17574*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDUH_R_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 2964:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17582*/ /*Scope*/ 10, /*->17593*/
+/* 17583*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 17585*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDUH_R_QB_MMR2), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 2964:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17593*/ 0, /*End of Scope*/
+/* 17594*/ /*Scope*/ 29, /*->17624*/
+/* 17595*/ OPC_CheckChild0Integer, 126|128,27/*3582*/,
+/* 17598*/ OPC_RecordChild1, // #0 = $rs
+/* 17599*/ OPC_RecordChild2, // #1 = $rt
+/* 17600*/ OPC_Scope, 10, /*->17612*/ // 2 children in Scope
+/* 17602*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 17604*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBUH_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3582:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17612*/ /*Scope*/ 10, /*->17623*/
+/* 17613*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 17615*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBUH_QB_MMR2), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3582:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17623*/ 0, /*End of Scope*/
+/* 17624*/ /*Scope*/ 29, /*->17654*/
+/* 17625*/ OPC_CheckChild0Integer, 127|128,27/*3583*/,
+/* 17628*/ OPC_RecordChild1, // #0 = $rs
+/* 17629*/ OPC_RecordChild2, // #1 = $rt
+/* 17630*/ OPC_Scope, 10, /*->17642*/ // 2 children in Scope
+/* 17632*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 17634*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBUH_R_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3583:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17642*/ /*Scope*/ 10, /*->17653*/
+/* 17643*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 17645*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBUH_R_QB_MMR2), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3583:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 17653*/ 0, /*End of Scope*/
+/* 17654*/ /*Scope*/ 29, /*->17684*/
+/* 17655*/ OPC_CheckChild0Integer, 126|128,22/*2942*/,
+/* 17658*/ OPC_RecordChild1, // #0 = $rs
+/* 17659*/ OPC_RecordChild2, // #1 = $rt
+/* 17660*/ OPC_Scope, 10, /*->17672*/ // 2 children in Scope
+/* 17662*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 17664*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQH_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 2942:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17672*/ /*Scope*/ 10, /*->17683*/
+/* 17673*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 17675*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQH_PH_MMR2), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 2942:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17683*/ 0, /*End of Scope*/
+/* 17684*/ /*Scope*/ 29, /*->17714*/
+/* 17685*/ OPC_CheckChild0Integer, 127|128,22/*2943*/,
+/* 17688*/ OPC_RecordChild1, // #0 = $rs
+/* 17689*/ OPC_RecordChild2, // #1 = $rt
+/* 17690*/ OPC_Scope, 10, /*->17702*/ // 2 children in Scope
+/* 17692*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 17694*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQH_R_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 2943:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17702*/ /*Scope*/ 10, /*->17713*/
+/* 17703*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 17705*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQH_R_PH_MMR2), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 2943:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17713*/ 0, /*End of Scope*/
+/* 17714*/ /*Scope*/ 29, /*->17744*/
+/* 17715*/ OPC_CheckChild0Integer, 102|128,27/*3558*/,
+/* 17718*/ OPC_RecordChild1, // #0 = $rs
+/* 17719*/ OPC_RecordChild2, // #1 = $rt
+/* 17720*/ OPC_Scope, 10, /*->17732*/ // 2 children in Scope
+/* 17722*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 17724*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQH_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3558:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17732*/ /*Scope*/ 10, /*->17743*/
+/* 17733*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 17735*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQH_PH_MMR2), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3558:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17743*/ 0, /*End of Scope*/
+/* 17744*/ /*Scope*/ 29, /*->17774*/
+/* 17745*/ OPC_CheckChild0Integer, 103|128,27/*3559*/,
+/* 17748*/ OPC_RecordChild1, // #0 = $rs
+/* 17749*/ OPC_RecordChild2, // #1 = $rt
+/* 17750*/ OPC_Scope, 10, /*->17762*/ // 2 children in Scope
+/* 17752*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 17754*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQH_R_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3559:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17762*/ /*Scope*/ 10, /*->17773*/
+/* 17763*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 17765*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQH_R_PH_MMR2), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3559:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 17773*/ 0, /*End of Scope*/
+/* 17774*/ /*Scope*/ 15, /*->17790*/
+/* 17775*/ OPC_CheckChild0Integer, 123|128,22/*2939*/,
+/* 17778*/ OPC_RecordChild1, // #0 = $a
+/* 17779*/ OPC_RecordChild2, // #1 = $b
+/* 17780*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17782*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQ_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 2939:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) - Complexity = 8
+ // Dst: (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+/* 17790*/ /*Scope*/ 15, /*->17806*/
+/* 17791*/ OPC_CheckChild0Integer, 99|128,27/*3555*/,
+/* 17794*/ OPC_RecordChild1, // #0 = $a
+/* 17795*/ OPC_RecordChild2, // #1 = $b
+/* 17796*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17798*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQ_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i16] } 3555:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) - Complexity = 8
+ // Dst: (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+/* 17806*/ /*Scope*/ 15, /*->17822*/
+/* 17807*/ OPC_CheckChild0Integer, 16|128,23/*2960*/,
+/* 17810*/ OPC_RecordChild1, // #0 = $a
+/* 17811*/ OPC_RecordChild2, // #1 = $b
+/* 17812*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17814*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 2960:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) - Complexity = 8
+ // Dst: (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
+/* 17822*/ /*Scope*/ 15, /*->17838*/
+/* 17823*/ OPC_CheckChild0Integer, 123|128,27/*3579*/,
+/* 17826*/ OPC_RecordChild1, // #0 = $a
+/* 17827*/ OPC_RecordChild2, // #1 = $b
+/* 17828*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 17830*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i8] } 3579:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) - Complexity = 8
+ // Dst: (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
+/* 17838*/ /*Scope*/ 15, /*->17854*/
+/* 17839*/ OPC_CheckChild0Integer, 119|128,22/*2935*/,
+/* 17842*/ OPC_RecordChild1, // #0 = $ws
+/* 17843*/ OPC_RecordChild2, // #1 = $wt
+/* 17844*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17846*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADD_A_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2935:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 17854*/ /*Scope*/ 15, /*->17870*/
+/* 17855*/ OPC_CheckChild0Integer, 121|128,22/*2937*/,
+/* 17858*/ OPC_RecordChild1, // #0 = $ws
+/* 17859*/ OPC_RecordChild2, // #1 = $wt
+/* 17860*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17862*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADD_A_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2937:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 17870*/ /*Scope*/ 15, /*->17886*/
+/* 17871*/ OPC_CheckChild0Integer, 122|128,22/*2938*/,
+/* 17874*/ OPC_RecordChild1, // #0 = $ws
+/* 17875*/ OPC_RecordChild2, // #1 = $wt
+/* 17876*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17878*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADD_A_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2938:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 17886*/ /*Scope*/ 15, /*->17902*/
+/* 17887*/ OPC_CheckChild0Integer, 120|128,22/*2936*/,
+/* 17890*/ OPC_RecordChild1, // #0 = $ws
+/* 17891*/ OPC_RecordChild2, // #1 = $wt
+/* 17892*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17894*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADD_A_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2936:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 17902*/ /*Scope*/ 15, /*->17918*/
+/* 17903*/ OPC_CheckChild0Integer, 2|128,23/*2946*/,
+/* 17906*/ OPC_RecordChild1, // #0 = $ws
+/* 17907*/ OPC_RecordChild2, // #1 = $wt
+/* 17908*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17910*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_A_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2946:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 17918*/ /*Scope*/ 15, /*->17934*/
+/* 17919*/ OPC_CheckChild0Integer, 4|128,23/*2948*/,
+/* 17922*/ OPC_RecordChild1, // #0 = $ws
+/* 17923*/ OPC_RecordChild2, // #1 = $wt
+/* 17924*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17926*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_A_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2948:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 17934*/ /*Scope*/ 15, /*->17950*/
+/* 17935*/ OPC_CheckChild0Integer, 5|128,23/*2949*/,
+/* 17938*/ OPC_RecordChild1, // #0 = $ws
+/* 17939*/ OPC_RecordChild2, // #1 = $wt
+/* 17940*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17942*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_A_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2949:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 17950*/ /*Scope*/ 15, /*->17966*/
+/* 17951*/ OPC_CheckChild0Integer, 3|128,23/*2947*/,
+/* 17954*/ OPC_RecordChild1, // #0 = $ws
+/* 17955*/ OPC_RecordChild2, // #1 = $wt
+/* 17956*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17958*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_A_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2947:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 17966*/ /*Scope*/ 15, /*->17982*/
+/* 17967*/ OPC_CheckChild0Integer, 6|128,23/*2950*/,
+/* 17970*/ OPC_RecordChild1, // #0 = $ws
+/* 17971*/ OPC_RecordChild2, // #1 = $wt
+/* 17972*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17974*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2950:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 17982*/ /*Scope*/ 15, /*->17998*/
+/* 17983*/ OPC_CheckChild0Integer, 8|128,23/*2952*/,
+/* 17986*/ OPC_RecordChild1, // #0 = $ws
+/* 17987*/ OPC_RecordChild2, // #1 = $wt
+/* 17988*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 17990*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2952:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 17998*/ /*Scope*/ 15, /*->18014*/
+/* 17999*/ OPC_CheckChild0Integer, 9|128,23/*2953*/,
+/* 18002*/ OPC_RecordChild1, // #0 = $ws
+/* 18003*/ OPC_RecordChild2, // #1 = $wt
+/* 18004*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18006*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2953:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18014*/ /*Scope*/ 15, /*->18030*/
+/* 18015*/ OPC_CheckChild0Integer, 7|128,23/*2951*/,
+/* 18018*/ OPC_RecordChild1, // #0 = $ws
+/* 18019*/ OPC_RecordChild2, // #1 = $wt
+/* 18020*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18022*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2951:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18030*/ /*Scope*/ 15, /*->18046*/
+/* 18031*/ OPC_CheckChild0Integer, 10|128,23/*2954*/,
+/* 18034*/ OPC_RecordChild1, // #0 = $ws
+/* 18035*/ OPC_RecordChild2, // #1 = $wt
+/* 18036*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18038*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2954:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18046*/ /*Scope*/ 15, /*->18062*/
+/* 18047*/ OPC_CheckChild0Integer, 12|128,23/*2956*/,
+/* 18050*/ OPC_RecordChild1, // #0 = $ws
+/* 18051*/ OPC_RecordChild2, // #1 = $wt
+/* 18052*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18054*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2956:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18062*/ /*Scope*/ 15, /*->18078*/
+/* 18063*/ OPC_CheckChild0Integer, 13|128,23/*2957*/,
+/* 18066*/ OPC_RecordChild1, // #0 = $ws
+/* 18067*/ OPC_RecordChild2, // #1 = $wt
+/* 18068*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18070*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2957:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18078*/ /*Scope*/ 15, /*->18094*/
+/* 18079*/ OPC_CheckChild0Integer, 11|128,23/*2955*/,
+/* 18082*/ OPC_RecordChild1, // #0 = $ws
+/* 18083*/ OPC_RecordChild2, // #1 = $wt
+/* 18084*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18086*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDS_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2955:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18094*/ /*Scope*/ 15, /*->18110*/
+/* 18095*/ OPC_CheckChild0Integer, 33|128,23/*2977*/,
+/* 18098*/ OPC_RecordChild1, // #0 = $ws
+/* 18099*/ OPC_RecordChild2, // #1 = $wt
+/* 18100*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18102*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ASUB_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2977:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18110*/ /*Scope*/ 15, /*->18126*/
+/* 18111*/ OPC_CheckChild0Integer, 35|128,23/*2979*/,
+/* 18114*/ OPC_RecordChild1, // #0 = $ws
+/* 18115*/ OPC_RecordChild2, // #1 = $wt
+/* 18116*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18118*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ASUB_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18126*/ /*Scope*/ 15, /*->18142*/
+/* 18127*/ OPC_CheckChild0Integer, 36|128,23/*2980*/,
+/* 18130*/ OPC_RecordChild1, // #0 = $ws
+/* 18131*/ OPC_RecordChild2, // #1 = $wt
+/* 18132*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18134*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ASUB_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2980:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18142*/ /*Scope*/ 15, /*->18158*/
+/* 18143*/ OPC_CheckChild0Integer, 34|128,23/*2978*/,
+/* 18146*/ OPC_RecordChild1, // #0 = $ws
+/* 18147*/ OPC_RecordChild2, // #1 = $wt
+/* 18148*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18150*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ASUB_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2978:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18158*/ /*Scope*/ 15, /*->18174*/
+/* 18159*/ OPC_CheckChild0Integer, 37|128,23/*2981*/,
+/* 18162*/ OPC_RecordChild1, // #0 = $ws
+/* 18163*/ OPC_RecordChild2, // #1 = $wt
+/* 18164*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18166*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ASUB_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2981:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18174*/ /*Scope*/ 15, /*->18190*/
+/* 18175*/ OPC_CheckChild0Integer, 39|128,23/*2983*/,
+/* 18178*/ OPC_RecordChild1, // #0 = $ws
+/* 18179*/ OPC_RecordChild2, // #1 = $wt
+/* 18180*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18182*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ASUB_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2983:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18190*/ /*Scope*/ 15, /*->18206*/
+/* 18191*/ OPC_CheckChild0Integer, 40|128,23/*2984*/,
+/* 18194*/ OPC_RecordChild1, // #0 = $ws
+/* 18195*/ OPC_RecordChild2, // #1 = $wt
+/* 18196*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18198*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ASUB_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2984:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18206*/ /*Scope*/ 15, /*->18222*/
+/* 18207*/ OPC_CheckChild0Integer, 38|128,23/*2982*/,
+/* 18210*/ OPC_RecordChild1, // #0 = $ws
+/* 18211*/ OPC_RecordChild2, // #1 = $wt
+/* 18212*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18214*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ASUB_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2982:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18222*/ /*Scope*/ 15, /*->18238*/
+/* 18223*/ OPC_CheckChild0Integer, 41|128,23/*2985*/,
+/* 18226*/ OPC_RecordChild1, // #0 = $ws
+/* 18227*/ OPC_RecordChild2, // #1 = $wt
+/* 18228*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18230*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVE_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2985:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18238*/ /*Scope*/ 15, /*->18254*/
+/* 18239*/ OPC_CheckChild0Integer, 43|128,23/*2987*/,
+/* 18242*/ OPC_RecordChild1, // #0 = $ws
+/* 18243*/ OPC_RecordChild2, // #1 = $wt
+/* 18244*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18246*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVE_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2987:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18254*/ /*Scope*/ 15, /*->18270*/
+/* 18255*/ OPC_CheckChild0Integer, 44|128,23/*2988*/,
+/* 18258*/ OPC_RecordChild1, // #0 = $ws
+/* 18259*/ OPC_RecordChild2, // #1 = $wt
+/* 18260*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18262*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVE_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2988:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18270*/ /*Scope*/ 15, /*->18286*/
+/* 18271*/ OPC_CheckChild0Integer, 42|128,23/*2986*/,
+/* 18274*/ OPC_RecordChild1, // #0 = $ws
+/* 18275*/ OPC_RecordChild2, // #1 = $wt
+/* 18276*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18278*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVE_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2986:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18286*/ /*Scope*/ 15, /*->18302*/
+/* 18287*/ OPC_CheckChild0Integer, 45|128,23/*2989*/,
+/* 18290*/ OPC_RecordChild1, // #0 = $ws
+/* 18291*/ OPC_RecordChild2, // #1 = $wt
+/* 18292*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18294*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVE_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2989:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18302*/ /*Scope*/ 15, /*->18318*/
+/* 18303*/ OPC_CheckChild0Integer, 47|128,23/*2991*/,
+/* 18306*/ OPC_RecordChild1, // #0 = $ws
+/* 18307*/ OPC_RecordChild2, // #1 = $wt
+/* 18308*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18310*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVE_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2991:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18318*/ /*Scope*/ 15, /*->18334*/
+/* 18319*/ OPC_CheckChild0Integer, 48|128,23/*2992*/,
+/* 18322*/ OPC_RecordChild1, // #0 = $ws
+/* 18323*/ OPC_RecordChild2, // #1 = $wt
+/* 18324*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18326*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVE_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2992:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18334*/ /*Scope*/ 15, /*->18350*/
+/* 18335*/ OPC_CheckChild0Integer, 46|128,23/*2990*/,
+/* 18338*/ OPC_RecordChild1, // #0 = $ws
+/* 18339*/ OPC_RecordChild2, // #1 = $wt
+/* 18340*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18342*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVE_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2990:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18350*/ /*Scope*/ 15, /*->18366*/
+/* 18351*/ OPC_CheckChild0Integer, 49|128,23/*2993*/,
+/* 18354*/ OPC_RecordChild1, // #0 = $ws
+/* 18355*/ OPC_RecordChild2, // #1 = $wt
+/* 18356*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18358*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVER_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2993:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18366*/ /*Scope*/ 15, /*->18382*/
+/* 18367*/ OPC_CheckChild0Integer, 51|128,23/*2995*/,
+/* 18370*/ OPC_RecordChild1, // #0 = $ws
+/* 18371*/ OPC_RecordChild2, // #1 = $wt
+/* 18372*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18374*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVER_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2995:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18382*/ /*Scope*/ 15, /*->18398*/
+/* 18383*/ OPC_CheckChild0Integer, 52|128,23/*2996*/,
+/* 18386*/ OPC_RecordChild1, // #0 = $ws
+/* 18387*/ OPC_RecordChild2, // #1 = $wt
+/* 18388*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18390*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVER_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 2996:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18398*/ /*Scope*/ 15, /*->18414*/
+/* 18399*/ OPC_CheckChild0Integer, 50|128,23/*2994*/,
+/* 18402*/ OPC_RecordChild1, // #0 = $ws
+/* 18403*/ OPC_RecordChild2, // #1 = $wt
+/* 18404*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18406*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVER_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2994:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18414*/ /*Scope*/ 15, /*->18430*/
+/* 18415*/ OPC_CheckChild0Integer, 53|128,23/*2997*/,
+/* 18418*/ OPC_RecordChild1, // #0 = $ws
+/* 18419*/ OPC_RecordChild2, // #1 = $wt
+/* 18420*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18422*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVER_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 2997:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18430*/ /*Scope*/ 15, /*->18446*/
+/* 18431*/ OPC_CheckChild0Integer, 55|128,23/*2999*/,
+/* 18434*/ OPC_RecordChild1, // #0 = $ws
+/* 18435*/ OPC_RecordChild2, // #1 = $wt
+/* 18436*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18438*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVER_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 2999:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18446*/ /*Scope*/ 15, /*->18462*/
+/* 18447*/ OPC_CheckChild0Integer, 56|128,23/*3000*/,
+/* 18450*/ OPC_RecordChild1, // #0 = $ws
+/* 18451*/ OPC_RecordChild2, // #1 = $wt
+/* 18452*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18454*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVER_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3000:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18462*/ /*Scope*/ 15, /*->18478*/
+/* 18463*/ OPC_CheckChild0Integer, 54|128,23/*2998*/,
+/* 18466*/ OPC_RecordChild1, // #0 = $ws
+/* 18467*/ OPC_RecordChild2, // #1 = $wt
+/* 18468*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18470*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AVER_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 2998:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18478*/ /*Scope*/ 17, /*->18496*/
+/* 18479*/ OPC_CheckChild0Integer, 66|128,23/*3010*/,
+/* 18482*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18483*/ OPC_RecordChild2, // #1 = $ws
+/* 18484*/ OPC_RecordChild3, // #2 = $wt
+/* 18485*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18487*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSL_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3010:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18496*/ /*Scope*/ 17, /*->18514*/
+/* 18497*/ OPC_CheckChild0Integer, 68|128,23/*3012*/,
+/* 18500*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18501*/ OPC_RecordChild2, // #1 = $ws
+/* 18502*/ OPC_RecordChild3, // #2 = $wt
+/* 18503*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18505*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSL_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3012:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18514*/ /*Scope*/ 17, /*->18532*/
+/* 18515*/ OPC_CheckChild0Integer, 69|128,23/*3013*/,
+/* 18518*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18519*/ OPC_RecordChild2, // #1 = $ws
+/* 18520*/ OPC_RecordChild3, // #2 = $wt
+/* 18521*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18523*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSL_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3013:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18532*/ /*Scope*/ 17, /*->18550*/
+/* 18533*/ OPC_CheckChild0Integer, 67|128,23/*3011*/,
+/* 18536*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18537*/ OPC_RecordChild2, // #1 = $ws
+/* 18538*/ OPC_RecordChild3, // #2 = $wt
+/* 18539*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18541*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSL_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3011:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18550*/ /*Scope*/ 17, /*->18568*/
+/* 18551*/ OPC_CheckChild0Integer, 74|128,23/*3018*/,
+/* 18554*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18555*/ OPC_RecordChild2, // #1 = $ws
+/* 18556*/ OPC_RecordChild3, // #2 = $wt
+/* 18557*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18559*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSR_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18568*/ /*Scope*/ 17, /*->18586*/
+/* 18569*/ OPC_CheckChild0Integer, 76|128,23/*3020*/,
+/* 18572*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18573*/ OPC_RecordChild2, // #1 = $ws
+/* 18574*/ OPC_RecordChild3, // #2 = $wt
+/* 18575*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18577*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSR_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3020:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18586*/ /*Scope*/ 17, /*->18604*/
+/* 18587*/ OPC_CheckChild0Integer, 77|128,23/*3021*/,
+/* 18590*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18591*/ OPC_RecordChild2, // #1 = $ws
+/* 18592*/ OPC_RecordChild3, // #2 = $wt
+/* 18593*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18595*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSR_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3021:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18604*/ /*Scope*/ 17, /*->18622*/
+/* 18605*/ OPC_CheckChild0Integer, 75|128,23/*3019*/,
+/* 18608*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18609*/ OPC_RecordChild2, // #1 = $ws
+/* 18610*/ OPC_RecordChild3, // #2 = $wt
+/* 18611*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18613*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSR_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3019:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 18622*/ /*Scope*/ 15, /*->18638*/
+/* 18623*/ OPC_CheckChild0Integer, 60|128,24/*3132*/,
+/* 18626*/ OPC_RecordChild1, // #0 = $ws
+/* 18627*/ OPC_RecordChild2, // #1 = $wt
+/* 18628*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18630*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DOTP_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3132:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18638*/ /*Scope*/ 15, /*->18654*/
+/* 18639*/ OPC_CheckChild0Integer, 61|128,24/*3133*/,
+/* 18642*/ OPC_RecordChild1, // #0 = $ws
+/* 18643*/ OPC_RecordChild2, // #1 = $wt
+/* 18644*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18646*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DOTP_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3133:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18654*/ /*Scope*/ 15, /*->18670*/
+/* 18655*/ OPC_CheckChild0Integer, 59|128,24/*3131*/,
+/* 18658*/ OPC_RecordChild1, // #0 = $ws
+/* 18659*/ OPC_RecordChild2, // #1 = $wt
+/* 18660*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18662*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DOTP_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3131:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18670*/ /*Scope*/ 15, /*->18686*/
+/* 18671*/ OPC_CheckChild0Integer, 63|128,24/*3135*/,
+/* 18674*/ OPC_RecordChild1, // #0 = $ws
+/* 18675*/ OPC_RecordChild2, // #1 = $wt
+/* 18676*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18678*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DOTP_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3135:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18686*/ /*Scope*/ 15, /*->18702*/
+/* 18687*/ OPC_CheckChild0Integer, 64|128,24/*3136*/,
+/* 18690*/ OPC_RecordChild1, // #0 = $ws
+/* 18691*/ OPC_RecordChild2, // #1 = $wt
+/* 18692*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18694*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DOTP_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3136:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18702*/ /*Scope*/ 15, /*->18718*/
+/* 18703*/ OPC_CheckChild0Integer, 62|128,24/*3134*/,
+/* 18706*/ OPC_RecordChild1, // #0 = $ws
+/* 18707*/ OPC_RecordChild2, // #1 = $wt
+/* 18708*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18710*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DOTP_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3134:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18718*/ /*Scope*/ 17, /*->18736*/
+/* 18719*/ OPC_CheckChild0Integer, 67|128,24/*3139*/,
+/* 18722*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18723*/ OPC_RecordChild2, // #1 = $ws
+/* 18724*/ OPC_RecordChild3, // #2 = $wt
+/* 18725*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18727*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPADD_S_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3139:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18736*/ /*Scope*/ 17, /*->18754*/
+/* 18737*/ OPC_CheckChild0Integer, 68|128,24/*3140*/,
+/* 18740*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18741*/ OPC_RecordChild2, // #1 = $ws
+/* 18742*/ OPC_RecordChild3, // #2 = $wt
+/* 18743*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18745*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPADD_S_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3140:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18754*/ /*Scope*/ 17, /*->18772*/
+/* 18755*/ OPC_CheckChild0Integer, 66|128,24/*3138*/,
+/* 18758*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18759*/ OPC_RecordChild2, // #1 = $ws
+/* 18760*/ OPC_RecordChild3, // #2 = $wt
+/* 18761*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18763*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPADD_S_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3138:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18772*/ /*Scope*/ 17, /*->18790*/
+/* 18773*/ OPC_CheckChild0Integer, 70|128,24/*3142*/,
+/* 18776*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18777*/ OPC_RecordChild2, // #1 = $ws
+/* 18778*/ OPC_RecordChild3, // #2 = $wt
+/* 18779*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18781*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPADD_U_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3142:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18790*/ /*Scope*/ 17, /*->18808*/
+/* 18791*/ OPC_CheckChild0Integer, 71|128,24/*3143*/,
+/* 18794*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18795*/ OPC_RecordChild2, // #1 = $ws
+/* 18796*/ OPC_RecordChild3, // #2 = $wt
+/* 18797*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18799*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPADD_U_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3143:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18808*/ /*Scope*/ 17, /*->18826*/
+/* 18809*/ OPC_CheckChild0Integer, 69|128,24/*3141*/,
+/* 18812*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18813*/ OPC_RecordChild2, // #1 = $ws
+/* 18814*/ OPC_RecordChild3, // #2 = $wt
+/* 18815*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18817*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPADD_U_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3141:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18826*/ /*Scope*/ 17, /*->18844*/
+/* 18827*/ OPC_CheckChild0Integer, 87|128,24/*3159*/,
+/* 18830*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18831*/ OPC_RecordChild2, // #1 = $ws
+/* 18832*/ OPC_RecordChild3, // #2 = $wt
+/* 18833*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18835*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSUB_S_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3159:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18844*/ /*Scope*/ 17, /*->18862*/
+/* 18845*/ OPC_CheckChild0Integer, 88|128,24/*3160*/,
+/* 18848*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18849*/ OPC_RecordChild2, // #1 = $ws
+/* 18850*/ OPC_RecordChild3, // #2 = $wt
+/* 18851*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18853*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSUB_S_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3160:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18862*/ /*Scope*/ 17, /*->18880*/
+/* 18863*/ OPC_CheckChild0Integer, 86|128,24/*3158*/,
+/* 18866*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18867*/ OPC_RecordChild2, // #1 = $ws
+/* 18868*/ OPC_RecordChild3, // #2 = $wt
+/* 18869*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18871*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSUB_S_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3158:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18880*/ /*Scope*/ 17, /*->18898*/
+/* 18881*/ OPC_CheckChild0Integer, 90|128,24/*3162*/,
+/* 18884*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18885*/ OPC_RecordChild2, // #1 = $ws
+/* 18886*/ OPC_RecordChild3, // #2 = $wt
+/* 18887*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18889*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSUB_U_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3162:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 18898*/ /*Scope*/ 17, /*->18916*/
+/* 18899*/ OPC_CheckChild0Integer, 91|128,24/*3163*/,
+/* 18902*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18903*/ OPC_RecordChild2, // #1 = $ws
+/* 18904*/ OPC_RecordChild3, // #2 = $wt
+/* 18905*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18907*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSUB_U_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3163:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 18916*/ /*Scope*/ 17, /*->18934*/
+/* 18917*/ OPC_CheckChild0Integer, 89|128,24/*3161*/,
+/* 18920*/ OPC_RecordChild1, // #0 = $wd_in
+/* 18921*/ OPC_RecordChild2, // #1 = $ws
+/* 18922*/ OPC_RecordChild3, // #2 = $wt
+/* 18923*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18925*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSUB_U_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3161:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 18934*/ /*Scope*/ 15, /*->18950*/
+/* 18935*/ OPC_CheckChild0Integer, 102|128,24/*3174*/,
+/* 18938*/ OPC_RecordChild1, // #0 = $ws
+/* 18939*/ OPC_RecordChild2, // #1 = $wt
+/* 18940*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18942*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCAF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3174:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 18950*/ /*Scope*/ 15, /*->18966*/
+/* 18951*/ OPC_CheckChild0Integer, 101|128,24/*3173*/,
+/* 18954*/ OPC_RecordChild1, // #0 = $ws
+/* 18955*/ OPC_RecordChild2, // #1 = $wt
+/* 18956*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18958*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCAF_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3173:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 18966*/ /*Scope*/ 13, /*->18980*/
+/* 18967*/ OPC_CheckChild0Integer, 106|128,24/*3178*/,
+/* 18970*/ OPC_RecordChild1, // #0 = $ws
+/* 18971*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18973*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCLASS_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3178:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 8
+ // Dst: (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 18980*/ /*Scope*/ 13, /*->18994*/
+/* 18981*/ OPC_CheckChild0Integer, 105|128,24/*3177*/,
+/* 18984*/ OPC_RecordChild1, // #0 = $ws
+/* 18985*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 18987*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCLASS_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3177:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 8
+ // Dst: (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 18994*/ /*Scope*/ 15, /*->19010*/
+/* 18995*/ OPC_CheckChild0Integer, 42|128,25/*3242*/,
+/* 18998*/ OPC_RecordChild1, // #0 = $ws
+/* 18999*/ OPC_RecordChild2, // #1 = $wt
+/* 19000*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19002*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSAF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3242:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19010*/ /*Scope*/ 15, /*->19026*/
+/* 19011*/ OPC_CheckChild0Integer, 41|128,25/*3241*/,
+/* 19014*/ OPC_RecordChild1, // #0 = $ws
+/* 19015*/ OPC_RecordChild2, // #1 = $wt
+/* 19016*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19018*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSAF_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3241:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19026*/ /*Scope*/ 15, /*->19042*/
+/* 19027*/ OPC_CheckChild0Integer, 44|128,25/*3244*/,
+/* 19030*/ OPC_RecordChild1, // #0 = $ws
+/* 19031*/ OPC_RecordChild2, // #1 = $wt
+/* 19032*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19034*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSEQ_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3244:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19042*/ /*Scope*/ 15, /*->19058*/
+/* 19043*/ OPC_CheckChild0Integer, 43|128,25/*3243*/,
+/* 19046*/ OPC_RecordChild1, // #0 = $ws
+/* 19047*/ OPC_RecordChild2, // #1 = $wt
+/* 19048*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19050*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSEQ_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3243:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19058*/ /*Scope*/ 15, /*->19074*/
+/* 19059*/ OPC_CheckChild0Integer, 46|128,25/*3246*/,
+/* 19062*/ OPC_RecordChild1, // #0 = $ws
+/* 19063*/ OPC_RecordChild2, // #1 = $wt
+/* 19064*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19066*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSLE_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3246:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19074*/ /*Scope*/ 15, /*->19090*/
+/* 19075*/ OPC_CheckChild0Integer, 45|128,25/*3245*/,
+/* 19078*/ OPC_RecordChild1, // #0 = $ws
+/* 19079*/ OPC_RecordChild2, // #1 = $wt
+/* 19080*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19082*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSLE_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3245:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19090*/ /*Scope*/ 15, /*->19106*/
+/* 19091*/ OPC_CheckChild0Integer, 48|128,25/*3248*/,
+/* 19094*/ OPC_RecordChild1, // #0 = $ws
+/* 19095*/ OPC_RecordChild2, // #1 = $wt
+/* 19096*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19098*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSLT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3248:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19106*/ /*Scope*/ 15, /*->19122*/
+/* 19107*/ OPC_CheckChild0Integer, 47|128,25/*3247*/,
+/* 19110*/ OPC_RecordChild1, // #0 = $ws
+/* 19111*/ OPC_RecordChild2, // #1 = $wt
+/* 19112*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19114*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSLT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3247:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19122*/ /*Scope*/ 15, /*->19138*/
+/* 19123*/ OPC_CheckChild0Integer, 50|128,25/*3250*/,
+/* 19126*/ OPC_RecordChild1, // #0 = $ws
+/* 19127*/ OPC_RecordChild2, // #1 = $wt
+/* 19128*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19130*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSNE_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3250:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19138*/ /*Scope*/ 15, /*->19154*/
+/* 19139*/ OPC_CheckChild0Integer, 49|128,25/*3249*/,
+/* 19142*/ OPC_RecordChild1, // #0 = $ws
+/* 19143*/ OPC_RecordChild2, // #1 = $wt
+/* 19144*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19146*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSNE_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3249:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19154*/ /*Scope*/ 15, /*->19170*/
+/* 19155*/ OPC_CheckChild0Integer, 52|128,25/*3252*/,
+/* 19158*/ OPC_RecordChild1, // #0 = $ws
+/* 19159*/ OPC_RecordChild2, // #1 = $wt
+/* 19160*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19162*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSOR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3252:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19170*/ /*Scope*/ 15, /*->19186*/
+/* 19171*/ OPC_CheckChild0Integer, 51|128,25/*3251*/,
+/* 19174*/ OPC_RecordChild1, // #0 = $ws
+/* 19175*/ OPC_RecordChild2, // #1 = $wt
+/* 19176*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19178*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSOR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3251:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19186*/ /*Scope*/ 15, /*->19202*/
+/* 19187*/ OPC_CheckChild0Integer, 58|128,25/*3258*/,
+/* 19190*/ OPC_RecordChild1, // #0 = $ws
+/* 19191*/ OPC_RecordChild2, // #1 = $wt
+/* 19192*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19194*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUEQ_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3258:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19202*/ /*Scope*/ 15, /*->19218*/
+/* 19203*/ OPC_CheckChild0Integer, 57|128,25/*3257*/,
+/* 19206*/ OPC_RecordChild1, // #0 = $ws
+/* 19207*/ OPC_RecordChild2, // #1 = $wt
+/* 19208*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19210*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUEQ_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3257:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19218*/ /*Scope*/ 15, /*->19234*/
+/* 19219*/ OPC_CheckChild0Integer, 60|128,25/*3260*/,
+/* 19222*/ OPC_RecordChild1, // #0 = $ws
+/* 19223*/ OPC_RecordChild2, // #1 = $wt
+/* 19224*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19226*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSULE_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3260:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19234*/ /*Scope*/ 15, /*->19250*/
+/* 19235*/ OPC_CheckChild0Integer, 59|128,25/*3259*/,
+/* 19238*/ OPC_RecordChild1, // #0 = $ws
+/* 19239*/ OPC_RecordChild2, // #1 = $wt
+/* 19240*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19242*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSULE_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3259:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19250*/ /*Scope*/ 15, /*->19266*/
+/* 19251*/ OPC_CheckChild0Integer, 62|128,25/*3262*/,
+/* 19254*/ OPC_RecordChild1, // #0 = $ws
+/* 19255*/ OPC_RecordChild2, // #1 = $wt
+/* 19256*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19258*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSULT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3262:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19266*/ /*Scope*/ 15, /*->19282*/
+/* 19267*/ OPC_CheckChild0Integer, 61|128,25/*3261*/,
+/* 19270*/ OPC_RecordChild1, // #0 = $ws
+/* 19271*/ OPC_RecordChild2, // #1 = $wt
+/* 19272*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19274*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSULT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3261:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19282*/ /*Scope*/ 15, /*->19298*/
+/* 19283*/ OPC_CheckChild0Integer, 64|128,25/*3264*/,
+/* 19286*/ OPC_RecordChild1, // #0 = $ws
+/* 19287*/ OPC_RecordChild2, // #1 = $wt
+/* 19288*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19290*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUN_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3264:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19298*/ /*Scope*/ 15, /*->19314*/
+/* 19299*/ OPC_CheckChild0Integer, 63|128,25/*3263*/,
+/* 19302*/ OPC_RecordChild1, // #0 = $ws
+/* 19303*/ OPC_RecordChild2, // #1 = $wt
+/* 19304*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19306*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUN_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3263:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19314*/ /*Scope*/ 15, /*->19330*/
+/* 19315*/ OPC_CheckChild0Integer, 66|128,25/*3266*/,
+/* 19318*/ OPC_RecordChild1, // #0 = $ws
+/* 19319*/ OPC_RecordChild2, // #1 = $wt
+/* 19320*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19322*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUNE_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3266:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19330*/ /*Scope*/ 15, /*->19346*/
+/* 19331*/ OPC_CheckChild0Integer, 65|128,25/*3265*/,
+/* 19334*/ OPC_RecordChild1, // #0 = $ws
+/* 19335*/ OPC_RecordChild2, // #1 = $wt
+/* 19336*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19338*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUNE_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3265:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19346*/ /*Scope*/ 13, /*->19360*/
+/* 19347*/ OPC_CheckChild0Integer, 68|128,25/*3268*/,
+/* 19350*/ OPC_RecordChild1, // #0 = $ws
+/* 19351*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19353*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTINT_S_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3268:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 8
+ // Dst: (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 19360*/ /*Scope*/ 13, /*->19374*/
+/* 19361*/ OPC_CheckChild0Integer, 67|128,25/*3267*/,
+/* 19364*/ OPC_RecordChild1, // #0 = $ws
+/* 19365*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19367*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTINT_S_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3267:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 8
+ // Dst: (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 19374*/ /*Scope*/ 13, /*->19388*/
+/* 19375*/ OPC_CheckChild0Integer, 70|128,25/*3270*/,
+/* 19378*/ OPC_RecordChild1, // #0 = $ws
+/* 19379*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19381*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTINT_U_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3270:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 8
+ // Dst: (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 19388*/ /*Scope*/ 13, /*->19402*/
+/* 19389*/ OPC_CheckChild0Integer, 69|128,25/*3269*/,
+/* 19392*/ OPC_RecordChild1, // #0 = $ws
+/* 19393*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19395*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTINT_U_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3269:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 8
+ // Dst: (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 19402*/ /*Scope*/ 15, /*->19418*/
+/* 19403*/ OPC_CheckChild0Integer, 71|128,25/*3271*/,
+/* 19406*/ OPC_RecordChild1, // #0 = $ws
+/* 19407*/ OPC_RecordChild2, // #1 = $wt
+/* 19408*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19410*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTQ_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3271:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 19418*/ /*Scope*/ 15, /*->19434*/
+/* 19419*/ OPC_CheckChild0Integer, 72|128,25/*3272*/,
+/* 19422*/ OPC_RecordChild1, // #0 = $ws
+/* 19423*/ OPC_RecordChild2, // #1 = $wt
+/* 19424*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19426*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTQ_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3272:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 19434*/ /*Scope*/ 15, /*->19450*/
+/* 19435*/ OPC_CheckChild0Integer, 78|128,25/*3278*/,
+/* 19438*/ OPC_RecordChild1, // #0 = $ws
+/* 19439*/ OPC_RecordChild2, // #1 = $wt
+/* 19440*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19442*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HADD_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3278:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 19450*/ /*Scope*/ 15, /*->19466*/
+/* 19451*/ OPC_CheckChild0Integer, 79|128,25/*3279*/,
+/* 19454*/ OPC_RecordChild1, // #0 = $ws
+/* 19455*/ OPC_RecordChild2, // #1 = $wt
+/* 19456*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19458*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HADD_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3279:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19466*/ /*Scope*/ 15, /*->19482*/
+/* 19467*/ OPC_CheckChild0Integer, 77|128,25/*3277*/,
+/* 19470*/ OPC_RecordChild1, // #0 = $ws
+/* 19471*/ OPC_RecordChild2, // #1 = $wt
+/* 19472*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19474*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HADD_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3277:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19482*/ /*Scope*/ 15, /*->19498*/
+/* 19483*/ OPC_CheckChild0Integer, 81|128,25/*3281*/,
+/* 19486*/ OPC_RecordChild1, // #0 = $ws
+/* 19487*/ OPC_RecordChild2, // #1 = $wt
+/* 19488*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19490*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HADD_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3281:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 19498*/ /*Scope*/ 15, /*->19514*/
+/* 19499*/ OPC_CheckChild0Integer, 82|128,25/*3282*/,
+/* 19502*/ OPC_RecordChild1, // #0 = $ws
+/* 19503*/ OPC_RecordChild2, // #1 = $wt
+/* 19504*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19506*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HADD_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3282:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19514*/ /*Scope*/ 15, /*->19530*/
+/* 19515*/ OPC_CheckChild0Integer, 80|128,25/*3280*/,
+/* 19518*/ OPC_RecordChild1, // #0 = $ws
+/* 19519*/ OPC_RecordChild2, // #1 = $wt
+/* 19520*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19522*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HADD_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19530*/ /*Scope*/ 15, /*->19546*/
+/* 19531*/ OPC_CheckChild0Integer, 84|128,25/*3284*/,
+/* 19534*/ OPC_RecordChild1, // #0 = $ws
+/* 19535*/ OPC_RecordChild2, // #1 = $wt
+/* 19536*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19538*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HSUB_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3284:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 19546*/ /*Scope*/ 15, /*->19562*/
+/* 19547*/ OPC_CheckChild0Integer, 85|128,25/*3285*/,
+/* 19550*/ OPC_RecordChild1, // #0 = $ws
+/* 19551*/ OPC_RecordChild2, // #1 = $wt
+/* 19552*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19554*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HSUB_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3285:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19562*/ /*Scope*/ 15, /*->19578*/
+/* 19563*/ OPC_CheckChild0Integer, 83|128,25/*3283*/,
+/* 19566*/ OPC_RecordChild1, // #0 = $ws
+/* 19567*/ OPC_RecordChild2, // #1 = $wt
+/* 19568*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19570*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HSUB_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3283:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19578*/ /*Scope*/ 15, /*->19594*/
+/* 19579*/ OPC_CheckChild0Integer, 87|128,25/*3287*/,
+/* 19582*/ OPC_RecordChild1, // #0 = $ws
+/* 19583*/ OPC_RecordChild2, // #1 = $wt
+/* 19584*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19586*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HSUB_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3287:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 19594*/ /*Scope*/ 15, /*->19610*/
+/* 19595*/ OPC_CheckChild0Integer, 88|128,25/*3288*/,
+/* 19598*/ OPC_RecordChild1, // #0 = $ws
+/* 19599*/ OPC_RecordChild2, // #1 = $wt
+/* 19600*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19602*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HSUB_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3288:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19610*/ /*Scope*/ 15, /*->19626*/
+/* 19611*/ OPC_CheckChild0Integer, 86|128,25/*3286*/,
+/* 19614*/ OPC_RecordChild1, // #0 = $ws
+/* 19615*/ OPC_RecordChild2, // #1 = $wt
+/* 19616*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19618*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::HSUB_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3286:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19626*/ /*Scope*/ 17, /*->19644*/
+/* 19627*/ OPC_CheckChild0Integer, 127|128,25/*3327*/,
+/* 19630*/ OPC_RecordChild1, // #0 = $wd_in
+/* 19631*/ OPC_RecordChild2, // #1 = $ws
+/* 19632*/ OPC_RecordChild3, // #2 = $wt
+/* 19633*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19635*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_Q_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3327:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19644*/ /*Scope*/ 17, /*->19662*/
+/* 19645*/ OPC_CheckChild0Integer, 0|128,26/*3328*/,
+/* 19648*/ OPC_RecordChild1, // #0 = $wd_in
+/* 19649*/ OPC_RecordChild2, // #1 = $ws
+/* 19650*/ OPC_RecordChild3, // #2 = $wt
+/* 19651*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19653*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_Q_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19662*/ /*Scope*/ 17, /*->19680*/
+/* 19663*/ OPC_CheckChild0Integer, 1|128,26/*3329*/,
+/* 19666*/ OPC_RecordChild1, // #0 = $wd_in
+/* 19667*/ OPC_RecordChild2, // #1 = $ws
+/* 19668*/ OPC_RecordChild3, // #2 = $wt
+/* 19669*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19671*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDR_Q_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3329:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19680*/ /*Scope*/ 17, /*->19698*/
+/* 19681*/ OPC_CheckChild0Integer, 2|128,26/*3330*/,
+/* 19684*/ OPC_RecordChild1, // #0 = $wd_in
+/* 19685*/ OPC_RecordChild2, // #1 = $ws
+/* 19686*/ OPC_RecordChild3, // #2 = $wt
+/* 19687*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19689*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDR_Q_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3330:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19698*/ /*Scope*/ 15, /*->19714*/
+/* 19699*/ OPC_CheckChild0Integer, 12|128,26/*3340*/,
+/* 19702*/ OPC_RecordChild1, // #0 = $ws
+/* 19703*/ OPC_RecordChild2, // #1 = $wt
+/* 19704*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19706*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_A_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3340:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 19714*/ /*Scope*/ 15, /*->19730*/
+/* 19715*/ OPC_CheckChild0Integer, 14|128,26/*3342*/,
+/* 19718*/ OPC_RecordChild1, // #0 = $ws
+/* 19719*/ OPC_RecordChild2, // #1 = $wt
+/* 19720*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19722*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_A_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3342:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19730*/ /*Scope*/ 15, /*->19746*/
+/* 19731*/ OPC_CheckChild0Integer, 15|128,26/*3343*/,
+/* 19734*/ OPC_RecordChild1, // #0 = $ws
+/* 19735*/ OPC_RecordChild2, // #1 = $wt
+/* 19736*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19738*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_A_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3343:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19746*/ /*Scope*/ 15, /*->19762*/
+/* 19747*/ OPC_CheckChild0Integer, 13|128,26/*3341*/,
+/* 19750*/ OPC_RecordChild1, // #0 = $ws
+/* 19751*/ OPC_RecordChild2, // #1 = $wt
+/* 19752*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19754*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_A_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3341:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 19762*/ /*Scope*/ 15, /*->19778*/
+/* 19763*/ OPC_CheckChild0Integer, 32|128,26/*3360*/,
+/* 19766*/ OPC_RecordChild1, // #0 = $ws
+/* 19767*/ OPC_RecordChild2, // #1 = $wt
+/* 19768*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19770*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_A_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3360:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 19778*/ /*Scope*/ 15, /*->19794*/
+/* 19779*/ OPC_CheckChild0Integer, 34|128,26/*3362*/,
+/* 19782*/ OPC_RecordChild1, // #0 = $ws
+/* 19783*/ OPC_RecordChild2, // #1 = $wt
+/* 19784*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19786*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_A_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3362:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19794*/ /*Scope*/ 15, /*->19810*/
+/* 19795*/ OPC_CheckChild0Integer, 35|128,26/*3363*/,
+/* 19798*/ OPC_RecordChild1, // #0 = $ws
+/* 19799*/ OPC_RecordChild2, // #1 = $wt
+/* 19800*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19802*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_A_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3363:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19810*/ /*Scope*/ 15, /*->19826*/
+/* 19811*/ OPC_CheckChild0Integer, 33|128,26/*3361*/,
+/* 19814*/ OPC_RecordChild1, // #0 = $ws
+/* 19815*/ OPC_RecordChild2, // #1 = $wt
+/* 19816*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19818*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_A_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3361:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 19826*/ /*Scope*/ 17, /*->19844*/
+/* 19827*/ OPC_CheckChild0Integer, 63|128,26/*3391*/,
+/* 19830*/ OPC_RecordChild1, // #0 = $wd_in
+/* 19831*/ OPC_RecordChild2, // #1 = $ws
+/* 19832*/ OPC_RecordChild3, // #2 = $wt
+/* 19833*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19835*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUB_Q_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3391:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19844*/ /*Scope*/ 17, /*->19862*/
+/* 19845*/ OPC_CheckChild0Integer, 64|128,26/*3392*/,
+/* 19848*/ OPC_RecordChild1, // #0 = $wd_in
+/* 19849*/ OPC_RecordChild2, // #1 = $ws
+/* 19850*/ OPC_RecordChild3, // #2 = $wt
+/* 19851*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19853*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUB_Q_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3392:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19862*/ /*Scope*/ 17, /*->19880*/
+/* 19863*/ OPC_CheckChild0Integer, 65|128,26/*3393*/,
+/* 19866*/ OPC_RecordChild1, // #0 = $wd_in
+/* 19867*/ OPC_RecordChild2, // #1 = $ws
+/* 19868*/ OPC_RecordChild3, // #2 = $wt
+/* 19869*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19871*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUBR_Q_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3393:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19880*/ /*Scope*/ 17, /*->19898*/
+/* 19881*/ OPC_CheckChild0Integer, 66|128,26/*3394*/,
+/* 19884*/ OPC_RecordChild1, // #0 = $wd_in
+/* 19885*/ OPC_RecordChild2, // #1 = $ws
+/* 19886*/ OPC_RecordChild3, // #2 = $wt
+/* 19887*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19889*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUBR_Q_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3394:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19898*/ /*Scope*/ 15, /*->19914*/
+/* 19899*/ OPC_CheckChild0Integer, 74|128,26/*3402*/,
+/* 19902*/ OPC_RecordChild1, // #0 = $ws
+/* 19903*/ OPC_RecordChild2, // #1 = $wt
+/* 19904*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19906*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUL_Q_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3402:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19914*/ /*Scope*/ 15, /*->19930*/
+/* 19915*/ OPC_CheckChild0Integer, 75|128,26/*3403*/,
+/* 19918*/ OPC_RecordChild1, // #0 = $ws
+/* 19919*/ OPC_RecordChild2, // #1 = $wt
+/* 19920*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19922*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUL_Q_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3403:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19930*/ /*Scope*/ 15, /*->19946*/
+/* 19931*/ OPC_CheckChild0Integer, 85|128,26/*3413*/,
+/* 19934*/ OPC_RecordChild1, // #0 = $ws
+/* 19935*/ OPC_RecordChild2, // #1 = $wt
+/* 19936*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19938*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULR_Q_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3413:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 19946*/ /*Scope*/ 15, /*->19962*/
+/* 19947*/ OPC_CheckChild0Integer, 86|128,26/*3414*/,
+/* 19950*/ OPC_RecordChild1, // #0 = $ws
+/* 19951*/ OPC_RecordChild2, // #1 = $wt
+/* 19952*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19954*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULR_Q_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3414:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 19962*/ /*Scope*/ 13, /*->19976*/
+/* 19963*/ OPC_CheckChild0Integer, 95|128,26/*3423*/,
+/* 19966*/ OPC_RecordChild1, // #0 = $ws
+/* 19967*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19969*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NLOC_B), 0,
+ MVT::v16i8, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3423:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 8
+ // Dst: (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
+/* 19976*/ /*Scope*/ 13, /*->19990*/
+/* 19977*/ OPC_CheckChild0Integer, 97|128,26/*3425*/,
+/* 19980*/ OPC_RecordChild1, // #0 = $ws
+/* 19981*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19983*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NLOC_H), 0,
+ MVT::v8i16, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3425:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 8
+ // Dst: (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
+/* 19990*/ /*Scope*/ 13, /*->20004*/
+/* 19991*/ OPC_CheckChild0Integer, 98|128,26/*3426*/,
+/* 19994*/ OPC_RecordChild1, // #0 = $ws
+/* 19995*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 19997*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NLOC_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3426:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 8
+ // Dst: (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+/* 20004*/ /*Scope*/ 13, /*->20018*/
+/* 20005*/ OPC_CheckChild0Integer, 96|128,26/*3424*/,
+/* 20008*/ OPC_RecordChild1, // #0 = $ws
+/* 20009*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20011*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NLOC_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3424:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 8
+ // Dst: (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
+/* 20018*/ /*Scope*/ 17, /*->20036*/
+/* 20019*/ OPC_CheckChild0Integer, 39|128,27/*3495*/,
+/* 20022*/ OPC_RecordChild1, // #0 = $wd_in
+/* 20023*/ OPC_RecordChild2, // #1 = $ws
+/* 20024*/ OPC_RecordChild3, // #2 = $rt
+/* 20025*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20027*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLD_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3495:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 20036*/ /*Scope*/ 17, /*->20054*/
+/* 20037*/ OPC_CheckChild0Integer, 41|128,27/*3497*/,
+/* 20040*/ OPC_RecordChild1, // #0 = $wd_in
+/* 20041*/ OPC_RecordChild2, // #1 = $ws
+/* 20042*/ OPC_RecordChild3, // #2 = $rt
+/* 20043*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20045*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLD_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3497:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 20054*/ /*Scope*/ 17, /*->20072*/
+/* 20055*/ OPC_CheckChild0Integer, 42|128,27/*3498*/,
+/* 20058*/ OPC_RecordChild1, // #0 = $wd_in
+/* 20059*/ OPC_RecordChild2, // #1 = $ws
+/* 20060*/ OPC_RecordChild3, // #2 = $rt
+/* 20061*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20063*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLD_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3498:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 20072*/ /*Scope*/ 17, /*->20090*/
+/* 20073*/ OPC_CheckChild0Integer, 40|128,27/*3496*/,
+/* 20076*/ OPC_RecordChild1, // #0 = $wd_in
+/* 20077*/ OPC_RecordChild2, // #1 = $ws
+/* 20078*/ OPC_RecordChild3, // #2 = $rt
+/* 20079*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20081*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLD_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3496:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 8
+ // Dst: (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 20090*/ /*Scope*/ 15, /*->20106*/
+/* 20091*/ OPC_CheckChild0Integer, 71|128,27/*3527*/,
+/* 20094*/ OPC_RecordChild1, // #0 = $ws
+/* 20095*/ OPC_RecordChild2, // #1 = $wt
+/* 20096*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20098*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3527:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 20106*/ /*Scope*/ 15, /*->20122*/
+/* 20107*/ OPC_CheckChild0Integer, 73|128,27/*3529*/,
+/* 20110*/ OPC_RecordChild1, // #0 = $ws
+/* 20111*/ OPC_RecordChild2, // #1 = $wt
+/* 20112*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20114*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3529:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 20122*/ /*Scope*/ 15, /*->20138*/
+/* 20123*/ OPC_CheckChild0Integer, 74|128,27/*3530*/,
+/* 20126*/ OPC_RecordChild1, // #0 = $ws
+/* 20127*/ OPC_RecordChild2, // #1 = $wt
+/* 20128*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20130*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3530:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 20138*/ /*Scope*/ 15, /*->20154*/
+/* 20139*/ OPC_CheckChild0Integer, 72|128,27/*3528*/,
+/* 20142*/ OPC_RecordChild1, // #0 = $ws
+/* 20143*/ OPC_RecordChild2, // #1 = $wt
+/* 20144*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20146*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3528:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 20154*/ /*Scope*/ 15, /*->20170*/
+/* 20155*/ OPC_CheckChild0Integer, 87|128,27/*3543*/,
+/* 20158*/ OPC_RecordChild1, // #0 = $ws
+/* 20159*/ OPC_RecordChild2, // #1 = $wt
+/* 20160*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20162*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3543:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 20170*/ /*Scope*/ 15, /*->20186*/
+/* 20171*/ OPC_CheckChild0Integer, 89|128,27/*3545*/,
+/* 20174*/ OPC_RecordChild1, // #0 = $ws
+/* 20175*/ OPC_RecordChild2, // #1 = $wt
+/* 20176*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20178*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3545:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 20186*/ /*Scope*/ 15, /*->20202*/
+/* 20187*/ OPC_CheckChild0Integer, 90|128,27/*3546*/,
+/* 20190*/ OPC_RecordChild1, // #0 = $ws
+/* 20191*/ OPC_RecordChild2, // #1 = $wt
+/* 20192*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20194*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3546:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 20202*/ /*Scope*/ 15, /*->20218*/
+/* 20203*/ OPC_CheckChild0Integer, 88|128,27/*3544*/,
+/* 20206*/ OPC_RecordChild1, // #0 = $ws
+/* 20207*/ OPC_RecordChild2, // #1 = $wt
+/* 20208*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20210*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3544:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 20218*/ /*Scope*/ 15, /*->20234*/
+/* 20219*/ OPC_CheckChild0Integer, 106|128,27/*3562*/,
+/* 20222*/ OPC_RecordChild1, // #0 = $ws
+/* 20223*/ OPC_RecordChild2, // #1 = $wt
+/* 20224*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20226*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBS_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3562:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 20234*/ /*Scope*/ 15, /*->20250*/
+/* 20235*/ OPC_CheckChild0Integer, 108|128,27/*3564*/,
+/* 20238*/ OPC_RecordChild1, // #0 = $ws
+/* 20239*/ OPC_RecordChild2, // #1 = $wt
+/* 20240*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20242*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBS_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3564:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 20250*/ /*Scope*/ 15, /*->20266*/
+/* 20251*/ OPC_CheckChild0Integer, 109|128,27/*3565*/,
+/* 20254*/ OPC_RecordChild1, // #0 = $ws
+/* 20255*/ OPC_RecordChild2, // #1 = $wt
+/* 20256*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20258*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBS_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3565:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 20266*/ /*Scope*/ 15, /*->20282*/
+/* 20267*/ OPC_CheckChild0Integer, 107|128,27/*3563*/,
+/* 20270*/ OPC_RecordChild1, // #0 = $ws
+/* 20271*/ OPC_RecordChild2, // #1 = $wt
+/* 20272*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20274*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBS_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3563:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 20282*/ /*Scope*/ 15, /*->20298*/
+/* 20283*/ OPC_CheckChild0Integer, 110|128,27/*3566*/,
+/* 20286*/ OPC_RecordChild1, // #0 = $ws
+/* 20287*/ OPC_RecordChild2, // #1 = $wt
+/* 20288*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20290*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBS_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3566:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 20298*/ /*Scope*/ 15, /*->20314*/
+/* 20299*/ OPC_CheckChild0Integer, 112|128,27/*3568*/,
+/* 20302*/ OPC_RecordChild1, // #0 = $ws
+/* 20303*/ OPC_RecordChild2, // #1 = $wt
+/* 20304*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20306*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBS_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3568:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 20314*/ /*Scope*/ 15, /*->20330*/
+/* 20315*/ OPC_CheckChild0Integer, 113|128,27/*3569*/,
+/* 20318*/ OPC_RecordChild1, // #0 = $ws
+/* 20319*/ OPC_RecordChild2, // #1 = $wt
+/* 20320*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20322*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBS_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3569:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 20330*/ /*Scope*/ 15, /*->20346*/
+/* 20331*/ OPC_CheckChild0Integer, 111|128,27/*3567*/,
+/* 20334*/ OPC_RecordChild1, // #0 = $ws
+/* 20335*/ OPC_RecordChild2, // #1 = $wt
+/* 20336*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20338*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBS_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3567:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 20346*/ /*Scope*/ 15, /*->20362*/
+/* 20347*/ OPC_CheckChild0Integer, 114|128,27/*3570*/,
+/* 20350*/ OPC_RecordChild1, // #0 = $ws
+/* 20351*/ OPC_RecordChild2, // #1 = $wt
+/* 20352*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20354*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBSUS_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3570:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 20362*/ /*Scope*/ 15, /*->20378*/
+/* 20363*/ OPC_CheckChild0Integer, 116|128,27/*3572*/,
+/* 20366*/ OPC_RecordChild1, // #0 = $ws
+/* 20367*/ OPC_RecordChild2, // #1 = $wt
+/* 20368*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20370*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBSUS_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3572:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 20378*/ /*Scope*/ 15, /*->20394*/
+/* 20379*/ OPC_CheckChild0Integer, 117|128,27/*3573*/,
+/* 20382*/ OPC_RecordChild1, // #0 = $ws
+/* 20383*/ OPC_RecordChild2, // #1 = $wt
+/* 20384*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20386*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBSUS_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3573:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 20394*/ /*Scope*/ 15, /*->20410*/
+/* 20395*/ OPC_CheckChild0Integer, 115|128,27/*3571*/,
+/* 20398*/ OPC_RecordChild1, // #0 = $ws
+/* 20399*/ OPC_RecordChild2, // #1 = $wt
+/* 20400*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20402*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBSUS_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3571:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 20410*/ /*Scope*/ 15, /*->20426*/
+/* 20411*/ OPC_CheckChild0Integer, 118|128,27/*3574*/,
+/* 20414*/ OPC_RecordChild1, // #0 = $ws
+/* 20415*/ OPC_RecordChild2, // #1 = $wt
+/* 20416*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20418*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBSUU_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v16i8] } 3574:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 8
+ // Dst: (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 20426*/ /*Scope*/ 15, /*->20442*/
+/* 20427*/ OPC_CheckChild0Integer, 120|128,27/*3576*/,
+/* 20430*/ OPC_RecordChild1, // #0 = $ws
+/* 20431*/ OPC_RecordChild2, // #1 = $wt
+/* 20432*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20434*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBSUU_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8i16] } 3576:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 8
+ // Dst: (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 20442*/ /*Scope*/ 15, /*->20458*/
+/* 20443*/ OPC_CheckChild0Integer, 121|128,27/*3577*/,
+/* 20446*/ OPC_RecordChild1, // #0 = $ws
+/* 20447*/ OPC_RecordChild2, // #1 = $wt
+/* 20448*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20450*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBSUU_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4i32] } 3577:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 8
+ // Dst: (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 20458*/ /*Scope*/ 15, /*->20474*/
+/* 20459*/ OPC_CheckChild0Integer, 119|128,27/*3575*/,
+/* 20462*/ OPC_RecordChild1, // #0 = $ws
+/* 20463*/ OPC_RecordChild2, // #1 = $wt
+/* 20464*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20466*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBSUU_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2i64] } 3575:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 8
+ // Dst: (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 20474*/ /*Scope*/ 15, /*->20490*/
+/* 20475*/ OPC_CheckChild0Integer, 127|128,24/*3199*/,
+/* 20478*/ OPC_RecordChild1, // #0 = $ws
+/* 20479*/ OPC_RecordChild2, // #1 = $wt
+/* 20480*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20482*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXDO_H), 0,
+ MVT::v8f16, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v8f16] } 3199:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 20490*/ /*Scope*/ 15, /*->20506*/
+/* 20491*/ OPC_CheckChild0Integer, 0|128,25/*3200*/,
+/* 20494*/ OPC_RecordChild1, // #0 = $ws
+/* 20495*/ OPC_RecordChild2, // #1 = $wt
+/* 20496*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20498*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXDO_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3200:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 20506*/ /*Scope*/ 13, /*->20520*/
+/* 20507*/ OPC_CheckChild0Integer, 4|128,25/*3204*/,
+/* 20510*/ OPC_RecordChild1, // #0 = $ws
+/* 20511*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20513*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXUPL_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3204:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) - Complexity = 8
+ // Dst: (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
+/* 20520*/ /*Scope*/ 13, /*->20534*/
+/* 20521*/ OPC_CheckChild0Integer, 3|128,25/*3203*/,
+/* 20524*/ OPC_RecordChild1, // #0 = $ws
+/* 20525*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20527*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXUPL_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3203:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 8
+ // Dst: (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 20534*/ /*Scope*/ 13, /*->20548*/
+/* 20535*/ OPC_CheckChild0Integer, 6|128,25/*3206*/,
+/* 20538*/ OPC_RecordChild1, // #0 = $ws
+/* 20539*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20541*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXUPR_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3206:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) - Complexity = 8
+ // Dst: (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
+/* 20548*/ /*Scope*/ 13, /*->20562*/
+/* 20549*/ OPC_CheckChild0Integer, 5|128,25/*3205*/,
+/* 20552*/ OPC_RecordChild1, // #0 = $ws
+/* 20553*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20555*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXUPR_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3205:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 8
+ // Dst: (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 20562*/ /*Scope*/ 13, /*->20576*/
+/* 20563*/ OPC_CheckChild0Integer, 12|128,25/*3212*/,
+/* 20566*/ OPC_RecordChild1, // #0 = $ws
+/* 20567*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20569*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FFQL_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3212:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 8
+ // Dst: (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
+/* 20576*/ /*Scope*/ 13, /*->20590*/
+/* 20577*/ OPC_CheckChild0Integer, 11|128,25/*3211*/,
+/* 20580*/ OPC_RecordChild1, // #0 = $ws
+/* 20581*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20583*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FFQL_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3211:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 8
+ // Dst: (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+/* 20590*/ /*Scope*/ 13, /*->20604*/
+/* 20591*/ OPC_CheckChild0Integer, 14|128,25/*3214*/,
+/* 20594*/ OPC_RecordChild1, // #0 = $ws
+/* 20595*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20597*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FFQR_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3214:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 8
+ // Dst: (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
+/* 20604*/ /*Scope*/ 13, /*->20618*/
+/* 20605*/ OPC_CheckChild0Integer, 13|128,25/*3213*/,
+/* 20608*/ OPC_RecordChild1, // #0 = $ws
+/* 20609*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20611*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FFQR_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3213:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 8
+ // Dst: (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+/* 20618*/ /*Scope*/ 15, /*->20634*/
+/* 20619*/ OPC_CheckChild0Integer, 26|128,25/*3226*/,
+/* 20622*/ OPC_RecordChild1, // #0 = $ws
+/* 20623*/ OPC_RecordChild2, // #1 = $wt
+/* 20624*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20626*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMAX_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3226:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 20634*/ /*Scope*/ 15, /*->20650*/
+/* 20635*/ OPC_CheckChild0Integer, 25|128,25/*3225*/,
+/* 20638*/ OPC_RecordChild1, // #0 = $ws
+/* 20639*/ OPC_RecordChild2, // #1 = $wt
+/* 20640*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20642*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMAX_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3225:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 20650*/ /*Scope*/ 15, /*->20666*/
+/* 20651*/ OPC_CheckChild0Integer, 24|128,25/*3224*/,
+/* 20654*/ OPC_RecordChild1, // #0 = $ws
+/* 20655*/ OPC_RecordChild2, // #1 = $wt
+/* 20656*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20658*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMAX_A_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3224:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 20666*/ /*Scope*/ 15, /*->20682*/
+/* 20667*/ OPC_CheckChild0Integer, 23|128,25/*3223*/,
+/* 20670*/ OPC_RecordChild1, // #0 = $ws
+/* 20671*/ OPC_RecordChild2, // #1 = $wt
+/* 20672*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20674*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMAX_A_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3223:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 20682*/ /*Scope*/ 15, /*->20698*/
+/* 20683*/ OPC_CheckChild0Integer, 30|128,25/*3230*/,
+/* 20686*/ OPC_RecordChild1, // #0 = $ws
+/* 20687*/ OPC_RecordChild2, // #1 = $wt
+/* 20688*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20690*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMIN_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3230:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 20698*/ /*Scope*/ 15, /*->20714*/
+/* 20699*/ OPC_CheckChild0Integer, 29|128,25/*3229*/,
+/* 20702*/ OPC_RecordChild1, // #0 = $ws
+/* 20703*/ OPC_RecordChild2, // #1 = $wt
+/* 20704*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20706*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMIN_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3229:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 20714*/ /*Scope*/ 15, /*->20730*/
+/* 20715*/ OPC_CheckChild0Integer, 28|128,25/*3228*/,
+/* 20718*/ OPC_RecordChild1, // #0 = $ws
+/* 20719*/ OPC_RecordChild2, // #1 = $wt
+/* 20720*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20722*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMIN_A_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3228:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 8
+ // Dst: (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 20730*/ /*Scope*/ 15, /*->20746*/
+/* 20731*/ OPC_CheckChild0Integer, 27|128,25/*3227*/,
+/* 20734*/ OPC_RecordChild1, // #0 = $ws
+/* 20735*/ OPC_RecordChild2, // #1 = $wt
+/* 20736*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20738*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMIN_A_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3227:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 8
+ // Dst: (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 20746*/ /*Scope*/ 13, /*->20760*/
+/* 20747*/ OPC_CheckChild0Integer, 36|128,25/*3236*/,
+/* 20750*/ OPC_RecordChild1, // #0 = $ws
+/* 20751*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20753*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FRCP_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3236:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 8
+ // Dst: (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 20760*/ /*Scope*/ 13, /*->20774*/
+/* 20761*/ OPC_CheckChild0Integer, 35|128,25/*3235*/,
+/* 20764*/ OPC_RecordChild1, // #0 = $ws
+/* 20765*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20767*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FRCP_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3235:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 8
+ // Dst: (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 20774*/ /*Scope*/ 13, /*->20788*/
+/* 20775*/ OPC_CheckChild0Integer, 40|128,25/*3240*/,
+/* 20778*/ OPC_RecordChild1, // #0 = $ws
+/* 20779*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20781*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FRSQRT_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v4f32] } 3240:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 8
+ // Dst: (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 20788*/ /*Scope*/ 13, /*->20802*/
+/* 20789*/ OPC_CheckChild0Integer, 39|128,25/*3239*/,
+/* 20792*/ OPC_RecordChild1, // #0 = $ws
+/* 20793*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 20795*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FRSQRT_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (intrinsic_wo_chain:{ *:[v2f64] } 3239:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 8
+ // Dst: (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 20802*/ 0, /*End of Scope*/
+/* 20803*/ /*SwitchOpcode*/ 99|128,1/*227*/, TARGET_VAL(ISD::INTRINSIC_VOID),// ->21034
+/* 20807*/ OPC_RecordNode, // #0 = 'intrinsic_void' chained node
+/* 20808*/ OPC_Scope, 43, /*->20853*/ // 7 children in Scope
+/* 20810*/ OPC_CheckChild1Integer, 12|128,28/*3596*/,
+/* 20813*/ OPC_RecordChild2, // #1 = $rs
+/* 20814*/ OPC_RecordChild3, // #2 = $mask
+/* 20815*/ OPC_MoveChild3,
+/* 20816*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 20819*/ OPC_Scope, 15, /*->20836*/ // 2 children in Scope
+/* 20821*/ OPC_CheckPredicate, 29, // Predicate_immZExt10
+/* 20823*/ OPC_MoveParent,
+/* 20824*/ OPC_CheckPatternPredicate, 48, // (Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())
+/* 20826*/ OPC_EmitMergeInputChains1_0,
+/* 20827*/ OPC_EmitConvertToTarget, 2,
+/* 20829*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::WRDSP), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 3,
+ // Src: (intrinsic_void 3596:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt10>>:$mask) - Complexity = 12
+ // Dst: (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$mask)
+/* 20836*/ /*Scope*/ 15, /*->20852*/
+/* 20837*/ OPC_CheckPredicate, 30, // Predicate_immZExt7
+/* 20839*/ OPC_MoveParent,
+/* 20840*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 20842*/ OPC_EmitMergeInputChains1_0,
+/* 20843*/ OPC_EmitConvertToTarget, 2,
+/* 20845*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::WRDSP_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 3,
+ // Src: (intrinsic_void 3596:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt7>>:$mask) - Complexity = 12
+ // Dst: (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$mask)
+/* 20852*/ 0, /*End of Scope*/
+/* 20853*/ /*Scope*/ 29, /*->20883*/
+/* 20854*/ OPC_CheckChild1Integer, 38|128,24/*3110*/,
+/* 20857*/ OPC_RecordChild2, // #1 = $rs
+/* 20858*/ OPC_RecordChild3, // #2 = $rt
+/* 20859*/ OPC_Scope, 10, /*->20871*/ // 2 children in Scope
+/* 20861*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 20863*/ OPC_EmitMergeInputChains1_0,
+/* 20864*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMPU_EQ_QB), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3110:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 20871*/ /*Scope*/ 10, /*->20882*/
+/* 20872*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 20874*/ OPC_EmitMergeInputChains1_0,
+/* 20875*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMPU_EQ_QB_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3110:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 20882*/ 0, /*End of Scope*/
+/* 20883*/ /*Scope*/ 29, /*->20913*/
+/* 20884*/ OPC_CheckChild1Integer, 40|128,24/*3112*/,
+/* 20887*/ OPC_RecordChild2, // #1 = $rs
+/* 20888*/ OPC_RecordChild3, // #2 = $rt
+/* 20889*/ OPC_Scope, 10, /*->20901*/ // 2 children in Scope
+/* 20891*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 20893*/ OPC_EmitMergeInputChains1_0,
+/* 20894*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMPU_LT_QB), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3112:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 20901*/ /*Scope*/ 10, /*->20912*/
+/* 20902*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 20904*/ OPC_EmitMergeInputChains1_0,
+/* 20905*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMPU_LT_QB_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3112:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 20912*/ 0, /*End of Scope*/
+/* 20913*/ /*Scope*/ 29, /*->20943*/
+/* 20914*/ OPC_CheckChild1Integer, 39|128,24/*3111*/,
+/* 20917*/ OPC_RecordChild2, // #1 = $rs
+/* 20918*/ OPC_RecordChild3, // #2 = $rt
+/* 20919*/ OPC_Scope, 10, /*->20931*/ // 2 children in Scope
+/* 20921*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 20923*/ OPC_EmitMergeInputChains1_0,
+/* 20924*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMPU_LE_QB), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 20931*/ /*Scope*/ 10, /*->20942*/
+/* 20932*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 20934*/ OPC_EmitMergeInputChains1_0,
+/* 20935*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMPU_LE_QB_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) - Complexity = 8
+ // Dst: (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+/* 20942*/ 0, /*End of Scope*/
+/* 20943*/ /*Scope*/ 29, /*->20973*/
+/* 20944*/ OPC_CheckChild1Integer, 29|128,24/*3101*/,
+/* 20947*/ OPC_RecordChild2, // #1 = $rs
+/* 20948*/ OPC_RecordChild3, // #2 = $rt
+/* 20949*/ OPC_Scope, 10, /*->20961*/ // 2 children in Scope
+/* 20951*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 20953*/ OPC_EmitMergeInputChains1_0,
+/* 20954*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMP_EQ_PH), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3101:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 20961*/ /*Scope*/ 10, /*->20972*/
+/* 20962*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 20964*/ OPC_EmitMergeInputChains1_0,
+/* 20965*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMP_EQ_PH_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3101:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 20972*/ 0, /*End of Scope*/
+/* 20973*/ /*Scope*/ 29, /*->21003*/
+/* 20974*/ OPC_CheckChild1Integer, 31|128,24/*3103*/,
+/* 20977*/ OPC_RecordChild2, // #1 = $rs
+/* 20978*/ OPC_RecordChild3, // #2 = $rt
+/* 20979*/ OPC_Scope, 10, /*->20991*/ // 2 children in Scope
+/* 20981*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 20983*/ OPC_EmitMergeInputChains1_0,
+/* 20984*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMP_LT_PH), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3103:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 20991*/ /*Scope*/ 10, /*->21002*/
+/* 20992*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 20994*/ OPC_EmitMergeInputChains1_0,
+/* 20995*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMP_LT_PH_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3103:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 21002*/ 0, /*End of Scope*/
+/* 21003*/ /*Scope*/ 29, /*->21033*/
+/* 21004*/ OPC_CheckChild1Integer, 30|128,24/*3102*/,
+/* 21007*/ OPC_RecordChild2, // #1 = $rs
+/* 21008*/ OPC_RecordChild3, // #2 = $rt
+/* 21009*/ OPC_Scope, 10, /*->21021*/ // 2 children in Scope
+/* 21011*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 21013*/ OPC_EmitMergeInputChains1_0,
+/* 21014*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMP_LE_PH), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3102:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 21021*/ /*Scope*/ 10, /*->21032*/
+/* 21022*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 21024*/ OPC_EmitMergeInputChains1_0,
+/* 21025*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::CMP_LE_PH_MM), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (intrinsic_void 3102:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) - Complexity = 8
+ // Dst: (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+/* 21032*/ 0, /*End of Scope*/
+/* 21033*/ 0, /*End of Scope*/
+/* 21034*/ /*SwitchOpcode*/ 52|128,18/*2356*/, TARGET_VAL(ISD::XOR),// ->23394
+/* 21038*/ OPC_Scope, 69, /*->21109*/ // 14 children in Scope
+/* 21040*/ OPC_MoveChild0,
+/* 21041*/ OPC_CheckOpcode, TARGET_VAL(ISD::OR),
+/* 21044*/ OPC_RecordChild0, // #0 = $rs
+/* 21045*/ OPC_RecordChild1, // #1 = $rt
+/* 21046*/ OPC_MoveParent,
+/* 21047*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 21058*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->21096
+/* 21061*/ OPC_Scope, 10, /*->21073*/ // 3 children in Scope
+/* 21063*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 21065*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) - Complexity = 11
+ // Dst: (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 21073*/ /*Scope*/ 10, /*->21084*/
+/* 21074*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 21076*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) - Complexity = 11
+ // Dst: (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 21084*/ /*Scope*/ 10, /*->21095*/
+/* 21085*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 21087*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) - Complexity = 11
+ // Dst: (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 21095*/ 0, /*End of Scope*/
+/* 21096*/ /*SwitchType*/ 10, MVT::i64,// ->21108
+/* 21098*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 21100*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) - Complexity = 11
+ // Dst: (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 21108*/ 0, // EndSwitchType
+/* 21109*/ /*Scope*/ 2|128,5/*642*/, /*->21753*/
+/* 21111*/ OPC_RecordChild0, // #0 = $rs
+/* 21112*/ OPC_Scope, 109, /*->21223*/ // 3 children in Scope
+/* 21114*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 21125*/ OPC_CheckType, MVT::i32,
+/* 21127*/ OPC_Scope, 9, /*->21138*/ // 6 children in Scope
+/* 21129*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 21131*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOT16_MMR6), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) - Complexity = 9
+ // Dst: (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
+/* 21138*/ /*Scope*/ 13, /*->21152*/
+/* 21139*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 21141*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 21144*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) - Complexity = 8
+ // Dst: (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
+/* 21152*/ /*Scope*/ 9, /*->21162*/
+/* 21153*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 21155*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NotRxRy16), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) - Complexity = 8
+ // Dst: (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
+/* 21162*/ /*Scope*/ 9, /*->21172*/
+/* 21163*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 21165*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOT16_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) - Complexity = 8
+ // Dst: (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
+/* 21172*/ /*Scope*/ 24, /*->21197*/
+/* 21173*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 21175*/ OPC_Scope, 7, /*->21184*/ // 2 children in Scope
+/* 21177*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOT16_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) - Complexity = 8
+ // Dst: (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
+/* 21184*/ /*Scope*/ 11, /*->21196*/
+/* 21185*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 21188*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) - Complexity = 8
+ // Dst: (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
+/* 21196*/ 0, /*End of Scope*/
+/* 21197*/ /*Scope*/ 24, /*->21222*/
+/* 21198*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 21200*/ OPC_Scope, 7, /*->21209*/ // 2 children in Scope
+/* 21202*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOT16_MMR6), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) - Complexity = 8
+ // Dst: (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
+/* 21209*/ /*Scope*/ 11, /*->21221*/
+/* 21210*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 21213*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) - Complexity = 8
+ // Dst: (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
+/* 21221*/ 0, /*End of Scope*/
+/* 21222*/ 0, /*End of Scope*/
+/* 21223*/ /*Scope*/ 28|128,1/*156*/, /*->21381*/
+/* 21225*/ OPC_RecordChild1, // #1 = $imm16
+/* 21226*/ OPC_Scope, 78, /*->21306*/ // 3 children in Scope
+/* 21228*/ OPC_MoveChild1,
+/* 21229*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21232*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 21234*/ OPC_MoveParent,
+/* 21235*/ OPC_SwitchType /*2 cases */, 50, MVT::i32,// ->21288
+/* 21238*/ OPC_Scope, 15, /*->21255*/ // 3 children in Scope
+/* 21240*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 21242*/ OPC_EmitConvertToTarget, 1,
+/* 21244*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 21247*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm16))
+/* 21255*/ /*Scope*/ 15, /*->21271*/
+/* 21256*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 21258*/ OPC_EmitConvertToTarget, 1,
+/* 21260*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 21263*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (XORi_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm16))
+/* 21271*/ /*Scope*/ 15, /*->21287*/
+/* 21272*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 21274*/ OPC_EmitConvertToTarget, 1,
+/* 21276*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 21279*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORI_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (XORI_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm16))
+/* 21287*/ 0, /*End of Scope*/
+/* 21288*/ /*SwitchType*/ 15, MVT::i64,// ->21305
+/* 21290*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 21292*/ OPC_EmitConvertToTarget, 1,
+/* 21294*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 21297*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 3,
+ // Src: (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (XORi64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (LO16:{ *:[i64] } (imm:{ *:[i64] }):$imm16))
+/* 21305*/ 0, // EndSwitchType
+/* 21306*/ /*Scope*/ 60, /*->21367*/
+/* 21307*/ OPC_CheckType, MVT::i32,
+/* 21309*/ OPC_Scope, 10, /*->21321*/ // 4 children in Scope
+/* 21311*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 21313*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 21321*/ /*Scope*/ 10, /*->21332*/
+/* 21322*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 21324*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XorRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) - Complexity = 3
+ // Dst: (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+/* 21332*/ /*Scope*/ 22, /*->21355*/
+/* 21333*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 21335*/ OPC_Scope, 8, /*->21345*/ // 2 children in Scope
+/* 21337*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR16_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+/* 21345*/ /*Scope*/ 8, /*->21354*/
+/* 21346*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 21354*/ 0, /*End of Scope*/
+/* 21355*/ /*Scope*/ 10, /*->21366*/
+/* 21356*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 21358*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 21366*/ 0, /*End of Scope*/
+/* 21367*/ /*Scope*/ 12, /*->21380*/
+/* 21368*/ OPC_CheckType, MVT::i64,
+/* 21370*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 21372*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 21380*/ 0, /*End of Scope*/
+/* 21381*/ /*Scope*/ 113|128,2/*369*/, /*->21752*/
+/* 21383*/ OPC_MoveChild1,
+/* 21384*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 21387*/ OPC_MoveChild0,
+/* 21388*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 21391*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 21393*/ OPC_MoveParent,
+/* 21394*/ OPC_MoveChild1,
+/* 21395*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 21398*/ OPC_Scope, 46|128,1/*174*/, /*->21575*/ // 2 children in Scope
+/* 21401*/ OPC_RecordChild0, // #1 = $wt
+/* 21402*/ OPC_MoveChild1,
+/* 21403*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 21406*/ OPC_MoveChild0,
+/* 21407*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21410*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21412*/ OPC_CheckType, MVT::i32,
+/* 21414*/ OPC_MoveParent,
+/* 21415*/ OPC_MoveChild1,
+/* 21416*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21419*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21421*/ OPC_CheckType, MVT::i32,
+/* 21423*/ OPC_MoveParent,
+/* 21424*/ OPC_MoveChild2,
+/* 21425*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21428*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21430*/ OPC_CheckType, MVT::i32,
+/* 21432*/ OPC_MoveParent,
+/* 21433*/ OPC_MoveChild3,
+/* 21434*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21437*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21439*/ OPC_CheckType, MVT::i32,
+/* 21441*/ OPC_MoveParent,
+/* 21442*/ OPC_MoveChild4,
+/* 21443*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21446*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21448*/ OPC_CheckType, MVT::i32,
+/* 21450*/ OPC_MoveParent,
+/* 21451*/ OPC_MoveChild5,
+/* 21452*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21455*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21457*/ OPC_CheckType, MVT::i32,
+/* 21459*/ OPC_MoveParent,
+/* 21460*/ OPC_MoveChild6,
+/* 21461*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21464*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21466*/ OPC_CheckType, MVT::i32,
+/* 21468*/ OPC_MoveParent,
+/* 21469*/ OPC_MoveChild7,
+/* 21470*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21473*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21475*/ OPC_CheckType, MVT::i32,
+/* 21477*/ OPC_MoveParent,
+/* 21478*/ OPC_MoveChild, 8,
+/* 21480*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21483*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21485*/ OPC_CheckType, MVT::i32,
+/* 21487*/ OPC_MoveParent,
+/* 21488*/ OPC_MoveChild, 9,
+/* 21490*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21493*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21495*/ OPC_CheckType, MVT::i32,
+/* 21497*/ OPC_MoveParent,
+/* 21498*/ OPC_MoveChild, 10,
+/* 21500*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21503*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21505*/ OPC_CheckType, MVT::i32,
+/* 21507*/ OPC_MoveParent,
+/* 21508*/ OPC_MoveChild, 11,
+/* 21510*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21513*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21515*/ OPC_CheckType, MVT::i32,
+/* 21517*/ OPC_MoveParent,
+/* 21518*/ OPC_MoveChild, 12,
+/* 21520*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21523*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21525*/ OPC_CheckType, MVT::i32,
+/* 21527*/ OPC_MoveParent,
+/* 21528*/ OPC_MoveChild, 13,
+/* 21530*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21533*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21535*/ OPC_CheckType, MVT::i32,
+/* 21537*/ OPC_MoveParent,
+/* 21538*/ OPC_MoveChild, 14,
+/* 21540*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21543*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21545*/ OPC_CheckType, MVT::i32,
+/* 21547*/ OPC_MoveParent,
+/* 21548*/ OPC_MoveChild, 15,
+/* 21550*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21553*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21555*/ OPC_CheckType, MVT::i32,
+/* 21557*/ OPC_MoveParent,
+/* 21558*/ OPC_MoveParent,
+/* 21559*/ OPC_CheckType, MVT::v16i8,
+/* 21561*/ OPC_MoveParent,
+/* 21562*/ OPC_MoveParent,
+/* 21563*/ OPC_CheckType, MVT::v16i8,
+/* 21565*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 21567*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))) - Complexity = 80
+ // Dst: (BNEG_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 21575*/ /*Scope*/ 46|128,1/*174*/, /*->21751*/
+/* 21577*/ OPC_MoveChild0,
+/* 21578*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 21581*/ OPC_MoveChild0,
+/* 21582*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21585*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21587*/ OPC_CheckType, MVT::i32,
+/* 21589*/ OPC_MoveParent,
+/* 21590*/ OPC_MoveChild1,
+/* 21591*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21594*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21596*/ OPC_CheckType, MVT::i32,
+/* 21598*/ OPC_MoveParent,
+/* 21599*/ OPC_MoveChild2,
+/* 21600*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21603*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21605*/ OPC_CheckType, MVT::i32,
+/* 21607*/ OPC_MoveParent,
+/* 21608*/ OPC_MoveChild3,
+/* 21609*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21612*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21614*/ OPC_CheckType, MVT::i32,
+/* 21616*/ OPC_MoveParent,
+/* 21617*/ OPC_MoveChild4,
+/* 21618*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21621*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21623*/ OPC_CheckType, MVT::i32,
+/* 21625*/ OPC_MoveParent,
+/* 21626*/ OPC_MoveChild5,
+/* 21627*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21630*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21632*/ OPC_CheckType, MVT::i32,
+/* 21634*/ OPC_MoveParent,
+/* 21635*/ OPC_MoveChild6,
+/* 21636*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21639*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21641*/ OPC_CheckType, MVT::i32,
+/* 21643*/ OPC_MoveParent,
+/* 21644*/ OPC_MoveChild7,
+/* 21645*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21648*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21650*/ OPC_CheckType, MVT::i32,
+/* 21652*/ OPC_MoveParent,
+/* 21653*/ OPC_MoveChild, 8,
+/* 21655*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21658*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21660*/ OPC_CheckType, MVT::i32,
+/* 21662*/ OPC_MoveParent,
+/* 21663*/ OPC_MoveChild, 9,
+/* 21665*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21668*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21670*/ OPC_CheckType, MVT::i32,
+/* 21672*/ OPC_MoveParent,
+/* 21673*/ OPC_MoveChild, 10,
+/* 21675*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21678*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21680*/ OPC_CheckType, MVT::i32,
+/* 21682*/ OPC_MoveParent,
+/* 21683*/ OPC_MoveChild, 11,
+/* 21685*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21688*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21690*/ OPC_CheckType, MVT::i32,
+/* 21692*/ OPC_MoveParent,
+/* 21693*/ OPC_MoveChild, 12,
+/* 21695*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21698*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21700*/ OPC_CheckType, MVT::i32,
+/* 21702*/ OPC_MoveParent,
+/* 21703*/ OPC_MoveChild, 13,
+/* 21705*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21708*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21710*/ OPC_CheckType, MVT::i32,
+/* 21712*/ OPC_MoveParent,
+/* 21713*/ OPC_MoveChild, 14,
+/* 21715*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21718*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21720*/ OPC_CheckType, MVT::i32,
+/* 21722*/ OPC_MoveParent,
+/* 21723*/ OPC_MoveChild, 15,
+/* 21725*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21728*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21730*/ OPC_CheckType, MVT::i32,
+/* 21732*/ OPC_MoveParent,
+/* 21733*/ OPC_MoveParent,
+/* 21734*/ OPC_RecordChild1, // #1 = $wt
+/* 21735*/ OPC_CheckType, MVT::v16i8,
+/* 21737*/ OPC_MoveParent,
+/* 21738*/ OPC_MoveParent,
+/* 21739*/ OPC_CheckType, MVT::v16i8,
+/* 21741*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 21743*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))) - Complexity = 80
+ // Dst: (BNEG_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 21751*/ 0, /*End of Scope*/
+/* 21752*/ 0, /*End of Scope*/
+/* 21753*/ /*Scope*/ 115|128,2/*371*/, /*->22126*/
+/* 21755*/ OPC_MoveChild0,
+/* 21756*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 21759*/ OPC_MoveChild0,
+/* 21760*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 21763*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 21765*/ OPC_MoveParent,
+/* 21766*/ OPC_MoveChild1,
+/* 21767*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 21770*/ OPC_Scope, 47|128,1/*175*/, /*->21948*/ // 2 children in Scope
+/* 21773*/ OPC_RecordChild0, // #0 = $wt
+/* 21774*/ OPC_MoveChild1,
+/* 21775*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 21778*/ OPC_MoveChild0,
+/* 21779*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21782*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21784*/ OPC_CheckType, MVT::i32,
+/* 21786*/ OPC_MoveParent,
+/* 21787*/ OPC_MoveChild1,
+/* 21788*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21791*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21793*/ OPC_CheckType, MVT::i32,
+/* 21795*/ OPC_MoveParent,
+/* 21796*/ OPC_MoveChild2,
+/* 21797*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21800*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21802*/ OPC_CheckType, MVT::i32,
+/* 21804*/ OPC_MoveParent,
+/* 21805*/ OPC_MoveChild3,
+/* 21806*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21809*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21811*/ OPC_CheckType, MVT::i32,
+/* 21813*/ OPC_MoveParent,
+/* 21814*/ OPC_MoveChild4,
+/* 21815*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21818*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21820*/ OPC_CheckType, MVT::i32,
+/* 21822*/ OPC_MoveParent,
+/* 21823*/ OPC_MoveChild5,
+/* 21824*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21827*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21829*/ OPC_CheckType, MVT::i32,
+/* 21831*/ OPC_MoveParent,
+/* 21832*/ OPC_MoveChild6,
+/* 21833*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21836*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21838*/ OPC_CheckType, MVT::i32,
+/* 21840*/ OPC_MoveParent,
+/* 21841*/ OPC_MoveChild7,
+/* 21842*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21845*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21847*/ OPC_CheckType, MVT::i32,
+/* 21849*/ OPC_MoveParent,
+/* 21850*/ OPC_MoveChild, 8,
+/* 21852*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21855*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21857*/ OPC_CheckType, MVT::i32,
+/* 21859*/ OPC_MoveParent,
+/* 21860*/ OPC_MoveChild, 9,
+/* 21862*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21865*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21867*/ OPC_CheckType, MVT::i32,
+/* 21869*/ OPC_MoveParent,
+/* 21870*/ OPC_MoveChild, 10,
+/* 21872*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21875*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21877*/ OPC_CheckType, MVT::i32,
+/* 21879*/ OPC_MoveParent,
+/* 21880*/ OPC_MoveChild, 11,
+/* 21882*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21885*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21887*/ OPC_CheckType, MVT::i32,
+/* 21889*/ OPC_MoveParent,
+/* 21890*/ OPC_MoveChild, 12,
+/* 21892*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21895*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21897*/ OPC_CheckType, MVT::i32,
+/* 21899*/ OPC_MoveParent,
+/* 21900*/ OPC_MoveChild, 13,
+/* 21902*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21905*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21907*/ OPC_CheckType, MVT::i32,
+/* 21909*/ OPC_MoveParent,
+/* 21910*/ OPC_MoveChild, 14,
+/* 21912*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21915*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21917*/ OPC_CheckType, MVT::i32,
+/* 21919*/ OPC_MoveParent,
+/* 21920*/ OPC_MoveChild, 15,
+/* 21922*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21925*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21927*/ OPC_CheckType, MVT::i32,
+/* 21929*/ OPC_MoveParent,
+/* 21930*/ OPC_MoveParent,
+/* 21931*/ OPC_CheckType, MVT::v16i8,
+/* 21933*/ OPC_MoveParent,
+/* 21934*/ OPC_MoveParent,
+/* 21935*/ OPC_RecordChild1, // #1 = $ws
+/* 21936*/ OPC_CheckType, MVT::v16i8,
+/* 21938*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 21940*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))), v16i8:{ *:[v16i8] }:$ws) - Complexity = 80
+ // Dst: (BNEG_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 21948*/ /*Scope*/ 47|128,1/*175*/, /*->22125*/
+/* 21950*/ OPC_MoveChild0,
+/* 21951*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 21954*/ OPC_MoveChild0,
+/* 21955*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21958*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21960*/ OPC_CheckType, MVT::i32,
+/* 21962*/ OPC_MoveParent,
+/* 21963*/ OPC_MoveChild1,
+/* 21964*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21967*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21969*/ OPC_CheckType, MVT::i32,
+/* 21971*/ OPC_MoveParent,
+/* 21972*/ OPC_MoveChild2,
+/* 21973*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21976*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21978*/ OPC_CheckType, MVT::i32,
+/* 21980*/ OPC_MoveParent,
+/* 21981*/ OPC_MoveChild3,
+/* 21982*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21985*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21987*/ OPC_CheckType, MVT::i32,
+/* 21989*/ OPC_MoveParent,
+/* 21990*/ OPC_MoveChild4,
+/* 21991*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 21994*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 21996*/ OPC_CheckType, MVT::i32,
+/* 21998*/ OPC_MoveParent,
+/* 21999*/ OPC_MoveChild5,
+/* 22000*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22003*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22005*/ OPC_CheckType, MVT::i32,
+/* 22007*/ OPC_MoveParent,
+/* 22008*/ OPC_MoveChild6,
+/* 22009*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22012*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22014*/ OPC_CheckType, MVT::i32,
+/* 22016*/ OPC_MoveParent,
+/* 22017*/ OPC_MoveChild7,
+/* 22018*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22021*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22023*/ OPC_CheckType, MVT::i32,
+/* 22025*/ OPC_MoveParent,
+/* 22026*/ OPC_MoveChild, 8,
+/* 22028*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22031*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22033*/ OPC_CheckType, MVT::i32,
+/* 22035*/ OPC_MoveParent,
+/* 22036*/ OPC_MoveChild, 9,
+/* 22038*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22041*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22043*/ OPC_CheckType, MVT::i32,
+/* 22045*/ OPC_MoveParent,
+/* 22046*/ OPC_MoveChild, 10,
+/* 22048*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22051*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22053*/ OPC_CheckType, MVT::i32,
+/* 22055*/ OPC_MoveParent,
+/* 22056*/ OPC_MoveChild, 11,
+/* 22058*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22061*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22063*/ OPC_CheckType, MVT::i32,
+/* 22065*/ OPC_MoveParent,
+/* 22066*/ OPC_MoveChild, 12,
+/* 22068*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22071*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22073*/ OPC_CheckType, MVT::i32,
+/* 22075*/ OPC_MoveParent,
+/* 22076*/ OPC_MoveChild, 13,
+/* 22078*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22081*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22083*/ OPC_CheckType, MVT::i32,
+/* 22085*/ OPC_MoveParent,
+/* 22086*/ OPC_MoveChild, 14,
+/* 22088*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22091*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22093*/ OPC_CheckType, MVT::i32,
+/* 22095*/ OPC_MoveParent,
+/* 22096*/ OPC_MoveChild, 15,
+/* 22098*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22101*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 22103*/ OPC_CheckType, MVT::i32,
+/* 22105*/ OPC_MoveParent,
+/* 22106*/ OPC_MoveParent,
+/* 22107*/ OPC_RecordChild1, // #0 = $wt
+/* 22108*/ OPC_CheckType, MVT::v16i8,
+/* 22110*/ OPC_MoveParent,
+/* 22111*/ OPC_MoveParent,
+/* 22112*/ OPC_RecordChild1, // #1 = $ws
+/* 22113*/ OPC_CheckType, MVT::v16i8,
+/* 22115*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22117*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)), v16i8:{ *:[v16i8] }:$ws) - Complexity = 80
+ // Dst: (BNEG_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 22125*/ 0, /*End of Scope*/
+/* 22126*/ /*Scope*/ 80|128,1/*208*/, /*->22336*/
+/* 22128*/ OPC_RecordChild0, // #0 = $ws
+/* 22129*/ OPC_MoveChild1,
+/* 22130*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 22133*/ OPC_MoveChild0,
+/* 22134*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22137*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 22139*/ OPC_MoveParent,
+/* 22140*/ OPC_MoveChild1,
+/* 22141*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 22144*/ OPC_Scope, 94, /*->22240*/ // 2 children in Scope
+/* 22146*/ OPC_RecordChild0, // #1 = $wt
+/* 22147*/ OPC_MoveChild1,
+/* 22148*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22151*/ OPC_MoveChild0,
+/* 22152*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22155*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22157*/ OPC_CheckType, MVT::i32,
+/* 22159*/ OPC_MoveParent,
+/* 22160*/ OPC_MoveChild1,
+/* 22161*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22164*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22166*/ OPC_CheckType, MVT::i32,
+/* 22168*/ OPC_MoveParent,
+/* 22169*/ OPC_MoveChild2,
+/* 22170*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22173*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22175*/ OPC_CheckType, MVT::i32,
+/* 22177*/ OPC_MoveParent,
+/* 22178*/ OPC_MoveChild3,
+/* 22179*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22182*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22184*/ OPC_CheckType, MVT::i32,
+/* 22186*/ OPC_MoveParent,
+/* 22187*/ OPC_MoveChild4,
+/* 22188*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22191*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22193*/ OPC_CheckType, MVT::i32,
+/* 22195*/ OPC_MoveParent,
+/* 22196*/ OPC_MoveChild5,
+/* 22197*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22200*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22202*/ OPC_CheckType, MVT::i32,
+/* 22204*/ OPC_MoveParent,
+/* 22205*/ OPC_MoveChild6,
+/* 22206*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22209*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22211*/ OPC_CheckType, MVT::i32,
+/* 22213*/ OPC_MoveParent,
+/* 22214*/ OPC_MoveChild7,
+/* 22215*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22218*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22220*/ OPC_CheckType, MVT::i32,
+/* 22222*/ OPC_MoveParent,
+/* 22223*/ OPC_MoveParent,
+/* 22224*/ OPC_CheckType, MVT::v8i16,
+/* 22226*/ OPC_MoveParent,
+/* 22227*/ OPC_MoveParent,
+/* 22228*/ OPC_CheckType, MVT::v8i16,
+/* 22230*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22232*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))) - Complexity = 48
+ // Dst: (BNEG_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 22240*/ /*Scope*/ 94, /*->22335*/
+/* 22241*/ OPC_MoveChild0,
+/* 22242*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22245*/ OPC_MoveChild0,
+/* 22246*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22249*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22251*/ OPC_CheckType, MVT::i32,
+/* 22253*/ OPC_MoveParent,
+/* 22254*/ OPC_MoveChild1,
+/* 22255*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22258*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22260*/ OPC_CheckType, MVT::i32,
+/* 22262*/ OPC_MoveParent,
+/* 22263*/ OPC_MoveChild2,
+/* 22264*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22267*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22269*/ OPC_CheckType, MVT::i32,
+/* 22271*/ OPC_MoveParent,
+/* 22272*/ OPC_MoveChild3,
+/* 22273*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22276*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22278*/ OPC_CheckType, MVT::i32,
+/* 22280*/ OPC_MoveParent,
+/* 22281*/ OPC_MoveChild4,
+/* 22282*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22285*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22287*/ OPC_CheckType, MVT::i32,
+/* 22289*/ OPC_MoveParent,
+/* 22290*/ OPC_MoveChild5,
+/* 22291*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22294*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22296*/ OPC_CheckType, MVT::i32,
+/* 22298*/ OPC_MoveParent,
+/* 22299*/ OPC_MoveChild6,
+/* 22300*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22303*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22305*/ OPC_CheckType, MVT::i32,
+/* 22307*/ OPC_MoveParent,
+/* 22308*/ OPC_MoveChild7,
+/* 22309*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22312*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22314*/ OPC_CheckType, MVT::i32,
+/* 22316*/ OPC_MoveParent,
+/* 22317*/ OPC_MoveParent,
+/* 22318*/ OPC_RecordChild1, // #1 = $wt
+/* 22319*/ OPC_CheckType, MVT::v8i16,
+/* 22321*/ OPC_MoveParent,
+/* 22322*/ OPC_MoveParent,
+/* 22323*/ OPC_CheckType, MVT::v8i16,
+/* 22325*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22327*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))) - Complexity = 48
+ // Dst: (BNEG_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 22335*/ 0, /*End of Scope*/
+/* 22336*/ /*Scope*/ 81|128,1/*209*/, /*->22547*/
+/* 22338*/ OPC_MoveChild0,
+/* 22339*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 22342*/ OPC_MoveChild0,
+/* 22343*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22346*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 22348*/ OPC_MoveParent,
+/* 22349*/ OPC_MoveChild1,
+/* 22350*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 22353*/ OPC_Scope, 95, /*->22450*/ // 2 children in Scope
+/* 22355*/ OPC_RecordChild0, // #0 = $wt
+/* 22356*/ OPC_MoveChild1,
+/* 22357*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22360*/ OPC_MoveChild0,
+/* 22361*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22364*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22366*/ OPC_CheckType, MVT::i32,
+/* 22368*/ OPC_MoveParent,
+/* 22369*/ OPC_MoveChild1,
+/* 22370*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22373*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22375*/ OPC_CheckType, MVT::i32,
+/* 22377*/ OPC_MoveParent,
+/* 22378*/ OPC_MoveChild2,
+/* 22379*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22382*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22384*/ OPC_CheckType, MVT::i32,
+/* 22386*/ OPC_MoveParent,
+/* 22387*/ OPC_MoveChild3,
+/* 22388*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22391*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22393*/ OPC_CheckType, MVT::i32,
+/* 22395*/ OPC_MoveParent,
+/* 22396*/ OPC_MoveChild4,
+/* 22397*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22400*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22402*/ OPC_CheckType, MVT::i32,
+/* 22404*/ OPC_MoveParent,
+/* 22405*/ OPC_MoveChild5,
+/* 22406*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22409*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22411*/ OPC_CheckType, MVT::i32,
+/* 22413*/ OPC_MoveParent,
+/* 22414*/ OPC_MoveChild6,
+/* 22415*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22418*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22420*/ OPC_CheckType, MVT::i32,
+/* 22422*/ OPC_MoveParent,
+/* 22423*/ OPC_MoveChild7,
+/* 22424*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22427*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22429*/ OPC_CheckType, MVT::i32,
+/* 22431*/ OPC_MoveParent,
+/* 22432*/ OPC_MoveParent,
+/* 22433*/ OPC_CheckType, MVT::v8i16,
+/* 22435*/ OPC_MoveParent,
+/* 22436*/ OPC_MoveParent,
+/* 22437*/ OPC_RecordChild1, // #1 = $ws
+/* 22438*/ OPC_CheckType, MVT::v8i16,
+/* 22440*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22442*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))), v8i16:{ *:[v8i16] }:$ws) - Complexity = 48
+ // Dst: (BNEG_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 22450*/ /*Scope*/ 95, /*->22546*/
+/* 22451*/ OPC_MoveChild0,
+/* 22452*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22455*/ OPC_MoveChild0,
+/* 22456*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22459*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22461*/ OPC_CheckType, MVT::i32,
+/* 22463*/ OPC_MoveParent,
+/* 22464*/ OPC_MoveChild1,
+/* 22465*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22468*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22470*/ OPC_CheckType, MVT::i32,
+/* 22472*/ OPC_MoveParent,
+/* 22473*/ OPC_MoveChild2,
+/* 22474*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22477*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22479*/ OPC_CheckType, MVT::i32,
+/* 22481*/ OPC_MoveParent,
+/* 22482*/ OPC_MoveChild3,
+/* 22483*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22486*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22488*/ OPC_CheckType, MVT::i32,
+/* 22490*/ OPC_MoveParent,
+/* 22491*/ OPC_MoveChild4,
+/* 22492*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22495*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22497*/ OPC_CheckType, MVT::i32,
+/* 22499*/ OPC_MoveParent,
+/* 22500*/ OPC_MoveChild5,
+/* 22501*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22504*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22506*/ OPC_CheckType, MVT::i32,
+/* 22508*/ OPC_MoveParent,
+/* 22509*/ OPC_MoveChild6,
+/* 22510*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22513*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22515*/ OPC_CheckType, MVT::i32,
+/* 22517*/ OPC_MoveParent,
+/* 22518*/ OPC_MoveChild7,
+/* 22519*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22522*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 22524*/ OPC_CheckType, MVT::i32,
+/* 22526*/ OPC_MoveParent,
+/* 22527*/ OPC_MoveParent,
+/* 22528*/ OPC_RecordChild1, // #0 = $wt
+/* 22529*/ OPC_CheckType, MVT::v8i16,
+/* 22531*/ OPC_MoveParent,
+/* 22532*/ OPC_MoveParent,
+/* 22533*/ OPC_RecordChild1, // #1 = $ws
+/* 22534*/ OPC_CheckType, MVT::v8i16,
+/* 22536*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22538*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)), v8i16:{ *:[v8i16] }:$ws) - Complexity = 48
+ // Dst: (BNEG_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 22546*/ 0, /*End of Scope*/
+/* 22547*/ /*Scope*/ 8|128,1/*136*/, /*->22685*/
+/* 22549*/ OPC_RecordChild0, // #0 = $ws
+/* 22550*/ OPC_MoveChild1,
+/* 22551*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 22554*/ OPC_MoveChild0,
+/* 22555*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22558*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 22560*/ OPC_MoveParent,
+/* 22561*/ OPC_MoveChild1,
+/* 22562*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 22565*/ OPC_Scope, 58, /*->22625*/ // 2 children in Scope
+/* 22567*/ OPC_RecordChild0, // #1 = $wt
+/* 22568*/ OPC_MoveChild1,
+/* 22569*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22572*/ OPC_MoveChild0,
+/* 22573*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22576*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22578*/ OPC_CheckType, MVT::i32,
+/* 22580*/ OPC_MoveParent,
+/* 22581*/ OPC_MoveChild1,
+/* 22582*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22585*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22587*/ OPC_CheckType, MVT::i32,
+/* 22589*/ OPC_MoveParent,
+/* 22590*/ OPC_MoveChild2,
+/* 22591*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22594*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22596*/ OPC_CheckType, MVT::i32,
+/* 22598*/ OPC_MoveParent,
+/* 22599*/ OPC_MoveChild3,
+/* 22600*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22603*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22605*/ OPC_CheckType, MVT::i32,
+/* 22607*/ OPC_MoveParent,
+/* 22608*/ OPC_MoveParent,
+/* 22609*/ OPC_CheckType, MVT::v4i32,
+/* 22611*/ OPC_MoveParent,
+/* 22612*/ OPC_MoveParent,
+/* 22613*/ OPC_CheckType, MVT::v4i32,
+/* 22615*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22617*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))) - Complexity = 32
+ // Dst: (BNEG_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 22625*/ /*Scope*/ 58, /*->22684*/
+/* 22626*/ OPC_MoveChild0,
+/* 22627*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22630*/ OPC_MoveChild0,
+/* 22631*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22634*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22636*/ OPC_CheckType, MVT::i32,
+/* 22638*/ OPC_MoveParent,
+/* 22639*/ OPC_MoveChild1,
+/* 22640*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22643*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22645*/ OPC_CheckType, MVT::i32,
+/* 22647*/ OPC_MoveParent,
+/* 22648*/ OPC_MoveChild2,
+/* 22649*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22652*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22654*/ OPC_CheckType, MVT::i32,
+/* 22656*/ OPC_MoveParent,
+/* 22657*/ OPC_MoveChild3,
+/* 22658*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22661*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22663*/ OPC_CheckType, MVT::i32,
+/* 22665*/ OPC_MoveParent,
+/* 22666*/ OPC_MoveParent,
+/* 22667*/ OPC_RecordChild1, // #1 = $wt
+/* 22668*/ OPC_CheckType, MVT::v4i32,
+/* 22670*/ OPC_MoveParent,
+/* 22671*/ OPC_MoveParent,
+/* 22672*/ OPC_CheckType, MVT::v4i32,
+/* 22674*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22676*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))) - Complexity = 32
+ // Dst: (BNEG_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 22684*/ 0, /*End of Scope*/
+/* 22685*/ /*Scope*/ 9|128,1/*137*/, /*->22824*/
+/* 22687*/ OPC_MoveChild0,
+/* 22688*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 22691*/ OPC_MoveChild0,
+/* 22692*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22695*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 22697*/ OPC_MoveParent,
+/* 22698*/ OPC_MoveChild1,
+/* 22699*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 22702*/ OPC_Scope, 59, /*->22763*/ // 2 children in Scope
+/* 22704*/ OPC_RecordChild0, // #0 = $wt
+/* 22705*/ OPC_MoveChild1,
+/* 22706*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22709*/ OPC_MoveChild0,
+/* 22710*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22713*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22715*/ OPC_CheckType, MVT::i32,
+/* 22717*/ OPC_MoveParent,
+/* 22718*/ OPC_MoveChild1,
+/* 22719*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22722*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22724*/ OPC_CheckType, MVT::i32,
+/* 22726*/ OPC_MoveParent,
+/* 22727*/ OPC_MoveChild2,
+/* 22728*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22731*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22733*/ OPC_CheckType, MVT::i32,
+/* 22735*/ OPC_MoveParent,
+/* 22736*/ OPC_MoveChild3,
+/* 22737*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22740*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22742*/ OPC_CheckType, MVT::i32,
+/* 22744*/ OPC_MoveParent,
+/* 22745*/ OPC_MoveParent,
+/* 22746*/ OPC_CheckType, MVT::v4i32,
+/* 22748*/ OPC_MoveParent,
+/* 22749*/ OPC_MoveParent,
+/* 22750*/ OPC_RecordChild1, // #1 = $ws
+/* 22751*/ OPC_CheckType, MVT::v4i32,
+/* 22753*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22755*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))), v4i32:{ *:[v4i32] }:$ws) - Complexity = 32
+ // Dst: (BNEG_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 22763*/ /*Scope*/ 59, /*->22823*/
+/* 22764*/ OPC_MoveChild0,
+/* 22765*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22768*/ OPC_MoveChild0,
+/* 22769*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22772*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22774*/ OPC_CheckType, MVT::i32,
+/* 22776*/ OPC_MoveParent,
+/* 22777*/ OPC_MoveChild1,
+/* 22778*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22781*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22783*/ OPC_CheckType, MVT::i32,
+/* 22785*/ OPC_MoveParent,
+/* 22786*/ OPC_MoveChild2,
+/* 22787*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22790*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22792*/ OPC_CheckType, MVT::i32,
+/* 22794*/ OPC_MoveParent,
+/* 22795*/ OPC_MoveChild3,
+/* 22796*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 22799*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 22801*/ OPC_CheckType, MVT::i32,
+/* 22803*/ OPC_MoveParent,
+/* 22804*/ OPC_MoveParent,
+/* 22805*/ OPC_RecordChild1, // #0 = $wt
+/* 22806*/ OPC_CheckType, MVT::v4i32,
+/* 22808*/ OPC_MoveParent,
+/* 22809*/ OPC_MoveParent,
+/* 22810*/ OPC_RecordChild1, // #1 = $ws
+/* 22811*/ OPC_CheckType, MVT::v4i32,
+/* 22813*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22815*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)), v4i32:{ *:[v4i32] }:$ws) - Complexity = 32
+ // Dst: (BNEG_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 22823*/ 0, /*End of Scope*/
+/* 22824*/ /*Scope*/ 89, /*->22914*/
+/* 22825*/ OPC_RecordChild0, // #0 = $ws
+/* 22826*/ OPC_MoveChild1,
+/* 22827*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 22830*/ OPC_MoveChild0,
+/* 22831*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 22834*/ OPC_MoveChild0,
+/* 22835*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22838*/ OPC_CheckType, MVT::v4i32,
+/* 22840*/ OPC_MoveParent,
+/* 22841*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 22843*/ OPC_MoveParent,
+/* 22844*/ OPC_MoveChild1,
+/* 22845*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 22848*/ OPC_Scope, 31, /*->22881*/ // 2 children in Scope
+/* 22850*/ OPC_RecordChild0, // #1 = $wt
+/* 22851*/ OPC_MoveChild1,
+/* 22852*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 22855*/ OPC_MoveChild0,
+/* 22856*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22859*/ OPC_CheckType, MVT::v4i32,
+/* 22861*/ OPC_MoveParent,
+/* 22862*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 22864*/ OPC_MoveParent,
+/* 22865*/ OPC_CheckType, MVT::v2i64,
+/* 22867*/ OPC_MoveParent,
+/* 22868*/ OPC_MoveParent,
+/* 22869*/ OPC_CheckType, MVT::v2i64,
+/* 22871*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22873*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>))) - Complexity = 23
+ // Dst: (BNEG_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 22881*/ /*Scope*/ 31, /*->22913*/
+/* 22882*/ OPC_MoveChild0,
+/* 22883*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 22886*/ OPC_MoveChild0,
+/* 22887*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22890*/ OPC_CheckType, MVT::v4i32,
+/* 22892*/ OPC_MoveParent,
+/* 22893*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 22895*/ OPC_MoveParent,
+/* 22896*/ OPC_RecordChild1, // #1 = $wt
+/* 22897*/ OPC_CheckType, MVT::v2i64,
+/* 22899*/ OPC_MoveParent,
+/* 22900*/ OPC_MoveParent,
+/* 22901*/ OPC_CheckType, MVT::v2i64,
+/* 22903*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22905*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt))) - Complexity = 23
+ // Dst: (BNEG_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 22913*/ 0, /*End of Scope*/
+/* 22914*/ /*Scope*/ 90, /*->23005*/
+/* 22915*/ OPC_MoveChild0,
+/* 22916*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 22919*/ OPC_MoveChild0,
+/* 22920*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 22923*/ OPC_MoveChild0,
+/* 22924*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22927*/ OPC_CheckType, MVT::v4i32,
+/* 22929*/ OPC_MoveParent,
+/* 22930*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 22932*/ OPC_MoveParent,
+/* 22933*/ OPC_MoveChild1,
+/* 22934*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 22937*/ OPC_Scope, 32, /*->22971*/ // 2 children in Scope
+/* 22939*/ OPC_RecordChild0, // #0 = $wt
+/* 22940*/ OPC_MoveChild1,
+/* 22941*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 22944*/ OPC_MoveChild0,
+/* 22945*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22948*/ OPC_CheckType, MVT::v4i32,
+/* 22950*/ OPC_MoveParent,
+/* 22951*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 22953*/ OPC_MoveParent,
+/* 22954*/ OPC_CheckType, MVT::v2i64,
+/* 22956*/ OPC_MoveParent,
+/* 22957*/ OPC_MoveParent,
+/* 22958*/ OPC_RecordChild1, // #1 = $ws
+/* 22959*/ OPC_CheckType, MVT::v2i64,
+/* 22961*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22963*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>)), v2i64:{ *:[v2i64] }:$ws) - Complexity = 23
+ // Dst: (BNEG_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 22971*/ /*Scope*/ 32, /*->23004*/
+/* 22972*/ OPC_MoveChild0,
+/* 22973*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 22976*/ OPC_MoveChild0,
+/* 22977*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 22980*/ OPC_CheckType, MVT::v4i32,
+/* 22982*/ OPC_MoveParent,
+/* 22983*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 22985*/ OPC_MoveParent,
+/* 22986*/ OPC_RecordChild1, // #0 = $wt
+/* 22987*/ OPC_CheckType, MVT::v2i64,
+/* 22989*/ OPC_MoveParent,
+/* 22990*/ OPC_MoveParent,
+/* 22991*/ OPC_RecordChild1, // #1 = $ws
+/* 22992*/ OPC_CheckType, MVT::v2i64,
+/* 22994*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 22996*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt)), v2i64:{ *:[v2i64] }:$ws) - Complexity = 23
+ // Dst: (BNEG_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 23004*/ 0, /*End of Scope*/
+/* 23005*/ /*Scope*/ 35, /*->23041*/
+/* 23006*/ OPC_RecordChild0, // #0 = $ws
+/* 23007*/ OPC_MoveChild1,
+/* 23008*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 23011*/ OPC_MoveChild0,
+/* 23012*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 23015*/ OPC_MoveChild0,
+/* 23016*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 23019*/ OPC_CheckType, MVT::v4i32,
+/* 23021*/ OPC_MoveParent,
+/* 23022*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 23024*/ OPC_MoveParent,
+/* 23025*/ OPC_RecordChild1, // #1 = $wt
+/* 23026*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 23028*/ OPC_MoveParent,
+/* 23029*/ OPC_CheckType, MVT::v2i64,
+/* 23031*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23033*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, MSA128DOpnd:{ *:[v2i64] }:$wt)) - Complexity = 13
+ // Dst: (BNEG_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 23041*/ /*Scope*/ 35, /*->23077*/
+/* 23042*/ OPC_MoveChild0,
+/* 23043*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 23046*/ OPC_MoveChild0,
+/* 23047*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 23050*/ OPC_MoveChild0,
+/* 23051*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 23054*/ OPC_CheckType, MVT::v4i32,
+/* 23056*/ OPC_MoveParent,
+/* 23057*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 23059*/ OPC_MoveParent,
+/* 23060*/ OPC_RecordChild1, // #0 = $wt
+/* 23061*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 23063*/ OPC_MoveParent,
+/* 23064*/ OPC_RecordChild1, // #1 = $ws
+/* 23065*/ OPC_CheckType, MVT::v2i64,
+/* 23067*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23069*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 13
+ // Dst: (BNEG_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 23077*/ /*Scope*/ 63, /*->23141*/
+/* 23078*/ OPC_RecordChild0, // #0 = $ws
+/* 23079*/ OPC_MoveChild1,
+/* 23080*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 23083*/ OPC_MoveChild0,
+/* 23084*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 23087*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 23089*/ OPC_MoveParent,
+/* 23090*/ OPC_RecordChild1, // #1 = $wt
+/* 23091*/ OPC_Scope, 15, /*->23108*/ // 3 children in Scope
+/* 23093*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 23095*/ OPC_MoveParent,
+/* 23096*/ OPC_CheckType, MVT::v16i8,
+/* 23098*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23100*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128BOpnd:{ *:[v16i8] }:$wt)) - Complexity = 10
+ // Dst: (BNEG_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 23108*/ /*Scope*/ 15, /*->23124*/
+/* 23109*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 23111*/ OPC_MoveParent,
+/* 23112*/ OPC_CheckType, MVT::v8i16,
+/* 23114*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23116*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128HOpnd:{ *:[v8i16] }:$wt)) - Complexity = 10
+ // Dst: (BNEG_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 23124*/ /*Scope*/ 15, /*->23140*/
+/* 23125*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 23127*/ OPC_MoveParent,
+/* 23128*/ OPC_CheckType, MVT::v4i32,
+/* 23130*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23132*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128WOpnd:{ *:[v4i32] }:$wt)) - Complexity = 10
+ // Dst: (BNEG_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 23140*/ 0, /*End of Scope*/
+/* 23141*/ /*Scope*/ 65, /*->23207*/
+/* 23142*/ OPC_MoveChild0,
+/* 23143*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 23146*/ OPC_MoveChild0,
+/* 23147*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 23150*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 23152*/ OPC_MoveParent,
+/* 23153*/ OPC_RecordChild1, // #0 = $wt
+/* 23154*/ OPC_Scope, 16, /*->23172*/ // 3 children in Scope
+/* 23156*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 23158*/ OPC_MoveParent,
+/* 23159*/ OPC_RecordChild1, // #1 = $ws
+/* 23160*/ OPC_CheckType, MVT::v16i8,
+/* 23162*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23164*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 10
+ // Dst: (BNEG_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 23172*/ /*Scope*/ 16, /*->23189*/
+/* 23173*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 23175*/ OPC_MoveParent,
+/* 23176*/ OPC_RecordChild1, // #1 = $ws
+/* 23177*/ OPC_CheckType, MVT::v8i16,
+/* 23179*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23181*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 10
+ // Dst: (BNEG_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 23189*/ /*Scope*/ 16, /*->23206*/
+/* 23190*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 23192*/ OPC_MoveParent,
+/* 23193*/ OPC_RecordChild1, // #1 = $ws
+/* 23194*/ OPC_CheckType, MVT::v4i32,
+/* 23196*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23198*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEG_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 10
+ // Dst: (BNEG_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 23206*/ 0, /*End of Scope*/
+/* 23207*/ /*Scope*/ 56|128,1/*184*/, /*->23393*/
+/* 23209*/ OPC_RecordChild0, // #0 = $ws
+/* 23210*/ OPC_RecordChild1, // #1 = $m
+/* 23211*/ OPC_SwitchType /*4 cases */, 61, MVT::v16i8,// ->23275
+/* 23214*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23216*/ OPC_Scope, 11, /*->23229*/ // 5 children in Scope
+/* 23218*/ OPC_CheckComplexPat, /*CP*/13, /*#*/1, // selectVSplatUimmPow2:$m #2
+/* 23221*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEGI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_pow2:{ *:[v16i8] }:$m) - Complexity = 9
+ // Dst: (BNEGI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_pow2:{ *:[v16i8] }:$m)
+/* 23229*/ /*Scope*/ 11, /*->23241*/
+/* 23230*/ OPC_CheckComplexPat, /*CP*/14, /*#*/1, // selectVSplatUimm8:$u8 #2
+/* 23233*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8) - Complexity = 9
+ // Dst: (XORI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 23241*/ /*Scope*/ 11, /*->23253*/
+/* 23242*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // selectVSplatUimmPow2:$m #2
+/* 23245*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEGI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (xor:{ *:[v16i8] } vsplat_uimm_pow2:{ *:[v16i8] }:$m, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (BNEGI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_pow2:{ *:[v16i8] }:$m)
+/* 23253*/ /*Scope*/ 11, /*->23265*/
+/* 23254*/ OPC_CheckComplexPat, /*CP*/14, /*#*/0, // selectVSplatUimm8:$u8 #2
+/* 23257*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (xor:{ *:[v16i8] } vsplati8_uimm8:{ *:[v16i8] }:$u8, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (XORI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 23265*/ /*Scope*/ 8, /*->23274*/
+/* 23266*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR_V), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 23274*/ 0, /*End of Scope*/
+/* 23275*/ /*SwitchType*/ 37, MVT::v8i16,// ->23314
+/* 23277*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23279*/ OPC_Scope, 11, /*->23292*/ // 3 children in Scope
+/* 23281*/ OPC_CheckComplexPat, /*CP*/13, /*#*/1, // selectVSplatUimmPow2:$m #2
+/* 23284*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEGI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_pow2:{ *:[v8i16] }:$m) - Complexity = 9
+ // Dst: (BNEGI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_pow2:{ *:[v8i16] }:$m)
+/* 23292*/ /*Scope*/ 11, /*->23304*/
+/* 23293*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // selectVSplatUimmPow2:$m #2
+/* 23296*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEGI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (xor:{ *:[v8i16] } vsplat_uimm_pow2:{ *:[v8i16] }:$m, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (BNEGI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_pow2:{ *:[v8i16] }:$m)
+/* 23304*/ /*Scope*/ 8, /*->23313*/
+/* 23305*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR_V_H_PSEUDO), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 23313*/ 0, /*End of Scope*/
+/* 23314*/ /*SwitchType*/ 37, MVT::v4i32,// ->23353
+/* 23316*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23318*/ OPC_Scope, 11, /*->23331*/ // 3 children in Scope
+/* 23320*/ OPC_CheckComplexPat, /*CP*/13, /*#*/1, // selectVSplatUimmPow2:$m #2
+/* 23323*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEGI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_pow2:{ *:[v4i32] }:$m) - Complexity = 9
+ // Dst: (BNEGI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_pow2:{ *:[v4i32] }:$m)
+/* 23331*/ /*Scope*/ 11, /*->23343*/
+/* 23332*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // selectVSplatUimmPow2:$m #2
+/* 23335*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEGI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (xor:{ *:[v4i32] } vsplat_uimm_pow2:{ *:[v4i32] }:$m, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (BNEGI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_pow2:{ *:[v4i32] }:$m)
+/* 23343*/ /*Scope*/ 8, /*->23352*/
+/* 23344*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR_V_W_PSEUDO), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 23352*/ 0, /*End of Scope*/
+/* 23353*/ /*SwitchType*/ 37, MVT::v2i64,// ->23392
+/* 23355*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23357*/ OPC_Scope, 11, /*->23370*/ // 3 children in Scope
+/* 23359*/ OPC_CheckComplexPat, /*CP*/13, /*#*/1, // selectVSplatUimmPow2:$m #2
+/* 23362*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEGI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_pow2:{ *:[v2i64] }:$m) - Complexity = 9
+ // Dst: (BNEGI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_pow2:{ *:[v2i64] }:$m)
+/* 23370*/ /*Scope*/ 11, /*->23382*/
+/* 23371*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // selectVSplatUimmPow2:$m #2
+/* 23374*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BNEGI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (xor:{ *:[v2i64] } vsplat_uimm_pow2:{ *:[v2i64] }:$m, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (BNEGI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_pow2:{ *:[v2i64] }:$m)
+/* 23382*/ /*Scope*/ 8, /*->23391*/
+/* 23383*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XOR_V_D_PSEUDO), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 23391*/ 0, /*End of Scope*/
+/* 23392*/ 0, // EndSwitchType
+/* 23393*/ 0, /*End of Scope*/
+/* 23394*/ /*SwitchOpcode*/ 58|128,1/*186*/, TARGET_VAL(ISD::CTLZ),// ->23584
+/* 23398*/ OPC_Scope, 77, /*->23477*/ // 2 children in Scope
+/* 23400*/ OPC_MoveChild0,
+/* 23401*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 23404*/ OPC_RecordChild0, // #0 = $rs
+/* 23405*/ OPC_CheckChild1Integer, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 23416*/ OPC_MoveParent,
+/* 23417*/ OPC_SwitchType /*2 cases */, 32, MVT::i32,// ->23452
+/* 23420*/ OPC_Scope, 9, /*->23431*/ // 3 children in Scope
+/* 23422*/ OPC_CheckPatternPredicate, 49, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 23424*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) - Complexity = 11
+ // Dst: (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 23431*/ /*Scope*/ 9, /*->23441*/
+/* 23432*/ OPC_CheckPatternPredicate, 50, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())
+/* 23434*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLO_R6), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) - Complexity = 11
+ // Dst: (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 23441*/ /*Scope*/ 9, /*->23451*/
+/* 23442*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 23444*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLO_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })) - Complexity = 11
+ // Dst: (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 23451*/ 0, /*End of Scope*/
+/* 23452*/ /*SwitchType*/ 22, MVT::i64,// ->23476
+/* 23454*/ OPC_Scope, 9, /*->23465*/ // 2 children in Scope
+/* 23456*/ OPC_CheckPatternPredicate, 51, // (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())
+/* 23458*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DCLO), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) - Complexity = 11
+ // Dst: (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
+/* 23465*/ /*Scope*/ 9, /*->23475*/
+/* 23466*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 23468*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DCLO_R6), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] })) - Complexity = 11
+ // Dst: (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
+/* 23475*/ 0, /*End of Scope*/
+/* 23476*/ 0, // EndSwitchType
+/* 23477*/ /*Scope*/ 105, /*->23583*/
+/* 23478*/ OPC_RecordChild0, // #0 = $rs
+/* 23479*/ OPC_SwitchType /*6 cases */, 32, MVT::i32,// ->23514
+/* 23482*/ OPC_Scope, 9, /*->23493*/ // 3 children in Scope
+/* 23484*/ OPC_CheckPatternPredicate, 49, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 23486*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLZ), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 23493*/ /*Scope*/ 9, /*->23503*/
+/* 23494*/ OPC_CheckPatternPredicate, 50, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())
+/* 23496*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLZ_R6), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 23503*/ /*Scope*/ 9, /*->23513*/
+/* 23504*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 23506*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLZ_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 23513*/ 0, /*End of Scope*/
+/* 23514*/ /*SwitchType*/ 22, MVT::i64,// ->23538
+/* 23516*/ OPC_Scope, 9, /*->23527*/ // 2 children in Scope
+/* 23518*/ OPC_CheckPatternPredicate, 51, // (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())
+/* 23520*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DCLZ), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
+/* 23527*/ /*Scope*/ 9, /*->23537*/
+/* 23528*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 23530*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DCLZ_R6), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
+/* 23537*/ 0, /*End of Scope*/
+/* 23538*/ /*SwitchType*/ 9, MVT::v16i8,// ->23549
+/* 23540*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23542*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NLZC_B), 0,
+ MVT::v16i8, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 3
+ // Dst: (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
+/* 23549*/ /*SwitchType*/ 9, MVT::v8i16,// ->23560
+/* 23551*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23553*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NLZC_H), 0,
+ MVT::v8i16, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 3
+ // Dst: (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
+/* 23560*/ /*SwitchType*/ 9, MVT::v4i32,// ->23571
+/* 23562*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23564*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NLZC_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 3
+ // Dst: (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+/* 23571*/ /*SwitchType*/ 9, MVT::v2i64,// ->23582
+/* 23573*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 23575*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NLZC_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 3
+ // Dst: (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
+/* 23582*/ 0, // EndSwitchType
+/* 23583*/ 0, /*End of Scope*/
+/* 23584*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(MipsISD::Ext),// ->23751
+/* 23588*/ OPC_RecordChild0, // #0 = $rs
+/* 23589*/ OPC_RecordChild1, // #1 = $pos
+/* 23590*/ OPC_MoveChild1,
+/* 23591*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 23594*/ OPC_Scope, 71, /*->23667*/ // 4 children in Scope
+/* 23596*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 23598*/ OPC_MoveParent,
+/* 23599*/ OPC_RecordChild2, // #2 = $size
+/* 23600*/ OPC_MoveChild2,
+/* 23601*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 23604*/ OPC_Scope, 39, /*->23645*/ // 2 children in Scope
+/* 23606*/ OPC_CheckPredicate, 44, // Predicate_immZExt5Plus1
+/* 23608*/ OPC_MoveParent,
+/* 23609*/ OPC_SwitchType /*2 cases */, 15, MVT::i32,// ->23627
+/* 23612*/ OPC_CheckPatternPredicate, 53, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 23614*/ OPC_EmitConvertToTarget, 1,
+/* 23616*/ OPC_EmitConvertToTarget, 2,
+/* 23618*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXT), 0,
+ MVT::i32, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsExt:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$pos, (imm:{ *:[i32] })<<P:Predicate_immZExt5Plus1>>:$size) - Complexity = 11
+ // Dst: (EXT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size)
+/* 23627*/ /*SwitchType*/ 15, MVT::i64,// ->23644
+/* 23629*/ OPC_CheckPatternPredicate, 54, // (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 23631*/ OPC_EmitConvertToTarget, 1,
+/* 23633*/ OPC_EmitConvertToTarget, 2,
+/* 23635*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DEXT), 0,
+ MVT::i64, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsExt:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$pos, (imm:{ *:[i32] })<<P:Predicate_immZExt5Plus1>>:$size) - Complexity = 11
+ // Dst: (DEXT:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size)
+/* 23644*/ 0, // EndSwitchType
+/* 23645*/ /*Scope*/ 20, /*->23666*/
+/* 23646*/ OPC_CheckPredicate, 45, // Predicate_immZExt5Plus33
+/* 23648*/ OPC_MoveParent,
+/* 23649*/ OPC_CheckType, MVT::i64,
+/* 23651*/ OPC_CheckPatternPredicate, 54, // (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 23653*/ OPC_EmitConvertToTarget, 1,
+/* 23655*/ OPC_EmitConvertToTarget, 2,
+/* 23657*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DEXTM), 0,
+ MVT::i64, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsExt:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$pos, (imm:{ *:[i32] })<<P:Predicate_immZExt5Plus33>>:$size) - Complexity = 11
+ // Dst: (DEXTM:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size)
+/* 23666*/ 0, /*End of Scope*/
+/* 23667*/ /*Scope*/ 28, /*->23696*/
+/* 23668*/ OPC_CheckPredicate, 46, // Predicate_immZExt5Plus32
+/* 23670*/ OPC_MoveParent,
+/* 23671*/ OPC_RecordChild2, // #2 = $size
+/* 23672*/ OPC_MoveChild2,
+/* 23673*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 23676*/ OPC_CheckPredicate, 44, // Predicate_immZExt5Plus1
+/* 23678*/ OPC_MoveParent,
+/* 23679*/ OPC_CheckType, MVT::i64,
+/* 23681*/ OPC_CheckPatternPredicate, 54, // (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 23683*/ OPC_EmitConvertToTarget, 1,
+/* 23685*/ OPC_EmitConvertToTarget, 2,
+/* 23687*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DEXTU), 0,
+ MVT::i64, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsExt:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5Plus32>>:$pos, (imm:{ *:[i32] })<<P:Predicate_immZExt5Plus1>>:$size) - Complexity = 11
+ // Dst: (DEXTU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size)
+/* 23696*/ /*Scope*/ 28, /*->23725*/
+/* 23697*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 23699*/ OPC_MoveParent,
+/* 23700*/ OPC_RecordChild2, // #2 = $size
+/* 23701*/ OPC_MoveChild2,
+/* 23702*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 23705*/ OPC_CheckPredicate, 44, // Predicate_immZExt5Plus1
+/* 23707*/ OPC_MoveParent,
+/* 23708*/ OPC_CheckType, MVT::i32,
+/* 23710*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 23712*/ OPC_EmitConvertToTarget, 1,
+/* 23714*/ OPC_EmitConvertToTarget, 2,
+/* 23716*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXT_MM), 0,
+ MVT::i32, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsExt:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$pos, (imm:{ *:[i32] })<<P:Predicate_immZExt5Plus1>>:$size) - Complexity = 11
+ // Dst: (EXT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size)
+/* 23725*/ /*Scope*/ 24, /*->23750*/
+/* 23726*/ OPC_MoveParent,
+/* 23727*/ OPC_RecordChild2, // #2 = $size
+/* 23728*/ OPC_MoveChild2,
+/* 23729*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 23732*/ OPC_MoveParent,
+/* 23733*/ OPC_CheckType, MVT::i32,
+/* 23735*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 23737*/ OPC_EmitConvertToTarget, 1,
+/* 23739*/ OPC_EmitConvertToTarget, 2,
+/* 23741*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXT_MMR6), 0,
+ MVT::i32, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsExt:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size) - Complexity = 9
+ // Dst: (EXT_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size)
+/* 23750*/ 0, /*End of Scope*/
+/* 23751*/ /*SwitchOpcode*/ 120|128,35/*4600*/, TARGET_VAL(ISD::AND),// ->28355
+/* 23755*/ OPC_Scope, 22, /*->23779*/ // 18 children in Scope
+/* 23757*/ OPC_CheckAndImm, 127|128,1/*255*/,
+/* 23760*/ OPC_MoveChild0,
+/* 23761*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+/* 23764*/ OPC_RecordChild0, // #0 = $rs
+/* 23765*/ OPC_RecordChild1, // #1 = $rt
+/* 23766*/ OPC_MoveParent,
+/* 23767*/ OPC_CheckType, MVT::i64,
+/* 23769*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 23771*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BADDu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) - Complexity = 11
+ // Dst: (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 23779*/ /*Scope*/ 83|128,7/*979*/, /*->24760*/
+/* 23781*/ OPC_RecordChild0, // #0 = $rs
+/* 23782*/ OPC_Scope, 74|128,1/*202*/, /*->23987*/ // 2 children in Scope
+/* 23785*/ OPC_RecordChild1, // #1 = $imm16
+/* 23786*/ OPC_Scope, 124, /*->23912*/ // 3 children in Scope
+/* 23788*/ OPC_MoveChild1,
+/* 23789*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 23792*/ OPC_Scope, 39, /*->23833*/ // 5 children in Scope
+/* 23794*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 23796*/ OPC_MoveParent,
+/* 23797*/ OPC_SwitchType /*2 cases */, 15, MVT::i32,// ->23815
+/* 23800*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 23802*/ OPC_EmitConvertToTarget, 1,
+/* 23804*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 23807*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ANDi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm16))
+/* 23815*/ /*SwitchType*/ 15, MVT::i64,// ->23832
+/* 23817*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 23819*/ OPC_EmitConvertToTarget, 1,
+/* 23821*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 23824*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ANDi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 3,
+ // Src: (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (ANDi64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (LO16:{ *:[i64] } (imm:{ *:[i64] }):$imm16))
+/* 23832*/ 0, // EndSwitchType
+/* 23833*/ /*Scope*/ 17, /*->23851*/
+/* 23834*/ OPC_CheckPredicate, 47, // Predicate_immZExtAndi16
+/* 23836*/ OPC_MoveParent,
+/* 23837*/ OPC_CheckType, MVT::i32,
+/* 23839*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 23841*/ OPC_EmitConvertToTarget, 1,
+/* 23843*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ANDI16_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) - Complexity = 7
+ // Dst: (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
+/* 23851*/ /*Scope*/ 20, /*->23872*/
+/* 23852*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 23854*/ OPC_MoveParent,
+/* 23855*/ OPC_CheckType, MVT::i32,
+/* 23857*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 23859*/ OPC_EmitConvertToTarget, 1,
+/* 23861*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 23864*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ANDi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (and:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm) - Complexity = 7
+ // Dst: (ANDi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))
+/* 23872*/ /*Scope*/ 17, /*->23890*/
+/* 23873*/ OPC_CheckPredicate, 47, // Predicate_immZExtAndi16
+/* 23875*/ OPC_MoveParent,
+/* 23876*/ OPC_CheckType, MVT::i32,
+/* 23878*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 23880*/ OPC_EmitConvertToTarget, 1,
+/* 23882*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ANDI16_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) - Complexity = 7
+ // Dst: (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
+/* 23890*/ /*Scope*/ 20, /*->23911*/
+/* 23891*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 23893*/ OPC_MoveParent,
+/* 23894*/ OPC_CheckType, MVT::i32,
+/* 23896*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 23898*/ OPC_EmitConvertToTarget, 1,
+/* 23900*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 23903*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ANDI_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (and:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm) - Complexity = 7
+ // Dst: (ANDI_MMR6:{ *:[i32] } GPR32:{ *:[i32] }:$src, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))
+/* 23911*/ 0, /*End of Scope*/
+/* 23912*/ /*Scope*/ 60, /*->23973*/
+/* 23913*/ OPC_CheckType, MVT::i32,
+/* 23915*/ OPC_Scope, 10, /*->23927*/ // 4 children in Scope
+/* 23917*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 23919*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 23927*/ /*Scope*/ 10, /*->23938*/
+/* 23928*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 23930*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AndRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) - Complexity = 3
+ // Dst: (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+/* 23938*/ /*Scope*/ 22, /*->23961*/
+/* 23939*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 23941*/ OPC_Scope, 8, /*->23951*/ // 2 children in Scope
+/* 23943*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND16_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+/* 23951*/ /*Scope*/ 8, /*->23960*/
+/* 23952*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 23960*/ 0, /*End of Scope*/
+/* 23961*/ /*Scope*/ 10, /*->23972*/
+/* 23962*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 23964*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 23972*/ 0, /*End of Scope*/
+/* 23973*/ /*Scope*/ 12, /*->23986*/
+/* 23974*/ OPC_CheckType, MVT::i64,
+/* 23976*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 23978*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 23986*/ 0, /*End of Scope*/
+/* 23987*/ /*Scope*/ 2|128,6/*770*/, /*->24759*/
+/* 23989*/ OPC_MoveChild1,
+/* 23990*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 23993*/ OPC_MoveChild0,
+/* 23994*/ OPC_SwitchOpcode /*2 cases */, 125|128,2/*381*/, TARGET_VAL(ISD::SHL),// ->24380
+/* 23999*/ OPC_MoveChild0,
+/* 24000*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24003*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 24005*/ OPC_MoveParent,
+/* 24006*/ OPC_MoveChild1,
+/* 24007*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 24010*/ OPC_Scope, 54|128,1/*182*/, /*->24195*/ // 2 children in Scope
+/* 24013*/ OPC_RecordChild0, // #1 = $wt
+/* 24014*/ OPC_MoveChild1,
+/* 24015*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24018*/ OPC_MoveChild0,
+/* 24019*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24022*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24024*/ OPC_CheckType, MVT::i32,
+/* 24026*/ OPC_MoveParent,
+/* 24027*/ OPC_MoveChild1,
+/* 24028*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24031*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24033*/ OPC_CheckType, MVT::i32,
+/* 24035*/ OPC_MoveParent,
+/* 24036*/ OPC_MoveChild2,
+/* 24037*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24040*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24042*/ OPC_CheckType, MVT::i32,
+/* 24044*/ OPC_MoveParent,
+/* 24045*/ OPC_MoveChild3,
+/* 24046*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24049*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24051*/ OPC_CheckType, MVT::i32,
+/* 24053*/ OPC_MoveParent,
+/* 24054*/ OPC_MoveChild4,
+/* 24055*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24058*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24060*/ OPC_CheckType, MVT::i32,
+/* 24062*/ OPC_MoveParent,
+/* 24063*/ OPC_MoveChild5,
+/* 24064*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24067*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24069*/ OPC_CheckType, MVT::i32,
+/* 24071*/ OPC_MoveParent,
+/* 24072*/ OPC_MoveChild6,
+/* 24073*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24076*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24078*/ OPC_CheckType, MVT::i32,
+/* 24080*/ OPC_MoveParent,
+/* 24081*/ OPC_MoveChild7,
+/* 24082*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24085*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24087*/ OPC_CheckType, MVT::i32,
+/* 24089*/ OPC_MoveParent,
+/* 24090*/ OPC_MoveChild, 8,
+/* 24092*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24095*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24097*/ OPC_CheckType, MVT::i32,
+/* 24099*/ OPC_MoveParent,
+/* 24100*/ OPC_MoveChild, 9,
+/* 24102*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24105*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24107*/ OPC_CheckType, MVT::i32,
+/* 24109*/ OPC_MoveParent,
+/* 24110*/ OPC_MoveChild, 10,
+/* 24112*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24115*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24117*/ OPC_CheckType, MVT::i32,
+/* 24119*/ OPC_MoveParent,
+/* 24120*/ OPC_MoveChild, 11,
+/* 24122*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24125*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24127*/ OPC_CheckType, MVT::i32,
+/* 24129*/ OPC_MoveParent,
+/* 24130*/ OPC_MoveChild, 12,
+/* 24132*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24135*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24137*/ OPC_CheckType, MVT::i32,
+/* 24139*/ OPC_MoveParent,
+/* 24140*/ OPC_MoveChild, 13,
+/* 24142*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24145*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24147*/ OPC_CheckType, MVT::i32,
+/* 24149*/ OPC_MoveParent,
+/* 24150*/ OPC_MoveChild, 14,
+/* 24152*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24155*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24157*/ OPC_CheckType, MVT::i32,
+/* 24159*/ OPC_MoveParent,
+/* 24160*/ OPC_MoveChild, 15,
+/* 24162*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24165*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24167*/ OPC_CheckType, MVT::i32,
+/* 24169*/ OPC_MoveParent,
+/* 24170*/ OPC_MoveParent,
+/* 24171*/ OPC_CheckType, MVT::v16i8,
+/* 24173*/ OPC_MoveParent,
+/* 24174*/ OPC_MoveParent,
+/* 24175*/ OPC_MoveChild1,
+/* 24176*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24179*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 24181*/ OPC_MoveParent,
+/* 24182*/ OPC_MoveParent,
+/* 24183*/ OPC_CheckType, MVT::v16i8,
+/* 24185*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 24187*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))), (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>)) - Complexity = 87
+ // Dst: (BCLR_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 24195*/ /*Scope*/ 54|128,1/*182*/, /*->24379*/
+/* 24197*/ OPC_MoveChild0,
+/* 24198*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24201*/ OPC_MoveChild0,
+/* 24202*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24205*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24207*/ OPC_CheckType, MVT::i32,
+/* 24209*/ OPC_MoveParent,
+/* 24210*/ OPC_MoveChild1,
+/* 24211*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24214*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24216*/ OPC_CheckType, MVT::i32,
+/* 24218*/ OPC_MoveParent,
+/* 24219*/ OPC_MoveChild2,
+/* 24220*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24223*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24225*/ OPC_CheckType, MVT::i32,
+/* 24227*/ OPC_MoveParent,
+/* 24228*/ OPC_MoveChild3,
+/* 24229*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24232*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24234*/ OPC_CheckType, MVT::i32,
+/* 24236*/ OPC_MoveParent,
+/* 24237*/ OPC_MoveChild4,
+/* 24238*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24241*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24243*/ OPC_CheckType, MVT::i32,
+/* 24245*/ OPC_MoveParent,
+/* 24246*/ OPC_MoveChild5,
+/* 24247*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24250*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24252*/ OPC_CheckType, MVT::i32,
+/* 24254*/ OPC_MoveParent,
+/* 24255*/ OPC_MoveChild6,
+/* 24256*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24259*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24261*/ OPC_CheckType, MVT::i32,
+/* 24263*/ OPC_MoveParent,
+/* 24264*/ OPC_MoveChild7,
+/* 24265*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24268*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24270*/ OPC_CheckType, MVT::i32,
+/* 24272*/ OPC_MoveParent,
+/* 24273*/ OPC_MoveChild, 8,
+/* 24275*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24278*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24280*/ OPC_CheckType, MVT::i32,
+/* 24282*/ OPC_MoveParent,
+/* 24283*/ OPC_MoveChild, 9,
+/* 24285*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24288*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24290*/ OPC_CheckType, MVT::i32,
+/* 24292*/ OPC_MoveParent,
+/* 24293*/ OPC_MoveChild, 10,
+/* 24295*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24298*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24300*/ OPC_CheckType, MVT::i32,
+/* 24302*/ OPC_MoveParent,
+/* 24303*/ OPC_MoveChild, 11,
+/* 24305*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24308*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24310*/ OPC_CheckType, MVT::i32,
+/* 24312*/ OPC_MoveParent,
+/* 24313*/ OPC_MoveChild, 12,
+/* 24315*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24318*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24320*/ OPC_CheckType, MVT::i32,
+/* 24322*/ OPC_MoveParent,
+/* 24323*/ OPC_MoveChild, 13,
+/* 24325*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24328*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24330*/ OPC_CheckType, MVT::i32,
+/* 24332*/ OPC_MoveParent,
+/* 24333*/ OPC_MoveChild, 14,
+/* 24335*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24338*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24340*/ OPC_CheckType, MVT::i32,
+/* 24342*/ OPC_MoveParent,
+/* 24343*/ OPC_MoveChild, 15,
+/* 24345*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24348*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24350*/ OPC_CheckType, MVT::i32,
+/* 24352*/ OPC_MoveParent,
+/* 24353*/ OPC_MoveParent,
+/* 24354*/ OPC_RecordChild1, // #1 = $wt
+/* 24355*/ OPC_CheckType, MVT::v16i8,
+/* 24357*/ OPC_MoveParent,
+/* 24358*/ OPC_MoveParent,
+/* 24359*/ OPC_MoveChild1,
+/* 24360*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24363*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 24365*/ OPC_MoveParent,
+/* 24366*/ OPC_MoveParent,
+/* 24367*/ OPC_CheckType, MVT::v16i8,
+/* 24369*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 24371*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)), (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>)) - Complexity = 87
+ // Dst: (BCLR_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 24379*/ 0, /*End of Scope*/
+/* 24380*/ /*SwitchOpcode*/ 118|128,2/*374*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->24758
+/* 24384*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 24386*/ OPC_MoveParent,
+/* 24387*/ OPC_MoveChild1,
+/* 24388*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 24391*/ OPC_MoveChild0,
+/* 24392*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24395*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 24397*/ OPC_MoveParent,
+/* 24398*/ OPC_MoveChild1,
+/* 24399*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 24402*/ OPC_Scope, 47|128,1/*175*/, /*->24580*/ // 2 children in Scope
+/* 24405*/ OPC_RecordChild0, // #1 = $wt
+/* 24406*/ OPC_MoveChild1,
+/* 24407*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24410*/ OPC_MoveChild0,
+/* 24411*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24414*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24416*/ OPC_CheckType, MVT::i32,
+/* 24418*/ OPC_MoveParent,
+/* 24419*/ OPC_MoveChild1,
+/* 24420*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24423*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24425*/ OPC_CheckType, MVT::i32,
+/* 24427*/ OPC_MoveParent,
+/* 24428*/ OPC_MoveChild2,
+/* 24429*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24432*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24434*/ OPC_CheckType, MVT::i32,
+/* 24436*/ OPC_MoveParent,
+/* 24437*/ OPC_MoveChild3,
+/* 24438*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24441*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24443*/ OPC_CheckType, MVT::i32,
+/* 24445*/ OPC_MoveParent,
+/* 24446*/ OPC_MoveChild4,
+/* 24447*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24450*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24452*/ OPC_CheckType, MVT::i32,
+/* 24454*/ OPC_MoveParent,
+/* 24455*/ OPC_MoveChild5,
+/* 24456*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24459*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24461*/ OPC_CheckType, MVT::i32,
+/* 24463*/ OPC_MoveParent,
+/* 24464*/ OPC_MoveChild6,
+/* 24465*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24468*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24470*/ OPC_CheckType, MVT::i32,
+/* 24472*/ OPC_MoveParent,
+/* 24473*/ OPC_MoveChild7,
+/* 24474*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24477*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24479*/ OPC_CheckType, MVT::i32,
+/* 24481*/ OPC_MoveParent,
+/* 24482*/ OPC_MoveChild, 8,
+/* 24484*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24487*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24489*/ OPC_CheckType, MVT::i32,
+/* 24491*/ OPC_MoveParent,
+/* 24492*/ OPC_MoveChild, 9,
+/* 24494*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24497*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24499*/ OPC_CheckType, MVT::i32,
+/* 24501*/ OPC_MoveParent,
+/* 24502*/ OPC_MoveChild, 10,
+/* 24504*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24507*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24509*/ OPC_CheckType, MVT::i32,
+/* 24511*/ OPC_MoveParent,
+/* 24512*/ OPC_MoveChild, 11,
+/* 24514*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24517*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24519*/ OPC_CheckType, MVT::i32,
+/* 24521*/ OPC_MoveParent,
+/* 24522*/ OPC_MoveChild, 12,
+/* 24524*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24527*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24529*/ OPC_CheckType, MVT::i32,
+/* 24531*/ OPC_MoveParent,
+/* 24532*/ OPC_MoveChild, 13,
+/* 24534*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24537*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24539*/ OPC_CheckType, MVT::i32,
+/* 24541*/ OPC_MoveParent,
+/* 24542*/ OPC_MoveChild, 14,
+/* 24544*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24547*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24549*/ OPC_CheckType, MVT::i32,
+/* 24551*/ OPC_MoveParent,
+/* 24552*/ OPC_MoveChild, 15,
+/* 24554*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24557*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24559*/ OPC_CheckType, MVT::i32,
+/* 24561*/ OPC_MoveParent,
+/* 24562*/ OPC_MoveParent,
+/* 24563*/ OPC_CheckType, MVT::v16i8,
+/* 24565*/ OPC_MoveParent,
+/* 24566*/ OPC_MoveParent,
+/* 24567*/ OPC_MoveParent,
+/* 24568*/ OPC_CheckType, MVT::v16i8,
+/* 24570*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 24572*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (xor:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))))) - Complexity = 87
+ // Dst: (BCLR_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 24580*/ /*Scope*/ 47|128,1/*175*/, /*->24757*/
+/* 24582*/ OPC_MoveChild0,
+/* 24583*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24586*/ OPC_MoveChild0,
+/* 24587*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24590*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24592*/ OPC_CheckType, MVT::i32,
+/* 24594*/ OPC_MoveParent,
+/* 24595*/ OPC_MoveChild1,
+/* 24596*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24599*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24601*/ OPC_CheckType, MVT::i32,
+/* 24603*/ OPC_MoveParent,
+/* 24604*/ OPC_MoveChild2,
+/* 24605*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24608*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24610*/ OPC_CheckType, MVT::i32,
+/* 24612*/ OPC_MoveParent,
+/* 24613*/ OPC_MoveChild3,
+/* 24614*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24617*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24619*/ OPC_CheckType, MVT::i32,
+/* 24621*/ OPC_MoveParent,
+/* 24622*/ OPC_MoveChild4,
+/* 24623*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24626*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24628*/ OPC_CheckType, MVT::i32,
+/* 24630*/ OPC_MoveParent,
+/* 24631*/ OPC_MoveChild5,
+/* 24632*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24635*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24637*/ OPC_CheckType, MVT::i32,
+/* 24639*/ OPC_MoveParent,
+/* 24640*/ OPC_MoveChild6,
+/* 24641*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24644*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24646*/ OPC_CheckType, MVT::i32,
+/* 24648*/ OPC_MoveParent,
+/* 24649*/ OPC_MoveChild7,
+/* 24650*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24653*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24655*/ OPC_CheckType, MVT::i32,
+/* 24657*/ OPC_MoveParent,
+/* 24658*/ OPC_MoveChild, 8,
+/* 24660*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24663*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24665*/ OPC_CheckType, MVT::i32,
+/* 24667*/ OPC_MoveParent,
+/* 24668*/ OPC_MoveChild, 9,
+/* 24670*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24673*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24675*/ OPC_CheckType, MVT::i32,
+/* 24677*/ OPC_MoveParent,
+/* 24678*/ OPC_MoveChild, 10,
+/* 24680*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24683*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24685*/ OPC_CheckType, MVT::i32,
+/* 24687*/ OPC_MoveParent,
+/* 24688*/ OPC_MoveChild, 11,
+/* 24690*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24693*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24695*/ OPC_CheckType, MVT::i32,
+/* 24697*/ OPC_MoveParent,
+/* 24698*/ OPC_MoveChild, 12,
+/* 24700*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24703*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24705*/ OPC_CheckType, MVT::i32,
+/* 24707*/ OPC_MoveParent,
+/* 24708*/ OPC_MoveChild, 13,
+/* 24710*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24713*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24715*/ OPC_CheckType, MVT::i32,
+/* 24717*/ OPC_MoveParent,
+/* 24718*/ OPC_MoveChild, 14,
+/* 24720*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24723*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24725*/ OPC_CheckType, MVT::i32,
+/* 24727*/ OPC_MoveParent,
+/* 24728*/ OPC_MoveChild, 15,
+/* 24730*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24733*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24735*/ OPC_CheckType, MVT::i32,
+/* 24737*/ OPC_MoveParent,
+/* 24738*/ OPC_MoveParent,
+/* 24739*/ OPC_RecordChild1, // #1 = $wt
+/* 24740*/ OPC_CheckType, MVT::v16i8,
+/* 24742*/ OPC_MoveParent,
+/* 24743*/ OPC_MoveParent,
+/* 24744*/ OPC_MoveParent,
+/* 24745*/ OPC_CheckType, MVT::v16i8,
+/* 24747*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 24749*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (xor:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)))) - Complexity = 87
+ // Dst: (BCLR_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 24757*/ 0, /*End of Scope*/
+/* 24758*/ 0, // EndSwitchOpcode
+/* 24759*/ 0, /*End of Scope*/
+/* 24760*/ /*Scope*/ 6|128,6/*774*/, /*->25536*/
+/* 24762*/ OPC_MoveChild0,
+/* 24763*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 24766*/ OPC_MoveChild0,
+/* 24767*/ OPC_SwitchOpcode /*2 cases */, 127|128,2/*383*/, TARGET_VAL(ISD::SHL),// ->25155
+/* 24772*/ OPC_MoveChild0,
+/* 24773*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24776*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 24778*/ OPC_MoveParent,
+/* 24779*/ OPC_MoveChild1,
+/* 24780*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 24783*/ OPC_Scope, 55|128,1/*183*/, /*->24969*/ // 2 children in Scope
+/* 24786*/ OPC_RecordChild0, // #0 = $wt
+/* 24787*/ OPC_MoveChild1,
+/* 24788*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24791*/ OPC_MoveChild0,
+/* 24792*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24795*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24797*/ OPC_CheckType, MVT::i32,
+/* 24799*/ OPC_MoveParent,
+/* 24800*/ OPC_MoveChild1,
+/* 24801*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24804*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24806*/ OPC_CheckType, MVT::i32,
+/* 24808*/ OPC_MoveParent,
+/* 24809*/ OPC_MoveChild2,
+/* 24810*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24813*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24815*/ OPC_CheckType, MVT::i32,
+/* 24817*/ OPC_MoveParent,
+/* 24818*/ OPC_MoveChild3,
+/* 24819*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24822*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24824*/ OPC_CheckType, MVT::i32,
+/* 24826*/ OPC_MoveParent,
+/* 24827*/ OPC_MoveChild4,
+/* 24828*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24831*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24833*/ OPC_CheckType, MVT::i32,
+/* 24835*/ OPC_MoveParent,
+/* 24836*/ OPC_MoveChild5,
+/* 24837*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24840*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24842*/ OPC_CheckType, MVT::i32,
+/* 24844*/ OPC_MoveParent,
+/* 24845*/ OPC_MoveChild6,
+/* 24846*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24849*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24851*/ OPC_CheckType, MVT::i32,
+/* 24853*/ OPC_MoveParent,
+/* 24854*/ OPC_MoveChild7,
+/* 24855*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24858*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24860*/ OPC_CheckType, MVT::i32,
+/* 24862*/ OPC_MoveParent,
+/* 24863*/ OPC_MoveChild, 8,
+/* 24865*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24868*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24870*/ OPC_CheckType, MVT::i32,
+/* 24872*/ OPC_MoveParent,
+/* 24873*/ OPC_MoveChild, 9,
+/* 24875*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24878*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24880*/ OPC_CheckType, MVT::i32,
+/* 24882*/ OPC_MoveParent,
+/* 24883*/ OPC_MoveChild, 10,
+/* 24885*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24888*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24890*/ OPC_CheckType, MVT::i32,
+/* 24892*/ OPC_MoveParent,
+/* 24893*/ OPC_MoveChild, 11,
+/* 24895*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24898*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24900*/ OPC_CheckType, MVT::i32,
+/* 24902*/ OPC_MoveParent,
+/* 24903*/ OPC_MoveChild, 12,
+/* 24905*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24908*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24910*/ OPC_CheckType, MVT::i32,
+/* 24912*/ OPC_MoveParent,
+/* 24913*/ OPC_MoveChild, 13,
+/* 24915*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24918*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24920*/ OPC_CheckType, MVT::i32,
+/* 24922*/ OPC_MoveParent,
+/* 24923*/ OPC_MoveChild, 14,
+/* 24925*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24928*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24930*/ OPC_CheckType, MVT::i32,
+/* 24932*/ OPC_MoveParent,
+/* 24933*/ OPC_MoveChild, 15,
+/* 24935*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24938*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24940*/ OPC_CheckType, MVT::i32,
+/* 24942*/ OPC_MoveParent,
+/* 24943*/ OPC_MoveParent,
+/* 24944*/ OPC_CheckType, MVT::v16i8,
+/* 24946*/ OPC_MoveParent,
+/* 24947*/ OPC_MoveParent,
+/* 24948*/ OPC_MoveChild1,
+/* 24949*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24952*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 24954*/ OPC_MoveParent,
+/* 24955*/ OPC_MoveParent,
+/* 24956*/ OPC_RecordChild1, // #1 = $ws
+/* 24957*/ OPC_CheckType, MVT::v16i8,
+/* 24959*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 24961*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v16i8] } (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))), (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>), v16i8:{ *:[v16i8] }:$ws) - Complexity = 87
+ // Dst: (BCLR_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 24969*/ /*Scope*/ 55|128,1/*183*/, /*->25154*/
+/* 24971*/ OPC_MoveChild0,
+/* 24972*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 24975*/ OPC_MoveChild0,
+/* 24976*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24979*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24981*/ OPC_CheckType, MVT::i32,
+/* 24983*/ OPC_MoveParent,
+/* 24984*/ OPC_MoveChild1,
+/* 24985*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24988*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24990*/ OPC_CheckType, MVT::i32,
+/* 24992*/ OPC_MoveParent,
+/* 24993*/ OPC_MoveChild2,
+/* 24994*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 24997*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 24999*/ OPC_CheckType, MVT::i32,
+/* 25001*/ OPC_MoveParent,
+/* 25002*/ OPC_MoveChild3,
+/* 25003*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25006*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25008*/ OPC_CheckType, MVT::i32,
+/* 25010*/ OPC_MoveParent,
+/* 25011*/ OPC_MoveChild4,
+/* 25012*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25015*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25017*/ OPC_CheckType, MVT::i32,
+/* 25019*/ OPC_MoveParent,
+/* 25020*/ OPC_MoveChild5,
+/* 25021*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25024*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25026*/ OPC_CheckType, MVT::i32,
+/* 25028*/ OPC_MoveParent,
+/* 25029*/ OPC_MoveChild6,
+/* 25030*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25033*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25035*/ OPC_CheckType, MVT::i32,
+/* 25037*/ OPC_MoveParent,
+/* 25038*/ OPC_MoveChild7,
+/* 25039*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25042*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25044*/ OPC_CheckType, MVT::i32,
+/* 25046*/ OPC_MoveParent,
+/* 25047*/ OPC_MoveChild, 8,
+/* 25049*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25052*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25054*/ OPC_CheckType, MVT::i32,
+/* 25056*/ OPC_MoveParent,
+/* 25057*/ OPC_MoveChild, 9,
+/* 25059*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25062*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25064*/ OPC_CheckType, MVT::i32,
+/* 25066*/ OPC_MoveParent,
+/* 25067*/ OPC_MoveChild, 10,
+/* 25069*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25072*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25074*/ OPC_CheckType, MVT::i32,
+/* 25076*/ OPC_MoveParent,
+/* 25077*/ OPC_MoveChild, 11,
+/* 25079*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25082*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25084*/ OPC_CheckType, MVT::i32,
+/* 25086*/ OPC_MoveParent,
+/* 25087*/ OPC_MoveChild, 12,
+/* 25089*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25092*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25094*/ OPC_CheckType, MVT::i32,
+/* 25096*/ OPC_MoveParent,
+/* 25097*/ OPC_MoveChild, 13,
+/* 25099*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25102*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25104*/ OPC_CheckType, MVT::i32,
+/* 25106*/ OPC_MoveParent,
+/* 25107*/ OPC_MoveChild, 14,
+/* 25109*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25112*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25114*/ OPC_CheckType, MVT::i32,
+/* 25116*/ OPC_MoveParent,
+/* 25117*/ OPC_MoveChild, 15,
+/* 25119*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25122*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25124*/ OPC_CheckType, MVT::i32,
+/* 25126*/ OPC_MoveParent,
+/* 25127*/ OPC_MoveParent,
+/* 25128*/ OPC_RecordChild1, // #0 = $wt
+/* 25129*/ OPC_CheckType, MVT::v16i8,
+/* 25131*/ OPC_MoveParent,
+/* 25132*/ OPC_MoveParent,
+/* 25133*/ OPC_MoveChild1,
+/* 25134*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25137*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 25139*/ OPC_MoveParent,
+/* 25140*/ OPC_MoveParent,
+/* 25141*/ OPC_RecordChild1, // #1 = $ws
+/* 25142*/ OPC_CheckType, MVT::v16i8,
+/* 25144*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 25146*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v16i8] } (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)), (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>), v16i8:{ *:[v16i8] }:$ws) - Complexity = 87
+ // Dst: (BCLR_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 25154*/ 0, /*End of Scope*/
+/* 25155*/ /*SwitchOpcode*/ 120|128,2/*376*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->25535
+/* 25159*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 25161*/ OPC_MoveParent,
+/* 25162*/ OPC_MoveChild1,
+/* 25163*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 25166*/ OPC_MoveChild0,
+/* 25167*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25170*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 25172*/ OPC_MoveParent,
+/* 25173*/ OPC_MoveChild1,
+/* 25174*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 25177*/ OPC_Scope, 48|128,1/*176*/, /*->25356*/ // 2 children in Scope
+/* 25180*/ OPC_RecordChild0, // #0 = $wt
+/* 25181*/ OPC_MoveChild1,
+/* 25182*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25185*/ OPC_MoveChild0,
+/* 25186*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25189*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25191*/ OPC_CheckType, MVT::i32,
+/* 25193*/ OPC_MoveParent,
+/* 25194*/ OPC_MoveChild1,
+/* 25195*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25198*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25200*/ OPC_CheckType, MVT::i32,
+/* 25202*/ OPC_MoveParent,
+/* 25203*/ OPC_MoveChild2,
+/* 25204*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25207*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25209*/ OPC_CheckType, MVT::i32,
+/* 25211*/ OPC_MoveParent,
+/* 25212*/ OPC_MoveChild3,
+/* 25213*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25216*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25218*/ OPC_CheckType, MVT::i32,
+/* 25220*/ OPC_MoveParent,
+/* 25221*/ OPC_MoveChild4,
+/* 25222*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25225*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25227*/ OPC_CheckType, MVT::i32,
+/* 25229*/ OPC_MoveParent,
+/* 25230*/ OPC_MoveChild5,
+/* 25231*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25234*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25236*/ OPC_CheckType, MVT::i32,
+/* 25238*/ OPC_MoveParent,
+/* 25239*/ OPC_MoveChild6,
+/* 25240*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25243*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25245*/ OPC_CheckType, MVT::i32,
+/* 25247*/ OPC_MoveParent,
+/* 25248*/ OPC_MoveChild7,
+/* 25249*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25252*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25254*/ OPC_CheckType, MVT::i32,
+/* 25256*/ OPC_MoveParent,
+/* 25257*/ OPC_MoveChild, 8,
+/* 25259*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25262*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25264*/ OPC_CheckType, MVT::i32,
+/* 25266*/ OPC_MoveParent,
+/* 25267*/ OPC_MoveChild, 9,
+/* 25269*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25272*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25274*/ OPC_CheckType, MVT::i32,
+/* 25276*/ OPC_MoveParent,
+/* 25277*/ OPC_MoveChild, 10,
+/* 25279*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25282*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25284*/ OPC_CheckType, MVT::i32,
+/* 25286*/ OPC_MoveParent,
+/* 25287*/ OPC_MoveChild, 11,
+/* 25289*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25292*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25294*/ OPC_CheckType, MVT::i32,
+/* 25296*/ OPC_MoveParent,
+/* 25297*/ OPC_MoveChild, 12,
+/* 25299*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25302*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25304*/ OPC_CheckType, MVT::i32,
+/* 25306*/ OPC_MoveParent,
+/* 25307*/ OPC_MoveChild, 13,
+/* 25309*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25312*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25314*/ OPC_CheckType, MVT::i32,
+/* 25316*/ OPC_MoveParent,
+/* 25317*/ OPC_MoveChild, 14,
+/* 25319*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25322*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25324*/ OPC_CheckType, MVT::i32,
+/* 25326*/ OPC_MoveParent,
+/* 25327*/ OPC_MoveChild, 15,
+/* 25329*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25332*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25334*/ OPC_CheckType, MVT::i32,
+/* 25336*/ OPC_MoveParent,
+/* 25337*/ OPC_MoveParent,
+/* 25338*/ OPC_CheckType, MVT::v16i8,
+/* 25340*/ OPC_MoveParent,
+/* 25341*/ OPC_MoveParent,
+/* 25342*/ OPC_MoveParent,
+/* 25343*/ OPC_RecordChild1, // #1 = $ws
+/* 25344*/ OPC_CheckType, MVT::v16i8,
+/* 25346*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 25348*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v16i8] } (xor:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))), v16i8:{ *:[v16i8] }:$ws) - Complexity = 87
+ // Dst: (BCLR_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 25356*/ /*Scope*/ 48|128,1/*176*/, /*->25534*/
+/* 25358*/ OPC_MoveChild0,
+/* 25359*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25362*/ OPC_MoveChild0,
+/* 25363*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25366*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25368*/ OPC_CheckType, MVT::i32,
+/* 25370*/ OPC_MoveParent,
+/* 25371*/ OPC_MoveChild1,
+/* 25372*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25375*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25377*/ OPC_CheckType, MVT::i32,
+/* 25379*/ OPC_MoveParent,
+/* 25380*/ OPC_MoveChild2,
+/* 25381*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25384*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25386*/ OPC_CheckType, MVT::i32,
+/* 25388*/ OPC_MoveParent,
+/* 25389*/ OPC_MoveChild3,
+/* 25390*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25393*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25395*/ OPC_CheckType, MVT::i32,
+/* 25397*/ OPC_MoveParent,
+/* 25398*/ OPC_MoveChild4,
+/* 25399*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25402*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25404*/ OPC_CheckType, MVT::i32,
+/* 25406*/ OPC_MoveParent,
+/* 25407*/ OPC_MoveChild5,
+/* 25408*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25411*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25413*/ OPC_CheckType, MVT::i32,
+/* 25415*/ OPC_MoveParent,
+/* 25416*/ OPC_MoveChild6,
+/* 25417*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25420*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25422*/ OPC_CheckType, MVT::i32,
+/* 25424*/ OPC_MoveParent,
+/* 25425*/ OPC_MoveChild7,
+/* 25426*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25429*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25431*/ OPC_CheckType, MVT::i32,
+/* 25433*/ OPC_MoveParent,
+/* 25434*/ OPC_MoveChild, 8,
+/* 25436*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25439*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25441*/ OPC_CheckType, MVT::i32,
+/* 25443*/ OPC_MoveParent,
+/* 25444*/ OPC_MoveChild, 9,
+/* 25446*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25449*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25451*/ OPC_CheckType, MVT::i32,
+/* 25453*/ OPC_MoveParent,
+/* 25454*/ OPC_MoveChild, 10,
+/* 25456*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25459*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25461*/ OPC_CheckType, MVT::i32,
+/* 25463*/ OPC_MoveParent,
+/* 25464*/ OPC_MoveChild, 11,
+/* 25466*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25469*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25471*/ OPC_CheckType, MVT::i32,
+/* 25473*/ OPC_MoveParent,
+/* 25474*/ OPC_MoveChild, 12,
+/* 25476*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25479*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25481*/ OPC_CheckType, MVT::i32,
+/* 25483*/ OPC_MoveParent,
+/* 25484*/ OPC_MoveChild, 13,
+/* 25486*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25489*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25491*/ OPC_CheckType, MVT::i32,
+/* 25493*/ OPC_MoveParent,
+/* 25494*/ OPC_MoveChild, 14,
+/* 25496*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25499*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25501*/ OPC_CheckType, MVT::i32,
+/* 25503*/ OPC_MoveParent,
+/* 25504*/ OPC_MoveChild, 15,
+/* 25506*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25509*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 25511*/ OPC_CheckType, MVT::i32,
+/* 25513*/ OPC_MoveParent,
+/* 25514*/ OPC_MoveParent,
+/* 25515*/ OPC_RecordChild1, // #0 = $wt
+/* 25516*/ OPC_CheckType, MVT::v16i8,
+/* 25518*/ OPC_MoveParent,
+/* 25519*/ OPC_MoveParent,
+/* 25520*/ OPC_MoveParent,
+/* 25521*/ OPC_RecordChild1, // #1 = $ws
+/* 25522*/ OPC_CheckType, MVT::v16i8,
+/* 25524*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 25526*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v16i8] } (xor:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))), v16i8:{ *:[v16i8] }:$ws) - Complexity = 87
+ // Dst: (BCLR_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 25534*/ 0, /*End of Scope*/
+/* 25535*/ 0, // EndSwitchOpcode
+/* 25536*/ /*Scope*/ 63|128,3/*447*/, /*->25985*/
+/* 25538*/ OPC_RecordChild0, // #0 = $ws
+/* 25539*/ OPC_MoveChild1,
+/* 25540*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 25543*/ OPC_MoveChild0,
+/* 25544*/ OPC_SwitchOpcode /*2 cases */, 91|128,1/*219*/, TARGET_VAL(ISD::SHL),// ->25768
+/* 25549*/ OPC_MoveChild0,
+/* 25550*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25553*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 25555*/ OPC_MoveParent,
+/* 25556*/ OPC_MoveChild1,
+/* 25557*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 25560*/ OPC_Scope, 102, /*->25664*/ // 2 children in Scope
+/* 25562*/ OPC_RecordChild0, // #1 = $wt
+/* 25563*/ OPC_MoveChild1,
+/* 25564*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25567*/ OPC_MoveChild0,
+/* 25568*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25571*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25573*/ OPC_CheckType, MVT::i32,
+/* 25575*/ OPC_MoveParent,
+/* 25576*/ OPC_MoveChild1,
+/* 25577*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25580*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25582*/ OPC_CheckType, MVT::i32,
+/* 25584*/ OPC_MoveParent,
+/* 25585*/ OPC_MoveChild2,
+/* 25586*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25589*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25591*/ OPC_CheckType, MVT::i32,
+/* 25593*/ OPC_MoveParent,
+/* 25594*/ OPC_MoveChild3,
+/* 25595*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25598*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25600*/ OPC_CheckType, MVT::i32,
+/* 25602*/ OPC_MoveParent,
+/* 25603*/ OPC_MoveChild4,
+/* 25604*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25607*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25609*/ OPC_CheckType, MVT::i32,
+/* 25611*/ OPC_MoveParent,
+/* 25612*/ OPC_MoveChild5,
+/* 25613*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25616*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25618*/ OPC_CheckType, MVT::i32,
+/* 25620*/ OPC_MoveParent,
+/* 25621*/ OPC_MoveChild6,
+/* 25622*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25625*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25627*/ OPC_CheckType, MVT::i32,
+/* 25629*/ OPC_MoveParent,
+/* 25630*/ OPC_MoveChild7,
+/* 25631*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25634*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25636*/ OPC_CheckType, MVT::i32,
+/* 25638*/ OPC_MoveParent,
+/* 25639*/ OPC_MoveParent,
+/* 25640*/ OPC_CheckType, MVT::v8i16,
+/* 25642*/ OPC_MoveParent,
+/* 25643*/ OPC_MoveParent,
+/* 25644*/ OPC_MoveChild1,
+/* 25645*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25648*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 25650*/ OPC_MoveParent,
+/* 25651*/ OPC_MoveParent,
+/* 25652*/ OPC_CheckType, MVT::v8i16,
+/* 25654*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 25656*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))), (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>)) - Complexity = 55
+ // Dst: (BCLR_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 25664*/ /*Scope*/ 102, /*->25767*/
+/* 25665*/ OPC_MoveChild0,
+/* 25666*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25669*/ OPC_MoveChild0,
+/* 25670*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25673*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25675*/ OPC_CheckType, MVT::i32,
+/* 25677*/ OPC_MoveParent,
+/* 25678*/ OPC_MoveChild1,
+/* 25679*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25682*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25684*/ OPC_CheckType, MVT::i32,
+/* 25686*/ OPC_MoveParent,
+/* 25687*/ OPC_MoveChild2,
+/* 25688*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25691*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25693*/ OPC_CheckType, MVT::i32,
+/* 25695*/ OPC_MoveParent,
+/* 25696*/ OPC_MoveChild3,
+/* 25697*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25700*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25702*/ OPC_CheckType, MVT::i32,
+/* 25704*/ OPC_MoveParent,
+/* 25705*/ OPC_MoveChild4,
+/* 25706*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25709*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25711*/ OPC_CheckType, MVT::i32,
+/* 25713*/ OPC_MoveParent,
+/* 25714*/ OPC_MoveChild5,
+/* 25715*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25718*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25720*/ OPC_CheckType, MVT::i32,
+/* 25722*/ OPC_MoveParent,
+/* 25723*/ OPC_MoveChild6,
+/* 25724*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25727*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25729*/ OPC_CheckType, MVT::i32,
+/* 25731*/ OPC_MoveParent,
+/* 25732*/ OPC_MoveChild7,
+/* 25733*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25736*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25738*/ OPC_CheckType, MVT::i32,
+/* 25740*/ OPC_MoveParent,
+/* 25741*/ OPC_MoveParent,
+/* 25742*/ OPC_RecordChild1, // #1 = $wt
+/* 25743*/ OPC_CheckType, MVT::v8i16,
+/* 25745*/ OPC_MoveParent,
+/* 25746*/ OPC_MoveParent,
+/* 25747*/ OPC_MoveChild1,
+/* 25748*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25751*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 25753*/ OPC_MoveParent,
+/* 25754*/ OPC_MoveParent,
+/* 25755*/ OPC_CheckType, MVT::v8i16,
+/* 25757*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 25759*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)), (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>)) - Complexity = 55
+ // Dst: (BCLR_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 25767*/ 0, /*End of Scope*/
+/* 25768*/ /*SwitchOpcode*/ 84|128,1/*212*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->25984
+/* 25772*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 25774*/ OPC_MoveParent,
+/* 25775*/ OPC_MoveChild1,
+/* 25776*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 25779*/ OPC_MoveChild0,
+/* 25780*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25783*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 25785*/ OPC_MoveParent,
+/* 25786*/ OPC_MoveChild1,
+/* 25787*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 25790*/ OPC_Scope, 95, /*->25887*/ // 2 children in Scope
+/* 25792*/ OPC_RecordChild0, // #1 = $wt
+/* 25793*/ OPC_MoveChild1,
+/* 25794*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25797*/ OPC_MoveChild0,
+/* 25798*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25801*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25803*/ OPC_CheckType, MVT::i32,
+/* 25805*/ OPC_MoveParent,
+/* 25806*/ OPC_MoveChild1,
+/* 25807*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25810*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25812*/ OPC_CheckType, MVT::i32,
+/* 25814*/ OPC_MoveParent,
+/* 25815*/ OPC_MoveChild2,
+/* 25816*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25819*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25821*/ OPC_CheckType, MVT::i32,
+/* 25823*/ OPC_MoveParent,
+/* 25824*/ OPC_MoveChild3,
+/* 25825*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25828*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25830*/ OPC_CheckType, MVT::i32,
+/* 25832*/ OPC_MoveParent,
+/* 25833*/ OPC_MoveChild4,
+/* 25834*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25837*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25839*/ OPC_CheckType, MVT::i32,
+/* 25841*/ OPC_MoveParent,
+/* 25842*/ OPC_MoveChild5,
+/* 25843*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25846*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25848*/ OPC_CheckType, MVT::i32,
+/* 25850*/ OPC_MoveParent,
+/* 25851*/ OPC_MoveChild6,
+/* 25852*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25855*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25857*/ OPC_CheckType, MVT::i32,
+/* 25859*/ OPC_MoveParent,
+/* 25860*/ OPC_MoveChild7,
+/* 25861*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25864*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25866*/ OPC_CheckType, MVT::i32,
+/* 25868*/ OPC_MoveParent,
+/* 25869*/ OPC_MoveParent,
+/* 25870*/ OPC_CheckType, MVT::v8i16,
+/* 25872*/ OPC_MoveParent,
+/* 25873*/ OPC_MoveParent,
+/* 25874*/ OPC_MoveParent,
+/* 25875*/ OPC_CheckType, MVT::v8i16,
+/* 25877*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 25879*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (xor:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))))) - Complexity = 55
+ // Dst: (BCLR_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 25887*/ /*Scope*/ 95, /*->25983*/
+/* 25888*/ OPC_MoveChild0,
+/* 25889*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 25892*/ OPC_MoveChild0,
+/* 25893*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25896*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25898*/ OPC_CheckType, MVT::i32,
+/* 25900*/ OPC_MoveParent,
+/* 25901*/ OPC_MoveChild1,
+/* 25902*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25905*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25907*/ OPC_CheckType, MVT::i32,
+/* 25909*/ OPC_MoveParent,
+/* 25910*/ OPC_MoveChild2,
+/* 25911*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25914*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25916*/ OPC_CheckType, MVT::i32,
+/* 25918*/ OPC_MoveParent,
+/* 25919*/ OPC_MoveChild3,
+/* 25920*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25923*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25925*/ OPC_CheckType, MVT::i32,
+/* 25927*/ OPC_MoveParent,
+/* 25928*/ OPC_MoveChild4,
+/* 25929*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25932*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25934*/ OPC_CheckType, MVT::i32,
+/* 25936*/ OPC_MoveParent,
+/* 25937*/ OPC_MoveChild5,
+/* 25938*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25941*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25943*/ OPC_CheckType, MVT::i32,
+/* 25945*/ OPC_MoveParent,
+/* 25946*/ OPC_MoveChild6,
+/* 25947*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25950*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25952*/ OPC_CheckType, MVT::i32,
+/* 25954*/ OPC_MoveParent,
+/* 25955*/ OPC_MoveChild7,
+/* 25956*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 25959*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 25961*/ OPC_CheckType, MVT::i32,
+/* 25963*/ OPC_MoveParent,
+/* 25964*/ OPC_MoveParent,
+/* 25965*/ OPC_RecordChild1, // #1 = $wt
+/* 25966*/ OPC_CheckType, MVT::v8i16,
+/* 25968*/ OPC_MoveParent,
+/* 25969*/ OPC_MoveParent,
+/* 25970*/ OPC_MoveParent,
+/* 25971*/ OPC_CheckType, MVT::v8i16,
+/* 25973*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 25975*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (xor:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)))) - Complexity = 55
+ // Dst: (BCLR_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 25983*/ 0, /*End of Scope*/
+/* 25984*/ 0, // EndSwitchOpcode
+/* 25985*/ /*Scope*/ 66|128,3/*450*/, /*->26437*/
+/* 25987*/ OPC_MoveChild0,
+/* 25988*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 25991*/ OPC_MoveChild0,
+/* 25992*/ OPC_SwitchOpcode /*2 cases */, 93|128,1/*221*/, TARGET_VAL(ISD::SHL),// ->26218
+/* 25997*/ OPC_MoveChild0,
+/* 25998*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26001*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 26003*/ OPC_MoveParent,
+/* 26004*/ OPC_MoveChild1,
+/* 26005*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 26008*/ OPC_Scope, 103, /*->26113*/ // 2 children in Scope
+/* 26010*/ OPC_RecordChild0, // #0 = $wt
+/* 26011*/ OPC_MoveChild1,
+/* 26012*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26015*/ OPC_MoveChild0,
+/* 26016*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26019*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26021*/ OPC_CheckType, MVT::i32,
+/* 26023*/ OPC_MoveParent,
+/* 26024*/ OPC_MoveChild1,
+/* 26025*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26028*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26030*/ OPC_CheckType, MVT::i32,
+/* 26032*/ OPC_MoveParent,
+/* 26033*/ OPC_MoveChild2,
+/* 26034*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26037*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26039*/ OPC_CheckType, MVT::i32,
+/* 26041*/ OPC_MoveParent,
+/* 26042*/ OPC_MoveChild3,
+/* 26043*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26046*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26048*/ OPC_CheckType, MVT::i32,
+/* 26050*/ OPC_MoveParent,
+/* 26051*/ OPC_MoveChild4,
+/* 26052*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26055*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26057*/ OPC_CheckType, MVT::i32,
+/* 26059*/ OPC_MoveParent,
+/* 26060*/ OPC_MoveChild5,
+/* 26061*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26064*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26066*/ OPC_CheckType, MVT::i32,
+/* 26068*/ OPC_MoveParent,
+/* 26069*/ OPC_MoveChild6,
+/* 26070*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26073*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26075*/ OPC_CheckType, MVT::i32,
+/* 26077*/ OPC_MoveParent,
+/* 26078*/ OPC_MoveChild7,
+/* 26079*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26082*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26084*/ OPC_CheckType, MVT::i32,
+/* 26086*/ OPC_MoveParent,
+/* 26087*/ OPC_MoveParent,
+/* 26088*/ OPC_CheckType, MVT::v8i16,
+/* 26090*/ OPC_MoveParent,
+/* 26091*/ OPC_MoveParent,
+/* 26092*/ OPC_MoveChild1,
+/* 26093*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26096*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26098*/ OPC_MoveParent,
+/* 26099*/ OPC_MoveParent,
+/* 26100*/ OPC_RecordChild1, // #1 = $ws
+/* 26101*/ OPC_CheckType, MVT::v8i16,
+/* 26103*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26105*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v8i16] } (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))), (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>), v8i16:{ *:[v8i16] }:$ws) - Complexity = 55
+ // Dst: (BCLR_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 26113*/ /*Scope*/ 103, /*->26217*/
+/* 26114*/ OPC_MoveChild0,
+/* 26115*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26118*/ OPC_MoveChild0,
+/* 26119*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26122*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26124*/ OPC_CheckType, MVT::i32,
+/* 26126*/ OPC_MoveParent,
+/* 26127*/ OPC_MoveChild1,
+/* 26128*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26131*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26133*/ OPC_CheckType, MVT::i32,
+/* 26135*/ OPC_MoveParent,
+/* 26136*/ OPC_MoveChild2,
+/* 26137*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26140*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26142*/ OPC_CheckType, MVT::i32,
+/* 26144*/ OPC_MoveParent,
+/* 26145*/ OPC_MoveChild3,
+/* 26146*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26149*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26151*/ OPC_CheckType, MVT::i32,
+/* 26153*/ OPC_MoveParent,
+/* 26154*/ OPC_MoveChild4,
+/* 26155*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26158*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26160*/ OPC_CheckType, MVT::i32,
+/* 26162*/ OPC_MoveParent,
+/* 26163*/ OPC_MoveChild5,
+/* 26164*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26167*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26169*/ OPC_CheckType, MVT::i32,
+/* 26171*/ OPC_MoveParent,
+/* 26172*/ OPC_MoveChild6,
+/* 26173*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26176*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26178*/ OPC_CheckType, MVT::i32,
+/* 26180*/ OPC_MoveParent,
+/* 26181*/ OPC_MoveChild7,
+/* 26182*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26185*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26187*/ OPC_CheckType, MVT::i32,
+/* 26189*/ OPC_MoveParent,
+/* 26190*/ OPC_MoveParent,
+/* 26191*/ OPC_RecordChild1, // #0 = $wt
+/* 26192*/ OPC_CheckType, MVT::v8i16,
+/* 26194*/ OPC_MoveParent,
+/* 26195*/ OPC_MoveParent,
+/* 26196*/ OPC_MoveChild1,
+/* 26197*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26200*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26202*/ OPC_MoveParent,
+/* 26203*/ OPC_MoveParent,
+/* 26204*/ OPC_RecordChild1, // #1 = $ws
+/* 26205*/ OPC_CheckType, MVT::v8i16,
+/* 26207*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26209*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v8i16] } (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)), (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>), v8i16:{ *:[v8i16] }:$ws) - Complexity = 55
+ // Dst: (BCLR_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 26217*/ 0, /*End of Scope*/
+/* 26218*/ /*SwitchOpcode*/ 86|128,1/*214*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->26436
+/* 26222*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26224*/ OPC_MoveParent,
+/* 26225*/ OPC_MoveChild1,
+/* 26226*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 26229*/ OPC_MoveChild0,
+/* 26230*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26233*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 26235*/ OPC_MoveParent,
+/* 26236*/ OPC_MoveChild1,
+/* 26237*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 26240*/ OPC_Scope, 96, /*->26338*/ // 2 children in Scope
+/* 26242*/ OPC_RecordChild0, // #0 = $wt
+/* 26243*/ OPC_MoveChild1,
+/* 26244*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26247*/ OPC_MoveChild0,
+/* 26248*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26251*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26253*/ OPC_CheckType, MVT::i32,
+/* 26255*/ OPC_MoveParent,
+/* 26256*/ OPC_MoveChild1,
+/* 26257*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26260*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26262*/ OPC_CheckType, MVT::i32,
+/* 26264*/ OPC_MoveParent,
+/* 26265*/ OPC_MoveChild2,
+/* 26266*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26269*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26271*/ OPC_CheckType, MVT::i32,
+/* 26273*/ OPC_MoveParent,
+/* 26274*/ OPC_MoveChild3,
+/* 26275*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26278*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26280*/ OPC_CheckType, MVT::i32,
+/* 26282*/ OPC_MoveParent,
+/* 26283*/ OPC_MoveChild4,
+/* 26284*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26287*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26289*/ OPC_CheckType, MVT::i32,
+/* 26291*/ OPC_MoveParent,
+/* 26292*/ OPC_MoveChild5,
+/* 26293*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26296*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26298*/ OPC_CheckType, MVT::i32,
+/* 26300*/ OPC_MoveParent,
+/* 26301*/ OPC_MoveChild6,
+/* 26302*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26305*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26307*/ OPC_CheckType, MVT::i32,
+/* 26309*/ OPC_MoveParent,
+/* 26310*/ OPC_MoveChild7,
+/* 26311*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26314*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26316*/ OPC_CheckType, MVT::i32,
+/* 26318*/ OPC_MoveParent,
+/* 26319*/ OPC_MoveParent,
+/* 26320*/ OPC_CheckType, MVT::v8i16,
+/* 26322*/ OPC_MoveParent,
+/* 26323*/ OPC_MoveParent,
+/* 26324*/ OPC_MoveParent,
+/* 26325*/ OPC_RecordChild1, // #1 = $ws
+/* 26326*/ OPC_CheckType, MVT::v8i16,
+/* 26328*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26330*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v8i16] } (xor:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))), v8i16:{ *:[v8i16] }:$ws) - Complexity = 55
+ // Dst: (BCLR_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 26338*/ /*Scope*/ 96, /*->26435*/
+/* 26339*/ OPC_MoveChild0,
+/* 26340*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26343*/ OPC_MoveChild0,
+/* 26344*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26347*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26349*/ OPC_CheckType, MVT::i32,
+/* 26351*/ OPC_MoveParent,
+/* 26352*/ OPC_MoveChild1,
+/* 26353*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26356*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26358*/ OPC_CheckType, MVT::i32,
+/* 26360*/ OPC_MoveParent,
+/* 26361*/ OPC_MoveChild2,
+/* 26362*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26365*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26367*/ OPC_CheckType, MVT::i32,
+/* 26369*/ OPC_MoveParent,
+/* 26370*/ OPC_MoveChild3,
+/* 26371*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26374*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26376*/ OPC_CheckType, MVT::i32,
+/* 26378*/ OPC_MoveParent,
+/* 26379*/ OPC_MoveChild4,
+/* 26380*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26383*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26385*/ OPC_CheckType, MVT::i32,
+/* 26387*/ OPC_MoveParent,
+/* 26388*/ OPC_MoveChild5,
+/* 26389*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26392*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26394*/ OPC_CheckType, MVT::i32,
+/* 26396*/ OPC_MoveParent,
+/* 26397*/ OPC_MoveChild6,
+/* 26398*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26401*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26403*/ OPC_CheckType, MVT::i32,
+/* 26405*/ OPC_MoveParent,
+/* 26406*/ OPC_MoveChild7,
+/* 26407*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26410*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 26412*/ OPC_CheckType, MVT::i32,
+/* 26414*/ OPC_MoveParent,
+/* 26415*/ OPC_MoveParent,
+/* 26416*/ OPC_RecordChild1, // #0 = $wt
+/* 26417*/ OPC_CheckType, MVT::v8i16,
+/* 26419*/ OPC_MoveParent,
+/* 26420*/ OPC_MoveParent,
+/* 26421*/ OPC_MoveParent,
+/* 26422*/ OPC_RecordChild1, // #1 = $ws
+/* 26423*/ OPC_CheckType, MVT::v8i16,
+/* 26425*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26427*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v8i16] } (xor:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))), v8i16:{ *:[v8i16] }:$ws) - Complexity = 55
+ // Dst: (BCLR_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 26435*/ 0, /*End of Scope*/
+/* 26436*/ 0, // EndSwitchOpcode
+/* 26437*/ /*Scope*/ 47|128,2/*303*/, /*->26742*/
+/* 26439*/ OPC_RecordChild0, // #0 = $ws
+/* 26440*/ OPC_MoveChild1,
+/* 26441*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 26444*/ OPC_MoveChild0,
+/* 26445*/ OPC_SwitchOpcode /*2 cases */, 19|128,1/*147*/, TARGET_VAL(ISD::SHL),// ->26597
+/* 26450*/ OPC_MoveChild0,
+/* 26451*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26454*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 26456*/ OPC_MoveParent,
+/* 26457*/ OPC_MoveChild1,
+/* 26458*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 26461*/ OPC_Scope, 66, /*->26529*/ // 2 children in Scope
+/* 26463*/ OPC_RecordChild0, // #1 = $wt
+/* 26464*/ OPC_MoveChild1,
+/* 26465*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26468*/ OPC_MoveChild0,
+/* 26469*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26472*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26474*/ OPC_CheckType, MVT::i32,
+/* 26476*/ OPC_MoveParent,
+/* 26477*/ OPC_MoveChild1,
+/* 26478*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26481*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26483*/ OPC_CheckType, MVT::i32,
+/* 26485*/ OPC_MoveParent,
+/* 26486*/ OPC_MoveChild2,
+/* 26487*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26490*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26492*/ OPC_CheckType, MVT::i32,
+/* 26494*/ OPC_MoveParent,
+/* 26495*/ OPC_MoveChild3,
+/* 26496*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26499*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26501*/ OPC_CheckType, MVT::i32,
+/* 26503*/ OPC_MoveParent,
+/* 26504*/ OPC_MoveParent,
+/* 26505*/ OPC_CheckType, MVT::v4i32,
+/* 26507*/ OPC_MoveParent,
+/* 26508*/ OPC_MoveParent,
+/* 26509*/ OPC_MoveChild1,
+/* 26510*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26513*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26515*/ OPC_MoveParent,
+/* 26516*/ OPC_MoveParent,
+/* 26517*/ OPC_CheckType, MVT::v4i32,
+/* 26519*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26521*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))), (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>)) - Complexity = 39
+ // Dst: (BCLR_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 26529*/ /*Scope*/ 66, /*->26596*/
+/* 26530*/ OPC_MoveChild0,
+/* 26531*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26534*/ OPC_MoveChild0,
+/* 26535*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26538*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26540*/ OPC_CheckType, MVT::i32,
+/* 26542*/ OPC_MoveParent,
+/* 26543*/ OPC_MoveChild1,
+/* 26544*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26547*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26549*/ OPC_CheckType, MVT::i32,
+/* 26551*/ OPC_MoveParent,
+/* 26552*/ OPC_MoveChild2,
+/* 26553*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26556*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26558*/ OPC_CheckType, MVT::i32,
+/* 26560*/ OPC_MoveParent,
+/* 26561*/ OPC_MoveChild3,
+/* 26562*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26565*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26567*/ OPC_CheckType, MVT::i32,
+/* 26569*/ OPC_MoveParent,
+/* 26570*/ OPC_MoveParent,
+/* 26571*/ OPC_RecordChild1, // #1 = $wt
+/* 26572*/ OPC_CheckType, MVT::v4i32,
+/* 26574*/ OPC_MoveParent,
+/* 26575*/ OPC_MoveParent,
+/* 26576*/ OPC_MoveChild1,
+/* 26577*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26580*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26582*/ OPC_MoveParent,
+/* 26583*/ OPC_MoveParent,
+/* 26584*/ OPC_CheckType, MVT::v4i32,
+/* 26586*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26588*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)), (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>)) - Complexity = 39
+ // Dst: (BCLR_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 26596*/ 0, /*End of Scope*/
+/* 26597*/ /*SwitchOpcode*/ 12|128,1/*140*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->26741
+/* 26601*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26603*/ OPC_MoveParent,
+/* 26604*/ OPC_MoveChild1,
+/* 26605*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 26608*/ OPC_MoveChild0,
+/* 26609*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26612*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 26614*/ OPC_MoveParent,
+/* 26615*/ OPC_MoveChild1,
+/* 26616*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 26619*/ OPC_Scope, 59, /*->26680*/ // 2 children in Scope
+/* 26621*/ OPC_RecordChild0, // #1 = $wt
+/* 26622*/ OPC_MoveChild1,
+/* 26623*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26626*/ OPC_MoveChild0,
+/* 26627*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26630*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26632*/ OPC_CheckType, MVT::i32,
+/* 26634*/ OPC_MoveParent,
+/* 26635*/ OPC_MoveChild1,
+/* 26636*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26639*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26641*/ OPC_CheckType, MVT::i32,
+/* 26643*/ OPC_MoveParent,
+/* 26644*/ OPC_MoveChild2,
+/* 26645*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26648*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26650*/ OPC_CheckType, MVT::i32,
+/* 26652*/ OPC_MoveParent,
+/* 26653*/ OPC_MoveChild3,
+/* 26654*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26657*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26659*/ OPC_CheckType, MVT::i32,
+/* 26661*/ OPC_MoveParent,
+/* 26662*/ OPC_MoveParent,
+/* 26663*/ OPC_CheckType, MVT::v4i32,
+/* 26665*/ OPC_MoveParent,
+/* 26666*/ OPC_MoveParent,
+/* 26667*/ OPC_MoveParent,
+/* 26668*/ OPC_CheckType, MVT::v4i32,
+/* 26670*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26672*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (xor:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))))) - Complexity = 39
+ // Dst: (BCLR_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 26680*/ /*Scope*/ 59, /*->26740*/
+/* 26681*/ OPC_MoveChild0,
+/* 26682*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26685*/ OPC_MoveChild0,
+/* 26686*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26689*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26691*/ OPC_CheckType, MVT::i32,
+/* 26693*/ OPC_MoveParent,
+/* 26694*/ OPC_MoveChild1,
+/* 26695*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26698*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26700*/ OPC_CheckType, MVT::i32,
+/* 26702*/ OPC_MoveParent,
+/* 26703*/ OPC_MoveChild2,
+/* 26704*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26707*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26709*/ OPC_CheckType, MVT::i32,
+/* 26711*/ OPC_MoveParent,
+/* 26712*/ OPC_MoveChild3,
+/* 26713*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26716*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26718*/ OPC_CheckType, MVT::i32,
+/* 26720*/ OPC_MoveParent,
+/* 26721*/ OPC_MoveParent,
+/* 26722*/ OPC_RecordChild1, // #1 = $wt
+/* 26723*/ OPC_CheckType, MVT::v4i32,
+/* 26725*/ OPC_MoveParent,
+/* 26726*/ OPC_MoveParent,
+/* 26727*/ OPC_MoveParent,
+/* 26728*/ OPC_CheckType, MVT::v4i32,
+/* 26730*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26732*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (xor:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)))) - Complexity = 39
+ // Dst: (BCLR_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 26740*/ 0, /*End of Scope*/
+/* 26741*/ 0, // EndSwitchOpcode
+/* 26742*/ /*Scope*/ 50|128,2/*306*/, /*->27050*/
+/* 26744*/ OPC_MoveChild0,
+/* 26745*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 26748*/ OPC_MoveChild0,
+/* 26749*/ OPC_SwitchOpcode /*2 cases */, 21|128,1/*149*/, TARGET_VAL(ISD::SHL),// ->26903
+/* 26754*/ OPC_MoveChild0,
+/* 26755*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26758*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 26760*/ OPC_MoveParent,
+/* 26761*/ OPC_MoveChild1,
+/* 26762*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 26765*/ OPC_Scope, 67, /*->26834*/ // 2 children in Scope
+/* 26767*/ OPC_RecordChild0, // #0 = $wt
+/* 26768*/ OPC_MoveChild1,
+/* 26769*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26772*/ OPC_MoveChild0,
+/* 26773*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26776*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26778*/ OPC_CheckType, MVT::i32,
+/* 26780*/ OPC_MoveParent,
+/* 26781*/ OPC_MoveChild1,
+/* 26782*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26785*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26787*/ OPC_CheckType, MVT::i32,
+/* 26789*/ OPC_MoveParent,
+/* 26790*/ OPC_MoveChild2,
+/* 26791*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26794*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26796*/ OPC_CheckType, MVT::i32,
+/* 26798*/ OPC_MoveParent,
+/* 26799*/ OPC_MoveChild3,
+/* 26800*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26803*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26805*/ OPC_CheckType, MVT::i32,
+/* 26807*/ OPC_MoveParent,
+/* 26808*/ OPC_MoveParent,
+/* 26809*/ OPC_CheckType, MVT::v4i32,
+/* 26811*/ OPC_MoveParent,
+/* 26812*/ OPC_MoveParent,
+/* 26813*/ OPC_MoveChild1,
+/* 26814*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26817*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26819*/ OPC_MoveParent,
+/* 26820*/ OPC_MoveParent,
+/* 26821*/ OPC_RecordChild1, // #1 = $ws
+/* 26822*/ OPC_CheckType, MVT::v4i32,
+/* 26824*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26826*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))), (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), v4i32:{ *:[v4i32] }:$ws) - Complexity = 39
+ // Dst: (BCLR_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 26834*/ /*Scope*/ 67, /*->26902*/
+/* 26835*/ OPC_MoveChild0,
+/* 26836*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26839*/ OPC_MoveChild0,
+/* 26840*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26843*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26845*/ OPC_CheckType, MVT::i32,
+/* 26847*/ OPC_MoveParent,
+/* 26848*/ OPC_MoveChild1,
+/* 26849*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26852*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26854*/ OPC_CheckType, MVT::i32,
+/* 26856*/ OPC_MoveParent,
+/* 26857*/ OPC_MoveChild2,
+/* 26858*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26861*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26863*/ OPC_CheckType, MVT::i32,
+/* 26865*/ OPC_MoveParent,
+/* 26866*/ OPC_MoveChild3,
+/* 26867*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26870*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26872*/ OPC_CheckType, MVT::i32,
+/* 26874*/ OPC_MoveParent,
+/* 26875*/ OPC_MoveParent,
+/* 26876*/ OPC_RecordChild1, // #0 = $wt
+/* 26877*/ OPC_CheckType, MVT::v4i32,
+/* 26879*/ OPC_MoveParent,
+/* 26880*/ OPC_MoveParent,
+/* 26881*/ OPC_MoveChild1,
+/* 26882*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26885*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26887*/ OPC_MoveParent,
+/* 26888*/ OPC_MoveParent,
+/* 26889*/ OPC_RecordChild1, // #1 = $ws
+/* 26890*/ OPC_CheckType, MVT::v4i32,
+/* 26892*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26894*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)), (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), v4i32:{ *:[v4i32] }:$ws) - Complexity = 39
+ // Dst: (BCLR_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 26902*/ 0, /*End of Scope*/
+/* 26903*/ /*SwitchOpcode*/ 14|128,1/*142*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->27049
+/* 26907*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 26909*/ OPC_MoveParent,
+/* 26910*/ OPC_MoveChild1,
+/* 26911*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 26914*/ OPC_MoveChild0,
+/* 26915*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26918*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 26920*/ OPC_MoveParent,
+/* 26921*/ OPC_MoveChild1,
+/* 26922*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 26925*/ OPC_Scope, 60, /*->26987*/ // 2 children in Scope
+/* 26927*/ OPC_RecordChild0, // #0 = $wt
+/* 26928*/ OPC_MoveChild1,
+/* 26929*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26932*/ OPC_MoveChild0,
+/* 26933*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26936*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26938*/ OPC_CheckType, MVT::i32,
+/* 26940*/ OPC_MoveParent,
+/* 26941*/ OPC_MoveChild1,
+/* 26942*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26945*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26947*/ OPC_CheckType, MVT::i32,
+/* 26949*/ OPC_MoveParent,
+/* 26950*/ OPC_MoveChild2,
+/* 26951*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26954*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26956*/ OPC_CheckType, MVT::i32,
+/* 26958*/ OPC_MoveParent,
+/* 26959*/ OPC_MoveChild3,
+/* 26960*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26963*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26965*/ OPC_CheckType, MVT::i32,
+/* 26967*/ OPC_MoveParent,
+/* 26968*/ OPC_MoveParent,
+/* 26969*/ OPC_CheckType, MVT::v4i32,
+/* 26971*/ OPC_MoveParent,
+/* 26972*/ OPC_MoveParent,
+/* 26973*/ OPC_MoveParent,
+/* 26974*/ OPC_RecordChild1, // #1 = $ws
+/* 26975*/ OPC_CheckType, MVT::v4i32,
+/* 26977*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 26979*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))), v4i32:{ *:[v4i32] }:$ws) - Complexity = 39
+ // Dst: (BCLR_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 26987*/ /*Scope*/ 60, /*->27048*/
+/* 26988*/ OPC_MoveChild0,
+/* 26989*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 26992*/ OPC_MoveChild0,
+/* 26993*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 26996*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 26998*/ OPC_CheckType, MVT::i32,
+/* 27000*/ OPC_MoveParent,
+/* 27001*/ OPC_MoveChild1,
+/* 27002*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 27005*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 27007*/ OPC_CheckType, MVT::i32,
+/* 27009*/ OPC_MoveParent,
+/* 27010*/ OPC_MoveChild2,
+/* 27011*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 27014*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 27016*/ OPC_CheckType, MVT::i32,
+/* 27018*/ OPC_MoveParent,
+/* 27019*/ OPC_MoveChild3,
+/* 27020*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 27023*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 27025*/ OPC_CheckType, MVT::i32,
+/* 27027*/ OPC_MoveParent,
+/* 27028*/ OPC_MoveParent,
+/* 27029*/ OPC_RecordChild1, // #0 = $wt
+/* 27030*/ OPC_CheckType, MVT::v4i32,
+/* 27032*/ OPC_MoveParent,
+/* 27033*/ OPC_MoveParent,
+/* 27034*/ OPC_MoveParent,
+/* 27035*/ OPC_RecordChild1, // #1 = $ws
+/* 27036*/ OPC_CheckType, MVT::v4i32,
+/* 27038*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27040*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))), v4i32:{ *:[v4i32] }:$ws) - Complexity = 39
+ // Dst: (BCLR_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 27048*/ 0, /*End of Scope*/
+/* 27049*/ 0, // EndSwitchOpcode
+/* 27050*/ /*Scope*/ 100|128,1/*228*/, /*->27280*/
+/* 27052*/ OPC_RecordChild0, // #0 = $ws
+/* 27053*/ OPC_MoveChild1,
+/* 27054*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 27057*/ OPC_MoveChild0,
+/* 27058*/ OPC_SwitchOpcode /*2 cases */, 114, TARGET_VAL(ISD::SHL),// ->27176
+/* 27062*/ OPC_MoveChild0,
+/* 27063*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27066*/ OPC_MoveChild0,
+/* 27067*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27070*/ OPC_CheckType, MVT::v4i32,
+/* 27072*/ OPC_MoveParent,
+/* 27073*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 27075*/ OPC_MoveParent,
+/* 27076*/ OPC_MoveChild1,
+/* 27077*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 27080*/ OPC_Scope, 46, /*->27128*/ // 2 children in Scope
+/* 27082*/ OPC_RecordChild0, // #1 = $wt
+/* 27083*/ OPC_MoveChild1,
+/* 27084*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27087*/ OPC_MoveChild0,
+/* 27088*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27091*/ OPC_CheckType, MVT::v4i32,
+/* 27093*/ OPC_MoveParent,
+/* 27094*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 27096*/ OPC_MoveParent,
+/* 27097*/ OPC_CheckType, MVT::v2i64,
+/* 27099*/ OPC_MoveParent,
+/* 27100*/ OPC_MoveParent,
+/* 27101*/ OPC_MoveChild1,
+/* 27102*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27105*/ OPC_MoveChild0,
+/* 27106*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27109*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27111*/ OPC_CheckType, MVT::v4i32,
+/* 27113*/ OPC_MoveParent,
+/* 27114*/ OPC_MoveParent,
+/* 27115*/ OPC_MoveParent,
+/* 27116*/ OPC_CheckType, MVT::v2i64,
+/* 27118*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27120*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>)), (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>))) - Complexity = 33
+ // Dst: (BCLR_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 27128*/ /*Scope*/ 46, /*->27175*/
+/* 27129*/ OPC_MoveChild0,
+/* 27130*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27133*/ OPC_MoveChild0,
+/* 27134*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27137*/ OPC_CheckType, MVT::v4i32,
+/* 27139*/ OPC_MoveParent,
+/* 27140*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 27142*/ OPC_MoveParent,
+/* 27143*/ OPC_RecordChild1, // #1 = $wt
+/* 27144*/ OPC_CheckType, MVT::v2i64,
+/* 27146*/ OPC_MoveParent,
+/* 27147*/ OPC_MoveParent,
+/* 27148*/ OPC_MoveChild1,
+/* 27149*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27152*/ OPC_MoveChild0,
+/* 27153*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27156*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27158*/ OPC_CheckType, MVT::v4i32,
+/* 27160*/ OPC_MoveParent,
+/* 27161*/ OPC_MoveParent,
+/* 27162*/ OPC_MoveParent,
+/* 27163*/ OPC_CheckType, MVT::v2i64,
+/* 27165*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27167*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt)), (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>))) - Complexity = 33
+ // Dst: (BCLR_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 27175*/ 0, /*End of Scope*/
+/* 27176*/ /*SwitchOpcode*/ 100, TARGET_VAL(ISD::BITCAST),// ->27279
+/* 27179*/ OPC_MoveChild0,
+/* 27180*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27183*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27185*/ OPC_CheckType, MVT::v4i32,
+/* 27187*/ OPC_MoveParent,
+/* 27188*/ OPC_MoveParent,
+/* 27189*/ OPC_MoveChild1,
+/* 27190*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 27193*/ OPC_MoveChild0,
+/* 27194*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27197*/ OPC_MoveChild0,
+/* 27198*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27201*/ OPC_CheckType, MVT::v4i32,
+/* 27203*/ OPC_MoveParent,
+/* 27204*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 27206*/ OPC_MoveParent,
+/* 27207*/ OPC_MoveChild1,
+/* 27208*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 27211*/ OPC_Scope, 32, /*->27245*/ // 2 children in Scope
+/* 27213*/ OPC_RecordChild0, // #1 = $wt
+/* 27214*/ OPC_MoveChild1,
+/* 27215*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27218*/ OPC_MoveChild0,
+/* 27219*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27222*/ OPC_CheckType, MVT::v4i32,
+/* 27224*/ OPC_MoveParent,
+/* 27225*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 27227*/ OPC_MoveParent,
+/* 27228*/ OPC_CheckType, MVT::v2i64,
+/* 27230*/ OPC_MoveParent,
+/* 27231*/ OPC_MoveParent,
+/* 27232*/ OPC_MoveParent,
+/* 27233*/ OPC_CheckType, MVT::v2i64,
+/* 27235*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27237*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (xor:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>)))) - Complexity = 33
+ // Dst: (BCLR_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 27245*/ /*Scope*/ 32, /*->27278*/
+/* 27246*/ OPC_MoveChild0,
+/* 27247*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27250*/ OPC_MoveChild0,
+/* 27251*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27254*/ OPC_CheckType, MVT::v4i32,
+/* 27256*/ OPC_MoveParent,
+/* 27257*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 27259*/ OPC_MoveParent,
+/* 27260*/ OPC_RecordChild1, // #1 = $wt
+/* 27261*/ OPC_CheckType, MVT::v2i64,
+/* 27263*/ OPC_MoveParent,
+/* 27264*/ OPC_MoveParent,
+/* 27265*/ OPC_MoveParent,
+/* 27266*/ OPC_CheckType, MVT::v2i64,
+/* 27268*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27270*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (xor:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt)))) - Complexity = 33
+ // Dst: (BCLR_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 27278*/ 0, /*End of Scope*/
+/* 27279*/ 0, // EndSwitchOpcode
+/* 27280*/ /*Scope*/ 103|128,1/*231*/, /*->27513*/
+/* 27282*/ OPC_MoveChild0,
+/* 27283*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 27286*/ OPC_MoveChild0,
+/* 27287*/ OPC_SwitchOpcode /*2 cases */, 116, TARGET_VAL(ISD::SHL),// ->27407
+/* 27291*/ OPC_MoveChild0,
+/* 27292*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27295*/ OPC_MoveChild0,
+/* 27296*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27299*/ OPC_CheckType, MVT::v4i32,
+/* 27301*/ OPC_MoveParent,
+/* 27302*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 27304*/ OPC_MoveParent,
+/* 27305*/ OPC_MoveChild1,
+/* 27306*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 27309*/ OPC_Scope, 47, /*->27358*/ // 2 children in Scope
+/* 27311*/ OPC_RecordChild0, // #0 = $wt
+/* 27312*/ OPC_MoveChild1,
+/* 27313*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27316*/ OPC_MoveChild0,
+/* 27317*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27320*/ OPC_CheckType, MVT::v4i32,
+/* 27322*/ OPC_MoveParent,
+/* 27323*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 27325*/ OPC_MoveParent,
+/* 27326*/ OPC_CheckType, MVT::v2i64,
+/* 27328*/ OPC_MoveParent,
+/* 27329*/ OPC_MoveParent,
+/* 27330*/ OPC_MoveChild1,
+/* 27331*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27334*/ OPC_MoveChild0,
+/* 27335*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27338*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27340*/ OPC_CheckType, MVT::v4i32,
+/* 27342*/ OPC_MoveParent,
+/* 27343*/ OPC_MoveParent,
+/* 27344*/ OPC_MoveParent,
+/* 27345*/ OPC_RecordChild1, // #1 = $ws
+/* 27346*/ OPC_CheckType, MVT::v2i64,
+/* 27348*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27350*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v2i64] } (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>)), (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>)), v2i64:{ *:[v2i64] }:$ws) - Complexity = 33
+ // Dst: (BCLR_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 27358*/ /*Scope*/ 47, /*->27406*/
+/* 27359*/ OPC_MoveChild0,
+/* 27360*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27363*/ OPC_MoveChild0,
+/* 27364*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27367*/ OPC_CheckType, MVT::v4i32,
+/* 27369*/ OPC_MoveParent,
+/* 27370*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 27372*/ OPC_MoveParent,
+/* 27373*/ OPC_RecordChild1, // #0 = $wt
+/* 27374*/ OPC_CheckType, MVT::v2i64,
+/* 27376*/ OPC_MoveParent,
+/* 27377*/ OPC_MoveParent,
+/* 27378*/ OPC_MoveChild1,
+/* 27379*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27382*/ OPC_MoveChild0,
+/* 27383*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27386*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27388*/ OPC_CheckType, MVT::v4i32,
+/* 27390*/ OPC_MoveParent,
+/* 27391*/ OPC_MoveParent,
+/* 27392*/ OPC_MoveParent,
+/* 27393*/ OPC_RecordChild1, // #1 = $ws
+/* 27394*/ OPC_CheckType, MVT::v2i64,
+/* 27396*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27398*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v2i64] } (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt)), (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>)), v2i64:{ *:[v2i64] }:$ws) - Complexity = 33
+ // Dst: (BCLR_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 27406*/ 0, /*End of Scope*/
+/* 27407*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::BITCAST),// ->27512
+/* 27410*/ OPC_MoveChild0,
+/* 27411*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27414*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27416*/ OPC_CheckType, MVT::v4i32,
+/* 27418*/ OPC_MoveParent,
+/* 27419*/ OPC_MoveParent,
+/* 27420*/ OPC_MoveChild1,
+/* 27421*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 27424*/ OPC_MoveChild0,
+/* 27425*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27428*/ OPC_MoveChild0,
+/* 27429*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27432*/ OPC_CheckType, MVT::v4i32,
+/* 27434*/ OPC_MoveParent,
+/* 27435*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 27437*/ OPC_MoveParent,
+/* 27438*/ OPC_MoveChild1,
+/* 27439*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 27442*/ OPC_Scope, 33, /*->27477*/ // 2 children in Scope
+/* 27444*/ OPC_RecordChild0, // #0 = $wt
+/* 27445*/ OPC_MoveChild1,
+/* 27446*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27449*/ OPC_MoveChild0,
+/* 27450*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27453*/ OPC_CheckType, MVT::v4i32,
+/* 27455*/ OPC_MoveParent,
+/* 27456*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 27458*/ OPC_MoveParent,
+/* 27459*/ OPC_CheckType, MVT::v2i64,
+/* 27461*/ OPC_MoveParent,
+/* 27462*/ OPC_MoveParent,
+/* 27463*/ OPC_MoveParent,
+/* 27464*/ OPC_RecordChild1, // #1 = $ws
+/* 27465*/ OPC_CheckType, MVT::v2i64,
+/* 27467*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v2i64] } (xor:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>))), v2i64:{ *:[v2i64] }:$ws) - Complexity = 33
+ // Dst: (BCLR_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 27477*/ /*Scope*/ 33, /*->27511*/
+/* 27478*/ OPC_MoveChild0,
+/* 27479*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27482*/ OPC_MoveChild0,
+/* 27483*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27486*/ OPC_CheckType, MVT::v4i32,
+/* 27488*/ OPC_MoveParent,
+/* 27489*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 27491*/ OPC_MoveParent,
+/* 27492*/ OPC_RecordChild1, // #0 = $wt
+/* 27493*/ OPC_CheckType, MVT::v2i64,
+/* 27495*/ OPC_MoveParent,
+/* 27496*/ OPC_MoveParent,
+/* 27497*/ OPC_MoveParent,
+/* 27498*/ OPC_RecordChild1, // #1 = $ws
+/* 27499*/ OPC_CheckType, MVT::v2i64,
+/* 27501*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 27503*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v2i64] } (xor:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt))), v2i64:{ *:[v2i64] }:$ws) - Complexity = 33
+ // Dst: (BCLR_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 27511*/ 0, /*End of Scope*/
+/* 27512*/ 0, // EndSwitchOpcode
+/* 27513*/ /*Scope*/ 104, /*->27618*/
+/* 27514*/ OPC_RecordChild0, // #0 = $ws
+/* 27515*/ OPC_MoveChild1,
+/* 27516*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 27519*/ OPC_MoveChild0,
+/* 27520*/ OPC_SwitchOpcode /*2 cases */, 45, TARGET_VAL(ISD::SHL),// ->27569
+/* 27524*/ OPC_MoveChild0,
+/* 27525*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27528*/ OPC_MoveChild0,
+/* 27529*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27532*/ OPC_CheckType, MVT::v4i32,
+/* 27534*/ OPC_MoveParent,
+/* 27535*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 27537*/ OPC_MoveParent,
+/* 27538*/ OPC_RecordChild1, // #1 = $wt
+/* 27539*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 27541*/ OPC_MoveParent,
+/* 27542*/ OPC_MoveChild1,
+/* 27543*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27546*/ OPC_MoveChild0,
+/* 27547*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27550*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27552*/ OPC_CheckType, MVT::v4i32,
+/* 27554*/ OPC_MoveParent,
+/* 27555*/ OPC_MoveParent,
+/* 27556*/ OPC_MoveParent,
+/* 27557*/ OPC_CheckType, MVT::v2i64,
+/* 27559*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27561*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, MSA128DOpnd:{ *:[v2i64] }:$wt), (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>))) - Complexity = 23
+ // Dst: (BCLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 27569*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::BITCAST),// ->27617
+/* 27572*/ OPC_MoveChild0,
+/* 27573*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27576*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27578*/ OPC_CheckType, MVT::v4i32,
+/* 27580*/ OPC_MoveParent,
+/* 27581*/ OPC_MoveParent,
+/* 27582*/ OPC_MoveChild1,
+/* 27583*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 27586*/ OPC_MoveChild0,
+/* 27587*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27590*/ OPC_MoveChild0,
+/* 27591*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27594*/ OPC_CheckType, MVT::v4i32,
+/* 27596*/ OPC_MoveParent,
+/* 27597*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 27599*/ OPC_MoveParent,
+/* 27600*/ OPC_RecordChild1, // #1 = $wt
+/* 27601*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 27603*/ OPC_MoveParent,
+/* 27604*/ OPC_MoveParent,
+/* 27605*/ OPC_CheckType, MVT::v2i64,
+/* 27607*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27609*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (xor:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, MSA128DOpnd:{ *:[v2i64] }:$wt))) - Complexity = 23
+ // Dst: (BCLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 27617*/ 0, // EndSwitchOpcode
+/* 27618*/ /*Scope*/ 105, /*->27724*/
+/* 27619*/ OPC_MoveChild0,
+/* 27620*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 27623*/ OPC_MoveChild0,
+/* 27624*/ OPC_SwitchOpcode /*2 cases */, 46, TARGET_VAL(ISD::SHL),// ->27674
+/* 27628*/ OPC_MoveChild0,
+/* 27629*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27632*/ OPC_MoveChild0,
+/* 27633*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27636*/ OPC_CheckType, MVT::v4i32,
+/* 27638*/ OPC_MoveParent,
+/* 27639*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 27641*/ OPC_MoveParent,
+/* 27642*/ OPC_RecordChild1, // #0 = $wt
+/* 27643*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 27645*/ OPC_MoveParent,
+/* 27646*/ OPC_MoveChild1,
+/* 27647*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27650*/ OPC_MoveChild0,
+/* 27651*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27654*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27656*/ OPC_CheckType, MVT::v4i32,
+/* 27658*/ OPC_MoveParent,
+/* 27659*/ OPC_MoveParent,
+/* 27660*/ OPC_MoveParent,
+/* 27661*/ OPC_RecordChild1, // #1 = $ws
+/* 27662*/ OPC_CheckType, MVT::v2i64,
+/* 27664*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27666*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v2i64] } (xor:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, MSA128DOpnd:{ *:[v2i64] }:$wt), (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>)), MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 23
+ // Dst: (BCLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 27674*/ /*SwitchOpcode*/ 46, TARGET_VAL(ISD::BITCAST),// ->27723
+/* 27677*/ OPC_MoveChild0,
+/* 27678*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27681*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27683*/ OPC_CheckType, MVT::v4i32,
+/* 27685*/ OPC_MoveParent,
+/* 27686*/ OPC_MoveParent,
+/* 27687*/ OPC_MoveChild1,
+/* 27688*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 27691*/ OPC_MoveChild0,
+/* 27692*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 27695*/ OPC_MoveChild0,
+/* 27696*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27699*/ OPC_CheckType, MVT::v4i32,
+/* 27701*/ OPC_MoveParent,
+/* 27702*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 27704*/ OPC_MoveParent,
+/* 27705*/ OPC_RecordChild1, // #0 = $wt
+/* 27706*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 27708*/ OPC_MoveParent,
+/* 27709*/ OPC_MoveParent,
+/* 27710*/ OPC_RecordChild1, // #1 = $ws
+/* 27711*/ OPC_CheckType, MVT::v2i64,
+/* 27713*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27715*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v2i64] } (xor:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, MSA128DOpnd:{ *:[v2i64] }:$wt)), MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 23
+ // Dst: (BCLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 27723*/ 0, // EndSwitchOpcode
+/* 27724*/ /*Scope*/ 127, /*->27852*/
+/* 27725*/ OPC_RecordChild0, // #0 = $ws
+/* 27726*/ OPC_MoveChild1,
+/* 27727*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 27730*/ OPC_MoveChild0,
+/* 27731*/ OPC_SwitchOpcode /*2 cases */, 82, TARGET_VAL(ISD::SHL),// ->27817
+/* 27735*/ OPC_MoveChild0,
+/* 27736*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27739*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 27741*/ OPC_MoveParent,
+/* 27742*/ OPC_RecordChild1, // #1 = $wt
+/* 27743*/ OPC_Scope, 23, /*->27768*/ // 3 children in Scope
+/* 27745*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 27747*/ OPC_MoveParent,
+/* 27748*/ OPC_MoveChild1,
+/* 27749*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27752*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27754*/ OPC_MoveParent,
+/* 27755*/ OPC_MoveParent,
+/* 27756*/ OPC_CheckType, MVT::v16i8,
+/* 27758*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27760*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128BOpnd:{ *:[v16i8] }:$wt), (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>)) - Complexity = 17
+ // Dst: (BCLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 27768*/ /*Scope*/ 23, /*->27792*/
+/* 27769*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 27771*/ OPC_MoveParent,
+/* 27772*/ OPC_MoveChild1,
+/* 27773*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27776*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27778*/ OPC_MoveParent,
+/* 27779*/ OPC_MoveParent,
+/* 27780*/ OPC_CheckType, MVT::v8i16,
+/* 27782*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27784*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128HOpnd:{ *:[v8i16] }:$wt), (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>)) - Complexity = 17
+ // Dst: (BCLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 27792*/ /*Scope*/ 23, /*->27816*/
+/* 27793*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 27795*/ OPC_MoveParent,
+/* 27796*/ OPC_MoveChild1,
+/* 27797*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27800*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27802*/ OPC_MoveParent,
+/* 27803*/ OPC_MoveParent,
+/* 27804*/ OPC_CheckType, MVT::v4i32,
+/* 27806*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27808*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128WOpnd:{ *:[v4i32] }:$wt), (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>)) - Complexity = 17
+ // Dst: (BCLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 27816*/ 0, /*End of Scope*/
+/* 27817*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::BUILD_VECTOR),// ->27851
+/* 27820*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27822*/ OPC_MoveParent,
+/* 27823*/ OPC_MoveChild1,
+/* 27824*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 27827*/ OPC_MoveChild0,
+/* 27828*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27831*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 27833*/ OPC_MoveParent,
+/* 27834*/ OPC_RecordChild1, // #1 = $wt
+/* 27835*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 27837*/ OPC_MoveParent,
+/* 27838*/ OPC_MoveParent,
+/* 27839*/ OPC_CheckType, MVT::v16i8,
+/* 27841*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27843*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (xor:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128BOpnd:{ *:[v16i8] }:$wt))) - Complexity = 17
+ // Dst: (BCLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 27851*/ 0, // EndSwitchOpcode
+/* 27852*/ /*Scope*/ 77, /*->27930*/
+/* 27853*/ OPC_MoveChild0,
+/* 27854*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 27857*/ OPC_MoveChild0,
+/* 27858*/ OPC_SwitchOpcode /*2 cases */, 32, TARGET_VAL(ISD::SHL),// ->27894
+/* 27862*/ OPC_MoveChild0,
+/* 27863*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27866*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 27868*/ OPC_MoveParent,
+/* 27869*/ OPC_RecordChild1, // #0 = $wt
+/* 27870*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 27872*/ OPC_MoveParent,
+/* 27873*/ OPC_MoveChild1,
+/* 27874*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27877*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27879*/ OPC_MoveParent,
+/* 27880*/ OPC_MoveParent,
+/* 27881*/ OPC_RecordChild1, // #1 = $ws
+/* 27882*/ OPC_CheckType, MVT::v16i8,
+/* 27884*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27886*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v16i8] } (xor:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128BOpnd:{ *:[v16i8] }:$wt), (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>), MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 17
+ // Dst: (BCLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 27894*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::BUILD_VECTOR),// ->27929
+/* 27897*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27899*/ OPC_MoveParent,
+/* 27900*/ OPC_MoveChild1,
+/* 27901*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 27904*/ OPC_MoveChild0,
+/* 27905*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27908*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 27910*/ OPC_MoveParent,
+/* 27911*/ OPC_RecordChild1, // #0 = $wt
+/* 27912*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 27914*/ OPC_MoveParent,
+/* 27915*/ OPC_MoveParent,
+/* 27916*/ OPC_RecordChild1, // #1 = $ws
+/* 27917*/ OPC_CheckType, MVT::v16i8,
+/* 27919*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27921*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v16i8] } (xor:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128BOpnd:{ *:[v16i8] }:$wt)), MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 17
+ // Dst: (BCLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 27929*/ 0, // EndSwitchOpcode
+/* 27930*/ /*Scope*/ 40, /*->27971*/
+/* 27931*/ OPC_RecordChild0, // #0 = $ws
+/* 27932*/ OPC_MoveChild1,
+/* 27933*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 27936*/ OPC_MoveChild0,
+/* 27937*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27940*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27942*/ OPC_MoveParent,
+/* 27943*/ OPC_MoveChild1,
+/* 27944*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 27947*/ OPC_MoveChild0,
+/* 27948*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27951*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 27953*/ OPC_MoveParent,
+/* 27954*/ OPC_RecordChild1, // #1 = $wt
+/* 27955*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 27957*/ OPC_MoveParent,
+/* 27958*/ OPC_MoveParent,
+/* 27959*/ OPC_CheckType, MVT::v8i16,
+/* 27961*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 27963*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (xor:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128HOpnd:{ *:[v8i16] }:$wt))) - Complexity = 17
+ // Dst: (BCLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 27971*/ /*Scope*/ 77, /*->28049*/
+/* 27972*/ OPC_MoveChild0,
+/* 27973*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 27976*/ OPC_MoveChild0,
+/* 27977*/ OPC_SwitchOpcode /*2 cases */, 32, TARGET_VAL(ISD::SHL),// ->28013
+/* 27981*/ OPC_MoveChild0,
+/* 27982*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27985*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 27987*/ OPC_MoveParent,
+/* 27988*/ OPC_RecordChild1, // #0 = $wt
+/* 27989*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 27991*/ OPC_MoveParent,
+/* 27992*/ OPC_MoveChild1,
+/* 27993*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 27996*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 27998*/ OPC_MoveParent,
+/* 27999*/ OPC_MoveParent,
+/* 28000*/ OPC_RecordChild1, // #1 = $ws
+/* 28001*/ OPC_CheckType, MVT::v8i16,
+/* 28003*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28005*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v8i16] } (xor:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128HOpnd:{ *:[v8i16] }:$wt), (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>), MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 17
+ // Dst: (BCLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 28013*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::BUILD_VECTOR),// ->28048
+/* 28016*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 28018*/ OPC_MoveParent,
+/* 28019*/ OPC_MoveChild1,
+/* 28020*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 28023*/ OPC_MoveChild0,
+/* 28024*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 28027*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 28029*/ OPC_MoveParent,
+/* 28030*/ OPC_RecordChild1, // #0 = $wt
+/* 28031*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 28033*/ OPC_MoveParent,
+/* 28034*/ OPC_MoveParent,
+/* 28035*/ OPC_RecordChild1, // #1 = $ws
+/* 28036*/ OPC_CheckType, MVT::v8i16,
+/* 28038*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28040*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v8i16] } (xor:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128HOpnd:{ *:[v8i16] }:$wt)), MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 17
+ // Dst: (BCLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 28048*/ 0, // EndSwitchOpcode
+/* 28049*/ /*Scope*/ 40, /*->28090*/
+/* 28050*/ OPC_RecordChild0, // #0 = $ws
+/* 28051*/ OPC_MoveChild1,
+/* 28052*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 28055*/ OPC_MoveChild0,
+/* 28056*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 28059*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 28061*/ OPC_MoveParent,
+/* 28062*/ OPC_MoveChild1,
+/* 28063*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 28066*/ OPC_MoveChild0,
+/* 28067*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 28070*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 28072*/ OPC_MoveParent,
+/* 28073*/ OPC_RecordChild1, // #1 = $wt
+/* 28074*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 28076*/ OPC_MoveParent,
+/* 28077*/ OPC_MoveParent,
+/* 28078*/ OPC_CheckType, MVT::v4i32,
+/* 28080*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28082*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (xor:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128WOpnd:{ *:[v4i32] }:$wt))) - Complexity = 17
+ // Dst: (BCLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 28090*/ /*Scope*/ 77, /*->28168*/
+/* 28091*/ OPC_MoveChild0,
+/* 28092*/ OPC_CheckOpcode, TARGET_VAL(ISD::XOR),
+/* 28095*/ OPC_MoveChild0,
+/* 28096*/ OPC_SwitchOpcode /*2 cases */, 32, TARGET_VAL(ISD::SHL),// ->28132
+/* 28100*/ OPC_MoveChild0,
+/* 28101*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 28104*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 28106*/ OPC_MoveParent,
+/* 28107*/ OPC_RecordChild1, // #0 = $wt
+/* 28108*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 28110*/ OPC_MoveParent,
+/* 28111*/ OPC_MoveChild1,
+/* 28112*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 28115*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 28117*/ OPC_MoveParent,
+/* 28118*/ OPC_MoveParent,
+/* 28119*/ OPC_RecordChild1, // #1 = $ws
+/* 28120*/ OPC_CheckType, MVT::v4i32,
+/* 28122*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28124*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128WOpnd:{ *:[v4i32] }:$wt), (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>), MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 17
+ // Dst: (BCLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 28132*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::BUILD_VECTOR),// ->28167
+/* 28135*/ OPC_CheckPredicate, 48, // Predicate_immAllOnesV
+/* 28137*/ OPC_MoveParent,
+/* 28138*/ OPC_MoveChild1,
+/* 28139*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 28142*/ OPC_MoveChild0,
+/* 28143*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 28146*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 28148*/ OPC_MoveParent,
+/* 28149*/ OPC_RecordChild1, // #0 = $wt
+/* 28150*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 28152*/ OPC_MoveParent,
+/* 28153*/ OPC_MoveParent,
+/* 28154*/ OPC_RecordChild1, // #1 = $ws
+/* 28155*/ OPC_CheckType, MVT::v4i32,
+/* 28157*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28159*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_immAllOnesV>>, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128WOpnd:{ *:[v4i32] }:$wt)), MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 17
+ // Dst: (BCLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 28167*/ 0, // EndSwitchOpcode
+/* 28168*/ /*Scope*/ 56|128,1/*184*/, /*->28354*/
+/* 28170*/ OPC_RecordChild0, // #0 = $ws
+/* 28171*/ OPC_RecordChild1, // #1 = $u8
+/* 28172*/ OPC_SwitchType /*4 cases */, 61, MVT::v16i8,// ->28236
+/* 28175*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28177*/ OPC_Scope, 11, /*->28190*/ // 5 children in Scope
+/* 28179*/ OPC_CheckComplexPat, /*CP*/14, /*#*/1, // selectVSplatUimm8:$u8 #2
+/* 28182*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ANDI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8) - Complexity = 9
+ // Dst: (ANDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 28190*/ /*Scope*/ 11, /*->28202*/
+/* 28191*/ OPC_CheckComplexPat, /*CP*/15, /*#*/1, // selectVSplatUimmInvPow2:$m #2
+/* 28194*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLRI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_inv_pow2:{ *:[v16i8] }:$m) - Complexity = 9
+ // Dst: (BCLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_inv_pow2:{ *:[v16i8] }:$m)
+/* 28202*/ /*Scope*/ 11, /*->28214*/
+/* 28203*/ OPC_CheckComplexPat, /*CP*/14, /*#*/0, // selectVSplatUimm8:$u8 #2
+/* 28206*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ANDI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (and:{ *:[v16i8] } vsplati8_uimm8:{ *:[v16i8] }:$u8, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (ANDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 28214*/ /*Scope*/ 11, /*->28226*/
+/* 28215*/ OPC_CheckComplexPat, /*CP*/15, /*#*/0, // selectVSplatUimmInvPow2:$m #2
+/* 28218*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLRI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (and:{ *:[v16i8] } vsplat_uimm_inv_pow2:{ *:[v16i8] }:$m, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (BCLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_inv_pow2:{ *:[v16i8] }:$m)
+/* 28226*/ /*Scope*/ 8, /*->28235*/
+/* 28227*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND_V), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 28235*/ 0, /*End of Scope*/
+/* 28236*/ /*SwitchType*/ 37, MVT::v8i16,// ->28275
+/* 28238*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28240*/ OPC_Scope, 11, /*->28253*/ // 3 children in Scope
+/* 28242*/ OPC_CheckComplexPat, /*CP*/15, /*#*/1, // selectVSplatUimmInvPow2:$m #2
+/* 28245*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLRI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_inv_pow2:{ *:[v8i16] }:$m) - Complexity = 9
+ // Dst: (BCLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_inv_pow2:{ *:[v8i16] }:$m)
+/* 28253*/ /*Scope*/ 11, /*->28265*/
+/* 28254*/ OPC_CheckComplexPat, /*CP*/15, /*#*/0, // selectVSplatUimmInvPow2:$m #2
+/* 28257*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLRI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (and:{ *:[v8i16] } vsplat_uimm_inv_pow2:{ *:[v8i16] }:$m, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (BCLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_inv_pow2:{ *:[v8i16] }:$m)
+/* 28265*/ /*Scope*/ 8, /*->28274*/
+/* 28266*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND_V_H_PSEUDO), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 28274*/ 0, /*End of Scope*/
+/* 28275*/ /*SwitchType*/ 37, MVT::v4i32,// ->28314
+/* 28277*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28279*/ OPC_Scope, 11, /*->28292*/ // 3 children in Scope
+/* 28281*/ OPC_CheckComplexPat, /*CP*/15, /*#*/1, // selectVSplatUimmInvPow2:$m #2
+/* 28284*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLRI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_inv_pow2:{ *:[v4i32] }:$m) - Complexity = 9
+ // Dst: (BCLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_inv_pow2:{ *:[v4i32] }:$m)
+/* 28292*/ /*Scope*/ 11, /*->28304*/
+/* 28293*/ OPC_CheckComplexPat, /*CP*/15, /*#*/0, // selectVSplatUimmInvPow2:$m #2
+/* 28296*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLRI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (and:{ *:[v4i32] } vsplat_uimm_inv_pow2:{ *:[v4i32] }:$m, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (BCLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_inv_pow2:{ *:[v4i32] }:$m)
+/* 28304*/ /*Scope*/ 8, /*->28313*/
+/* 28305*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND_V_W_PSEUDO), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 28313*/ 0, /*End of Scope*/
+/* 28314*/ /*SwitchType*/ 37, MVT::v2i64,// ->28353
+/* 28316*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28318*/ OPC_Scope, 11, /*->28331*/ // 3 children in Scope
+/* 28320*/ OPC_CheckComplexPat, /*CP*/15, /*#*/1, // selectVSplatUimmInvPow2:$m #2
+/* 28323*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLRI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_inv_pow2:{ *:[v2i64] }:$m) - Complexity = 9
+ // Dst: (BCLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_inv_pow2:{ *:[v2i64] }:$m)
+/* 28331*/ /*Scope*/ 11, /*->28343*/
+/* 28332*/ OPC_CheckComplexPat, /*CP*/15, /*#*/0, // selectVSplatUimmInvPow2:$m #2
+/* 28335*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BCLRI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (and:{ *:[v2i64] } vsplat_uimm_inv_pow2:{ *:[v2i64] }:$m, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (BCLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_inv_pow2:{ *:[v2i64] }:$m)
+/* 28343*/ /*Scope*/ 8, /*->28352*/
+/* 28344*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AND_V_D_PSEUDO), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 28352*/ 0, /*End of Scope*/
+/* 28353*/ 0, // EndSwitchType
+/* 28354*/ 0, /*End of Scope*/
+/* 28355*/ /*SwitchOpcode*/ 89, TARGET_VAL(MipsISD::CIns),// ->28447
+/* 28358*/ OPC_RecordChild0, // #0 = $rs
+/* 28359*/ OPC_RecordChild1, // #1 = $pos
+/* 28360*/ OPC_MoveChild1,
+/* 28361*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 28364*/ OPC_Scope, 26, /*->28392*/ // 3 children in Scope
+/* 28366*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 28368*/ OPC_MoveParent,
+/* 28369*/ OPC_RecordChild2, // #2 = $lenm1
+/* 28370*/ OPC_MoveChild2,
+/* 28371*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 28374*/ OPC_MoveParent,
+/* 28375*/ OPC_CheckType, MVT::i64,
+/* 28377*/ OPC_CheckPatternPredicate, 55, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (!Subtarget->inMicroMipsMode())
+/* 28379*/ OPC_EmitConvertToTarget, 1,
+/* 28381*/ OPC_EmitConvertToTarget, 2,
+/* 28383*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CINS), 0,
+ MVT::i64, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsCIns:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$pos, (imm:{ *:[i32] }):$lenm1) - Complexity = 10
+ // Dst: (CINS:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$lenm1)
+/* 28392*/ /*Scope*/ 26, /*->28419*/
+/* 28393*/ OPC_CheckPredicate, 46, // Predicate_immZExt5Plus32
+/* 28395*/ OPC_MoveParent,
+/* 28396*/ OPC_RecordChild2, // #2 = $lenm1
+/* 28397*/ OPC_MoveChild2,
+/* 28398*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 28401*/ OPC_MoveParent,
+/* 28402*/ OPC_CheckType, MVT::i64,
+/* 28404*/ OPC_CheckPatternPredicate, 55, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (!Subtarget->inMicroMipsMode())
+/* 28406*/ OPC_EmitConvertToTarget, 1,
+/* 28408*/ OPC_EmitConvertToTarget, 2,
+/* 28410*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CINS32), 0,
+ MVT::i64, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsCIns:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5Plus32>>:$pos, (imm:{ *:[i32] }):$lenm1) - Complexity = 10
+ // Dst: (CINS32:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$lenm1)
+/* 28419*/ /*Scope*/ 26, /*->28446*/
+/* 28420*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 28422*/ OPC_MoveParent,
+/* 28423*/ OPC_RecordChild2, // #2 = $lenm1
+/* 28424*/ OPC_MoveChild2,
+/* 28425*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 28428*/ OPC_MoveParent,
+/* 28429*/ OPC_CheckType, MVT::i32,
+/* 28431*/ OPC_CheckPatternPredicate, 55, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (!Subtarget->inMicroMipsMode())
+/* 28433*/ OPC_EmitConvertToTarget, 1,
+/* 28435*/ OPC_EmitConvertToTarget, 2,
+/* 28437*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CINS_i32), 0,
+ MVT::i32, 3/*#Ops*/, 0, 3, 4,
+ // Src: (MipsCIns:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$pos, (imm:{ *:[i32] }):$lenm1) - Complexity = 10
+ // Dst: (CINS_i32:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$lenm1)
+/* 28446*/ 0, /*End of Scope*/
+/* 28447*/ /*SwitchOpcode*/ 55|128,1/*183*/, TARGET_VAL(ISD::ZERO_EXTEND),// ->28634
+/* 28451*/ OPC_Scope, 6|128,1/*134*/, /*->28588*/ // 2 children in Scope
+/* 28454*/ OPC_MoveChild0,
+/* 28455*/ OPC_SwitchOpcode /*2 cases */, 93, TARGET_VAL(ISD::SETCC),// ->28552
+/* 28459*/ OPC_RecordChild0, // #0 = $rs
+/* 28460*/ OPC_CheckChild0Type, MVT::i64,
+/* 28462*/ OPC_RecordChild1, // #1 = $imm10
+/* 28463*/ OPC_Scope, 48, /*->28513*/ // 2 children in Scope
+/* 28465*/ OPC_MoveChild1,
+/* 28466*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 28469*/ OPC_CheckPredicate, 49, // Predicate_immSExt10_64
+/* 28471*/ OPC_MoveParent,
+/* 28472*/ OPC_MoveChild2,
+/* 28473*/ OPC_Scope, 18, /*->28493*/ // 2 children in Scope
+/* 28475*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 28477*/ OPC_MoveParent,
+/* 28478*/ OPC_MoveParent,
+/* 28479*/ OPC_CheckType, MVT::i64,
+/* 28481*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 28483*/ OPC_EmitConvertToTarget, 1,
+/* 28485*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEQi), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt10_64>>:$imm10, SETEQ:{ *:[Other] })) - Complexity = 10
+ // Dst: (SEQi:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm10)
+/* 28493*/ /*Scope*/ 18, /*->28512*/
+/* 28494*/ OPC_CheckCondCode, ISD::SETNE,
+/* 28496*/ OPC_MoveParent,
+/* 28497*/ OPC_MoveParent,
+/* 28498*/ OPC_CheckType, MVT::i64,
+/* 28500*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 28502*/ OPC_EmitConvertToTarget, 1,
+/* 28504*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SNEi), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt10_64>>:$imm10, SETNE:{ *:[Other] })) - Complexity = 10
+ // Dst: (SNEi:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm10)
+/* 28512*/ 0, /*End of Scope*/
+/* 28513*/ /*Scope*/ 37, /*->28551*/
+/* 28514*/ OPC_MoveChild2,
+/* 28515*/ OPC_Scope, 16, /*->28533*/ // 2 children in Scope
+/* 28517*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 28519*/ OPC_MoveParent,
+/* 28520*/ OPC_MoveParent,
+/* 28521*/ OPC_CheckType, MVT::i64,
+/* 28523*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 28525*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEQ), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] })) - Complexity = 6
+ // Dst: (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 28533*/ /*Scope*/ 16, /*->28550*/
+/* 28534*/ OPC_CheckCondCode, ISD::SETNE,
+/* 28536*/ OPC_MoveParent,
+/* 28537*/ OPC_MoveParent,
+/* 28538*/ OPC_CheckType, MVT::i64,
+/* 28540*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 28542*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SNE), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] })) - Complexity = 6
+ // Dst: (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 28550*/ 0, /*End of Scope*/
+/* 28551*/ 0, /*End of Scope*/
+/* 28552*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::SHL),// ->28587
+/* 28555*/ OPC_RecordChild0, // #0 = $rt
+/* 28556*/ OPC_RecordChild1, // #1 = $imm
+/* 28557*/ OPC_MoveChild1,
+/* 28558*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 28561*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 28563*/ OPC_CheckType, MVT::i32,
+/* 28565*/ OPC_MoveParent,
+/* 28566*/ OPC_MoveParent,
+/* 28567*/ OPC_CheckType, MVT::i64,
+/* 28569*/ OPC_CheckPatternPredicate, 56, // (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 28571*/ OPC_EmitConvertToTarget, 1,
+/* 28573*/ OPC_EmitConvertToTarget, 1,
+/* 28575*/ OPC_EmitNodeXForm, 4, 3, // immZExt5To31
+/* 28578*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CINS64_32), 0,
+ MVT::i64, 3/*#Ops*/, 0, 2, 4,
+ // Src: (zext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)) - Complexity = 10
+ // Dst: (CINS64_32:{ *:[i64] } GPR32:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$imm, (immZExt5To31:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 28587*/ 0, // EndSwitchOpcode
+/* 28588*/ /*Scope*/ 44, /*->28633*/
+/* 28589*/ OPC_RecordChild0, // #0 = $src
+/* 28590*/ OPC_CheckType, MVT::i64,
+/* 28592*/ OPC_Scope, 17, /*->28611*/ // 2 children in Scope
+/* 28594*/ OPC_CheckPatternPredicate, 57, // (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 28596*/ OPC_EmitInteger, MVT::i32, 0,
+/* 28599*/ OPC_EmitInteger, MVT::i32, 32,
+/* 28602*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DEXT64_32), 0,
+ MVT::i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
+/* 28611*/ /*Scope*/ 20, /*->28632*/
+/* 28612*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 28614*/ OPC_EmitNode1, TARGET_VAL(Mips::DSLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #1
+/* 28621*/ OPC_EmitInteger, MVT::i32, 32,
+/* 28624*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRL), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
+/* 28632*/ 0, /*End of Scope*/
+/* 28633*/ 0, /*End of Scope*/
+/* 28634*/ /*SwitchOpcode*/ 4|128,13/*1668*/, TARGET_VAL(ISD::ADD),// ->30306
+/* 28638*/ OPC_Scope, 49, /*->28689*/ // 7 children in Scope
+/* 28640*/ OPC_RecordChild0, // #0 = $rt
+/* 28641*/ OPC_MoveChild1,
+/* 28642*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 28645*/ OPC_RecordChild0, // #1 = $rs
+/* 28646*/ OPC_RecordChild1, // #2 = $sa
+/* 28647*/ OPC_MoveChild1,
+/* 28648*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 28651*/ OPC_CheckPredicate, 50, // Predicate_immZExt2Lsa
+/* 28653*/ OPC_CheckType, MVT::i32,
+/* 28655*/ OPC_MoveParent,
+/* 28656*/ OPC_MoveParent,
+/* 28657*/ OPC_SwitchType /*2 cases */, 13, MVT::i32,// ->28673
+/* 28660*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28662*/ OPC_EmitConvertToTarget, 2,
+/* 28664*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LSA), 0,
+ MVT::i32, 3/*#Ops*/, 1, 0, 3,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) - Complexity = 10
+ // Dst: (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
+/* 28673*/ /*SwitchType*/ 13, MVT::i64,// ->28688
+/* 28675*/ OPC_CheckPatternPredicate, 58, // (Subtarget->hasMSA()) && (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding())
+/* 28677*/ OPC_EmitConvertToTarget, 2,
+/* 28679*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DLSA), 0,
+ MVT::i64, 3/*#Ops*/, 1, 0, 3,
+ // Src: (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) - Complexity = 10
+ // Dst: (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
+/* 28688*/ 0, // EndSwitchType
+/* 28689*/ /*Scope*/ 49, /*->28739*/
+/* 28690*/ OPC_MoveChild0,
+/* 28691*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 28694*/ OPC_RecordChild0, // #0 = $rs
+/* 28695*/ OPC_RecordChild1, // #1 = $sa
+/* 28696*/ OPC_MoveChild1,
+/* 28697*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 28700*/ OPC_CheckPredicate, 50, // Predicate_immZExt2Lsa
+/* 28702*/ OPC_CheckType, MVT::i32,
+/* 28704*/ OPC_MoveParent,
+/* 28705*/ OPC_MoveParent,
+/* 28706*/ OPC_RecordChild1, // #2 = $rt
+/* 28707*/ OPC_SwitchType /*2 cases */, 13, MVT::i32,// ->28723
+/* 28710*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 28712*/ OPC_EmitConvertToTarget, 1,
+/* 28714*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LSA), 0,
+ MVT::i32, 3/*#Ops*/, 0, 2, 3,
+ // Src: (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 10
+ // Dst: (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
+/* 28723*/ /*SwitchType*/ 13, MVT::i64,// ->28738
+/* 28725*/ OPC_CheckPatternPredicate, 58, // (Subtarget->hasMSA()) && (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding())
+/* 28727*/ OPC_EmitConvertToTarget, 1,
+/* 28729*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DLSA), 0,
+ MVT::i64, 3/*#Ops*/, 0, 2, 3,
+ // Src: (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 10
+ // Dst: (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
+/* 28738*/ 0, // EndSwitchType
+/* 28739*/ /*Scope*/ 111|128,3/*495*/, /*->29236*/
+/* 28741*/ OPC_RecordChild0, // #0 = $hi
+/* 28742*/ OPC_MoveChild1,
+/* 28743*/ OPC_SwitchOpcode /*4 cases */, 112|128,1/*240*/, TARGET_VAL(MipsISD::Lo),// ->28988
+/* 28748*/ OPC_RecordChild0, // #1 = $lo
+/* 28749*/ OPC_MoveChild0,
+/* 28750*/ OPC_SwitchOpcode /*5 cases */, 53, TARGET_VAL(ISD::TargetGlobalAddress),// ->28807
+/* 28754*/ OPC_MoveParent,
+/* 28755*/ OPC_MoveParent,
+/* 28756*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->28794
+/* 28759*/ OPC_Scope, 10, /*->28771*/ // 3 children in Scope
+/* 28761*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 28763*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tglobaladdr:{ *:[i32] }):$lo)
+/* 28771*/ /*Scope*/ 10, /*->28782*/
+/* 28772*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 28774*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AddiuRxRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (AddiuRxRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$hi, (tglobaladdr:{ *:[i32] }):$lo)
+/* 28782*/ /*Scope*/ 10, /*->28793*/
+/* 28783*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 28785*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tglobaladdr:{ *:[i32] }):$lo)
+/* 28793*/ 0, /*End of Scope*/
+/* 28794*/ /*SwitchType*/ 10, MVT::i64,// ->28806
+/* 28796*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 28798*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (MipsLo:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tglobaladdr:{ *:[i64] }):$lo)
+/* 28806*/ 0, // EndSwitchType
+/* 28807*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::TargetBlockAddress),// ->28852
+/* 28810*/ OPC_MoveParent,
+/* 28811*/ OPC_MoveParent,
+/* 28812*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->28839
+/* 28815*/ OPC_Scope, 10, /*->28827*/ // 2 children in Scope
+/* 28817*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 28819*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tblockaddress:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tblockaddress:{ *:[i32] }):$lo)
+/* 28827*/ /*Scope*/ 10, /*->28838*/
+/* 28828*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 28830*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tblockaddress:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tblockaddress:{ *:[i32] }):$lo)
+/* 28838*/ 0, /*End of Scope*/
+/* 28839*/ /*SwitchType*/ 10, MVT::i64,// ->28851
+/* 28841*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 28843*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (MipsLo:{ *:[i64] } (tblockaddress:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tblockaddress:{ *:[i64] }):$lo)
+/* 28851*/ 0, // EndSwitchType
+/* 28852*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::TargetJumpTable),// ->28897
+/* 28855*/ OPC_MoveParent,
+/* 28856*/ OPC_MoveParent,
+/* 28857*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->28884
+/* 28860*/ OPC_Scope, 10, /*->28872*/ // 2 children in Scope
+/* 28862*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 28864*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tjumptable:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tjumptable:{ *:[i32] }):$lo)
+/* 28872*/ /*Scope*/ 10, /*->28883*/
+/* 28873*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 28875*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tjumptable:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tjumptable:{ *:[i32] }):$lo)
+/* 28883*/ 0, /*End of Scope*/
+/* 28884*/ /*SwitchType*/ 10, MVT::i64,// ->28896
+/* 28886*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 28888*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (MipsLo:{ *:[i64] } (tjumptable:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tjumptable:{ *:[i64] }):$lo)
+/* 28896*/ 0, // EndSwitchType
+/* 28897*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::TargetConstantPool),// ->28942
+/* 28900*/ OPC_MoveParent,
+/* 28901*/ OPC_MoveParent,
+/* 28902*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->28929
+/* 28905*/ OPC_Scope, 10, /*->28917*/ // 2 children in Scope
+/* 28907*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 28909*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tconstpool:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tconstpool:{ *:[i32] }):$lo)
+/* 28917*/ /*Scope*/ 10, /*->28928*/
+/* 28918*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 28920*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tconstpool:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tconstpool:{ *:[i32] }):$lo)
+/* 28928*/ 0, /*End of Scope*/
+/* 28929*/ /*SwitchType*/ 10, MVT::i64,// ->28941
+/* 28931*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 28933*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (MipsLo:{ *:[i64] } (tconstpool:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tconstpool:{ *:[i64] }):$lo)
+/* 28941*/ 0, // EndSwitchType
+/* 28942*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::TargetGlobalTLSAddress),// ->28987
+/* 28945*/ OPC_MoveParent,
+/* 28946*/ OPC_MoveParent,
+/* 28947*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->28974
+/* 28950*/ OPC_Scope, 10, /*->28962*/ // 2 children in Scope
+/* 28952*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 28954*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tglobaltlsaddr:{ *:[i32] }):$lo)
+/* 28962*/ /*Scope*/ 10, /*->28973*/
+/* 28963*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 28965*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (MipsLo:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$lo)) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tglobaltlsaddr:{ *:[i32] }):$lo)
+/* 28973*/ 0, /*End of Scope*/
+/* 28974*/ /*SwitchType*/ 10, MVT::i64,// ->28986
+/* 28976*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 28978*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (MipsLo:{ *:[i64] } (tglobaltlsaddr:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tglobaltlsaddr:{ *:[i64] }):$lo)
+/* 28986*/ 0, // EndSwitchType
+/* 28987*/ 0, // EndSwitchOpcode
+/* 28988*/ /*SwitchOpcode*/ 94, TARGET_VAL(MipsISD::GPRel),// ->29085
+/* 28991*/ OPC_RecordChild0, // #1 = $in
+/* 28992*/ OPC_MoveChild0,
+/* 28993*/ OPC_SwitchOpcode /*2 cases */, 42, TARGET_VAL(ISD::TargetGlobalAddress),// ->29039
+/* 28997*/ OPC_MoveParent,
+/* 28998*/ OPC_MoveParent,
+/* 28999*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->29026
+/* 29002*/ OPC_Scope, 10, /*->29014*/ // 2 children in Scope
+/* 29004*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29006*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (MipsGPRel:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in)) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in)
+/* 29014*/ /*Scope*/ 10, /*->29025*/
+/* 29015*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29017*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (MipsGPRel:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in)) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in)
+/* 29025*/ 0, /*End of Scope*/
+/* 29026*/ /*SwitchType*/ 10, MVT::i64,// ->29038
+/* 29028*/ OPC_CheckPatternPredicate, 60, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64())
+/* 29030*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (MipsGPRel:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tglobaladdr:{ *:[i64] }):$in)
+/* 29038*/ 0, // EndSwitchType
+/* 29039*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::TargetConstantPool),// ->29084
+/* 29042*/ OPC_MoveParent,
+/* 29043*/ OPC_MoveParent,
+/* 29044*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->29071
+/* 29047*/ OPC_Scope, 10, /*->29059*/ // 2 children in Scope
+/* 29049*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29051*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (MipsGPRel:{ *:[i32] } (tconstpool:{ *:[i32] }):$in)) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tconstpool:{ *:[i32] }):$in)
+/* 29059*/ /*Scope*/ 10, /*->29070*/
+/* 29060*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29062*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (MipsGPRel:{ *:[i32] } (tconstpool:{ *:[i32] }):$in)) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tconstpool:{ *:[i32] }):$in)
+/* 29070*/ 0, /*End of Scope*/
+/* 29071*/ /*SwitchType*/ 10, MVT::i64,// ->29083
+/* 29073*/ OPC_CheckPatternPredicate, 60, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64())
+/* 29075*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (MipsGPRel:{ *:[i64] } (tconstpool:{ *:[i64] }):$in)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tconstpool:{ *:[i64] }):$in)
+/* 29083*/ 0, // EndSwitchType
+/* 29084*/ 0, // EndSwitchOpcode
+/* 29085*/ /*SwitchOpcode*/ 72, TARGET_VAL(MipsISD::Higher),// ->29160
+/* 29088*/ OPC_RecordChild0, // #1 = $lo
+/* 29089*/ OPC_MoveChild0,
+/* 29090*/ OPC_SwitchOpcode /*4 cases */, 14, TARGET_VAL(ISD::TargetGlobalAddress),// ->29108
+/* 29094*/ OPC_MoveParent,
+/* 29095*/ OPC_MoveParent,
+/* 29096*/ OPC_CheckType, MVT::i64,
+/* 29098*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29100*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (MipsHigher:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tglobaladdr:{ *:[i64] }):$lo)
+/* 29108*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::TargetBlockAddress),// ->29125
+/* 29111*/ OPC_MoveParent,
+/* 29112*/ OPC_MoveParent,
+/* 29113*/ OPC_CheckType, MVT::i64,
+/* 29115*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29117*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (MipsHigher:{ *:[i64] } (tblockaddress:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tblockaddress:{ *:[i64] }):$lo)
+/* 29125*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::TargetJumpTable),// ->29142
+/* 29128*/ OPC_MoveParent,
+/* 29129*/ OPC_MoveParent,
+/* 29130*/ OPC_CheckType, MVT::i64,
+/* 29132*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29134*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (MipsHigher:{ *:[i64] } (tjumptable:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tjumptable:{ *:[i64] }):$lo)
+/* 29142*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::TargetConstantPool),// ->29159
+/* 29145*/ OPC_MoveParent,
+/* 29146*/ OPC_MoveParent,
+/* 29147*/ OPC_CheckType, MVT::i64,
+/* 29149*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29151*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (MipsHigher:{ *:[i64] } (tconstpool:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tconstpool:{ *:[i64] }):$lo)
+/* 29159*/ 0, // EndSwitchOpcode
+/* 29160*/ /*SwitchOpcode*/ 72, TARGET_VAL(MipsISD::Hi),// ->29235
+/* 29163*/ OPC_RecordChild0, // #1 = $lo
+/* 29164*/ OPC_MoveChild0,
+/* 29165*/ OPC_SwitchOpcode /*4 cases */, 14, TARGET_VAL(ISD::TargetGlobalAddress),// ->29183
+/* 29169*/ OPC_MoveParent,
+/* 29170*/ OPC_MoveParent,
+/* 29171*/ OPC_CheckType, MVT::i64,
+/* 29173*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29175*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (MipsHi:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tglobaladdr:{ *:[i64] }):$lo)
+/* 29183*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::TargetBlockAddress),// ->29200
+/* 29186*/ OPC_MoveParent,
+/* 29187*/ OPC_MoveParent,
+/* 29188*/ OPC_CheckType, MVT::i64,
+/* 29190*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29192*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (MipsHi:{ *:[i64] } (tblockaddress:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tblockaddress:{ *:[i64] }):$lo)
+/* 29200*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::TargetJumpTable),// ->29217
+/* 29203*/ OPC_MoveParent,
+/* 29204*/ OPC_MoveParent,
+/* 29205*/ OPC_CheckType, MVT::i64,
+/* 29207*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29209*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (MipsHi:{ *:[i64] } (tjumptable:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tjumptable:{ *:[i64] }):$lo)
+/* 29217*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::TargetConstantPool),// ->29234
+/* 29220*/ OPC_MoveParent,
+/* 29221*/ OPC_MoveParent,
+/* 29222*/ OPC_CheckType, MVT::i64,
+/* 29224*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29226*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (MipsHi:{ *:[i64] } (tconstpool:{ *:[i64] }):$lo)) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tconstpool:{ *:[i64] }):$lo)
+/* 29234*/ 0, // EndSwitchOpcode
+/* 29235*/ 0, // EndSwitchOpcode
+/* 29236*/ /*Scope*/ 125|128,3/*509*/, /*->29747*/
+/* 29238*/ OPC_MoveChild0,
+/* 29239*/ OPC_SwitchOpcode /*4 cases */, 117|128,1/*245*/, TARGET_VAL(MipsISD::Lo),// ->29489
+/* 29244*/ OPC_RecordChild0, // #0 = $lo
+/* 29245*/ OPC_MoveChild0,
+/* 29246*/ OPC_SwitchOpcode /*5 cases */, 54, TARGET_VAL(ISD::TargetGlobalAddress),// ->29304
+/* 29250*/ OPC_MoveParent,
+/* 29251*/ OPC_MoveParent,
+/* 29252*/ OPC_RecordChild1, // #1 = $hi
+/* 29253*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->29291
+/* 29256*/ OPC_Scope, 10, /*->29268*/ // 3 children in Scope
+/* 29258*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29260*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tglobaladdr:{ *:[i32] }):$lo)
+/* 29268*/ /*Scope*/ 10, /*->29279*/
+/* 29269*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 29271*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AddiuRxRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$lo), CPU16Regs:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (AddiuRxRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$hi, (tglobaladdr:{ *:[i32] }):$lo)
+/* 29279*/ /*Scope*/ 10, /*->29290*/
+/* 29280*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29282*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tglobaladdr:{ *:[i32] }):$lo)
+/* 29290*/ 0, /*End of Scope*/
+/* 29291*/ /*SwitchType*/ 10, MVT::i64,// ->29303
+/* 29293*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29295*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsLo:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$lo), GPR64Opnd:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tglobaladdr:{ *:[i64] }):$lo)
+/* 29303*/ 0, // EndSwitchType
+/* 29304*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::TargetBlockAddress),// ->29350
+/* 29307*/ OPC_MoveParent,
+/* 29308*/ OPC_MoveParent,
+/* 29309*/ OPC_RecordChild1, // #1 = $hi
+/* 29310*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->29337
+/* 29313*/ OPC_Scope, 10, /*->29325*/ // 2 children in Scope
+/* 29315*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29317*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tblockaddress:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tblockaddress:{ *:[i32] }):$lo)
+/* 29325*/ /*Scope*/ 10, /*->29336*/
+/* 29326*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29328*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tblockaddress:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tblockaddress:{ *:[i32] }):$lo)
+/* 29336*/ 0, /*End of Scope*/
+/* 29337*/ /*SwitchType*/ 10, MVT::i64,// ->29349
+/* 29339*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29341*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsLo:{ *:[i64] } (tblockaddress:{ *:[i64] }):$lo), GPR64Opnd:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tblockaddress:{ *:[i64] }):$lo)
+/* 29349*/ 0, // EndSwitchType
+/* 29350*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::TargetJumpTable),// ->29396
+/* 29353*/ OPC_MoveParent,
+/* 29354*/ OPC_MoveParent,
+/* 29355*/ OPC_RecordChild1, // #1 = $hi
+/* 29356*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->29383
+/* 29359*/ OPC_Scope, 10, /*->29371*/ // 2 children in Scope
+/* 29361*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29363*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tjumptable:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tjumptable:{ *:[i32] }):$lo)
+/* 29371*/ /*Scope*/ 10, /*->29382*/
+/* 29372*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29374*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tjumptable:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tjumptable:{ *:[i32] }):$lo)
+/* 29382*/ 0, /*End of Scope*/
+/* 29383*/ /*SwitchType*/ 10, MVT::i64,// ->29395
+/* 29385*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29387*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsLo:{ *:[i64] } (tjumptable:{ *:[i64] }):$lo), GPR64Opnd:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tjumptable:{ *:[i64] }):$lo)
+/* 29395*/ 0, // EndSwitchType
+/* 29396*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::TargetConstantPool),// ->29442
+/* 29399*/ OPC_MoveParent,
+/* 29400*/ OPC_MoveParent,
+/* 29401*/ OPC_RecordChild1, // #1 = $hi
+/* 29402*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->29429
+/* 29405*/ OPC_Scope, 10, /*->29417*/ // 2 children in Scope
+/* 29407*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29409*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tconstpool:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tconstpool:{ *:[i32] }):$lo)
+/* 29417*/ /*Scope*/ 10, /*->29428*/
+/* 29418*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29420*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tconstpool:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tconstpool:{ *:[i32] }):$lo)
+/* 29428*/ 0, /*End of Scope*/
+/* 29429*/ /*SwitchType*/ 10, MVT::i64,// ->29441
+/* 29431*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29433*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsLo:{ *:[i64] } (tconstpool:{ *:[i64] }):$lo), GPR64Opnd:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tconstpool:{ *:[i64] }):$lo)
+/* 29441*/ 0, // EndSwitchType
+/* 29442*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::TargetGlobalTLSAddress),// ->29488
+/* 29445*/ OPC_MoveParent,
+/* 29446*/ OPC_MoveParent,
+/* 29447*/ OPC_RecordChild1, // #1 = $hi
+/* 29448*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->29475
+/* 29451*/ OPC_Scope, 10, /*->29463*/ // 2 children in Scope
+/* 29453*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29455*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tglobaltlsaddr:{ *:[i32] }):$lo)
+/* 29463*/ /*Scope*/ 10, /*->29474*/
+/* 29464*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29466*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsLo:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$lo), GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$hi, (tglobaltlsaddr:{ *:[i32] }):$lo)
+/* 29474*/ 0, /*End of Scope*/
+/* 29475*/ /*SwitchType*/ 10, MVT::i64,// ->29487
+/* 29477*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29479*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsLo:{ *:[i64] } (tglobaltlsaddr:{ *:[i64] }):$lo), GPR64Opnd:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$hi, (tglobaltlsaddr:{ *:[i64] }):$lo)
+/* 29487*/ 0, // EndSwitchType
+/* 29488*/ 0, // EndSwitchOpcode
+/* 29489*/ /*SwitchOpcode*/ 96, TARGET_VAL(MipsISD::GPRel),// ->29588
+/* 29492*/ OPC_RecordChild0, // #0 = $in
+/* 29493*/ OPC_MoveChild0,
+/* 29494*/ OPC_SwitchOpcode /*2 cases */, 43, TARGET_VAL(ISD::TargetGlobalAddress),// ->29541
+/* 29498*/ OPC_MoveParent,
+/* 29499*/ OPC_MoveParent,
+/* 29500*/ OPC_RecordChild1, // #1 = $gp
+/* 29501*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->29528
+/* 29504*/ OPC_Scope, 10, /*->29516*/ // 2 children in Scope
+/* 29506*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29508*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsGPRel:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in), GPR32:{ *:[i32] }:$gp) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in)
+/* 29516*/ /*Scope*/ 10, /*->29527*/
+/* 29517*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29519*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsGPRel:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in), GPR32:{ *:[i32] }:$gp) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in)
+/* 29527*/ 0, /*End of Scope*/
+/* 29528*/ /*SwitchType*/ 10, MVT::i64,// ->29540
+/* 29530*/ OPC_CheckPatternPredicate, 60, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64())
+/* 29532*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsGPRel:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in), GPR64:{ *:[i64] }:$gp) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tglobaladdr:{ *:[i64] }):$in)
+/* 29540*/ 0, // EndSwitchType
+/* 29541*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::TargetConstantPool),// ->29587
+/* 29544*/ OPC_MoveParent,
+/* 29545*/ OPC_MoveParent,
+/* 29546*/ OPC_RecordChild1, // #1 = $gp
+/* 29547*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->29574
+/* 29550*/ OPC_Scope, 10, /*->29562*/ // 2 children in Scope
+/* 29552*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29554*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsGPRel:{ *:[i32] } (tconstpool:{ *:[i32] }):$in), GPR32:{ *:[i32] }:$gp) - Complexity = 9
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tconstpool:{ *:[i32] }):$in)
+/* 29562*/ /*Scope*/ 10, /*->29573*/
+/* 29563*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29565*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i32] } (MipsGPRel:{ *:[i32] } (tconstpool:{ *:[i32] }):$in), GPR32:{ *:[i32] }:$gp) - Complexity = 9
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tconstpool:{ *:[i32] }):$in)
+/* 29573*/ 0, /*End of Scope*/
+/* 29574*/ /*SwitchType*/ 10, MVT::i64,// ->29586
+/* 29576*/ OPC_CheckPatternPredicate, 60, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64())
+/* 29578*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsGPRel:{ *:[i64] } (tconstpool:{ *:[i64] }):$in), GPR64:{ *:[i64] }:$gp) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tconstpool:{ *:[i64] }):$in)
+/* 29586*/ 0, // EndSwitchType
+/* 29587*/ 0, // EndSwitchOpcode
+/* 29588*/ /*SwitchOpcode*/ 76, TARGET_VAL(MipsISD::Higher),// ->29667
+/* 29591*/ OPC_RecordChild0, // #0 = $lo
+/* 29592*/ OPC_MoveChild0,
+/* 29593*/ OPC_SwitchOpcode /*4 cases */, 15, TARGET_VAL(ISD::TargetGlobalAddress),// ->29612
+/* 29597*/ OPC_MoveParent,
+/* 29598*/ OPC_MoveParent,
+/* 29599*/ OPC_RecordChild1, // #1 = $hi
+/* 29600*/ OPC_CheckType, MVT::i64,
+/* 29602*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29604*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsHigher:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$lo), GPR64:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tglobaladdr:{ *:[i64] }):$lo)
+/* 29612*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::TargetBlockAddress),// ->29630
+/* 29615*/ OPC_MoveParent,
+/* 29616*/ OPC_MoveParent,
+/* 29617*/ OPC_RecordChild1, // #1 = $hi
+/* 29618*/ OPC_CheckType, MVT::i64,
+/* 29620*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29622*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsHigher:{ *:[i64] } (tblockaddress:{ *:[i64] }):$lo), GPR64:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tblockaddress:{ *:[i64] }):$lo)
+/* 29630*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::TargetJumpTable),// ->29648
+/* 29633*/ OPC_MoveParent,
+/* 29634*/ OPC_MoveParent,
+/* 29635*/ OPC_RecordChild1, // #1 = $hi
+/* 29636*/ OPC_CheckType, MVT::i64,
+/* 29638*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29640*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsHigher:{ *:[i64] } (tjumptable:{ *:[i64] }):$lo), GPR64:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tjumptable:{ *:[i64] }):$lo)
+/* 29648*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::TargetConstantPool),// ->29666
+/* 29651*/ OPC_MoveParent,
+/* 29652*/ OPC_MoveParent,
+/* 29653*/ OPC_RecordChild1, // #1 = $hi
+/* 29654*/ OPC_CheckType, MVT::i64,
+/* 29656*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29658*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsHigher:{ *:[i64] } (tconstpool:{ *:[i64] }):$lo), GPR64:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tconstpool:{ *:[i64] }):$lo)
+/* 29666*/ 0, // EndSwitchOpcode
+/* 29667*/ /*SwitchOpcode*/ 76, TARGET_VAL(MipsISD::Hi),// ->29746
+/* 29670*/ OPC_RecordChild0, // #0 = $lo
+/* 29671*/ OPC_MoveChild0,
+/* 29672*/ OPC_SwitchOpcode /*4 cases */, 15, TARGET_VAL(ISD::TargetGlobalAddress),// ->29691
+/* 29676*/ OPC_MoveParent,
+/* 29677*/ OPC_MoveParent,
+/* 29678*/ OPC_RecordChild1, // #1 = $hi
+/* 29679*/ OPC_CheckType, MVT::i64,
+/* 29681*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29683*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsHi:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$lo), GPR64:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tglobaladdr:{ *:[i64] }):$lo)
+/* 29691*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::TargetBlockAddress),// ->29709
+/* 29694*/ OPC_MoveParent,
+/* 29695*/ OPC_MoveParent,
+/* 29696*/ OPC_RecordChild1, // #1 = $hi
+/* 29697*/ OPC_CheckType, MVT::i64,
+/* 29699*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29701*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsHi:{ *:[i64] } (tblockaddress:{ *:[i64] }):$lo), GPR64:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tblockaddress:{ *:[i64] }):$lo)
+/* 29709*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::TargetJumpTable),// ->29727
+/* 29712*/ OPC_MoveParent,
+/* 29713*/ OPC_MoveParent,
+/* 29714*/ OPC_RecordChild1, // #1 = $hi
+/* 29715*/ OPC_CheckType, MVT::i64,
+/* 29717*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29719*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsHi:{ *:[i64] } (tjumptable:{ *:[i64] }):$lo), GPR64:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tjumptable:{ *:[i64] }):$lo)
+/* 29727*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::TargetConstantPool),// ->29745
+/* 29730*/ OPC_MoveParent,
+/* 29731*/ OPC_MoveParent,
+/* 29732*/ OPC_RecordChild1, // #1 = $hi
+/* 29733*/ OPC_CheckType, MVT::i64,
+/* 29735*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 29737*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (add:{ *:[i64] } (MipsHi:{ *:[i64] } (tconstpool:{ *:[i64] }):$lo), GPR64:{ *:[i64] }:$hi) - Complexity = 9
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$hi, (tconstpool:{ *:[i64] }):$lo)
+/* 29745*/ 0, // EndSwitchOpcode
+/* 29746*/ 0, // EndSwitchOpcode
+/* 29747*/ /*Scope*/ 32|128,3/*416*/, /*->30165*/
+/* 29749*/ OPC_RecordChild0, // #0 = $rs
+/* 29750*/ OPC_Scope, 93|128,2/*349*/, /*->30102*/ // 2 children in Scope
+/* 29753*/ OPC_RecordChild1, // #1 = $imm16
+/* 29754*/ OPC_Scope, 18|128,1/*146*/, /*->29903*/ // 7 children in Scope
+/* 29757*/ OPC_MoveChild1,
+/* 29758*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 29761*/ OPC_Scope, 33, /*->29796*/ // 6 children in Scope
+/* 29763*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 29765*/ OPC_MoveParent,
+/* 29766*/ OPC_SwitchType /*2 cases */, 12, MVT::i32,// ->29781
+/* 29769*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29771*/ OPC_EmitConvertToTarget, 1,
+/* 29773*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16) - Complexity = 7
+ // Dst: (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
+/* 29781*/ /*SwitchType*/ 12, MVT::i64,// ->29795
+/* 29783*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29785*/ OPC_EmitConvertToTarget, 1,
+/* 29787*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$imm16) - Complexity = 7
+ // Dst: (DADDiu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm16)
+/* 29795*/ 0, // EndSwitchType
+/* 29796*/ /*Scope*/ 17, /*->29814*/
+/* 29797*/ OPC_CheckPredicate, 51, // Predicate_immSExt8
+/* 29799*/ OPC_MoveParent,
+/* 29800*/ OPC_CheckType, MVT::i32,
+/* 29802*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 29804*/ OPC_EmitConvertToTarget, 1,
+/* 29806*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AddiuRxRxImm16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immSExt8>>:$imm) - Complexity = 7
+ // Dst: (AddiuRxRxImm16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immSExt8>>:$imm)
+/* 29814*/ /*Scope*/ 17, /*->29832*/
+/* 29815*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 29817*/ OPC_MoveParent,
+/* 29818*/ OPC_CheckType, MVT::i32,
+/* 29820*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 29822*/ OPC_EmitConvertToTarget, 1,
+/* 29824*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AddiuRxRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm) - Complexity = 7
+ // Dst: (AddiuRxRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm)
+/* 29832*/ /*Scope*/ 17, /*->29850*/
+/* 29833*/ OPC_CheckPredicate, 52, // Predicate_immSExtAddiur2
+/* 29835*/ OPC_MoveParent,
+/* 29836*/ OPC_CheckType, MVT::i32,
+/* 29838*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29840*/ OPC_EmitConvertToTarget, 1,
+/* 29842*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDIUR2_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) - Complexity = 7
+ // Dst: (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
+/* 29850*/ /*Scope*/ 17, /*->29868*/
+/* 29851*/ OPC_CheckPredicate, 53, // Predicate_immSExtAddius5
+/* 29853*/ OPC_MoveParent,
+/* 29854*/ OPC_CheckType, MVT::i32,
+/* 29856*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29858*/ OPC_EmitConvertToTarget, 1,
+/* 29860*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDIUS5_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) - Complexity = 7
+ // Dst: (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
+/* 29868*/ /*Scope*/ 33, /*->29902*/
+/* 29869*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 29871*/ OPC_MoveParent,
+/* 29872*/ OPC_CheckType, MVT::i32,
+/* 29874*/ OPC_Scope, 12, /*->29888*/ // 2 children in Scope
+/* 29876*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 29878*/ OPC_EmitConvertToTarget, 1,
+/* 29880*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm) - Complexity = 7
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm)
+/* 29888*/ /*Scope*/ 12, /*->29901*/
+/* 29889*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 29891*/ OPC_EmitConvertToTarget, 1,
+/* 29893*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDIU_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16) - Complexity = 7
+ // Dst: (ADDIU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
+/* 29901*/ 0, /*End of Scope*/
+/* 29902*/ 0, /*End of Scope*/
+/* 29903*/ /*Scope*/ 60, /*->29964*/
+/* 29904*/ OPC_CheckType, MVT::i32,
+/* 29906*/ OPC_Scope, 10, /*->29918*/ // 4 children in Scope
+/* 29908*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 29910*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU16_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) - Complexity = 4
+ // Dst: (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+/* 29918*/ /*Scope*/ 10, /*->29929*/
+/* 29919*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29921*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 29929*/ /*Scope*/ 10, /*->29940*/
+/* 29930*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 29932*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AdduRxRyRz16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) - Complexity = 3
+ // Dst: (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+/* 29940*/ /*Scope*/ 22, /*->29963*/
+/* 29941*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 29943*/ OPC_Scope, 8, /*->29953*/ // 2 children in Scope
+/* 29945*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU16_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+/* 29953*/ /*Scope*/ 8, /*->29962*/
+/* 29954*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 29962*/ 0, /*End of Scope*/
+/* 29963*/ 0, /*End of Scope*/
+/* 29964*/ /*Scope*/ 12, /*->29977*/
+/* 29965*/ OPC_CheckType, MVT::i64,
+/* 29967*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 29969*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 29977*/ /*Scope*/ 30, /*->30008*/
+/* 29978*/ OPC_CheckType, MVT::v16i8,
+/* 29980*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 29982*/ OPC_Scope, 11, /*->29995*/ // 2 children in Scope
+/* 29984*/ OPC_CheckComplexPat, /*CP*/16, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 29987*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm) - Complexity = 9
+ // Dst: (ADDVI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 29995*/ /*Scope*/ 11, /*->30007*/
+/* 29996*/ OPC_CheckComplexPat, /*CP*/16, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 29999*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (add:{ *:[v16i8] } vsplati8_uimm5:{ *:[v16i8] }:$imm, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (ADDVI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 30007*/ 0, /*End of Scope*/
+/* 30008*/ /*Scope*/ 30, /*->30039*/
+/* 30009*/ OPC_CheckType, MVT::v8i16,
+/* 30011*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30013*/ OPC_Scope, 11, /*->30026*/ // 2 children in Scope
+/* 30015*/ OPC_CheckComplexPat, /*CP*/17, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 30018*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm) - Complexity = 9
+ // Dst: (ADDVI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 30026*/ /*Scope*/ 11, /*->30038*/
+/* 30027*/ OPC_CheckComplexPat, /*CP*/17, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 30030*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (add:{ *:[v8i16] } vsplati16_uimm5:{ *:[v8i16] }:$imm, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (ADDVI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 30038*/ 0, /*End of Scope*/
+/* 30039*/ /*Scope*/ 30, /*->30070*/
+/* 30040*/ OPC_CheckType, MVT::v4i32,
+/* 30042*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30044*/ OPC_Scope, 11, /*->30057*/ // 2 children in Scope
+/* 30046*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 30049*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm) - Complexity = 9
+ // Dst: (ADDVI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 30057*/ /*Scope*/ 11, /*->30069*/
+/* 30058*/ OPC_CheckComplexPat, /*CP*/18, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 30061*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (add:{ *:[v4i32] } vsplati32_uimm5:{ *:[v4i32] }:$imm, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (ADDVI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 30069*/ 0, /*End of Scope*/
+/* 30070*/ /*Scope*/ 30, /*->30101*/
+/* 30071*/ OPC_CheckType, MVT::v2i64,
+/* 30073*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30075*/ OPC_Scope, 11, /*->30088*/ // 2 children in Scope
+/* 30077*/ OPC_CheckComplexPat, /*CP*/19, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 30080*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm) - Complexity = 9
+ // Dst: (ADDVI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 30088*/ /*Scope*/ 11, /*->30100*/
+/* 30089*/ OPC_CheckComplexPat, /*CP*/19, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 30092*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (add:{ *:[v2i64] } vsplati64_uimm5:{ *:[v2i64] }:$imm, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (ADDVI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 30100*/ 0, /*End of Scope*/
+/* 30101*/ 0, /*End of Scope*/
+/* 30102*/ /*Scope*/ 61, /*->30164*/
+/* 30103*/ OPC_MoveChild1,
+/* 30104*/ OPC_CheckOpcode, TARGET_VAL(ISD::MUL),
+/* 30107*/ OPC_RecordChild0, // #1 = $ws
+/* 30108*/ OPC_RecordChild1, // #2 = $wt
+/* 30109*/ OPC_MoveParent,
+/* 30110*/ OPC_SwitchType /*4 cases */, 11, MVT::v16i8,// ->30124
+/* 30113*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30115*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDV_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 1, 2,
+ // Src: (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) - Complexity = 6
+ // Dst: (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 30124*/ /*SwitchType*/ 11, MVT::v8i16,// ->30137
+/* 30126*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30128*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDV_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) - Complexity = 6
+ // Dst: (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 30137*/ /*SwitchType*/ 11, MVT::v4i32,// ->30150
+/* 30139*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30141*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDV_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) - Complexity = 6
+ // Dst: (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 30150*/ /*SwitchType*/ 11, MVT::v2i64,// ->30163
+/* 30152*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30154*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDV_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) - Complexity = 6
+ // Dst: (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 30163*/ 0, // EndSwitchType
+/* 30164*/ 0, /*End of Scope*/
+/* 30165*/ /*Scope*/ 62, /*->30228*/
+/* 30166*/ OPC_MoveChild0,
+/* 30167*/ OPC_CheckOpcode, TARGET_VAL(ISD::MUL),
+/* 30170*/ OPC_RecordChild0, // #0 = $ws
+/* 30171*/ OPC_RecordChild1, // #1 = $wt
+/* 30172*/ OPC_MoveParent,
+/* 30173*/ OPC_RecordChild1, // #2 = $wd_in
+/* 30174*/ OPC_SwitchType /*4 cases */, 11, MVT::v16i8,// ->30188
+/* 30177*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30179*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDV_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 2, 0, 1,
+ // Src: (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) - Complexity = 6
+ // Dst: (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 30188*/ /*SwitchType*/ 11, MVT::v8i16,// ->30201
+/* 30190*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30192*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDV_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 2, 0, 1,
+ // Src: (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) - Complexity = 6
+ // Dst: (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 30201*/ /*SwitchType*/ 11, MVT::v4i32,// ->30214
+/* 30203*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30205*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDV_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) - Complexity = 6
+ // Dst: (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 30214*/ /*SwitchType*/ 11, MVT::v2i64,// ->30227
+/* 30216*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30218*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDV_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) - Complexity = 6
+ // Dst: (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 30227*/ 0, // EndSwitchType
+/* 30228*/ /*Scope*/ 76, /*->30305*/
+/* 30229*/ OPC_RecordChild0, // #0 = $a
+/* 30230*/ OPC_RecordChild1, // #1 = $b
+/* 30231*/ OPC_SwitchType /*6 cases */, 10, MVT::v2i16,// ->30244
+/* 30234*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 30236*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDQ_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) - Complexity = 3
+ // Dst: (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+/* 30244*/ /*SwitchType*/ 10, MVT::v4i8,// ->30256
+/* 30246*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 30248*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDU_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) - Complexity = 3
+ // Dst: (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
+/* 30256*/ /*SwitchType*/ 10, MVT::v16i8,// ->30268
+/* 30258*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30260*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDV_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 30268*/ /*SwitchType*/ 10, MVT::v8i16,// ->30280
+/* 30270*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30272*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDV_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 30280*/ /*SwitchType*/ 10, MVT::v4i32,// ->30292
+/* 30282*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30284*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDV_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 30292*/ /*SwitchType*/ 10, MVT::v2i64,// ->30304
+/* 30294*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 30296*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDV_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 30304*/ 0, // EndSwitchType
+/* 30305*/ 0, /*End of Scope*/
+/* 30306*/ /*SwitchOpcode*/ 101|128,4/*613*/, TARGET_VAL(ISD::SIGN_EXTEND),// ->30923
+/* 30310*/ OPC_Scope, 84|128,4/*596*/, /*->30909*/ // 2 children in Scope
+/* 30313*/ OPC_MoveChild0,
+/* 30314*/ OPC_SwitchOpcode /*12 cases */, 73, TARGET_VAL(ISD::ADD),// ->30391
+/* 30318*/ OPC_RecordChild0, // #0 = $src
+/* 30319*/ OPC_RecordChild1, // #1 = $imm16
+/* 30320*/ OPC_Scope, 38, /*->30360*/ // 2 children in Scope
+/* 30322*/ OPC_MoveChild1,
+/* 30323*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 30326*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 30328*/ OPC_MoveParent,
+/* 30329*/ OPC_MoveParent,
+/* 30330*/ OPC_CheckType, MVT::i64,
+/* 30332*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30338*/ OPC_EmitConvertToTarget, 1,
+/* 30340*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
+/* 30348*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30351*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 5,
+ // Src: (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16)) - Complexity = 10
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16), sub_32:{ *:[i32] })
+/* 30360*/ /*Scope*/ 29, /*->30390*/
+/* 30361*/ OPC_MoveParent,
+/* 30362*/ OPC_CheckType, MVT::i64,
+/* 30364*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30370*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30378*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30381*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30390*/ 0, /*End of Scope*/
+/* 30391*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SHL),// ->30471
+/* 30394*/ OPC_RecordChild0, // #0 = $src
+/* 30395*/ OPC_RecordChild1, // #1 = $imm5
+/* 30396*/ OPC_Scope, 40, /*->30438*/ // 2 children in Scope
+/* 30398*/ OPC_MoveChild1,
+/* 30399*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 30402*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 30404*/ OPC_CheckType, MVT::i32,
+/* 30406*/ OPC_MoveParent,
+/* 30407*/ OPC_MoveParent,
+/* 30408*/ OPC_CheckType, MVT::i64,
+/* 30410*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30416*/ OPC_EmitConvertToTarget, 1,
+/* 30418*/ OPC_EmitNode1, TARGET_VAL(Mips::SLL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
+/* 30426*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30429*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 5,
+ // Src: (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) - Complexity = 10
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
+/* 30438*/ /*Scope*/ 31, /*->30470*/
+/* 30439*/ OPC_CheckChild1Type, MVT::i32,
+/* 30441*/ OPC_MoveParent,
+/* 30442*/ OPC_CheckType, MVT::i64,
+/* 30444*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30450*/ OPC_EmitNode1, TARGET_VAL(Mips::SLLV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30458*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30461*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30470*/ 0, /*End of Scope*/
+/* 30471*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SRL),// ->30551
+/* 30474*/ OPC_RecordChild0, // #0 = $src
+/* 30475*/ OPC_RecordChild1, // #1 = $imm5
+/* 30476*/ OPC_Scope, 40, /*->30518*/ // 2 children in Scope
+/* 30478*/ OPC_MoveChild1,
+/* 30479*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 30482*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 30484*/ OPC_CheckType, MVT::i32,
+/* 30486*/ OPC_MoveParent,
+/* 30487*/ OPC_MoveParent,
+/* 30488*/ OPC_CheckType, MVT::i64,
+/* 30490*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30496*/ OPC_EmitConvertToTarget, 1,
+/* 30498*/ OPC_EmitNode1, TARGET_VAL(Mips::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
+/* 30506*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30509*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 5,
+ // Src: (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) - Complexity = 10
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
+/* 30518*/ /*Scope*/ 31, /*->30550*/
+/* 30519*/ OPC_CheckChild1Type, MVT::i32,
+/* 30521*/ OPC_MoveParent,
+/* 30522*/ OPC_CheckType, MVT::i64,
+/* 30524*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30530*/ OPC_EmitNode1, TARGET_VAL(Mips::SRLV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30538*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30541*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30550*/ 0, /*End of Scope*/
+/* 30551*/ /*SwitchOpcode*/ 77, TARGET_VAL(ISD::SRA),// ->30631
+/* 30554*/ OPC_RecordChild0, // #0 = $src
+/* 30555*/ OPC_RecordChild1, // #1 = $imm5
+/* 30556*/ OPC_Scope, 40, /*->30598*/ // 2 children in Scope
+/* 30558*/ OPC_MoveChild1,
+/* 30559*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 30562*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 30564*/ OPC_CheckType, MVT::i32,
+/* 30566*/ OPC_MoveParent,
+/* 30567*/ OPC_MoveParent,
+/* 30568*/ OPC_CheckType, MVT::i64,
+/* 30570*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30576*/ OPC_EmitConvertToTarget, 1,
+/* 30578*/ OPC_EmitNode1, TARGET_VAL(Mips::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
+/* 30586*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30589*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 4, 5,
+ // Src: (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5)) - Complexity = 10
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
+/* 30598*/ /*Scope*/ 31, /*->30630*/
+/* 30599*/ OPC_CheckChild1Type, MVT::i32,
+/* 30601*/ OPC_MoveParent,
+/* 30602*/ OPC_CheckType, MVT::i64,
+/* 30604*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30610*/ OPC_EmitNode1, TARGET_VAL(Mips::SRAV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30618*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30621*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30630*/ 0, /*End of Scope*/
+/* 30631*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::SUB),// ->30665
+/* 30634*/ OPC_RecordChild0, // #0 = $src
+/* 30635*/ OPC_RecordChild1, // #1 = $src2
+/* 30636*/ OPC_MoveParent,
+/* 30637*/ OPC_CheckType, MVT::i64,
+/* 30639*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30645*/ OPC_EmitNode1, TARGET_VAL(Mips::SUBu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30653*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30656*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30665*/ /*SwitchOpcode*/ 32, TARGET_VAL(ISD::MUL),// ->30700
+/* 30668*/ OPC_RecordChild0, // #0 = $src
+/* 30669*/ OPC_RecordChild1, // #1 = $src2
+/* 30670*/ OPC_MoveParent,
+/* 30671*/ OPC_CheckType, MVT::i64,
+/* 30673*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30679*/ OPC_EmitNode2, TARGET_VAL(Mips::MUL), 0,
+ MVT::i32, MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3 #4
+/* 30688*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30691*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 5,
+ // Src: (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30700*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::MFHI),// ->30732
+/* 30703*/ OPC_RecordChild0, // #0 = $src
+/* 30704*/ OPC_MoveParent,
+/* 30705*/ OPC_CheckType, MVT::i64,
+/* 30707*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #1
+/* 30713*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoMFHI), 0,
+ MVT::i32, 1/*#Ops*/, 0, // Results = #2
+/* 30720*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30723*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (sext:{ *:[i64] } (MipsMFHI:{ *:[i32] } ACC64:{ *:[Untyped] }:$src)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (PseudoMFHI:{ *:[i32] } ACC64:{ *:[Untyped] }:$src), sub_32:{ *:[i32] })
+/* 30732*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::MFLO),// ->30764
+/* 30735*/ OPC_RecordChild0, // #0 = $src
+/* 30736*/ OPC_MoveParent,
+/* 30737*/ OPC_CheckType, MVT::i64,
+/* 30739*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #1
+/* 30745*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoMFLO), 0,
+ MVT::i32, 1/*#Ops*/, 0, // Results = #2
+/* 30752*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30755*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (sext:{ *:[i64] } (MipsMFLO:{ *:[i32] } ACC64:{ *:[Untyped] }:$src)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (PseudoMFLO:{ *:[i32] } ACC64:{ *:[Untyped] }:$src), sub_32:{ *:[i32] })
+/* 30764*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SDIV),// ->30800
+/* 30767*/ OPC_RecordChild0, // #0 = $src
+/* 30768*/ OPC_RecordChild1, // #1 = $src2
+/* 30769*/ OPC_MoveParent,
+/* 30770*/ OPC_CheckType, MVT::i64,
+/* 30772*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 30774*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30780*/ OPC_EmitNode1, TARGET_VAL(Mips::DIV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30788*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30791*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30800*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::UDIV),// ->30836
+/* 30803*/ OPC_RecordChild0, // #0 = $src
+/* 30804*/ OPC_RecordChild1, // #1 = $src2
+/* 30805*/ OPC_MoveParent,
+/* 30806*/ OPC_CheckType, MVT::i64,
+/* 30808*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 30810*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30816*/ OPC_EmitNode1, TARGET_VAL(Mips::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30824*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30827*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30836*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SREM),// ->30872
+/* 30839*/ OPC_RecordChild0, // #0 = $src
+/* 30840*/ OPC_RecordChild1, // #1 = $src2
+/* 30841*/ OPC_MoveParent,
+/* 30842*/ OPC_CheckType, MVT::i64,
+/* 30844*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 30846*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30852*/ OPC_EmitNode1, TARGET_VAL(Mips::MOD), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30860*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30863*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30872*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::UREM),// ->30908
+/* 30875*/ OPC_RecordChild0, // #0 = $src
+/* 30876*/ OPC_RecordChild1, // #1 = $src2
+/* 30877*/ OPC_MoveParent,
+/* 30878*/ OPC_CheckType, MVT::i64,
+/* 30880*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding())
+/* 30882*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #2
+/* 30888*/ OPC_EmitNode1, TARGET_VAL(Mips::MODU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 30896*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 30899*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 2, 3, 4,
+ // Src: (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2)) - Complexity = 6
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
+/* 30908*/ 0, // EndSwitchOpcode
+/* 30909*/ /*Scope*/ 12, /*->30922*/
+/* 30910*/ OPC_RecordChild0, // #0 = $src
+/* 30911*/ OPC_CheckType, MVT::i64,
+/* 30913*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 30915*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL64_32), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
+/* 30922*/ 0, /*End of Scope*/
+/* 30923*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::CALLSEQ_START),// ->30947
+/* 30926*/ OPC_RecordNode, // #0 = 'callseq_start' chained node
+/* 30927*/ OPC_RecordChild1, // #1 = $amt1
+/* 30928*/ OPC_MoveChild1,
+/* 30929*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 30932*/ OPC_MoveParent,
+/* 30933*/ OPC_RecordChild2, // #2 = $amt2
+/* 30934*/ OPC_MoveChild2,
+/* 30935*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 30938*/ OPC_MoveParent,
+/* 30939*/ OPC_EmitMergeInputChains1_0,
+/* 30940*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ADJCALLSTACKDOWN), 0|OPFL_Chain|OPFL_GlueOutput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (callseq_start (timm:{ *:[i32] }):$amt1, (timm:{ *:[i32] }):$amt2) - Complexity = 9
+ // Dst: (ADJCALLSTACKDOWN (timm:{ *:[i32] }):$amt1, (timm:{ *:[i32] }):$amt2)
+/* 30947*/ /*SwitchOpcode*/ 22, TARGET_VAL(ISD::CALLSEQ_END),// ->30972
+/* 30950*/ OPC_RecordNode, // #0 = 'callseq_end' chained node
+/* 30951*/ OPC_CaptureGlueInput,
+/* 30952*/ OPC_RecordChild1, // #1 = $amt1
+/* 30953*/ OPC_MoveChild1,
+/* 30954*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 30957*/ OPC_MoveParent,
+/* 30958*/ OPC_RecordChild2, // #2 = $amt2
+/* 30959*/ OPC_MoveChild2,
+/* 30960*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 30963*/ OPC_MoveParent,
+/* 30964*/ OPC_EmitMergeInputChains1_0,
+/* 30965*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ADJCALLSTACKUP), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (callseq_end (timm:{ *:[i32] }):$amt1, (timm:{ *:[i32] }):$amt2) - Complexity = 9
+ // Dst: (ADJCALLSTACKUP (timm:{ *:[i32] }):$amt1, (timm:{ *:[i32] }):$amt2)
+/* 30972*/ /*SwitchOpcode*/ 64, TARGET_VAL(ISD::FrameIndex),// ->31039
+/* 30975*/ OPC_RecordNode, // #0 = $addr
+/* 30976*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->31023
+/* 30979*/ OPC_Scope, 13, /*->30994*/ // 3 children in Scope
+/* 30981*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 30983*/ OPC_CheckComplexPat, /*CP*/1, /*#*/0, // selectIntAddr:$addr #1 #2
+/* 30986*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LEA_ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: addr:{ *:[i32] }:$addr - Complexity = 9
+ // Dst: (LEA_ADDiu:{ *:[i32] } addr:{ *:[i32] }:$addr)
+/* 30994*/ /*Scope*/ 13, /*->31008*/
+/* 30995*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 30997*/ OPC_CheckComplexPat, /*CP*/4, /*#*/0, // selectAddr16SP:$addr #1 #2
+/* 31000*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AddiuRxRyOffMemX16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: addr16sp:{ *:[i32] }:$addr - Complexity = 9
+ // Dst: (AddiuRxRyOffMemX16:{ *:[i32] } addr16sp:{ *:[i32] }:$addr)
+/* 31008*/ /*Scope*/ 13, /*->31022*/
+/* 31009*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31011*/ OPC_CheckComplexPat, /*CP*/1, /*#*/0, // selectIntAddr:$addr #1 #2
+/* 31014*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LEA_ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: addr:{ *:[i32] }:$addr - Complexity = 9
+ // Dst: (LEA_ADDiu_MM:{ *:[i32] } addr:{ *:[i32] }:$addr)
+/* 31022*/ 0, /*End of Scope*/
+/* 31023*/ /*SwitchType*/ 13, MVT::i64,// ->31038
+/* 31025*/ OPC_CheckPatternPredicate, 61, // (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())
+/* 31027*/ OPC_CheckComplexPat, /*CP*/1, /*#*/0, // selectIntAddr:$addr #1 #2
+/* 31030*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LEA_ADDiu64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: addr:{ *:[i64] }:$addr - Complexity = 9
+ // Dst: (LEA_ADDiu64:{ *:[i64] } addr:{ *:[i64] }:$addr)
+/* 31038*/ 0, // EndSwitchType
+/* 31039*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::Ins),// ->31074
+/* 31042*/ OPC_RecordChild0, // #0 = $rs
+/* 31043*/ OPC_RecordChild1, // #1 = $pos
+/* 31044*/ OPC_MoveChild1,
+/* 31045*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 31048*/ OPC_MoveParent,
+/* 31049*/ OPC_RecordChild2, // #2 = $size
+/* 31050*/ OPC_MoveChild2,
+/* 31051*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 31054*/ OPC_MoveParent,
+/* 31055*/ OPC_RecordChild3, // #3 = $src
+/* 31056*/ OPC_CheckType, MVT::i32,
+/* 31058*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 31060*/ OPC_EmitConvertToTarget, 1,
+/* 31062*/ OPC_EmitConvertToTarget, 2,
+/* 31064*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INS_MMR6), 0,
+ MVT::i32, 4/*#Ops*/, 0, 4, 5, 3,
+ // Src: (MipsIns:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size, GPR32Opnd:{ *:[i32] }:$src) - Complexity = 9
+ // Dst: (INS_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$size, GPR32Opnd:{ *:[i32] }:$src)
+/* 31074*/ /*SwitchOpcode*/ 92|128,29/*3804*/, TARGET_VAL(ISD::SETCC),// ->34882
+/* 31078*/ OPC_RecordChild0, // #0 = $lhs
+/* 31079*/ OPC_Scope, 98|128,8/*1122*/, /*->32204*/ // 10 children in Scope
+/* 31082*/ OPC_CheckChild0Type, MVT::i32,
+/* 31084*/ OPC_Scope, 100, /*->31186*/ // 3 children in Scope
+/* 31086*/ OPC_CheckChild1Integer, 0,
+/* 31088*/ OPC_MoveChild2,
+/* 31089*/ OPC_Scope, 18, /*->31109*/ // 5 children in Scope
+/* 31091*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 31093*/ OPC_MoveParent,
+/* 31094*/ OPC_CheckType, MVT::i32,
+/* 31096*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31098*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31101*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
+/* 31109*/ /*Scope*/ 18, /*->31128*/
+/* 31110*/ OPC_CheckCondCode, ISD::SETNE,
+/* 31112*/ OPC_MoveParent,
+/* 31113*/ OPC_CheckType, MVT::i32,
+/* 31115*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31117*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 31120*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
+/* 31128*/ /*Scope*/ 18, /*->31147*/
+/* 31129*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 31131*/ OPC_MoveParent,
+/* 31132*/ OPC_CheckType, MVT::i32,
+/* 31134*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31136*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31139*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
+/* 31147*/ /*Scope*/ 18, /*->31166*/
+/* 31148*/ OPC_CheckCondCode, ISD::SETNE,
+/* 31150*/ OPC_MoveParent,
+/* 31151*/ OPC_CheckType, MVT::i32,
+/* 31153*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31155*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 31158*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
+/* 31166*/ /*Scope*/ 18, /*->31185*/
+/* 31167*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 31169*/ OPC_MoveParent,
+/* 31170*/ OPC_CheckType, MVT::i32,
+/* 31172*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 31174*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31177*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltiuCCRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) - Complexity = 8
+ // Dst: (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
+/* 31185*/ 0, /*End of Scope*/
+/* 31186*/ /*Scope*/ 57, /*->31244*/
+/* 31187*/ OPC_CheckChild1Integer, 127|128,127|128,125|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709518847*/,
+/* 31198*/ OPC_MoveChild2,
+/* 31199*/ OPC_CheckCondCode, ISD::SETGT,
+/* 31201*/ OPC_MoveParent,
+/* 31202*/ OPC_CheckType, MVT::i32,
+/* 31204*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 31206*/ OPC_EmitInteger, MVT::i32, 0|128,0|128,126|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709518848*/,
+/* 31218*/ OPC_EmitNode1, TARGET_VAL(Mips::SltiCCRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 31226*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31229*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 3, // Results = #4
+/* 31236*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XorRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 2, 4,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] }) - Complexity = 8
+ // Dst: (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
+/* 31244*/ /*Scope*/ 61|128,7/*957*/, /*->32203*/
+/* 31246*/ OPC_RecordChild1, // #1 = $imm16
+/* 31247*/ OPC_Scope, 106|128,1/*234*/, /*->31484*/ // 2 children in Scope
+/* 31250*/ OPC_MoveChild1,
+/* 31251*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 31254*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 31256*/ OPC_MoveParent,
+/* 31257*/ OPC_MoveChild2,
+/* 31258*/ OPC_Scope, 17, /*->31277*/ // 10 children in Scope
+/* 31260*/ OPC_CheckCondCode, ISD::SETLT,
+/* 31262*/ OPC_MoveParent,
+/* 31263*/ OPC_CheckType, MVT::i32,
+/* 31265*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31267*/ OPC_EmitConvertToTarget, 1,
+/* 31269*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETLT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
+/* 31277*/ /*Scope*/ 17, /*->31295*/
+/* 31278*/ OPC_CheckCondCode, ISD::SETULT,
+/* 31280*/ OPC_MoveParent,
+/* 31281*/ OPC_CheckType, MVT::i32,
+/* 31283*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31285*/ OPC_EmitConvertToTarget, 1,
+/* 31287*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETULT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
+/* 31295*/ /*Scope*/ 17, /*->31313*/
+/* 31296*/ OPC_CheckCondCode, ISD::SETLT,
+/* 31298*/ OPC_MoveParent,
+/* 31299*/ OPC_CheckType, MVT::i32,
+/* 31301*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31303*/ OPC_EmitConvertToTarget, 1,
+/* 31305*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETLT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTi_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
+/* 31313*/ /*Scope*/ 17, /*->31331*/
+/* 31314*/ OPC_CheckCondCode, ISD::SETULT,
+/* 31316*/ OPC_MoveParent,
+/* 31317*/ OPC_CheckType, MVT::i32,
+/* 31319*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31321*/ OPC_EmitConvertToTarget, 1,
+/* 31323*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETULT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTiu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
+/* 31331*/ /*Scope*/ 28, /*->31360*/
+/* 31332*/ OPC_CheckCondCode, ISD::SETGE,
+/* 31334*/ OPC_MoveParent,
+/* 31335*/ OPC_CheckType, MVT::i32,
+/* 31337*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31339*/ OPC_EmitConvertToTarget, 1,
+/* 31341*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
+/* 31349*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31352*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }) - Complexity = 7
+ // Dst: (XORi:{ *:[i32] } (SLTi:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), 1:{ *:[i32] })
+/* 31360*/ /*Scope*/ 28, /*->31389*/
+/* 31361*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 31363*/ OPC_MoveParent,
+/* 31364*/ OPC_CheckType, MVT::i32,
+/* 31366*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31368*/ OPC_EmitConvertToTarget, 1,
+/* 31370*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
+/* 31378*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31381*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }) - Complexity = 7
+ // Dst: (XORi:{ *:[i32] } (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), 1:{ *:[i32] })
+/* 31389*/ /*Scope*/ 28, /*->31418*/
+/* 31390*/ OPC_CheckCondCode, ISD::SETGE,
+/* 31392*/ OPC_MoveParent,
+/* 31393*/ OPC_CheckType, MVT::i32,
+/* 31395*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31397*/ OPC_EmitConvertToTarget, 1,
+/* 31399*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
+/* 31407*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31410*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }) - Complexity = 7
+ // Dst: (XORi_MM:{ *:[i32] } (SLTi_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), 1:{ *:[i32] })
+/* 31418*/ /*Scope*/ 28, /*->31447*/
+/* 31419*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 31421*/ OPC_MoveParent,
+/* 31422*/ OPC_CheckType, MVT::i32,
+/* 31424*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31426*/ OPC_EmitConvertToTarget, 1,
+/* 31428*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
+/* 31436*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31439*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }) - Complexity = 7
+ // Dst: (XORi_MM:{ *:[i32] } (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$rhs), 1:{ *:[i32] })
+/* 31447*/ /*Scope*/ 17, /*->31465*/
+/* 31448*/ OPC_CheckCondCode, ISD::SETLT,
+/* 31450*/ OPC_MoveParent,
+/* 31451*/ OPC_CheckType, MVT::i32,
+/* 31453*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 31455*/ OPC_EmitConvertToTarget, 1,
+/* 31457*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltiCCRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETLT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16)
+/* 31465*/ /*Scope*/ 17, /*->31483*/
+/* 31466*/ OPC_CheckCondCode, ISD::SETULT,
+/* 31468*/ OPC_MoveParent,
+/* 31469*/ OPC_CheckType, MVT::i32,
+/* 31471*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 31473*/ OPC_EmitConvertToTarget, 1,
+/* 31475*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltiuCCRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16, SETULT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm16)
+/* 31483*/ 0, /*End of Scope*/
+/* 31484*/ /*Scope*/ 76|128,5/*716*/, /*->32202*/
+/* 31486*/ OPC_MoveChild2,
+/* 31487*/ OPC_Scope, 15, /*->31504*/ // 30 children in Scope
+/* 31489*/ OPC_CheckCondCode, ISD::SETLT,
+/* 31491*/ OPC_MoveParent,
+/* 31492*/ OPC_CheckType, MVT::i32,
+/* 31494*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31496*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 31504*/ /*Scope*/ 15, /*->31520*/
+/* 31505*/ OPC_CheckCondCode, ISD::SETULT,
+/* 31507*/ OPC_MoveParent,
+/* 31508*/ OPC_CheckType, MVT::i32,
+/* 31510*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31512*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 31520*/ /*Scope*/ 15, /*->31536*/
+/* 31521*/ OPC_CheckCondCode, ISD::SETGT,
+/* 31523*/ OPC_MoveParent,
+/* 31524*/ OPC_CheckType, MVT::i32,
+/* 31526*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31528*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
+/* 31536*/ /*Scope*/ 15, /*->31552*/
+/* 31537*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 31539*/ OPC_MoveParent,
+/* 31540*/ OPC_CheckType, MVT::i32,
+/* 31542*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31544*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
+/* 31552*/ /*Scope*/ 15, /*->31568*/
+/* 31553*/ OPC_CheckCondCode, ISD::SETLT,
+/* 31555*/ OPC_MoveParent,
+/* 31556*/ OPC_CheckType, MVT::i32,
+/* 31558*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31560*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 31568*/ /*Scope*/ 15, /*->31584*/
+/* 31569*/ OPC_CheckCondCode, ISD::SETULT,
+/* 31571*/ OPC_MoveParent,
+/* 31572*/ OPC_CheckType, MVT::i32,
+/* 31574*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31576*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 31584*/ /*Scope*/ 15, /*->31600*/
+/* 31585*/ OPC_CheckCondCode, ISD::SETGT,
+/* 31587*/ OPC_MoveParent,
+/* 31588*/ OPC_CheckType, MVT::i32,
+/* 31590*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31592*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
+/* 31600*/ /*Scope*/ 15, /*->31616*/
+/* 31601*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 31603*/ OPC_MoveParent,
+/* 31604*/ OPC_CheckType, MVT::i32,
+/* 31606*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31608*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
+/* 31616*/ /*Scope*/ 26, /*->31643*/
+/* 31617*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 31619*/ OPC_MoveParent,
+/* 31620*/ OPC_CheckType, MVT::i32,
+/* 31622*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31624*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 31632*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31635*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
+/* 31643*/ /*Scope*/ 26, /*->31670*/
+/* 31644*/ OPC_CheckCondCode, ISD::SETNE,
+/* 31646*/ OPC_MoveParent,
+/* 31647*/ OPC_CheckType, MVT::i32,
+/* 31649*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31651*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 31654*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 31662*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
+/* 31670*/ /*Scope*/ 26, /*->31697*/
+/* 31671*/ OPC_CheckCondCode, ISD::SETLE,
+/* 31673*/ OPC_MoveParent,
+/* 31674*/ OPC_CheckType, MVT::i32,
+/* 31676*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31678*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 31686*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31689*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
+/* 31697*/ /*Scope*/ 26, /*->31724*/
+/* 31698*/ OPC_CheckCondCode, ISD::SETULE,
+/* 31700*/ OPC_MoveParent,
+/* 31701*/ OPC_CheckType, MVT::i32,
+/* 31703*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31705*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 31713*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31716*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
+/* 31724*/ /*Scope*/ 26, /*->31751*/
+/* 31725*/ OPC_CheckCondCode, ISD::SETGE,
+/* 31727*/ OPC_MoveParent,
+/* 31728*/ OPC_CheckType, MVT::i32,
+/* 31730*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31732*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 31740*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31743*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
+/* 31751*/ /*Scope*/ 26, /*->31778*/
+/* 31752*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 31754*/ OPC_MoveParent,
+/* 31755*/ OPC_CheckType, MVT::i32,
+/* 31757*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 31759*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 31767*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31770*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
+/* 31778*/ /*Scope*/ 26, /*->31805*/
+/* 31779*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 31781*/ OPC_MoveParent,
+/* 31782*/ OPC_CheckType, MVT::i32,
+/* 31784*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31786*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 31794*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31797*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
+/* 31805*/ /*Scope*/ 26, /*->31832*/
+/* 31806*/ OPC_CheckCondCode, ISD::SETNE,
+/* 31808*/ OPC_MoveParent,
+/* 31809*/ OPC_CheckType, MVT::i32,
+/* 31811*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31813*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 31816*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 31824*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
+/* 31832*/ /*Scope*/ 26, /*->31859*/
+/* 31833*/ OPC_CheckCondCode, ISD::SETLE,
+/* 31835*/ OPC_MoveParent,
+/* 31836*/ OPC_CheckType, MVT::i32,
+/* 31838*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31840*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 31848*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31851*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
+/* 31859*/ /*Scope*/ 26, /*->31886*/
+/* 31860*/ OPC_CheckCondCode, ISD::SETULE,
+/* 31862*/ OPC_MoveParent,
+/* 31863*/ OPC_CheckType, MVT::i32,
+/* 31865*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31867*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 31875*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31878*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
+/* 31886*/ /*Scope*/ 26, /*->31913*/
+/* 31887*/ OPC_CheckCondCode, ISD::SETGE,
+/* 31889*/ OPC_MoveParent,
+/* 31890*/ OPC_CheckType, MVT::i32,
+/* 31892*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31894*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 31902*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31905*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
+/* 31913*/ /*Scope*/ 26, /*->31940*/
+/* 31914*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 31916*/ OPC_MoveParent,
+/* 31917*/ OPC_CheckType, MVT::i32,
+/* 31919*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 31921*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 31929*/ OPC_EmitInteger, MVT::i32, 1,
+/* 31932*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
+/* 31940*/ /*Scope*/ 15, /*->31956*/
+/* 31941*/ OPC_CheckCondCode, ISD::SETGT,
+/* 31943*/ OPC_MoveParent,
+/* 31944*/ OPC_CheckType, MVT::i32,
+/* 31946*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 31948*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
+/* 31956*/ /*Scope*/ 15, /*->31972*/
+/* 31957*/ OPC_CheckCondCode, ISD::SETLT,
+/* 31959*/ OPC_MoveParent,
+/* 31960*/ OPC_CheckType, MVT::i32,
+/* 31962*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 31964*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
+/* 31972*/ /*Scope*/ 15, /*->31988*/
+/* 31973*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 31975*/ OPC_MoveParent,
+/* 31976*/ OPC_CheckType, MVT::i32,
+/* 31978*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 31980*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltuCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
+/* 31988*/ /*Scope*/ 15, /*->32004*/
+/* 31989*/ OPC_CheckCondCode, ISD::SETULT,
+/* 31991*/ OPC_MoveParent,
+/* 31992*/ OPC_CheckType, MVT::i32,
+/* 31994*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 31996*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltuCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
+/* 32004*/ /*Scope*/ 26, /*->32031*/
+/* 32005*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 32007*/ OPC_MoveParent,
+/* 32008*/ OPC_CheckType, MVT::i32,
+/* 32010*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 32012*/ OPC_EmitNode1, TARGET_VAL(Mips::XorRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 32020*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32023*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltiuCCRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
+/* 32031*/ /*Scope*/ 33, /*->32065*/
+/* 32032*/ OPC_CheckCondCode, ISD::SETGE,
+/* 32034*/ OPC_MoveParent,
+/* 32035*/ OPC_CheckType, MVT::i32,
+/* 32037*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 32039*/ OPC_EmitNode1, TARGET_VAL(Mips::SltCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 32047*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32050*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 3, // Results = #4
+/* 32057*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XorRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 2, 4,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
+/* 32065*/ /*Scope*/ 33, /*->32099*/
+/* 32066*/ OPC_CheckCondCode, ISD::SETLE,
+/* 32068*/ OPC_MoveParent,
+/* 32069*/ OPC_CheckType, MVT::i32,
+/* 32071*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 32073*/ OPC_EmitNode1, TARGET_VAL(Mips::SltCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 32081*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32084*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImm16), 0,
+ MVT::i32, 1/*#Ops*/, 3, // Results = #4
+/* 32091*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XorRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 2, 4,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
+/* 32099*/ /*Scope*/ 33, /*->32133*/
+/* 32100*/ OPC_CheckCondCode, ISD::SETNE,
+/* 32102*/ OPC_MoveParent,
+/* 32103*/ OPC_CheckType, MVT::i32,
+/* 32105*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 32107*/ OPC_EmitInteger, MVT::i32, 0,
+/* 32110*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 2, // Results = #3
+/* 32117*/ OPC_EmitNode1, TARGET_VAL(Mips::XorRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #4
+/* 32125*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SltuCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
+/* 32133*/ /*Scope*/ 33, /*->32167*/
+/* 32134*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 32136*/ OPC_MoveParent,
+/* 32137*/ OPC_CheckType, MVT::i32,
+/* 32139*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 32141*/ OPC_EmitNode1, TARGET_VAL(Mips::SltuCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 32149*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32152*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 3, // Results = #4
+/* 32159*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XorRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 2, 4,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
+/* 32167*/ /*Scope*/ 33, /*->32201*/
+/* 32168*/ OPC_CheckCondCode, ISD::SETULE,
+/* 32170*/ OPC_MoveParent,
+/* 32171*/ OPC_CheckType, MVT::i32,
+/* 32173*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 32175*/ OPC_EmitNode1, TARGET_VAL(Mips::SltuCCRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 32183*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32186*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 3, // Results = #4
+/* 32193*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XorRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 2, 4,
+ // Src: (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
+/* 32201*/ 0, /*End of Scope*/
+/* 32202*/ 0, /*End of Scope*/
+/* 32203*/ 0, /*End of Scope*/
+/* 32204*/ /*Scope*/ 7|128,3/*391*/, /*->32597*/
+/* 32206*/ OPC_CheckChild0Type, MVT::i64,
+/* 32208*/ OPC_Scope, 44, /*->32254*/ // 2 children in Scope
+/* 32210*/ OPC_CheckChild1Integer, 0,
+/* 32212*/ OPC_MoveChild2,
+/* 32213*/ OPC_Scope, 18, /*->32233*/ // 2 children in Scope
+/* 32215*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 32217*/ OPC_MoveParent,
+/* 32218*/ OPC_CheckType, MVT::i32,
+/* 32220*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32222*/ OPC_EmitInteger, MVT::i64, 1,
+/* 32225*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
+/* 32233*/ /*Scope*/ 19, /*->32253*/
+/* 32234*/ OPC_CheckCondCode, ISD::SETNE,
+/* 32236*/ OPC_MoveParent,
+/* 32237*/ OPC_CheckType, MVT::i32,
+/* 32239*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32241*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 32245*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
+/* 32253*/ 0, /*End of Scope*/
+/* 32254*/ /*Scope*/ 84|128,2/*340*/, /*->32596*/
+/* 32256*/ OPC_RecordChild1, // #1 = $imm16
+/* 32257*/ OPC_Scope, 104, /*->32363*/ // 2 children in Scope
+/* 32259*/ OPC_MoveChild1,
+/* 32260*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 32263*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 32265*/ OPC_MoveParent,
+/* 32266*/ OPC_MoveChild2,
+/* 32267*/ OPC_Scope, 17, /*->32286*/ // 4 children in Scope
+/* 32269*/ OPC_CheckCondCode, ISD::SETLT,
+/* 32271*/ OPC_MoveParent,
+/* 32272*/ OPC_CheckType, MVT::i32,
+/* 32274*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 32276*/ OPC_EmitConvertToTarget, 1,
+/* 32278*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$imm16, SETLT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTi64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm16)
+/* 32286*/ /*Scope*/ 17, /*->32304*/
+/* 32287*/ OPC_CheckCondCode, ISD::SETULT,
+/* 32289*/ OPC_MoveParent,
+/* 32290*/ OPC_CheckType, MVT::i32,
+/* 32292*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 32294*/ OPC_EmitConvertToTarget, 1,
+/* 32296*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$imm16, SETULT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTiu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$imm16)
+/* 32304*/ /*Scope*/ 28, /*->32333*/
+/* 32305*/ OPC_CheckCondCode, ISD::SETGE,
+/* 32307*/ OPC_MoveParent,
+/* 32308*/ OPC_CheckType, MVT::i32,
+/* 32310*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32312*/ OPC_EmitConvertToTarget, 1,
+/* 32314*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTi64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
+/* 32322*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32325*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs, SETGE:{ *:[Other] }) - Complexity = 7
+ // Dst: (XORi:{ *:[i32] } (SLTi64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs), 1:{ *:[i32] })
+/* 32333*/ /*Scope*/ 28, /*->32362*/
+/* 32334*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 32336*/ OPC_MoveParent,
+/* 32337*/ OPC_CheckType, MVT::i32,
+/* 32339*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32341*/ OPC_EmitConvertToTarget, 1,
+/* 32343*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
+/* 32351*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32354*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs, SETUGE:{ *:[Other] }) - Complexity = 7
+ // Dst: (XORi:{ *:[i32] } (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$rhs), 1:{ *:[i32] })
+/* 32362*/ 0, /*End of Scope*/
+/* 32363*/ /*Scope*/ 102|128,1/*230*/, /*->32595*/
+/* 32365*/ OPC_MoveChild2,
+/* 32366*/ OPC_Scope, 15, /*->32383*/ // 10 children in Scope
+/* 32368*/ OPC_CheckCondCode, ISD::SETLT,
+/* 32370*/ OPC_MoveParent,
+/* 32371*/ OPC_CheckType, MVT::i32,
+/* 32373*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 32375*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 32383*/ /*Scope*/ 15, /*->32399*/
+/* 32384*/ OPC_CheckCondCode, ISD::SETULT,
+/* 32386*/ OPC_MoveParent,
+/* 32387*/ OPC_CheckType, MVT::i32,
+/* 32389*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 32391*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 32399*/ /*Scope*/ 15, /*->32415*/
+/* 32400*/ OPC_CheckCondCode, ISD::SETGT,
+/* 32402*/ OPC_MoveParent,
+/* 32403*/ OPC_CheckType, MVT::i32,
+/* 32405*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32407*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
+/* 32415*/ /*Scope*/ 15, /*->32431*/
+/* 32416*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 32418*/ OPC_MoveParent,
+/* 32419*/ OPC_CheckType, MVT::i32,
+/* 32421*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32423*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
+/* 32431*/ /*Scope*/ 26, /*->32458*/
+/* 32432*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 32434*/ OPC_MoveParent,
+/* 32435*/ OPC_CheckType, MVT::i32,
+/* 32437*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32439*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #2
+/* 32447*/ OPC_EmitInteger, MVT::i64, 1,
+/* 32450*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTiu64), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
+/* 32458*/ /*Scope*/ 27, /*->32486*/
+/* 32459*/ OPC_CheckCondCode, ISD::SETNE,
+/* 32461*/ OPC_MoveParent,
+/* 32462*/ OPC_CheckType, MVT::i32,
+/* 32464*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32466*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 32470*/ OPC_EmitNode1, TARGET_VAL(Mips::XOR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #3
+/* 32478*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
+/* 32486*/ /*Scope*/ 26, /*->32513*/
+/* 32487*/ OPC_CheckCondCode, ISD::SETLE,
+/* 32489*/ OPC_MoveParent,
+/* 32490*/ OPC_CheckType, MVT::i32,
+/* 32492*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32494*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 32502*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32505*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
+/* 32513*/ /*Scope*/ 26, /*->32540*/
+/* 32514*/ OPC_CheckCondCode, ISD::SETULE,
+/* 32516*/ OPC_MoveParent,
+/* 32517*/ OPC_CheckType, MVT::i32,
+/* 32519*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32521*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 32529*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32532*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
+/* 32540*/ /*Scope*/ 26, /*->32567*/
+/* 32541*/ OPC_CheckCondCode, ISD::SETGE,
+/* 32543*/ OPC_MoveParent,
+/* 32544*/ OPC_CheckType, MVT::i32,
+/* 32546*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32548*/ OPC_EmitNode1, TARGET_VAL(Mips::SLT64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 32556*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32559*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
+/* 32567*/ /*Scope*/ 26, /*->32594*/
+/* 32568*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 32570*/ OPC_MoveParent,
+/* 32571*/ OPC_CheckType, MVT::i32,
+/* 32573*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 32575*/ OPC_EmitNode1, TARGET_VAL(Mips::SLTu64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 32583*/ OPC_EmitInteger, MVT::i32, 1,
+/* 32586*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORi), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
+/* 32594*/ 0, /*End of Scope*/
+/* 32595*/ 0, /*End of Scope*/
+/* 32596*/ 0, /*End of Scope*/
+/* 32597*/ /*Scope*/ 94|128,4/*606*/, /*->33205*/
+/* 32599*/ OPC_CheckChild0Type, MVT::f32,
+/* 32601*/ OPC_RecordChild1, // #1 = $ft
+/* 32602*/ OPC_MoveChild2,
+/* 32603*/ OPC_Scope, 15, /*->32620*/ // 32 children in Scope
+/* 32605*/ OPC_CheckCondCode, ISD::SETUO,
+/* 32607*/ OPC_MoveParent,
+/* 32608*/ OPC_CheckType, MVT::i32,
+/* 32610*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 32612*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_UN_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32620*/ /*Scope*/ 15, /*->32636*/
+/* 32621*/ OPC_CheckCondCode, ISD::SETOEQ,
+/* 32623*/ OPC_MoveParent,
+/* 32624*/ OPC_CheckType, MVT::i32,
+/* 32626*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 32628*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_EQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32636*/ /*Scope*/ 15, /*->32652*/
+/* 32637*/ OPC_CheckCondCode, ISD::SETUEQ,
+/* 32639*/ OPC_MoveParent,
+/* 32640*/ OPC_CheckType, MVT::i32,
+/* 32642*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 32644*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_UEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32652*/ /*Scope*/ 15, /*->32668*/
+/* 32653*/ OPC_CheckCondCode, ISD::SETOLT,
+/* 32655*/ OPC_MoveParent,
+/* 32656*/ OPC_CheckType, MVT::i32,
+/* 32658*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 32660*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32668*/ /*Scope*/ 15, /*->32684*/
+/* 32669*/ OPC_CheckCondCode, ISD::SETULT,
+/* 32671*/ OPC_MoveParent,
+/* 32672*/ OPC_CheckType, MVT::i32,
+/* 32674*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 32676*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_ULT_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32684*/ /*Scope*/ 15, /*->32700*/
+/* 32685*/ OPC_CheckCondCode, ISD::SETOLE,
+/* 32687*/ OPC_MoveParent,
+/* 32688*/ OPC_CheckType, MVT::i32,
+/* 32690*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 32692*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32700*/ /*Scope*/ 15, /*->32716*/
+/* 32701*/ OPC_CheckCondCode, ISD::SETULE,
+/* 32703*/ OPC_MoveParent,
+/* 32704*/ OPC_CheckType, MVT::i32,
+/* 32706*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 32708*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_ULE_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32716*/ /*Scope*/ 15, /*->32732*/
+/* 32717*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 32719*/ OPC_MoveParent,
+/* 32720*/ OPC_CheckType, MVT::i32,
+/* 32722*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 32724*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_EQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
+/* 32732*/ /*Scope*/ 15, /*->32748*/
+/* 32733*/ OPC_CheckCondCode, ISD::SETGT,
+/* 32735*/ OPC_MoveParent,
+/* 32736*/ OPC_CheckType, MVT::i32,
+/* 32738*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 32740*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_S), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_S:{ *:[i32] } f32:{ *:[f32] }:$rhs, f32:{ *:[f32] }:$lhs)
+/* 32748*/ /*Scope*/ 15, /*->32764*/
+/* 32749*/ OPC_CheckCondCode, ISD::SETGE,
+/* 32751*/ OPC_MoveParent,
+/* 32752*/ OPC_CheckType, MVT::i32,
+/* 32754*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 32756*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_S), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_S:{ *:[i32] } f32:{ *:[f32] }:$rhs, f32:{ *:[f32] }:$lhs)
+/* 32764*/ /*Scope*/ 15, /*->32780*/
+/* 32765*/ OPC_CheckCondCode, ISD::SETLT,
+/* 32767*/ OPC_MoveParent,
+/* 32768*/ OPC_CheckType, MVT::i32,
+/* 32770*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 32772*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
+/* 32780*/ /*Scope*/ 15, /*->32796*/
+/* 32781*/ OPC_CheckCondCode, ISD::SETLE,
+/* 32783*/ OPC_MoveParent,
+/* 32784*/ OPC_CheckType, MVT::i32,
+/* 32786*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 32788*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
+/* 32796*/ /*Scope*/ 15, /*->32812*/
+/* 32797*/ OPC_CheckCondCode, ISD::SETUO,
+/* 32799*/ OPC_MoveParent,
+/* 32800*/ OPC_CheckType, MVT::i32,
+/* 32802*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 32804*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_UN_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32812*/ /*Scope*/ 15, /*->32828*/
+/* 32813*/ OPC_CheckCondCode, ISD::SETOEQ,
+/* 32815*/ OPC_MoveParent,
+/* 32816*/ OPC_CheckType, MVT::i32,
+/* 32818*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 32820*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_EQ_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32828*/ /*Scope*/ 15, /*->32844*/
+/* 32829*/ OPC_CheckCondCode, ISD::SETUEQ,
+/* 32831*/ OPC_MoveParent,
+/* 32832*/ OPC_CheckType, MVT::i32,
+/* 32834*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 32836*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_UEQ_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32844*/ /*Scope*/ 15, /*->32860*/
+/* 32845*/ OPC_CheckCondCode, ISD::SETOLT,
+/* 32847*/ OPC_MoveParent,
+/* 32848*/ OPC_CheckType, MVT::i32,
+/* 32850*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 32852*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32860*/ /*Scope*/ 15, /*->32876*/
+/* 32861*/ OPC_CheckCondCode, ISD::SETULT,
+/* 32863*/ OPC_MoveParent,
+/* 32864*/ OPC_CheckType, MVT::i32,
+/* 32866*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 32868*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_ULT_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32876*/ /*Scope*/ 15, /*->32892*/
+/* 32877*/ OPC_CheckCondCode, ISD::SETOLE,
+/* 32879*/ OPC_MoveParent,
+/* 32880*/ OPC_CheckType, MVT::i32,
+/* 32882*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 32884*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32892*/ /*Scope*/ 15, /*->32908*/
+/* 32893*/ OPC_CheckCondCode, ISD::SETULE,
+/* 32895*/ OPC_MoveParent,
+/* 32896*/ OPC_CheckType, MVT::i32,
+/* 32898*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 32900*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_ULE_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 32908*/ /*Scope*/ 15, /*->32924*/
+/* 32909*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 32911*/ OPC_MoveParent,
+/* 32912*/ OPC_CheckType, MVT::i32,
+/* 32914*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 32916*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_EQ_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
+/* 32924*/ /*Scope*/ 15, /*->32940*/
+/* 32925*/ OPC_CheckCondCode, ISD::SETGT,
+/* 32927*/ OPC_MoveParent,
+/* 32928*/ OPC_CheckType, MVT::i32,
+/* 32930*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 32932*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$rhs, f32:{ *:[f32] }:$lhs)
+/* 32940*/ /*Scope*/ 15, /*->32956*/
+/* 32941*/ OPC_CheckCondCode, ISD::SETGE,
+/* 32943*/ OPC_MoveParent,
+/* 32944*/ OPC_CheckType, MVT::i32,
+/* 32946*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 32948*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$rhs, f32:{ *:[f32] }:$lhs)
+/* 32956*/ /*Scope*/ 15, /*->32972*/
+/* 32957*/ OPC_CheckCondCode, ISD::SETLT,
+/* 32959*/ OPC_MoveParent,
+/* 32960*/ OPC_CheckType, MVT::i32,
+/* 32962*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 32964*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
+/* 32972*/ /*Scope*/ 15, /*->32988*/
+/* 32973*/ OPC_CheckCondCode, ISD::SETLE,
+/* 32975*/ OPC_MoveParent,
+/* 32976*/ OPC_CheckType, MVT::i32,
+/* 32978*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 32980*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
+/* 32988*/ /*Scope*/ 26, /*->33015*/
+/* 32989*/ OPC_CheckCondCode, ISD::SETONE,
+/* 32991*/ OPC_MoveParent,
+/* 32992*/ OPC_CheckType, MVT::i32,
+/* 32994*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 32996*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_UEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33004*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33007*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR:{ *:[i32] } (CMP_UEQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
+/* 33015*/ /*Scope*/ 26, /*->33042*/
+/* 33016*/ OPC_CheckCondCode, ISD::SETO,
+/* 33018*/ OPC_MoveParent,
+/* 33019*/ OPC_CheckType, MVT::i32,
+/* 33021*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33023*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_UN_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33031*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33034*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR:{ *:[i32] } (CMP_UN_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
+/* 33042*/ /*Scope*/ 26, /*->33069*/
+/* 33043*/ OPC_CheckCondCode, ISD::SETUNE,
+/* 33045*/ OPC_MoveParent,
+/* 33046*/ OPC_CheckType, MVT::i32,
+/* 33048*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33050*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_EQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33058*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33061*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR:{ *:[i32] } (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
+/* 33069*/ /*Scope*/ 26, /*->33096*/
+/* 33070*/ OPC_CheckCondCode, ISD::SETNE,
+/* 33072*/ OPC_MoveParent,
+/* 33073*/ OPC_CheckType, MVT::i32,
+/* 33075*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33077*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_EQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33085*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33088*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR:{ *:[i32] } (CMP_EQ_S:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
+/* 33096*/ /*Scope*/ 26, /*->33123*/
+/* 33097*/ OPC_CheckCondCode, ISD::SETONE,
+/* 33099*/ OPC_MoveParent,
+/* 33100*/ OPC_CheckType, MVT::i32,
+/* 33102*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33104*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_UEQ_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33112*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33115*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETONE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR_MMR6:{ *:[i32] } (CMP_UEQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
+/* 33123*/ /*Scope*/ 26, /*->33150*/
+/* 33124*/ OPC_CheckCondCode, ISD::SETO,
+/* 33126*/ OPC_MoveParent,
+/* 33127*/ OPC_CheckType, MVT::i32,
+/* 33129*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33131*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_UN_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33139*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33142*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR_MMR6:{ *:[i32] } (CMP_UN_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
+/* 33150*/ /*Scope*/ 26, /*->33177*/
+/* 33151*/ OPC_CheckCondCode, ISD::SETUNE,
+/* 33153*/ OPC_MoveParent,
+/* 33154*/ OPC_CheckType, MVT::i32,
+/* 33156*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33158*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_EQ_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33166*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33169*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETUNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR_MMR6:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
+/* 33177*/ /*Scope*/ 26, /*->33204*/
+/* 33178*/ OPC_CheckCondCode, ISD::SETNE,
+/* 33180*/ OPC_MoveParent,
+/* 33181*/ OPC_CheckType, MVT::i32,
+/* 33183*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33185*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_EQ_S_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33193*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33196*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR_MMR6:{ *:[i32] } (CMP_EQ_S_MMR6:{ *:[i32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs), ZERO:{ *:[i32] })
+/* 33204*/ 0, /*End of Scope*/
+/* 33205*/ /*Scope*/ 94|128,4/*606*/, /*->33813*/
+/* 33207*/ OPC_CheckChild0Type, MVT::f64,
+/* 33209*/ OPC_RecordChild1, // #1 = $ft
+/* 33210*/ OPC_MoveChild2,
+/* 33211*/ OPC_Scope, 15, /*->33228*/ // 32 children in Scope
+/* 33213*/ OPC_CheckCondCode, ISD::SETUO,
+/* 33215*/ OPC_MoveParent,
+/* 33216*/ OPC_CheckType, MVT::i32,
+/* 33218*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 33220*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_UN_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33228*/ /*Scope*/ 15, /*->33244*/
+/* 33229*/ OPC_CheckCondCode, ISD::SETOEQ,
+/* 33231*/ OPC_MoveParent,
+/* 33232*/ OPC_CheckType, MVT::i32,
+/* 33234*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 33236*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_EQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33244*/ /*Scope*/ 15, /*->33260*/
+/* 33245*/ OPC_CheckCondCode, ISD::SETUEQ,
+/* 33247*/ OPC_MoveParent,
+/* 33248*/ OPC_CheckType, MVT::i32,
+/* 33250*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 33252*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_UEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33260*/ /*Scope*/ 15, /*->33276*/
+/* 33261*/ OPC_CheckCondCode, ISD::SETOLT,
+/* 33263*/ OPC_MoveParent,
+/* 33264*/ OPC_CheckType, MVT::i32,
+/* 33266*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 33268*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33276*/ /*Scope*/ 15, /*->33292*/
+/* 33277*/ OPC_CheckCondCode, ISD::SETULT,
+/* 33279*/ OPC_MoveParent,
+/* 33280*/ OPC_CheckType, MVT::i32,
+/* 33282*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 33284*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_ULT_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33292*/ /*Scope*/ 15, /*->33308*/
+/* 33293*/ OPC_CheckCondCode, ISD::SETOLE,
+/* 33295*/ OPC_MoveParent,
+/* 33296*/ OPC_CheckType, MVT::i32,
+/* 33298*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 33300*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33308*/ /*Scope*/ 15, /*->33324*/
+/* 33309*/ OPC_CheckCondCode, ISD::SETULE,
+/* 33311*/ OPC_MoveParent,
+/* 33312*/ OPC_CheckType, MVT::i32,
+/* 33314*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 33316*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_ULE_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33324*/ /*Scope*/ 15, /*->33340*/
+/* 33325*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 33327*/ OPC_MoveParent,
+/* 33328*/ OPC_CheckType, MVT::i32,
+/* 33330*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33332*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_EQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
+/* 33340*/ /*Scope*/ 15, /*->33356*/
+/* 33341*/ OPC_CheckCondCode, ISD::SETGT,
+/* 33343*/ OPC_MoveParent,
+/* 33344*/ OPC_CheckType, MVT::i32,
+/* 33346*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33348*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_D), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_D:{ *:[i32] } f64:{ *:[f64] }:$rhs, f64:{ *:[f64] }:$lhs)
+/* 33356*/ /*Scope*/ 15, /*->33372*/
+/* 33357*/ OPC_CheckCondCode, ISD::SETGE,
+/* 33359*/ OPC_MoveParent,
+/* 33360*/ OPC_CheckType, MVT::i32,
+/* 33362*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33364*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_D), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_D:{ *:[i32] } f64:{ *:[f64] }:$rhs, f64:{ *:[f64] }:$lhs)
+/* 33372*/ /*Scope*/ 15, /*->33388*/
+/* 33373*/ OPC_CheckCondCode, ISD::SETLT,
+/* 33375*/ OPC_MoveParent,
+/* 33376*/ OPC_CheckType, MVT::i32,
+/* 33378*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33380*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
+/* 33388*/ /*Scope*/ 15, /*->33404*/
+/* 33389*/ OPC_CheckCondCode, ISD::SETLE,
+/* 33391*/ OPC_MoveParent,
+/* 33392*/ OPC_CheckType, MVT::i32,
+/* 33394*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33396*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
+/* 33404*/ /*Scope*/ 15, /*->33420*/
+/* 33405*/ OPC_CheckCondCode, ISD::SETUO,
+/* 33407*/ OPC_MoveParent,
+/* 33408*/ OPC_CheckType, MVT::i32,
+/* 33410*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 33412*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_UN_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33420*/ /*Scope*/ 15, /*->33436*/
+/* 33421*/ OPC_CheckCondCode, ISD::SETOEQ,
+/* 33423*/ OPC_MoveParent,
+/* 33424*/ OPC_CheckType, MVT::i32,
+/* 33426*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 33428*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_EQ_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33436*/ /*Scope*/ 15, /*->33452*/
+/* 33437*/ OPC_CheckCondCode, ISD::SETUEQ,
+/* 33439*/ OPC_MoveParent,
+/* 33440*/ OPC_CheckType, MVT::i32,
+/* 33442*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 33444*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_UEQ_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33452*/ /*Scope*/ 15, /*->33468*/
+/* 33453*/ OPC_CheckCondCode, ISD::SETOLT,
+/* 33455*/ OPC_MoveParent,
+/* 33456*/ OPC_CheckType, MVT::i32,
+/* 33458*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 33460*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33468*/ /*Scope*/ 15, /*->33484*/
+/* 33469*/ OPC_CheckCondCode, ISD::SETULT,
+/* 33471*/ OPC_MoveParent,
+/* 33472*/ OPC_CheckType, MVT::i32,
+/* 33474*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 33476*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_ULT_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33484*/ /*Scope*/ 15, /*->33500*/
+/* 33485*/ OPC_CheckCondCode, ISD::SETOLE,
+/* 33487*/ OPC_MoveParent,
+/* 33488*/ OPC_CheckType, MVT::i32,
+/* 33490*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 33492*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33500*/ /*Scope*/ 15, /*->33516*/
+/* 33501*/ OPC_CheckCondCode, ISD::SETULE,
+/* 33503*/ OPC_MoveParent,
+/* 33504*/ OPC_CheckType, MVT::i32,
+/* 33506*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 33508*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_ULE_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 33516*/ /*Scope*/ 15, /*->33532*/
+/* 33517*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 33519*/ OPC_MoveParent,
+/* 33520*/ OPC_CheckType, MVT::i32,
+/* 33522*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33524*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_EQ_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
+/* 33532*/ /*Scope*/ 15, /*->33548*/
+/* 33533*/ OPC_CheckCondCode, ISD::SETGT,
+/* 33535*/ OPC_MoveParent,
+/* 33536*/ OPC_CheckType, MVT::i32,
+/* 33538*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33540*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$rhs, f64:{ *:[f64] }:$lhs)
+/* 33548*/ /*Scope*/ 15, /*->33564*/
+/* 33549*/ OPC_CheckCondCode, ISD::SETGE,
+/* 33551*/ OPC_MoveParent,
+/* 33552*/ OPC_CheckType, MVT::i32,
+/* 33554*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33556*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$rhs, f64:{ *:[f64] }:$lhs)
+/* 33564*/ /*Scope*/ 15, /*->33580*/
+/* 33565*/ OPC_CheckCondCode, ISD::SETLT,
+/* 33567*/ OPC_MoveParent,
+/* 33568*/ OPC_CheckType, MVT::i32,
+/* 33570*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33572*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LT_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LT_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
+/* 33580*/ /*Scope*/ 15, /*->33596*/
+/* 33581*/ OPC_CheckCondCode, ISD::SETLE,
+/* 33583*/ OPC_MoveParent,
+/* 33584*/ OPC_CheckType, MVT::i32,
+/* 33586*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33588*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CMP_LE_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CMP_LE_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
+/* 33596*/ /*Scope*/ 26, /*->33623*/
+/* 33597*/ OPC_CheckCondCode, ISD::SETONE,
+/* 33599*/ OPC_MoveParent,
+/* 33600*/ OPC_CheckType, MVT::i32,
+/* 33602*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33604*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_UEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33612*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33615*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR:{ *:[i32] } (CMP_UEQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
+/* 33623*/ /*Scope*/ 26, /*->33650*/
+/* 33624*/ OPC_CheckCondCode, ISD::SETO,
+/* 33626*/ OPC_MoveParent,
+/* 33627*/ OPC_CheckType, MVT::i32,
+/* 33629*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33631*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_UN_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33639*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33642*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR:{ *:[i32] } (CMP_UN_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
+/* 33650*/ /*Scope*/ 26, /*->33677*/
+/* 33651*/ OPC_CheckCondCode, ISD::SETUNE,
+/* 33653*/ OPC_MoveParent,
+/* 33654*/ OPC_CheckType, MVT::i32,
+/* 33656*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33658*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_EQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33666*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33669*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR:{ *:[i32] } (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
+/* 33677*/ /*Scope*/ 26, /*->33704*/
+/* 33678*/ OPC_CheckCondCode, ISD::SETNE,
+/* 33680*/ OPC_MoveParent,
+/* 33681*/ OPC_CheckType, MVT::i32,
+/* 33683*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 33685*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_EQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33693*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33696*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR:{ *:[i32] } (CMP_EQ_D:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
+/* 33704*/ /*Scope*/ 26, /*->33731*/
+/* 33705*/ OPC_CheckCondCode, ISD::SETONE,
+/* 33707*/ OPC_MoveParent,
+/* 33708*/ OPC_CheckType, MVT::i32,
+/* 33710*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33712*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_UEQ_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33720*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33723*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETONE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR_MMR6:{ *:[i32] } (CMP_UEQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
+/* 33731*/ /*Scope*/ 26, /*->33758*/
+/* 33732*/ OPC_CheckCondCode, ISD::SETO,
+/* 33734*/ OPC_MoveParent,
+/* 33735*/ OPC_CheckType, MVT::i32,
+/* 33737*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33739*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_UN_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33747*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33750*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR_MMR6:{ *:[i32] } (CMP_UN_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
+/* 33758*/ /*Scope*/ 26, /*->33785*/
+/* 33759*/ OPC_CheckCondCode, ISD::SETUNE,
+/* 33761*/ OPC_MoveParent,
+/* 33762*/ OPC_CheckType, MVT::i32,
+/* 33764*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33766*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_EQ_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33774*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33777*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETUNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR_MMR6:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
+/* 33785*/ /*Scope*/ 26, /*->33812*/
+/* 33786*/ OPC_CheckCondCode, ISD::SETNE,
+/* 33788*/ OPC_MoveParent,
+/* 33789*/ OPC_CheckType, MVT::i32,
+/* 33791*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 33793*/ OPC_EmitNode1, TARGET_VAL(Mips::CMP_EQ_D_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 33801*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 33804*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (NOR_MMR6:{ *:[i32] } (CMP_EQ_D_MMR6:{ *:[i32] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs), ZERO:{ *:[i32] })
+/* 33812*/ 0, /*End of Scope*/
+/* 33813*/ /*Scope*/ 53|128,1/*181*/, /*->33996*/
+/* 33815*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 33817*/ OPC_RecordChild1, // #1 = $imm
+/* 33818*/ OPC_MoveChild2,
+/* 33819*/ OPC_Scope, 18, /*->33839*/ // 10 children in Scope
+/* 33821*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 33823*/ OPC_MoveParent,
+/* 33824*/ OPC_CheckType, MVT::v16i8,
+/* 33826*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33828*/ OPC_CheckComplexPat, /*CP*/20, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 33831*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CEQI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm, SETEQ:{ *:[Other] }) - Complexity = 9
+ // Dst: (CEQI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm)
+/* 33839*/ /*Scope*/ 18, /*->33858*/
+/* 33840*/ OPC_CheckCondCode, ISD::SETLE,
+/* 33842*/ OPC_MoveParent,
+/* 33843*/ OPC_CheckType, MVT::v16i8,
+/* 33845*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33847*/ OPC_CheckComplexPat, /*CP*/20, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 33850*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLEI_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm, SETLE:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLEI_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm)
+/* 33858*/ /*Scope*/ 18, /*->33877*/
+/* 33859*/ OPC_CheckCondCode, ISD::SETULE,
+/* 33861*/ OPC_MoveParent,
+/* 33862*/ OPC_CheckType, MVT::v16i8,
+/* 33864*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33866*/ OPC_CheckComplexPat, /*CP*/16, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 33869*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLEI_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm, SETULE:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLEI_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 33877*/ /*Scope*/ 18, /*->33896*/
+/* 33878*/ OPC_CheckCondCode, ISD::SETLT,
+/* 33880*/ OPC_MoveParent,
+/* 33881*/ OPC_CheckType, MVT::v16i8,
+/* 33883*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33885*/ OPC_CheckComplexPat, /*CP*/20, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 33888*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLTI_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm, SETLT:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLTI_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm)
+/* 33896*/ /*Scope*/ 18, /*->33915*/
+/* 33897*/ OPC_CheckCondCode, ISD::SETULT,
+/* 33899*/ OPC_MoveParent,
+/* 33900*/ OPC_CheckType, MVT::v16i8,
+/* 33902*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33904*/ OPC_CheckComplexPat, /*CP*/16, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 33907*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLTI_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm, SETULT:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLTI_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 33915*/ /*Scope*/ 15, /*->33931*/
+/* 33916*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 33918*/ OPC_MoveParent,
+/* 33919*/ OPC_CheckType, MVT::v16i8,
+/* 33921*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33923*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CEQ_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CEQ_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 33931*/ /*Scope*/ 15, /*->33947*/
+/* 33932*/ OPC_CheckCondCode, ISD::SETLE,
+/* 33934*/ OPC_MoveParent,
+/* 33935*/ OPC_CheckType, MVT::v16i8,
+/* 33937*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33939*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLE_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 33947*/ /*Scope*/ 15, /*->33963*/
+/* 33948*/ OPC_CheckCondCode, ISD::SETULE,
+/* 33950*/ OPC_MoveParent,
+/* 33951*/ OPC_CheckType, MVT::v16i8,
+/* 33953*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33955*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLE_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 33963*/ /*Scope*/ 15, /*->33979*/
+/* 33964*/ OPC_CheckCondCode, ISD::SETLT,
+/* 33966*/ OPC_MoveParent,
+/* 33967*/ OPC_CheckType, MVT::v16i8,
+/* 33969*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33971*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLT_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 33979*/ /*Scope*/ 15, /*->33995*/
+/* 33980*/ OPC_CheckCondCode, ISD::SETULT,
+/* 33982*/ OPC_MoveParent,
+/* 33983*/ OPC_CheckType, MVT::v16i8,
+/* 33985*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 33987*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLT_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 33995*/ 0, /*End of Scope*/
+/* 33996*/ /*Scope*/ 53|128,1/*181*/, /*->34179*/
+/* 33998*/ OPC_CheckChild0Type, MVT::v8i16,
+/* 34000*/ OPC_RecordChild1, // #1 = $imm
+/* 34001*/ OPC_MoveChild2,
+/* 34002*/ OPC_Scope, 18, /*->34022*/ // 10 children in Scope
+/* 34004*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 34006*/ OPC_MoveParent,
+/* 34007*/ OPC_CheckType, MVT::v8i16,
+/* 34009*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34011*/ OPC_CheckComplexPat, /*CP*/21, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34014*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CEQI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm, SETEQ:{ *:[Other] }) - Complexity = 9
+ // Dst: (CEQI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm)
+/* 34022*/ /*Scope*/ 18, /*->34041*/
+/* 34023*/ OPC_CheckCondCode, ISD::SETLE,
+/* 34025*/ OPC_MoveParent,
+/* 34026*/ OPC_CheckType, MVT::v8i16,
+/* 34028*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34030*/ OPC_CheckComplexPat, /*CP*/21, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34033*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLEI_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm, SETLE:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLEI_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm)
+/* 34041*/ /*Scope*/ 18, /*->34060*/
+/* 34042*/ OPC_CheckCondCode, ISD::SETULE,
+/* 34044*/ OPC_MoveParent,
+/* 34045*/ OPC_CheckType, MVT::v8i16,
+/* 34047*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34049*/ OPC_CheckComplexPat, /*CP*/17, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 34052*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLEI_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm, SETULE:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLEI_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 34060*/ /*Scope*/ 18, /*->34079*/
+/* 34061*/ OPC_CheckCondCode, ISD::SETLT,
+/* 34063*/ OPC_MoveParent,
+/* 34064*/ OPC_CheckType, MVT::v8i16,
+/* 34066*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34068*/ OPC_CheckComplexPat, /*CP*/21, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34071*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLTI_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm, SETLT:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLTI_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm)
+/* 34079*/ /*Scope*/ 18, /*->34098*/
+/* 34080*/ OPC_CheckCondCode, ISD::SETULT,
+/* 34082*/ OPC_MoveParent,
+/* 34083*/ OPC_CheckType, MVT::v8i16,
+/* 34085*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34087*/ OPC_CheckComplexPat, /*CP*/17, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 34090*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLTI_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm, SETULT:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLTI_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 34098*/ /*Scope*/ 15, /*->34114*/
+/* 34099*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 34101*/ OPC_MoveParent,
+/* 34102*/ OPC_CheckType, MVT::v8i16,
+/* 34104*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34106*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CEQ_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CEQ_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 34114*/ /*Scope*/ 15, /*->34130*/
+/* 34115*/ OPC_CheckCondCode, ISD::SETLE,
+/* 34117*/ OPC_MoveParent,
+/* 34118*/ OPC_CheckType, MVT::v8i16,
+/* 34120*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34122*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLE_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 34130*/ /*Scope*/ 15, /*->34146*/
+/* 34131*/ OPC_CheckCondCode, ISD::SETULE,
+/* 34133*/ OPC_MoveParent,
+/* 34134*/ OPC_CheckType, MVT::v8i16,
+/* 34136*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34138*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLE_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 34146*/ /*Scope*/ 15, /*->34162*/
+/* 34147*/ OPC_CheckCondCode, ISD::SETLT,
+/* 34149*/ OPC_MoveParent,
+/* 34150*/ OPC_CheckType, MVT::v8i16,
+/* 34152*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34154*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLT_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 34162*/ /*Scope*/ 15, /*->34178*/
+/* 34163*/ OPC_CheckCondCode, ISD::SETULT,
+/* 34165*/ OPC_MoveParent,
+/* 34166*/ OPC_CheckType, MVT::v8i16,
+/* 34168*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34170*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLT_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 34178*/ 0, /*End of Scope*/
+/* 34179*/ /*Scope*/ 53|128,1/*181*/, /*->34362*/
+/* 34181*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 34183*/ OPC_RecordChild1, // #1 = $imm
+/* 34184*/ OPC_MoveChild2,
+/* 34185*/ OPC_Scope, 18, /*->34205*/ // 10 children in Scope
+/* 34187*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 34189*/ OPC_MoveParent,
+/* 34190*/ OPC_CheckType, MVT::v4i32,
+/* 34192*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34194*/ OPC_CheckComplexPat, /*CP*/22, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34197*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CEQI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm, SETEQ:{ *:[Other] }) - Complexity = 9
+ // Dst: (CEQI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm)
+/* 34205*/ /*Scope*/ 18, /*->34224*/
+/* 34206*/ OPC_CheckCondCode, ISD::SETLE,
+/* 34208*/ OPC_MoveParent,
+/* 34209*/ OPC_CheckType, MVT::v4i32,
+/* 34211*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34213*/ OPC_CheckComplexPat, /*CP*/22, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34216*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLEI_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm, SETLE:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLEI_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm)
+/* 34224*/ /*Scope*/ 18, /*->34243*/
+/* 34225*/ OPC_CheckCondCode, ISD::SETULE,
+/* 34227*/ OPC_MoveParent,
+/* 34228*/ OPC_CheckType, MVT::v4i32,
+/* 34230*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34232*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 34235*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLEI_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm, SETULE:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLEI_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 34243*/ /*Scope*/ 18, /*->34262*/
+/* 34244*/ OPC_CheckCondCode, ISD::SETLT,
+/* 34246*/ OPC_MoveParent,
+/* 34247*/ OPC_CheckType, MVT::v4i32,
+/* 34249*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34251*/ OPC_CheckComplexPat, /*CP*/22, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34254*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLTI_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm, SETLT:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLTI_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm)
+/* 34262*/ /*Scope*/ 18, /*->34281*/
+/* 34263*/ OPC_CheckCondCode, ISD::SETULT,
+/* 34265*/ OPC_MoveParent,
+/* 34266*/ OPC_CheckType, MVT::v4i32,
+/* 34268*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34270*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 34273*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLTI_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm, SETULT:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLTI_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 34281*/ /*Scope*/ 15, /*->34297*/
+/* 34282*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 34284*/ OPC_MoveParent,
+/* 34285*/ OPC_CheckType, MVT::v4i32,
+/* 34287*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34289*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CEQ_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 34297*/ /*Scope*/ 15, /*->34313*/
+/* 34298*/ OPC_CheckCondCode, ISD::SETLE,
+/* 34300*/ OPC_MoveParent,
+/* 34301*/ OPC_CheckType, MVT::v4i32,
+/* 34303*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34305*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLE_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 34313*/ /*Scope*/ 15, /*->34329*/
+/* 34314*/ OPC_CheckCondCode, ISD::SETULE,
+/* 34316*/ OPC_MoveParent,
+/* 34317*/ OPC_CheckType, MVT::v4i32,
+/* 34319*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34321*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLE_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 34329*/ /*Scope*/ 15, /*->34345*/
+/* 34330*/ OPC_CheckCondCode, ISD::SETLT,
+/* 34332*/ OPC_MoveParent,
+/* 34333*/ OPC_CheckType, MVT::v4i32,
+/* 34335*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34337*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLT_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 34345*/ /*Scope*/ 15, /*->34361*/
+/* 34346*/ OPC_CheckCondCode, ISD::SETULT,
+/* 34348*/ OPC_MoveParent,
+/* 34349*/ OPC_CheckType, MVT::v4i32,
+/* 34351*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34353*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLT_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 34361*/ 0, /*End of Scope*/
+/* 34362*/ /*Scope*/ 53|128,1/*181*/, /*->34545*/
+/* 34364*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 34366*/ OPC_RecordChild1, // #1 = $imm
+/* 34367*/ OPC_MoveChild2,
+/* 34368*/ OPC_Scope, 18, /*->34388*/ // 10 children in Scope
+/* 34370*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 34372*/ OPC_MoveParent,
+/* 34373*/ OPC_CheckType, MVT::v2i64,
+/* 34375*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34377*/ OPC_CheckComplexPat, /*CP*/23, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34380*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CEQI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm, SETEQ:{ *:[Other] }) - Complexity = 9
+ // Dst: (CEQI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm)
+/* 34388*/ /*Scope*/ 18, /*->34407*/
+/* 34389*/ OPC_CheckCondCode, ISD::SETLE,
+/* 34391*/ OPC_MoveParent,
+/* 34392*/ OPC_CheckType, MVT::v2i64,
+/* 34394*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34396*/ OPC_CheckComplexPat, /*CP*/23, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34399*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLEI_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm, SETLE:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLEI_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm)
+/* 34407*/ /*Scope*/ 18, /*->34426*/
+/* 34408*/ OPC_CheckCondCode, ISD::SETULE,
+/* 34410*/ OPC_MoveParent,
+/* 34411*/ OPC_CheckType, MVT::v2i64,
+/* 34413*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34415*/ OPC_CheckComplexPat, /*CP*/19, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 34418*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLEI_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm, SETULE:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLEI_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 34426*/ /*Scope*/ 18, /*->34445*/
+/* 34427*/ OPC_CheckCondCode, ISD::SETLT,
+/* 34429*/ OPC_MoveParent,
+/* 34430*/ OPC_CheckType, MVT::v2i64,
+/* 34432*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34434*/ OPC_CheckComplexPat, /*CP*/23, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 34437*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLTI_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm, SETLT:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLTI_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm)
+/* 34445*/ /*Scope*/ 18, /*->34464*/
+/* 34446*/ OPC_CheckCondCode, ISD::SETULT,
+/* 34448*/ OPC_MoveParent,
+/* 34449*/ OPC_CheckType, MVT::v2i64,
+/* 34451*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34453*/ OPC_CheckComplexPat, /*CP*/19, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 34456*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLTI_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm, SETULT:{ *:[Other] }) - Complexity = 9
+ // Dst: (CLTI_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 34464*/ /*Scope*/ 15, /*->34480*/
+/* 34465*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 34467*/ OPC_MoveParent,
+/* 34468*/ OPC_CheckType, MVT::v2i64,
+/* 34470*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34472*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CEQ_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (CEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 34480*/ /*Scope*/ 15, /*->34496*/
+/* 34481*/ OPC_CheckCondCode, ISD::SETLE,
+/* 34483*/ OPC_MoveParent,
+/* 34484*/ OPC_CheckType, MVT::v2i64,
+/* 34486*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34488*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLE_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 34496*/ /*Scope*/ 15, /*->34512*/
+/* 34497*/ OPC_CheckCondCode, ISD::SETULE,
+/* 34499*/ OPC_MoveParent,
+/* 34500*/ OPC_CheckType, MVT::v2i64,
+/* 34502*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34504*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLE_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 34512*/ /*Scope*/ 15, /*->34528*/
+/* 34513*/ OPC_CheckCondCode, ISD::SETLT,
+/* 34515*/ OPC_MoveParent,
+/* 34516*/ OPC_CheckType, MVT::v2i64,
+/* 34518*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34520*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLT_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 34528*/ /*Scope*/ 15, /*->34544*/
+/* 34529*/ OPC_CheckCondCode, ISD::SETULT,
+/* 34531*/ OPC_MoveParent,
+/* 34532*/ OPC_CheckType, MVT::v2i64,
+/* 34534*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34536*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CLT_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (CLT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 34544*/ 0, /*End of Scope*/
+/* 34545*/ /*Scope*/ 38|128,1/*166*/, /*->34713*/
+/* 34547*/ OPC_CheckChild0Type, MVT::v4f32,
+/* 34549*/ OPC_RecordChild1, // #1 = $wt
+/* 34550*/ OPC_MoveChild2,
+/* 34551*/ OPC_Scope, 15, /*->34568*/ // 10 children in Scope
+/* 34553*/ OPC_CheckCondCode, ISD::SETOEQ,
+/* 34555*/ OPC_MoveParent,
+/* 34556*/ OPC_CheckType, MVT::v4i32,
+/* 34558*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34560*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCEQ_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34568*/ /*Scope*/ 15, /*->34584*/
+/* 34569*/ OPC_CheckCondCode, ISD::SETOLE,
+/* 34571*/ OPC_MoveParent,
+/* 34572*/ OPC_CheckType, MVT::v4i32,
+/* 34574*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34576*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCLE_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34584*/ /*Scope*/ 15, /*->34600*/
+/* 34585*/ OPC_CheckCondCode, ISD::SETOLT,
+/* 34587*/ OPC_MoveParent,
+/* 34588*/ OPC_CheckType, MVT::v4i32,
+/* 34590*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34592*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCLT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34600*/ /*Scope*/ 15, /*->34616*/
+/* 34601*/ OPC_CheckCondCode, ISD::SETONE,
+/* 34603*/ OPC_MoveParent,
+/* 34604*/ OPC_CheckType, MVT::v4i32,
+/* 34606*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34608*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCNE_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETONE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34616*/ /*Scope*/ 15, /*->34632*/
+/* 34617*/ OPC_CheckCondCode, ISD::SETO,
+/* 34619*/ OPC_MoveParent,
+/* 34620*/ OPC_CheckType, MVT::v4i32,
+/* 34622*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34624*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCOR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34632*/ /*Scope*/ 15, /*->34648*/
+/* 34633*/ OPC_CheckCondCode, ISD::SETUEQ,
+/* 34635*/ OPC_MoveParent,
+/* 34636*/ OPC_CheckType, MVT::v4i32,
+/* 34638*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34640*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCUEQ_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETUEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34648*/ /*Scope*/ 15, /*->34664*/
+/* 34649*/ OPC_CheckCondCode, ISD::SETULE,
+/* 34651*/ OPC_MoveParent,
+/* 34652*/ OPC_CheckType, MVT::v4i32,
+/* 34654*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34656*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCULE_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34664*/ /*Scope*/ 15, /*->34680*/
+/* 34665*/ OPC_CheckCondCode, ISD::SETULT,
+/* 34667*/ OPC_MoveParent,
+/* 34668*/ OPC_CheckType, MVT::v4i32,
+/* 34670*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34672*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCULT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34680*/ /*Scope*/ 15, /*->34696*/
+/* 34681*/ OPC_CheckCondCode, ISD::SETUO,
+/* 34683*/ OPC_MoveParent,
+/* 34684*/ OPC_CheckType, MVT::v4i32,
+/* 34686*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34688*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCUN_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34696*/ /*Scope*/ 15, /*->34712*/
+/* 34697*/ OPC_CheckCondCode, ISD::SETUNE,
+/* 34699*/ OPC_MoveParent,
+/* 34700*/ OPC_CheckType, MVT::v4i32,
+/* 34702*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34704*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCUNE_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt, SETUNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 34712*/ 0, /*End of Scope*/
+/* 34713*/ /*Scope*/ 38|128,1/*166*/, /*->34881*/
+/* 34715*/ OPC_CheckChild0Type, MVT::v2f64,
+/* 34717*/ OPC_RecordChild1, // #1 = $wt
+/* 34718*/ OPC_MoveChild2,
+/* 34719*/ OPC_Scope, 15, /*->34736*/ // 10 children in Scope
+/* 34721*/ OPC_CheckCondCode, ISD::SETOEQ,
+/* 34723*/ OPC_MoveParent,
+/* 34724*/ OPC_CheckType, MVT::v2i64,
+/* 34726*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34728*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCEQ_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34736*/ /*Scope*/ 15, /*->34752*/
+/* 34737*/ OPC_CheckCondCode, ISD::SETOLE,
+/* 34739*/ OPC_MoveParent,
+/* 34740*/ OPC_CheckType, MVT::v2i64,
+/* 34742*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34744*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCLE_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34752*/ /*Scope*/ 15, /*->34768*/
+/* 34753*/ OPC_CheckCondCode, ISD::SETOLT,
+/* 34755*/ OPC_MoveParent,
+/* 34756*/ OPC_CheckType, MVT::v2i64,
+/* 34758*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34760*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCLT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34768*/ /*Scope*/ 15, /*->34784*/
+/* 34769*/ OPC_CheckCondCode, ISD::SETONE,
+/* 34771*/ OPC_MoveParent,
+/* 34772*/ OPC_CheckType, MVT::v2i64,
+/* 34774*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34776*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCNE_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETONE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34784*/ /*Scope*/ 15, /*->34800*/
+/* 34785*/ OPC_CheckCondCode, ISD::SETO,
+/* 34787*/ OPC_MoveParent,
+/* 34788*/ OPC_CheckType, MVT::v2i64,
+/* 34790*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34792*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCOR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34800*/ /*Scope*/ 15, /*->34816*/
+/* 34801*/ OPC_CheckCondCode, ISD::SETUEQ,
+/* 34803*/ OPC_MoveParent,
+/* 34804*/ OPC_CheckType, MVT::v2i64,
+/* 34806*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34808*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCUEQ_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETUEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34816*/ /*Scope*/ 15, /*->34832*/
+/* 34817*/ OPC_CheckCondCode, ISD::SETULE,
+/* 34819*/ OPC_MoveParent,
+/* 34820*/ OPC_CheckType, MVT::v2i64,
+/* 34822*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34824*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCULE_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34832*/ /*Scope*/ 15, /*->34848*/
+/* 34833*/ OPC_CheckCondCode, ISD::SETULT,
+/* 34835*/ OPC_MoveParent,
+/* 34836*/ OPC_CheckType, MVT::v2i64,
+/* 34838*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34840*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCULT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34848*/ /*Scope*/ 15, /*->34864*/
+/* 34849*/ OPC_CheckCondCode, ISD::SETUO,
+/* 34851*/ OPC_MoveParent,
+/* 34852*/ OPC_CheckType, MVT::v2i64,
+/* 34854*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34856*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCUN_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34864*/ /*Scope*/ 15, /*->34880*/
+/* 34865*/ OPC_CheckCondCode, ISD::SETUNE,
+/* 34867*/ OPC_MoveParent,
+/* 34868*/ OPC_CheckType, MVT::v2i64,
+/* 34870*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 34872*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCUNE_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (vfsetcc:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt, SETUNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FCUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 34880*/ 0, /*End of Scope*/
+/* 34881*/ 0, /*End of Scope*/
+/* 34882*/ /*SwitchOpcode*/ 76, TARGET_VAL(MipsISD::FPBrcond),// ->34961
+/* 34885*/ OPC_RecordNode, // #0 = 'MipsFPBrcond' chained node
+/* 34886*/ OPC_CaptureGlueInput,
+/* 34887*/ OPC_Scope, 35, /*->34924*/ // 2 children in Scope
+/* 34889*/ OPC_CheckChild1Integer, 0,
+/* 34891*/ OPC_CheckChild1Type, MVT::i32,
+/* 34893*/ OPC_RecordChild2, // #1 = $fcc
+/* 34894*/ OPC_RecordChild3, // #2 = $offset
+/* 34895*/ OPC_MoveChild3,
+/* 34896*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 34899*/ OPC_MoveParent,
+/* 34900*/ OPC_Scope, 10, /*->34912*/ // 2 children in Scope
+/* 34902*/ OPC_CheckPatternPredicate, 63, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 34904*/ OPC_EmitMergeInputChains1_0,
+/* 34905*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BC1F), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (MipsFPBrcond 0:{ *:[i32] }, FCCRegsOpnd:{ *:[i32] }:$fcc, (bb:{ *:[Other] }):$offset) - Complexity = 8
+ // Dst: (BC1F FCCRegsOpnd:{ *:[i32] }:$fcc, (bb:{ *:[Other] }):$offset)
+/* 34912*/ /*Scope*/ 10, /*->34923*/
+/* 34913*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 34915*/ OPC_EmitMergeInputChains1_0,
+/* 34916*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BC1F_MM), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (MipsFPBrcond 0:{ *:[i32] }, FCCRegsOpnd:{ *:[i32] }:$fcc, (bb:{ *:[Other] }):$offset) - Complexity = 8
+ // Dst: (BC1F_MM FCCRegsOpnd:{ *:[i32] }:$fcc, (bb:{ *:[Other] }):$offset)
+/* 34923*/ 0, /*End of Scope*/
+/* 34924*/ /*Scope*/ 35, /*->34960*/
+/* 34925*/ OPC_CheckChild1Integer, 1,
+/* 34927*/ OPC_CheckChild1Type, MVT::i32,
+/* 34929*/ OPC_RecordChild2, // #1 = $fcc
+/* 34930*/ OPC_RecordChild3, // #2 = $offset
+/* 34931*/ OPC_MoveChild3,
+/* 34932*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 34935*/ OPC_MoveParent,
+/* 34936*/ OPC_Scope, 10, /*->34948*/ // 2 children in Scope
+/* 34938*/ OPC_CheckPatternPredicate, 63, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 34940*/ OPC_EmitMergeInputChains1_0,
+/* 34941*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BC1T), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (MipsFPBrcond 1:{ *:[i32] }, FCCRegsOpnd:{ *:[i32] }:$fcc, (bb:{ *:[Other] }):$offset) - Complexity = 8
+ // Dst: (BC1T FCCRegsOpnd:{ *:[i32] }:$fcc, (bb:{ *:[Other] }):$offset)
+/* 34948*/ /*Scope*/ 10, /*->34959*/
+/* 34949*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 34951*/ OPC_EmitMergeInputChains1_0,
+/* 34952*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BC1T_MM), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (MipsFPBrcond 1:{ *:[i32] }, FCCRegsOpnd:{ *:[i32] }:$fcc, (bb:{ *:[Other] }):$offset) - Complexity = 8
+ // Dst: (BC1T_MM FCCRegsOpnd:{ *:[i32] }:$fcc, (bb:{ *:[Other] }):$offset)
+/* 34959*/ 0, /*End of Scope*/
+/* 34960*/ 0, /*End of Scope*/
+/* 34961*/ /*SwitchOpcode*/ 41|128,2/*297*/, TARGET_VAL(ISD::SUB),// ->35262
+/* 34965*/ OPC_Scope, 14, /*->34981*/ // 2 children in Scope
+/* 34967*/ OPC_CheckChild0Integer, 0,
+/* 34969*/ OPC_RecordChild1, // #0 = $r
+/* 34970*/ OPC_CheckType, MVT::i32,
+/* 34972*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 34974*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NegRxRy16), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) - Complexity = 8
+ // Dst: (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
+/* 34981*/ /*Scope*/ 22|128,2/*278*/, /*->35261*/
+/* 34983*/ OPC_RecordChild0, // #0 = $rs
+/* 34984*/ OPC_Scope, 7|128,1/*135*/, /*->35122*/ // 3 children in Scope
+/* 34987*/ OPC_RecordChild1, // #1 = $rt
+/* 34988*/ OPC_SwitchType /*6 cases */, 58, MVT::i32,// ->35049
+/* 34991*/ OPC_Scope, 10, /*->35003*/ // 4 children in Scope
+/* 34993*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 34995*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU16_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) - Complexity = 4
+ // Dst: (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+/* 35003*/ /*Scope*/ 10, /*->35014*/
+/* 35004*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 35006*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 35014*/ /*Scope*/ 10, /*->35025*/
+/* 35015*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 35017*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SubuRxRyRz16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) - Complexity = 3
+ // Dst: (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+/* 35025*/ /*Scope*/ 22, /*->35048*/
+/* 35026*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 35028*/ OPC_Scope, 8, /*->35038*/ // 2 children in Scope
+/* 35030*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU16_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+/* 35038*/ /*Scope*/ 8, /*->35047*/
+/* 35039*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 35047*/ 0, /*End of Scope*/
+/* 35048*/ 0, /*End of Scope*/
+/* 35049*/ /*SwitchType*/ 10, MVT::i64,// ->35061
+/* 35051*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 35053*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSUBu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 35061*/ /*SwitchType*/ 13, MVT::v16i8,// ->35076
+/* 35063*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35065*/ OPC_CheckComplexPat, /*CP*/16, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 35068*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBVI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm) - Complexity = 9
+ // Dst: (SUBVI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 35076*/ /*SwitchType*/ 13, MVT::v8i16,// ->35091
+/* 35078*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35080*/ OPC_CheckComplexPat, /*CP*/17, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 35083*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBVI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm) - Complexity = 9
+ // Dst: (SUBVI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 35091*/ /*SwitchType*/ 13, MVT::v4i32,// ->35106
+/* 35093*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35095*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 35098*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBVI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm) - Complexity = 9
+ // Dst: (SUBVI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 35106*/ /*SwitchType*/ 13, MVT::v2i64,// ->35121
+/* 35108*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35110*/ OPC_CheckComplexPat, /*CP*/19, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 35113*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBVI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm) - Complexity = 9
+ // Dst: (SUBVI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 35121*/ 0, // EndSwitchType
+/* 35122*/ /*Scope*/ 61, /*->35184*/
+/* 35123*/ OPC_MoveChild1,
+/* 35124*/ OPC_CheckOpcode, TARGET_VAL(ISD::MUL),
+/* 35127*/ OPC_RecordChild0, // #1 = $ws
+/* 35128*/ OPC_RecordChild1, // #2 = $wt
+/* 35129*/ OPC_MoveParent,
+/* 35130*/ OPC_SwitchType /*4 cases */, 11, MVT::v16i8,// ->35144
+/* 35133*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35135*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUBV_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 1, 2,
+ // Src: (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) - Complexity = 6
+ // Dst: (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 35144*/ /*SwitchType*/ 11, MVT::v8i16,// ->35157
+/* 35146*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35148*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUBV_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) - Complexity = 6
+ // Dst: (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 35157*/ /*SwitchType*/ 11, MVT::v4i32,// ->35170
+/* 35159*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35161*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUBV_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) - Complexity = 6
+ // Dst: (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 35170*/ /*SwitchType*/ 11, MVT::v2i64,// ->35183
+/* 35172*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35174*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUBV_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) - Complexity = 6
+ // Dst: (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 35183*/ 0, // EndSwitchType
+/* 35184*/ /*Scope*/ 75, /*->35260*/
+/* 35185*/ OPC_RecordChild1, // #1 = $b
+/* 35186*/ OPC_SwitchType /*6 cases */, 10, MVT::v2i16,// ->35199
+/* 35189*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 35191*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBQ_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) - Complexity = 3
+ // Dst: (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+/* 35199*/ /*SwitchType*/ 10, MVT::v4i8,// ->35211
+/* 35201*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 35203*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) - Complexity = 3
+ // Dst: (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
+/* 35211*/ /*SwitchType*/ 10, MVT::v16i8,// ->35223
+/* 35213*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35215*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBV_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 35223*/ /*SwitchType*/ 10, MVT::v8i16,// ->35235
+/* 35225*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35227*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBV_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 35235*/ /*SwitchType*/ 10, MVT::v4i32,// ->35247
+/* 35237*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35239*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBV_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 35247*/ /*SwitchType*/ 10, MVT::v2i64,// ->35259
+/* 35249*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 35251*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBV_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 35259*/ 0, // EndSwitchType
+/* 35260*/ 0, /*End of Scope*/
+/* 35261*/ 0, /*End of Scope*/
+/* 35262*/ /*SwitchOpcode*/ 0|128,17/*2176*/, TARGET_VAL(ISD::OR),// ->37442
+/* 35266*/ OPC_Scope, 20|128,4/*532*/, /*->35801*/ // 13 children in Scope
+/* 35269*/ OPC_RecordChild0, // #0 = $rs
+/* 35270*/ OPC_Scope, 28|128,1/*156*/, /*->35429*/ // 2 children in Scope
+/* 35273*/ OPC_RecordChild1, // #1 = $imm16
+/* 35274*/ OPC_Scope, 78, /*->35354*/ // 3 children in Scope
+/* 35276*/ OPC_MoveChild1,
+/* 35277*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35280*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 35282*/ OPC_MoveParent,
+/* 35283*/ OPC_SwitchType /*2 cases */, 50, MVT::i32,// ->35336
+/* 35286*/ OPC_Scope, 15, /*->35303*/ // 3 children in Scope
+/* 35288*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 35290*/ OPC_EmitConvertToTarget, 1,
+/* 35292*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 35295*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORI_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 8
+ // Dst: (ORI_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm16))
+/* 35303*/ /*Scope*/ 15, /*->35319*/
+/* 35304*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 35306*/ OPC_EmitConvertToTarget, 1,
+/* 35308*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 35311*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm16))
+/* 35319*/ /*Scope*/ 15, /*->35335*/
+/* 35320*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 35322*/ OPC_EmitConvertToTarget, 1,
+/* 35324*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 35327*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3,
+ // Src: (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (ORi_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm16))
+/* 35335*/ 0, /*End of Scope*/
+/* 35336*/ /*SwitchType*/ 15, MVT::i64,// ->35353
+/* 35338*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 35340*/ OPC_EmitConvertToTarget, 1,
+/* 35342*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 35345*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 3,
+ // Src: (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm16) - Complexity = 7
+ // Dst: (ORi64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (LO16:{ *:[i64] } (imm:{ *:[i64] }):$imm16))
+/* 35353*/ 0, // EndSwitchType
+/* 35354*/ /*Scope*/ 60, /*->35415*/
+/* 35355*/ OPC_CheckType, MVT::i32,
+/* 35357*/ OPC_Scope, 10, /*->35369*/ // 4 children in Scope
+/* 35359*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 35361*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 35369*/ /*Scope*/ 10, /*->35380*/
+/* 35370*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 35372*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OrRxRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) - Complexity = 3
+ // Dst: (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+/* 35380*/ /*Scope*/ 22, /*->35403*/
+/* 35381*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 35383*/ OPC_Scope, 8, /*->35393*/ // 2 children in Scope
+/* 35385*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR16_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+/* 35393*/ /*Scope*/ 8, /*->35402*/
+/* 35394*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 35402*/ 0, /*End of Scope*/
+/* 35403*/ /*Scope*/ 10, /*->35414*/
+/* 35404*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 35406*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 35414*/ 0, /*End of Scope*/
+/* 35415*/ /*Scope*/ 12, /*->35428*/
+/* 35416*/ OPC_CheckType, MVT::i64,
+/* 35418*/ OPC_CheckPatternPredicate, 22, // (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())
+/* 35420*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR64), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 35428*/ 0, /*End of Scope*/
+/* 35429*/ /*Scope*/ 113|128,2/*369*/, /*->35800*/
+/* 35431*/ OPC_MoveChild1,
+/* 35432*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 35435*/ OPC_MoveChild0,
+/* 35436*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 35439*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 35441*/ OPC_MoveParent,
+/* 35442*/ OPC_MoveChild1,
+/* 35443*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 35446*/ OPC_Scope, 46|128,1/*174*/, /*->35623*/ // 2 children in Scope
+/* 35449*/ OPC_RecordChild0, // #1 = $wt
+/* 35450*/ OPC_MoveChild1,
+/* 35451*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 35454*/ OPC_MoveChild0,
+/* 35455*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35458*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35460*/ OPC_CheckType, MVT::i32,
+/* 35462*/ OPC_MoveParent,
+/* 35463*/ OPC_MoveChild1,
+/* 35464*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35467*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35469*/ OPC_CheckType, MVT::i32,
+/* 35471*/ OPC_MoveParent,
+/* 35472*/ OPC_MoveChild2,
+/* 35473*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35476*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35478*/ OPC_CheckType, MVT::i32,
+/* 35480*/ OPC_MoveParent,
+/* 35481*/ OPC_MoveChild3,
+/* 35482*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35485*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35487*/ OPC_CheckType, MVT::i32,
+/* 35489*/ OPC_MoveParent,
+/* 35490*/ OPC_MoveChild4,
+/* 35491*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35494*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35496*/ OPC_CheckType, MVT::i32,
+/* 35498*/ OPC_MoveParent,
+/* 35499*/ OPC_MoveChild5,
+/* 35500*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35503*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35505*/ OPC_CheckType, MVT::i32,
+/* 35507*/ OPC_MoveParent,
+/* 35508*/ OPC_MoveChild6,
+/* 35509*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35512*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35514*/ OPC_CheckType, MVT::i32,
+/* 35516*/ OPC_MoveParent,
+/* 35517*/ OPC_MoveChild7,
+/* 35518*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35521*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35523*/ OPC_CheckType, MVT::i32,
+/* 35525*/ OPC_MoveParent,
+/* 35526*/ OPC_MoveChild, 8,
+/* 35528*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35531*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35533*/ OPC_CheckType, MVT::i32,
+/* 35535*/ OPC_MoveParent,
+/* 35536*/ OPC_MoveChild, 9,
+/* 35538*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35541*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35543*/ OPC_CheckType, MVT::i32,
+/* 35545*/ OPC_MoveParent,
+/* 35546*/ OPC_MoveChild, 10,
+/* 35548*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35551*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35553*/ OPC_CheckType, MVT::i32,
+/* 35555*/ OPC_MoveParent,
+/* 35556*/ OPC_MoveChild, 11,
+/* 35558*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35561*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35563*/ OPC_CheckType, MVT::i32,
+/* 35565*/ OPC_MoveParent,
+/* 35566*/ OPC_MoveChild, 12,
+/* 35568*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35571*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35573*/ OPC_CheckType, MVT::i32,
+/* 35575*/ OPC_MoveParent,
+/* 35576*/ OPC_MoveChild, 13,
+/* 35578*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35581*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35583*/ OPC_CheckType, MVT::i32,
+/* 35585*/ OPC_MoveParent,
+/* 35586*/ OPC_MoveChild, 14,
+/* 35588*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35591*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35593*/ OPC_CheckType, MVT::i32,
+/* 35595*/ OPC_MoveParent,
+/* 35596*/ OPC_MoveChild, 15,
+/* 35598*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35601*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35603*/ OPC_CheckType, MVT::i32,
+/* 35605*/ OPC_MoveParent,
+/* 35606*/ OPC_MoveParent,
+/* 35607*/ OPC_CheckType, MVT::v16i8,
+/* 35609*/ OPC_MoveParent,
+/* 35610*/ OPC_MoveParent,
+/* 35611*/ OPC_CheckType, MVT::v16i8,
+/* 35613*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 35615*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))) - Complexity = 80
+ // Dst: (BSET_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 35623*/ /*Scope*/ 46|128,1/*174*/, /*->35799*/
+/* 35625*/ OPC_MoveChild0,
+/* 35626*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 35629*/ OPC_MoveChild0,
+/* 35630*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35633*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35635*/ OPC_CheckType, MVT::i32,
+/* 35637*/ OPC_MoveParent,
+/* 35638*/ OPC_MoveChild1,
+/* 35639*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35642*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35644*/ OPC_CheckType, MVT::i32,
+/* 35646*/ OPC_MoveParent,
+/* 35647*/ OPC_MoveChild2,
+/* 35648*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35651*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35653*/ OPC_CheckType, MVT::i32,
+/* 35655*/ OPC_MoveParent,
+/* 35656*/ OPC_MoveChild3,
+/* 35657*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35660*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35662*/ OPC_CheckType, MVT::i32,
+/* 35664*/ OPC_MoveParent,
+/* 35665*/ OPC_MoveChild4,
+/* 35666*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35669*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35671*/ OPC_CheckType, MVT::i32,
+/* 35673*/ OPC_MoveParent,
+/* 35674*/ OPC_MoveChild5,
+/* 35675*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35678*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35680*/ OPC_CheckType, MVT::i32,
+/* 35682*/ OPC_MoveParent,
+/* 35683*/ OPC_MoveChild6,
+/* 35684*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35687*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35689*/ OPC_CheckType, MVT::i32,
+/* 35691*/ OPC_MoveParent,
+/* 35692*/ OPC_MoveChild7,
+/* 35693*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35696*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35698*/ OPC_CheckType, MVT::i32,
+/* 35700*/ OPC_MoveParent,
+/* 35701*/ OPC_MoveChild, 8,
+/* 35703*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35706*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35708*/ OPC_CheckType, MVT::i32,
+/* 35710*/ OPC_MoveParent,
+/* 35711*/ OPC_MoveChild, 9,
+/* 35713*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35716*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35718*/ OPC_CheckType, MVT::i32,
+/* 35720*/ OPC_MoveParent,
+/* 35721*/ OPC_MoveChild, 10,
+/* 35723*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35726*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35728*/ OPC_CheckType, MVT::i32,
+/* 35730*/ OPC_MoveParent,
+/* 35731*/ OPC_MoveChild, 11,
+/* 35733*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35736*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35738*/ OPC_CheckType, MVT::i32,
+/* 35740*/ OPC_MoveParent,
+/* 35741*/ OPC_MoveChild, 12,
+/* 35743*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35746*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35748*/ OPC_CheckType, MVT::i32,
+/* 35750*/ OPC_MoveParent,
+/* 35751*/ OPC_MoveChild, 13,
+/* 35753*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35756*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35758*/ OPC_CheckType, MVT::i32,
+/* 35760*/ OPC_MoveParent,
+/* 35761*/ OPC_MoveChild, 14,
+/* 35763*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35766*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35768*/ OPC_CheckType, MVT::i32,
+/* 35770*/ OPC_MoveParent,
+/* 35771*/ OPC_MoveChild, 15,
+/* 35773*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35776*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35778*/ OPC_CheckType, MVT::i32,
+/* 35780*/ OPC_MoveParent,
+/* 35781*/ OPC_MoveParent,
+/* 35782*/ OPC_RecordChild1, // #1 = $wt
+/* 35783*/ OPC_CheckType, MVT::v16i8,
+/* 35785*/ OPC_MoveParent,
+/* 35786*/ OPC_MoveParent,
+/* 35787*/ OPC_CheckType, MVT::v16i8,
+/* 35789*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 35791*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))) - Complexity = 80
+ // Dst: (BSET_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 35799*/ 0, /*End of Scope*/
+/* 35800*/ 0, /*End of Scope*/
+/* 35801*/ /*Scope*/ 115|128,2/*371*/, /*->36174*/
+/* 35803*/ OPC_MoveChild0,
+/* 35804*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 35807*/ OPC_MoveChild0,
+/* 35808*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 35811*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 35813*/ OPC_MoveParent,
+/* 35814*/ OPC_MoveChild1,
+/* 35815*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 35818*/ OPC_Scope, 47|128,1/*175*/, /*->35996*/ // 2 children in Scope
+/* 35821*/ OPC_RecordChild0, // #0 = $wt
+/* 35822*/ OPC_MoveChild1,
+/* 35823*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 35826*/ OPC_MoveChild0,
+/* 35827*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35830*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35832*/ OPC_CheckType, MVT::i32,
+/* 35834*/ OPC_MoveParent,
+/* 35835*/ OPC_MoveChild1,
+/* 35836*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35839*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35841*/ OPC_CheckType, MVT::i32,
+/* 35843*/ OPC_MoveParent,
+/* 35844*/ OPC_MoveChild2,
+/* 35845*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35848*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35850*/ OPC_CheckType, MVT::i32,
+/* 35852*/ OPC_MoveParent,
+/* 35853*/ OPC_MoveChild3,
+/* 35854*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35857*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35859*/ OPC_CheckType, MVT::i32,
+/* 35861*/ OPC_MoveParent,
+/* 35862*/ OPC_MoveChild4,
+/* 35863*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35866*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35868*/ OPC_CheckType, MVT::i32,
+/* 35870*/ OPC_MoveParent,
+/* 35871*/ OPC_MoveChild5,
+/* 35872*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35875*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35877*/ OPC_CheckType, MVT::i32,
+/* 35879*/ OPC_MoveParent,
+/* 35880*/ OPC_MoveChild6,
+/* 35881*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35884*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35886*/ OPC_CheckType, MVT::i32,
+/* 35888*/ OPC_MoveParent,
+/* 35889*/ OPC_MoveChild7,
+/* 35890*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35893*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35895*/ OPC_CheckType, MVT::i32,
+/* 35897*/ OPC_MoveParent,
+/* 35898*/ OPC_MoveChild, 8,
+/* 35900*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35903*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35905*/ OPC_CheckType, MVT::i32,
+/* 35907*/ OPC_MoveParent,
+/* 35908*/ OPC_MoveChild, 9,
+/* 35910*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35913*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35915*/ OPC_CheckType, MVT::i32,
+/* 35917*/ OPC_MoveParent,
+/* 35918*/ OPC_MoveChild, 10,
+/* 35920*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35923*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35925*/ OPC_CheckType, MVT::i32,
+/* 35927*/ OPC_MoveParent,
+/* 35928*/ OPC_MoveChild, 11,
+/* 35930*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35933*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35935*/ OPC_CheckType, MVT::i32,
+/* 35937*/ OPC_MoveParent,
+/* 35938*/ OPC_MoveChild, 12,
+/* 35940*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35943*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35945*/ OPC_CheckType, MVT::i32,
+/* 35947*/ OPC_MoveParent,
+/* 35948*/ OPC_MoveChild, 13,
+/* 35950*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35953*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35955*/ OPC_CheckType, MVT::i32,
+/* 35957*/ OPC_MoveParent,
+/* 35958*/ OPC_MoveChild, 14,
+/* 35960*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35963*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35965*/ OPC_CheckType, MVT::i32,
+/* 35967*/ OPC_MoveParent,
+/* 35968*/ OPC_MoveChild, 15,
+/* 35970*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 35973*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 35975*/ OPC_CheckType, MVT::i32,
+/* 35977*/ OPC_MoveParent,
+/* 35978*/ OPC_MoveParent,
+/* 35979*/ OPC_CheckType, MVT::v16i8,
+/* 35981*/ OPC_MoveParent,
+/* 35982*/ OPC_MoveParent,
+/* 35983*/ OPC_RecordChild1, // #1 = $ws
+/* 35984*/ OPC_CheckType, MVT::v16i8,
+/* 35986*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 35988*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))), v16i8:{ *:[v16i8] }:$ws) - Complexity = 80
+ // Dst: (BSET_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 35996*/ /*Scope*/ 47|128,1/*175*/, /*->36173*/
+/* 35998*/ OPC_MoveChild0,
+/* 35999*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36002*/ OPC_MoveChild0,
+/* 36003*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36006*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36008*/ OPC_CheckType, MVT::i32,
+/* 36010*/ OPC_MoveParent,
+/* 36011*/ OPC_MoveChild1,
+/* 36012*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36015*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36017*/ OPC_CheckType, MVT::i32,
+/* 36019*/ OPC_MoveParent,
+/* 36020*/ OPC_MoveChild2,
+/* 36021*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36024*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36026*/ OPC_CheckType, MVT::i32,
+/* 36028*/ OPC_MoveParent,
+/* 36029*/ OPC_MoveChild3,
+/* 36030*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36033*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36035*/ OPC_CheckType, MVT::i32,
+/* 36037*/ OPC_MoveParent,
+/* 36038*/ OPC_MoveChild4,
+/* 36039*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36042*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36044*/ OPC_CheckType, MVT::i32,
+/* 36046*/ OPC_MoveParent,
+/* 36047*/ OPC_MoveChild5,
+/* 36048*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36051*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36053*/ OPC_CheckType, MVT::i32,
+/* 36055*/ OPC_MoveParent,
+/* 36056*/ OPC_MoveChild6,
+/* 36057*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36060*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36062*/ OPC_CheckType, MVT::i32,
+/* 36064*/ OPC_MoveParent,
+/* 36065*/ OPC_MoveChild7,
+/* 36066*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36069*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36071*/ OPC_CheckType, MVT::i32,
+/* 36073*/ OPC_MoveParent,
+/* 36074*/ OPC_MoveChild, 8,
+/* 36076*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36079*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36081*/ OPC_CheckType, MVT::i32,
+/* 36083*/ OPC_MoveParent,
+/* 36084*/ OPC_MoveChild, 9,
+/* 36086*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36089*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36091*/ OPC_CheckType, MVT::i32,
+/* 36093*/ OPC_MoveParent,
+/* 36094*/ OPC_MoveChild, 10,
+/* 36096*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36099*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36101*/ OPC_CheckType, MVT::i32,
+/* 36103*/ OPC_MoveParent,
+/* 36104*/ OPC_MoveChild, 11,
+/* 36106*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36109*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36111*/ OPC_CheckType, MVT::i32,
+/* 36113*/ OPC_MoveParent,
+/* 36114*/ OPC_MoveChild, 12,
+/* 36116*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36119*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36121*/ OPC_CheckType, MVT::i32,
+/* 36123*/ OPC_MoveParent,
+/* 36124*/ OPC_MoveChild, 13,
+/* 36126*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36129*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36131*/ OPC_CheckType, MVT::i32,
+/* 36133*/ OPC_MoveParent,
+/* 36134*/ OPC_MoveChild, 14,
+/* 36136*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36139*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36141*/ OPC_CheckType, MVT::i32,
+/* 36143*/ OPC_MoveParent,
+/* 36144*/ OPC_MoveChild, 15,
+/* 36146*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36149*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 36151*/ OPC_CheckType, MVT::i32,
+/* 36153*/ OPC_MoveParent,
+/* 36154*/ OPC_MoveParent,
+/* 36155*/ OPC_RecordChild1, // #0 = $wt
+/* 36156*/ OPC_CheckType, MVT::v16i8,
+/* 36158*/ OPC_MoveParent,
+/* 36159*/ OPC_MoveParent,
+/* 36160*/ OPC_RecordChild1, // #1 = $ws
+/* 36161*/ OPC_CheckType, MVT::v16i8,
+/* 36163*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36165*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)), v16i8:{ *:[v16i8] }:$ws) - Complexity = 80
+ // Dst: (BSET_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 36173*/ 0, /*End of Scope*/
+/* 36174*/ /*Scope*/ 80|128,1/*208*/, /*->36384*/
+/* 36176*/ OPC_RecordChild0, // #0 = $ws
+/* 36177*/ OPC_MoveChild1,
+/* 36178*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 36181*/ OPC_MoveChild0,
+/* 36182*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36185*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 36187*/ OPC_MoveParent,
+/* 36188*/ OPC_MoveChild1,
+/* 36189*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 36192*/ OPC_Scope, 94, /*->36288*/ // 2 children in Scope
+/* 36194*/ OPC_RecordChild0, // #1 = $wt
+/* 36195*/ OPC_MoveChild1,
+/* 36196*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36199*/ OPC_MoveChild0,
+/* 36200*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36203*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36205*/ OPC_CheckType, MVT::i32,
+/* 36207*/ OPC_MoveParent,
+/* 36208*/ OPC_MoveChild1,
+/* 36209*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36212*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36214*/ OPC_CheckType, MVT::i32,
+/* 36216*/ OPC_MoveParent,
+/* 36217*/ OPC_MoveChild2,
+/* 36218*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36221*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36223*/ OPC_CheckType, MVT::i32,
+/* 36225*/ OPC_MoveParent,
+/* 36226*/ OPC_MoveChild3,
+/* 36227*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36230*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36232*/ OPC_CheckType, MVT::i32,
+/* 36234*/ OPC_MoveParent,
+/* 36235*/ OPC_MoveChild4,
+/* 36236*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36239*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36241*/ OPC_CheckType, MVT::i32,
+/* 36243*/ OPC_MoveParent,
+/* 36244*/ OPC_MoveChild5,
+/* 36245*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36248*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36250*/ OPC_CheckType, MVT::i32,
+/* 36252*/ OPC_MoveParent,
+/* 36253*/ OPC_MoveChild6,
+/* 36254*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36257*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36259*/ OPC_CheckType, MVT::i32,
+/* 36261*/ OPC_MoveParent,
+/* 36262*/ OPC_MoveChild7,
+/* 36263*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36266*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36268*/ OPC_CheckType, MVT::i32,
+/* 36270*/ OPC_MoveParent,
+/* 36271*/ OPC_MoveParent,
+/* 36272*/ OPC_CheckType, MVT::v8i16,
+/* 36274*/ OPC_MoveParent,
+/* 36275*/ OPC_MoveParent,
+/* 36276*/ OPC_CheckType, MVT::v8i16,
+/* 36278*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36280*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))) - Complexity = 48
+ // Dst: (BSET_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 36288*/ /*Scope*/ 94, /*->36383*/
+/* 36289*/ OPC_MoveChild0,
+/* 36290*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36293*/ OPC_MoveChild0,
+/* 36294*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36297*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36299*/ OPC_CheckType, MVT::i32,
+/* 36301*/ OPC_MoveParent,
+/* 36302*/ OPC_MoveChild1,
+/* 36303*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36306*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36308*/ OPC_CheckType, MVT::i32,
+/* 36310*/ OPC_MoveParent,
+/* 36311*/ OPC_MoveChild2,
+/* 36312*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36315*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36317*/ OPC_CheckType, MVT::i32,
+/* 36319*/ OPC_MoveParent,
+/* 36320*/ OPC_MoveChild3,
+/* 36321*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36324*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36326*/ OPC_CheckType, MVT::i32,
+/* 36328*/ OPC_MoveParent,
+/* 36329*/ OPC_MoveChild4,
+/* 36330*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36333*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36335*/ OPC_CheckType, MVT::i32,
+/* 36337*/ OPC_MoveParent,
+/* 36338*/ OPC_MoveChild5,
+/* 36339*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36342*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36344*/ OPC_CheckType, MVT::i32,
+/* 36346*/ OPC_MoveParent,
+/* 36347*/ OPC_MoveChild6,
+/* 36348*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36351*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36353*/ OPC_CheckType, MVT::i32,
+/* 36355*/ OPC_MoveParent,
+/* 36356*/ OPC_MoveChild7,
+/* 36357*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36360*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36362*/ OPC_CheckType, MVT::i32,
+/* 36364*/ OPC_MoveParent,
+/* 36365*/ OPC_MoveParent,
+/* 36366*/ OPC_RecordChild1, // #1 = $wt
+/* 36367*/ OPC_CheckType, MVT::v8i16,
+/* 36369*/ OPC_MoveParent,
+/* 36370*/ OPC_MoveParent,
+/* 36371*/ OPC_CheckType, MVT::v8i16,
+/* 36373*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36375*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))) - Complexity = 48
+ // Dst: (BSET_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 36383*/ 0, /*End of Scope*/
+/* 36384*/ /*Scope*/ 81|128,1/*209*/, /*->36595*/
+/* 36386*/ OPC_MoveChild0,
+/* 36387*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 36390*/ OPC_MoveChild0,
+/* 36391*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36394*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 36396*/ OPC_MoveParent,
+/* 36397*/ OPC_MoveChild1,
+/* 36398*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 36401*/ OPC_Scope, 95, /*->36498*/ // 2 children in Scope
+/* 36403*/ OPC_RecordChild0, // #0 = $wt
+/* 36404*/ OPC_MoveChild1,
+/* 36405*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36408*/ OPC_MoveChild0,
+/* 36409*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36412*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36414*/ OPC_CheckType, MVT::i32,
+/* 36416*/ OPC_MoveParent,
+/* 36417*/ OPC_MoveChild1,
+/* 36418*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36421*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36423*/ OPC_CheckType, MVT::i32,
+/* 36425*/ OPC_MoveParent,
+/* 36426*/ OPC_MoveChild2,
+/* 36427*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36430*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36432*/ OPC_CheckType, MVT::i32,
+/* 36434*/ OPC_MoveParent,
+/* 36435*/ OPC_MoveChild3,
+/* 36436*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36439*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36441*/ OPC_CheckType, MVT::i32,
+/* 36443*/ OPC_MoveParent,
+/* 36444*/ OPC_MoveChild4,
+/* 36445*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36448*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36450*/ OPC_CheckType, MVT::i32,
+/* 36452*/ OPC_MoveParent,
+/* 36453*/ OPC_MoveChild5,
+/* 36454*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36457*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36459*/ OPC_CheckType, MVT::i32,
+/* 36461*/ OPC_MoveParent,
+/* 36462*/ OPC_MoveChild6,
+/* 36463*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36466*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36468*/ OPC_CheckType, MVT::i32,
+/* 36470*/ OPC_MoveParent,
+/* 36471*/ OPC_MoveChild7,
+/* 36472*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36475*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36477*/ OPC_CheckType, MVT::i32,
+/* 36479*/ OPC_MoveParent,
+/* 36480*/ OPC_MoveParent,
+/* 36481*/ OPC_CheckType, MVT::v8i16,
+/* 36483*/ OPC_MoveParent,
+/* 36484*/ OPC_MoveParent,
+/* 36485*/ OPC_RecordChild1, // #1 = $ws
+/* 36486*/ OPC_CheckType, MVT::v8i16,
+/* 36488*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36490*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))), v8i16:{ *:[v8i16] }:$ws) - Complexity = 48
+ // Dst: (BSET_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 36498*/ /*Scope*/ 95, /*->36594*/
+/* 36499*/ OPC_MoveChild0,
+/* 36500*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36503*/ OPC_MoveChild0,
+/* 36504*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36507*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36509*/ OPC_CheckType, MVT::i32,
+/* 36511*/ OPC_MoveParent,
+/* 36512*/ OPC_MoveChild1,
+/* 36513*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36516*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36518*/ OPC_CheckType, MVT::i32,
+/* 36520*/ OPC_MoveParent,
+/* 36521*/ OPC_MoveChild2,
+/* 36522*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36525*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36527*/ OPC_CheckType, MVT::i32,
+/* 36529*/ OPC_MoveParent,
+/* 36530*/ OPC_MoveChild3,
+/* 36531*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36534*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36536*/ OPC_CheckType, MVT::i32,
+/* 36538*/ OPC_MoveParent,
+/* 36539*/ OPC_MoveChild4,
+/* 36540*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36543*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36545*/ OPC_CheckType, MVT::i32,
+/* 36547*/ OPC_MoveParent,
+/* 36548*/ OPC_MoveChild5,
+/* 36549*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36552*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36554*/ OPC_CheckType, MVT::i32,
+/* 36556*/ OPC_MoveParent,
+/* 36557*/ OPC_MoveChild6,
+/* 36558*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36561*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36563*/ OPC_CheckType, MVT::i32,
+/* 36565*/ OPC_MoveParent,
+/* 36566*/ OPC_MoveChild7,
+/* 36567*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36570*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 36572*/ OPC_CheckType, MVT::i32,
+/* 36574*/ OPC_MoveParent,
+/* 36575*/ OPC_MoveParent,
+/* 36576*/ OPC_RecordChild1, // #0 = $wt
+/* 36577*/ OPC_CheckType, MVT::v8i16,
+/* 36579*/ OPC_MoveParent,
+/* 36580*/ OPC_MoveParent,
+/* 36581*/ OPC_RecordChild1, // #1 = $ws
+/* 36582*/ OPC_CheckType, MVT::v8i16,
+/* 36584*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36586*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)), v8i16:{ *:[v8i16] }:$ws) - Complexity = 48
+ // Dst: (BSET_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 36594*/ 0, /*End of Scope*/
+/* 36595*/ /*Scope*/ 8|128,1/*136*/, /*->36733*/
+/* 36597*/ OPC_RecordChild0, // #0 = $ws
+/* 36598*/ OPC_MoveChild1,
+/* 36599*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 36602*/ OPC_MoveChild0,
+/* 36603*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36606*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 36608*/ OPC_MoveParent,
+/* 36609*/ OPC_MoveChild1,
+/* 36610*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 36613*/ OPC_Scope, 58, /*->36673*/ // 2 children in Scope
+/* 36615*/ OPC_RecordChild0, // #1 = $wt
+/* 36616*/ OPC_MoveChild1,
+/* 36617*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36620*/ OPC_MoveChild0,
+/* 36621*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36624*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36626*/ OPC_CheckType, MVT::i32,
+/* 36628*/ OPC_MoveParent,
+/* 36629*/ OPC_MoveChild1,
+/* 36630*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36633*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36635*/ OPC_CheckType, MVT::i32,
+/* 36637*/ OPC_MoveParent,
+/* 36638*/ OPC_MoveChild2,
+/* 36639*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36642*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36644*/ OPC_CheckType, MVT::i32,
+/* 36646*/ OPC_MoveParent,
+/* 36647*/ OPC_MoveChild3,
+/* 36648*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36651*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36653*/ OPC_CheckType, MVT::i32,
+/* 36655*/ OPC_MoveParent,
+/* 36656*/ OPC_MoveParent,
+/* 36657*/ OPC_CheckType, MVT::v4i32,
+/* 36659*/ OPC_MoveParent,
+/* 36660*/ OPC_MoveParent,
+/* 36661*/ OPC_CheckType, MVT::v4i32,
+/* 36663*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36665*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))) - Complexity = 32
+ // Dst: (BSET_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 36673*/ /*Scope*/ 58, /*->36732*/
+/* 36674*/ OPC_MoveChild0,
+/* 36675*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36678*/ OPC_MoveChild0,
+/* 36679*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36682*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36684*/ OPC_CheckType, MVT::i32,
+/* 36686*/ OPC_MoveParent,
+/* 36687*/ OPC_MoveChild1,
+/* 36688*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36691*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36693*/ OPC_CheckType, MVT::i32,
+/* 36695*/ OPC_MoveParent,
+/* 36696*/ OPC_MoveChild2,
+/* 36697*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36700*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36702*/ OPC_CheckType, MVT::i32,
+/* 36704*/ OPC_MoveParent,
+/* 36705*/ OPC_MoveChild3,
+/* 36706*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36709*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36711*/ OPC_CheckType, MVT::i32,
+/* 36713*/ OPC_MoveParent,
+/* 36714*/ OPC_MoveParent,
+/* 36715*/ OPC_RecordChild1, // #1 = $wt
+/* 36716*/ OPC_CheckType, MVT::v4i32,
+/* 36718*/ OPC_MoveParent,
+/* 36719*/ OPC_MoveParent,
+/* 36720*/ OPC_CheckType, MVT::v4i32,
+/* 36722*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36724*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))) - Complexity = 32
+ // Dst: (BSET_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 36732*/ 0, /*End of Scope*/
+/* 36733*/ /*Scope*/ 9|128,1/*137*/, /*->36872*/
+/* 36735*/ OPC_MoveChild0,
+/* 36736*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 36739*/ OPC_MoveChild0,
+/* 36740*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36743*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 36745*/ OPC_MoveParent,
+/* 36746*/ OPC_MoveChild1,
+/* 36747*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 36750*/ OPC_Scope, 59, /*->36811*/ // 2 children in Scope
+/* 36752*/ OPC_RecordChild0, // #0 = $wt
+/* 36753*/ OPC_MoveChild1,
+/* 36754*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36757*/ OPC_MoveChild0,
+/* 36758*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36761*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36763*/ OPC_CheckType, MVT::i32,
+/* 36765*/ OPC_MoveParent,
+/* 36766*/ OPC_MoveChild1,
+/* 36767*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36770*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36772*/ OPC_CheckType, MVT::i32,
+/* 36774*/ OPC_MoveParent,
+/* 36775*/ OPC_MoveChild2,
+/* 36776*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36779*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36781*/ OPC_CheckType, MVT::i32,
+/* 36783*/ OPC_MoveParent,
+/* 36784*/ OPC_MoveChild3,
+/* 36785*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36788*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36790*/ OPC_CheckType, MVT::i32,
+/* 36792*/ OPC_MoveParent,
+/* 36793*/ OPC_MoveParent,
+/* 36794*/ OPC_CheckType, MVT::v4i32,
+/* 36796*/ OPC_MoveParent,
+/* 36797*/ OPC_MoveParent,
+/* 36798*/ OPC_RecordChild1, // #1 = $ws
+/* 36799*/ OPC_CheckType, MVT::v4i32,
+/* 36801*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36803*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))), v4i32:{ *:[v4i32] }:$ws) - Complexity = 32
+ // Dst: (BSET_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 36811*/ /*Scope*/ 59, /*->36871*/
+/* 36812*/ OPC_MoveChild0,
+/* 36813*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36816*/ OPC_MoveChild0,
+/* 36817*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36820*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36822*/ OPC_CheckType, MVT::i32,
+/* 36824*/ OPC_MoveParent,
+/* 36825*/ OPC_MoveChild1,
+/* 36826*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36829*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36831*/ OPC_CheckType, MVT::i32,
+/* 36833*/ OPC_MoveParent,
+/* 36834*/ OPC_MoveChild2,
+/* 36835*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36838*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36840*/ OPC_CheckType, MVT::i32,
+/* 36842*/ OPC_MoveParent,
+/* 36843*/ OPC_MoveChild3,
+/* 36844*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 36847*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 36849*/ OPC_CheckType, MVT::i32,
+/* 36851*/ OPC_MoveParent,
+/* 36852*/ OPC_MoveParent,
+/* 36853*/ OPC_RecordChild1, // #0 = $wt
+/* 36854*/ OPC_CheckType, MVT::v4i32,
+/* 36856*/ OPC_MoveParent,
+/* 36857*/ OPC_MoveParent,
+/* 36858*/ OPC_RecordChild1, // #1 = $ws
+/* 36859*/ OPC_CheckType, MVT::v4i32,
+/* 36861*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36863*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)), v4i32:{ *:[v4i32] }:$ws) - Complexity = 32
+ // Dst: (BSET_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 36871*/ 0, /*End of Scope*/
+/* 36872*/ /*Scope*/ 89, /*->36962*/
+/* 36873*/ OPC_RecordChild0, // #0 = $ws
+/* 36874*/ OPC_MoveChild1,
+/* 36875*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 36878*/ OPC_MoveChild0,
+/* 36879*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 36882*/ OPC_MoveChild0,
+/* 36883*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36886*/ OPC_CheckType, MVT::v4i32,
+/* 36888*/ OPC_MoveParent,
+/* 36889*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 36891*/ OPC_MoveParent,
+/* 36892*/ OPC_MoveChild1,
+/* 36893*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 36896*/ OPC_Scope, 31, /*->36929*/ // 2 children in Scope
+/* 36898*/ OPC_RecordChild0, // #1 = $wt
+/* 36899*/ OPC_MoveChild1,
+/* 36900*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 36903*/ OPC_MoveChild0,
+/* 36904*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36907*/ OPC_CheckType, MVT::v4i32,
+/* 36909*/ OPC_MoveParent,
+/* 36910*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 36912*/ OPC_MoveParent,
+/* 36913*/ OPC_CheckType, MVT::v2i64,
+/* 36915*/ OPC_MoveParent,
+/* 36916*/ OPC_MoveParent,
+/* 36917*/ OPC_CheckType, MVT::v2i64,
+/* 36919*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36921*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>))) - Complexity = 23
+ // Dst: (BSET_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 36929*/ /*Scope*/ 31, /*->36961*/
+/* 36930*/ OPC_MoveChild0,
+/* 36931*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 36934*/ OPC_MoveChild0,
+/* 36935*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36938*/ OPC_CheckType, MVT::v4i32,
+/* 36940*/ OPC_MoveParent,
+/* 36941*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 36943*/ OPC_MoveParent,
+/* 36944*/ OPC_RecordChild1, // #1 = $wt
+/* 36945*/ OPC_CheckType, MVT::v2i64,
+/* 36947*/ OPC_MoveParent,
+/* 36948*/ OPC_MoveParent,
+/* 36949*/ OPC_CheckType, MVT::v2i64,
+/* 36951*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 36953*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt))) - Complexity = 23
+ // Dst: (BSET_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 36961*/ 0, /*End of Scope*/
+/* 36962*/ /*Scope*/ 90, /*->37053*/
+/* 36963*/ OPC_MoveChild0,
+/* 36964*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 36967*/ OPC_MoveChild0,
+/* 36968*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 36971*/ OPC_MoveChild0,
+/* 36972*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36975*/ OPC_CheckType, MVT::v4i32,
+/* 36977*/ OPC_MoveParent,
+/* 36978*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 36980*/ OPC_MoveParent,
+/* 36981*/ OPC_MoveChild1,
+/* 36982*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 36985*/ OPC_Scope, 32, /*->37019*/ // 2 children in Scope
+/* 36987*/ OPC_RecordChild0, // #0 = $wt
+/* 36988*/ OPC_MoveChild1,
+/* 36989*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 36992*/ OPC_MoveChild0,
+/* 36993*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 36996*/ OPC_CheckType, MVT::v4i32,
+/* 36998*/ OPC_MoveParent,
+/* 36999*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 37001*/ OPC_MoveParent,
+/* 37002*/ OPC_CheckType, MVT::v2i64,
+/* 37004*/ OPC_MoveParent,
+/* 37005*/ OPC_MoveParent,
+/* 37006*/ OPC_RecordChild1, // #1 = $ws
+/* 37007*/ OPC_CheckType, MVT::v2i64,
+/* 37009*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 37011*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>)), v2i64:{ *:[v2i64] }:$ws) - Complexity = 23
+ // Dst: (BSET_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 37019*/ /*Scope*/ 32, /*->37052*/
+/* 37020*/ OPC_MoveChild0,
+/* 37021*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 37024*/ OPC_MoveChild0,
+/* 37025*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 37028*/ OPC_CheckType, MVT::v4i32,
+/* 37030*/ OPC_MoveParent,
+/* 37031*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 37033*/ OPC_MoveParent,
+/* 37034*/ OPC_RecordChild1, // #0 = $wt
+/* 37035*/ OPC_CheckType, MVT::v2i64,
+/* 37037*/ OPC_MoveParent,
+/* 37038*/ OPC_MoveParent,
+/* 37039*/ OPC_RecordChild1, // #1 = $ws
+/* 37040*/ OPC_CheckType, MVT::v2i64,
+/* 37042*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 37044*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt)), v2i64:{ *:[v2i64] }:$ws) - Complexity = 23
+ // Dst: (BSET_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 37052*/ 0, /*End of Scope*/
+/* 37053*/ /*Scope*/ 35, /*->37089*/
+/* 37054*/ OPC_RecordChild0, // #0 = $ws
+/* 37055*/ OPC_MoveChild1,
+/* 37056*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 37059*/ OPC_MoveChild0,
+/* 37060*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 37063*/ OPC_MoveChild0,
+/* 37064*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 37067*/ OPC_CheckType, MVT::v4i32,
+/* 37069*/ OPC_MoveParent,
+/* 37070*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 37072*/ OPC_MoveParent,
+/* 37073*/ OPC_RecordChild1, // #1 = $wt
+/* 37074*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 37076*/ OPC_MoveParent,
+/* 37077*/ OPC_CheckType, MVT::v2i64,
+/* 37079*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37081*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, MSA128DOpnd:{ *:[v2i64] }:$wt)) - Complexity = 13
+ // Dst: (BSET_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 37089*/ /*Scope*/ 35, /*->37125*/
+/* 37090*/ OPC_MoveChild0,
+/* 37091*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 37094*/ OPC_MoveChild0,
+/* 37095*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 37098*/ OPC_MoveChild0,
+/* 37099*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 37102*/ OPC_CheckType, MVT::v4i32,
+/* 37104*/ OPC_MoveParent,
+/* 37105*/ OPC_CheckPredicate, 42, // Predicate_vsplati64_imm_eq_1
+/* 37107*/ OPC_MoveParent,
+/* 37108*/ OPC_RecordChild1, // #0 = $wt
+/* 37109*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 37111*/ OPC_MoveParent,
+/* 37112*/ OPC_RecordChild1, // #1 = $ws
+/* 37113*/ OPC_CheckType, MVT::v2i64,
+/* 37115*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37117*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v2i64] } (shl:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_1>>, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 13
+ // Dst: (BSET_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 37125*/ /*Scope*/ 63, /*->37189*/
+/* 37126*/ OPC_RecordChild0, // #0 = $ws
+/* 37127*/ OPC_MoveChild1,
+/* 37128*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 37131*/ OPC_MoveChild0,
+/* 37132*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 37135*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 37137*/ OPC_MoveParent,
+/* 37138*/ OPC_RecordChild1, // #1 = $wt
+/* 37139*/ OPC_Scope, 15, /*->37156*/ // 3 children in Scope
+/* 37141*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 37143*/ OPC_MoveParent,
+/* 37144*/ OPC_CheckType, MVT::v16i8,
+/* 37146*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37148*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128BOpnd:{ *:[v16i8] }:$wt)) - Complexity = 10
+ // Dst: (BSET_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 37156*/ /*Scope*/ 15, /*->37172*/
+/* 37157*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 37159*/ OPC_MoveParent,
+/* 37160*/ OPC_CheckType, MVT::v8i16,
+/* 37162*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37164*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128HOpnd:{ *:[v8i16] }:$wt)) - Complexity = 10
+ // Dst: (BSET_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 37172*/ /*Scope*/ 15, /*->37188*/
+/* 37173*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 37175*/ OPC_MoveParent,
+/* 37176*/ OPC_CheckType, MVT::v4i32,
+/* 37178*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37180*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128WOpnd:{ *:[v4i32] }:$wt)) - Complexity = 10
+ // Dst: (BSET_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 37188*/ 0, /*End of Scope*/
+/* 37189*/ /*Scope*/ 65, /*->37255*/
+/* 37190*/ OPC_MoveChild0,
+/* 37191*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 37194*/ OPC_MoveChild0,
+/* 37195*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 37198*/ OPC_CheckPredicate, 38, // Predicate_vsplat_imm_eq_1
+/* 37200*/ OPC_MoveParent,
+/* 37201*/ OPC_RecordChild1, // #0 = $wt
+/* 37202*/ OPC_Scope, 16, /*->37220*/ // 3 children in Scope
+/* 37204*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 37206*/ OPC_MoveParent,
+/* 37207*/ OPC_RecordChild1, // #1 = $ws
+/* 37208*/ OPC_CheckType, MVT::v16i8,
+/* 37210*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37212*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v16i8] } (shl:{ *:[v16i8] } (build_vector:{ *:[v16i8] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 10
+ // Dst: (BSET_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 37220*/ /*Scope*/ 16, /*->37237*/
+/* 37221*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 37223*/ OPC_MoveParent,
+/* 37224*/ OPC_RecordChild1, // #1 = $ws
+/* 37225*/ OPC_CheckType, MVT::v8i16,
+/* 37227*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37229*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v8i16] } (shl:{ *:[v8i16] } (build_vector:{ *:[v8i16] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 10
+ // Dst: (BSET_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 37237*/ /*Scope*/ 16, /*->37254*/
+/* 37238*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 37240*/ OPC_MoveParent,
+/* 37241*/ OPC_RecordChild1, // #1 = $ws
+/* 37242*/ OPC_CheckType, MVT::v4i32,
+/* 37244*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37246*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSET_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (or:{ *:[v4i32] } (shl:{ *:[v4i32] } (build_vector:{ *:[v4i32] })<<P:Predicate_vsplat_imm_eq_1>>, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 10
+ // Dst: (BSET_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 37254*/ 0, /*End of Scope*/
+/* 37255*/ /*Scope*/ 56|128,1/*184*/, /*->37441*/
+/* 37257*/ OPC_RecordChild0, // #0 = $ws
+/* 37258*/ OPC_RecordChild1, // #1 = $m
+/* 37259*/ OPC_SwitchType /*4 cases */, 61, MVT::v16i8,// ->37323
+/* 37262*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37264*/ OPC_Scope, 11, /*->37277*/ // 5 children in Scope
+/* 37266*/ OPC_CheckComplexPat, /*CP*/13, /*#*/1, // selectVSplatUimmPow2:$m #2
+/* 37269*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSETI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_pow2:{ *:[v16i8] }:$m) - Complexity = 9
+ // Dst: (BSETI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_pow2:{ *:[v16i8] }:$m)
+/* 37277*/ /*Scope*/ 11, /*->37289*/
+/* 37278*/ OPC_CheckComplexPat, /*CP*/14, /*#*/1, // selectVSplatUimm8:$u8 #2
+/* 37281*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8) - Complexity = 9
+ // Dst: (ORI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 37289*/ /*Scope*/ 11, /*->37301*/
+/* 37290*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // selectVSplatUimmPow2:$m #2
+/* 37293*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSETI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (or:{ *:[v16i8] } vsplat_uimm_pow2:{ *:[v16i8] }:$m, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (BSETI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_uimm_pow2:{ *:[v16i8] }:$m)
+/* 37301*/ /*Scope*/ 11, /*->37313*/
+/* 37302*/ OPC_CheckComplexPat, /*CP*/14, /*#*/0, // selectVSplatUimm8:$u8 #2
+/* 37305*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (or:{ *:[v16i8] } vsplati8_uimm8:{ *:[v16i8] }:$u8, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (ORI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 37313*/ /*Scope*/ 8, /*->37322*/
+/* 37314*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_V), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 37322*/ 0, /*End of Scope*/
+/* 37323*/ /*SwitchType*/ 37, MVT::v8i16,// ->37362
+/* 37325*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37327*/ OPC_Scope, 11, /*->37340*/ // 3 children in Scope
+/* 37329*/ OPC_CheckComplexPat, /*CP*/13, /*#*/1, // selectVSplatUimmPow2:$m #2
+/* 37332*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSETI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_pow2:{ *:[v8i16] }:$m) - Complexity = 9
+ // Dst: (BSETI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_pow2:{ *:[v8i16] }:$m)
+/* 37340*/ /*Scope*/ 11, /*->37352*/
+/* 37341*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // selectVSplatUimmPow2:$m #2
+/* 37344*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSETI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (or:{ *:[v8i16] } vsplat_uimm_pow2:{ *:[v8i16] }:$m, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (BSETI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_uimm_pow2:{ *:[v8i16] }:$m)
+/* 37352*/ /*Scope*/ 8, /*->37361*/
+/* 37353*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_V_H_PSEUDO), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 37361*/ 0, /*End of Scope*/
+/* 37362*/ /*SwitchType*/ 37, MVT::v4i32,// ->37401
+/* 37364*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37366*/ OPC_Scope, 11, /*->37379*/ // 3 children in Scope
+/* 37368*/ OPC_CheckComplexPat, /*CP*/13, /*#*/1, // selectVSplatUimmPow2:$m #2
+/* 37371*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSETI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_pow2:{ *:[v4i32] }:$m) - Complexity = 9
+ // Dst: (BSETI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_pow2:{ *:[v4i32] }:$m)
+/* 37379*/ /*Scope*/ 11, /*->37391*/
+/* 37380*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // selectVSplatUimmPow2:$m #2
+/* 37383*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSETI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (or:{ *:[v4i32] } vsplat_uimm_pow2:{ *:[v4i32] }:$m, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (BSETI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_uimm_pow2:{ *:[v4i32] }:$m)
+/* 37391*/ /*Scope*/ 8, /*->37400*/
+/* 37392*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_V_W_PSEUDO), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 37400*/ 0, /*End of Scope*/
+/* 37401*/ /*SwitchType*/ 37, MVT::v2i64,// ->37440
+/* 37403*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 37405*/ OPC_Scope, 11, /*->37418*/ // 3 children in Scope
+/* 37407*/ OPC_CheckComplexPat, /*CP*/13, /*#*/1, // selectVSplatUimmPow2:$m #2
+/* 37410*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSETI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_pow2:{ *:[v2i64] }:$m) - Complexity = 9
+ // Dst: (BSETI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_pow2:{ *:[v2i64] }:$m)
+/* 37418*/ /*Scope*/ 11, /*->37430*/
+/* 37419*/ OPC_CheckComplexPat, /*CP*/13, /*#*/0, // selectVSplatUimmPow2:$m #2
+/* 37422*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSETI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (or:{ *:[v2i64] } vsplat_uimm_pow2:{ *:[v2i64] }:$m, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (BSETI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_uimm_pow2:{ *:[v2i64] }:$m)
+/* 37430*/ /*Scope*/ 8, /*->37439*/
+/* 37431*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::OR_V_D_PSEUDO), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 37439*/ 0, /*End of Scope*/
+/* 37440*/ 0, // EndSwitchType
+/* 37441*/ 0, /*End of Scope*/
+/* 37442*/ /*SwitchOpcode*/ 10|128,8/*1034*/, TARGET_VAL(ISD::SHL),// ->38480
+/* 37446*/ OPC_RecordChild0, // #0 = $rt
+/* 37447*/ OPC_Scope, 99, /*->37548*/ // 5 children in Scope
+/* 37449*/ OPC_RecordChild1, // #1 = $shamt
+/* 37450*/ OPC_MoveChild1,
+/* 37451*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37454*/ OPC_CheckType, MVT::i32,
+/* 37456*/ OPC_Scope, 17, /*->37475*/ // 5 children in Scope
+/* 37458*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 37460*/ OPC_MoveParent,
+/* 37461*/ OPC_CheckType, MVT::i32,
+/* 37463*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 37465*/ OPC_EmitConvertToTarget, 1,
+/* 37467*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) - Complexity = 7
+ // Dst: (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 37475*/ /*Scope*/ 17, /*->37493*/
+/* 37476*/ OPC_CheckPredicate, 36, // Predicate_immZExt6
+/* 37478*/ OPC_MoveParent,
+/* 37479*/ OPC_CheckType, MVT::i64,
+/* 37481*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 37483*/ OPC_EmitConvertToTarget, 1,
+/* 37485*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSLL), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) - Complexity = 7
+ // Dst: (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 37493*/ /*Scope*/ 17, /*->37511*/
+/* 37494*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 37496*/ OPC_MoveParent,
+/* 37497*/ OPC_CheckType, MVT::i32,
+/* 37499*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 37501*/ OPC_EmitConvertToTarget, 1,
+/* 37503*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SllX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) - Complexity = 7
+ // Dst: (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+/* 37511*/ /*Scope*/ 17, /*->37529*/
+/* 37512*/ OPC_CheckPredicate, 54, // Predicate_immZExt2Shift
+/* 37514*/ OPC_MoveParent,
+/* 37515*/ OPC_CheckType, MVT::i32,
+/* 37517*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 37519*/ OPC_EmitConvertToTarget, 1,
+/* 37521*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL16_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) - Complexity = 7
+ // Dst: (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
+/* 37529*/ /*Scope*/ 17, /*->37547*/
+/* 37530*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 37532*/ OPC_MoveParent,
+/* 37533*/ OPC_CheckType, MVT::i32,
+/* 37535*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 37537*/ OPC_EmitConvertToTarget, 1,
+/* 37539*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) - Complexity = 7
+ // Dst: (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+/* 37547*/ 0, /*End of Scope*/
+/* 37548*/ /*Scope*/ 31, /*->37580*/
+/* 37549*/ OPC_MoveChild1,
+/* 37550*/ OPC_CheckOpcode, TARGET_VAL(ISD::TRUNCATE),
+/* 37553*/ OPC_RecordChild0, // #1 = $rs
+/* 37554*/ OPC_CheckType, MVT::i32,
+/* 37556*/ OPC_MoveParent,
+/* 37557*/ OPC_CheckType, MVT::i64,
+/* 37559*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 37561*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 37564*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 37572*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSLLV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 3,
+ // Src: (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) - Complexity = 6
+ // Dst: (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
+/* 37580*/ /*Scope*/ 54, /*->37635*/
+/* 37581*/ OPC_RecordChild1, // #1 = $rs
+/* 37582*/ OPC_CheckChild1Type, MVT::i32,
+/* 37584*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->37622
+/* 37587*/ OPC_Scope, 10, /*->37599*/ // 3 children in Scope
+/* 37589*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 37591*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLLV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 37599*/ /*Scope*/ 10, /*->37610*/
+/* 37600*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 37602*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SllvRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) - Complexity = 3
+ // Dst: (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
+/* 37610*/ /*Scope*/ 10, /*->37621*/
+/* 37611*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 37613*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLLV_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) - Complexity = 3
+ // Dst: (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+/* 37621*/ 0, /*End of Scope*/
+/* 37622*/ /*SwitchType*/ 10, MVT::i64,// ->37634
+/* 37624*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 37626*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSLLV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 37634*/ 0, // EndSwitchType
+/* 37635*/ /*Scope*/ 82|128,5/*722*/, /*->38359*/
+/* 37637*/ OPC_MoveChild1,
+/* 37638*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 37641*/ OPC_Scope, 45|128,1/*173*/, /*->37817*/ // 8 children in Scope
+/* 37644*/ OPC_RecordChild0, // #1 = $wt
+/* 37645*/ OPC_MoveChild1,
+/* 37646*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 37649*/ OPC_MoveChild0,
+/* 37650*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37653*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37655*/ OPC_CheckType, MVT::i32,
+/* 37657*/ OPC_MoveParent,
+/* 37658*/ OPC_MoveChild1,
+/* 37659*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37662*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37664*/ OPC_CheckType, MVT::i32,
+/* 37666*/ OPC_MoveParent,
+/* 37667*/ OPC_MoveChild2,
+/* 37668*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37671*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37673*/ OPC_CheckType, MVT::i32,
+/* 37675*/ OPC_MoveParent,
+/* 37676*/ OPC_MoveChild3,
+/* 37677*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37680*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37682*/ OPC_CheckType, MVT::i32,
+/* 37684*/ OPC_MoveParent,
+/* 37685*/ OPC_MoveChild4,
+/* 37686*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37689*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37691*/ OPC_CheckType, MVT::i32,
+/* 37693*/ OPC_MoveParent,
+/* 37694*/ OPC_MoveChild5,
+/* 37695*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37698*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37700*/ OPC_CheckType, MVT::i32,
+/* 37702*/ OPC_MoveParent,
+/* 37703*/ OPC_MoveChild6,
+/* 37704*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37707*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37709*/ OPC_CheckType, MVT::i32,
+/* 37711*/ OPC_MoveParent,
+/* 37712*/ OPC_MoveChild7,
+/* 37713*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37716*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37718*/ OPC_CheckType, MVT::i32,
+/* 37720*/ OPC_MoveParent,
+/* 37721*/ OPC_MoveChild, 8,
+/* 37723*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37726*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37728*/ OPC_CheckType, MVT::i32,
+/* 37730*/ OPC_MoveParent,
+/* 37731*/ OPC_MoveChild, 9,
+/* 37733*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37736*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37738*/ OPC_CheckType, MVT::i32,
+/* 37740*/ OPC_MoveParent,
+/* 37741*/ OPC_MoveChild, 10,
+/* 37743*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37746*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37748*/ OPC_CheckType, MVT::i32,
+/* 37750*/ OPC_MoveParent,
+/* 37751*/ OPC_MoveChild, 11,
+/* 37753*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37756*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37758*/ OPC_CheckType, MVT::i32,
+/* 37760*/ OPC_MoveParent,
+/* 37761*/ OPC_MoveChild, 12,
+/* 37763*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37766*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37768*/ OPC_CheckType, MVT::i32,
+/* 37770*/ OPC_MoveParent,
+/* 37771*/ OPC_MoveChild, 13,
+/* 37773*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37776*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37778*/ OPC_CheckType, MVT::i32,
+/* 37780*/ OPC_MoveParent,
+/* 37781*/ OPC_MoveChild, 14,
+/* 37783*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37786*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37788*/ OPC_CheckType, MVT::i32,
+/* 37790*/ OPC_MoveParent,
+/* 37791*/ OPC_MoveChild, 15,
+/* 37793*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37796*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37798*/ OPC_CheckType, MVT::i32,
+/* 37800*/ OPC_MoveParent,
+/* 37801*/ OPC_MoveParent,
+/* 37802*/ OPC_CheckType, MVT::v16i8,
+/* 37804*/ OPC_MoveParent,
+/* 37805*/ OPC_CheckType, MVT::v16i8,
+/* 37807*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 37809*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) - Complexity = 73
+ // Dst: (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 37817*/ /*Scope*/ 45|128,1/*173*/, /*->37992*/
+/* 37819*/ OPC_MoveChild0,
+/* 37820*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 37823*/ OPC_MoveChild0,
+/* 37824*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37827*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37829*/ OPC_CheckType, MVT::i32,
+/* 37831*/ OPC_MoveParent,
+/* 37832*/ OPC_MoveChild1,
+/* 37833*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37836*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37838*/ OPC_CheckType, MVT::i32,
+/* 37840*/ OPC_MoveParent,
+/* 37841*/ OPC_MoveChild2,
+/* 37842*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37845*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37847*/ OPC_CheckType, MVT::i32,
+/* 37849*/ OPC_MoveParent,
+/* 37850*/ OPC_MoveChild3,
+/* 37851*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37854*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37856*/ OPC_CheckType, MVT::i32,
+/* 37858*/ OPC_MoveParent,
+/* 37859*/ OPC_MoveChild4,
+/* 37860*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37863*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37865*/ OPC_CheckType, MVT::i32,
+/* 37867*/ OPC_MoveParent,
+/* 37868*/ OPC_MoveChild5,
+/* 37869*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37872*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37874*/ OPC_CheckType, MVT::i32,
+/* 37876*/ OPC_MoveParent,
+/* 37877*/ OPC_MoveChild6,
+/* 37878*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37881*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37883*/ OPC_CheckType, MVT::i32,
+/* 37885*/ OPC_MoveParent,
+/* 37886*/ OPC_MoveChild7,
+/* 37887*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37890*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37892*/ OPC_CheckType, MVT::i32,
+/* 37894*/ OPC_MoveParent,
+/* 37895*/ OPC_MoveChild, 8,
+/* 37897*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37900*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37902*/ OPC_CheckType, MVT::i32,
+/* 37904*/ OPC_MoveParent,
+/* 37905*/ OPC_MoveChild, 9,
+/* 37907*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37910*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37912*/ OPC_CheckType, MVT::i32,
+/* 37914*/ OPC_MoveParent,
+/* 37915*/ OPC_MoveChild, 10,
+/* 37917*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37920*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37922*/ OPC_CheckType, MVT::i32,
+/* 37924*/ OPC_MoveParent,
+/* 37925*/ OPC_MoveChild, 11,
+/* 37927*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37930*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37932*/ OPC_CheckType, MVT::i32,
+/* 37934*/ OPC_MoveParent,
+/* 37935*/ OPC_MoveChild, 12,
+/* 37937*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37940*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37942*/ OPC_CheckType, MVT::i32,
+/* 37944*/ OPC_MoveParent,
+/* 37945*/ OPC_MoveChild, 13,
+/* 37947*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37950*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37952*/ OPC_CheckType, MVT::i32,
+/* 37954*/ OPC_MoveParent,
+/* 37955*/ OPC_MoveChild, 14,
+/* 37957*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37960*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37962*/ OPC_CheckType, MVT::i32,
+/* 37964*/ OPC_MoveParent,
+/* 37965*/ OPC_MoveChild, 15,
+/* 37967*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 37970*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 37972*/ OPC_CheckType, MVT::i32,
+/* 37974*/ OPC_MoveParent,
+/* 37975*/ OPC_MoveParent,
+/* 37976*/ OPC_RecordChild1, // #1 = $wt
+/* 37977*/ OPC_CheckType, MVT::v16i8,
+/* 37979*/ OPC_MoveParent,
+/* 37980*/ OPC_CheckType, MVT::v16i8,
+/* 37982*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 37984*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) - Complexity = 73
+ // Dst: (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 37992*/ /*Scope*/ 93, /*->38086*/
+/* 37993*/ OPC_RecordChild0, // #1 = $wt
+/* 37994*/ OPC_MoveChild1,
+/* 37995*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 37998*/ OPC_MoveChild0,
+/* 37999*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38002*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38004*/ OPC_CheckType, MVT::i32,
+/* 38006*/ OPC_MoveParent,
+/* 38007*/ OPC_MoveChild1,
+/* 38008*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38011*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38013*/ OPC_CheckType, MVT::i32,
+/* 38015*/ OPC_MoveParent,
+/* 38016*/ OPC_MoveChild2,
+/* 38017*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38020*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38022*/ OPC_CheckType, MVT::i32,
+/* 38024*/ OPC_MoveParent,
+/* 38025*/ OPC_MoveChild3,
+/* 38026*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38029*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38031*/ OPC_CheckType, MVT::i32,
+/* 38033*/ OPC_MoveParent,
+/* 38034*/ OPC_MoveChild4,
+/* 38035*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38038*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38040*/ OPC_CheckType, MVT::i32,
+/* 38042*/ OPC_MoveParent,
+/* 38043*/ OPC_MoveChild5,
+/* 38044*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38047*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38049*/ OPC_CheckType, MVT::i32,
+/* 38051*/ OPC_MoveParent,
+/* 38052*/ OPC_MoveChild6,
+/* 38053*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38056*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38058*/ OPC_CheckType, MVT::i32,
+/* 38060*/ OPC_MoveParent,
+/* 38061*/ OPC_MoveChild7,
+/* 38062*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38065*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38067*/ OPC_CheckType, MVT::i32,
+/* 38069*/ OPC_MoveParent,
+/* 38070*/ OPC_MoveParent,
+/* 38071*/ OPC_CheckType, MVT::v8i16,
+/* 38073*/ OPC_MoveParent,
+/* 38074*/ OPC_CheckType, MVT::v8i16,
+/* 38076*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 38078*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) - Complexity = 41
+ // Dst: (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 38086*/ /*Scope*/ 93, /*->38180*/
+/* 38087*/ OPC_MoveChild0,
+/* 38088*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 38091*/ OPC_MoveChild0,
+/* 38092*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38095*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38097*/ OPC_CheckType, MVT::i32,
+/* 38099*/ OPC_MoveParent,
+/* 38100*/ OPC_MoveChild1,
+/* 38101*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38104*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38106*/ OPC_CheckType, MVT::i32,
+/* 38108*/ OPC_MoveParent,
+/* 38109*/ OPC_MoveChild2,
+/* 38110*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38113*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38115*/ OPC_CheckType, MVT::i32,
+/* 38117*/ OPC_MoveParent,
+/* 38118*/ OPC_MoveChild3,
+/* 38119*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38122*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38124*/ OPC_CheckType, MVT::i32,
+/* 38126*/ OPC_MoveParent,
+/* 38127*/ OPC_MoveChild4,
+/* 38128*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38131*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38133*/ OPC_CheckType, MVT::i32,
+/* 38135*/ OPC_MoveParent,
+/* 38136*/ OPC_MoveChild5,
+/* 38137*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38140*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38142*/ OPC_CheckType, MVT::i32,
+/* 38144*/ OPC_MoveParent,
+/* 38145*/ OPC_MoveChild6,
+/* 38146*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38149*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38151*/ OPC_CheckType, MVT::i32,
+/* 38153*/ OPC_MoveParent,
+/* 38154*/ OPC_MoveChild7,
+/* 38155*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38158*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 38160*/ OPC_CheckType, MVT::i32,
+/* 38162*/ OPC_MoveParent,
+/* 38163*/ OPC_MoveParent,
+/* 38164*/ OPC_RecordChild1, // #1 = $wt
+/* 38165*/ OPC_CheckType, MVT::v8i16,
+/* 38167*/ OPC_MoveParent,
+/* 38168*/ OPC_CheckType, MVT::v8i16,
+/* 38170*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 38172*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) - Complexity = 41
+ // Dst: (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 38180*/ /*Scope*/ 57, /*->38238*/
+/* 38181*/ OPC_RecordChild0, // #1 = $wt
+/* 38182*/ OPC_MoveChild1,
+/* 38183*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 38186*/ OPC_MoveChild0,
+/* 38187*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38190*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 38192*/ OPC_CheckType, MVT::i32,
+/* 38194*/ OPC_MoveParent,
+/* 38195*/ OPC_MoveChild1,
+/* 38196*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38199*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 38201*/ OPC_CheckType, MVT::i32,
+/* 38203*/ OPC_MoveParent,
+/* 38204*/ OPC_MoveChild2,
+/* 38205*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38208*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 38210*/ OPC_CheckType, MVT::i32,
+/* 38212*/ OPC_MoveParent,
+/* 38213*/ OPC_MoveChild3,
+/* 38214*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38217*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 38219*/ OPC_CheckType, MVT::i32,
+/* 38221*/ OPC_MoveParent,
+/* 38222*/ OPC_MoveParent,
+/* 38223*/ OPC_CheckType, MVT::v4i32,
+/* 38225*/ OPC_MoveParent,
+/* 38226*/ OPC_CheckType, MVT::v4i32,
+/* 38228*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 38230*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) - Complexity = 25
+ // Dst: (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 38238*/ /*Scope*/ 57, /*->38296*/
+/* 38239*/ OPC_MoveChild0,
+/* 38240*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 38243*/ OPC_MoveChild0,
+/* 38244*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38247*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 38249*/ OPC_CheckType, MVT::i32,
+/* 38251*/ OPC_MoveParent,
+/* 38252*/ OPC_MoveChild1,
+/* 38253*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38256*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 38258*/ OPC_CheckType, MVT::i32,
+/* 38260*/ OPC_MoveParent,
+/* 38261*/ OPC_MoveChild2,
+/* 38262*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38265*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 38267*/ OPC_CheckType, MVT::i32,
+/* 38269*/ OPC_MoveParent,
+/* 38270*/ OPC_MoveChild3,
+/* 38271*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38274*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 38276*/ OPC_CheckType, MVT::i32,
+/* 38278*/ OPC_MoveParent,
+/* 38279*/ OPC_MoveParent,
+/* 38280*/ OPC_RecordChild1, // #1 = $wt
+/* 38281*/ OPC_CheckType, MVT::v4i32,
+/* 38283*/ OPC_MoveParent,
+/* 38284*/ OPC_CheckType, MVT::v4i32,
+/* 38286*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 38288*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) - Complexity = 25
+ // Dst: (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 38296*/ /*Scope*/ 30, /*->38327*/
+/* 38297*/ OPC_RecordChild0, // #1 = $wt
+/* 38298*/ OPC_MoveChild1,
+/* 38299*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 38302*/ OPC_MoveChild0,
+/* 38303*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 38306*/ OPC_CheckType, MVT::v4i32,
+/* 38308*/ OPC_MoveParent,
+/* 38309*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 38311*/ OPC_MoveParent,
+/* 38312*/ OPC_CheckType, MVT::v2i64,
+/* 38314*/ OPC_MoveParent,
+/* 38315*/ OPC_CheckType, MVT::v2i64,
+/* 38317*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 38319*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>)) - Complexity = 13
+ // Dst: (SLL_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 38327*/ /*Scope*/ 30, /*->38358*/
+/* 38328*/ OPC_MoveChild0,
+/* 38329*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 38332*/ OPC_MoveChild0,
+/* 38333*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 38336*/ OPC_CheckType, MVT::v4i32,
+/* 38338*/ OPC_MoveParent,
+/* 38339*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 38341*/ OPC_MoveParent,
+/* 38342*/ OPC_RecordChild1, // #1 = $wt
+/* 38343*/ OPC_CheckType, MVT::v2i64,
+/* 38345*/ OPC_MoveParent,
+/* 38346*/ OPC_CheckType, MVT::v2i64,
+/* 38348*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 38350*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt)) - Complexity = 13
+ // Dst: (SLL_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 38358*/ 0, /*End of Scope*/
+/* 38359*/ /*Scope*/ 119, /*->38479*/
+/* 38360*/ OPC_RecordChild1, // #1 = $m
+/* 38361*/ OPC_SwitchType /*4 cases */, 27, MVT::v16i8,// ->38391
+/* 38364*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 38366*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 38368*/ OPC_Scope, 11, /*->38381*/ // 2 children in Scope
+/* 38370*/ OPC_CheckComplexPat, /*CP*/24, /*#*/1, // selectVSplatUimm3:$m #2
+/* 38373*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLLI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm3:{ *:[v16i8] }:$m) - Complexity = 9
+ // Dst: (SLLI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm3:{ *:[v16i8] }:$m)
+/* 38381*/ /*Scope*/ 8, /*->38390*/
+/* 38382*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 38390*/ 0, /*End of Scope*/
+/* 38391*/ /*SwitchType*/ 27, MVT::v8i16,// ->38420
+/* 38393*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 38395*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 38397*/ OPC_Scope, 11, /*->38410*/ // 2 children in Scope
+/* 38399*/ OPC_CheckComplexPat, /*CP*/25, /*#*/1, // selectVSplatUimm4:$m #2
+/* 38402*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLLI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm4:{ *:[v8i16] }:$m) - Complexity = 9
+ // Dst: (SLLI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm4:{ *:[v8i16] }:$m)
+/* 38410*/ /*Scope*/ 8, /*->38419*/
+/* 38411*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 38419*/ 0, /*End of Scope*/
+/* 38420*/ /*SwitchType*/ 27, MVT::v4i32,// ->38449
+/* 38422*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 38424*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 38426*/ OPC_Scope, 11, /*->38439*/ // 2 children in Scope
+/* 38428*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$m #2
+/* 38431*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLLI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$m) - Complexity = 9
+ // Dst: (SLLI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$m)
+/* 38439*/ /*Scope*/ 8, /*->38448*/
+/* 38440*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 38448*/ 0, /*End of Scope*/
+/* 38449*/ /*SwitchType*/ 27, MVT::v2i64,// ->38478
+/* 38451*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 38453*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 38455*/ OPC_Scope, 11, /*->38468*/ // 2 children in Scope
+/* 38457*/ OPC_CheckComplexPat, /*CP*/26, /*#*/1, // selectVSplatUimm6:$m #2
+/* 38460*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLLI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm6:{ *:[v2i64] }:$m) - Complexity = 9
+ // Dst: (SLLI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm6:{ *:[v2i64] }:$m)
+/* 38468*/ /*Scope*/ 8, /*->38477*/
+/* 38469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 38477*/ 0, /*End of Scope*/
+/* 38478*/ 0, // EndSwitchType
+/* 38479*/ 0, /*End of Scope*/
+/* 38480*/ /*SwitchOpcode*/ 10|128,8/*1034*/, TARGET_VAL(ISD::SRL),// ->39518
+/* 38484*/ OPC_RecordChild0, // #0 = $rt
+/* 38485*/ OPC_Scope, 99, /*->38586*/ // 5 children in Scope
+/* 38487*/ OPC_RecordChild1, // #1 = $shamt
+/* 38488*/ OPC_MoveChild1,
+/* 38489*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38492*/ OPC_CheckType, MVT::i32,
+/* 38494*/ OPC_Scope, 17, /*->38513*/ // 5 children in Scope
+/* 38496*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 38498*/ OPC_MoveParent,
+/* 38499*/ OPC_CheckType, MVT::i32,
+/* 38501*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 38503*/ OPC_EmitConvertToTarget, 1,
+/* 38505*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) - Complexity = 7
+ // Dst: (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 38513*/ /*Scope*/ 17, /*->38531*/
+/* 38514*/ OPC_CheckPredicate, 36, // Predicate_immZExt6
+/* 38516*/ OPC_MoveParent,
+/* 38517*/ OPC_CheckType, MVT::i64,
+/* 38519*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 38521*/ OPC_EmitConvertToTarget, 1,
+/* 38523*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRL), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) - Complexity = 7
+ // Dst: (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 38531*/ /*Scope*/ 17, /*->38549*/
+/* 38532*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 38534*/ OPC_MoveParent,
+/* 38535*/ OPC_CheckType, MVT::i32,
+/* 38537*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 38539*/ OPC_EmitConvertToTarget, 1,
+/* 38541*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SrlX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) - Complexity = 7
+ // Dst: (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+/* 38549*/ /*Scope*/ 17, /*->38567*/
+/* 38550*/ OPC_CheckPredicate, 54, // Predicate_immZExt2Shift
+/* 38552*/ OPC_MoveParent,
+/* 38553*/ OPC_CheckType, MVT::i32,
+/* 38555*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 38557*/ OPC_EmitConvertToTarget, 1,
+/* 38559*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL16_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) - Complexity = 7
+ // Dst: (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
+/* 38567*/ /*Scope*/ 17, /*->38585*/
+/* 38568*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 38570*/ OPC_MoveParent,
+/* 38571*/ OPC_CheckType, MVT::i32,
+/* 38573*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 38575*/ OPC_EmitConvertToTarget, 1,
+/* 38577*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) - Complexity = 7
+ // Dst: (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+/* 38585*/ 0, /*End of Scope*/
+/* 38586*/ /*Scope*/ 31, /*->38618*/
+/* 38587*/ OPC_MoveChild1,
+/* 38588*/ OPC_CheckOpcode, TARGET_VAL(ISD::TRUNCATE),
+/* 38591*/ OPC_RecordChild0, // #1 = $rs
+/* 38592*/ OPC_CheckType, MVT::i32,
+/* 38594*/ OPC_MoveParent,
+/* 38595*/ OPC_CheckType, MVT::i64,
+/* 38597*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 38599*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 38602*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 38610*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRLV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 3,
+ // Src: (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) - Complexity = 6
+ // Dst: (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
+/* 38618*/ /*Scope*/ 54, /*->38673*/
+/* 38619*/ OPC_RecordChild1, // #1 = $rs
+/* 38620*/ OPC_CheckChild1Type, MVT::i32,
+/* 38622*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->38660
+/* 38625*/ OPC_Scope, 10, /*->38637*/ // 3 children in Scope
+/* 38627*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 38629*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 38637*/ /*Scope*/ 10, /*->38648*/
+/* 38638*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 38640*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SrlvRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) - Complexity = 3
+ // Dst: (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
+/* 38648*/ /*Scope*/ 10, /*->38659*/
+/* 38649*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 38651*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLV_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) - Complexity = 3
+ // Dst: (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+/* 38659*/ 0, /*End of Scope*/
+/* 38660*/ /*SwitchType*/ 10, MVT::i64,// ->38672
+/* 38662*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 38664*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRLV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 38672*/ 0, // EndSwitchType
+/* 38673*/ /*Scope*/ 82|128,5/*722*/, /*->39397*/
+/* 38675*/ OPC_MoveChild1,
+/* 38676*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 38679*/ OPC_Scope, 45|128,1/*173*/, /*->38855*/ // 8 children in Scope
+/* 38682*/ OPC_RecordChild0, // #1 = $wt
+/* 38683*/ OPC_MoveChild1,
+/* 38684*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 38687*/ OPC_MoveChild0,
+/* 38688*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38691*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38693*/ OPC_CheckType, MVT::i32,
+/* 38695*/ OPC_MoveParent,
+/* 38696*/ OPC_MoveChild1,
+/* 38697*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38700*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38702*/ OPC_CheckType, MVT::i32,
+/* 38704*/ OPC_MoveParent,
+/* 38705*/ OPC_MoveChild2,
+/* 38706*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38709*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38711*/ OPC_CheckType, MVT::i32,
+/* 38713*/ OPC_MoveParent,
+/* 38714*/ OPC_MoveChild3,
+/* 38715*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38718*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38720*/ OPC_CheckType, MVT::i32,
+/* 38722*/ OPC_MoveParent,
+/* 38723*/ OPC_MoveChild4,
+/* 38724*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38727*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38729*/ OPC_CheckType, MVT::i32,
+/* 38731*/ OPC_MoveParent,
+/* 38732*/ OPC_MoveChild5,
+/* 38733*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38736*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38738*/ OPC_CheckType, MVT::i32,
+/* 38740*/ OPC_MoveParent,
+/* 38741*/ OPC_MoveChild6,
+/* 38742*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38745*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38747*/ OPC_CheckType, MVT::i32,
+/* 38749*/ OPC_MoveParent,
+/* 38750*/ OPC_MoveChild7,
+/* 38751*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38754*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38756*/ OPC_CheckType, MVT::i32,
+/* 38758*/ OPC_MoveParent,
+/* 38759*/ OPC_MoveChild, 8,
+/* 38761*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38764*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38766*/ OPC_CheckType, MVT::i32,
+/* 38768*/ OPC_MoveParent,
+/* 38769*/ OPC_MoveChild, 9,
+/* 38771*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38774*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38776*/ OPC_CheckType, MVT::i32,
+/* 38778*/ OPC_MoveParent,
+/* 38779*/ OPC_MoveChild, 10,
+/* 38781*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38784*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38786*/ OPC_CheckType, MVT::i32,
+/* 38788*/ OPC_MoveParent,
+/* 38789*/ OPC_MoveChild, 11,
+/* 38791*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38794*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38796*/ OPC_CheckType, MVT::i32,
+/* 38798*/ OPC_MoveParent,
+/* 38799*/ OPC_MoveChild, 12,
+/* 38801*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38804*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38806*/ OPC_CheckType, MVT::i32,
+/* 38808*/ OPC_MoveParent,
+/* 38809*/ OPC_MoveChild, 13,
+/* 38811*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38814*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38816*/ OPC_CheckType, MVT::i32,
+/* 38818*/ OPC_MoveParent,
+/* 38819*/ OPC_MoveChild, 14,
+/* 38821*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38824*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38826*/ OPC_CheckType, MVT::i32,
+/* 38828*/ OPC_MoveParent,
+/* 38829*/ OPC_MoveChild, 15,
+/* 38831*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38834*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38836*/ OPC_CheckType, MVT::i32,
+/* 38838*/ OPC_MoveParent,
+/* 38839*/ OPC_MoveParent,
+/* 38840*/ OPC_CheckType, MVT::v16i8,
+/* 38842*/ OPC_MoveParent,
+/* 38843*/ OPC_CheckType, MVT::v16i8,
+/* 38845*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 38847*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) - Complexity = 73
+ // Dst: (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 38855*/ /*Scope*/ 45|128,1/*173*/, /*->39030*/
+/* 38857*/ OPC_MoveChild0,
+/* 38858*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 38861*/ OPC_MoveChild0,
+/* 38862*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38865*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38867*/ OPC_CheckType, MVT::i32,
+/* 38869*/ OPC_MoveParent,
+/* 38870*/ OPC_MoveChild1,
+/* 38871*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38874*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38876*/ OPC_CheckType, MVT::i32,
+/* 38878*/ OPC_MoveParent,
+/* 38879*/ OPC_MoveChild2,
+/* 38880*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38883*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38885*/ OPC_CheckType, MVT::i32,
+/* 38887*/ OPC_MoveParent,
+/* 38888*/ OPC_MoveChild3,
+/* 38889*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38892*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38894*/ OPC_CheckType, MVT::i32,
+/* 38896*/ OPC_MoveParent,
+/* 38897*/ OPC_MoveChild4,
+/* 38898*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38901*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38903*/ OPC_CheckType, MVT::i32,
+/* 38905*/ OPC_MoveParent,
+/* 38906*/ OPC_MoveChild5,
+/* 38907*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38910*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38912*/ OPC_CheckType, MVT::i32,
+/* 38914*/ OPC_MoveParent,
+/* 38915*/ OPC_MoveChild6,
+/* 38916*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38919*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38921*/ OPC_CheckType, MVT::i32,
+/* 38923*/ OPC_MoveParent,
+/* 38924*/ OPC_MoveChild7,
+/* 38925*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38928*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38930*/ OPC_CheckType, MVT::i32,
+/* 38932*/ OPC_MoveParent,
+/* 38933*/ OPC_MoveChild, 8,
+/* 38935*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38938*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38940*/ OPC_CheckType, MVT::i32,
+/* 38942*/ OPC_MoveParent,
+/* 38943*/ OPC_MoveChild, 9,
+/* 38945*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38948*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38950*/ OPC_CheckType, MVT::i32,
+/* 38952*/ OPC_MoveParent,
+/* 38953*/ OPC_MoveChild, 10,
+/* 38955*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38958*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38960*/ OPC_CheckType, MVT::i32,
+/* 38962*/ OPC_MoveParent,
+/* 38963*/ OPC_MoveChild, 11,
+/* 38965*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38968*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38970*/ OPC_CheckType, MVT::i32,
+/* 38972*/ OPC_MoveParent,
+/* 38973*/ OPC_MoveChild, 12,
+/* 38975*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38978*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38980*/ OPC_CheckType, MVT::i32,
+/* 38982*/ OPC_MoveParent,
+/* 38983*/ OPC_MoveChild, 13,
+/* 38985*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38988*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 38990*/ OPC_CheckType, MVT::i32,
+/* 38992*/ OPC_MoveParent,
+/* 38993*/ OPC_MoveChild, 14,
+/* 38995*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 38998*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39000*/ OPC_CheckType, MVT::i32,
+/* 39002*/ OPC_MoveParent,
+/* 39003*/ OPC_MoveChild, 15,
+/* 39005*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39008*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39010*/ OPC_CheckType, MVT::i32,
+/* 39012*/ OPC_MoveParent,
+/* 39013*/ OPC_MoveParent,
+/* 39014*/ OPC_RecordChild1, // #1 = $wt
+/* 39015*/ OPC_CheckType, MVT::v16i8,
+/* 39017*/ OPC_MoveParent,
+/* 39018*/ OPC_CheckType, MVT::v16i8,
+/* 39020*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 39022*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) - Complexity = 73
+ // Dst: (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 39030*/ /*Scope*/ 93, /*->39124*/
+/* 39031*/ OPC_RecordChild0, // #1 = $wt
+/* 39032*/ OPC_MoveChild1,
+/* 39033*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 39036*/ OPC_MoveChild0,
+/* 39037*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39040*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39042*/ OPC_CheckType, MVT::i32,
+/* 39044*/ OPC_MoveParent,
+/* 39045*/ OPC_MoveChild1,
+/* 39046*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39049*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39051*/ OPC_CheckType, MVT::i32,
+/* 39053*/ OPC_MoveParent,
+/* 39054*/ OPC_MoveChild2,
+/* 39055*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39058*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39060*/ OPC_CheckType, MVT::i32,
+/* 39062*/ OPC_MoveParent,
+/* 39063*/ OPC_MoveChild3,
+/* 39064*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39067*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39069*/ OPC_CheckType, MVT::i32,
+/* 39071*/ OPC_MoveParent,
+/* 39072*/ OPC_MoveChild4,
+/* 39073*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39076*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39078*/ OPC_CheckType, MVT::i32,
+/* 39080*/ OPC_MoveParent,
+/* 39081*/ OPC_MoveChild5,
+/* 39082*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39085*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39087*/ OPC_CheckType, MVT::i32,
+/* 39089*/ OPC_MoveParent,
+/* 39090*/ OPC_MoveChild6,
+/* 39091*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39094*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39096*/ OPC_CheckType, MVT::i32,
+/* 39098*/ OPC_MoveParent,
+/* 39099*/ OPC_MoveChild7,
+/* 39100*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39103*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39105*/ OPC_CheckType, MVT::i32,
+/* 39107*/ OPC_MoveParent,
+/* 39108*/ OPC_MoveParent,
+/* 39109*/ OPC_CheckType, MVT::v8i16,
+/* 39111*/ OPC_MoveParent,
+/* 39112*/ OPC_CheckType, MVT::v8i16,
+/* 39114*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 39116*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) - Complexity = 41
+ // Dst: (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 39124*/ /*Scope*/ 93, /*->39218*/
+/* 39125*/ OPC_MoveChild0,
+/* 39126*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 39129*/ OPC_MoveChild0,
+/* 39130*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39133*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39135*/ OPC_CheckType, MVT::i32,
+/* 39137*/ OPC_MoveParent,
+/* 39138*/ OPC_MoveChild1,
+/* 39139*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39142*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39144*/ OPC_CheckType, MVT::i32,
+/* 39146*/ OPC_MoveParent,
+/* 39147*/ OPC_MoveChild2,
+/* 39148*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39151*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39153*/ OPC_CheckType, MVT::i32,
+/* 39155*/ OPC_MoveParent,
+/* 39156*/ OPC_MoveChild3,
+/* 39157*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39160*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39162*/ OPC_CheckType, MVT::i32,
+/* 39164*/ OPC_MoveParent,
+/* 39165*/ OPC_MoveChild4,
+/* 39166*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39169*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39171*/ OPC_CheckType, MVT::i32,
+/* 39173*/ OPC_MoveParent,
+/* 39174*/ OPC_MoveChild5,
+/* 39175*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39178*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39180*/ OPC_CheckType, MVT::i32,
+/* 39182*/ OPC_MoveParent,
+/* 39183*/ OPC_MoveChild6,
+/* 39184*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39187*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39189*/ OPC_CheckType, MVT::i32,
+/* 39191*/ OPC_MoveParent,
+/* 39192*/ OPC_MoveChild7,
+/* 39193*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39196*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 39198*/ OPC_CheckType, MVT::i32,
+/* 39200*/ OPC_MoveParent,
+/* 39201*/ OPC_MoveParent,
+/* 39202*/ OPC_RecordChild1, // #1 = $wt
+/* 39203*/ OPC_CheckType, MVT::v8i16,
+/* 39205*/ OPC_MoveParent,
+/* 39206*/ OPC_CheckType, MVT::v8i16,
+/* 39208*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 39210*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) - Complexity = 41
+ // Dst: (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 39218*/ /*Scope*/ 57, /*->39276*/
+/* 39219*/ OPC_RecordChild0, // #1 = $wt
+/* 39220*/ OPC_MoveChild1,
+/* 39221*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 39224*/ OPC_MoveChild0,
+/* 39225*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39228*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 39230*/ OPC_CheckType, MVT::i32,
+/* 39232*/ OPC_MoveParent,
+/* 39233*/ OPC_MoveChild1,
+/* 39234*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39237*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 39239*/ OPC_CheckType, MVT::i32,
+/* 39241*/ OPC_MoveParent,
+/* 39242*/ OPC_MoveChild2,
+/* 39243*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39246*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 39248*/ OPC_CheckType, MVT::i32,
+/* 39250*/ OPC_MoveParent,
+/* 39251*/ OPC_MoveChild3,
+/* 39252*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39255*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 39257*/ OPC_CheckType, MVT::i32,
+/* 39259*/ OPC_MoveParent,
+/* 39260*/ OPC_MoveParent,
+/* 39261*/ OPC_CheckType, MVT::v4i32,
+/* 39263*/ OPC_MoveParent,
+/* 39264*/ OPC_CheckType, MVT::v4i32,
+/* 39266*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 39268*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) - Complexity = 25
+ // Dst: (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 39276*/ /*Scope*/ 57, /*->39334*/
+/* 39277*/ OPC_MoveChild0,
+/* 39278*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 39281*/ OPC_MoveChild0,
+/* 39282*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39285*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 39287*/ OPC_CheckType, MVT::i32,
+/* 39289*/ OPC_MoveParent,
+/* 39290*/ OPC_MoveChild1,
+/* 39291*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39294*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 39296*/ OPC_CheckType, MVT::i32,
+/* 39298*/ OPC_MoveParent,
+/* 39299*/ OPC_MoveChild2,
+/* 39300*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39303*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 39305*/ OPC_CheckType, MVT::i32,
+/* 39307*/ OPC_MoveParent,
+/* 39308*/ OPC_MoveChild3,
+/* 39309*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39312*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 39314*/ OPC_CheckType, MVT::i32,
+/* 39316*/ OPC_MoveParent,
+/* 39317*/ OPC_MoveParent,
+/* 39318*/ OPC_RecordChild1, // #1 = $wt
+/* 39319*/ OPC_CheckType, MVT::v4i32,
+/* 39321*/ OPC_MoveParent,
+/* 39322*/ OPC_CheckType, MVT::v4i32,
+/* 39324*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 39326*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) - Complexity = 25
+ // Dst: (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 39334*/ /*Scope*/ 30, /*->39365*/
+/* 39335*/ OPC_RecordChild0, // #1 = $wt
+/* 39336*/ OPC_MoveChild1,
+/* 39337*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 39340*/ OPC_MoveChild0,
+/* 39341*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 39344*/ OPC_CheckType, MVT::v4i32,
+/* 39346*/ OPC_MoveParent,
+/* 39347*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 39349*/ OPC_MoveParent,
+/* 39350*/ OPC_CheckType, MVT::v2i64,
+/* 39352*/ OPC_MoveParent,
+/* 39353*/ OPC_CheckType, MVT::v2i64,
+/* 39355*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 39357*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>)) - Complexity = 13
+ // Dst: (SRL_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 39365*/ /*Scope*/ 30, /*->39396*/
+/* 39366*/ OPC_MoveChild0,
+/* 39367*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 39370*/ OPC_MoveChild0,
+/* 39371*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 39374*/ OPC_CheckType, MVT::v4i32,
+/* 39376*/ OPC_MoveParent,
+/* 39377*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 39379*/ OPC_MoveParent,
+/* 39380*/ OPC_RecordChild1, // #1 = $wt
+/* 39381*/ OPC_CheckType, MVT::v2i64,
+/* 39383*/ OPC_MoveParent,
+/* 39384*/ OPC_CheckType, MVT::v2i64,
+/* 39386*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 39388*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt)) - Complexity = 13
+ // Dst: (SRL_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 39396*/ 0, /*End of Scope*/
+/* 39397*/ /*Scope*/ 119, /*->39517*/
+/* 39398*/ OPC_RecordChild1, // #1 = $m
+/* 39399*/ OPC_SwitchType /*4 cases */, 27, MVT::v16i8,// ->39429
+/* 39402*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 39404*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 39406*/ OPC_Scope, 11, /*->39419*/ // 2 children in Scope
+/* 39408*/ OPC_CheckComplexPat, /*CP*/24, /*#*/1, // selectVSplatUimm3:$m #2
+/* 39411*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm3:{ *:[v16i8] }:$m) - Complexity = 9
+ // Dst: (SRLI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm3:{ *:[v16i8] }:$m)
+/* 39419*/ /*Scope*/ 8, /*->39428*/
+/* 39420*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 39428*/ 0, /*End of Scope*/
+/* 39429*/ /*SwitchType*/ 27, MVT::v8i16,// ->39458
+/* 39431*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 39433*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 39435*/ OPC_Scope, 11, /*->39448*/ // 2 children in Scope
+/* 39437*/ OPC_CheckComplexPat, /*CP*/25, /*#*/1, // selectVSplatUimm4:$m #2
+/* 39440*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm4:{ *:[v8i16] }:$m) - Complexity = 9
+ // Dst: (SRLI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm4:{ *:[v8i16] }:$m)
+/* 39448*/ /*Scope*/ 8, /*->39457*/
+/* 39449*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 39457*/ 0, /*End of Scope*/
+/* 39458*/ /*SwitchType*/ 27, MVT::v4i32,// ->39487
+/* 39460*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 39462*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 39464*/ OPC_Scope, 11, /*->39477*/ // 2 children in Scope
+/* 39466*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$m #2
+/* 39469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$m) - Complexity = 9
+ // Dst: (SRLI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$m)
+/* 39477*/ /*Scope*/ 8, /*->39486*/
+/* 39478*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 39486*/ 0, /*End of Scope*/
+/* 39487*/ /*SwitchType*/ 27, MVT::v2i64,// ->39516
+/* 39489*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 39491*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 39493*/ OPC_Scope, 11, /*->39506*/ // 2 children in Scope
+/* 39495*/ OPC_CheckComplexPat, /*CP*/26, /*#*/1, // selectVSplatUimm6:$m #2
+/* 39498*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRLI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm6:{ *:[v2i64] }:$m) - Complexity = 9
+ // Dst: (SRLI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm6:{ *:[v2i64] }:$m)
+/* 39506*/ /*Scope*/ 8, /*->39515*/
+/* 39507*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 39515*/ 0, /*End of Scope*/
+/* 39516*/ 0, // EndSwitchType
+/* 39517*/ 0, /*End of Scope*/
+/* 39518*/ /*SwitchOpcode*/ 118|128,7/*1014*/, TARGET_VAL(ISD::SRA),// ->40536
+/* 39522*/ OPC_RecordChild0, // #0 = $rt
+/* 39523*/ OPC_Scope, 79, /*->39604*/ // 5 children in Scope
+/* 39525*/ OPC_RecordChild1, // #1 = $shamt
+/* 39526*/ OPC_MoveChild1,
+/* 39527*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39530*/ OPC_CheckType, MVT::i32,
+/* 39532*/ OPC_Scope, 17, /*->39551*/ // 3 children in Scope
+/* 39534*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 39536*/ OPC_MoveParent,
+/* 39537*/ OPC_CheckType, MVT::i32,
+/* 39539*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 39541*/ OPC_EmitConvertToTarget, 1,
+/* 39543*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) - Complexity = 7
+ // Dst: (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 39551*/ /*Scope*/ 17, /*->39569*/
+/* 39552*/ OPC_CheckPredicate, 36, // Predicate_immZExt6
+/* 39554*/ OPC_MoveParent,
+/* 39555*/ OPC_CheckType, MVT::i64,
+/* 39557*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 39559*/ OPC_EmitConvertToTarget, 1,
+/* 39561*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRA), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) - Complexity = 7
+ // Dst: (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 39569*/ /*Scope*/ 33, /*->39603*/
+/* 39570*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 39572*/ OPC_MoveParent,
+/* 39573*/ OPC_CheckType, MVT::i32,
+/* 39575*/ OPC_Scope, 12, /*->39589*/ // 2 children in Scope
+/* 39577*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 39579*/ OPC_EmitConvertToTarget, 1,
+/* 39581*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SraX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) - Complexity = 7
+ // Dst: (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+/* 39589*/ /*Scope*/ 12, /*->39602*/
+/* 39590*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 39592*/ OPC_EmitConvertToTarget, 1,
+/* 39594*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) - Complexity = 7
+ // Dst: (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+/* 39602*/ 0, /*End of Scope*/
+/* 39603*/ 0, /*End of Scope*/
+/* 39604*/ /*Scope*/ 31, /*->39636*/
+/* 39605*/ OPC_MoveChild1,
+/* 39606*/ OPC_CheckOpcode, TARGET_VAL(ISD::TRUNCATE),
+/* 39609*/ OPC_RecordChild0, // #1 = $rs
+/* 39610*/ OPC_CheckType, MVT::i32,
+/* 39612*/ OPC_MoveParent,
+/* 39613*/ OPC_CheckType, MVT::i64,
+/* 39615*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 39617*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 39620*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 39628*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRAV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 3,
+ // Src: (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) - Complexity = 6
+ // Dst: (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
+/* 39636*/ /*Scope*/ 54, /*->39691*/
+/* 39637*/ OPC_RecordChild1, // #1 = $rs
+/* 39638*/ OPC_CheckChild1Type, MVT::i32,
+/* 39640*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->39678
+/* 39643*/ OPC_Scope, 10, /*->39655*/ // 3 children in Scope
+/* 39645*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 39647*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 39655*/ /*Scope*/ 10, /*->39666*/
+/* 39656*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 39658*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SravRxRy16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) - Complexity = 3
+ // Dst: (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
+/* 39666*/ /*Scope*/ 10, /*->39677*/
+/* 39667*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 39669*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAV_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) - Complexity = 3
+ // Dst: (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+/* 39677*/ 0, /*End of Scope*/
+/* 39678*/ /*SwitchType*/ 10, MVT::i64,// ->39690
+/* 39680*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 39682*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSRAV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 39690*/ 0, // EndSwitchType
+/* 39691*/ /*Scope*/ 82|128,5/*722*/, /*->40415*/
+/* 39693*/ OPC_MoveChild1,
+/* 39694*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 39697*/ OPC_Scope, 45|128,1/*173*/, /*->39873*/ // 8 children in Scope
+/* 39700*/ OPC_RecordChild0, // #1 = $wt
+/* 39701*/ OPC_MoveChild1,
+/* 39702*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 39705*/ OPC_MoveChild0,
+/* 39706*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39709*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39711*/ OPC_CheckType, MVT::i32,
+/* 39713*/ OPC_MoveParent,
+/* 39714*/ OPC_MoveChild1,
+/* 39715*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39718*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39720*/ OPC_CheckType, MVT::i32,
+/* 39722*/ OPC_MoveParent,
+/* 39723*/ OPC_MoveChild2,
+/* 39724*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39727*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39729*/ OPC_CheckType, MVT::i32,
+/* 39731*/ OPC_MoveParent,
+/* 39732*/ OPC_MoveChild3,
+/* 39733*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39736*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39738*/ OPC_CheckType, MVT::i32,
+/* 39740*/ OPC_MoveParent,
+/* 39741*/ OPC_MoveChild4,
+/* 39742*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39745*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39747*/ OPC_CheckType, MVT::i32,
+/* 39749*/ OPC_MoveParent,
+/* 39750*/ OPC_MoveChild5,
+/* 39751*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39754*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39756*/ OPC_CheckType, MVT::i32,
+/* 39758*/ OPC_MoveParent,
+/* 39759*/ OPC_MoveChild6,
+/* 39760*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39763*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39765*/ OPC_CheckType, MVT::i32,
+/* 39767*/ OPC_MoveParent,
+/* 39768*/ OPC_MoveChild7,
+/* 39769*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39772*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39774*/ OPC_CheckType, MVT::i32,
+/* 39776*/ OPC_MoveParent,
+/* 39777*/ OPC_MoveChild, 8,
+/* 39779*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39782*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39784*/ OPC_CheckType, MVT::i32,
+/* 39786*/ OPC_MoveParent,
+/* 39787*/ OPC_MoveChild, 9,
+/* 39789*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39792*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39794*/ OPC_CheckType, MVT::i32,
+/* 39796*/ OPC_MoveParent,
+/* 39797*/ OPC_MoveChild, 10,
+/* 39799*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39802*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39804*/ OPC_CheckType, MVT::i32,
+/* 39806*/ OPC_MoveParent,
+/* 39807*/ OPC_MoveChild, 11,
+/* 39809*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39812*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39814*/ OPC_CheckType, MVT::i32,
+/* 39816*/ OPC_MoveParent,
+/* 39817*/ OPC_MoveChild, 12,
+/* 39819*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39822*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39824*/ OPC_CheckType, MVT::i32,
+/* 39826*/ OPC_MoveParent,
+/* 39827*/ OPC_MoveChild, 13,
+/* 39829*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39832*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39834*/ OPC_CheckType, MVT::i32,
+/* 39836*/ OPC_MoveParent,
+/* 39837*/ OPC_MoveChild, 14,
+/* 39839*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39842*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39844*/ OPC_CheckType, MVT::i32,
+/* 39846*/ OPC_MoveParent,
+/* 39847*/ OPC_MoveChild, 15,
+/* 39849*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39852*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39854*/ OPC_CheckType, MVT::i32,
+/* 39856*/ OPC_MoveParent,
+/* 39857*/ OPC_MoveParent,
+/* 39858*/ OPC_CheckType, MVT::v16i8,
+/* 39860*/ OPC_MoveParent,
+/* 39861*/ OPC_CheckType, MVT::v16i8,
+/* 39863*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 39865*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>))) - Complexity = 73
+ // Dst: (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 39873*/ /*Scope*/ 45|128,1/*173*/, /*->40048*/
+/* 39875*/ OPC_MoveChild0,
+/* 39876*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 39879*/ OPC_MoveChild0,
+/* 39880*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39883*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39885*/ OPC_CheckType, MVT::i32,
+/* 39887*/ OPC_MoveParent,
+/* 39888*/ OPC_MoveChild1,
+/* 39889*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39892*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39894*/ OPC_CheckType, MVT::i32,
+/* 39896*/ OPC_MoveParent,
+/* 39897*/ OPC_MoveChild2,
+/* 39898*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39901*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39903*/ OPC_CheckType, MVT::i32,
+/* 39905*/ OPC_MoveParent,
+/* 39906*/ OPC_MoveChild3,
+/* 39907*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39910*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39912*/ OPC_CheckType, MVT::i32,
+/* 39914*/ OPC_MoveParent,
+/* 39915*/ OPC_MoveChild4,
+/* 39916*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39919*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39921*/ OPC_CheckType, MVT::i32,
+/* 39923*/ OPC_MoveParent,
+/* 39924*/ OPC_MoveChild5,
+/* 39925*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39928*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39930*/ OPC_CheckType, MVT::i32,
+/* 39932*/ OPC_MoveParent,
+/* 39933*/ OPC_MoveChild6,
+/* 39934*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39937*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39939*/ OPC_CheckType, MVT::i32,
+/* 39941*/ OPC_MoveParent,
+/* 39942*/ OPC_MoveChild7,
+/* 39943*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39946*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39948*/ OPC_CheckType, MVT::i32,
+/* 39950*/ OPC_MoveParent,
+/* 39951*/ OPC_MoveChild, 8,
+/* 39953*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39956*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39958*/ OPC_CheckType, MVT::i32,
+/* 39960*/ OPC_MoveParent,
+/* 39961*/ OPC_MoveChild, 9,
+/* 39963*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39966*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39968*/ OPC_CheckType, MVT::i32,
+/* 39970*/ OPC_MoveParent,
+/* 39971*/ OPC_MoveChild, 10,
+/* 39973*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39976*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39978*/ OPC_CheckType, MVT::i32,
+/* 39980*/ OPC_MoveParent,
+/* 39981*/ OPC_MoveChild, 11,
+/* 39983*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39986*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39988*/ OPC_CheckType, MVT::i32,
+/* 39990*/ OPC_MoveParent,
+/* 39991*/ OPC_MoveChild, 12,
+/* 39993*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 39996*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 39998*/ OPC_CheckType, MVT::i32,
+/* 40000*/ OPC_MoveParent,
+/* 40001*/ OPC_MoveChild, 13,
+/* 40003*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40006*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 40008*/ OPC_CheckType, MVT::i32,
+/* 40010*/ OPC_MoveParent,
+/* 40011*/ OPC_MoveChild, 14,
+/* 40013*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40016*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 40018*/ OPC_CheckType, MVT::i32,
+/* 40020*/ OPC_MoveParent,
+/* 40021*/ OPC_MoveChild, 15,
+/* 40023*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40026*/ OPC_CheckPredicate, 39, // Predicate_immi32Cst7
+/* 40028*/ OPC_CheckType, MVT::i32,
+/* 40030*/ OPC_MoveParent,
+/* 40031*/ OPC_MoveParent,
+/* 40032*/ OPC_RecordChild1, // #1 = $wt
+/* 40033*/ OPC_CheckType, MVT::v16i8,
+/* 40035*/ OPC_MoveParent,
+/* 40036*/ OPC_CheckType, MVT::v16i8,
+/* 40038*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 40040*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt)) - Complexity = 73
+ // Dst: (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
+/* 40048*/ /*Scope*/ 93, /*->40142*/
+/* 40049*/ OPC_RecordChild0, // #1 = $wt
+/* 40050*/ OPC_MoveChild1,
+/* 40051*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 40054*/ OPC_MoveChild0,
+/* 40055*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40058*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40060*/ OPC_CheckType, MVT::i32,
+/* 40062*/ OPC_MoveParent,
+/* 40063*/ OPC_MoveChild1,
+/* 40064*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40067*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40069*/ OPC_CheckType, MVT::i32,
+/* 40071*/ OPC_MoveParent,
+/* 40072*/ OPC_MoveChild2,
+/* 40073*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40076*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40078*/ OPC_CheckType, MVT::i32,
+/* 40080*/ OPC_MoveParent,
+/* 40081*/ OPC_MoveChild3,
+/* 40082*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40085*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40087*/ OPC_CheckType, MVT::i32,
+/* 40089*/ OPC_MoveParent,
+/* 40090*/ OPC_MoveChild4,
+/* 40091*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40094*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40096*/ OPC_CheckType, MVT::i32,
+/* 40098*/ OPC_MoveParent,
+/* 40099*/ OPC_MoveChild5,
+/* 40100*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40103*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40105*/ OPC_CheckType, MVT::i32,
+/* 40107*/ OPC_MoveParent,
+/* 40108*/ OPC_MoveChild6,
+/* 40109*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40112*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40114*/ OPC_CheckType, MVT::i32,
+/* 40116*/ OPC_MoveParent,
+/* 40117*/ OPC_MoveChild7,
+/* 40118*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40121*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40123*/ OPC_CheckType, MVT::i32,
+/* 40125*/ OPC_MoveParent,
+/* 40126*/ OPC_MoveParent,
+/* 40127*/ OPC_CheckType, MVT::v8i16,
+/* 40129*/ OPC_MoveParent,
+/* 40130*/ OPC_CheckType, MVT::v8i16,
+/* 40132*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 40134*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>))) - Complexity = 41
+ // Dst: (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 40142*/ /*Scope*/ 93, /*->40236*/
+/* 40143*/ OPC_MoveChild0,
+/* 40144*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 40147*/ OPC_MoveChild0,
+/* 40148*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40151*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40153*/ OPC_CheckType, MVT::i32,
+/* 40155*/ OPC_MoveParent,
+/* 40156*/ OPC_MoveChild1,
+/* 40157*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40160*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40162*/ OPC_CheckType, MVT::i32,
+/* 40164*/ OPC_MoveParent,
+/* 40165*/ OPC_MoveChild2,
+/* 40166*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40169*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40171*/ OPC_CheckType, MVT::i32,
+/* 40173*/ OPC_MoveParent,
+/* 40174*/ OPC_MoveChild3,
+/* 40175*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40178*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40180*/ OPC_CheckType, MVT::i32,
+/* 40182*/ OPC_MoveParent,
+/* 40183*/ OPC_MoveChild4,
+/* 40184*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40187*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40189*/ OPC_CheckType, MVT::i32,
+/* 40191*/ OPC_MoveParent,
+/* 40192*/ OPC_MoveChild5,
+/* 40193*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40196*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40198*/ OPC_CheckType, MVT::i32,
+/* 40200*/ OPC_MoveParent,
+/* 40201*/ OPC_MoveChild6,
+/* 40202*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40205*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40207*/ OPC_CheckType, MVT::i32,
+/* 40209*/ OPC_MoveParent,
+/* 40210*/ OPC_MoveChild7,
+/* 40211*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40214*/ OPC_CheckPredicate, 40, // Predicate_immi32Cst15
+/* 40216*/ OPC_CheckType, MVT::i32,
+/* 40218*/ OPC_MoveParent,
+/* 40219*/ OPC_MoveParent,
+/* 40220*/ OPC_RecordChild1, // #1 = $wt
+/* 40221*/ OPC_CheckType, MVT::v8i16,
+/* 40223*/ OPC_MoveParent,
+/* 40224*/ OPC_CheckType, MVT::v8i16,
+/* 40226*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 40228*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt)) - Complexity = 41
+ // Dst: (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
+/* 40236*/ /*Scope*/ 57, /*->40294*/
+/* 40237*/ OPC_RecordChild0, // #1 = $wt
+/* 40238*/ OPC_MoveChild1,
+/* 40239*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 40242*/ OPC_MoveChild0,
+/* 40243*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40246*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 40248*/ OPC_CheckType, MVT::i32,
+/* 40250*/ OPC_MoveParent,
+/* 40251*/ OPC_MoveChild1,
+/* 40252*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40255*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 40257*/ OPC_CheckType, MVT::i32,
+/* 40259*/ OPC_MoveParent,
+/* 40260*/ OPC_MoveChild2,
+/* 40261*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40264*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 40266*/ OPC_CheckType, MVT::i32,
+/* 40268*/ OPC_MoveParent,
+/* 40269*/ OPC_MoveChild3,
+/* 40270*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40273*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 40275*/ OPC_CheckType, MVT::i32,
+/* 40277*/ OPC_MoveParent,
+/* 40278*/ OPC_MoveParent,
+/* 40279*/ OPC_CheckType, MVT::v4i32,
+/* 40281*/ OPC_MoveParent,
+/* 40282*/ OPC_CheckType, MVT::v4i32,
+/* 40284*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 40286*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>))) - Complexity = 25
+ // Dst: (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 40294*/ /*Scope*/ 57, /*->40352*/
+/* 40295*/ OPC_MoveChild0,
+/* 40296*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 40299*/ OPC_MoveChild0,
+/* 40300*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40303*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 40305*/ OPC_CheckType, MVT::i32,
+/* 40307*/ OPC_MoveParent,
+/* 40308*/ OPC_MoveChild1,
+/* 40309*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40312*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 40314*/ OPC_CheckType, MVT::i32,
+/* 40316*/ OPC_MoveParent,
+/* 40317*/ OPC_MoveChild2,
+/* 40318*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40321*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 40323*/ OPC_CheckType, MVT::i32,
+/* 40325*/ OPC_MoveParent,
+/* 40326*/ OPC_MoveChild3,
+/* 40327*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40330*/ OPC_CheckPredicate, 41, // Predicate_immi32Cst31
+/* 40332*/ OPC_CheckType, MVT::i32,
+/* 40334*/ OPC_MoveParent,
+/* 40335*/ OPC_MoveParent,
+/* 40336*/ OPC_RecordChild1, // #1 = $wt
+/* 40337*/ OPC_CheckType, MVT::v4i32,
+/* 40339*/ OPC_MoveParent,
+/* 40340*/ OPC_CheckType, MVT::v4i32,
+/* 40342*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 40344*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt)) - Complexity = 25
+ // Dst: (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
+/* 40352*/ /*Scope*/ 30, /*->40383*/
+/* 40353*/ OPC_RecordChild0, // #1 = $wt
+/* 40354*/ OPC_MoveChild1,
+/* 40355*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 40358*/ OPC_MoveChild0,
+/* 40359*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 40362*/ OPC_CheckType, MVT::v4i32,
+/* 40364*/ OPC_MoveParent,
+/* 40365*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 40367*/ OPC_MoveParent,
+/* 40368*/ OPC_CheckType, MVT::v2i64,
+/* 40370*/ OPC_MoveParent,
+/* 40371*/ OPC_CheckType, MVT::v2i64,
+/* 40373*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 40375*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (and:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$wt, (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>)) - Complexity = 13
+ // Dst: (SRA_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 40383*/ /*Scope*/ 30, /*->40414*/
+/* 40384*/ OPC_MoveChild0,
+/* 40385*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 40388*/ OPC_MoveChild0,
+/* 40389*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 40392*/ OPC_CheckType, MVT::v4i32,
+/* 40394*/ OPC_MoveParent,
+/* 40395*/ OPC_CheckPredicate, 43, // Predicate_vsplati64_imm_eq_63
+/* 40397*/ OPC_MoveParent,
+/* 40398*/ OPC_RecordChild1, // #1 = $wt
+/* 40399*/ OPC_CheckType, MVT::v2i64,
+/* 40401*/ OPC_MoveParent,
+/* 40402*/ OPC_CheckType, MVT::v2i64,
+/* 40404*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 40406*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (and:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (build_vector:{ *:[v4i32] }))<<P:Predicate_vsplati64_imm_eq_63>>, v2i64:{ *:[v2i64] }:$wt)) - Complexity = 13
+ // Dst: (SRA_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, v2i64:{ *:[v2i64] }:$wt)
+/* 40414*/ 0, /*End of Scope*/
+/* 40415*/ /*Scope*/ 119, /*->40535*/
+/* 40416*/ OPC_RecordChild1, // #1 = $m
+/* 40417*/ OPC_SwitchType /*4 cases */, 27, MVT::v16i8,// ->40447
+/* 40420*/ OPC_CheckChild1Type, MVT::v16i8,
+/* 40422*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 40424*/ OPC_Scope, 11, /*->40437*/ // 2 children in Scope
+/* 40426*/ OPC_CheckComplexPat, /*CP*/24, /*#*/1, // selectVSplatUimm3:$m #2
+/* 40429*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm3:{ *:[v16i8] }:$m) - Complexity = 9
+ // Dst: (SRAI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm3:{ *:[v16i8] }:$m)
+/* 40437*/ /*Scope*/ 8, /*->40446*/
+/* 40438*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 40446*/ 0, /*End of Scope*/
+/* 40447*/ /*SwitchType*/ 27, MVT::v8i16,// ->40476
+/* 40449*/ OPC_CheckChild1Type, MVT::v8i16,
+/* 40451*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 40453*/ OPC_Scope, 11, /*->40466*/ // 2 children in Scope
+/* 40455*/ OPC_CheckComplexPat, /*CP*/25, /*#*/1, // selectVSplatUimm4:$m #2
+/* 40458*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm4:{ *:[v8i16] }:$m) - Complexity = 9
+ // Dst: (SRAI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm4:{ *:[v8i16] }:$m)
+/* 40466*/ /*Scope*/ 8, /*->40475*/
+/* 40467*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 40475*/ 0, /*End of Scope*/
+/* 40476*/ /*SwitchType*/ 27, MVT::v4i32,// ->40505
+/* 40478*/ OPC_CheckChild1Type, MVT::v4i32,
+/* 40480*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 40482*/ OPC_Scope, 11, /*->40495*/ // 2 children in Scope
+/* 40484*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$m #2
+/* 40487*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$m) - Complexity = 9
+ // Dst: (SRAI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$m)
+/* 40495*/ /*Scope*/ 8, /*->40504*/
+/* 40496*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 40504*/ 0, /*End of Scope*/
+/* 40505*/ /*SwitchType*/ 27, MVT::v2i64,// ->40534
+/* 40507*/ OPC_CheckChild1Type, MVT::v2i64,
+/* 40509*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 40511*/ OPC_Scope, 11, /*->40524*/ // 2 children in Scope
+/* 40513*/ OPC_CheckComplexPat, /*CP*/26, /*#*/1, // selectVSplatUimm6:$m #2
+/* 40516*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRAI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm6:{ *:[v2i64] }:$m) - Complexity = 9
+ // Dst: (SRAI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm6:{ *:[v2i64] }:$m)
+/* 40524*/ /*Scope*/ 8, /*->40533*/
+/* 40525*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 40533*/ 0, /*End of Scope*/
+/* 40534*/ 0, // EndSwitchType
+/* 40535*/ 0, /*End of Scope*/
+/* 40536*/ /*SwitchOpcode*/ 15|128,1/*143*/, TARGET_VAL(ISD::ROTR),// ->40683
+/* 40540*/ OPC_RecordChild0, // #0 = $rt
+/* 40541*/ OPC_Scope, 63, /*->40606*/ // 3 children in Scope
+/* 40543*/ OPC_RecordChild1, // #1 = $shamt
+/* 40544*/ OPC_MoveChild1,
+/* 40545*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40548*/ OPC_CheckType, MVT::i32,
+/* 40550*/ OPC_Scope, 17, /*->40569*/ // 3 children in Scope
+/* 40552*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 40554*/ OPC_MoveParent,
+/* 40555*/ OPC_CheckType, MVT::i32,
+/* 40557*/ OPC_CheckPatternPredicate, 53, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 40559*/ OPC_EmitConvertToTarget, 1,
+/* 40561*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ROTR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) - Complexity = 7
+ // Dst: (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 40569*/ /*Scope*/ 17, /*->40587*/
+/* 40570*/ OPC_CheckPredicate, 36, // Predicate_immZExt6
+/* 40572*/ OPC_MoveParent,
+/* 40573*/ OPC_CheckType, MVT::i64,
+/* 40575*/ OPC_CheckPatternPredicate, 54, // (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 40577*/ OPC_EmitConvertToTarget, 1,
+/* 40579*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DROTR), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) - Complexity = 7
+ // Dst: (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 40587*/ /*Scope*/ 17, /*->40605*/
+/* 40588*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 40590*/ OPC_MoveParent,
+/* 40591*/ OPC_CheckType, MVT::i32,
+/* 40593*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 40595*/ OPC_EmitConvertToTarget, 1,
+/* 40597*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ROTR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) - Complexity = 7
+ // Dst: (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
+/* 40605*/ 0, /*End of Scope*/
+/* 40606*/ /*Scope*/ 31, /*->40638*/
+/* 40607*/ OPC_MoveChild1,
+/* 40608*/ OPC_CheckOpcode, TARGET_VAL(ISD::TRUNCATE),
+/* 40611*/ OPC_RecordChild0, // #1 = $rs
+/* 40612*/ OPC_CheckType, MVT::i32,
+/* 40614*/ OPC_MoveParent,
+/* 40615*/ OPC_CheckType, MVT::i64,
+/* 40617*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 40619*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 40622*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 40630*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DROTRV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 3,
+ // Src: (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) - Complexity = 6
+ // Dst: (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
+/* 40638*/ /*Scope*/ 43, /*->40682*/
+/* 40639*/ OPC_RecordChild1, // #1 = $rs
+/* 40640*/ OPC_CheckChild1Type, MVT::i32,
+/* 40642*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->40669
+/* 40645*/ OPC_Scope, 10, /*->40657*/ // 2 children in Scope
+/* 40647*/ OPC_CheckPatternPredicate, 53, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 40649*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ROTRV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 40657*/ /*Scope*/ 10, /*->40668*/
+/* 40658*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 40660*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ROTRV_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 40668*/ 0, /*End of Scope*/
+/* 40669*/ /*SwitchType*/ 10, MVT::i64,// ->40681
+/* 40671*/ OPC_CheckPatternPredicate, 54, // (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 40673*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DROTRV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+/* 40681*/ 0, // EndSwitchType
+/* 40682*/ 0, /*End of Scope*/
+/* 40683*/ /*SwitchOpcode*/ 78, TARGET_VAL(MipsISD::Sync),// ->40764
+/* 40686*/ OPC_RecordNode, // #0 = 'MipsSync' chained node
+/* 40687*/ OPC_Scope, 19, /*->40708*/ // 3 children in Scope
+/* 40689*/ OPC_RecordChild1, // #1 = $stype
+/* 40690*/ OPC_MoveChild1,
+/* 40691*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40694*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 40696*/ OPC_MoveParent,
+/* 40697*/ OPC_CheckPatternPredicate, 64, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 40699*/ OPC_EmitMergeInputChains1_0,
+/* 40700*/ OPC_EmitConvertToTarget, 1,
+/* 40702*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SYNC), 0|OPFL_Chain,
+ 1/*#Ops*/, 2,
+ // Src: (MipsSync (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$stype) - Complexity = 7
+ // Dst: (SYNC (imm:{ *:[i32] }):$stype)
+/* 40708*/ /*Scope*/ 19, /*->40728*/
+/* 40709*/ OPC_MoveChild1,
+/* 40710*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40713*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 40715*/ OPC_MoveParent,
+/* 40716*/ OPC_CheckPatternPredicate, 65, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding())
+/* 40718*/ OPC_EmitMergeInputChains1_0,
+/* 40719*/ OPC_EmitInteger, MVT::i32, 0,
+/* 40722*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SYNC), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (MipsSync (imm:{ *:[i32] })<<P:Predicate_immz>>) - Complexity = 7
+ // Dst: (SYNC 0:{ *:[i32] })
+/* 40728*/ /*Scope*/ 34, /*->40763*/
+/* 40729*/ OPC_RecordChild1, // #1 = $stype
+/* 40730*/ OPC_MoveChild1,
+/* 40731*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40734*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 40736*/ OPC_MoveParent,
+/* 40737*/ OPC_Scope, 11, /*->40750*/ // 2 children in Scope
+/* 40739*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 40741*/ OPC_EmitMergeInputChains1_0,
+/* 40742*/ OPC_EmitConvertToTarget, 1,
+/* 40744*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SYNC_MM), 0|OPFL_Chain,
+ 1/*#Ops*/, 2,
+ // Src: (MipsSync (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$stype) - Complexity = 7
+ // Dst: (SYNC_MM (imm:{ *:[i32] }):$stype)
+/* 40750*/ /*Scope*/ 11, /*->40762*/
+/* 40751*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 40753*/ OPC_EmitMergeInputChains1_0,
+/* 40754*/ OPC_EmitConvertToTarget, 1,
+/* 40756*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::SYNC_MMR6), 0|OPFL_Chain,
+ 1/*#Ops*/, 2,
+ // Src: (MipsSync (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$stype) - Complexity = 7
+ // Dst: (SYNC_MMR6 (imm:{ *:[i32] }):$stype)
+/* 40762*/ 0, /*End of Scope*/
+/* 40763*/ 0, /*End of Scope*/
+/* 40764*/ /*SwitchOpcode*/ 82, TARGET_VAL(ISD::ADDC),// ->40849
+/* 40767*/ OPC_RecordChild0, // #0 = $src
+/* 40768*/ OPC_RecordChild1, // #1 = $imm
+/* 40769*/ OPC_Scope, 37, /*->40808*/ // 3 children in Scope
+/* 40771*/ OPC_MoveChild1,
+/* 40772*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40775*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 40777*/ OPC_MoveParent,
+/* 40778*/ OPC_SwitchType /*2 cases */, 12, MVT::i32,// ->40793
+/* 40781*/ OPC_CheckPatternPredicate, 66, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())
+/* 40783*/ OPC_EmitConvertToTarget, 1,
+/* 40785*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (addc:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm) - Complexity = 7
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
+/* 40793*/ /*SwitchType*/ 12, MVT::i64,// ->40807
+/* 40795*/ OPC_CheckPatternPredicate, 67, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())
+/* 40797*/ OPC_EmitConvertToTarget, 1,
+/* 40799*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0|OPFL_GlueOutput,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (addc:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$imm) - Complexity = 7
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, (imm:{ *:[i64] }):$imm)
+/* 40807*/ 0, // EndSwitchType
+/* 40808*/ /*Scope*/ 26, /*->40835*/
+/* 40809*/ OPC_CheckType, MVT::i32,
+/* 40811*/ OPC_Scope, 10, /*->40823*/ // 2 children in Scope
+/* 40813*/ OPC_CheckPatternPredicate, 66, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())
+/* 40815*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDu), 0|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (addc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) - Complexity = 3
+ // Dst: (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+/* 40823*/ /*Scope*/ 10, /*->40834*/
+/* 40824*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 40826*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDSC), 0|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (addc:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) - Complexity = 3
+ // Dst: (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
+/* 40834*/ 0, /*End of Scope*/
+/* 40835*/ /*Scope*/ 12, /*->40848*/
+/* 40836*/ OPC_CheckType, MVT::i64,
+/* 40838*/ OPC_CheckPatternPredicate, 67, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())
+/* 40840*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDu), 0|OPFL_GlueOutput,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (addc:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs) - Complexity = 3
+ // Dst: (DADDu:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs)
+/* 40848*/ 0, /*End of Scope*/
+/* 40849*/ /*SwitchOpcode*/ 76, TARGET_VAL(ISD::TRUNCATE),// ->40928
+/* 40852*/ OPC_Scope, 45, /*->40899*/ // 2 children in Scope
+/* 40854*/ OPC_MoveChild0,
+/* 40855*/ OPC_SwitchOpcode /*2 cases */, 19, TARGET_VAL(ISD::AssertZext),// ->40878
+/* 40859*/ OPC_RecordChild0, // #0 = $src
+/* 40860*/ OPC_CheckPredicate, 55, // Predicate_assertzext_lt_i32
+/* 40862*/ OPC_MoveParent,
+/* 40863*/ OPC_CheckType, MVT::i32,
+/* 40865*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 40867*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 40870*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (trunc:{ *:[i32] } (assertzext:{ *:[i64] } GPR64:{ *:[i64] }:$src)<<P:Predicate_assertzext_lt_i32>>) - Complexity = 7
+ // Dst: (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] })
+/* 40878*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::AssertSext),// ->40898
+/* 40881*/ OPC_RecordChild0, // #0 = $src
+/* 40882*/ OPC_MoveParent,
+/* 40883*/ OPC_CheckType, MVT::i32,
+/* 40885*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 40887*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 40890*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (trunc:{ *:[i32] } (assertsext:{ *:[i64] } GPR64:{ *:[i64] }:$src)) - Complexity = 6
+ // Dst: (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] })
+/* 40898*/ 0, // EndSwitchOpcode
+/* 40899*/ /*Scope*/ 27, /*->40927*/
+/* 40900*/ OPC_RecordChild0, // #0 = $src
+/* 40901*/ OPC_CheckType, MVT::i32,
+/* 40903*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 40905*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 40908*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 40916*/ OPC_EmitInteger, MVT::i32, 0,
+/* 40919*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) - Complexity = 3
+ // Dst: (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
+/* 40927*/ 0, /*End of Scope*/
+/* 40928*/ /*SwitchOpcode*/ 66, TARGET_VAL(MipsISD::SHILO),// ->40997
+/* 40931*/ OPC_RecordChild0, // #0 = $shift
+/* 40932*/ OPC_Scope, 36, /*->40970*/ // 2 children in Scope
+/* 40934*/ OPC_MoveChild0,
+/* 40935*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 40938*/ OPC_CheckPredicate, 56, // Predicate_immSExt6
+/* 40940*/ OPC_MoveParent,
+/* 40941*/ OPC_RecordChild1, // #1 = $acin
+/* 40942*/ OPC_Scope, 12, /*->40956*/ // 2 children in Scope
+/* 40944*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 40946*/ OPC_EmitConvertToTarget, 0,
+/* 40948*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHILO), 0,
+ MVT::Untyped, 2/*#Ops*/, 2, 1,
+ // Src: (MipsSHILO:{ *:[Untyped] } (imm:{ *:[i32] })<<P:Predicate_immSExt6>>:$shift, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 7
+ // Dst: (SHILO:{ *:[Untyped] } (imm:{ *:[i32] }):$shift, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 40956*/ /*Scope*/ 12, /*->40969*/
+/* 40957*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 40959*/ OPC_EmitConvertToTarget, 0,
+/* 40961*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHILO_MM), 0,
+ MVT::Untyped, 2/*#Ops*/, 2, 1,
+ // Src: (MipsSHILO:{ *:[Untyped] } (imm:{ *:[i32] })<<P:Predicate_immSExt6>>:$shift, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 7
+ // Dst: (SHILO_MM:{ *:[Untyped] } (imm:{ *:[i32] }):$shift, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 40969*/ 0, /*End of Scope*/
+/* 40970*/ /*Scope*/ 25, /*->40996*/
+/* 40971*/ OPC_RecordChild1, // #1 = $acin
+/* 40972*/ OPC_Scope, 10, /*->40984*/ // 2 children in Scope
+/* 40974*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 40976*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHILOV), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsSHILO:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (SHILOV:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 40984*/ /*Scope*/ 10, /*->40995*/
+/* 40985*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 40987*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHILOV_MM), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsSHILO:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (SHILOV_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 40995*/ 0, /*End of Scope*/
+/* 40996*/ 0, /*End of Scope*/
+/* 40997*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTP),// ->41039
+/* 41000*/ OPC_RecordNode, // #0 = 'MipsEXTP' chained node
+/* 41001*/ OPC_RecordChild1, // #1 = $shift
+/* 41002*/ OPC_Scope, 21, /*->41025*/ // 2 children in Scope
+/* 41004*/ OPC_MoveChild1,
+/* 41005*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41008*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 41010*/ OPC_MoveParent,
+/* 41011*/ OPC_RecordChild2, // #2 = $ac
+/* 41012*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41014*/ OPC_EmitMergeInputChains1_0,
+/* 41015*/ OPC_EmitConvertToTarget, 1,
+/* 41017*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTP), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (MipsEXTP:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 7
+ // Dst: (EXTP:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift)
+/* 41025*/ /*Scope*/ 12, /*->41038*/
+/* 41026*/ OPC_RecordChild2, // #2 = $ac
+/* 41027*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41029*/ OPC_EmitMergeInputChains1_0,
+/* 41030*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTPV), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 1,
+ // Src: (MipsEXTP:{ *:[i32] } GPR32:{ *:[i32] }:$rs, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (EXTPV:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, GPR32:{ *:[i32] }:$rs)
+/* 41038*/ 0, /*End of Scope*/
+/* 41039*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTPDP),// ->41081
+/* 41042*/ OPC_RecordNode, // #0 = 'MipsEXTPDP' chained node
+/* 41043*/ OPC_RecordChild1, // #1 = $shift
+/* 41044*/ OPC_Scope, 21, /*->41067*/ // 2 children in Scope
+/* 41046*/ OPC_MoveChild1,
+/* 41047*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41050*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 41052*/ OPC_MoveParent,
+/* 41053*/ OPC_RecordChild2, // #2 = $ac
+/* 41054*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41056*/ OPC_EmitMergeInputChains1_0,
+/* 41057*/ OPC_EmitConvertToTarget, 1,
+/* 41059*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTPDP), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (MipsEXTPDP:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 7
+ // Dst: (EXTPDP:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift)
+/* 41067*/ /*Scope*/ 12, /*->41080*/
+/* 41068*/ OPC_RecordChild2, // #2 = $ac
+/* 41069*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41071*/ OPC_EmitMergeInputChains1_0,
+/* 41072*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTPDPV), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 1,
+ // Src: (MipsEXTPDP:{ *:[i32] } GPR32:{ *:[i32] }:$rs, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (EXTPDPV:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, GPR32:{ *:[i32] }:$rs)
+/* 41080*/ 0, /*End of Scope*/
+/* 41081*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTR_W),// ->41123
+/* 41084*/ OPC_RecordNode, // #0 = 'MipsEXTR_W' chained node
+/* 41085*/ OPC_RecordChild1, // #1 = $shift
+/* 41086*/ OPC_Scope, 21, /*->41109*/ // 2 children in Scope
+/* 41088*/ OPC_MoveChild1,
+/* 41089*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41092*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 41094*/ OPC_MoveParent,
+/* 41095*/ OPC_RecordChild2, // #2 = $ac
+/* 41096*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41098*/ OPC_EmitMergeInputChains1_0,
+/* 41099*/ OPC_EmitConvertToTarget, 1,
+/* 41101*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTR_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (MipsEXTR_W:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 7
+ // Dst: (EXTR_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift)
+/* 41109*/ /*Scope*/ 12, /*->41122*/
+/* 41110*/ OPC_RecordChild2, // #2 = $ac
+/* 41111*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41113*/ OPC_EmitMergeInputChains1_0,
+/* 41114*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTRV_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 1,
+ // Src: (MipsEXTR_W:{ *:[i32] } GPR32:{ *:[i32] }:$rs, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (EXTRV_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, GPR32:{ *:[i32] }:$rs)
+/* 41122*/ 0, /*End of Scope*/
+/* 41123*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTR_R_W),// ->41165
+/* 41126*/ OPC_RecordNode, // #0 = 'MipsEXTR_R_W' chained node
+/* 41127*/ OPC_RecordChild1, // #1 = $shift
+/* 41128*/ OPC_Scope, 21, /*->41151*/ // 2 children in Scope
+/* 41130*/ OPC_MoveChild1,
+/* 41131*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41134*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 41136*/ OPC_MoveParent,
+/* 41137*/ OPC_RecordChild2, // #2 = $ac
+/* 41138*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41140*/ OPC_EmitMergeInputChains1_0,
+/* 41141*/ OPC_EmitConvertToTarget, 1,
+/* 41143*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTR_R_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (MipsEXTR_R_W:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 7
+ // Dst: (EXTR_R_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift)
+/* 41151*/ /*Scope*/ 12, /*->41164*/
+/* 41152*/ OPC_RecordChild2, // #2 = $ac
+/* 41153*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41155*/ OPC_EmitMergeInputChains1_0,
+/* 41156*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTRV_R_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 1,
+ // Src: (MipsEXTR_R_W:{ *:[i32] } GPR32:{ *:[i32] }:$rs, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (EXTRV_R_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, GPR32:{ *:[i32] }:$rs)
+/* 41164*/ 0, /*End of Scope*/
+/* 41165*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTR_RS_W),// ->41207
+/* 41168*/ OPC_RecordNode, // #0 = 'MipsEXTR_RS_W' chained node
+/* 41169*/ OPC_RecordChild1, // #1 = $shift
+/* 41170*/ OPC_Scope, 21, /*->41193*/ // 2 children in Scope
+/* 41172*/ OPC_MoveChild1,
+/* 41173*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41176*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 41178*/ OPC_MoveParent,
+/* 41179*/ OPC_RecordChild2, // #2 = $ac
+/* 41180*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41182*/ OPC_EmitMergeInputChains1_0,
+/* 41183*/ OPC_EmitConvertToTarget, 1,
+/* 41185*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTR_RS_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (MipsEXTR_RS_W:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 7
+ // Dst: (EXTR_RS_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift)
+/* 41193*/ /*Scope*/ 12, /*->41206*/
+/* 41194*/ OPC_RecordChild2, // #2 = $ac
+/* 41195*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41197*/ OPC_EmitMergeInputChains1_0,
+/* 41198*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTRV_RS_W), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 1,
+ // Src: (MipsEXTR_RS_W:{ *:[i32] } GPR32:{ *:[i32] }:$rs, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (EXTRV_RS_W:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, GPR32:{ *:[i32] }:$rs)
+/* 41206*/ 0, /*End of Scope*/
+/* 41207*/ /*SwitchOpcode*/ 39, TARGET_VAL(MipsISD::EXTR_S_H),// ->41249
+/* 41210*/ OPC_RecordNode, // #0 = 'MipsEXTR_S_H' chained node
+/* 41211*/ OPC_RecordChild1, // #1 = $shift
+/* 41212*/ OPC_Scope, 21, /*->41235*/ // 2 children in Scope
+/* 41214*/ OPC_MoveChild1,
+/* 41215*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41218*/ OPC_CheckPredicate, 28, // Predicate_immZExt5
+/* 41220*/ OPC_MoveParent,
+/* 41221*/ OPC_RecordChild2, // #2 = $ac
+/* 41222*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41224*/ OPC_EmitMergeInputChains1_0,
+/* 41225*/ OPC_EmitConvertToTarget, 1,
+/* 41227*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTR_S_H), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (MipsEXTR_S_H:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 7
+ // Dst: (EXTR_S_H:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shift)
+/* 41235*/ /*Scope*/ 12, /*->41248*/
+/* 41236*/ OPC_RecordChild2, // #2 = $ac
+/* 41237*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 41239*/ OPC_EmitMergeInputChains1_0,
+/* 41240*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::EXTRV_S_H), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 2, 1,
+ // Src: (MipsEXTR_S_H:{ *:[i32] } GPR32:{ *:[i32] }:$rs, ACC64DSP:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (EXTRV_S_H:{ *:[i32] } ACC64DSP:{ *:[Untyped] }:$ac, GPR32:{ *:[i32] }:$rs)
+/* 41248*/ 0, /*End of Scope*/
+/* 41249*/ /*SwitchOpcode*/ 83|128,4/*595*/, TARGET_VAL(MipsISD::VEXTRACT_SEXT_ELT),// ->41848
+/* 41253*/ OPC_RecordChild0, // #0 = $ws
+/* 41254*/ OPC_Scope, 29|128,1/*157*/, /*->41414*/ // 4 children in Scope
+/* 41257*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 41259*/ OPC_RecordChild1, // #1 = $n
+/* 41260*/ OPC_Scope, 25, /*->41287*/ // 3 children in Scope
+/* 41262*/ OPC_MoveChild1,
+/* 41263*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41266*/ OPC_CheckPredicate, 31, // Predicate_immZExt4Ptr
+/* 41268*/ OPC_MoveParent,
+/* 41269*/ OPC_MoveChild2,
+/* 41270*/ OPC_CheckValueType, MVT::i8,
+/* 41272*/ OPC_MoveParent,
+/* 41273*/ OPC_CheckType, MVT::i32,
+/* 41275*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 41277*/ OPC_EmitConvertToTarget, 1,
+/* 41279*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_B), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractSExt:{ *:[i32] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt4Ptr>>:$n, i8:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_S_B:{ *:[i32] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 41287*/ /*Scope*/ 51, /*->41339*/
+/* 41288*/ OPC_CheckChild1Type, MVT::i32,
+/* 41290*/ OPC_MoveChild2,
+/* 41291*/ OPC_CheckValueType, MVT::i8,
+/* 41293*/ OPC_MoveParent,
+/* 41294*/ OPC_CheckType, MVT::i32,
+/* 41296*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 41298*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 41306*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 41309*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 41317*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41320*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 41328*/ OPC_EmitInteger, MVT::i32, 24,
+/* 41331*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7,
+ // Src: (MipsVExtractSExt:{ *:[i32] } v16i8:{ *:[v16i8] }:$ws, i32:{ *:[i32] }:$idx, i8:{ *:[Other] }) - Complexity = 3
+ // Dst: (SRA:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, i32:{ *:[i32] }:$idx), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] }), 24:{ *:[i32] })
+/* 41339*/ /*Scope*/ 73, /*->41413*/
+/* 41340*/ OPC_CheckChild1Type, MVT::i64,
+/* 41342*/ OPC_MoveChild2,
+/* 41343*/ OPC_CheckValueType, MVT::i8,
+/* 41345*/ OPC_MoveParent,
+/* 41346*/ OPC_CheckType, MVT::i32,
+/* 41348*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 41350*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 41353*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 41361*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41364*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 41372*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 5, // Results = #6
+/* 41380*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 41383*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 41391*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41394*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 8, 9, // Results = #10
+/* 41402*/ OPC_EmitInteger, MVT::i32, 24,
+/* 41405*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 10, 11,
+ // Src: (MipsVExtractSExt:{ *:[i32] } v16i8:{ *:[v16i8] }:$ws, i64:{ *:[i64] }:$idx, i8:{ *:[Other] }) - Complexity = 3
+ // Dst: (SRA:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] }), 24:{ *:[i32] })
+/* 41413*/ 0, /*End of Scope*/
+/* 41414*/ /*Scope*/ 29|128,1/*157*/, /*->41573*/
+/* 41416*/ OPC_CheckChild0Type, MVT::v8i16,
+/* 41418*/ OPC_RecordChild1, // #1 = $n
+/* 41419*/ OPC_Scope, 25, /*->41446*/ // 3 children in Scope
+/* 41421*/ OPC_MoveChild1,
+/* 41422*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41425*/ OPC_CheckPredicate, 32, // Predicate_immZExt3Ptr
+/* 41427*/ OPC_MoveParent,
+/* 41428*/ OPC_MoveChild2,
+/* 41429*/ OPC_CheckValueType, MVT::i16,
+/* 41431*/ OPC_MoveParent,
+/* 41432*/ OPC_CheckType, MVT::i32,
+/* 41434*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 41436*/ OPC_EmitConvertToTarget, 1,
+/* 41438*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_H), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractSExt:{ *:[i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt3Ptr>>:$n, i16:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_S_H:{ *:[i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 41446*/ /*Scope*/ 51, /*->41498*/
+/* 41447*/ OPC_CheckChild1Type, MVT::i32,
+/* 41449*/ OPC_MoveChild2,
+/* 41450*/ OPC_CheckValueType, MVT::i16,
+/* 41452*/ OPC_MoveParent,
+/* 41453*/ OPC_CheckType, MVT::i32,
+/* 41455*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 41457*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 41465*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 41468*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 41476*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41479*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 41487*/ OPC_EmitInteger, MVT::i32, 16,
+/* 41490*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7,
+ // Src: (MipsVExtractSExt:{ *:[i32] } v8i16:{ *:[v8i16] }:$ws, i32:{ *:[i32] }:$idx, i16:{ *:[Other] }) - Complexity = 3
+ // Dst: (SRA:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, i32:{ *:[i32] }:$idx), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] }), 16:{ *:[i32] })
+/* 41498*/ /*Scope*/ 73, /*->41572*/
+/* 41499*/ OPC_CheckChild1Type, MVT::i64,
+/* 41501*/ OPC_MoveChild2,
+/* 41502*/ OPC_CheckValueType, MVT::i16,
+/* 41504*/ OPC_MoveParent,
+/* 41505*/ OPC_CheckType, MVT::i32,
+/* 41507*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 41509*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 41512*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 41520*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41523*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 41531*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 5, // Results = #6
+/* 41539*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 41542*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 41550*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41553*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 8, 9, // Results = #10
+/* 41561*/ OPC_EmitInteger, MVT::i32, 16,
+/* 41564*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 10, 11,
+ // Src: (MipsVExtractSExt:{ *:[i32] } v8i16:{ *:[v8i16] }:$ws, i64:{ *:[i64] }:$idx, i16:{ *:[Other] }) - Complexity = 3
+ // Dst: (SRA:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] }), 16:{ *:[i32] })
+/* 41572*/ 0, /*End of Scope*/
+/* 41573*/ /*Scope*/ 7|128,1/*135*/, /*->41710*/
+/* 41575*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 41577*/ OPC_RecordChild1, // #1 = $n
+/* 41578*/ OPC_Scope, 25, /*->41605*/ // 3 children in Scope
+/* 41580*/ OPC_MoveChild1,
+/* 41581*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41584*/ OPC_CheckPredicate, 33, // Predicate_immZExt2Ptr
+/* 41586*/ OPC_MoveParent,
+/* 41587*/ OPC_MoveChild2,
+/* 41588*/ OPC_CheckValueType, MVT::i32,
+/* 41590*/ OPC_MoveParent,
+/* 41591*/ OPC_CheckType, MVT::i32,
+/* 41593*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 41595*/ OPC_EmitConvertToTarget, 1,
+/* 41597*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractSExt:{ *:[i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt2Ptr>>:$n, i32:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_S_W:{ *:[i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 41605*/ /*Scope*/ 40, /*->41646*/
+/* 41606*/ OPC_CheckChild1Type, MVT::i32,
+/* 41608*/ OPC_MoveChild2,
+/* 41609*/ OPC_CheckValueType, MVT::i32,
+/* 41611*/ OPC_MoveParent,
+/* 41612*/ OPC_CheckType, MVT::i32,
+/* 41614*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 41616*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 41624*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 41627*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 41635*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41638*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5,
+ // Src: (MipsVExtractSExt:{ *:[i32] } v4i32:{ *:[v4i32] }:$ws, i32:{ *:[i32] }:$idx, i32:{ *:[Other] }) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, i32:{ *:[i32] }:$idx), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] })
+/* 41646*/ /*Scope*/ 62, /*->41709*/
+/* 41647*/ OPC_CheckChild1Type, MVT::i64,
+/* 41649*/ OPC_MoveChild2,
+/* 41650*/ OPC_CheckValueType, MVT::i32,
+/* 41652*/ OPC_MoveParent,
+/* 41653*/ OPC_CheckType, MVT::i32,
+/* 41655*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 41657*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 41660*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 41668*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41671*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 41679*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 41687*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 41690*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 41698*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41701*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 8, 9,
+ // Src: (MipsVExtractSExt:{ *:[i32] } v4i32:{ *:[v4i32] }:$ws, i64:{ *:[i64] }:$idx, i32:{ *:[Other] }) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] })
+/* 41709*/ 0, /*End of Scope*/
+/* 41710*/ /*Scope*/ 7|128,1/*135*/, /*->41847*/
+/* 41712*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 41714*/ OPC_RecordChild1, // #1 = $n
+/* 41715*/ OPC_Scope, 25, /*->41742*/ // 3 children in Scope
+/* 41717*/ OPC_MoveChild1,
+/* 41718*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41721*/ OPC_CheckPredicate, 37, // Predicate_immZExt1Ptr
+/* 41723*/ OPC_MoveParent,
+/* 41724*/ OPC_MoveChild2,
+/* 41725*/ OPC_CheckValueType, MVT::i64,
+/* 41727*/ OPC_MoveParent,
+/* 41728*/ OPC_CheckType, MVT::i64,
+/* 41730*/ OPC_CheckPatternPredicate, 58, // (Subtarget->hasMSA()) && (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding())
+/* 41732*/ OPC_EmitConvertToTarget, 1,
+/* 41734*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractSExt:{ *:[i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt1Ptr>>:$n, i64:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_S_D:{ *:[i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 41742*/ /*Scope*/ 40, /*->41783*/
+/* 41743*/ OPC_CheckChild1Type, MVT::i32,
+/* 41745*/ OPC_MoveChild2,
+/* 41746*/ OPC_CheckValueType, MVT::i64,
+/* 41748*/ OPC_MoveParent,
+/* 41749*/ OPC_CheckType, MVT::i64,
+/* 41751*/ OPC_CheckPatternPredicate, 68, // (Subtarget->hasMSA()) && (Subtarget->isGP64bit())
+/* 41753*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1, // Results = #2
+/* 41761*/ OPC_EmitInteger, MVT::i32, Mips::sub_64,
+/* 41764*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3, // Results = #4
+/* 41772*/ OPC_EmitInteger, MVT::i32, Mips::GPR64RegClassID,
+/* 41775*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i64, 2/*#Ops*/, 4, 5,
+ // Src: (MipsVExtractSExt:{ *:[i64] } v2i64:{ *:[v2i64] }:$ws, i32:{ *:[i32] }:$idx, i64:{ *:[Other] }) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i64] } (SPLAT_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, i32:{ *:[i32] }:$idx), sub_64:{ *:[i32] }), GPR64:{ *:[i32] })
+/* 41783*/ /*Scope*/ 62, /*->41846*/
+/* 41784*/ OPC_CheckChild1Type, MVT::i64,
+/* 41786*/ OPC_MoveChild2,
+/* 41787*/ OPC_CheckValueType, MVT::i64,
+/* 41789*/ OPC_MoveParent,
+/* 41790*/ OPC_CheckType, MVT::i64,
+/* 41792*/ OPC_CheckPatternPredicate, 68, // (Subtarget->hasMSA()) && (Subtarget->isGP64bit())
+/* 41794*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 41797*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 41805*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41808*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 41816*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 5, // Results = #6
+/* 41824*/ OPC_EmitInteger, MVT::i32, Mips::sub_64,
+/* 41827*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i64, 2/*#Ops*/, 6, 7, // Results = #8
+/* 41835*/ OPC_EmitInteger, MVT::i32, Mips::GPR64RegClassID,
+/* 41838*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i64, 2/*#Ops*/, 8, 9,
+ // Src: (MipsVExtractSExt:{ *:[i64] } v2i64:{ *:[v2i64] }:$ws, i64:{ *:[i64] }:$idx, i64:{ *:[Other] }) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i64] } (SPLAT_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_64:{ *:[i32] }), GPR64:{ *:[i32] })
+/* 41846*/ 0, /*End of Scope*/
+/* 41847*/ 0, /*End of Scope*/
+/* 41848*/ /*SwitchOpcode*/ 29|128,5/*669*/, TARGET_VAL(MipsISD::VEXTRACT_ZEXT_ELT),// ->42521
+/* 41852*/ OPC_RecordChild0, // #0 = $ws
+/* 41853*/ OPC_Scope, 29|128,1/*157*/, /*->42013*/ // 6 children in Scope
+/* 41856*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 41858*/ OPC_RecordChild1, // #1 = $n
+/* 41859*/ OPC_Scope, 25, /*->41886*/ // 3 children in Scope
+/* 41861*/ OPC_MoveChild1,
+/* 41862*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 41865*/ OPC_CheckPredicate, 31, // Predicate_immZExt4Ptr
+/* 41867*/ OPC_MoveParent,
+/* 41868*/ OPC_MoveChild2,
+/* 41869*/ OPC_CheckValueType, MVT::i8,
+/* 41871*/ OPC_MoveParent,
+/* 41872*/ OPC_CheckType, MVT::i32,
+/* 41874*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 41876*/ OPC_EmitConvertToTarget, 1,
+/* 41878*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_U_B), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractZExt:{ *:[i32] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt4Ptr>>:$n, i8:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_U_B:{ *:[i32] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 41886*/ /*Scope*/ 51, /*->41938*/
+/* 41887*/ OPC_CheckChild1Type, MVT::i32,
+/* 41889*/ OPC_MoveChild2,
+/* 41890*/ OPC_CheckValueType, MVT::i8,
+/* 41892*/ OPC_MoveParent,
+/* 41893*/ OPC_CheckType, MVT::i32,
+/* 41895*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 41897*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 41905*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 41908*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 41916*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41919*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 41927*/ OPC_EmitInteger, MVT::i32, 24,
+/* 41930*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7,
+ // Src: (MipsVExtractZExt:{ *:[i32] } v16i8:{ *:[v16i8] }:$ws, i32:{ *:[i32] }:$idx, i8:{ *:[Other] }) - Complexity = 3
+ // Dst: (SRL:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, i32:{ *:[i32] }:$idx), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] }), 24:{ *:[i32] })
+/* 41938*/ /*Scope*/ 73, /*->42012*/
+/* 41939*/ OPC_CheckChild1Type, MVT::i64,
+/* 41941*/ OPC_MoveChild2,
+/* 41942*/ OPC_CheckValueType, MVT::i8,
+/* 41944*/ OPC_MoveParent,
+/* 41945*/ OPC_CheckType, MVT::i32,
+/* 41947*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 41949*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 41952*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 41960*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41963*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 41971*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 5, // Results = #6
+/* 41979*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 41982*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 41990*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 41993*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 8, 9, // Results = #10
+/* 42001*/ OPC_EmitInteger, MVT::i32, 24,
+/* 42004*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 10, 11,
+ // Src: (MipsVExtractZExt:{ *:[i32] } v16i8:{ *:[v16i8] }:$ws, i64:{ *:[i64] }:$idx, i8:{ *:[Other] }) - Complexity = 3
+ // Dst: (SRL:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] }), 24:{ *:[i32] })
+/* 42012*/ 0, /*End of Scope*/
+/* 42013*/ /*Scope*/ 29|128,1/*157*/, /*->42172*/
+/* 42015*/ OPC_CheckChild0Type, MVT::v8i16,
+/* 42017*/ OPC_RecordChild1, // #1 = $n
+/* 42018*/ OPC_Scope, 25, /*->42045*/ // 3 children in Scope
+/* 42020*/ OPC_MoveChild1,
+/* 42021*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 42024*/ OPC_CheckPredicate, 32, // Predicate_immZExt3Ptr
+/* 42026*/ OPC_MoveParent,
+/* 42027*/ OPC_MoveChild2,
+/* 42028*/ OPC_CheckValueType, MVT::i16,
+/* 42030*/ OPC_MoveParent,
+/* 42031*/ OPC_CheckType, MVT::i32,
+/* 42033*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 42035*/ OPC_EmitConvertToTarget, 1,
+/* 42037*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_U_H), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractZExt:{ *:[i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt3Ptr>>:$n, i16:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_U_H:{ *:[i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 42045*/ /*Scope*/ 51, /*->42097*/
+/* 42046*/ OPC_CheckChild1Type, MVT::i32,
+/* 42048*/ OPC_MoveChild2,
+/* 42049*/ OPC_CheckValueType, MVT::i16,
+/* 42051*/ OPC_MoveParent,
+/* 42052*/ OPC_CheckType, MVT::i32,
+/* 42054*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42056*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 42064*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 42067*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 42075*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42078*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 42086*/ OPC_EmitInteger, MVT::i32, 16,
+/* 42089*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7,
+ // Src: (MipsVExtractZExt:{ *:[i32] } v8i16:{ *:[v8i16] }:$ws, i32:{ *:[i32] }:$idx, i16:{ *:[Other] }) - Complexity = 3
+ // Dst: (SRL:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, i32:{ *:[i32] }:$idx), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] }), 16:{ *:[i32] })
+/* 42097*/ /*Scope*/ 73, /*->42171*/
+/* 42098*/ OPC_CheckChild1Type, MVT::i64,
+/* 42100*/ OPC_MoveChild2,
+/* 42101*/ OPC_CheckValueType, MVT::i16,
+/* 42103*/ OPC_MoveParent,
+/* 42104*/ OPC_CheckType, MVT::i32,
+/* 42106*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42108*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 42111*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 42119*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42122*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 42130*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 5, // Results = #6
+/* 42138*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 42141*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 42149*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42152*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 8, 9, // Results = #10
+/* 42160*/ OPC_EmitInteger, MVT::i32, 16,
+/* 42163*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 10, 11,
+ // Src: (MipsVExtractZExt:{ *:[i32] } v8i16:{ *:[v8i16] }:$ws, i64:{ *:[i64] }:$idx, i16:{ *:[Other] }) - Complexity = 3
+ // Dst: (SRL:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] }), 16:{ *:[i32] })
+/* 42171*/ 0, /*End of Scope*/
+/* 42172*/ /*Scope*/ 23|128,1/*151*/, /*->42325*/
+/* 42174*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 42176*/ OPC_RecordChild1, // #1 = $n
+/* 42177*/ OPC_Scope, 41, /*->42220*/ // 3 children in Scope
+/* 42179*/ OPC_MoveChild1,
+/* 42180*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 42183*/ OPC_CheckPredicate, 33, // Predicate_immZExt2Ptr
+/* 42185*/ OPC_MoveParent,
+/* 42186*/ OPC_MoveChild2,
+/* 42187*/ OPC_CheckValueType, MVT::i32,
+/* 42189*/ OPC_MoveParent,
+/* 42190*/ OPC_CheckType, MVT::i32,
+/* 42192*/ OPC_Scope, 12, /*->42206*/ // 2 children in Scope
+/* 42194*/ OPC_CheckPatternPredicate, 58, // (Subtarget->hasMSA()) && (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding())
+/* 42196*/ OPC_EmitConvertToTarget, 1,
+/* 42198*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_U_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractZExt:{ *:[i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt2Ptr>>:$n, i32:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_U_W:{ *:[i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 42206*/ /*Scope*/ 12, /*->42219*/
+/* 42207*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42209*/ OPC_EmitConvertToTarget, 1,
+/* 42211*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractZExt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt2Ptr>>:$idx, i32:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$idx)
+/* 42219*/ 0, /*End of Scope*/
+/* 42220*/ /*Scope*/ 40, /*->42261*/
+/* 42221*/ OPC_CheckChild1Type, MVT::i32,
+/* 42223*/ OPC_MoveChild2,
+/* 42224*/ OPC_CheckValueType, MVT::i32,
+/* 42226*/ OPC_MoveParent,
+/* 42227*/ OPC_CheckType, MVT::i32,
+/* 42229*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42231*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 42239*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 42242*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 42250*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42253*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5,
+ // Src: (MipsVExtractZExt:{ *:[i32] } v4i32:{ *:[v4i32] }:$ws, i32:{ *:[i32] }:$idx, i32:{ *:[Other] }) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, i32:{ *:[i32] }:$idx), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] })
+/* 42261*/ /*Scope*/ 62, /*->42324*/
+/* 42262*/ OPC_CheckChild1Type, MVT::i64,
+/* 42264*/ OPC_MoveChild2,
+/* 42265*/ OPC_CheckValueType, MVT::i32,
+/* 42267*/ OPC_MoveParent,
+/* 42268*/ OPC_CheckType, MVT::i32,
+/* 42270*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42272*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 42275*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 42283*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42286*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 42294*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 42302*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 42305*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 42313*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42316*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 8, 9,
+ // Src: (MipsVExtractZExt:{ *:[i32] } v4i32:{ *:[v4i32] }:$ws, i64:{ *:[i64] }:$idx, i32:{ *:[Other] }) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_lo:{ *:[i32] }), GPR32:{ *:[i32] })
+/* 42324*/ 0, /*End of Scope*/
+/* 42325*/ /*Scope*/ 28, /*->42354*/
+/* 42326*/ OPC_CheckChild0Type, MVT::v4f32,
+/* 42328*/ OPC_RecordChild1, // #1 = $idx
+/* 42329*/ OPC_MoveChild1,
+/* 42330*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 42333*/ OPC_CheckPredicate, 33, // Predicate_immZExt2Ptr
+/* 42335*/ OPC_MoveParent,
+/* 42336*/ OPC_MoveChild2,
+/* 42337*/ OPC_CheckValueType, MVT::i32,
+/* 42339*/ OPC_MoveParent,
+/* 42340*/ OPC_CheckType, MVT::i32,
+/* 42342*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42344*/ OPC_EmitConvertToTarget, 1,
+/* 42346*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractZExt:{ *:[i32] } MSA128W:{ *:[v4f32] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt2Ptr>>:$idx, i32:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4f32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$idx)
+/* 42354*/ /*Scope*/ 7|128,1/*135*/, /*->42491*/
+/* 42356*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 42358*/ OPC_RecordChild1, // #1 = $idx
+/* 42359*/ OPC_Scope, 25, /*->42386*/ // 3 children in Scope
+/* 42361*/ OPC_MoveChild1,
+/* 42362*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 42365*/ OPC_CheckPredicate, 37, // Predicate_immZExt1Ptr
+/* 42367*/ OPC_MoveParent,
+/* 42368*/ OPC_MoveChild2,
+/* 42369*/ OPC_CheckValueType, MVT::i64,
+/* 42371*/ OPC_MoveParent,
+/* 42372*/ OPC_CheckType, MVT::i64,
+/* 42374*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42376*/ OPC_EmitConvertToTarget, 1,
+/* 42378*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractZExt:{ *:[i64] } MSA128D:{ *:[v2i64] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt1Ptr>>:$idx, i64:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_S_D:{ *:[i64] } MSA128D:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt1>>:$idx)
+/* 42386*/ /*Scope*/ 40, /*->42427*/
+/* 42387*/ OPC_CheckChild1Type, MVT::i32,
+/* 42389*/ OPC_MoveChild2,
+/* 42390*/ OPC_CheckValueType, MVT::i64,
+/* 42392*/ OPC_MoveParent,
+/* 42393*/ OPC_CheckType, MVT::i64,
+/* 42395*/ OPC_CheckPatternPredicate, 68, // (Subtarget->hasMSA()) && (Subtarget->isGP64bit())
+/* 42397*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1, // Results = #2
+/* 42405*/ OPC_EmitInteger, MVT::i32, Mips::sub_64,
+/* 42408*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3, // Results = #4
+/* 42416*/ OPC_EmitInteger, MVT::i32, Mips::GPR64RegClassID,
+/* 42419*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i64, 2/*#Ops*/, 4, 5,
+ // Src: (MipsVExtractZExt:{ *:[i64] } v2i64:{ *:[v2i64] }:$ws, i32:{ *:[i32] }:$idx, i64:{ *:[Other] }) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i64] } (SPLAT_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, i32:{ *:[i32] }:$idx), sub_64:{ *:[i32] }), GPR64:{ *:[i32] })
+/* 42427*/ /*Scope*/ 62, /*->42490*/
+/* 42428*/ OPC_CheckChild1Type, MVT::i64,
+/* 42430*/ OPC_MoveChild2,
+/* 42431*/ OPC_CheckValueType, MVT::i64,
+/* 42433*/ OPC_MoveParent,
+/* 42434*/ OPC_CheckType, MVT::i64,
+/* 42436*/ OPC_CheckPatternPredicate, 68, // (Subtarget->hasMSA()) && (Subtarget->isGP64bit())
+/* 42438*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 42441*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 42449*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42452*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 42460*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 5, // Results = #6
+/* 42468*/ OPC_EmitInteger, MVT::i32, Mips::sub_64,
+/* 42471*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i64, 2/*#Ops*/, 6, 7, // Results = #8
+/* 42479*/ OPC_EmitInteger, MVT::i32, Mips::GPR64RegClassID,
+/* 42482*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i64, 2/*#Ops*/, 8, 9,
+ // Src: (MipsVExtractZExt:{ *:[i64] } v2i64:{ *:[v2i64] }:$ws, i64:{ *:[i64] }:$idx, i64:{ *:[Other] }) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i64] } (SPLAT_D:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_64:{ *:[i32] }), GPR64:{ *:[i32] })
+/* 42490*/ 0, /*End of Scope*/
+/* 42491*/ /*Scope*/ 28, /*->42520*/
+/* 42492*/ OPC_CheckChild0Type, MVT::v2f64,
+/* 42494*/ OPC_RecordChild1, // #1 = $idx
+/* 42495*/ OPC_MoveChild1,
+/* 42496*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 42499*/ OPC_CheckPredicate, 37, // Predicate_immZExt1Ptr
+/* 42501*/ OPC_MoveParent,
+/* 42502*/ OPC_MoveChild2,
+/* 42503*/ OPC_CheckValueType, MVT::i64,
+/* 42505*/ OPC_MoveParent,
+/* 42506*/ OPC_CheckType, MVT::i64,
+/* 42508*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42510*/ OPC_EmitConvertToTarget, 1,
+/* 42512*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVExtractZExt:{ *:[i64] } MSA128D:{ *:[v2f64] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt1Ptr>>:$idx, i64:{ *:[Other] }) - Complexity = 7
+ // Dst: (COPY_S_D:{ *:[i64] } MSA128D:{ *:[v2f64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt1>>:$idx)
+/* 42520*/ 0, /*End of Scope*/
+/* 42521*/ /*SwitchOpcode*/ 104|128,1/*232*/, TARGET_VAL(ISD::EXTRACT_VECTOR_ELT),// ->42757
+/* 42525*/ OPC_RecordChild0, // #0 = $ws
+/* 42526*/ OPC_Scope, 24, /*->42552*/ // 3 children in Scope
+/* 42528*/ OPC_RecordChild1, // #1 = $idx
+/* 42529*/ OPC_MoveChild1,
+/* 42530*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 42533*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 42535*/ OPC_CheckType, MVT::i32,
+/* 42537*/ OPC_MoveParent,
+/* 42538*/ OPC_CheckType, MVT::i32,
+/* 42540*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42542*/ OPC_EmitConvertToTarget, 1,
+/* 42544*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_S_W), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx) - Complexity = 7
+ // Dst: (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
+/* 42552*/ /*Scope*/ 101, /*->42654*/
+/* 42553*/ OPC_CheckChild0Type, MVT::v4f32,
+/* 42555*/ OPC_RecordChild1, // #1 = $n
+/* 42556*/ OPC_Scope, 21, /*->42579*/ // 3 children in Scope
+/* 42558*/ OPC_MoveChild1,
+/* 42559*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 42562*/ OPC_CheckPredicate, 33, // Predicate_immZExt2Ptr
+/* 42564*/ OPC_MoveParent,
+/* 42565*/ OPC_CheckType, MVT::f32,
+/* 42567*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 42569*/ OPC_EmitConvertToTarget, 1,
+/* 42571*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_FW_PSEUDO), 0,
+ MVT::f32, 2/*#Ops*/, 0, 2,
+ // Src: (vector_extract:{ *:[f32] } MSA128W:{ *:[v4f32] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt2Ptr>>:$n) - Complexity = 7
+ // Dst: (COPY_FW_PSEUDO:{ *:[f32] } MSA128W:{ *:[v4f32] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 42579*/ /*Scope*/ 25, /*->42605*/
+/* 42580*/ OPC_CheckChild1Type, MVT::i32,
+/* 42582*/ OPC_CheckType, MVT::f32,
+/* 42584*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42586*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 42594*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 42597*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::f32, 2/*#Ops*/, 2, 3,
+ // Src: (vector_extract:{ *:[f32] } v4f32:{ *:[v4f32] }:$ws, i32:{ *:[i32] }:$idx) - Complexity = 3
+ // Dst: (EXTRACT_SUBREG:{ *:[f32] } (SPLAT_W:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$ws, i32:{ *:[i32] }:$idx), sub_lo:{ *:[i32] })
+/* 42605*/ /*Scope*/ 47, /*->42653*/
+/* 42606*/ OPC_CheckChild1Type, MVT::i64,
+/* 42608*/ OPC_CheckType, MVT::f32,
+/* 42610*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42612*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 42615*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 42623*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42626*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 42634*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 5, // Results = #6
+/* 42642*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 42645*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::f32, 2/*#Ops*/, 6, 7,
+ // Src: (vector_extract:{ *:[f32] } v4f32:{ *:[v4f32] }:$ws, i64:{ *:[i64] }:$idx) - Complexity = 3
+ // Dst: (EXTRACT_SUBREG:{ *:[f32] } (SPLAT_W:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_lo:{ *:[i32] })
+/* 42653*/ 0, /*End of Scope*/
+/* 42654*/ /*Scope*/ 101, /*->42756*/
+/* 42655*/ OPC_CheckChild0Type, MVT::v2f64,
+/* 42657*/ OPC_RecordChild1, // #1 = $n
+/* 42658*/ OPC_Scope, 21, /*->42681*/ // 3 children in Scope
+/* 42660*/ OPC_MoveChild1,
+/* 42661*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 42664*/ OPC_CheckPredicate, 37, // Predicate_immZExt1Ptr
+/* 42666*/ OPC_MoveParent,
+/* 42667*/ OPC_CheckType, MVT::f64,
+/* 42669*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 42671*/ OPC_EmitConvertToTarget, 1,
+/* 42673*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::COPY_FD_PSEUDO), 0,
+ MVT::f64, 2/*#Ops*/, 0, 2,
+ // Src: (vector_extract:{ *:[f64] } MSA128D:{ *:[v2f64] }:$ws, (imm:{ *:[iPTR] })<<P:Predicate_immZExt1Ptr>>:$n) - Complexity = 7
+ // Dst: (COPY_FD_PSEUDO:{ *:[f64] } MSA128D:{ *:[v2f64] }:$ws, (imm:{ *:[iPTR] }):$n)
+/* 42681*/ /*Scope*/ 25, /*->42707*/
+/* 42682*/ OPC_CheckChild1Type, MVT::i32,
+/* 42684*/ OPC_CheckType, MVT::f64,
+/* 42686*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42688*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1, // Results = #2
+/* 42696*/ OPC_EmitInteger, MVT::i32, Mips::sub_64,
+/* 42699*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (vector_extract:{ *:[f64] } v2f64:{ *:[v2f64] }:$ws, i32:{ *:[i32] }:$idx) - Complexity = 3
+ // Dst: (EXTRACT_SUBREG:{ *:[f64] } (SPLAT_D:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$ws, i32:{ *:[i32] }:$idx), sub_64:{ *:[i32] })
+/* 42707*/ /*Scope*/ 47, /*->42755*/
+/* 42708*/ OPC_CheckChild1Type, MVT::i64,
+/* 42710*/ OPC_CheckType, MVT::f64,
+/* 42712*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 42714*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 42717*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 42725*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 42728*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 42736*/ OPC_EmitNode1, TARGET_VAL(Mips::SPLAT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 5, // Results = #6
+/* 42744*/ OPC_EmitInteger, MVT::i32, Mips::sub_64,
+/* 42747*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::f64, 2/*#Ops*/, 6, 7,
+ // Src: (vector_extract:{ *:[f64] } v2f64:{ *:[v2f64] }:$ws, i64:{ *:[i64] }:$idx) - Complexity = 3
+ // Dst: (EXTRACT_SUBREG:{ *:[f64] } (SPLAT_D:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$ws, (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } i64:{ *:[i64] }:$idx, sub_32:{ *:[i32] }), GPR32:{ *:[i32] })), sub_64:{ *:[i32] })
+/* 42755*/ 0, /*End of Scope*/
+/* 42756*/ 0, /*End of Scope*/
+/* 42757*/ /*SwitchOpcode*/ 66|128,1/*194*/, TARGET_VAL(MipsISD::JmpLink),// ->42955
+/* 42761*/ OPC_RecordNode, // #0 = 'MipsJmpLink' chained node
+/* 42762*/ OPC_CaptureGlueInput,
+/* 42763*/ OPC_RecordChild1, // #1 = $target
+/* 42764*/ OPC_Scope, 108, /*->42874*/ // 3 children in Scope
+/* 42766*/ OPC_MoveChild1,
+/* 42767*/ OPC_SwitchOpcode /*2 cases */, 60, TARGET_VAL(ISD::TargetGlobalAddress),// ->42831
+/* 42771*/ OPC_Scope, 23, /*->42796*/ // 3 children in Scope
+/* 42773*/ OPC_MoveParent,
+/* 42774*/ OPC_Scope, 9, /*->42785*/ // 2 children in Scope
+/* 42776*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 42778*/ OPC_EmitMergeInputChains1_0,
+/* 42779*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JAL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink (tglobaladdr:{ *:[iPTR] }):$target) - Complexity = 6
+ // Dst: (JAL (tglobaladdr:{ *:[iPTR] }):$target)
+/* 42785*/ /*Scope*/ 9, /*->42795*/
+/* 42786*/ OPC_CheckPatternPredicate, 49, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 42788*/ OPC_EmitMergeInputChains1_0,
+/* 42789*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JALX), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink (tglobaladdr:{ *:[iPTR] }):$target) - Complexity = 6
+ // Dst: (JALX (tglobaladdr:{ *:[iPTR] }):$target)
+/* 42795*/ 0, /*End of Scope*/
+/* 42796*/ /*Scope*/ 12, /*->42809*/
+/* 42797*/ OPC_CheckType, MVT::i32,
+/* 42799*/ OPC_MoveParent,
+/* 42800*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 42802*/ OPC_EmitMergeInputChains1_0,
+/* 42803*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::Jal16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink (tglobaladdr:{ *:[i32] }):$dst) - Complexity = 6
+ // Dst: (Jal16 (tglobaladdr:{ *:[i32] }):$dst)
+/* 42809*/ /*Scope*/ 20, /*->42830*/
+/* 42810*/ OPC_MoveParent,
+/* 42811*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 42813*/ OPC_EmitMergeInputChains1_0,
+/* 42814*/ OPC_Scope, 6, /*->42822*/ // 2 children in Scope
+/* 42816*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JAL_MM), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink (tglobaladdr:{ *:[iPTR] }):$target) - Complexity = 6
+ // Dst: (JAL_MM (tglobaladdr:{ *:[iPTR] }):$target)
+/* 42822*/ /*Scope*/ 6, /*->42829*/
+/* 42823*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JALX_MM), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink (tglobaladdr:{ *:[iPTR] }):$target) - Complexity = 6
+ // Dst: (JALX_MM (tglobaladdr:{ *:[iPTR] }):$target)
+/* 42829*/ 0, /*End of Scope*/
+/* 42830*/ 0, /*End of Scope*/
+/* 42831*/ /*SwitchOpcode*/ 39, TARGET_VAL(ISD::TargetExternalSymbol),// ->42873
+/* 42834*/ OPC_SwitchType /*2 cases */, 23, MVT::i32,// ->42860
+/* 42837*/ OPC_MoveParent,
+/* 42838*/ OPC_Scope, 9, /*->42849*/ // 2 children in Scope
+/* 42840*/ OPC_CheckPatternPredicate, 69, // (Subtarget->hasStandardEncoding())
+/* 42842*/ OPC_EmitMergeInputChains1_0,
+/* 42843*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JAL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink (texternalsym:{ *:[i32] }):$dst) - Complexity = 6
+ // Dst: (JAL (texternalsym:{ *:[i32] }):$dst)
+/* 42849*/ /*Scope*/ 9, /*->42859*/
+/* 42850*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 42852*/ OPC_EmitMergeInputChains1_0,
+/* 42853*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::Jal16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink (texternalsym:{ *:[i32] }):$dst) - Complexity = 6
+ // Dst: (Jal16 (texternalsym:{ *:[i32] }):$dst)
+/* 42859*/ 0, /*End of Scope*/
+/* 42860*/ /*SwitchType*/ 10, MVT::i64,// ->42872
+/* 42862*/ OPC_MoveParent,
+/* 42863*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 42865*/ OPC_EmitMergeInputChains1_0,
+/* 42866*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JAL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink (texternalsym:{ *:[i64] }):$dst) - Complexity = 6
+ // Dst: (JAL (texternalsym:{ *:[i64] }):$dst)
+/* 42872*/ 0, // EndSwitchType
+/* 42873*/ 0, // EndSwitchOpcode
+/* 42874*/ /*Scope*/ 54, /*->42929*/
+/* 42875*/ OPC_CheckChild1Type, MVT::i32,
+/* 42877*/ OPC_Scope, 9, /*->42888*/ // 5 children in Scope
+/* 42879*/ OPC_CheckPatternPredicate, 70, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())
+/* 42881*/ OPC_EmitMergeInputChains1_0,
+/* 42882*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JALRPseudo), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (JALRPseudo GPR32Opnd:{ *:[i32] }:$rs)
+/* 42888*/ /*Scope*/ 9, /*->42898*/
+/* 42889*/ OPC_CheckPatternPredicate, 71, // (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())
+/* 42891*/ OPC_EmitMergeInputChains1_0,
+/* 42892*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JALRHBPseudo), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (JALRHBPseudo GPR32Opnd:{ *:[i32] }:$rs)
+/* 42898*/ /*Scope*/ 9, /*->42908*/
+/* 42899*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 42901*/ OPC_EmitMergeInputChains1_0,
+/* 42902*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JumpLinkReg16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink CPU16Regs:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (JumpLinkReg16 CPU16Regs:{ *:[i32] }:$rs)
+/* 42908*/ /*Scope*/ 9, /*->42918*/
+/* 42909*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 42911*/ OPC_EmitMergeInputChains1_0,
+/* 42912*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JALR16_MM), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (JALR16_MM GPR32Opnd:{ *:[i32] }:$rs)
+/* 42918*/ /*Scope*/ 9, /*->42928*/
+/* 42919*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 42921*/ OPC_EmitMergeInputChains1_0,
+/* 42922*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JALRC16_MMR6), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (JALRC16_MMR6 GPR32Opnd:{ *:[i32] }:$rs)
+/* 42928*/ 0, /*End of Scope*/
+/* 42929*/ /*Scope*/ 24, /*->42954*/
+/* 42930*/ OPC_CheckChild1Type, MVT::i64,
+/* 42932*/ OPC_Scope, 9, /*->42943*/ // 2 children in Scope
+/* 42934*/ OPC_CheckPatternPredicate, 72, // (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())
+/* 42936*/ OPC_EmitMergeInputChains1_0,
+/* 42937*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JALR64Pseudo), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (JALR64Pseudo GPR64Opnd:{ *:[i64] }:$rs)
+/* 42943*/ /*Scope*/ 9, /*->42953*/
+/* 42944*/ OPC_CheckPatternPredicate, 73, // (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())
+/* 42946*/ OPC_EmitMergeInputChains1_0,
+/* 42947*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JALRHB64Pseudo), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsJmpLink GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (JALRHB64Pseudo GPR64Opnd:{ *:[i64] }:$rs)
+/* 42953*/ 0, /*End of Scope*/
+/* 42954*/ 0, /*End of Scope*/
+/* 42955*/ /*SwitchOpcode*/ 63|128,1/*191*/, TARGET_VAL(MipsISD::TailCall),// ->43150
+/* 42959*/ OPC_RecordNode, // #0 = 'MipsTailCall' chained node
+/* 42960*/ OPC_CaptureGlueInput,
+/* 42961*/ OPC_RecordChild1, // #1 = $dst
+/* 42962*/ OPC_Scope, 75, /*->43039*/ // 3 children in Scope
+/* 42964*/ OPC_MoveChild1,
+/* 42965*/ OPC_SwitchOpcode /*2 cases */, 33, TARGET_VAL(ISD::TargetGlobalAddress),// ->43002
+/* 42969*/ OPC_MoveParent,
+/* 42970*/ OPC_Scope, 9, /*->42981*/ // 3 children in Scope
+/* 42972*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 42974*/ OPC_EmitMergeInputChains1_0,
+/* 42975*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall (tglobaladdr:{ *:[iPTR] }):$dst) - Complexity = 6
+ // Dst: (TAILCALL (tglobaladdr:{ *:[iPTR] }):$dst)
+/* 42981*/ /*Scope*/ 9, /*->42991*/
+/* 42982*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 42984*/ OPC_EmitMergeInputChains1_0,
+/* 42985*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALL_MM), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall (tglobaladdr:{ *:[iPTR] }):$dst) - Complexity = 6
+ // Dst: (TAILCALL_MM (tglobaladdr:{ *:[iPTR] }):$dst)
+/* 42991*/ /*Scope*/ 9, /*->43001*/
+/* 42992*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 42994*/ OPC_EmitMergeInputChains1_0,
+/* 42995*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALL_MMR6), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall (tglobaladdr:{ *:[iPTR] }):$dst) - Complexity = 6
+ // Dst: (TAILCALL_MMR6 (tglobaladdr:{ *:[iPTR] }):$dst)
+/* 43001*/ 0, /*End of Scope*/
+/* 43002*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::TargetExternalSymbol),// ->43038
+/* 43005*/ OPC_MoveParent,
+/* 43006*/ OPC_Scope, 9, /*->43017*/ // 3 children in Scope
+/* 43008*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43010*/ OPC_EmitMergeInputChains1_0,
+/* 43011*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall (texternalsym:{ *:[iPTR] }):$dst) - Complexity = 6
+ // Dst: (TAILCALL (texternalsym:{ *:[iPTR] }):$dst)
+/* 43017*/ /*Scope*/ 9, /*->43027*/
+/* 43018*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 43020*/ OPC_EmitMergeInputChains1_0,
+/* 43021*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALL_MM), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall (texternalsym:{ *:[iPTR] }):$dst) - Complexity = 6
+ // Dst: (TAILCALL_MM (texternalsym:{ *:[iPTR] }):$dst)
+/* 43027*/ /*Scope*/ 9, /*->43037*/
+/* 43028*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 43030*/ OPC_EmitMergeInputChains1_0,
+/* 43031*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALL_MMR6), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall (texternalsym:{ *:[iPTR] }):$dst) - Complexity = 6
+ // Dst: (TAILCALL_MMR6 (texternalsym:{ *:[iPTR] }):$dst)
+/* 43037*/ 0, /*End of Scope*/
+/* 43038*/ 0, // EndSwitchOpcode
+/* 43039*/ /*Scope*/ 64, /*->43104*/
+/* 43040*/ OPC_CheckChild1Type, MVT::i32,
+/* 43042*/ OPC_Scope, 9, /*->43053*/ // 6 children in Scope
+/* 43044*/ OPC_CheckPatternPredicate, 74, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 43046*/ OPC_EmitMergeInputChains1_0,
+/* 43047*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLREG), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLREG GPR32Opnd:{ *:[i32] }:$rs)
+/* 43053*/ /*Scope*/ 9, /*->43063*/
+/* 43054*/ OPC_CheckPatternPredicate, 75, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())
+/* 43056*/ OPC_EmitMergeInputChains1_0,
+/* 43057*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLREGHB), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLREGHB GPR32Opnd:{ *:[i32] }:$rs)
+/* 43063*/ /*Scope*/ 9, /*->43073*/
+/* 43064*/ OPC_CheckPatternPredicate, 76, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())
+/* 43066*/ OPC_EmitMergeInputChains1_0,
+/* 43067*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLR6REG), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLR6REG GPR32Opnd:{ *:[i32] }:$rs)
+/* 43073*/ /*Scope*/ 9, /*->43083*/
+/* 43074*/ OPC_CheckPatternPredicate, 77, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())
+/* 43076*/ OPC_EmitMergeInputChains1_0,
+/* 43077*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLHBR6REG), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLHBR6REG GPR32Opnd:{ *:[i32] }:$rs)
+/* 43083*/ /*Scope*/ 9, /*->43093*/
+/* 43084*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 43086*/ OPC_EmitMergeInputChains1_0,
+/* 43087*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLREG_MM), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLREG_MM GPR32Opnd:{ *:[i32] }:$rs)
+/* 43093*/ /*Scope*/ 9, /*->43103*/
+/* 43094*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 43096*/ OPC_EmitMergeInputChains1_0,
+/* 43097*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLREG_MMR6), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLREG_MMR6 GPR32Opnd:{ *:[i32] }:$rs)
+/* 43103*/ 0, /*End of Scope*/
+/* 43104*/ /*Scope*/ 44, /*->43149*/
+/* 43105*/ OPC_CheckChild1Type, MVT::i64,
+/* 43107*/ OPC_Scope, 9, /*->43118*/ // 4 children in Scope
+/* 43109*/ OPC_CheckPatternPredicate, 78, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 43111*/ OPC_EmitMergeInputChains1_0,
+/* 43112*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLREG64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLREG64 GPR64Opnd:{ *:[i64] }:$rs)
+/* 43118*/ /*Scope*/ 9, /*->43128*/
+/* 43119*/ OPC_CheckPatternPredicate, 79, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())
+/* 43121*/ OPC_EmitMergeInputChains1_0,
+/* 43122*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLREGHB64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLREGHB64 GPR64Opnd:{ *:[i64] }:$rs)
+/* 43128*/ /*Scope*/ 9, /*->43138*/
+/* 43129*/ OPC_CheckPatternPredicate, 80, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())
+/* 43131*/ OPC_EmitMergeInputChains1_0,
+/* 43132*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALL64R6REG), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (TAILCALL64R6REG GPR64Opnd:{ *:[i64] }:$rs)
+/* 43138*/ /*Scope*/ 9, /*->43148*/
+/* 43139*/ OPC_CheckPatternPredicate, 81, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())
+/* 43141*/ OPC_EmitMergeInputChains1_0,
+/* 43142*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TAILCALLHB64R6REG), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (MipsTailCall GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (TAILCALLHB64R6REG GPR64Opnd:{ *:[i64] }:$rs)
+/* 43148*/ 0, /*End of Scope*/
+/* 43149*/ 0, /*End of Scope*/
+/* 43150*/ /*SwitchOpcode*/ 16|128,2/*272*/, TARGET_VAL(MipsISD::Hi),// ->43426
+/* 43154*/ OPC_RecordChild0, // #0 = $in
+/* 43155*/ OPC_MoveChild0,
+/* 43156*/ OPC_SwitchOpcode /*5 cases */, 59, TARGET_VAL(ISD::TargetGlobalAddress),// ->43219
+/* 43160*/ OPC_MoveParent,
+/* 43161*/ OPC_SwitchType /*2 cases */, 43, MVT::i32,// ->43207
+/* 43164*/ OPC_Scope, 9, /*->43175*/ // 3 children in Scope
+/* 43166*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43168*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in)
+/* 43175*/ /*Scope*/ 9, /*->43185*/
+/* 43176*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43178*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi_MM:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in)
+/* 43185*/ /*Scope*/ 20, /*->43206*/
+/* 43186*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 43188*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 0, // Results = #1
+/* 43195*/ OPC_EmitInteger, MVT::i32, 16,
+/* 43198*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SllX16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (MipsHi:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (SllX16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in), 16:{ *:[i32] })
+/* 43206*/ 0, /*End of Scope*/
+/* 43207*/ /*SwitchType*/ 9, MVT::i64,// ->43218
+/* 43209*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43211*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in)
+/* 43218*/ 0, // EndSwitchType
+/* 43219*/ /*SwitchOpcode*/ 59, TARGET_VAL(ISD::TargetBlockAddress),// ->43281
+/* 43222*/ OPC_MoveParent,
+/* 43223*/ OPC_SwitchType /*2 cases */, 43, MVT::i32,// ->43269
+/* 43226*/ OPC_Scope, 9, /*->43237*/ // 3 children in Scope
+/* 43228*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43230*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in)
+/* 43237*/ /*Scope*/ 9, /*->43247*/
+/* 43238*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43240*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi_MM:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in)
+/* 43247*/ /*Scope*/ 20, /*->43268*/
+/* 43248*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 43250*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 0, // Results = #1
+/* 43257*/ OPC_EmitInteger, MVT::i32, 16,
+/* 43260*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SllX16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (MipsHi:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (SllX16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in), 16:{ *:[i32] })
+/* 43268*/ 0, /*End of Scope*/
+/* 43269*/ /*SwitchType*/ 9, MVT::i64,// ->43280
+/* 43271*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43273*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i64] } (tblockaddress:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tblockaddress:{ *:[i64] }):$in)
+/* 43280*/ 0, // EndSwitchType
+/* 43281*/ /*SwitchOpcode*/ 59, TARGET_VAL(ISD::TargetJumpTable),// ->43343
+/* 43284*/ OPC_MoveParent,
+/* 43285*/ OPC_SwitchType /*2 cases */, 43, MVT::i32,// ->43331
+/* 43288*/ OPC_Scope, 9, /*->43299*/ // 3 children in Scope
+/* 43290*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43292*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (tjumptable:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi:{ *:[i32] } (tjumptable:{ *:[i32] }):$in)
+/* 43299*/ /*Scope*/ 9, /*->43309*/
+/* 43300*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43302*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (tjumptable:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi_MM:{ *:[i32] } (tjumptable:{ *:[i32] }):$in)
+/* 43309*/ /*Scope*/ 20, /*->43330*/
+/* 43310*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 43312*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 0, // Results = #1
+/* 43319*/ OPC_EmitInteger, MVT::i32, 16,
+/* 43322*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SllX16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (MipsHi:{ *:[i32] } (tjumptable:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (SllX16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } (tjumptable:{ *:[i32] }):$in), 16:{ *:[i32] })
+/* 43330*/ 0, /*End of Scope*/
+/* 43331*/ /*SwitchType*/ 9, MVT::i64,// ->43342
+/* 43333*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43335*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i64] } (tjumptable:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tjumptable:{ *:[i64] }):$in)
+/* 43342*/ 0, // EndSwitchType
+/* 43343*/ /*SwitchOpcode*/ 38, TARGET_VAL(ISD::TargetConstantPool),// ->43384
+/* 43346*/ OPC_MoveParent,
+/* 43347*/ OPC_SwitchType /*2 cases */, 22, MVT::i32,// ->43372
+/* 43350*/ OPC_Scope, 9, /*->43361*/ // 2 children in Scope
+/* 43352*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43354*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (tconstpool:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi:{ *:[i32] } (tconstpool:{ *:[i32] }):$in)
+/* 43361*/ /*Scope*/ 9, /*->43371*/
+/* 43362*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43364*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (tconstpool:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi_MM:{ *:[i32] } (tconstpool:{ *:[i32] }):$in)
+/* 43371*/ 0, /*End of Scope*/
+/* 43372*/ /*SwitchType*/ 9, MVT::i64,// ->43383
+/* 43374*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43376*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i64] } (tconstpool:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tconstpool:{ *:[i64] }):$in)
+/* 43383*/ 0, // EndSwitchType
+/* 43384*/ /*SwitchOpcode*/ 38, TARGET_VAL(ISD::TargetExternalSymbol),// ->43425
+/* 43387*/ OPC_MoveParent,
+/* 43388*/ OPC_SwitchType /*2 cases */, 22, MVT::i32,// ->43413
+/* 43391*/ OPC_Scope, 9, /*->43402*/ // 2 children in Scope
+/* 43393*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43395*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (texternalsym:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi:{ *:[i32] } (texternalsym:{ *:[i32] }):$in)
+/* 43402*/ /*Scope*/ 9, /*->43412*/
+/* 43403*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43405*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i32] } (texternalsym:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi_MM:{ *:[i32] } (texternalsym:{ *:[i32] }):$in)
+/* 43412*/ 0, /*End of Scope*/
+/* 43413*/ /*SwitchType*/ 9, MVT::i64,// ->43424
+/* 43415*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43417*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHi:{ *:[i64] } (texternalsym:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (texternalsym:{ *:[i64] }):$in)
+/* 43424*/ 0, // EndSwitchType
+/* 43425*/ 0, // EndSwitchOpcode
+/* 43426*/ /*SwitchOpcode*/ 82|128,2/*338*/, TARGET_VAL(MipsISD::Lo),// ->43768
+/* 43430*/ OPC_RecordChild0, // #0 = $in
+/* 43431*/ OPC_MoveChild0,
+/* 43432*/ OPC_SwitchOpcode /*6 cases */, 51, TARGET_VAL(ISD::TargetGlobalAddress),// ->43487
+/* 43436*/ OPC_MoveParent,
+/* 43437*/ OPC_SwitchType /*2 cases */, 30, MVT::i32,// ->43470
+/* 43440*/ OPC_Scope, 13, /*->43455*/ // 2 children in Scope
+/* 43442*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43444*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43447*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, (tglobaladdr:{ *:[i32] }):$in)
+/* 43455*/ /*Scope*/ 13, /*->43469*/
+/* 43456*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43458*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43461*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (tglobaladdr:{ *:[i32] }):$in)
+/* 43469*/ 0, /*End of Scope*/
+/* 43470*/ /*SwitchType*/ 14, MVT::i64,// ->43486
+/* 43472*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43474*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 43478*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tglobaladdr:{ *:[i64] }):$in)
+/* 43486*/ 0, // EndSwitchType
+/* 43487*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::TargetBlockAddress),// ->43551
+/* 43490*/ OPC_MoveParent,
+/* 43491*/ OPC_SwitchType /*2 cases */, 40, MVT::i32,// ->43534
+/* 43494*/ OPC_Scope, 13, /*->43509*/ // 3 children in Scope
+/* 43496*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43498*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43501*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, (tblockaddress:{ *:[i32] }):$in)
+/* 43509*/ /*Scope*/ 9, /*->43519*/
+/* 43510*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 43512*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsLo:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LiRxImmX16:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in)
+/* 43519*/ /*Scope*/ 13, /*->43533*/
+/* 43520*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43522*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43525*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tblockaddress:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (tblockaddress:{ *:[i32] }):$in)
+/* 43533*/ 0, /*End of Scope*/
+/* 43534*/ /*SwitchType*/ 14, MVT::i64,// ->43550
+/* 43536*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43538*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 43542*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i64] } (tblockaddress:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tblockaddress:{ *:[i64] }):$in)
+/* 43550*/ 0, // EndSwitchType
+/* 43551*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::TargetJumpTable),// ->43605
+/* 43554*/ OPC_MoveParent,
+/* 43555*/ OPC_SwitchType /*2 cases */, 30, MVT::i32,// ->43588
+/* 43558*/ OPC_Scope, 13, /*->43573*/ // 2 children in Scope
+/* 43560*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43562*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43565*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tjumptable:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, (tjumptable:{ *:[i32] }):$in)
+/* 43573*/ /*Scope*/ 13, /*->43587*/
+/* 43574*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43576*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43579*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tjumptable:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (tjumptable:{ *:[i32] }):$in)
+/* 43587*/ 0, /*End of Scope*/
+/* 43588*/ /*SwitchType*/ 14, MVT::i64,// ->43604
+/* 43590*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43592*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 43596*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i64] } (tjumptable:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tjumptable:{ *:[i64] }):$in)
+/* 43604*/ 0, // EndSwitchType
+/* 43605*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::TargetConstantPool),// ->43659
+/* 43608*/ OPC_MoveParent,
+/* 43609*/ OPC_SwitchType /*2 cases */, 30, MVT::i32,// ->43642
+/* 43612*/ OPC_Scope, 13, /*->43627*/ // 2 children in Scope
+/* 43614*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43616*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43619*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tconstpool:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, (tconstpool:{ *:[i32] }):$in)
+/* 43627*/ /*Scope*/ 13, /*->43641*/
+/* 43628*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43630*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43633*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tconstpool:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (tconstpool:{ *:[i32] }):$in)
+/* 43641*/ 0, /*End of Scope*/
+/* 43642*/ /*SwitchType*/ 14, MVT::i64,// ->43658
+/* 43644*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43646*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 43650*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i64] } (tconstpool:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tconstpool:{ *:[i64] }):$in)
+/* 43658*/ 0, // EndSwitchType
+/* 43659*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::TargetGlobalTLSAddress),// ->43713
+/* 43662*/ OPC_MoveParent,
+/* 43663*/ OPC_SwitchType /*2 cases */, 30, MVT::i32,// ->43696
+/* 43666*/ OPC_Scope, 13, /*->43681*/ // 2 children in Scope
+/* 43668*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43670*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43673*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, (tglobaltlsaddr:{ *:[i32] }):$in)
+/* 43681*/ /*Scope*/ 13, /*->43695*/
+/* 43682*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43684*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43687*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (tglobaltlsaddr:{ *:[i32] }):$in)
+/* 43695*/ 0, /*End of Scope*/
+/* 43696*/ /*SwitchType*/ 14, MVT::i64,// ->43712
+/* 43698*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43700*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 43704*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i64] } (tglobaltlsaddr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tglobaltlsaddr:{ *:[i64] }):$in)
+/* 43712*/ 0, // EndSwitchType
+/* 43713*/ /*SwitchOpcode*/ 51, TARGET_VAL(ISD::TargetExternalSymbol),// ->43767
+/* 43716*/ OPC_MoveParent,
+/* 43717*/ OPC_SwitchType /*2 cases */, 30, MVT::i32,// ->43750
+/* 43720*/ OPC_Scope, 13, /*->43735*/ // 2 children in Scope
+/* 43722*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43724*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43727*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (texternalsym:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, (texternalsym:{ *:[i32] }):$in)
+/* 43735*/ /*Scope*/ 13, /*->43749*/
+/* 43736*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43738*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 43741*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i32] } (texternalsym:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (texternalsym:{ *:[i32] }):$in)
+/* 43749*/ 0, /*End of Scope*/
+/* 43750*/ /*SwitchType*/ 14, MVT::i64,// ->43766
+/* 43752*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 43754*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 43758*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsLo:{ *:[i64] } (texternalsym:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (texternalsym:{ *:[i64] }):$in)
+/* 43766*/ 0, // EndSwitchType
+/* 43767*/ 0, // EndSwitchOpcode
+/* 43768*/ /*SwitchOpcode*/ 86, TARGET_VAL(MipsISD::GotHi),// ->43857
+/* 43771*/ OPC_RecordChild0, // #0 = $in
+/* 43772*/ OPC_MoveChild0,
+/* 43773*/ OPC_SwitchOpcode /*2 cases */, 38, TARGET_VAL(ISD::TargetGlobalAddress),// ->43815
+/* 43777*/ OPC_MoveParent,
+/* 43778*/ OPC_SwitchType /*2 cases */, 22, MVT::i32,// ->43803
+/* 43781*/ OPC_Scope, 9, /*->43792*/ // 2 children in Scope
+/* 43783*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43785*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsGotHi:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in)
+/* 43792*/ /*Scope*/ 9, /*->43802*/
+/* 43793*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43795*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsGotHi:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi_MM:{ *:[i32] } (tglobaladdr:{ *:[i32] }):$in)
+/* 43802*/ 0, /*End of Scope*/
+/* 43803*/ /*SwitchType*/ 9, MVT::i64,// ->43814
+/* 43805*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 43807*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsGotHi:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in)
+/* 43814*/ 0, // EndSwitchType
+/* 43815*/ /*SwitchOpcode*/ 38, TARGET_VAL(ISD::TargetExternalSymbol),// ->43856
+/* 43818*/ OPC_MoveParent,
+/* 43819*/ OPC_SwitchType /*2 cases */, 22, MVT::i32,// ->43844
+/* 43822*/ OPC_Scope, 9, /*->43833*/ // 2 children in Scope
+/* 43824*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43826*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsGotHi:{ *:[i32] } (texternalsym:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi:{ *:[i32] } (texternalsym:{ *:[i32] }):$in)
+/* 43833*/ /*Scope*/ 9, /*->43843*/
+/* 43834*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43836*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsGotHi:{ *:[i32] } (texternalsym:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi_MM:{ *:[i32] } (texternalsym:{ *:[i32] }):$in)
+/* 43843*/ 0, /*End of Scope*/
+/* 43844*/ /*SwitchType*/ 9, MVT::i64,// ->43855
+/* 43846*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 43848*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsGotHi:{ *:[i64] } (texternalsym:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (texternalsym:{ *:[i64] }):$in)
+/* 43855*/ 0, // EndSwitchType
+/* 43856*/ 0, // EndSwitchOpcode
+/* 43857*/ /*SwitchOpcode*/ 64, TARGET_VAL(MipsISD::TlsHi),// ->43924
+/* 43860*/ OPC_RecordChild0, // #0 = $in
+/* 43861*/ OPC_MoveChild0,
+/* 43862*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetGlobalTLSAddress),
+/* 43865*/ OPC_MoveParent,
+/* 43866*/ OPC_SwitchType /*2 cases */, 43, MVT::i32,// ->43912
+/* 43869*/ OPC_Scope, 9, /*->43880*/ // 3 children in Scope
+/* 43871*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43873*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsTlsHi:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$in)
+/* 43880*/ /*Scope*/ 9, /*->43890*/
+/* 43881*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43883*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsTlsHi:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (LUi_MM:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$in)
+/* 43890*/ /*Scope*/ 20, /*->43911*/
+/* 43891*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 43893*/ OPC_EmitNode1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 0, // Results = #1
+/* 43900*/ OPC_EmitInteger, MVT::i32, 16,
+/* 43903*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SllX16), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (MipsTlsHi:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (SllX16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } (tglobaltlsaddr:{ *:[i32] }):$in), 16:{ *:[i32] })
+/* 43911*/ 0, /*End of Scope*/
+/* 43912*/ /*SwitchType*/ 9, MVT::i64,// ->43923
+/* 43914*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 43916*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsTlsHi:{ *:[i64] } (tglobaltlsaddr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tglobaltlsaddr:{ *:[i64] }):$in)
+/* 43923*/ 0, // EndSwitchType
+/* 43924*/ /*SwitchOpcode*/ 35|128,2/*291*/, TARGET_VAL(MipsISD::Wrapper),// ->44219
+/* 43928*/ OPC_RecordChild0, // #0 = $gp
+/* 43929*/ OPC_RecordChild1, // #1 = $in
+/* 43930*/ OPC_MoveChild1,
+/* 43931*/ OPC_SwitchOpcode /*6 cases */, 52, TARGET_VAL(ISD::TargetGlobalAddress),// ->43987
+/* 43935*/ OPC_MoveParent,
+/* 43936*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->43974
+/* 43939*/ OPC_Scope, 10, /*->43951*/ // 3 children in Scope
+/* 43941*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43943*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in)
+/* 43951*/ /*Scope*/ 10, /*->43962*/
+/* 43952*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 43954*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AddiuRxRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } CPU16Regs:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (AddiuRxRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in)
+/* 43962*/ /*Scope*/ 10, /*->43973*/
+/* 43963*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 43965*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaladdr:{ *:[i32] }):$in)
+/* 43973*/ 0, /*End of Scope*/
+/* 43974*/ /*SwitchType*/ 10, MVT::i64,// ->43986
+/* 43976*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 43978*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tglobaladdr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tglobaladdr:{ *:[i64] }):$in)
+/* 43986*/ 0, // EndSwitchType
+/* 43987*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::TargetConstantPool),// ->44031
+/* 43990*/ OPC_MoveParent,
+/* 43991*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->44018
+/* 43994*/ OPC_Scope, 10, /*->44006*/ // 2 children in Scope
+/* 43996*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 43998*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tconstpool:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tconstpool:{ *:[i32] }):$in)
+/* 44006*/ /*Scope*/ 10, /*->44017*/
+/* 44007*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44009*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tconstpool:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tconstpool:{ *:[i32] }):$in)
+/* 44017*/ 0, /*End of Scope*/
+/* 44018*/ /*SwitchType*/ 10, MVT::i64,// ->44030
+/* 44020*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44022*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tconstpool:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tconstpool:{ *:[i64] }):$in)
+/* 44030*/ 0, // EndSwitchType
+/* 44031*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::TargetExternalSymbol),// ->44075
+/* 44034*/ OPC_MoveParent,
+/* 44035*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->44062
+/* 44038*/ OPC_Scope, 10, /*->44050*/ // 2 children in Scope
+/* 44040*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 44042*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (texternalsym:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (texternalsym:{ *:[i32] }):$in)
+/* 44050*/ /*Scope*/ 10, /*->44061*/
+/* 44051*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44053*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (texternalsym:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (texternalsym:{ *:[i32] }):$in)
+/* 44061*/ 0, /*End of Scope*/
+/* 44062*/ /*SwitchType*/ 10, MVT::i64,// ->44074
+/* 44064*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44066*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (texternalsym:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (texternalsym:{ *:[i64] }):$in)
+/* 44074*/ 0, // EndSwitchType
+/* 44075*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::TargetBlockAddress),// ->44119
+/* 44078*/ OPC_MoveParent,
+/* 44079*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->44106
+/* 44082*/ OPC_Scope, 10, /*->44094*/ // 2 children in Scope
+/* 44084*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 44086*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tblockaddress:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tblockaddress:{ *:[i32] }):$in)
+/* 44094*/ /*Scope*/ 10, /*->44105*/
+/* 44095*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44097*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tblockaddress:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tblockaddress:{ *:[i32] }):$in)
+/* 44105*/ 0, /*End of Scope*/
+/* 44106*/ /*SwitchType*/ 10, MVT::i64,// ->44118
+/* 44108*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44110*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tblockaddress:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tblockaddress:{ *:[i64] }):$in)
+/* 44118*/ 0, // EndSwitchType
+/* 44119*/ /*SwitchOpcode*/ 41, TARGET_VAL(ISD::TargetJumpTable),// ->44163
+/* 44122*/ OPC_MoveParent,
+/* 44123*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->44150
+/* 44126*/ OPC_Scope, 10, /*->44138*/ // 2 children in Scope
+/* 44128*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 44130*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tjumptable:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tjumptable:{ *:[i32] }):$in)
+/* 44138*/ /*Scope*/ 10, /*->44149*/
+/* 44139*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44141*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tjumptable:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tjumptable:{ *:[i32] }):$in)
+/* 44149*/ 0, /*End of Scope*/
+/* 44150*/ /*SwitchType*/ 10, MVT::i64,// ->44162
+/* 44152*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44154*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tjumptable:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tjumptable:{ *:[i64] }):$in)
+/* 44162*/ 0, // EndSwitchType
+/* 44163*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::TargetGlobalTLSAddress),// ->44218
+/* 44166*/ OPC_MoveParent,
+/* 44167*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->44205
+/* 44170*/ OPC_Scope, 10, /*->44182*/ // 3 children in Scope
+/* 44172*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 44174*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaltlsaddr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaltlsaddr:{ *:[i32] }):$in)
+/* 44182*/ /*Scope*/ 10, /*->44193*/
+/* 44183*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 44185*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AddiuRxRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } CPU16Regs:{ *:[i32] }:$gp, (tglobaltlsaddr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (AddiuRxRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$gp, (tglobaltlsaddr:{ *:[i32] }):$in)
+/* 44193*/ /*Scope*/ 10, /*->44204*/
+/* 44194*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44196*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaltlsaddr:{ *:[i32] }):$in) - Complexity = 6
+ // Dst: (ADDiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$gp, (tglobaltlsaddr:{ *:[i32] }):$in)
+/* 44204*/ 0, /*End of Scope*/
+/* 44205*/ /*SwitchType*/ 10, MVT::i64,// ->44217
+/* 44207*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44209*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsWrapper:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tglobaltlsaddr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } GPR64:{ *:[i64] }:$gp, (tglobaltlsaddr:{ *:[i64] }):$in)
+/* 44217*/ 0, // EndSwitchType
+/* 44218*/ 0, // EndSwitchOpcode
+/* 44219*/ /*SwitchOpcode*/ 6|128,1/*134*/, TARGET_VAL(MipsISD::FPCmp),// ->44357
+/* 44223*/ OPC_RecordChild0, // #0 = $fs
+/* 44224*/ OPC_Scope, 39, /*->44265*/ // 3 children in Scope
+/* 44226*/ OPC_CheckChild0Type, MVT::f32,
+/* 44228*/ OPC_RecordChild1, // #1 = $ft
+/* 44229*/ OPC_RecordChild2, // #2 = $cond
+/* 44230*/ OPC_MoveChild2,
+/* 44231*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 44234*/ OPC_MoveParent,
+/* 44235*/ OPC_Scope, 13, /*->44250*/ // 2 children in Scope
+/* 44237*/ OPC_CheckPatternPredicate, 63, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 44239*/ OPC_EmitConvertToTarget, 2,
+/* 44241*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCMP_S32), 0|OPFL_GlueOutput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 3,
+ // Src: (MipsFPCmp FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$ft, (imm:{ *:[i32] }):$cond) - Complexity = 6
+ // Dst: (FCMP_S32:{ *:[i32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$ft, (imm:{ *:[i32] }):$cond)
+/* 44250*/ /*Scope*/ 13, /*->44264*/
+/* 44251*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 44253*/ OPC_EmitConvertToTarget, 2,
+/* 44255*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCMP_S32_MM), 0|OPFL_GlueOutput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 3,
+ // Src: (MipsFPCmp FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$ft, (imm:{ *:[i32] }):$cond) - Complexity = 6
+ // Dst: (FCMP_S32_MM:{ *:[i32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$ft, (imm:{ *:[i32] }):$cond)
+/* 44264*/ 0, /*End of Scope*/
+/* 44265*/ /*Scope*/ 53, /*->44319*/
+/* 44266*/ OPC_CheckChild0Type, MVT::f64,
+/* 44268*/ OPC_RecordChild1, // #1 = $ft
+/* 44269*/ OPC_RecordChild2, // #2 = $cond
+/* 44270*/ OPC_MoveChild2,
+/* 44271*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 44274*/ OPC_MoveParent,
+/* 44275*/ OPC_Scope, 13, /*->44290*/ // 3 children in Scope
+/* 44277*/ OPC_CheckPatternPredicate, 82, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 44279*/ OPC_EmitConvertToTarget, 2,
+/* 44281*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCMP_D32), 0|OPFL_GlueOutput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 3,
+ // Src: (MipsFPCmp AFGR64:{ *:[f64] }:$fs, AFGR64:{ *:[f64] }:$ft, (imm:{ *:[i32] }):$cond) - Complexity = 6
+ // Dst: (FCMP_D32:{ *:[i32] } AFGR64:{ *:[f64] }:$fs, AFGR64:{ *:[f64] }:$ft, (imm:{ *:[i32] }):$cond)
+/* 44290*/ /*Scope*/ 13, /*->44304*/
+/* 44291*/ OPC_CheckPatternPredicate, 83, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 44293*/ OPC_EmitConvertToTarget, 2,
+/* 44295*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCMP_D64), 0|OPFL_GlueOutput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 3,
+ // Src: (MipsFPCmp FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$ft, (imm:{ *:[i32] }):$cond) - Complexity = 6
+ // Dst: (FCMP_D64:{ *:[i32] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$ft, (imm:{ *:[i32] }):$cond)
+/* 44304*/ /*Scope*/ 13, /*->44318*/
+/* 44305*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 44307*/ OPC_EmitConvertToTarget, 2,
+/* 44309*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCMP_D32_MM), 0|OPFL_GlueOutput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 3,
+ // Src: (MipsFPCmp AFGR64:{ *:[f64] }:$fs, AFGR64:{ *:[f64] }:$ft, (imm:{ *:[i32] }):$cond) - Complexity = 6
+ // Dst: (FCMP_D32_MM:{ *:[i32] } AFGR64:{ *:[f64] }:$fs, AFGR64:{ *:[f64] }:$ft, (imm:{ *:[i32] }):$cond)
+/* 44318*/ 0, /*End of Scope*/
+/* 44319*/ /*Scope*/ 36, /*->44356*/
+/* 44320*/ OPC_CheckChild0Type, MVT::f16,
+/* 44322*/ OPC_RecordChild1, // #1 = $wt
+/* 44323*/ OPC_RecordChild2, // #2 = $cond
+/* 44324*/ OPC_MoveChild2,
+/* 44325*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 44328*/ OPC_MoveParent,
+/* 44329*/ OPC_CheckPatternPredicate, 84, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 44331*/ OPC_EmitNode1, TARGET_VAL(Mips::MSA_FP_EXTEND_W_PSEUDO), 0,
+ MVT::f32, 1/*#Ops*/, 0, // Results = #3
+/* 44338*/ OPC_EmitNode1, TARGET_VAL(Mips::MSA_FP_EXTEND_W_PSEUDO), 0,
+ MVT::f32, 1/*#Ops*/, 1, // Results = #4
+/* 44345*/ OPC_EmitConvertToTarget, 2,
+/* 44347*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FCMP_S32), 0|OPFL_GlueOutput,
+ MVT::i32, 3/*#Ops*/, 3, 4, 5,
+ // Src: (MipsFPCmp MSA128F16:{ *:[f16] }:$ws, MSA128F16:{ *:[f16] }:$wt, (imm:{ *:[i32] }):$cond) - Complexity = 6
+ // Dst: (FCMP_S32:{ *:[i32] } (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws), (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$wt), (imm:{ *:[i32] }):$cond)
+/* 44356*/ 0, /*End of Scope*/
+/* 44357*/ /*SwitchOpcode*/ 35, TARGET_VAL(MipsISD::ExtractElementF64),// ->44395
+/* 44360*/ OPC_RecordChild0, // #0 = $src
+/* 44361*/ OPC_RecordChild1, // #1 = $n
+/* 44362*/ OPC_MoveChild1,
+/* 44363*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 44366*/ OPC_MoveParent,
+/* 44367*/ OPC_Scope, 12, /*->44381*/ // 2 children in Scope
+/* 44369*/ OPC_CheckPatternPredicate, 85, // (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())
+/* 44371*/ OPC_EmitConvertToTarget, 1,
+/* 44373*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ExtractElementF64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsExtractElementF64:{ *:[i32] } AFGR64Opnd:{ *:[f64] }:$src, (imm:{ *:[i32] }):$n) - Complexity = 6
+ // Dst: (ExtractElementF64:{ *:[i32] } AFGR64Opnd:{ *:[f64] }:$src, (imm:{ *:[i32] }):$n)
+/* 44381*/ /*Scope*/ 12, /*->44394*/
+/* 44382*/ OPC_CheckPatternPredicate, 86, // (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())
+/* 44384*/ OPC_EmitConvertToTarget, 1,
+/* 44386*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ExtractElementF64_64), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (MipsExtractElementF64:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$src, (imm:{ *:[i32] }):$n) - Complexity = 6
+ // Dst: (ExtractElementF64_64:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$src, (imm:{ *:[i32] }):$n)
+/* 44394*/ 0, /*End of Scope*/
+/* 44395*/ /*SwitchOpcode*/ 79, TARGET_VAL(MipsISD::Highest),// ->44477
+/* 44398*/ OPC_RecordChild0, // #0 = $in
+/* 44399*/ OPC_MoveChild0,
+/* 44400*/ OPC_SwitchOpcode /*5 cases */, 12, TARGET_VAL(ISD::TargetGlobalAddress),// ->44416
+/* 44404*/ OPC_MoveParent,
+/* 44405*/ OPC_CheckType, MVT::i64,
+/* 44407*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44409*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHighest:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in)
+/* 44416*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::TargetBlockAddress),// ->44431
+/* 44419*/ OPC_MoveParent,
+/* 44420*/ OPC_CheckType, MVT::i64,
+/* 44422*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44424*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHighest:{ *:[i64] } (tblockaddress:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tblockaddress:{ *:[i64] }):$in)
+/* 44431*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::TargetJumpTable),// ->44446
+/* 44434*/ OPC_MoveParent,
+/* 44435*/ OPC_CheckType, MVT::i64,
+/* 44437*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44439*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHighest:{ *:[i64] } (tjumptable:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tjumptable:{ *:[i64] }):$in)
+/* 44446*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::TargetConstantPool),// ->44461
+/* 44449*/ OPC_MoveParent,
+/* 44450*/ OPC_CheckType, MVT::i64,
+/* 44452*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44454*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHighest:{ *:[i64] } (tconstpool:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (tconstpool:{ *:[i64] }):$in)
+/* 44461*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::TargetExternalSymbol),// ->44476
+/* 44464*/ OPC_MoveParent,
+/* 44465*/ OPC_CheckType, MVT::i64,
+/* 44467*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsHighest:{ *:[i64] } (texternalsym:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (LUi64:{ *:[i64] } (texternalsym:{ *:[i64] }):$in)
+/* 44476*/ 0, // EndSwitchOpcode
+/* 44477*/ /*SwitchOpcode*/ 104, TARGET_VAL(MipsISD::Higher),// ->44584
+/* 44480*/ OPC_RecordChild0, // #0 = $in
+/* 44481*/ OPC_MoveChild0,
+/* 44482*/ OPC_SwitchOpcode /*5 cases */, 17, TARGET_VAL(ISD::TargetGlobalAddress),// ->44503
+/* 44486*/ OPC_MoveParent,
+/* 44487*/ OPC_CheckType, MVT::i64,
+/* 44489*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44491*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44495*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsHigher:{ *:[i64] } (tglobaladdr:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tglobaladdr:{ *:[i64] }):$in)
+/* 44503*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::TargetBlockAddress),// ->44523
+/* 44506*/ OPC_MoveParent,
+/* 44507*/ OPC_CheckType, MVT::i64,
+/* 44509*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44511*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44515*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsHigher:{ *:[i64] } (tblockaddress:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tblockaddress:{ *:[i64] }):$in)
+/* 44523*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::TargetJumpTable),// ->44543
+/* 44526*/ OPC_MoveParent,
+/* 44527*/ OPC_CheckType, MVT::i64,
+/* 44529*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44531*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44535*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsHigher:{ *:[i64] } (tjumptable:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tjumptable:{ *:[i64] }):$in)
+/* 44543*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::TargetConstantPool),// ->44563
+/* 44546*/ OPC_MoveParent,
+/* 44547*/ OPC_CheckType, MVT::i64,
+/* 44549*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44551*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44555*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsHigher:{ *:[i64] } (tconstpool:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (tconstpool:{ *:[i64] }):$in)
+/* 44563*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::TargetExternalSymbol),// ->44583
+/* 44566*/ OPC_MoveParent,
+/* 44567*/ OPC_CheckType, MVT::i64,
+/* 44569*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 44571*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44575*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsHigher:{ *:[i64] } (texternalsym:{ *:[i64] }):$in) - Complexity = 6
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (texternalsym:{ *:[i64] }):$in)
+/* 44583*/ 0, // EndSwitchOpcode
+/* 44584*/ /*SwitchOpcode*/ 88|128,3/*472*/, TARGET_VAL(ISD::Constant),// ->45060
+/* 44588*/ OPC_RecordNode, // #0 = $imm
+/* 44589*/ OPC_Scope, 18, /*->44609*/ // 18 children in Scope
+/* 44591*/ OPC_CheckPredicate, 57, // Predicate_LUiPred
+/* 44593*/ OPC_CheckType, MVT::i32,
+/* 44595*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 44597*/ OPC_EmitConvertToTarget, 0,
+/* 44599*/ OPC_EmitNodeXForm, 5, 1, // HI16
+/* 44602*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_LUiPred>>:$imm - Complexity = 4
+ // Dst: (LUi:{ *:[i32] } (HI16:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 44609*/ /*Scope*/ 19, /*->44629*/
+/* 44610*/ OPC_CheckPredicate, 58, // Predicate_ORiPred
+/* 44612*/ OPC_CheckType, MVT::i32,
+/* 44614*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 44616*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 44619*/ OPC_EmitConvertToTarget, 0,
+/* 44621*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_ORiPred>><<X:LO16>>:$imm - Complexity = 4
+ // Dst: (ORi:{ *:[i32] } ZERO:{ *:[i32] }, (imm:{ *:[i32] }):$imm)
+/* 44629*/ /*Scope*/ 19, /*->44649*/
+/* 44630*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 44632*/ OPC_CheckType, MVT::i32,
+/* 44634*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 44636*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 44639*/ OPC_EmitConvertToTarget, 0,
+/* 44641*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm - Complexity = 4
+ // Dst: (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, (imm:{ *:[i32] }):$imm)
+/* 44649*/ /*Scope*/ 18, /*->44668*/
+/* 44650*/ OPC_CheckPredicate, 57, // Predicate_LUiPred
+/* 44652*/ OPC_CheckType, MVT::i64,
+/* 44654*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44656*/ OPC_EmitConvertToTarget, 0,
+/* 44658*/ OPC_EmitNodeXForm, 5, 1, // HI16
+/* 44661*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 2,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_LUiPred>>:$imm - Complexity = 4
+ // Dst: (LUi64:{ *:[i64] } (HI16:{ *:[i64] } (imm:{ *:[i64] }):$imm))
+/* 44668*/ /*Scope*/ 20, /*->44689*/
+/* 44669*/ OPC_CheckPredicate, 58, // Predicate_ORiPred
+/* 44671*/ OPC_CheckType, MVT::i64,
+/* 44673*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44675*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44679*/ OPC_EmitConvertToTarget, 0,
+/* 44681*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_ORiPred>><<X:LO16>>:$imm - Complexity = 4
+ // Dst: (ORi64:{ *:[i64] } ZERO_64:{ *:[i64] }, (imm:{ *:[i64] }):$imm)
+/* 44689*/ /*Scope*/ 20, /*->44710*/
+/* 44690*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 44692*/ OPC_CheckType, MVT::i64,
+/* 44694*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44696*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44700*/ OPC_EmitConvertToTarget, 0,
+/* 44702*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DADDiu), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_immSExt16>>:$imm - Complexity = 4
+ // Dst: (DADDiu:{ *:[i64] } ZERO_64:{ *:[i64] }, (imm:{ *:[i64] }):$imm)
+/* 44710*/ /*Scope*/ 18, /*->44729*/
+/* 44711*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 44713*/ OPC_CheckType, MVT::i32,
+/* 44715*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 44717*/ OPC_EmitConvertToTarget, 0,
+/* 44719*/ OPC_EmitNodeXForm, 3, 1, // LO16
+/* 44722*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LiRxImmX16), 0,
+ MVT::i32, 1/*#Ops*/, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$in - Complexity = 4
+ // Dst: (LiRxImmX16:{ *:[i32] } (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$in))
+/* 44729*/ /*Scope*/ 15, /*->44745*/
+/* 44730*/ OPC_CheckPredicate, 59, // Predicate_immLi16
+/* 44732*/ OPC_CheckType, MVT::i32,
+/* 44734*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44736*/ OPC_EmitConvertToTarget, 0,
+/* 44738*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LI16_MM), 0,
+ MVT::i32, 1/*#Ops*/, 1,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm - Complexity = 4
+ // Dst: (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
+/* 44745*/ /*Scope*/ 18, /*->44764*/
+/* 44746*/ OPC_CheckPredicate, 57, // Predicate_LUiPred
+/* 44748*/ OPC_CheckType, MVT::i32,
+/* 44750*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44752*/ OPC_EmitConvertToTarget, 0,
+/* 44754*/ OPC_EmitNodeXForm, 5, 1, // HI16
+/* 44757*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_LUiPred>>:$imm - Complexity = 4
+ // Dst: (LUi_MM:{ *:[i32] } (HI16:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 44764*/ /*Scope*/ 19, /*->44784*/
+/* 44765*/ OPC_CheckPredicate, 58, // Predicate_ORiPred
+/* 44767*/ OPC_CheckType, MVT::i32,
+/* 44769*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44771*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 44774*/ OPC_EmitConvertToTarget, 0,
+/* 44776*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_ORiPred>><<X:LO16>>:$imm - Complexity = 4
+ // Dst: (ORi_MM:{ *:[i32] } ZERO:{ *:[i32] }, (imm:{ *:[i32] }):$imm)
+/* 44784*/ /*Scope*/ 19, /*->44804*/
+/* 44785*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 44787*/ OPC_CheckType, MVT::i32,
+/* 44789*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44791*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 44794*/ OPC_EmitConvertToTarget, 0,
+/* 44796*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDiu_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$imm - Complexity = 4
+ // Dst: (ADDiu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (imm:{ *:[i32] }):$imm)
+/* 44804*/ /*Scope*/ 22, /*->44827*/
+/* 44805*/ OPC_CheckPredicate, 21, // Predicate_immZExt16
+/* 44807*/ OPC_CheckType, MVT::i32,
+/* 44809*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 44811*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 44814*/ OPC_EmitConvertToTarget, 0,
+/* 44816*/ OPC_EmitNodeXForm, 3, 2, // LO16
+/* 44819*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::XORI_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_immZExt16>><<X:LO16>>:$imm - Complexity = 4
+ // Dst: (XORI_MMR6:{ *:[i32] } ZERO:{ *:[i32] }, (LO16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt16>>:$imm))
+/* 44827*/ /*Scope*/ 62, /*->44890*/
+/* 44828*/ OPC_CheckPredicate, 60, // Predicate_LUiORiPred
+/* 44830*/ OPC_SwitchType /*2 cases */, 27, MVT::i32,// ->44860
+/* 44833*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 44835*/ OPC_EmitConvertToTarget, 0,
+/* 44837*/ OPC_EmitNodeXForm, 5, 1, // HI16
+/* 44840*/ OPC_EmitNode1, TARGET_VAL(Mips::LUi), 0,
+ MVT::i32, 1/*#Ops*/, 2, // Results = #3
+/* 44847*/ OPC_EmitConvertToTarget, 0,
+/* 44849*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 44852*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi), 0,
+ MVT::i32, 2/*#Ops*/, 3, 5,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_LUiORiPred>>:$imm - Complexity = 4
+ // Dst: (ORi:{ *:[i32] } (LUi:{ *:[i32] } (HI16:{ *:[i32] } (imm:{ *:[i32] }):$imm)), (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 44860*/ /*SwitchType*/ 27, MVT::i64,// ->44889
+/* 44862*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44864*/ OPC_EmitConvertToTarget, 0,
+/* 44866*/ OPC_EmitNodeXForm, 5, 1, // HI16
+/* 44869*/ OPC_EmitNode1, TARGET_VAL(Mips::LUi64), 0,
+ MVT::i64, 1/*#Ops*/, 2, // Results = #3
+/* 44876*/ OPC_EmitConvertToTarget, 0,
+/* 44878*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 44881*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi64), 0,
+ MVT::i64, 2/*#Ops*/, 3, 5,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_LUiORiPred>>:$imm - Complexity = 4
+ // Dst: (ORi64:{ *:[i64] } (LUi64:{ *:[i64] } (HI16:{ *:[i64] } (imm:{ *:[i64] }):$imm)), (LO16:{ *:[i64] } (imm:{ *:[i64] }):$imm))
+/* 44889*/ 0, // EndSwitchType
+/* 44890*/ /*Scope*/ 34, /*->44925*/
+/* 44891*/ OPC_CheckPredicate, 61, // Predicate_immZExt32Low16Zero
+/* 44893*/ OPC_CheckType, MVT::i64,
+/* 44895*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44897*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44901*/ OPC_EmitConvertToTarget, 0,
+/* 44903*/ OPC_EmitNodeXForm, 5, 2, // HI16
+/* 44906*/ OPC_EmitNode1, TARGET_VAL(Mips::ORi64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 3, // Results = #4
+/* 44914*/ OPC_EmitInteger, MVT::i32, 16,
+/* 44917*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSLL), 0,
+ MVT::i64, 2/*#Ops*/, 4, 5,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_immZExt32Low16Zero>>:$imm - Complexity = 4
+ // Dst: (DSLL:{ *:[i64] } (ORi64:{ *:[i64] } ZERO_64:{ *:[i64] }, (HI16:{ *:[i64] } (imm:{ *:[i64] }):$imm)), 16:{ *:[i32] })
+/* 44925*/ /*Scope*/ 26, /*->44952*/
+/* 44926*/ OPC_CheckPredicate, 19, // Predicate_immSExt16
+/* 44928*/ OPC_CheckType, MVT::i32,
+/* 44930*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 44932*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 44935*/ OPC_EmitNode1, TARGET_VAL(Mips::MoveR3216), 0,
+ MVT::i32, 1/*#Ops*/, 1, // Results = #2
+/* 44942*/ OPC_EmitConvertToTarget, 0,
+/* 44944*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::AddiuRxRxImmX16), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$in - Complexity = 4
+ // Dst: (AddiuRxRxImmX16:{ *:[i32] } (MoveR3216:{ *:[i32] } ZERO:{ *:[i32] }), (imm:{ *:[i32] })<<P:Predicate_immSExt16>>:$in)
+/* 44952*/ /*Scope*/ 31, /*->44984*/
+/* 44953*/ OPC_CheckPredicate, 60, // Predicate_LUiORiPred
+/* 44955*/ OPC_CheckType, MVT::i32,
+/* 44957*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 44959*/ OPC_EmitConvertToTarget, 0,
+/* 44961*/ OPC_EmitNodeXForm, 5, 1, // HI16
+/* 44964*/ OPC_EmitNode1, TARGET_VAL(Mips::LUi_MM), 0,
+ MVT::i32, 1/*#Ops*/, 2, // Results = #3
+/* 44971*/ OPC_EmitConvertToTarget, 0,
+/* 44973*/ OPC_EmitNodeXForm, 3, 4, // LO16
+/* 44976*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi_MM), 0,
+ MVT::i32, 2/*#Ops*/, 3, 5,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_LUiORiPred>>:$imm - Complexity = 4
+ // Dst: (ORi_MM:{ *:[i32] } (LUi_MM:{ *:[i32] } (HI16:{ *:[i32] } (imm:{ *:[i32] }):$imm)), (LO16:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 44984*/ /*Scope*/ 47, /*->45032*/
+/* 44985*/ OPC_CheckPredicate, 62, // Predicate_immZExt32
+/* 44987*/ OPC_CheckType, MVT::i64,
+/* 44989*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 44991*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 44995*/ OPC_EmitConvertToTarget, 0,
+/* 44997*/ OPC_EmitNodeXForm, 5, 2, // HI16
+/* 45000*/ OPC_EmitNode1, TARGET_VAL(Mips::ORi64), 0,
+ MVT::i64, 2/*#Ops*/, 1, 3, // Results = #4
+/* 45008*/ OPC_EmitInteger, MVT::i32, 16,
+/* 45011*/ OPC_EmitNode1, TARGET_VAL(Mips::DSLL), 0,
+ MVT::i64, 2/*#Ops*/, 4, 5, // Results = #6
+/* 45019*/ OPC_EmitConvertToTarget, 0,
+/* 45021*/ OPC_EmitNodeXForm, 3, 7, // LO16
+/* 45024*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ORi64), 0,
+ MVT::i64, 2/*#Ops*/, 6, 8,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_immZExt32>>:$imm - Complexity = 4
+ // Dst: (ORi64:{ *:[i64] } (DSLL:{ *:[i64] } (ORi64:{ *:[i64] } ZERO_64:{ *:[i64] }, (HI16:{ *:[i64] } (imm:{ *:[i64] }):$imm)), 16:{ *:[i32] }), (LO16:{ *:[i64] } (imm:{ *:[i64] }):$imm))
+/* 45032*/ /*Scope*/ 26, /*->45059*/
+/* 45033*/ OPC_CheckType, MVT::i32,
+/* 45035*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 45037*/ OPC_EmitConvertToTarget, 0,
+/* 45039*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 45051*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LwConstant32), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i32] }):$imm - Complexity = 3
+ // Dst: (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
+/* 45059*/ 0, /*End of Scope*/
+/* 45060*/ /*SwitchOpcode*/ 124, TARGET_VAL(ISD::BRIND),// ->45187
+/* 45063*/ OPC_RecordNode, // #0 = 'brind' chained node
+/* 45064*/ OPC_RecordChild1, // #1 = $rs
+/* 45065*/ OPC_Scope, 74, /*->45141*/ // 2 children in Scope
+/* 45067*/ OPC_CheckChild1Type, MVT::i32,
+/* 45069*/ OPC_Scope, 9, /*->45080*/ // 7 children in Scope
+/* 45071*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 45073*/ OPC_EmitMergeInputChains1_0,
+/* 45074*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::JrcRx16), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind CPU16Regs:{ *:[i32] }:$rs) - Complexity = 4
+ // Dst: (JrcRx16 CPU16Regs:{ *:[i32] }:$rs)
+/* 45080*/ /*Scope*/ 9, /*->45090*/
+/* 45081*/ OPC_CheckPatternPredicate, 74, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 45083*/ OPC_EmitMergeInputChains1_0,
+/* 45084*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndirectBranch), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndirectBranch GPR32Opnd:{ *:[i32] }:$rs)
+/* 45090*/ /*Scope*/ 9, /*->45100*/
+/* 45091*/ OPC_CheckPatternPredicate, 87, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())
+/* 45093*/ OPC_EmitMergeInputChains1_0,
+/* 45094*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndirectHazardBranch), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndirectHazardBranch GPR32Opnd:{ *:[i32] }:$rs)
+/* 45100*/ /*Scope*/ 9, /*->45110*/
+/* 45101*/ OPC_CheckPatternPredicate, 76, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())
+/* 45103*/ OPC_EmitMergeInputChains1_0,
+/* 45104*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndirectBranchR6), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndirectBranchR6 GPR32Opnd:{ *:[i32] }:$rs)
+/* 45110*/ /*Scope*/ 9, /*->45120*/
+/* 45111*/ OPC_CheckPatternPredicate, 77, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())
+/* 45113*/ OPC_EmitMergeInputChains1_0,
+/* 45114*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndrectHazardBranchR6), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndrectHazardBranchR6 GPR32Opnd:{ *:[i32] }:$rs)
+/* 45120*/ /*Scope*/ 9, /*->45130*/
+/* 45121*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 45123*/ OPC_EmitMergeInputChains1_0,
+/* 45124*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndirectBranch_MM), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndirectBranch_MM GPR32Opnd:{ *:[i32] }:$rs)
+/* 45130*/ /*Scope*/ 9, /*->45140*/
+/* 45131*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 45133*/ OPC_EmitMergeInputChains1_0,
+/* 45134*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndirectBranch_MMR6), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndirectBranch_MMR6 GPR32Opnd:{ *:[i32] }:$rs)
+/* 45140*/ 0, /*End of Scope*/
+/* 45141*/ /*Scope*/ 44, /*->45186*/
+/* 45142*/ OPC_CheckChild1Type, MVT::i64,
+/* 45144*/ OPC_Scope, 9, /*->45155*/ // 4 children in Scope
+/* 45146*/ OPC_CheckPatternPredicate, 88, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 45148*/ OPC_EmitMergeInputChains1_0,
+/* 45149*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndirectBranch64), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndirectBranch64 GPR64Opnd:{ *:[i64] }:$rs)
+/* 45155*/ /*Scope*/ 9, /*->45165*/
+/* 45156*/ OPC_CheckPatternPredicate, 87, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())
+/* 45158*/ OPC_EmitMergeInputChains1_0,
+/* 45159*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndirectHazardBranch64), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndirectHazardBranch64 GPR64Opnd:{ *:[i64] }:$rs)
+/* 45165*/ /*Scope*/ 9, /*->45175*/
+/* 45166*/ OPC_CheckPatternPredicate, 80, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())
+/* 45168*/ OPC_EmitMergeInputChains1_0,
+/* 45169*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndirectBranch64R6), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndirectBranch64R6 GPR64Opnd:{ *:[i64] }:$rs)
+/* 45175*/ /*Scope*/ 9, /*->45185*/
+/* 45176*/ OPC_CheckPatternPredicate, 81, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())
+/* 45178*/ OPC_EmitMergeInputChains1_0,
+/* 45179*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::PseudoIndrectHazardBranch64R6), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (brind GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (PseudoIndrectHazardBranch64R6 GPR64Opnd:{ *:[i64] }:$rs)
+/* 45185*/ 0, /*End of Scope*/
+/* 45186*/ 0, /*End of Scope*/
+/* 45187*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->45257
+/* 45190*/ OPC_RecordMemRef,
+/* 45191*/ OPC_RecordNode, // #0 = 'atomic_load_add' chained node
+/* 45192*/ OPC_RecordChild1, // #1 = $ptr
+/* 45193*/ OPC_RecordChild2, // #2 = $incr
+/* 45194*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->45241
+/* 45197*/ OPC_Scope, 13, /*->45212*/ // 3 children in Scope
+/* 45199*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_add_8
+/* 45201*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45203*/ OPC_EmitMergeInputChains1_0,
+/* 45204*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_ADD_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_8>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_ADD_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45212*/ /*Scope*/ 13, /*->45226*/
+/* 45213*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_add_16
+/* 45215*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45217*/ OPC_EmitMergeInputChains1_0,
+/* 45218*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_ADD_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_16>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_ADD_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45226*/ /*Scope*/ 13, /*->45240*/
+/* 45227*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_add_32
+/* 45229*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45231*/ OPC_EmitMergeInputChains1_0,
+/* 45232*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_ADD_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_32>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_ADD_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45240*/ 0, /*End of Scope*/
+/* 45241*/ /*SwitchType*/ 13, MVT::i64,// ->45256
+/* 45243*/ OPC_CheckPredicate, 27, // Predicate_atomic_load_add_64
+/* 45245*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45247*/ OPC_EmitMergeInputChains1_0,
+/* 45248*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_ADD_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_add_64>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_ADD_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
+/* 45256*/ 0, // EndSwitchType
+/* 45257*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->45327
+/* 45260*/ OPC_RecordMemRef,
+/* 45261*/ OPC_RecordNode, // #0 = 'atomic_load_sub' chained node
+/* 45262*/ OPC_RecordChild1, // #1 = $ptr
+/* 45263*/ OPC_RecordChild2, // #2 = $incr
+/* 45264*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->45311
+/* 45267*/ OPC_Scope, 13, /*->45282*/ // 3 children in Scope
+/* 45269*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_sub_8
+/* 45271*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45273*/ OPC_EmitMergeInputChains1_0,
+/* 45274*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_SUB_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_8>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_SUB_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45282*/ /*Scope*/ 13, /*->45296*/
+/* 45283*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_sub_16
+/* 45285*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45287*/ OPC_EmitMergeInputChains1_0,
+/* 45288*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_SUB_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_16>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_SUB_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45296*/ /*Scope*/ 13, /*->45310*/
+/* 45297*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_sub_32
+/* 45299*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45301*/ OPC_EmitMergeInputChains1_0,
+/* 45302*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_SUB_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_SUB_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45310*/ 0, /*End of Scope*/
+/* 45311*/ /*SwitchType*/ 13, MVT::i64,// ->45326
+/* 45313*/ OPC_CheckPredicate, 27, // Predicate_atomic_load_sub_64
+/* 45315*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45317*/ OPC_EmitMergeInputChains1_0,
+/* 45318*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_SUB_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_sub:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_SUB_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
+/* 45326*/ 0, // EndSwitchType
+/* 45327*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->45397
+/* 45330*/ OPC_RecordMemRef,
+/* 45331*/ OPC_RecordNode, // #0 = 'atomic_load_and' chained node
+/* 45332*/ OPC_RecordChild1, // #1 = $ptr
+/* 45333*/ OPC_RecordChild2, // #2 = $incr
+/* 45334*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->45381
+/* 45337*/ OPC_Scope, 13, /*->45352*/ // 3 children in Scope
+/* 45339*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_and_8
+/* 45341*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45343*/ OPC_EmitMergeInputChains1_0,
+/* 45344*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_AND_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_8>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_AND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45352*/ /*Scope*/ 13, /*->45366*/
+/* 45353*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_and_16
+/* 45355*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45357*/ OPC_EmitMergeInputChains1_0,
+/* 45358*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_AND_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_16>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_AND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45366*/ /*Scope*/ 13, /*->45380*/
+/* 45367*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_and_32
+/* 45369*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45371*/ OPC_EmitMergeInputChains1_0,
+/* 45372*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_AND_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_32>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_AND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45380*/ 0, /*End of Scope*/
+/* 45381*/ /*SwitchType*/ 13, MVT::i64,// ->45396
+/* 45383*/ OPC_CheckPredicate, 27, // Predicate_atomic_load_and_64
+/* 45385*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45387*/ OPC_EmitMergeInputChains1_0,
+/* 45388*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_AND_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_and_64>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_AND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
+/* 45396*/ 0, // EndSwitchType
+/* 45397*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_OR),// ->45467
+/* 45400*/ OPC_RecordMemRef,
+/* 45401*/ OPC_RecordNode, // #0 = 'atomic_load_or' chained node
+/* 45402*/ OPC_RecordChild1, // #1 = $ptr
+/* 45403*/ OPC_RecordChild2, // #2 = $incr
+/* 45404*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->45451
+/* 45407*/ OPC_Scope, 13, /*->45422*/ // 3 children in Scope
+/* 45409*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_or_8
+/* 45411*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45413*/ OPC_EmitMergeInputChains1_0,
+/* 45414*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_OR_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_8>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_OR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45422*/ /*Scope*/ 13, /*->45436*/
+/* 45423*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_or_16
+/* 45425*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45427*/ OPC_EmitMergeInputChains1_0,
+/* 45428*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_OR_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_16>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_OR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45436*/ /*Scope*/ 13, /*->45450*/
+/* 45437*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_or_32
+/* 45439*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45441*/ OPC_EmitMergeInputChains1_0,
+/* 45442*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_OR_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_32>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_OR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45450*/ 0, /*End of Scope*/
+/* 45451*/ /*SwitchType*/ 13, MVT::i64,// ->45466
+/* 45453*/ OPC_CheckPredicate, 27, // Predicate_atomic_load_or_64
+/* 45455*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45457*/ OPC_EmitMergeInputChains1_0,
+/* 45458*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_OR_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_or_64>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_OR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
+/* 45466*/ 0, // EndSwitchType
+/* 45467*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->45537
+/* 45470*/ OPC_RecordMemRef,
+/* 45471*/ OPC_RecordNode, // #0 = 'atomic_load_xor' chained node
+/* 45472*/ OPC_RecordChild1, // #1 = $ptr
+/* 45473*/ OPC_RecordChild2, // #2 = $incr
+/* 45474*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->45521
+/* 45477*/ OPC_Scope, 13, /*->45492*/ // 3 children in Scope
+/* 45479*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_xor_8
+/* 45481*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45483*/ OPC_EmitMergeInputChains1_0,
+/* 45484*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_XOR_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_8>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_XOR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45492*/ /*Scope*/ 13, /*->45506*/
+/* 45493*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_xor_16
+/* 45495*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45497*/ OPC_EmitMergeInputChains1_0,
+/* 45498*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_XOR_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_16>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_XOR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45506*/ /*Scope*/ 13, /*->45520*/
+/* 45507*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_xor_32
+/* 45509*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45511*/ OPC_EmitMergeInputChains1_0,
+/* 45512*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_XOR_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_32>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_XOR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45520*/ 0, /*End of Scope*/
+/* 45521*/ /*SwitchType*/ 13, MVT::i64,// ->45536
+/* 45523*/ OPC_CheckPredicate, 27, // Predicate_atomic_load_xor_64
+/* 45525*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45527*/ OPC_EmitMergeInputChains1_0,
+/* 45528*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_XOR_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_xor_64>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_XOR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
+/* 45536*/ 0, // EndSwitchType
+/* 45537*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_LOAD_NAND),// ->45607
+/* 45540*/ OPC_RecordMemRef,
+/* 45541*/ OPC_RecordNode, // #0 = 'atomic_load_nand' chained node
+/* 45542*/ OPC_RecordChild1, // #1 = $ptr
+/* 45543*/ OPC_RecordChild2, // #2 = $incr
+/* 45544*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->45591
+/* 45547*/ OPC_Scope, 13, /*->45562*/ // 3 children in Scope
+/* 45549*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_nand_8
+/* 45551*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45553*/ OPC_EmitMergeInputChains1_0,
+/* 45554*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_NAND_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_8>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_NAND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45562*/ /*Scope*/ 13, /*->45576*/
+/* 45563*/ OPC_CheckPredicate, 25, // Predicate_atomic_load_nand_16
+/* 45565*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45567*/ OPC_EmitMergeInputChains1_0,
+/* 45568*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_NAND_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_16>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_NAND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45576*/ /*Scope*/ 13, /*->45590*/
+/* 45577*/ OPC_CheckPredicate, 26, // Predicate_atomic_load_nand_32
+/* 45579*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45581*/ OPC_EmitMergeInputChains1_0,
+/* 45582*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_NAND_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_NAND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45590*/ 0, /*End of Scope*/
+/* 45591*/ /*SwitchType*/ 13, MVT::i64,// ->45606
+/* 45593*/ OPC_CheckPredicate, 27, // Predicate_atomic_load_nand_64
+/* 45595*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45597*/ OPC_EmitMergeInputChains1_0,
+/* 45598*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_LOAD_NAND_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_nand:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>> - Complexity = 4
+ // Dst: (ATOMIC_LOAD_NAND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
+/* 45606*/ 0, // EndSwitchType
+/* 45607*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::ATOMIC_SWAP),// ->45677
+/* 45610*/ OPC_RecordMemRef,
+/* 45611*/ OPC_RecordNode, // #0 = 'atomic_swap' chained node
+/* 45612*/ OPC_RecordChild1, // #1 = $ptr
+/* 45613*/ OPC_RecordChild2, // #2 = $incr
+/* 45614*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->45661
+/* 45617*/ OPC_Scope, 13, /*->45632*/ // 3 children in Scope
+/* 45619*/ OPC_CheckPredicate, 24, // Predicate_atomic_swap_8
+/* 45621*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45623*/ OPC_EmitMergeInputChains1_0,
+/* 45624*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_8>> - Complexity = 4
+ // Dst: (ATOMIC_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45632*/ /*Scope*/ 13, /*->45646*/
+/* 45633*/ OPC_CheckPredicate, 25, // Predicate_atomic_swap_16
+/* 45635*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45637*/ OPC_EmitMergeInputChains1_0,
+/* 45638*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_16>> - Complexity = 4
+ // Dst: (ATOMIC_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45646*/ /*Scope*/ 13, /*->45660*/
+/* 45647*/ OPC_CheckPredicate, 26, // Predicate_atomic_swap_32
+/* 45649*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45651*/ OPC_EmitMergeInputChains1_0,
+/* 45652*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_32>> - Complexity = 4
+ // Dst: (ATOMIC_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
+/* 45660*/ 0, /*End of Scope*/
+/* 45661*/ /*SwitchType*/ 13, MVT::i64,// ->45676
+/* 45663*/ OPC_CheckPredicate, 27, // Predicate_atomic_swap_64
+/* 45665*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45667*/ OPC_EmitMergeInputChains1_0,
+/* 45668*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_SWAP_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_swap_64>> - Complexity = 4
+ // Dst: (ATOMIC_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
+/* 45676*/ 0, // EndSwitchType
+/* 45677*/ /*SwitchOpcode*/ 72, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->45752
+/* 45680*/ OPC_RecordMemRef,
+/* 45681*/ OPC_RecordNode, // #0 = 'atomic_cmp_swap' chained node
+/* 45682*/ OPC_RecordChild1, // #1 = $ptr
+/* 45683*/ OPC_RecordChild2, // #2 = $cmp
+/* 45684*/ OPC_RecordChild3, // #3 = $swap
+/* 45685*/ OPC_SwitchType /*2 cases */, 47, MVT::i32,// ->45735
+/* 45688*/ OPC_Scope, 14, /*->45704*/ // 3 children in Scope
+/* 45690*/ OPC_CheckPredicate, 24, // Predicate_atomic_cmp_swap_8
+/* 45692*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45694*/ OPC_EmitMergeInputChains1_0,
+/* 45695*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_CMP_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_8>> - Complexity = 4
+ // Dst: (ATOMIC_CMP_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
+/* 45704*/ /*Scope*/ 14, /*->45719*/
+/* 45705*/ OPC_CheckPredicate, 25, // Predicate_atomic_cmp_swap_16
+/* 45707*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45709*/ OPC_EmitMergeInputChains1_0,
+/* 45710*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_CMP_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_16>> - Complexity = 4
+ // Dst: (ATOMIC_CMP_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
+/* 45719*/ /*Scope*/ 14, /*->45734*/
+/* 45720*/ OPC_CheckPredicate, 26, // Predicate_atomic_cmp_swap_32
+/* 45722*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45724*/ OPC_EmitMergeInputChains1_0,
+/* 45725*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_CMP_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_32>> - Complexity = 4
+ // Dst: (ATOMIC_CMP_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
+/* 45734*/ 0, /*End of Scope*/
+/* 45735*/ /*SwitchType*/ 14, MVT::i64,// ->45751
+/* 45737*/ OPC_CheckPredicate, 27, // Predicate_atomic_cmp_swap_64
+/* 45739*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45741*/ OPC_EmitMergeInputChains1_0,
+/* 45742*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ATOMIC_CMP_SWAP_I64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_cmp_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_64>> - Complexity = 4
+ // Dst: (ATOMIC_CMP_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)
+/* 45751*/ 0, // EndSwitchType
+/* 45752*/ /*SwitchOpcode*/ 22, TARGET_VAL(MipsISD::Ret),// ->45777
+/* 45755*/ OPC_RecordNode, // #0 = 'MipsRet' chained node
+/* 45756*/ OPC_CaptureGlueInput,
+/* 45757*/ OPC_Scope, 8, /*->45767*/ // 2 children in Scope
+/* 45759*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45761*/ OPC_EmitMergeInputChains1_0,
+/* 45762*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::RetRA), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0,
+ 0/*#Ops*/,
+ // Src: (MipsRet) - Complexity = 3
+ // Dst: (RetRA)
+/* 45767*/ /*Scope*/ 8, /*->45776*/
+/* 45768*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 45770*/ OPC_EmitMergeInputChains1_0,
+/* 45771*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::RetRA16), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0,
+ 0/*#Ops*/,
+ // Src: (MipsRet) - Complexity = 3
+ // Dst: (RetRA16)
+/* 45776*/ 0, /*End of Scope*/
+/* 45777*/ /*SwitchOpcode*/ 10, TARGET_VAL(MipsISD::ERet),// ->45790
+/* 45780*/ OPC_RecordNode, // #0 = 'MipsERet' chained node
+/* 45781*/ OPC_CaptureGlueInput,
+/* 45782*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 45784*/ OPC_EmitMergeInputChains1_0,
+/* 45785*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::ERet), 0|OPFL_Chain|OPFL_GlueInput,
+ 0/*#Ops*/,
+ // Src: (MipsERet) - Complexity = 3
+ // Dst: (ERet)
+/* 45790*/ /*SwitchOpcode*/ 43|128,1/*171*/, TARGET_VAL(ISD::MUL),// ->45965
+/* 45794*/ OPC_RecordChild0, // #0 = $rs
+/* 45795*/ OPC_RecordChild1, // #1 = $rt
+/* 45796*/ OPC_SwitchType /*7 cases */, 78, MVT::i32,// ->45877
+/* 45799*/ OPC_Scope, 11, /*->45812*/ // 6 children in Scope
+/* 45801*/ OPC_CheckPatternPredicate, 49, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 45803*/ OPC_MorphNodeTo2, TARGET_VAL(Mips::MUL), 0,
+ MVT::i32, MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 45812*/ /*Scope*/ 10, /*->45823*/
+/* 45813*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 45815*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUL_R6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 45823*/ /*Scope*/ 11, /*->45835*/
+/* 45824*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 45826*/ OPC_MorphNodeTo2, TARGET_VAL(Mips::MultRxRyRz16), 0,
+ MVT::i32, MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) - Complexity = 3
+ // Dst: (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+/* 45835*/ /*Scope*/ 11, /*->45847*/
+/* 45836*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 45838*/ OPC_MorphNodeTo2, TARGET_VAL(Mips::MUL_MM), 0,
+ MVT::i32, MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 45847*/ /*Scope*/ 10, /*->45858*/
+/* 45848*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 45850*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUL_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 45858*/ /*Scope*/ 17, /*->45876*/
+/* 45859*/ OPC_CheckPatternPredicate, 90, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 45861*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoMULT), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1, // Results = #2
+/* 45869*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMFLO), 0,
+ MVT::i32, 1/*#Ops*/, 2,
+ // Src: (mul:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) - Complexity = 3
+ // Dst: (PseudoMFLO:{ *:[i32] } (PseudoMULT:{ *:[Untyped] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
+/* 45876*/ 0, /*End of Scope*/
+/* 45877*/ /*SwitchType*/ 25, MVT::i64,// ->45904
+/* 45879*/ OPC_Scope, 11, /*->45892*/ // 2 children in Scope
+/* 45881*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 45883*/ OPC_MorphNodeTo2, TARGET_VAL(Mips::DMUL), 0,
+ MVT::i64, MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 45892*/ /*Scope*/ 10, /*->45903*/
+/* 45893*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 45895*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMUL_R6), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 45903*/ 0, /*End of Scope*/
+/* 45904*/ /*SwitchType*/ 10, MVT::v2i16,// ->45916
+/* 45906*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 45908*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUL_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) - Complexity = 3
+ // Dst: (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+/* 45916*/ /*SwitchType*/ 10, MVT::v16i8,// ->45928
+/* 45918*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 45920*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULV_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 45928*/ /*SwitchType*/ 10, MVT::v8i16,// ->45940
+/* 45930*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 45932*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULV_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 45940*/ /*SwitchType*/ 10, MVT::v4i32,// ->45952
+/* 45942*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 45944*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULV_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 45952*/ /*SwitchType*/ 10, MVT::v2i64,// ->45964
+/* 45954*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 45956*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULV_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 45964*/ 0, // EndSwitchType
+/* 45965*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::TRAP),// ->45998
+/* 45968*/ OPC_RecordNode, // #0 = 'trap' chained node
+/* 45969*/ OPC_Scope, 8, /*->45979*/ // 3 children in Scope
+/* 45971*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 45973*/ OPC_EmitMergeInputChains1_0,
+/* 45974*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TRAP), 0|OPFL_Chain,
+ 0/*#Ops*/,
+ // Src: (trap) - Complexity = 3
+ // Dst: (TRAP)
+/* 45979*/ /*Scope*/ 8, /*->45988*/
+/* 45980*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 45982*/ OPC_EmitMergeInputChains1_0,
+/* 45983*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::Break16), 0|OPFL_Chain,
+ 0/*#Ops*/,
+ // Src: (trap) - Complexity = 3
+ // Dst: (Break16)
+/* 45988*/ /*Scope*/ 8, /*->45997*/
+/* 45989*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 45991*/ OPC_EmitMergeInputChains1_0,
+/* 45992*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::TRAP_MM), 0|OPFL_Chain,
+ 0/*#Ops*/,
+ // Src: (trap) - Complexity = 3
+ // Dst: (TRAP_MM)
+/* 45997*/ 0, /*End of Scope*/
+/* 45998*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::BR),// ->46070
+/* 46001*/ OPC_RecordNode, // #0 = 'br' chained node
+/* 46002*/ OPC_RecordChild1, // #1 = $target
+/* 46003*/ OPC_MoveChild1,
+/* 46004*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 46007*/ OPC_MoveParent,
+/* 46008*/ OPC_Scope, 9, /*->46019*/ // 6 children in Scope
+/* 46010*/ OPC_CheckPatternPredicate, 91, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!TM.isPositionIndependent())
+/* 46012*/ OPC_EmitMergeInputChains1_0,
+/* 46013*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::J), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (br (bb:{ *:[Other] }):$target) - Complexity = 3
+ // Dst: (J (bb:{ *:[Other] }):$target)
+/* 46019*/ /*Scope*/ 9, /*->46029*/
+/* 46020*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 46022*/ OPC_EmitMergeInputChains1_0,
+/* 46023*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::B), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (br (bb:{ *:[Other] }):$offset) - Complexity = 3
+ // Dst: (B (bb:{ *:[Other] }):$offset)
+/* 46029*/ /*Scope*/ 9, /*->46039*/
+/* 46030*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 46032*/ OPC_EmitMergeInputChains1_0,
+/* 46033*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::Bimm16), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (br (bb:{ *:[Other] }):$imm16) - Complexity = 3
+ // Dst: (Bimm16 (bb:{ *:[Other] }):$imm16)
+/* 46039*/ /*Scope*/ 9, /*->46049*/
+/* 46040*/ OPC_CheckPatternPredicate, 92, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!TM.isPositionIndependent())
+/* 46042*/ OPC_EmitMergeInputChains1_0,
+/* 46043*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::J_MM), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (br (bb:{ *:[Other] }):$target) - Complexity = 3
+ // Dst: (J_MM (bb:{ *:[Other] }):$target)
+/* 46049*/ /*Scope*/ 9, /*->46059*/
+/* 46050*/ OPC_CheckPatternPredicate, 93, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (TM.isPositionIndependent())
+/* 46052*/ OPC_EmitMergeInputChains1_0,
+/* 46053*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::B_MM), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (br (bb:{ *:[Other] }):$offset) - Complexity = 3
+ // Dst: (B_MM (bb:{ *:[Other] }):$offset)
+/* 46059*/ /*Scope*/ 9, /*->46069*/
+/* 46060*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 46062*/ OPC_EmitMergeInputChains1_0,
+/* 46063*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::BC_MMR6), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (br (bb:{ *:[Other] }):$offset) - Complexity = 3
+ // Dst: (BC_MMR6 (bb:{ *:[Other] }):$offset)
+/* 46069*/ 0, /*End of Scope*/
+/* 46070*/ /*SwitchOpcode*/ 33, TARGET_VAL(MipsISD::EH_RETURN),// ->46106
+/* 46073*/ OPC_RecordNode, // #0 = 'MIPSehret' chained node
+/* 46074*/ OPC_CaptureGlueInput,
+/* 46075*/ OPC_RecordChild1, // #1 = $spoff
+/* 46076*/ OPC_Scope, 13, /*->46091*/ // 2 children in Scope
+/* 46078*/ OPC_CheckChild1Type, MVT::i32,
+/* 46080*/ OPC_RecordChild2, // #2 = $dst
+/* 46081*/ OPC_CheckChild2Type, MVT::i32,
+/* 46083*/ OPC_EmitMergeInputChains1_0,
+/* 46084*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::MIPSeh_return32), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic2,
+ 2/*#Ops*/, 1, 2,
+ // Src: (MIPSehret GPR32:{ *:[i32] }:$spoff, GPR32:{ *:[i32] }:$dst) - Complexity = 3
+ // Dst: (MIPSeh_return32 GPR32:{ *:[i32] }:$spoff, GPR32:{ *:[i32] }:$dst)
+/* 46091*/ /*Scope*/ 13, /*->46105*/
+/* 46092*/ OPC_CheckChild1Type, MVT::i64,
+/* 46094*/ OPC_RecordChild2, // #2 = $dst
+/* 46095*/ OPC_CheckChild2Type, MVT::i64,
+/* 46097*/ OPC_EmitMergeInputChains1_0,
+/* 46098*/ OPC_MorphNodeTo0, TARGET_VAL(Mips::MIPSeh_return64), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic2,
+ 2/*#Ops*/, 1, 2,
+ // Src: (MIPSehret GPR64:{ *:[i64] }:$spoff, GPR64:{ *:[i64] }:$dst) - Complexity = 3
+ // Dst: (MIPSeh_return64 GPR64:{ *:[i64] }:$spoff, GPR64:{ *:[i64] }:$dst)
+/* 46105*/ 0, /*End of Scope*/
+/* 46106*/ /*SwitchOpcode*/ 119, TARGET_VAL(ISD::SIGN_EXTEND_INREG),// ->46228
+/* 46109*/ OPC_RecordChild0, // #0 = $rt
+/* 46110*/ OPC_MoveChild1,
+/* 46111*/ OPC_Scope, 50, /*->46163*/ // 3 children in Scope
+/* 46113*/ OPC_CheckValueType, MVT::i8,
+/* 46115*/ OPC_MoveParent,
+/* 46116*/ OPC_SwitchType /*2 cases */, 32, MVT::i32,// ->46151
+/* 46119*/ OPC_Scope, 9, /*->46130*/ // 3 children in Scope
+/* 46121*/ OPC_CheckPatternPredicate, 53, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 46123*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEB), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) - Complexity = 3
+ // Dst: (SEB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 46130*/ /*Scope*/ 9, /*->46140*/
+/* 46131*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 46133*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SebRx16), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i8:{ *:[Other] }) - Complexity = 3
+ // Dst: (SebRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
+/* 46140*/ /*Scope*/ 9, /*->46150*/
+/* 46141*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 46143*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEB_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] }) - Complexity = 3
+ // Dst: (SEB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 46150*/ 0, /*End of Scope*/
+/* 46151*/ /*SwitchType*/ 9, MVT::i64,// ->46162
+/* 46153*/ OPC_CheckPatternPredicate, 94, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding())
+/* 46155*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEB64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i8:{ *:[Other] }) - Complexity = 3
+ // Dst: (SEB64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
+/* 46162*/ 0, // EndSwitchType
+/* 46163*/ /*Scope*/ 50, /*->46214*/
+/* 46164*/ OPC_CheckValueType, MVT::i16,
+/* 46166*/ OPC_MoveParent,
+/* 46167*/ OPC_SwitchType /*2 cases */, 32, MVT::i32,// ->46202
+/* 46170*/ OPC_Scope, 9, /*->46181*/ // 3 children in Scope
+/* 46172*/ OPC_CheckPatternPredicate, 53, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 46174*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEH), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) - Complexity = 3
+ // Dst: (SEH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 46181*/ /*Scope*/ 9, /*->46191*/
+/* 46182*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 46184*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SehRx16), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i16:{ *:[Other] }) - Complexity = 3
+ // Dst: (SehRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
+/* 46191*/ /*Scope*/ 9, /*->46201*/
+/* 46192*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 46194*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEH_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] }) - Complexity = 3
+ // Dst: (SEH_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 46201*/ 0, /*End of Scope*/
+/* 46202*/ /*SwitchType*/ 9, MVT::i64,// ->46213
+/* 46204*/ OPC_CheckPatternPredicate, 94, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding())
+/* 46206*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEH64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i16:{ *:[Other] }) - Complexity = 3
+ // Dst: (SEH64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
+/* 46213*/ 0, // EndSwitchType
+/* 46214*/ /*Scope*/ 12, /*->46227*/
+/* 46215*/ OPC_CheckValueType, MVT::i32,
+/* 46217*/ OPC_MoveParent,
+/* 46218*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 46220*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SLL64_64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLL64_64:{ *:[i64] } GPR64:{ *:[i64] }:$src)
+/* 46227*/ 0, /*End of Scope*/
+/* 46228*/ /*SwitchOpcode*/ 56, TARGET_VAL(MipsISD::Mult),// ->46287
+/* 46231*/ OPC_RecordChild0, // #0 = $rs
+/* 46232*/ OPC_Scope, 38, /*->46272*/ // 2 children in Scope
+/* 46234*/ OPC_CheckChild0Type, MVT::i32,
+/* 46236*/ OPC_RecordChild1, // #1 = $rt
+/* 46237*/ OPC_Scope, 10, /*->46249*/ // 3 children in Scope
+/* 46239*/ OPC_CheckPatternPredicate, 95, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46241*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMULT), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMult:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (PseudoMULT:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 46249*/ /*Scope*/ 10, /*->46260*/
+/* 46250*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46252*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULT_DSP), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMult:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MULT_DSP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 46260*/ /*Scope*/ 10, /*->46271*/
+/* 46261*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 46263*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULT_DSP_MM), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMult:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MULT_DSP_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 46271*/ 0, /*End of Scope*/
+/* 46272*/ /*Scope*/ 13, /*->46286*/
+/* 46273*/ OPC_CheckChild0Type, MVT::i64,
+/* 46275*/ OPC_RecordChild1, // #1 = $rt
+/* 46276*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46278*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoDMULT), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMult:{ *:[Untyped] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (PseudoDMULT:{ *:[Untyped] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 46286*/ 0, /*End of Scope*/
+/* 46287*/ /*SwitchOpcode*/ 56, TARGET_VAL(MipsISD::Multu),// ->46346
+/* 46290*/ OPC_RecordChild0, // #0 = $rs
+/* 46291*/ OPC_Scope, 38, /*->46331*/ // 2 children in Scope
+/* 46293*/ OPC_CheckChild0Type, MVT::i32,
+/* 46295*/ OPC_RecordChild1, // #1 = $rt
+/* 46296*/ OPC_Scope, 10, /*->46308*/ // 3 children in Scope
+/* 46298*/ OPC_CheckPatternPredicate, 95, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46300*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMULTu), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMultu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (PseudoMULTu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 46308*/ /*Scope*/ 10, /*->46319*/
+/* 46309*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46311*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULTU_DSP), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMultu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MULTU_DSP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 46319*/ /*Scope*/ 10, /*->46330*/
+/* 46320*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 46322*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULTU_DSP_MM), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMultu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MULTU_DSP_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 46330*/ 0, /*End of Scope*/
+/* 46331*/ /*Scope*/ 13, /*->46345*/
+/* 46332*/ OPC_CheckChild0Type, MVT::i64,
+/* 46334*/ OPC_RecordChild1, // #1 = $rt
+/* 46335*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46337*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoDMULTu), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMultu:{ *:[Untyped] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (PseudoDMULTu:{ *:[Untyped] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 46345*/ 0, /*End of Scope*/
+/* 46346*/ /*SwitchOpcode*/ 48, TARGET_VAL(MipsISD::MFHI),// ->46397
+/* 46349*/ OPC_RecordChild0, // #0 = $hilo
+/* 46350*/ OPC_SwitchType /*2 cases */, 32, MVT::i32,// ->46385
+/* 46353*/ OPC_Scope, 9, /*->46364*/ // 3 children in Scope
+/* 46355*/ OPC_CheckPatternPredicate, 95, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46357*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMFHI), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsMFHI:{ *:[i32] } ACC64:{ *:[Untyped] }:$hilo) - Complexity = 3
+ // Dst: (PseudoMFHI:{ *:[i32] } ACC64:{ *:[Untyped] }:$hilo)
+/* 46364*/ /*Scope*/ 9, /*->46374*/
+/* 46365*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46367*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MFHI_DSP), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsMFHI:{ *:[i32] } ACC64DSPOpnd:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (MFHI_DSP:{ *:[i32] } ACC64DSPOpnd:{ *:[Untyped] }:$ac)
+/* 46374*/ /*Scope*/ 9, /*->46384*/
+/* 46375*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 46377*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MFHI_DSP_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsMFHI:{ *:[i32] } ACC64DSPOpnd:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (MFHI_DSP_MM:{ *:[i32] } ACC64DSPOpnd:{ *:[Untyped] }:$ac)
+/* 46384*/ 0, /*End of Scope*/
+/* 46385*/ /*SwitchType*/ 9, MVT::i64,// ->46396
+/* 46387*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46389*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMFHI64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsMFHI:{ *:[i64] } ACC128:{ *:[Untyped] }:$hilo) - Complexity = 3
+ // Dst: (PseudoMFHI64:{ *:[i64] } ACC128:{ *:[Untyped] }:$hilo)
+/* 46396*/ 0, // EndSwitchType
+/* 46397*/ /*SwitchOpcode*/ 48, TARGET_VAL(MipsISD::MFLO),// ->46448
+/* 46400*/ OPC_RecordChild0, // #0 = $hilo
+/* 46401*/ OPC_SwitchType /*2 cases */, 32, MVT::i32,// ->46436
+/* 46404*/ OPC_Scope, 9, /*->46415*/ // 3 children in Scope
+/* 46406*/ OPC_CheckPatternPredicate, 95, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46408*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMFLO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsMFLO:{ *:[i32] } ACC64:{ *:[Untyped] }:$hilo) - Complexity = 3
+ // Dst: (PseudoMFLO:{ *:[i32] } ACC64:{ *:[Untyped] }:$hilo)
+/* 46415*/ /*Scope*/ 9, /*->46425*/
+/* 46416*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46418*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MFLO_DSP), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsMFLO:{ *:[i32] } ACC64DSPOpnd:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (MFLO_DSP:{ *:[i32] } ACC64DSPOpnd:{ *:[Untyped] }:$ac)
+/* 46425*/ /*Scope*/ 9, /*->46435*/
+/* 46426*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 46428*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MFLO_DSP_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsMFLO:{ *:[i32] } ACC64DSPOpnd:{ *:[Untyped] }:$ac) - Complexity = 3
+ // Dst: (MFLO_DSP_MM:{ *:[i32] } ACC64DSPOpnd:{ *:[Untyped] }:$ac)
+/* 46435*/ 0, /*End of Scope*/
+/* 46436*/ /*SwitchType*/ 9, MVT::i64,// ->46447
+/* 46438*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46440*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMFLO64), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (MipsMFLO:{ *:[i64] } ACC128:{ *:[Untyped] }:$hilo) - Complexity = 3
+ // Dst: (PseudoMFLO64:{ *:[i64] } ACC128:{ *:[Untyped] }:$hilo)
+/* 46447*/ 0, // EndSwitchType
+/* 46448*/ /*SwitchOpcode*/ 45, TARGET_VAL(MipsISD::MTLOHI),// ->46496
+/* 46451*/ OPC_RecordChild0, // #0 = $lo
+/* 46452*/ OPC_Scope, 27, /*->46481*/ // 2 children in Scope
+/* 46454*/ OPC_CheckChild0Type, MVT::i32,
+/* 46456*/ OPC_RecordChild1, // #1 = $hi
+/* 46457*/ OPC_Scope, 10, /*->46469*/ // 2 children in Scope
+/* 46459*/ OPC_CheckPatternPredicate, 95, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46461*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMTLOHI), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMTLOHI:{ *:[Untyped] } GPR32:{ *:[i32] }:$lo, GPR32:{ *:[i32] }:$hi) - Complexity = 3
+ // Dst: (PseudoMTLOHI:{ *:[Untyped] } GPR32:{ *:[i32] }:$lo, GPR32:{ *:[i32] }:$hi)
+/* 46469*/ /*Scope*/ 10, /*->46480*/
+/* 46470*/ OPC_CheckPatternPredicate, 89, // (!Subtarget->inMips16Mode())
+/* 46472*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMTLOHI_DSP), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMTLOHI:{ *:[Untyped] } GPR32:{ *:[i32] }:$lo, GPR32:{ *:[i32] }:$hi) - Complexity = 3
+ // Dst: (PseudoMTLOHI_DSP:{ *:[Untyped] } GPR32:{ *:[i32] }:$lo, GPR32:{ *:[i32] }:$hi)
+/* 46480*/ 0, /*End of Scope*/
+/* 46481*/ /*Scope*/ 13, /*->46495*/
+/* 46482*/ OPC_CheckChild0Type, MVT::i64,
+/* 46484*/ OPC_RecordChild1, // #1 = $hi
+/* 46485*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46487*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMTLOHI64), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsMTLOHI:{ *:[Untyped] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi) - Complexity = 3
+ // Dst: (PseudoMTLOHI64:{ *:[Untyped] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi)
+/* 46495*/ 0, /*End of Scope*/
+/* 46496*/ /*SwitchOpcode*/ 41, TARGET_VAL(MipsISD::MAdd),// ->46540
+/* 46499*/ OPC_RecordChild0, // #0 = $rs
+/* 46500*/ OPC_RecordChild1, // #1 = $rt
+/* 46501*/ OPC_RecordChild2, // #2 = $acin
+/* 46502*/ OPC_Scope, 11, /*->46515*/ // 3 children in Scope
+/* 46504*/ OPC_CheckPatternPredicate, 96, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46506*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMADD), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMAdd:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (PseudoMADD:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64:{ *:[Untyped] }:$acin)
+/* 46515*/ /*Scope*/ 11, /*->46527*/
+/* 46516*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46518*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_DSP), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMAdd:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MADD_DSP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 46527*/ /*Scope*/ 11, /*->46539*/
+/* 46528*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 46530*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_DSP_MM), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMAdd:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MADD_DSP_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 46539*/ 0, /*End of Scope*/
+/* 46540*/ /*SwitchOpcode*/ 41, TARGET_VAL(MipsISD::MAddu),// ->46584
+/* 46543*/ OPC_RecordChild0, // #0 = $rs
+/* 46544*/ OPC_RecordChild1, // #1 = $rt
+/* 46545*/ OPC_RecordChild2, // #2 = $acin
+/* 46546*/ OPC_Scope, 11, /*->46559*/ // 3 children in Scope
+/* 46548*/ OPC_CheckPatternPredicate, 96, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46550*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMADDU), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMAddu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (PseudoMADDU:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64:{ *:[Untyped] }:$acin)
+/* 46559*/ /*Scope*/ 11, /*->46571*/
+/* 46560*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46562*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDU_DSP), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMAddu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MADDU_DSP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 46571*/ /*Scope*/ 11, /*->46583*/
+/* 46572*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 46574*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADDU_DSP_MM), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMAddu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MADDU_DSP_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 46583*/ 0, /*End of Scope*/
+/* 46584*/ /*SwitchOpcode*/ 41, TARGET_VAL(MipsISD::MSub),// ->46628
+/* 46587*/ OPC_RecordChild0, // #0 = $rs
+/* 46588*/ OPC_RecordChild1, // #1 = $rt
+/* 46589*/ OPC_RecordChild2, // #2 = $acin
+/* 46590*/ OPC_Scope, 11, /*->46603*/ // 3 children in Scope
+/* 46592*/ OPC_CheckPatternPredicate, 96, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46594*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMSUB), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMSub:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (PseudoMSUB:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64:{ *:[Untyped] }:$acin)
+/* 46603*/ /*Scope*/ 11, /*->46615*/
+/* 46604*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46606*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUB_DSP), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMSub:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MSUB_DSP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 46615*/ /*Scope*/ 11, /*->46627*/
+/* 46616*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 46618*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUB_DSP_MM), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMSub:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MSUB_DSP_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 46627*/ 0, /*End of Scope*/
+/* 46628*/ /*SwitchOpcode*/ 41, TARGET_VAL(MipsISD::MSubu),// ->46672
+/* 46631*/ OPC_RecordChild0, // #0 = $rs
+/* 46632*/ OPC_RecordChild1, // #1 = $rt
+/* 46633*/ OPC_RecordChild2, // #2 = $acin
+/* 46634*/ OPC_Scope, 11, /*->46647*/ // 3 children in Scope
+/* 46636*/ OPC_CheckPatternPredicate, 96, // (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 46638*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoMSUBU), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMSubu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (PseudoMSUBU:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64:{ *:[Untyped] }:$acin)
+/* 46647*/ /*Scope*/ 11, /*->46659*/
+/* 46648*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46650*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUBU_DSP), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMSubu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MSUBU_DSP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 46659*/ /*Scope*/ 11, /*->46671*/
+/* 46660*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 46662*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUBU_DSP_MM), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMSubu:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MSUBU_DSP_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 46671*/ 0, /*End of Scope*/
+/* 46672*/ /*SwitchOpcode*/ 53, TARGET_VAL(ISD::SUBC),// ->46728
+/* 46675*/ OPC_RecordChild0, // #0 = $lhs
+/* 46676*/ OPC_RecordChild1, // #1 = $rhs
+/* 46677*/ OPC_SwitchType /*2 cases */, 35, MVT::i32,// ->46715
+/* 46680*/ OPC_Scope, 10, /*->46692*/ // 3 children in Scope
+/* 46682*/ OPC_CheckPatternPredicate, 6, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 46684*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBu), 0|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (subc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) - Complexity = 3
+ // Dst: (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+/* 46692*/ /*Scope*/ 10, /*->46703*/
+/* 46693*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 46695*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBu_MM), 0|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (subc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) - Complexity = 3
+ // Dst: (SUBu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+/* 46703*/ /*Scope*/ 10, /*->46714*/
+/* 46704*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 46706*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SUBU_MMR6), 0|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (subc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) - Complexity = 3
+ // Dst: (SUBU_MMR6:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+/* 46714*/ 0, /*End of Scope*/
+/* 46715*/ /*SwitchType*/ 10, MVT::i64,// ->46727
+/* 46717*/ OPC_CheckPatternPredicate, 59, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 46719*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSUBu), 0|OPFL_GlueOutput,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (subc:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs) - Complexity = 3
+ // Dst: (DSUBu:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs)
+/* 46727*/ 0, // EndSwitchType
+/* 46728*/ /*SwitchOpcode*/ 38|128,18/*2342*/, TARGET_VAL(ISD::BITCAST),// ->49074
+/* 46732*/ OPC_RecordChild0, // #0 = $fs
+/* 46733*/ OPC_Scope, 68, /*->46803*/ // 13 children in Scope
+/* 46735*/ OPC_CheckChild0Type, MVT::f32,
+/* 46737*/ OPC_SwitchType /*3 cases */, 32, MVT::i32,// ->46772
+/* 46740*/ OPC_Scope, 9, /*->46751*/ // 3 children in Scope
+/* 46742*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 46744*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MFC1), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 46751*/ /*Scope*/ 9, /*->46761*/
+/* 46752*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 46754*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MFC1_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 46761*/ /*Scope*/ 9, /*->46771*/
+/* 46762*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 46764*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MFC1_MMR6), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 46771*/ 0, /*End of Scope*/
+/* 46772*/ /*SwitchType*/ 13, MVT::v2i16,// ->46787
+/* 46774*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46776*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 46779*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
+/* 46787*/ /*SwitchType*/ 13, MVT::v4i8,// ->46802
+/* 46789*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46791*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 46794*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
+/* 46802*/ 0, // EndSwitchType
+/* 46803*/ /*Scope*/ 13, /*->46817*/
+/* 46804*/ OPC_CheckChild0Type, MVT::f64,
+/* 46806*/ OPC_CheckType, MVT::i64,
+/* 46808*/ OPC_CheckPatternPredicate, 97, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 46810*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMFC1), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
+/* 46817*/ /*Scope*/ 34, /*->46852*/
+/* 46818*/ OPC_CheckChild0Type, MVT::v2i16,
+/* 46820*/ OPC_SwitchType /*2 cases */, 13, MVT::i32,// ->46836
+/* 46823*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46825*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 46828*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
+/* 46836*/ /*SwitchType*/ 13, MVT::f32,// ->46851
+/* 46838*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46840*/ OPC_EmitInteger, MVT::i32, Mips::FGR32RegClassID,
+/* 46843*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
+/* 46851*/ 0, // EndSwitchType
+/* 46852*/ /*Scope*/ 34, /*->46887*/
+/* 46853*/ OPC_CheckChild0Type, MVT::v4i8,
+/* 46855*/ OPC_SwitchType /*2 cases */, 13, MVT::i32,// ->46871
+/* 46858*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46860*/ OPC_EmitInteger, MVT::i32, Mips::GPR32RegClassID,
+/* 46863*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
+/* 46871*/ /*SwitchType*/ 13, MVT::f32,// ->46886
+/* 46873*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46875*/ OPC_EmitInteger, MVT::i32, Mips::FGR32RegClassID,
+/* 46878*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
+/* 46886*/ 0, // EndSwitchType
+/* 46887*/ /*Scope*/ 68, /*->46956*/
+/* 46888*/ OPC_CheckChild0Type, MVT::i32,
+/* 46890*/ OPC_SwitchType /*3 cases */, 32, MVT::f32,// ->46925
+/* 46893*/ OPC_Scope, 9, /*->46904*/ // 3 children in Scope
+/* 46895*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 46897*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 46904*/ /*Scope*/ 9, /*->46914*/
+/* 46905*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 46907*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 46914*/ /*Scope*/ 9, /*->46924*/
+/* 46915*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 46917*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1_MMR6), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
+/* 46924*/ 0, /*End of Scope*/
+/* 46925*/ /*SwitchType*/ 13, MVT::v2i16,// ->46940
+/* 46927*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46929*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 46932*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
+/* 46940*/ /*SwitchType*/ 13, MVT::v4i8,// ->46955
+/* 46942*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 46944*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 46947*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
+/* 46955*/ 0, // EndSwitchType
+/* 46956*/ /*Scope*/ 13, /*->46970*/
+/* 46957*/ OPC_CheckChild0Type, MVT::i64,
+/* 46959*/ OPC_CheckType, MVT::f64,
+/* 46961*/ OPC_CheckPatternPredicate, 97, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 46963*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMTC1), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
+/* 46970*/ /*Scope*/ 36|128,2/*292*/, /*->47264*/
+/* 46972*/ OPC_CheckChild0Type, MVT::v8f16,
+/* 46974*/ OPC_SwitchType /*6 cases */, 13, MVT::v8i16,// ->46990
+/* 46977*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 46979*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 46982*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
+/* 46990*/ /*SwitchType*/ 53, MVT::v16i8,// ->47045
+/* 46992*/ OPC_Scope, 13, /*->47007*/ // 2 children in Scope
+/* 46994*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 46996*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 46999*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
+/* 47007*/ /*Scope*/ 36, /*->47044*/
+/* 47008*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47010*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47013*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47021*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47025*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47033*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47036*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
+/* 47044*/ 0, /*End of Scope*/
+/* 47045*/ /*SwitchType*/ 53, MVT::v4i32,// ->47100
+/* 47047*/ OPC_Scope, 13, /*->47062*/ // 2 children in Scope
+/* 47049*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47051*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47054*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
+/* 47062*/ /*Scope*/ 36, /*->47099*/
+/* 47063*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47065*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47068*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47076*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47080*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47088*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47091*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 47099*/ 0, /*End of Scope*/
+/* 47100*/ /*SwitchType*/ 52, MVT::v2i64,// ->47154
+/* 47102*/ OPC_Scope, 13, /*->47117*/ // 2 children in Scope
+/* 47104*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47106*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47109*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
+/* 47117*/ /*Scope*/ 35, /*->47153*/
+/* 47118*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47120*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47123*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47131*/ OPC_EmitInteger, MVT::i32, 27,
+/* 47134*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47142*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47145*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 47153*/ 0, /*End of Scope*/
+/* 47154*/ /*SwitchType*/ 53, MVT::v4f32,// ->47209
+/* 47156*/ OPC_Scope, 13, /*->47171*/ // 2 children in Scope
+/* 47158*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47160*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47163*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
+/* 47171*/ /*Scope*/ 36, /*->47208*/
+/* 47172*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47174*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47177*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47185*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47189*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47197*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47200*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 47208*/ 0, /*End of Scope*/
+/* 47209*/ /*SwitchType*/ 52, MVT::v2f64,// ->47263
+/* 47211*/ OPC_Scope, 13, /*->47226*/ // 2 children in Scope
+/* 47213*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47215*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47218*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
+/* 47226*/ /*Scope*/ 35, /*->47262*/
+/* 47227*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47229*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47232*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47240*/ OPC_EmitInteger, MVT::i32, 27,
+/* 47243*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47251*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47254*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 47262*/ 0, /*End of Scope*/
+/* 47263*/ 0, // EndSwitchType
+/* 47264*/ /*Scope*/ 20|128,2/*276*/, /*->47542*/
+/* 47266*/ OPC_CheckChild0Type, MVT::v4f32,
+/* 47268*/ OPC_SwitchType /*6 cases */, 13, MVT::v4i32,// ->47284
+/* 47271*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 47273*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47276*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
+/* 47284*/ /*SwitchType*/ 52, MVT::v16i8,// ->47338
+/* 47286*/ OPC_Scope, 13, /*->47301*/ // 2 children in Scope
+/* 47288*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47290*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47293*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
+/* 47301*/ /*Scope*/ 35, /*->47337*/
+/* 47302*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47304*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47307*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47315*/ OPC_EmitInteger, MVT::i32, 27,
+/* 47318*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47326*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47329*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
+/* 47337*/ 0, /*End of Scope*/
+/* 47338*/ /*SwitchType*/ 53, MVT::v8i16,// ->47393
+/* 47340*/ OPC_Scope, 13, /*->47355*/ // 2 children in Scope
+/* 47342*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47344*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47347*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
+/* 47355*/ /*Scope*/ 36, /*->47392*/
+/* 47356*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47358*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47361*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47369*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47373*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47381*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47384*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 47392*/ 0, /*End of Scope*/
+/* 47393*/ /*SwitchType*/ 53, MVT::v2i64,// ->47448
+/* 47395*/ OPC_Scope, 13, /*->47410*/ // 2 children in Scope
+/* 47397*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47399*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47402*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
+/* 47410*/ /*Scope*/ 36, /*->47447*/
+/* 47411*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47413*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47416*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47424*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47428*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47436*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47439*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 47447*/ 0, /*End of Scope*/
+/* 47448*/ /*SwitchType*/ 53, MVT::v2f64,// ->47503
+/* 47450*/ OPC_Scope, 13, /*->47465*/ // 2 children in Scope
+/* 47452*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47454*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47457*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
+/* 47465*/ /*Scope*/ 36, /*->47502*/
+/* 47466*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47468*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47471*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47479*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47483*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47491*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47494*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 47502*/ 0, /*End of Scope*/
+/* 47503*/ /*SwitchType*/ 36, MVT::v8f16,// ->47541
+/* 47505*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47507*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47510*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47518*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47522*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47530*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47533*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8f16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 47541*/ 0, // EndSwitchType
+/* 47542*/ /*Scope*/ 41|128,2/*297*/, /*->47841*/
+/* 47544*/ OPC_CheckChild0Type, MVT::v2f64,
+/* 47546*/ OPC_SwitchType /*6 cases */, 13, MVT::v2i64,// ->47562
+/* 47549*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 47551*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47554*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
+/* 47562*/ /*SwitchType*/ 75, MVT::v16i8,// ->47639
+/* 47564*/ OPC_Scope, 13, /*->47579*/ // 2 children in Scope
+/* 47566*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47568*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47571*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
+/* 47579*/ /*Scope*/ 58, /*->47638*/
+/* 47580*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47582*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47585*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47593*/ OPC_EmitInteger, MVT::i32, 27,
+/* 47596*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47604*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47607*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 47615*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47619*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 47627*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47630*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 8, 9,
+ // Src: (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
+/* 47638*/ 0, /*End of Scope*/
+/* 47639*/ /*SwitchType*/ 52, MVT::v8i16,// ->47693
+/* 47641*/ OPC_Scope, 13, /*->47656*/ // 2 children in Scope
+/* 47643*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47645*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47648*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
+/* 47656*/ /*Scope*/ 35, /*->47692*/
+/* 47657*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47659*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47662*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47670*/ OPC_EmitInteger, MVT::i32, 27,
+/* 47673*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47681*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47684*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 47692*/ 0, /*End of Scope*/
+/* 47693*/ /*SwitchType*/ 53, MVT::v4i32,// ->47748
+/* 47695*/ OPC_Scope, 13, /*->47710*/ // 2 children in Scope
+/* 47697*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47699*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47702*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
+/* 47710*/ /*Scope*/ 36, /*->47747*/
+/* 47711*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47713*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47716*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47724*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47728*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47736*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47739*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 47747*/ 0, /*End of Scope*/
+/* 47748*/ /*SwitchType*/ 53, MVT::v4f32,// ->47803
+/* 47750*/ OPC_Scope, 13, /*->47765*/ // 2 children in Scope
+/* 47752*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47754*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47757*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
+/* 47765*/ /*Scope*/ 36, /*->47802*/
+/* 47766*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47768*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47771*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47779*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47783*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47791*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47794*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 47802*/ 0, /*End of Scope*/
+/* 47803*/ /*SwitchType*/ 35, MVT::v8f16,// ->47840
+/* 47805*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47807*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47810*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47818*/ OPC_EmitInteger, MVT::i32, 27,
+/* 47821*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47829*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47832*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8f16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 47840*/ 0, // EndSwitchType
+/* 47841*/ /*Scope*/ 36|128,2/*292*/, /*->48135*/
+/* 47843*/ OPC_CheckChild0Type, MVT::v8i16,
+/* 47845*/ OPC_SwitchType /*6 cases */, 53, MVT::v16i8,// ->47901
+/* 47848*/ OPC_Scope, 13, /*->47863*/ // 2 children in Scope
+/* 47850*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47852*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47855*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
+/* 47863*/ /*Scope*/ 36, /*->47900*/
+/* 47864*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47866*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47869*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47877*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47881*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47889*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 47892*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
+/* 47900*/ 0, /*End of Scope*/
+/* 47901*/ /*SwitchType*/ 53, MVT::v4i32,// ->47956
+/* 47903*/ OPC_Scope, 13, /*->47918*/ // 2 children in Scope
+/* 47905*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47907*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47910*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
+/* 47918*/ /*Scope*/ 36, /*->47955*/
+/* 47919*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47921*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47924*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47932*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 47936*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47944*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 47947*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 47955*/ 0, /*End of Scope*/
+/* 47956*/ /*SwitchType*/ 52, MVT::v2i64,// ->48010
+/* 47958*/ OPC_Scope, 13, /*->47973*/ // 2 children in Scope
+/* 47960*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 47962*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 47965*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
+/* 47973*/ /*Scope*/ 35, /*->48009*/
+/* 47974*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 47976*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 47979*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 47987*/ OPC_EmitInteger, MVT::i32, 27,
+/* 47990*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 47998*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48001*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 48009*/ 0, /*End of Scope*/
+/* 48010*/ /*SwitchType*/ 13, MVT::v8f16,// ->48025
+/* 48012*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 48014*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48017*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8f16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
+/* 48025*/ /*SwitchType*/ 53, MVT::v4f32,// ->48080
+/* 48027*/ OPC_Scope, 13, /*->48042*/ // 2 children in Scope
+/* 48029*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48031*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48034*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
+/* 48042*/ /*Scope*/ 36, /*->48079*/
+/* 48043*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48045*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48048*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48056*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48060*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48068*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48071*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 48079*/ 0, /*End of Scope*/
+/* 48080*/ /*SwitchType*/ 52, MVT::v2f64,// ->48134
+/* 48082*/ OPC_Scope, 13, /*->48097*/ // 2 children in Scope
+/* 48084*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48086*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48089*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
+/* 48097*/ /*Scope*/ 35, /*->48133*/
+/* 48098*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48100*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48103*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48111*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48114*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48122*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48125*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 48133*/ 0, /*End of Scope*/
+/* 48134*/ 0, // EndSwitchType
+/* 48135*/ /*Scope*/ 20|128,2/*276*/, /*->48413*/
+/* 48137*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 48139*/ OPC_SwitchType /*6 cases */, 52, MVT::v16i8,// ->48194
+/* 48142*/ OPC_Scope, 13, /*->48157*/ // 2 children in Scope
+/* 48144*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48146*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48149*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
+/* 48157*/ /*Scope*/ 35, /*->48193*/
+/* 48158*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48160*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48163*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48171*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48174*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48182*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48185*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
+/* 48193*/ 0, /*End of Scope*/
+/* 48194*/ /*SwitchType*/ 53, MVT::v8i16,// ->48249
+/* 48196*/ OPC_Scope, 13, /*->48211*/ // 2 children in Scope
+/* 48198*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48200*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48203*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
+/* 48211*/ /*Scope*/ 36, /*->48248*/
+/* 48212*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48214*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48217*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48225*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48229*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48237*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48240*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 48248*/ 0, /*End of Scope*/
+/* 48249*/ /*SwitchType*/ 53, MVT::v2i64,// ->48304
+/* 48251*/ OPC_Scope, 13, /*->48266*/ // 2 children in Scope
+/* 48253*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48255*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48258*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
+/* 48266*/ /*Scope*/ 36, /*->48303*/
+/* 48267*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48269*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48272*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48280*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48284*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48292*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48295*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 48303*/ 0, /*End of Scope*/
+/* 48304*/ /*SwitchType*/ 13, MVT::v4f32,// ->48319
+/* 48306*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 48308*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48311*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
+/* 48319*/ /*SwitchType*/ 53, MVT::v2f64,// ->48374
+/* 48321*/ OPC_Scope, 13, /*->48336*/ // 2 children in Scope
+/* 48323*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48325*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48328*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
+/* 48336*/ /*Scope*/ 36, /*->48373*/
+/* 48337*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48339*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48342*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48350*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48354*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48362*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48365*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 48373*/ 0, /*End of Scope*/
+/* 48374*/ /*SwitchType*/ 36, MVT::v8f16,// ->48412
+/* 48376*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48378*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48381*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48389*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48393*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48401*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48404*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8f16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 48412*/ 0, // EndSwitchType
+/* 48413*/ /*Scope*/ 41|128,2/*297*/, /*->48712*/
+/* 48415*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 48417*/ OPC_SwitchType /*6 cases */, 75, MVT::v16i8,// ->48495
+/* 48420*/ OPC_Scope, 13, /*->48435*/ // 2 children in Scope
+/* 48422*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48424*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48427*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
+/* 48435*/ /*Scope*/ 58, /*->48494*/
+/* 48436*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48438*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48441*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48449*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48452*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48460*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48463*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 48471*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48475*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 48483*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48486*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 8, 9,
+ // Src: (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
+/* 48494*/ 0, /*End of Scope*/
+/* 48495*/ /*SwitchType*/ 52, MVT::v8i16,// ->48549
+/* 48497*/ OPC_Scope, 13, /*->48512*/ // 2 children in Scope
+/* 48499*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48501*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48504*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
+/* 48512*/ /*Scope*/ 35, /*->48548*/
+/* 48513*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48515*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48518*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48526*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48529*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48537*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48540*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 48548*/ 0, /*End of Scope*/
+/* 48549*/ /*SwitchType*/ 53, MVT::v4i32,// ->48604
+/* 48551*/ OPC_Scope, 13, /*->48566*/ // 2 children in Scope
+/* 48553*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48555*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48558*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
+/* 48566*/ /*Scope*/ 36, /*->48603*/
+/* 48567*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48569*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48572*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48580*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48584*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48592*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48595*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 48603*/ 0, /*End of Scope*/
+/* 48604*/ /*SwitchType*/ 13, MVT::v2f64,// ->48619
+/* 48606*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 48608*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48611*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
+/* 48619*/ /*SwitchType*/ 53, MVT::v4f32,// ->48674
+/* 48621*/ OPC_Scope, 13, /*->48636*/ // 2 children in Scope
+/* 48623*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48625*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48628*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
+/* 48636*/ /*Scope*/ 36, /*->48673*/
+/* 48637*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48639*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48642*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48650*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48654*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48662*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48665*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 48673*/ 0, /*End of Scope*/
+/* 48674*/ /*SwitchType*/ 35, MVT::v8f16,// ->48711
+/* 48676*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48678*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48681*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48689*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48692*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48700*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48703*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8f16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 48711*/ 0, // EndSwitchType
+/* 48712*/ /*Scope*/ 103|128,2/*359*/, /*->49073*/
+/* 48714*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 48716*/ OPC_SwitchType /*6 cases */, 53, MVT::v8i16,// ->48772
+/* 48719*/ OPC_Scope, 13, /*->48734*/ // 2 children in Scope
+/* 48721*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48723*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48726*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
+/* 48734*/ /*Scope*/ 36, /*->48771*/
+/* 48735*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48737*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48740*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48748*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48752*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48760*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 48763*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8i16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 48771*/ 0, /*End of Scope*/
+/* 48772*/ /*SwitchType*/ 52, MVT::v4i32,// ->48826
+/* 48774*/ OPC_Scope, 13, /*->48789*/ // 2 children in Scope
+/* 48776*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48778*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48781*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
+/* 48789*/ /*Scope*/ 35, /*->48825*/
+/* 48790*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48792*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48795*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48803*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48806*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48814*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48817*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 48825*/ 0, /*End of Scope*/
+/* 48826*/ /*SwitchType*/ 75, MVT::v2i64,// ->48903
+/* 48828*/ OPC_Scope, 13, /*->48843*/ // 2 children in Scope
+/* 48830*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48832*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48835*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
+/* 48843*/ /*Scope*/ 58, /*->48902*/
+/* 48844*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48846*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48849*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48857*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48860*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48868*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48871*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 48879*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 48883*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 48891*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48894*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i64, 2/*#Ops*/, 8, 9,
+ // Src: (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 48902*/ 0, /*End of Scope*/
+/* 48903*/ /*SwitchType*/ 52, MVT::v4f32,// ->48957
+/* 48905*/ OPC_Scope, 13, /*->48920*/ // 2 children in Scope
+/* 48907*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48909*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48912*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
+/* 48920*/ /*Scope*/ 35, /*->48956*/
+/* 48921*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48923*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48926*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48934*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48937*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48945*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 48948*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4f32, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
+/* 48956*/ 0, /*End of Scope*/
+/* 48957*/ /*SwitchType*/ 75, MVT::v2f64,// ->49034
+/* 48959*/ OPC_Scope, 13, /*->48974*/ // 2 children in Scope
+/* 48961*/ OPC_CheckPatternPredicate, 98, // (Subtarget->hasMSA()) && (Subtarget->isLittle())
+/* 48963*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 48966*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
+/* 48974*/ /*Scope*/ 58, /*->49033*/
+/* 48975*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 48977*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 48980*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 48988*/ OPC_EmitInteger, MVT::i32, 27,
+/* 48991*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 48999*/ OPC_EmitInteger, MVT::i32, Mips::MSA128WRegClassID,
+/* 49002*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 49010*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 49014*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 6, 7, // Results = #8
+/* 49022*/ OPC_EmitInteger, MVT::i32, Mips::MSA128DRegClassID,
+/* 49025*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2f64, 2/*#Ops*/, 8, 9,
+ // Src: (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+/* 49033*/ 0, /*End of Scope*/
+/* 49034*/ /*SwitchType*/ 36, MVT::v8f16,// ->49072
+/* 49036*/ OPC_CheckPatternPredicate, 99, // (Subtarget->hasMSA()) && (!Subtarget->isLittle())
+/* 49038*/ OPC_EmitInteger, MVT::i32, Mips::MSA128BRegClassID,
+/* 49041*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 49049*/ OPC_EmitInteger, MVT::i32, 49|128,1/*177*/,
+/* 49053*/ OPC_EmitNode1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 2, 3, // Results = #4
+/* 49061*/ OPC_EmitInteger, MVT::i32, Mips::MSA128HRegClassID,
+/* 49064*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v8f16, 2/*#Ops*/, 4, 5,
+ // Src: (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) - Complexity = 3
+ // Dst: (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+/* 49072*/ 0, // EndSwitchType
+/* 49073*/ 0, /*End of Scope*/
+/* 49074*/ /*SwitchOpcode*/ 69, TARGET_VAL(ISD::CTPOP),// ->49146
+/* 49077*/ OPC_RecordChild0, // #0 = $rs
+/* 49078*/ OPC_SwitchType /*6 cases */, 9, MVT::i32,// ->49090
+/* 49081*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 49083*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::POP), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 49090*/ /*SwitchType*/ 9, MVT::i64,// ->49101
+/* 49092*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasCnMips())
+/* 49094*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPOP), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
+/* 49101*/ /*SwitchType*/ 9, MVT::v16i8,// ->49112
+/* 49103*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 49105*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCNT_B), 0,
+ MVT::v16i8, 1/*#Ops*/, 0,
+ // Src: (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 3
+ // Dst: (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
+/* 49112*/ /*SwitchType*/ 9, MVT::v8i16,// ->49123
+/* 49114*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 49116*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCNT_H), 0,
+ MVT::v8i16, 1/*#Ops*/, 0,
+ // Src: (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 3
+ // Dst: (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
+/* 49123*/ /*SwitchType*/ 9, MVT::v4i32,// ->49134
+/* 49125*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 49127*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCNT_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 3
+ // Dst: (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+/* 49134*/ /*SwitchType*/ 9, MVT::v2i64,// ->49145
+/* 49136*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 49138*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCNT_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 3
+ // Dst: (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
+/* 49145*/ 0, // EndSwitchType
+/* 49146*/ /*SwitchOpcode*/ 50|128,1/*178*/, TARGET_VAL(MipsISD::CMovFP_T),// ->49328
+/* 49150*/ OPC_CaptureGlueInput,
+/* 49151*/ OPC_RecordChild0, // #0 = $rs
+/* 49152*/ OPC_RecordChild1, // #1 = $fcc
+/* 49153*/ OPC_RecordChild2, // #2 = $F
+/* 49154*/ OPC_SwitchType /*4 cases */, 38, MVT::i32,// ->49195
+/* 49157*/ OPC_Scope, 11, /*->49170*/ // 3 children in Scope
+/* 49159*/ OPC_CheckPatternPredicate, 100, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49161*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVT_I), 0|OPFL_GlueInput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_T:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR32Opnd:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (MOVT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR32Opnd:{ *:[i32] }:$F)
+/* 49170*/ /*Scope*/ 11, /*->49182*/
+/* 49171*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 49173*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVT_I_MM), 0|OPFL_GlueInput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_T:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR32Opnd:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (MOVT_I_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR32Opnd:{ *:[i32] }:$F)
+/* 49182*/ /*Scope*/ 11, /*->49194*/
+/* 49183*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 49185*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_T_I), 0|OPFL_GlueInput,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_T:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_T_I:{ *:[i32] } FCCRegsOpnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
+/* 49194*/ 0, /*End of Scope*/
+/* 49195*/ /*SwitchType*/ 26, MVT::i64,// ->49223
+/* 49197*/ OPC_Scope, 11, /*->49210*/ // 2 children in Scope
+/* 49199*/ OPC_CheckPatternPredicate, 101, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49201*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVT_I64), 0|OPFL_GlueInput,
+ MVT::i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_T:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR64Opnd:{ *:[i64] }:$F) - Complexity = 3
+ // Dst: (MOVT_I64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR64Opnd:{ *:[i64] }:$F)
+/* 49210*/ /*Scope*/ 11, /*->49222*/
+/* 49211*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 49213*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_T_I64), 0|OPFL_GlueInput,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_T:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_T_I64:{ *:[i64] } FCCRegsOpnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
+/* 49222*/ 0, /*End of Scope*/
+/* 49223*/ /*SwitchType*/ 38, MVT::f32,// ->49263
+/* 49225*/ OPC_Scope, 11, /*->49238*/ // 3 children in Scope
+/* 49227*/ OPC_CheckPatternPredicate, 100, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49229*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVT_S), 0|OPFL_GlueInput,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_T:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR32Opnd:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (MOVT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR32Opnd:{ *:[f32] }:$F)
+/* 49238*/ /*Scope*/ 11, /*->49250*/
+/* 49239*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 49241*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVT_S_MM), 0|OPFL_GlueInput,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_T:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR32Opnd:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (MOVT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR32Opnd:{ *:[f32] }:$F)
+/* 49250*/ /*Scope*/ 11, /*->49262*/
+/* 49251*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 49253*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_T_S), 0|OPFL_GlueInput,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_T:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_T_S:{ *:[f32] } FCCRegsOpnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
+/* 49262*/ 0, /*End of Scope*/
+/* 49263*/ /*SwitchType*/ 62, MVT::f64,// ->49327
+/* 49265*/ OPC_Scope, 11, /*->49278*/ // 5 children in Scope
+/* 49267*/ OPC_CheckPatternPredicate, 102, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49269*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVT_D32), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_T:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, AFGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, AFGR64Opnd:{ *:[f64] }:$F)
+/* 49278*/ /*Scope*/ 11, /*->49290*/
+/* 49279*/ OPC_CheckPatternPredicate, 103, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49281*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVT_D64), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_T:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR64Opnd:{ *:[f64] }:$F)
+/* 49290*/ /*Scope*/ 11, /*->49302*/
+/* 49291*/ OPC_CheckPatternPredicate, 104, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 49293*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVT_D32_MM), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_T:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, AFGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, AFGR64Opnd:{ *:[f64] }:$F)
+/* 49302*/ /*Scope*/ 11, /*->49314*/
+/* 49303*/ OPC_CheckPatternPredicate, 41, // (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips4_32())
+/* 49305*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_T_D32), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_T:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_T_D32:{ *:[f64] } FCCRegsOpnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
+/* 49314*/ /*Scope*/ 11, /*->49326*/
+/* 49315*/ OPC_CheckPatternPredicate, 42, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips4_32())
+/* 49317*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_T_D64), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_T:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_T_D64:{ *:[f64] } FCCRegsOpnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
+/* 49326*/ 0, /*End of Scope*/
+/* 49327*/ 0, // EndSwitchType
+/* 49328*/ /*SwitchOpcode*/ 50|128,1/*178*/, TARGET_VAL(MipsISD::CMovFP_F),// ->49510
+/* 49332*/ OPC_CaptureGlueInput,
+/* 49333*/ OPC_RecordChild0, // #0 = $rs
+/* 49334*/ OPC_RecordChild1, // #1 = $fcc
+/* 49335*/ OPC_RecordChild2, // #2 = $F
+/* 49336*/ OPC_SwitchType /*4 cases */, 38, MVT::i32,// ->49377
+/* 49339*/ OPC_Scope, 11, /*->49352*/ // 3 children in Scope
+/* 49341*/ OPC_CheckPatternPredicate, 100, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49343*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVF_I), 0|OPFL_GlueInput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_F:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR32Opnd:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (MOVF_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR32Opnd:{ *:[i32] }:$F)
+/* 49352*/ /*Scope*/ 11, /*->49364*/
+/* 49353*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 49355*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVF_I_MM), 0|OPFL_GlueInput,
+ MVT::i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_F:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR32Opnd:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (MOVF_I_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR32Opnd:{ *:[i32] }:$F)
+/* 49364*/ /*Scope*/ 11, /*->49376*/
+/* 49365*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 49367*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_F_I), 0|OPFL_GlueInput,
+ MVT::i32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_F:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_F_I:{ *:[i32] } FCCRegsOpnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
+/* 49376*/ 0, /*End of Scope*/
+/* 49377*/ /*SwitchType*/ 26, MVT::i64,// ->49405
+/* 49379*/ OPC_Scope, 11, /*->49392*/ // 2 children in Scope
+/* 49381*/ OPC_CheckPatternPredicate, 101, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49383*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVF_I64), 0|OPFL_GlueInput,
+ MVT::i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_F:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR64Opnd:{ *:[i64] }:$F) - Complexity = 3
+ // Dst: (MOVF_I64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, FCCRegsOpnd:{ *:[i32] }:$fcc, GPR64Opnd:{ *:[i64] }:$F)
+/* 49392*/ /*Scope*/ 11, /*->49404*/
+/* 49393*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 49395*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_F_I64), 0|OPFL_GlueInput,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_F:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_F_I64:{ *:[i64] } FCCRegsOpnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
+/* 49404*/ 0, /*End of Scope*/
+/* 49405*/ /*SwitchType*/ 38, MVT::f32,// ->49445
+/* 49407*/ OPC_Scope, 11, /*->49420*/ // 3 children in Scope
+/* 49409*/ OPC_CheckPatternPredicate, 100, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49411*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVF_S), 0|OPFL_GlueInput,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_F:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR32Opnd:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (MOVF_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR32Opnd:{ *:[f32] }:$F)
+/* 49420*/ /*Scope*/ 11, /*->49432*/
+/* 49421*/ OPC_CheckPatternPredicate, 9, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6())
+/* 49423*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVF_S_MM), 0|OPFL_GlueInput,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_F:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR32Opnd:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (MOVF_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR32Opnd:{ *:[f32] }:$F)
+/* 49432*/ /*Scope*/ 11, /*->49444*/
+/* 49433*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32())
+/* 49435*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_F_S), 0|OPFL_GlueInput,
+ MVT::f32, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_F:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_F_S:{ *:[f32] } FCCRegsOpnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
+/* 49444*/ 0, /*End of Scope*/
+/* 49445*/ /*SwitchType*/ 62, MVT::f64,// ->49509
+/* 49447*/ OPC_Scope, 11, /*->49460*/ // 5 children in Scope
+/* 49449*/ OPC_CheckPatternPredicate, 102, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49451*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVF_D32), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_F:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, AFGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVF_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, AFGR64Opnd:{ *:[f64] }:$F)
+/* 49460*/ /*Scope*/ 11, /*->49472*/
+/* 49461*/ OPC_CheckPatternPredicate, 103, // (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 49463*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVF_D64), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_F:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVF_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, FGR64Opnd:{ *:[f64] }:$F)
+/* 49472*/ /*Scope*/ 11, /*->49484*/
+/* 49473*/ OPC_CheckPatternPredicate, 104, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 49475*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOVF_D32_MM), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsCMovFP_F:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, AFGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (MOVF_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, FCCRegsOpnd:{ *:[i32] }:$fcc, AFGR64Opnd:{ *:[f64] }:$F)
+/* 49484*/ /*Scope*/ 11, /*->49496*/
+/* 49485*/ OPC_CheckPatternPredicate, 41, // (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips4_32())
+/* 49487*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_F_D32), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_F:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_F_D32:{ *:[f64] } FCCRegsOpnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
+/* 49496*/ /*Scope*/ 11, /*->49508*/
+/* 49497*/ OPC_CheckPatternPredicate, 42, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips4_32())
+/* 49499*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSELECTFP_F_D64), 0|OPFL_GlueInput,
+ MVT::f64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (MipsCMovFP_F:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$T, FCCRegsOpnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$F) - Complexity = 3
+ // Dst: (PseudoSELECTFP_F_D64:{ *:[f64] } FCCRegsOpnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
+/* 49508*/ 0, /*End of Scope*/
+/* 49509*/ 0, // EndSwitchType
+/* 49510*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MULHS),// ->49555
+/* 49513*/ OPC_RecordChild0, // #0 = $rs
+/* 49514*/ OPC_RecordChild1, // #1 = $rt
+/* 49515*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->49542
+/* 49518*/ OPC_Scope, 10, /*->49530*/ // 2 children in Scope
+/* 49520*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 49522*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUH), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 49530*/ /*Scope*/ 10, /*->49541*/
+/* 49531*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 49533*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUH_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 49541*/ 0, /*End of Scope*/
+/* 49542*/ /*SwitchType*/ 10, MVT::i64,// ->49554
+/* 49544*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 49546*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMUH), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 49554*/ 0, // EndSwitchType
+/* 49555*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MULHU),// ->49600
+/* 49558*/ OPC_RecordChild0, // #0 = $rs
+/* 49559*/ OPC_RecordChild1, // #1 = $rt
+/* 49560*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->49587
+/* 49563*/ OPC_Scope, 10, /*->49575*/ // 2 children in Scope
+/* 49565*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 49567*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUHU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 49575*/ /*Scope*/ 10, /*->49586*/
+/* 49576*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 49578*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUHU_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 49586*/ 0, /*End of Scope*/
+/* 49587*/ /*SwitchType*/ 10, MVT::i64,// ->49599
+/* 49589*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 49591*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMUHU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 49599*/ 0, // EndSwitchType
+/* 49600*/ /*SwitchOpcode*/ 14, TARGET_VAL(MipsISD::DivRem16),// ->49617
+/* 49603*/ OPC_RecordChild0, // #0 = $rx
+/* 49604*/ OPC_CheckChild0Type, MVT::i32,
+/* 49606*/ OPC_RecordChild1, // #1 = $ry
+/* 49607*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 49609*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DivRxRy16), 0|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsDivRem16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry) - Complexity = 3
+ // Dst: (DivRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
+/* 49617*/ /*SwitchOpcode*/ 14, TARGET_VAL(MipsISD::DivRemU16),// ->49634
+/* 49620*/ OPC_RecordChild0, // #0 = $rx
+/* 49621*/ OPC_CheckChild0Type, MVT::i32,
+/* 49623*/ OPC_RecordChild1, // #1 = $ry
+/* 49624*/ OPC_CheckPatternPredicate, 14, // (Subtarget->inMips16Mode())
+/* 49626*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DivuRxRy16), 0|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsDivRemU16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry) - Complexity = 3
+ // Dst: (DivuRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
+/* 49634*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::MULSAQ_S_W_PH),// ->49669
+/* 49637*/ OPC_RecordNode, // #0 = 'MipsMULSAQ_S_W_PH' chained node
+/* 49638*/ OPC_RecordChild1, // #1 = $rs
+/* 49639*/ OPC_RecordChild2, // #2 = $rt
+/* 49640*/ OPC_RecordChild3, // #3 = $acin
+/* 49641*/ OPC_Scope, 12, /*->49655*/ // 2 children in Scope
+/* 49643*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49645*/ OPC_EmitMergeInputChains1_0,
+/* 49646*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULSAQ_S_W_PH), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMULSAQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MULSAQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49655*/ /*Scope*/ 12, /*->49668*/
+/* 49656*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49658*/ OPC_EmitMergeInputChains1_0,
+/* 49659*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULSAQ_S_W_PH_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMULSAQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MULSAQ_S_W_PH_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49668*/ 0, /*End of Scope*/
+/* 49669*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::MAQ_S_W_PHL),// ->49704
+/* 49672*/ OPC_RecordNode, // #0 = 'MipsMAQ_S_W_PHL' chained node
+/* 49673*/ OPC_RecordChild1, // #1 = $rs
+/* 49674*/ OPC_RecordChild2, // #2 = $rt
+/* 49675*/ OPC_RecordChild3, // #3 = $acin
+/* 49676*/ OPC_Scope, 12, /*->49690*/ // 2 children in Scope
+/* 49678*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49680*/ OPC_EmitMergeInputChains1_0,
+/* 49681*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_S_W_PHL), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMAQ_S_W_PHL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MAQ_S_W_PHL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49690*/ /*Scope*/ 12, /*->49703*/
+/* 49691*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49693*/ OPC_EmitMergeInputChains1_0,
+/* 49694*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_S_W_PHL_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMAQ_S_W_PHL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MAQ_S_W_PHL_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49703*/ 0, /*End of Scope*/
+/* 49704*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::MAQ_S_W_PHR),// ->49739
+/* 49707*/ OPC_RecordNode, // #0 = 'MipsMAQ_S_W_PHR' chained node
+/* 49708*/ OPC_RecordChild1, // #1 = $rs
+/* 49709*/ OPC_RecordChild2, // #2 = $rt
+/* 49710*/ OPC_RecordChild3, // #3 = $acin
+/* 49711*/ OPC_Scope, 12, /*->49725*/ // 2 children in Scope
+/* 49713*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49715*/ OPC_EmitMergeInputChains1_0,
+/* 49716*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_S_W_PHR), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMAQ_S_W_PHR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MAQ_S_W_PHR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49725*/ /*Scope*/ 12, /*->49738*/
+/* 49726*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49728*/ OPC_EmitMergeInputChains1_0,
+/* 49729*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_S_W_PHR_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMAQ_S_W_PHR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MAQ_S_W_PHR_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49738*/ 0, /*End of Scope*/
+/* 49739*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::MAQ_SA_W_PHL),// ->49774
+/* 49742*/ OPC_RecordNode, // #0 = 'MipsMAQ_SA_W_PHL' chained node
+/* 49743*/ OPC_RecordChild1, // #1 = $rs
+/* 49744*/ OPC_RecordChild2, // #2 = $rt
+/* 49745*/ OPC_RecordChild3, // #3 = $acin
+/* 49746*/ OPC_Scope, 12, /*->49760*/ // 2 children in Scope
+/* 49748*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49750*/ OPC_EmitMergeInputChains1_0,
+/* 49751*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_SA_W_PHL), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMAQ_SA_W_PHL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MAQ_SA_W_PHL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49760*/ /*Scope*/ 12, /*->49773*/
+/* 49761*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49763*/ OPC_EmitMergeInputChains1_0,
+/* 49764*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_SA_W_PHL_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMAQ_SA_W_PHL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MAQ_SA_W_PHL_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49773*/ 0, /*End of Scope*/
+/* 49774*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::MAQ_SA_W_PHR),// ->49809
+/* 49777*/ OPC_RecordNode, // #0 = 'MipsMAQ_SA_W_PHR' chained node
+/* 49778*/ OPC_RecordChild1, // #1 = $rs
+/* 49779*/ OPC_RecordChild2, // #2 = $rt
+/* 49780*/ OPC_RecordChild3, // #3 = $acin
+/* 49781*/ OPC_Scope, 12, /*->49795*/ // 2 children in Scope
+/* 49783*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49785*/ OPC_EmitMergeInputChains1_0,
+/* 49786*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_SA_W_PHR), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMAQ_SA_W_PHR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MAQ_SA_W_PHR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49795*/ /*Scope*/ 12, /*->49808*/
+/* 49796*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49798*/ OPC_EmitMergeInputChains1_0,
+/* 49799*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAQ_SA_W_PHR_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsMAQ_SA_W_PHR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MAQ_SA_W_PHR_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49808*/ 0, /*End of Scope*/
+/* 49809*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPAU_H_QBL),// ->49841
+/* 49812*/ OPC_RecordChild0, // #0 = $rs
+/* 49813*/ OPC_RecordChild1, // #1 = $rt
+/* 49814*/ OPC_RecordChild2, // #2 = $acin
+/* 49815*/ OPC_Scope, 11, /*->49828*/ // 2 children in Scope
+/* 49817*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49819*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAU_H_QBL), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPAU_H_QBL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAU_H_QBL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49828*/ /*Scope*/ 11, /*->49840*/
+/* 49829*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49831*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAU_H_QBL_MM), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPAU_H_QBL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAU_H_QBL_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49840*/ 0, /*End of Scope*/
+/* 49841*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPAU_H_QBR),// ->49873
+/* 49844*/ OPC_RecordChild0, // #0 = $rs
+/* 49845*/ OPC_RecordChild1, // #1 = $rt
+/* 49846*/ OPC_RecordChild2, // #2 = $acin
+/* 49847*/ OPC_Scope, 11, /*->49860*/ // 2 children in Scope
+/* 49849*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49851*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAU_H_QBR), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPAU_H_QBR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAU_H_QBR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49860*/ /*Scope*/ 11, /*->49872*/
+/* 49861*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49863*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAU_H_QBR_MM), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPAU_H_QBR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAU_H_QBR_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49872*/ 0, /*End of Scope*/
+/* 49873*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPSU_H_QBL),// ->49905
+/* 49876*/ OPC_RecordChild0, // #0 = $rs
+/* 49877*/ OPC_RecordChild1, // #1 = $rt
+/* 49878*/ OPC_RecordChild2, // #2 = $acin
+/* 49879*/ OPC_Scope, 11, /*->49892*/ // 2 children in Scope
+/* 49881*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49883*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSU_H_QBL), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPSU_H_QBL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSU_H_QBL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49892*/ /*Scope*/ 11, /*->49904*/
+/* 49893*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49895*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSU_H_QBL_MM), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPSU_H_QBL:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSU_H_QBL_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49904*/ 0, /*End of Scope*/
+/* 49905*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPSU_H_QBR),// ->49937
+/* 49908*/ OPC_RecordChild0, // #0 = $rs
+/* 49909*/ OPC_RecordChild1, // #1 = $rt
+/* 49910*/ OPC_RecordChild2, // #2 = $acin
+/* 49911*/ OPC_Scope, 11, /*->49924*/ // 2 children in Scope
+/* 49913*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49915*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSU_H_QBR), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPSU_H_QBR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSU_H_QBR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49924*/ /*Scope*/ 11, /*->49936*/
+/* 49925*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49927*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSU_H_QBR_MM), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPSU_H_QBR:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSU_H_QBR_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49936*/ 0, /*End of Scope*/
+/* 49937*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPAQ_S_W_PH),// ->49972
+/* 49940*/ OPC_RecordNode, // #0 = 'MipsDPAQ_S_W_PH' chained node
+/* 49941*/ OPC_RecordChild1, // #1 = $rs
+/* 49942*/ OPC_RecordChild2, // #2 = $rt
+/* 49943*/ OPC_RecordChild3, // #3 = $acin
+/* 49944*/ OPC_Scope, 12, /*->49958*/ // 2 children in Scope
+/* 49946*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49948*/ OPC_EmitMergeInputChains1_0,
+/* 49949*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAQ_S_W_PH), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPAQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49958*/ /*Scope*/ 12, /*->49971*/
+/* 49959*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49961*/ OPC_EmitMergeInputChains1_0,
+/* 49962*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAQ_S_W_PH_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPAQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAQ_S_W_PH_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49971*/ 0, /*End of Scope*/
+/* 49972*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPSQ_S_W_PH),// ->50007
+/* 49975*/ OPC_RecordNode, // #0 = 'MipsDPSQ_S_W_PH' chained node
+/* 49976*/ OPC_RecordChild1, // #1 = $rs
+/* 49977*/ OPC_RecordChild2, // #2 = $rt
+/* 49978*/ OPC_RecordChild3, // #3 = $acin
+/* 49979*/ OPC_Scope, 12, /*->49993*/ // 2 children in Scope
+/* 49981*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 49983*/ OPC_EmitMergeInputChains1_0,
+/* 49984*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQ_S_W_PH), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPSQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 49993*/ /*Scope*/ 12, /*->50006*/
+/* 49994*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 49996*/ OPC_EmitMergeInputChains1_0,
+/* 49997*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQ_S_W_PH_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPSQ_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSQ_S_W_PH_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50006*/ 0, /*End of Scope*/
+/* 50007*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPAQ_SA_L_W),// ->50042
+/* 50010*/ OPC_RecordNode, // #0 = 'MipsDPAQ_SA_L_W' chained node
+/* 50011*/ OPC_RecordChild1, // #1 = $rs
+/* 50012*/ OPC_RecordChild2, // #2 = $rt
+/* 50013*/ OPC_RecordChild3, // #3 = $acin
+/* 50014*/ OPC_Scope, 12, /*->50028*/ // 2 children in Scope
+/* 50016*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 50018*/ OPC_EmitMergeInputChains1_0,
+/* 50019*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAQ_SA_L_W), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPAQ_SA_L_W:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAQ_SA_L_W:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50028*/ /*Scope*/ 12, /*->50041*/
+/* 50029*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 50031*/ OPC_EmitMergeInputChains1_0,
+/* 50032*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAQ_SA_L_W_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPAQ_SA_L_W:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAQ_SA_L_W_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50041*/ 0, /*End of Scope*/
+/* 50042*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPSQ_SA_L_W),// ->50077
+/* 50045*/ OPC_RecordNode, // #0 = 'MipsDPSQ_SA_L_W' chained node
+/* 50046*/ OPC_RecordChild1, // #1 = $rs
+/* 50047*/ OPC_RecordChild2, // #2 = $rt
+/* 50048*/ OPC_RecordChild3, // #3 = $acin
+/* 50049*/ OPC_Scope, 12, /*->50063*/ // 2 children in Scope
+/* 50051*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 50053*/ OPC_EmitMergeInputChains1_0,
+/* 50054*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQ_SA_L_W), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPSQ_SA_L_W:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSQ_SA_L_W:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50063*/ /*Scope*/ 12, /*->50076*/
+/* 50064*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 50066*/ OPC_EmitMergeInputChains1_0,
+/* 50067*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQ_SA_L_W_MM), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPSQ_SA_L_W:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSQ_SA_L_W_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50076*/ 0, /*End of Scope*/
+/* 50077*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::MTHLIP),// ->50109
+/* 50080*/ OPC_RecordNode, // #0 = 'MipsMTHLIP' chained node
+/* 50081*/ OPC_RecordChild1, // #1 = $rs
+/* 50082*/ OPC_RecordChild2, // #2 = $acin
+/* 50083*/ OPC_Scope, 11, /*->50096*/ // 2 children in Scope
+/* 50085*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 50087*/ OPC_EmitMergeInputChains1_0,
+/* 50088*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTHLIP), 0|OPFL_Chain,
+ MVT::Untyped, 2/*#Ops*/, 1, 2,
+ // Src: (MipsMTHLIP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MTHLIP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50096*/ /*Scope*/ 11, /*->50108*/
+/* 50097*/ OPC_CheckPatternPredicate, 45, // (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())
+/* 50099*/ OPC_EmitMergeInputChains1_0,
+/* 50100*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTHLIP_MM), 0|OPFL_Chain,
+ MVT::Untyped, 2/*#Ops*/, 1, 2,
+ // Src: (MipsMTHLIP:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MTHLIP_MM:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50108*/ 0, /*End of Scope*/
+/* 50109*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPA_W_PH),// ->50141
+/* 50112*/ OPC_RecordChild0, // #0 = $rs
+/* 50113*/ OPC_RecordChild1, // #1 = $rt
+/* 50114*/ OPC_RecordChild2, // #2 = $acin
+/* 50115*/ OPC_Scope, 11, /*->50128*/ // 2 children in Scope
+/* 50117*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50119*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPA_W_PH), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50128*/ /*Scope*/ 11, /*->50140*/
+/* 50129*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50131*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPA_W_PH_MMR2), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPA_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50140*/ 0, /*End of Scope*/
+/* 50141*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPS_W_PH),// ->50173
+/* 50144*/ OPC_RecordChild0, // #0 = $rs
+/* 50145*/ OPC_RecordChild1, // #1 = $rt
+/* 50146*/ OPC_RecordChild2, // #2 = $acin
+/* 50147*/ OPC_Scope, 11, /*->50160*/ // 2 children in Scope
+/* 50149*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50151*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPS_W_PH), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPS_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPS_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50160*/ /*Scope*/ 11, /*->50172*/
+/* 50161*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50163*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPS_W_PH_MMR2), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPS_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPS_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50172*/ 0, /*End of Scope*/
+/* 50173*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPAQX_S_W_PH),// ->50208
+/* 50176*/ OPC_RecordNode, // #0 = 'MipsDPAQX_S_W_PH' chained node
+/* 50177*/ OPC_RecordChild1, // #1 = $rs
+/* 50178*/ OPC_RecordChild2, // #2 = $rt
+/* 50179*/ OPC_RecordChild3, // #3 = $acin
+/* 50180*/ OPC_Scope, 12, /*->50194*/ // 2 children in Scope
+/* 50182*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50184*/ OPC_EmitMergeInputChains1_0,
+/* 50185*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAQX_S_W_PH), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPAQX_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAQX_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50194*/ /*Scope*/ 12, /*->50207*/
+/* 50195*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50197*/ OPC_EmitMergeInputChains1_0,
+/* 50198*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAQX_S_W_PH_MMR2), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPAQX_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAQX_S_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50207*/ 0, /*End of Scope*/
+/* 50208*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPAQX_SA_W_PH),// ->50243
+/* 50211*/ OPC_RecordNode, // #0 = 'MipsDPAQX_SA_W_PH' chained node
+/* 50212*/ OPC_RecordChild1, // #1 = $rs
+/* 50213*/ OPC_RecordChild2, // #2 = $rt
+/* 50214*/ OPC_RecordChild3, // #3 = $acin
+/* 50215*/ OPC_Scope, 12, /*->50229*/ // 2 children in Scope
+/* 50217*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50219*/ OPC_EmitMergeInputChains1_0,
+/* 50220*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAQX_SA_W_PH), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPAQX_SA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAQX_SA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50229*/ /*Scope*/ 12, /*->50242*/
+/* 50230*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50232*/ OPC_EmitMergeInputChains1_0,
+/* 50233*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAQX_SA_W_PH_MMR2), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPAQX_SA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAQX_SA_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50242*/ 0, /*End of Scope*/
+/* 50243*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPAX_W_PH),// ->50275
+/* 50246*/ OPC_RecordChild0, // #0 = $rs
+/* 50247*/ OPC_RecordChild1, // #1 = $rt
+/* 50248*/ OPC_RecordChild2, // #2 = $acin
+/* 50249*/ OPC_Scope, 11, /*->50262*/ // 2 children in Scope
+/* 50251*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50253*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAX_W_PH), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPAX_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAX_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50262*/ /*Scope*/ 11, /*->50274*/
+/* 50263*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50265*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPAX_W_PH_MMR2), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPAX_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPAX_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50274*/ 0, /*End of Scope*/
+/* 50275*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::DPSX_W_PH),// ->50307
+/* 50278*/ OPC_RecordChild0, // #0 = $rs
+/* 50279*/ OPC_RecordChild1, // #1 = $rt
+/* 50280*/ OPC_RecordChild2, // #2 = $acin
+/* 50281*/ OPC_Scope, 11, /*->50294*/ // 2 children in Scope
+/* 50283*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50285*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSX_W_PH), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPSX_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSX_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50294*/ /*Scope*/ 11, /*->50306*/
+/* 50295*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50297*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSX_W_PH_MMR2), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsDPSX_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSX_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50306*/ 0, /*End of Scope*/
+/* 50307*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPSQX_S_W_PH),// ->50342
+/* 50310*/ OPC_RecordNode, // #0 = 'MipsDPSQX_S_W_PH' chained node
+/* 50311*/ OPC_RecordChild1, // #1 = $rs
+/* 50312*/ OPC_RecordChild2, // #2 = $rt
+/* 50313*/ OPC_RecordChild3, // #3 = $acin
+/* 50314*/ OPC_Scope, 12, /*->50328*/ // 2 children in Scope
+/* 50316*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50318*/ OPC_EmitMergeInputChains1_0,
+/* 50319*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQX_S_W_PH), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPSQX_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSQX_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50328*/ /*Scope*/ 12, /*->50341*/
+/* 50329*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50331*/ OPC_EmitMergeInputChains1_0,
+/* 50332*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQX_S_W_PH_MMR2), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPSQX_S_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSQX_S_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50341*/ 0, /*End of Scope*/
+/* 50342*/ /*SwitchOpcode*/ 32, TARGET_VAL(MipsISD::DPSQX_SA_W_PH),// ->50377
+/* 50345*/ OPC_RecordNode, // #0 = 'MipsDPSQX_SA_W_PH' chained node
+/* 50346*/ OPC_RecordChild1, // #1 = $rs
+/* 50347*/ OPC_RecordChild2, // #2 = $rt
+/* 50348*/ OPC_RecordChild3, // #3 = $acin
+/* 50349*/ OPC_Scope, 12, /*->50363*/ // 2 children in Scope
+/* 50351*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50353*/ OPC_EmitMergeInputChains1_0,
+/* 50354*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQX_SA_W_PH), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPSQX_SA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSQX_SA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50363*/ /*Scope*/ 12, /*->50376*/
+/* 50364*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50366*/ OPC_EmitMergeInputChains1_0,
+/* 50367*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DPSQX_SA_W_PH_MMR2), 0|OPFL_Chain,
+ MVT::Untyped, 3/*#Ops*/, 1, 2, 3,
+ // Src: (MipsDPSQX_SA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (DPSQX_SA_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50376*/ 0, /*End of Scope*/
+/* 50377*/ /*SwitchOpcode*/ 29, TARGET_VAL(MipsISD::MULSA_W_PH),// ->50409
+/* 50380*/ OPC_RecordChild0, // #0 = $rs
+/* 50381*/ OPC_RecordChild1, // #1 = $rt
+/* 50382*/ OPC_RecordChild2, // #2 = $acin
+/* 50383*/ OPC_Scope, 11, /*->50396*/ // 2 children in Scope
+/* 50385*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 50387*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULSA_W_PH), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMULSA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MULSA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50396*/ /*Scope*/ 11, /*->50408*/
+/* 50397*/ OPC_CheckPatternPredicate, 47, // (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode())
+/* 50399*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MULSA_W_PH_MMR2), 0,
+ MVT::Untyped, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsMULSA_W_PH:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin) - Complexity = 3
+ // Dst: (MULSA_W_PH_MMR2:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, ACC64DSPOpnd:{ *:[Untyped] }:$acin)
+/* 50408*/ 0, /*End of Scope*/
+/* 50409*/ /*SwitchOpcode*/ 15, TARGET_VAL(ISD::ADDE),// ->50427
+/* 50412*/ OPC_CaptureGlueInput,
+/* 50413*/ OPC_RecordChild0, // #0 = $a
+/* 50414*/ OPC_RecordChild1, // #1 = $b
+/* 50415*/ OPC_CheckType, MVT::i32,
+/* 50417*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 50419*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDWC), 0|OPFL_GlueInput|OPFL_GlueOutput,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (adde:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) - Complexity = 3
+ // Dst: (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
+/* 50427*/ /*SwitchOpcode*/ 67, TARGET_VAL(ISD::BSWAP),// ->50497
+/* 50430*/ OPC_RecordChild0, // #0 = $rt
+/* 50431*/ OPC_SwitchType /*2 cases */, 44, MVT::i32,// ->50478
+/* 50434*/ OPC_Scope, 20, /*->50456*/ // 2 children in Scope
+/* 50436*/ OPC_CheckPatternPredicate, 53, // (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50438*/ OPC_EmitNode1, TARGET_VAL(Mips::WSBH), 0,
+ MVT::i32, 1/*#Ops*/, 0, // Results = #1
+/* 50445*/ OPC_EmitInteger, MVT::i32, 16,
+/* 50448*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ROTR), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
+/* 50456*/ /*Scope*/ 20, /*->50477*/
+/* 50457*/ OPC_CheckPatternPredicate, 7, // (Subtarget->inMicroMipsMode())
+/* 50459*/ OPC_EmitNode1, TARGET_VAL(Mips::WSBH_MM), 0,
+ MVT::i32, 1/*#Ops*/, 0, // Results = #1
+/* 50466*/ OPC_EmitInteger, MVT::i32, 16,
+/* 50469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ROTR_MM), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
+/* 50477*/ 0, /*End of Scope*/
+/* 50478*/ /*SwitchType*/ 16, MVT::i64,// ->50496
+/* 50480*/ OPC_CheckPatternPredicate, 105, // (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding())
+/* 50482*/ OPC_EmitNode1, TARGET_VAL(Mips::DSBH), 0,
+ MVT::i64, 1/*#Ops*/, 0, // Results = #1
+/* 50489*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DSHD), 0,
+ MVT::i64, 1/*#Ops*/, 1,
+ // Src: (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
+/* 50496*/ 0, // EndSwitchType
+/* 50497*/ /*SwitchOpcode*/ 23, TARGET_VAL(ISD::ANY_EXTEND),// ->50523
+/* 50500*/ OPC_RecordChild0, // #0 = $src
+/* 50501*/ OPC_CheckType, MVT::i64,
+/* 50503*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())
+/* 50505*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::IMPLICIT_DEF), 0,
+ MVT::i64, 0/*#Ops*/, // Results = #1
+/* 50511*/ OPC_EmitInteger, MVT::i32, Mips::sub_32,
+/* 50514*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::INSERT_SUBREG), 0,
+ MVT::i64, 3/*#Ops*/, 1, 0, 2,
+ // Src: (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
+/* 50523*/ /*SwitchOpcode*/ 45, TARGET_VAL(MipsISD::DivRem),// ->50571
+/* 50526*/ OPC_RecordChild0, // #0 = $rs
+/* 50527*/ OPC_Scope, 27, /*->50556*/ // 2 children in Scope
+/* 50529*/ OPC_CheckChild0Type, MVT::i32,
+/* 50531*/ OPC_RecordChild1, // #1 = $rt
+/* 50532*/ OPC_Scope, 10, /*->50544*/ // 2 children in Scope
+/* 50534*/ OPC_CheckPatternPredicate, 10, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 50536*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoSDIV), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsDivRem:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (PseudoSDIV:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50544*/ /*Scope*/ 10, /*->50555*/
+/* 50545*/ OPC_CheckPatternPredicate, 106, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 50547*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SDIV_MM_Pseudo), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsDivRem:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (SDIV_MM_Pseudo:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50555*/ 0, /*End of Scope*/
+/* 50556*/ /*Scope*/ 13, /*->50570*/
+/* 50557*/ OPC_CheckChild0Type, MVT::i64,
+/* 50559*/ OPC_RecordChild1, // #1 = $rt
+/* 50560*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 50562*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoDSDIV), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsDivRem:{ *:[Untyped] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (PseudoDSDIV:{ *:[Untyped] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 50570*/ 0, /*End of Scope*/
+/* 50571*/ /*SwitchOpcode*/ 45, TARGET_VAL(MipsISD::DivRemU),// ->50619
+/* 50574*/ OPC_RecordChild0, // #0 = $rs
+/* 50575*/ OPC_Scope, 27, /*->50604*/ // 2 children in Scope
+/* 50577*/ OPC_CheckChild0Type, MVT::i32,
+/* 50579*/ OPC_RecordChild1, // #1 = $rt
+/* 50580*/ OPC_Scope, 10, /*->50592*/ // 2 children in Scope
+/* 50582*/ OPC_CheckPatternPredicate, 10, // (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 50584*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoUDIV), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsDivRemU:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (PseudoUDIV:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50592*/ /*Scope*/ 10, /*->50603*/
+/* 50593*/ OPC_CheckPatternPredicate, 106, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 50595*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::UDIV_MM_Pseudo), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsDivRemU:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (UDIV_MM_Pseudo:{ *:[Untyped] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50603*/ 0, /*End of Scope*/
+/* 50604*/ /*Scope*/ 13, /*->50618*/
+/* 50605*/ OPC_CheckChild0Type, MVT::i64,
+/* 50607*/ OPC_RecordChild1, // #1 = $rt
+/* 50608*/ OPC_CheckPatternPredicate, 44, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 50610*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoDUDIV), 0,
+ MVT::Untyped, 2/*#Ops*/, 0, 1,
+ // Src: (MipsDivRemU:{ *:[Untyped] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (PseudoDUDIV:{ *:[Untyped] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 50618*/ 0, /*End of Scope*/
+/* 50619*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::SDIV),// ->50712
+/* 50622*/ OPC_RecordChild0, // #0 = $rs
+/* 50623*/ OPC_RecordChild1, // #1 = $rt
+/* 50624*/ OPC_SwitchType /*6 cases */, 24, MVT::i32,// ->50651
+/* 50627*/ OPC_Scope, 10, /*->50639*/ // 2 children in Scope
+/* 50629*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50631*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50639*/ /*Scope*/ 10, /*->50650*/
+/* 50640*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 50642*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50650*/ 0, /*End of Scope*/
+/* 50651*/ /*SwitchType*/ 10, MVT::i64,// ->50663
+/* 50653*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50655*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DDIV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 50663*/ /*SwitchType*/ 10, MVT::v16i8,// ->50675
+/* 50665*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50667*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 50675*/ /*SwitchType*/ 10, MVT::v8i16,// ->50687
+/* 50677*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50679*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 50687*/ /*SwitchType*/ 10, MVT::v4i32,// ->50699
+/* 50689*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50691*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 50699*/ /*SwitchType*/ 10, MVT::v2i64,// ->50711
+/* 50701*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50703*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 50711*/ 0, // EndSwitchType
+/* 50712*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::UDIV),// ->50805
+/* 50715*/ OPC_RecordChild0, // #0 = $rs
+/* 50716*/ OPC_RecordChild1, // #1 = $rt
+/* 50717*/ OPC_SwitchType /*6 cases */, 24, MVT::i32,// ->50744
+/* 50720*/ OPC_Scope, 10, /*->50732*/ // 2 children in Scope
+/* 50722*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50724*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50732*/ /*Scope*/ 10, /*->50743*/
+/* 50733*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 50735*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIVU_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50743*/ 0, /*End of Scope*/
+/* 50744*/ /*SwitchType*/ 10, MVT::i64,// ->50756
+/* 50746*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50748*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DDIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 50756*/ /*SwitchType*/ 10, MVT::v16i8,// ->50768
+/* 50758*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50760*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 50768*/ /*SwitchType*/ 10, MVT::v8i16,// ->50780
+/* 50770*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50772*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 50780*/ /*SwitchType*/ 10, MVT::v4i32,// ->50792
+/* 50782*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50784*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 50792*/ /*SwitchType*/ 10, MVT::v2i64,// ->50804
+/* 50794*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50796*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DIV_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 50804*/ 0, // EndSwitchType
+/* 50805*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::SREM),// ->50898
+/* 50808*/ OPC_RecordChild0, // #0 = $rs
+/* 50809*/ OPC_RecordChild1, // #1 = $rt
+/* 50810*/ OPC_SwitchType /*6 cases */, 24, MVT::i32,// ->50837
+/* 50813*/ OPC_Scope, 10, /*->50825*/ // 2 children in Scope
+/* 50815*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50817*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50825*/ /*Scope*/ 10, /*->50836*/
+/* 50826*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 50828*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50836*/ 0, /*End of Scope*/
+/* 50837*/ /*SwitchType*/ 10, MVT::i64,// ->50849
+/* 50839*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50841*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMOD), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 50849*/ /*SwitchType*/ 10, MVT::v16i8,// ->50861
+/* 50851*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50853*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 50861*/ /*SwitchType*/ 10, MVT::v8i16,// ->50873
+/* 50863*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50865*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 50873*/ /*SwitchType*/ 10, MVT::v4i32,// ->50885
+/* 50875*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50877*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 50885*/ /*SwitchType*/ 10, MVT::v2i64,// ->50897
+/* 50887*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50889*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 50897*/ 0, // EndSwitchType
+/* 50898*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::UREM),// ->50991
+/* 50901*/ OPC_RecordChild0, // #0 = $rs
+/* 50902*/ OPC_RecordChild1, // #1 = $rt
+/* 50903*/ OPC_SwitchType /*6 cases */, 24, MVT::i32,// ->50930
+/* 50906*/ OPC_Scope, 10, /*->50918*/ // 2 children in Scope
+/* 50908*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50910*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MODU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50918*/ /*Scope*/ 10, /*->50929*/
+/* 50919*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 50921*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MODU_MMR6), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) - Complexity = 3
+ // Dst: (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+/* 50929*/ 0, /*End of Scope*/
+/* 50930*/ /*SwitchType*/ 10, MVT::i64,// ->50942
+/* 50932*/ OPC_CheckPatternPredicate, 52, // (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())
+/* 50934*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMODU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) - Complexity = 3
+ // Dst: (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+/* 50942*/ /*SwitchType*/ 10, MVT::v16i8,// ->50954
+/* 50944*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50946*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 50954*/ /*SwitchType*/ 10, MVT::v8i16,// ->50966
+/* 50956*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50958*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 50966*/ /*SwitchType*/ 10, MVT::v4i32,// ->50978
+/* 50968*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50970*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 50978*/ /*SwitchType*/ 10, MVT::v2i64,// ->50990
+/* 50980*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 50982*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MOD_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 50990*/ 0, // EndSwitchType
+/* 50991*/ /*SwitchOpcode*/ 45, TARGET_VAL(MipsISD::VALL_NONZERO),// ->51039
+/* 50994*/ OPC_RecordChild0, // #0 = $ws
+/* 50995*/ OPC_CheckType, MVT::i32,
+/* 50997*/ OPC_Scope, 9, /*->51008*/ // 4 children in Scope
+/* 50999*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 51001*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SNZ_B_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAllNonZero:{ *:[i32] } MSA128B:{ *:[v16i8] }:$ws) - Complexity = 3
+ // Dst: (SNZ_B_PSEUDO:{ *:[i32] } MSA128B:{ *:[v16i8] }:$ws)
+/* 51008*/ /*Scope*/ 9, /*->51018*/
+/* 51009*/ OPC_CheckChild0Type, MVT::v8i16,
+/* 51011*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SNZ_H_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAllNonZero:{ *:[i32] } MSA128H:{ *:[v8i16] }:$ws) - Complexity = 3
+ // Dst: (SNZ_H_PSEUDO:{ *:[i32] } MSA128H:{ *:[v8i16] }:$ws)
+/* 51018*/ /*Scope*/ 9, /*->51028*/
+/* 51019*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 51021*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SNZ_W_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAllNonZero:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws) - Complexity = 3
+ // Dst: (SNZ_W_PSEUDO:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws)
+/* 51028*/ /*Scope*/ 9, /*->51038*/
+/* 51029*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 51031*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SNZ_D_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAllNonZero:{ *:[i32] } MSA128D:{ *:[v2i64] }:$ws) - Complexity = 3
+ // Dst: (SNZ_D_PSEUDO:{ *:[i32] } MSA128D:{ *:[v2i64] }:$ws)
+/* 51038*/ 0, /*End of Scope*/
+/* 51039*/ /*SwitchOpcode*/ 12, TARGET_VAL(MipsISD::VANY_NONZERO),// ->51054
+/* 51042*/ OPC_RecordChild0, // #0 = $ws
+/* 51043*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 51045*/ OPC_CheckType, MVT::i32,
+/* 51047*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SNZ_V_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAnyNonZero:{ *:[i32] } MSA128B:{ *:[v16i8] }:$ws) - Complexity = 3
+ // Dst: (SNZ_V_PSEUDO:{ *:[i32] } MSA128B:{ *:[v16i8] }:$ws)
+/* 51054*/ /*SwitchOpcode*/ 45, TARGET_VAL(MipsISD::VALL_ZERO),// ->51102
+/* 51057*/ OPC_RecordChild0, // #0 = $ws
+/* 51058*/ OPC_CheckType, MVT::i32,
+/* 51060*/ OPC_Scope, 9, /*->51071*/ // 4 children in Scope
+/* 51062*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 51064*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SZ_B_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAllZero:{ *:[i32] } MSA128B:{ *:[v16i8] }:$ws) - Complexity = 3
+ // Dst: (SZ_B_PSEUDO:{ *:[i32] } MSA128B:{ *:[v16i8] }:$ws)
+/* 51071*/ /*Scope*/ 9, /*->51081*/
+/* 51072*/ OPC_CheckChild0Type, MVT::v8i16,
+/* 51074*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SZ_H_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAllZero:{ *:[i32] } MSA128H:{ *:[v8i16] }:$ws) - Complexity = 3
+ // Dst: (SZ_H_PSEUDO:{ *:[i32] } MSA128H:{ *:[v8i16] }:$ws)
+/* 51081*/ /*Scope*/ 9, /*->51091*/
+/* 51082*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 51084*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SZ_W_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAllZero:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws) - Complexity = 3
+ // Dst: (SZ_W_PSEUDO:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws)
+/* 51091*/ /*Scope*/ 9, /*->51101*/
+/* 51092*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 51094*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SZ_D_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAllZero:{ *:[i32] } MSA128D:{ *:[v2i64] }:$ws) - Complexity = 3
+ // Dst: (SZ_D_PSEUDO:{ *:[i32] } MSA128D:{ *:[v2i64] }:$ws)
+/* 51101*/ 0, /*End of Scope*/
+/* 51102*/ /*SwitchOpcode*/ 12, TARGET_VAL(MipsISD::VANY_ZERO),// ->51117
+/* 51105*/ OPC_RecordChild0, // #0 = $ws
+/* 51106*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 51108*/ OPC_CheckType, MVT::i32,
+/* 51110*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SZ_V_PSEUDO), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (MipsVAnyZero:{ *:[i32] } MSA128B:{ *:[v16i8] }:$ws) - Complexity = 3
+ // Dst: (SZ_V_PSEUDO:{ *:[i32] } MSA128B:{ *:[v16i8] }:$ws)
+/* 51117*/ /*SwitchOpcode*/ 7|128,3/*391*/, TARGET_VAL(ISD::FSUB),// ->51512
+/* 51121*/ OPC_Scope, 101|128,1/*229*/, /*->51353*/ // 2 children in Scope
+/* 51124*/ OPC_MoveChild0,
+/* 51125*/ OPC_SwitchOpcode /*2 cases */, 44|128,1/*172*/, TARGET_VAL(ISD::ConstantFP),// ->51302
+/* 51130*/ OPC_CheckPredicate, 63, // Predicate_fpimm0
+/* 51132*/ OPC_MoveParent,
+/* 51133*/ OPC_MoveChild1,
+/* 51134*/ OPC_SwitchOpcode /*2 cases */, 108, TARGET_VAL(ISD::FADD),// ->51246
+/* 51138*/ OPC_Scope, 52, /*->51192*/ // 2 children in Scope
+/* 51140*/ OPC_MoveChild0,
+/* 51141*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51144*/ OPC_RecordChild0, // #0 = $fs
+/* 51145*/ OPC_RecordChild1, // #1 = $ft
+/* 51146*/ OPC_MoveParent,
+/* 51147*/ OPC_RecordChild1, // #2 = $fr
+/* 51148*/ OPC_MoveParent,
+/* 51149*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->51163
+/* 51152*/ OPC_CheckPatternPredicate, 107, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51154*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) - Complexity = 13
+ // Dst: (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51163*/ /*SwitchType*/ 26, MVT::f64,// ->51191
+/* 51165*/ OPC_Scope, 11, /*->51178*/ // 2 children in Scope
+/* 51167*/ OPC_CheckPatternPredicate, 108, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51169*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 13
+ // Dst: (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51178*/ /*Scope*/ 11, /*->51190*/
+/* 51179*/ OPC_CheckPatternPredicate, 109, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51181*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 13
+ // Dst: (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51190*/ 0, /*End of Scope*/
+/* 51191*/ 0, // EndSwitchType
+/* 51192*/ /*Scope*/ 52, /*->51245*/
+/* 51193*/ OPC_RecordChild0, // #0 = $fr
+/* 51194*/ OPC_MoveChild1,
+/* 51195*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51198*/ OPC_RecordChild0, // #1 = $fs
+/* 51199*/ OPC_RecordChild1, // #2 = $ft
+/* 51200*/ OPC_MoveParent,
+/* 51201*/ OPC_MoveParent,
+/* 51202*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->51216
+/* 51205*/ OPC_CheckPatternPredicate, 107, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51207*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) - Complexity = 13
+ // Dst: (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51216*/ /*SwitchType*/ 26, MVT::f64,// ->51244
+/* 51218*/ OPC_Scope, 11, /*->51231*/ // 2 children in Scope
+/* 51220*/ OPC_CheckPatternPredicate, 108, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51222*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D32), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) - Complexity = 13
+ // Dst: (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51231*/ /*Scope*/ 11, /*->51243*/
+/* 51232*/ OPC_CheckPatternPredicate, 109, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51234*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D64), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) - Complexity = 13
+ // Dst: (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51243*/ 0, /*End of Scope*/
+/* 51244*/ 0, // EndSwitchType
+/* 51245*/ 0, /*End of Scope*/
+/* 51246*/ /*SwitchOpcode*/ 52, TARGET_VAL(ISD::FSUB),// ->51301
+/* 51249*/ OPC_MoveChild0,
+/* 51250*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51253*/ OPC_RecordChild0, // #0 = $fs
+/* 51254*/ OPC_RecordChild1, // #1 = $ft
+/* 51255*/ OPC_MoveParent,
+/* 51256*/ OPC_RecordChild1, // #2 = $fr
+/* 51257*/ OPC_MoveParent,
+/* 51258*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->51272
+/* 51261*/ OPC_CheckPatternPredicate, 107, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51263*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMSUB_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) - Complexity = 13
+ // Dst: (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51272*/ /*SwitchType*/ 26, MVT::f64,// ->51300
+/* 51274*/ OPC_Scope, 11, /*->51287*/ // 2 children in Scope
+/* 51276*/ OPC_CheckPatternPredicate, 108, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51278*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMSUB_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 13
+ // Dst: (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51287*/ /*Scope*/ 11, /*->51299*/
+/* 51288*/ OPC_CheckPatternPredicate, 109, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51290*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMSUB_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 13
+ // Dst: (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51299*/ 0, /*End of Scope*/
+/* 51300*/ 0, // EndSwitchType
+/* 51301*/ 0, // EndSwitchOpcode
+/* 51302*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::FMUL),// ->51352
+/* 51305*/ OPC_RecordChild0, // #0 = $fs
+/* 51306*/ OPC_RecordChild1, // #1 = $ft
+/* 51307*/ OPC_MoveParent,
+/* 51308*/ OPC_RecordChild1, // #2 = $fr
+/* 51309*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->51323
+/* 51312*/ OPC_CheckPatternPredicate, 110, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51314*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUB_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) - Complexity = 6
+ // Dst: (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51323*/ /*SwitchType*/ 26, MVT::f64,// ->51351
+/* 51325*/ OPC_Scope, 11, /*->51338*/ // 2 children in Scope
+/* 51327*/ OPC_CheckPatternPredicate, 111, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51329*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUB_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) - Complexity = 6
+ // Dst: (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51338*/ /*Scope*/ 11, /*->51350*/
+/* 51339*/ OPC_CheckPatternPredicate, 112, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51341*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSUB_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) - Complexity = 6
+ // Dst: (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51350*/ 0, /*End of Scope*/
+/* 51351*/ 0, // EndSwitchType
+/* 51352*/ 0, // EndSwitchOpcode
+/* 51353*/ /*Scope*/ 28|128,1/*156*/, /*->51511*/
+/* 51355*/ OPC_RecordChild0, // #0 = $fs
+/* 51356*/ OPC_Scope, 88, /*->51446*/ // 3 children in Scope
+/* 51358*/ OPC_RecordChild1, // #1 = $ft
+/* 51359*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->51397
+/* 51362*/ OPC_Scope, 10, /*->51374*/ // 3 children in Scope
+/* 51364*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 51366*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51374*/ /*Scope*/ 10, /*->51385*/
+/* 51375*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 51377*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_S_MM), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51385*/ /*Scope*/ 10, /*->51396*/
+/* 51386*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 51388*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_S_MMR6), 0,
+ MVT::f32, 2/*#Ops*/, 1, 0,
+ // Src: (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
+/* 51396*/ 0, /*End of Scope*/
+/* 51397*/ /*SwitchType*/ 46, MVT::f64,// ->51445
+/* 51399*/ OPC_Scope, 10, /*->51411*/ // 4 children in Scope
+/* 51401*/ OPC_CheckPatternPredicate, 113, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 51403*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_D32), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51411*/ /*Scope*/ 10, /*->51422*/
+/* 51412*/ OPC_CheckPatternPredicate, 114, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 51414*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_D64), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51422*/ /*Scope*/ 10, /*->51433*/
+/* 51423*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 51425*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_D32_MM), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51433*/ /*Scope*/ 10, /*->51444*/
+/* 51434*/ OPC_CheckPatternPredicate, 115, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 51436*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_D64_MM), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51444*/ 0, /*End of Scope*/
+/* 51445*/ 0, // EndSwitchType
+/* 51446*/ /*Scope*/ 35, /*->51482*/
+/* 51447*/ OPC_MoveChild1,
+/* 51448*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51451*/ OPC_RecordChild0, // #1 = $ws
+/* 51452*/ OPC_RecordChild1, // #2 = $wt
+/* 51453*/ OPC_MoveParent,
+/* 51454*/ OPC_SwitchType /*2 cases */, 11, MVT::v4f32,// ->51468
+/* 51457*/ OPC_CheckPatternPredicate, 116, // (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) && (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 51459*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMSUB_W), 0,
+ MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) - Complexity = 6
+ // Dst: (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 51468*/ /*SwitchType*/ 11, MVT::v2f64,// ->51481
+/* 51470*/ OPC_CheckPatternPredicate, 116, // (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) && (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 51472*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMSUB_D), 0,
+ MVT::v2f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) - Complexity = 6
+ // Dst: (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 51481*/ 0, // EndSwitchType
+/* 51482*/ /*Scope*/ 27, /*->51510*/
+/* 51483*/ OPC_RecordChild1, // #1 = $wt
+/* 51484*/ OPC_SwitchType /*2 cases */, 10, MVT::v4f32,// ->51497
+/* 51487*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 51489*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 3
+ // Dst: (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 51497*/ /*SwitchType*/ 10, MVT::v2f64,// ->51509
+/* 51499*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 51501*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSUB_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 3
+ // Dst: (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 51509*/ 0, // EndSwitchType
+/* 51510*/ 0, /*End of Scope*/
+/* 51511*/ 0, /*End of Scope*/
+/* 51512*/ /*SwitchOpcode*/ 81|128,2/*337*/, TARGET_VAL(ISD::FNEG),// ->51853
+/* 51516*/ OPC_Scope, 123|128,1/*251*/, /*->51770*/ // 2 children in Scope
+/* 51519*/ OPC_MoveChild0,
+/* 51520*/ OPC_SwitchOpcode /*2 cases */, 34|128,1/*162*/, TARGET_VAL(ISD::FADD),// ->51687
+/* 51525*/ OPC_Scope, 79, /*->51606*/ // 2 children in Scope
+/* 51527*/ OPC_MoveChild0,
+/* 51528*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51531*/ OPC_RecordChild0, // #0 = $fs
+/* 51532*/ OPC_RecordChild1, // #1 = $ft
+/* 51533*/ OPC_MoveParent,
+/* 51534*/ OPC_RecordChild1, // #2 = $fr
+/* 51535*/ OPC_MoveParent,
+/* 51536*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->51565
+/* 51539*/ OPC_Scope, 11, /*->51552*/ // 2 children in Scope
+/* 51541*/ OPC_CheckPatternPredicate, 117, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51543*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) - Complexity = 9
+ // Dst: (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51552*/ /*Scope*/ 11, /*->51564*/
+/* 51553*/ OPC_CheckPatternPredicate, 118, // (!Subtarget->disableMadd4()) && (Subtarget->inMicroMipsMode()) && (Subtarget->inMicroMipsMode()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips32r6())
+/* 51555*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) - Complexity = 9
+ // Dst: (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51564*/ 0, /*End of Scope*/
+/* 51565*/ /*SwitchType*/ 38, MVT::f64,// ->51605
+/* 51567*/ OPC_Scope, 11, /*->51580*/ // 3 children in Scope
+/* 51569*/ OPC_CheckPatternPredicate, 119, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51571*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 9
+ // Dst: (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51580*/ /*Scope*/ 11, /*->51592*/
+/* 51581*/ OPC_CheckPatternPredicate, 120, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51583*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 9
+ // Dst: (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51592*/ /*Scope*/ 11, /*->51604*/
+/* 51593*/ OPC_CheckPatternPredicate, 121, // (!Subtarget->disableMadd4()) && (Subtarget->inMicroMipsMode()) && (Subtarget->inMicroMipsMode()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips32r6())
+/* 51595*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 9
+ // Dst: (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51604*/ 0, /*End of Scope*/
+/* 51605*/ 0, // EndSwitchType
+/* 51606*/ /*Scope*/ 79, /*->51686*/
+/* 51607*/ OPC_RecordChild0, // #0 = $fr
+/* 51608*/ OPC_MoveChild1,
+/* 51609*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51612*/ OPC_RecordChild0, // #1 = $fs
+/* 51613*/ OPC_RecordChild1, // #2 = $ft
+/* 51614*/ OPC_MoveParent,
+/* 51615*/ OPC_MoveParent,
+/* 51616*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->51645
+/* 51619*/ OPC_Scope, 11, /*->51632*/ // 2 children in Scope
+/* 51621*/ OPC_CheckPatternPredicate, 117, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51623*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) - Complexity = 9
+ // Dst: (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51632*/ /*Scope*/ 11, /*->51644*/
+/* 51633*/ OPC_CheckPatternPredicate, 118, // (!Subtarget->disableMadd4()) && (Subtarget->inMicroMipsMode()) && (Subtarget->inMicroMipsMode()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips32r6())
+/* 51635*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) - Complexity = 9
+ // Dst: (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51644*/ 0, /*End of Scope*/
+/* 51645*/ /*SwitchType*/ 38, MVT::f64,// ->51685
+/* 51647*/ OPC_Scope, 11, /*->51660*/ // 3 children in Scope
+/* 51649*/ OPC_CheckPatternPredicate, 119, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51651*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D32), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) - Complexity = 9
+ // Dst: (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51660*/ /*Scope*/ 11, /*->51672*/
+/* 51661*/ OPC_CheckPatternPredicate, 120, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51663*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D64), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) - Complexity = 9
+ // Dst: (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51672*/ /*Scope*/ 11, /*->51684*/
+/* 51673*/ OPC_CheckPatternPredicate, 121, // (!Subtarget->disableMadd4()) && (Subtarget->inMicroMipsMode()) && (Subtarget->inMicroMipsMode()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips32r6())
+/* 51675*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMADD_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) - Complexity = 9
+ // Dst: (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51684*/ 0, /*End of Scope*/
+/* 51685*/ 0, // EndSwitchType
+/* 51686*/ 0, /*End of Scope*/
+/* 51687*/ /*SwitchOpcode*/ 79, TARGET_VAL(ISD::FSUB),// ->51769
+/* 51690*/ OPC_MoveChild0,
+/* 51691*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51694*/ OPC_RecordChild0, // #0 = $fs
+/* 51695*/ OPC_RecordChild1, // #1 = $ft
+/* 51696*/ OPC_MoveParent,
+/* 51697*/ OPC_RecordChild1, // #2 = $fr
+/* 51698*/ OPC_MoveParent,
+/* 51699*/ OPC_SwitchType /*2 cases */, 26, MVT::f32,// ->51728
+/* 51702*/ OPC_Scope, 11, /*->51715*/ // 2 children in Scope
+/* 51704*/ OPC_CheckPatternPredicate, 117, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51706*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMSUB_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) - Complexity = 9
+ // Dst: (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51715*/ /*Scope*/ 11, /*->51727*/
+/* 51716*/ OPC_CheckPatternPredicate, 118, // (!Subtarget->disableMadd4()) && (Subtarget->inMicroMipsMode()) && (Subtarget->inMicroMipsMode()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips32r6())
+/* 51718*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMSUB_S_MM), 0,
+ MVT::f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) - Complexity = 9
+ // Dst: (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51727*/ 0, /*End of Scope*/
+/* 51728*/ /*SwitchType*/ 38, MVT::f64,// ->51768
+/* 51730*/ OPC_Scope, 11, /*->51743*/ // 3 children in Scope
+/* 51732*/ OPC_CheckPatternPredicate, 119, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51734*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMSUB_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 9
+ // Dst: (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51743*/ /*Scope*/ 11, /*->51755*/
+/* 51744*/ OPC_CheckPatternPredicate, 120, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51746*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMSUB_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 9
+ // Dst: (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51755*/ /*Scope*/ 11, /*->51767*/
+/* 51756*/ OPC_CheckPatternPredicate, 121, // (!Subtarget->disableMadd4()) && (Subtarget->inMicroMipsMode()) && (Subtarget->inMicroMipsMode()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips32r6())
+/* 51758*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NMSUB_D32_MM), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) - Complexity = 9
+ // Dst: (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51767*/ 0, /*End of Scope*/
+/* 51768*/ 0, // EndSwitchType
+/* 51769*/ 0, // EndSwitchOpcode
+/* 51770*/ /*Scope*/ 81, /*->51852*/
+/* 51771*/ OPC_RecordChild0, // #0 = $fs
+/* 51772*/ OPC_SwitchType /*2 cases */, 32, MVT::f32,// ->51807
+/* 51775*/ OPC_Scope, 9, /*->51786*/ // 3 children in Scope
+/* 51777*/ OPC_CheckPatternPredicate, 122, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())
+/* 51779*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_S), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 51786*/ /*Scope*/ 9, /*->51796*/
+/* 51787*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 51789*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_S_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 51796*/ /*Scope*/ 9, /*->51806*/
+/* 51797*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 51799*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_S_MMR6), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 51806*/ 0, /*End of Scope*/
+/* 51807*/ /*SwitchType*/ 42, MVT::f64,// ->51851
+/* 51809*/ OPC_Scope, 9, /*->51820*/ // 4 children in Scope
+/* 51811*/ OPC_CheckPatternPredicate, 113, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 51813*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_D32), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
+/* 51820*/ /*Scope*/ 9, /*->51830*/
+/* 51821*/ OPC_CheckPatternPredicate, 114, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 51823*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_D64), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
+/* 51830*/ /*Scope*/ 9, /*->51840*/
+/* 51831*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 51833*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_D32_MM), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
+/* 51840*/ /*Scope*/ 9, /*->51850*/
+/* 51841*/ OPC_CheckPatternPredicate, 115, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 51843*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_D64_MM), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
+/* 51850*/ 0, /*End of Scope*/
+/* 51851*/ 0, // EndSwitchType
+/* 51852*/ 0, /*End of Scope*/
+/* 51853*/ /*SwitchOpcode*/ 45|128,2/*301*/, TARGET_VAL(ISD::FADD),// ->52158
+/* 51857*/ OPC_Scope, 51, /*->51910*/ // 4 children in Scope
+/* 51859*/ OPC_MoveChild0,
+/* 51860*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51863*/ OPC_RecordChild0, // #0 = $fs
+/* 51864*/ OPC_RecordChild1, // #1 = $ft
+/* 51865*/ OPC_MoveParent,
+/* 51866*/ OPC_RecordChild1, // #2 = $fr
+/* 51867*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->51881
+/* 51870*/ OPC_CheckPatternPredicate, 110, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51872*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) - Complexity = 6
+ // Dst: (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51881*/ /*SwitchType*/ 26, MVT::f64,// ->51909
+/* 51883*/ OPC_Scope, 11, /*->51896*/ // 2 children in Scope
+/* 51885*/ OPC_CheckPatternPredicate, 111, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51887*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_D32), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) - Complexity = 6
+ // Dst: (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51896*/ /*Scope*/ 11, /*->51908*/
+/* 51897*/ OPC_CheckPatternPredicate, 112, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51899*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_D64), 0,
+ MVT::f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) - Complexity = 6
+ // Dst: (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51908*/ 0, /*End of Scope*/
+/* 51909*/ 0, // EndSwitchType
+/* 51910*/ /*Scope*/ 51|128,1/*179*/, /*->52091*/
+/* 51912*/ OPC_RecordChild0, // #0 = $fr
+/* 51913*/ OPC_Scope, 50, /*->51965*/ // 3 children in Scope
+/* 51915*/ OPC_MoveChild1,
+/* 51916*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 51919*/ OPC_RecordChild0, // #1 = $fs
+/* 51920*/ OPC_RecordChild1, // #2 = $ft
+/* 51921*/ OPC_MoveParent,
+/* 51922*/ OPC_SwitchType /*2 cases */, 11, MVT::f32,// ->51936
+/* 51925*/ OPC_CheckPatternPredicate, 110, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51927*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) - Complexity = 6
+ // Dst: (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51936*/ /*SwitchType*/ 26, MVT::f64,// ->51964
+/* 51938*/ OPC_Scope, 11, /*->51951*/ // 2 children in Scope
+/* 51940*/ OPC_CheckPatternPredicate, 111, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51942*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_D32), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) - Complexity = 6
+ // Dst: (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 51951*/ /*Scope*/ 11, /*->51963*/
+/* 51952*/ OPC_CheckPatternPredicate, 112, // (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())
+/* 51954*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MADD_D64), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) - Complexity = 6
+ // Dst: (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 51963*/ 0, /*End of Scope*/
+/* 51964*/ 0, // EndSwitchType
+/* 51965*/ /*Scope*/ 88, /*->52054*/
+/* 51966*/ OPC_RecordChild1, // #1 = $ft
+/* 51967*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->52005
+/* 51970*/ OPC_Scope, 10, /*->51982*/ // 3 children in Scope
+/* 51972*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 51974*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51982*/ /*Scope*/ 10, /*->51993*/
+/* 51983*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 51985*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_S_MM), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 51993*/ /*Scope*/ 10, /*->52004*/
+/* 51994*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 51996*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_S_MMR6), 0,
+ MVT::f32, 2/*#Ops*/, 1, 0,
+ // Src: (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
+/* 52004*/ 0, /*End of Scope*/
+/* 52005*/ /*SwitchType*/ 46, MVT::f64,// ->52053
+/* 52007*/ OPC_Scope, 10, /*->52019*/ // 4 children in Scope
+/* 52009*/ OPC_CheckPatternPredicate, 113, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 52011*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_D32), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 52019*/ /*Scope*/ 10, /*->52030*/
+/* 52020*/ OPC_CheckPatternPredicate, 114, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52022*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_D64), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 52030*/ /*Scope*/ 10, /*->52041*/
+/* 52031*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 52033*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_D32_MM), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 52041*/ /*Scope*/ 10, /*->52052*/
+/* 52042*/ OPC_CheckPatternPredicate, 115, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 52044*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_D64_MM), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 52052*/ 0, /*End of Scope*/
+/* 52053*/ 0, // EndSwitchType
+/* 52054*/ /*Scope*/ 35, /*->52090*/
+/* 52055*/ OPC_MoveChild1,
+/* 52056*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 52059*/ OPC_RecordChild0, // #1 = $ws
+/* 52060*/ OPC_RecordChild1, // #2 = $wt
+/* 52061*/ OPC_MoveParent,
+/* 52062*/ OPC_SwitchType /*2 cases */, 11, MVT::v4f32,// ->52076
+/* 52065*/ OPC_CheckPatternPredicate, 116, // (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) && (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52067*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMADD_W), 0,
+ MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) - Complexity = 6
+ // Dst: (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 52076*/ /*SwitchType*/ 11, MVT::v2f64,// ->52089
+/* 52078*/ OPC_CheckPatternPredicate, 116, // (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) && (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52080*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMADD_D), 0,
+ MVT::v2f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) - Complexity = 6
+ // Dst: (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 52089*/ 0, // EndSwitchType
+/* 52090*/ 0, /*End of Scope*/
+/* 52091*/ /*Scope*/ 36, /*->52128*/
+/* 52092*/ OPC_MoveChild0,
+/* 52093*/ OPC_CheckOpcode, TARGET_VAL(ISD::FMUL),
+/* 52096*/ OPC_RecordChild0, // #0 = $ws
+/* 52097*/ OPC_RecordChild1, // #1 = $wt
+/* 52098*/ OPC_MoveParent,
+/* 52099*/ OPC_RecordChild1, // #2 = $wd
+/* 52100*/ OPC_SwitchType /*2 cases */, 11, MVT::v4f32,// ->52114
+/* 52103*/ OPC_CheckPatternPredicate, 116, // (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) && (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52105*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMADD_W), 0,
+ MVT::v4f32, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) - Complexity = 6
+ // Dst: (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 52114*/ /*SwitchType*/ 11, MVT::v2f64,// ->52127
+/* 52116*/ OPC_CheckPatternPredicate, 116, // (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) && (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52118*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMADD_D), 0,
+ MVT::v2f64, 3/*#Ops*/, 2, 0, 1,
+ // Src: (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) - Complexity = 6
+ // Dst: (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 52127*/ 0, // EndSwitchType
+/* 52128*/ /*Scope*/ 28, /*->52157*/
+/* 52129*/ OPC_RecordChild0, // #0 = $ws
+/* 52130*/ OPC_RecordChild1, // #1 = $wt
+/* 52131*/ OPC_SwitchType /*2 cases */, 10, MVT::v4f32,// ->52144
+/* 52134*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52136*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 3
+ // Dst: (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 52144*/ /*SwitchType*/ 10, MVT::v2f64,// ->52156
+/* 52146*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52148*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FADD_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 3
+ // Dst: (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 52156*/ 0, // EndSwitchType
+/* 52157*/ 0, /*End of Scope*/
+/* 52158*/ /*SwitchOpcode*/ 28|128,1/*156*/, TARGET_VAL(ISD::ConstantFP),// ->52318
+/* 52162*/ OPC_Scope, 62, /*->52226*/ // 2 children in Scope
+/* 52164*/ OPC_CheckPredicate, 63, // Predicate_fpimm0
+/* 52166*/ OPC_SwitchType /*2 cases */, 41, MVT::f32,// ->52210
+/* 52169*/ OPC_Scope, 12, /*->52183*/ // 3 children in Scope
+/* 52171*/ OPC_CheckPatternPredicate, 69, // (Subtarget->hasStandardEncoding())
+/* 52173*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 52176*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>> - Complexity = 4
+ // Dst: (MTC1:{ *:[f32] } ZERO:{ *:[i32] })
+/* 52183*/ /*Scope*/ 12, /*->52196*/
+/* 52184*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 52186*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 52189*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>> - Complexity = 4
+ // Dst: (MTC1_MM:{ *:[f32] } ZERO:{ *:[i32] })
+/* 52196*/ /*Scope*/ 12, /*->52209*/
+/* 52197*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 52199*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 52202*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1_MMR6), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>> - Complexity = 4
+ // Dst: (MTC1_MMR6:{ *:[f32] } ZERO:{ *:[i32] })
+/* 52209*/ 0, /*End of Scope*/
+/* 52210*/ /*SwitchType*/ 13, MVT::f64,// ->52225
+/* 52212*/ OPC_CheckPatternPredicate, 123, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (Subtarget->isGP64bit())
+/* 52214*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 52218*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DMTC1), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>> - Complexity = 4
+ // Dst: (DMTC1:{ *:[f64] } ZERO_64:{ *:[i64] })
+/* 52225*/ 0, // EndSwitchType
+/* 52226*/ /*Scope*/ 90, /*->52317*/
+/* 52227*/ OPC_CheckPredicate, 64, // Predicate_fpimm0neg
+/* 52229*/ OPC_SwitchType /*2 cases */, 62, MVT::f32,// ->52294
+/* 52232*/ OPC_Scope, 19, /*->52253*/ // 3 children in Scope
+/* 52234*/ OPC_CheckPatternPredicate, 69, // (Subtarget->hasStandardEncoding())
+/* 52236*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 52239*/ OPC_EmitNode1, TARGET_VAL(Mips::MTC1), 0,
+ MVT::f32, 1/*#Ops*/, 0, // Results = #1
+/* 52246*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_S), 0,
+ MVT::f32, 1/*#Ops*/, 1,
+ // Src: (fpimm:{ *:[f32] })<<P:Predicate_fpimm0neg>> - Complexity = 4
+ // Dst: (FNEG_S:{ *:[f32] } (MTC1:{ *:[f32] } ZERO:{ *:[i32] }))
+/* 52253*/ /*Scope*/ 19, /*->52273*/
+/* 52254*/ OPC_CheckPatternPredicate, 28, // (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())
+/* 52256*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 52259*/ OPC_EmitNode1, TARGET_VAL(Mips::MTC1_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0, // Results = #1
+/* 52266*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_S_MM), 0,
+ MVT::f32, 1/*#Ops*/, 1,
+ // Src: (fpimm:{ *:[f32] })<<P:Predicate_fpimm0neg>> - Complexity = 4
+ // Dst: (FNEG_S_MM:{ *:[f32] } (MTC1_MM:{ *:[f32] } ZERO:{ *:[i32] }))
+/* 52273*/ /*Scope*/ 19, /*->52293*/
+/* 52274*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 52276*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 52279*/ OPC_EmitNode1, TARGET_VAL(Mips::MTC1), 0,
+ MVT::f32, 1/*#Ops*/, 0, // Results = #1
+/* 52286*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_S_MMR6), 0,
+ MVT::f32, 1/*#Ops*/, 1,
+ // Src: (fpimm:{ *:[f32] })<<P:Predicate_fpimm0neg>> - Complexity = 4
+ // Dst: (FNEG_S_MMR6:{ *:[f32] } (MTC1:{ *:[f32] } ZERO:{ *:[i32] }))
+/* 52293*/ 0, /*End of Scope*/
+/* 52294*/ /*SwitchType*/ 20, MVT::f64,// ->52316
+/* 52296*/ OPC_CheckPatternPredicate, 123, // (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (Subtarget->isGP64bit())
+/* 52298*/ OPC_EmitRegister2, MVT::i64, TARGET_VAL(Mips::ZERO_64),
+/* 52302*/ OPC_EmitNode1, TARGET_VAL(Mips::DMTC1), 0,
+ MVT::f64, 1/*#Ops*/, 0, // Results = #1
+/* 52309*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FNEG_D64), 0,
+ MVT::f64, 1/*#Ops*/, 1,
+ // Src: (fpimm:{ *:[f64] })<<P:Predicate_fpimm0neg>> - Complexity = 4
+ // Dst: (FNEG_D64:{ *:[f64] } (DMTC1:{ *:[f64] } ZERO_64:{ *:[i64] }))
+/* 52316*/ 0, // EndSwitchType
+/* 52317*/ 0, /*End of Scope*/
+/* 52318*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FABS),// ->52414
+/* 52321*/ OPC_RecordChild0, // #0 = $fs
+/* 52322*/ OPC_SwitchType /*4 cases */, 22, MVT::f32,// ->52347
+/* 52325*/ OPC_Scope, 9, /*->52336*/ // 2 children in Scope
+/* 52327*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52329*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FABS_S), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 52336*/ /*Scope*/ 9, /*->52346*/
+/* 52337*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 52339*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FABS_S_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 52346*/ 0, /*End of Scope*/
+/* 52347*/ /*SwitchType*/ 42, MVT::f64,// ->52391
+/* 52349*/ OPC_Scope, 9, /*->52360*/ // 4 children in Scope
+/* 52351*/ OPC_CheckPatternPredicate, 113, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 52353*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FABS_D32), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
+/* 52360*/ /*Scope*/ 9, /*->52370*/
+/* 52361*/ OPC_CheckPatternPredicate, 114, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52363*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FABS_D64), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
+/* 52370*/ /*Scope*/ 9, /*->52380*/
+/* 52371*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 52373*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FABS_D32_MM), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
+/* 52380*/ /*Scope*/ 9, /*->52390*/
+/* 52381*/ OPC_CheckPatternPredicate, 115, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 52383*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FABS_D64_MM), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
+/* 52390*/ 0, /*End of Scope*/
+/* 52391*/ /*SwitchType*/ 9, MVT::v4f32,// ->52402
+/* 52393*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52395*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FABS_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 3
+ // Dst: (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 52402*/ /*SwitchType*/ 9, MVT::v2f64,// ->52413
+/* 52404*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52406*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FABS_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 3
+ // Dst: (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 52413*/ 0, // EndSwitchType
+/* 52414*/ /*SwitchOpcode*/ 93, TARGET_VAL(ISD::FSQRT),// ->52510
+/* 52417*/ OPC_RecordChild0, // #0 = $fs
+/* 52418*/ OPC_SwitchType /*4 cases */, 22, MVT::f32,// ->52443
+/* 52421*/ OPC_Scope, 9, /*->52432*/ // 2 children in Scope
+/* 52423*/ OPC_CheckPatternPredicate, 124, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52425*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSQRT_S), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 52432*/ /*Scope*/ 9, /*->52442*/
+/* 52433*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 52435*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSQRT_S_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 52442*/ 0, /*End of Scope*/
+/* 52443*/ /*SwitchType*/ 42, MVT::f64,// ->52487
+/* 52445*/ OPC_Scope, 9, /*->52456*/ // 4 children in Scope
+/* 52447*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 52449*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSQRT_D32), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
+/* 52456*/ /*Scope*/ 9, /*->52466*/
+/* 52457*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52459*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSQRT_D64), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
+/* 52466*/ /*Scope*/ 9, /*->52476*/
+/* 52467*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 52469*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSQRT_D32_MM), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
+/* 52476*/ /*Scope*/ 9, /*->52486*/
+/* 52477*/ OPC_CheckPatternPredicate, 115, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 52479*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSQRT_D64_MM), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
+/* 52486*/ 0, /*End of Scope*/
+/* 52487*/ /*SwitchType*/ 9, MVT::v4f32,// ->52498
+/* 52489*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52491*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSQRT_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 3
+ // Dst: (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 52498*/ /*SwitchType*/ 9, MVT::v2f64,// ->52509
+/* 52500*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52502*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FSQRT_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 3
+ // Dst: (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 52509*/ 0, // EndSwitchType
+/* 52510*/ /*SwitchOpcode*/ 113, TARGET_VAL(ISD::FDIV),// ->52626
+/* 52513*/ OPC_RecordChild0, // #0 = $fs
+/* 52514*/ OPC_RecordChild1, // #1 = $ft
+/* 52515*/ OPC_SwitchType /*4 cases */, 35, MVT::f32,// ->52553
+/* 52518*/ OPC_Scope, 10, /*->52530*/ // 3 children in Scope
+/* 52520*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52522*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 52530*/ /*Scope*/ 10, /*->52541*/
+/* 52531*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 52533*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_S_MM), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 52541*/ /*Scope*/ 10, /*->52552*/
+/* 52542*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 52544*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_S_MMR6), 0,
+ MVT::f32, 2/*#Ops*/, 1, 0,
+ // Src: (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
+/* 52552*/ 0, /*End of Scope*/
+/* 52553*/ /*SwitchType*/ 46, MVT::f64,// ->52601
+/* 52555*/ OPC_Scope, 10, /*->52567*/ // 4 children in Scope
+/* 52557*/ OPC_CheckPatternPredicate, 113, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 52559*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_D32), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 52567*/ /*Scope*/ 10, /*->52578*/
+/* 52568*/ OPC_CheckPatternPredicate, 114, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52570*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_D64), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 52578*/ /*Scope*/ 10, /*->52589*/
+/* 52579*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 52581*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_D32_MM), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 52589*/ /*Scope*/ 10, /*->52600*/
+/* 52590*/ OPC_CheckPatternPredicate, 115, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 52592*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_D64_MM), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 52600*/ 0, /*End of Scope*/
+/* 52601*/ /*SwitchType*/ 10, MVT::v4f32,// ->52613
+/* 52603*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52605*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 3
+ // Dst: (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 52613*/ /*SwitchType*/ 10, MVT::v2f64,// ->52625
+/* 52615*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52617*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FDIV_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 3
+ // Dst: (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 52625*/ 0, // EndSwitchType
+/* 52626*/ /*SwitchOpcode*/ 63|128,1/*191*/, TARGET_VAL(ISD::FMUL),// ->52821
+/* 52630*/ OPC_Scope, 125, /*->52757*/ // 3 children in Scope
+/* 52632*/ OPC_RecordChild0, // #0 = $fs
+/* 52633*/ OPC_Scope, 88, /*->52723*/ // 2 children in Scope
+/* 52635*/ OPC_RecordChild1, // #1 = $ft
+/* 52636*/ OPC_SwitchType /*2 cases */, 35, MVT::f32,// ->52674
+/* 52639*/ OPC_Scope, 10, /*->52651*/ // 3 children in Scope
+/* 52641*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52643*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 52651*/ /*Scope*/ 10, /*->52662*/
+/* 52652*/ OPC_CheckPatternPredicate, 17, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 52654*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_S_MM), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+/* 52662*/ /*Scope*/ 10, /*->52673*/
+/* 52663*/ OPC_CheckPatternPredicate, 62, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())
+/* 52665*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_S_MMR6), 0,
+ MVT::f32, 2/*#Ops*/, 1, 0,
+ // Src: (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) - Complexity = 3
+ // Dst: (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
+/* 52673*/ 0, /*End of Scope*/
+/* 52674*/ /*SwitchType*/ 46, MVT::f64,// ->52722
+/* 52676*/ OPC_Scope, 10, /*->52688*/ // 4 children in Scope
+/* 52678*/ OPC_CheckPatternPredicate, 113, // (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 52680*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_D32), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 52688*/ /*Scope*/ 10, /*->52699*/
+/* 52689*/ OPC_CheckPatternPredicate, 114, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 52691*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_D64), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 52699*/ /*Scope*/ 10, /*->52710*/
+/* 52700*/ OPC_CheckPatternPredicate, 20, // (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())
+/* 52702*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_D32_MM), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+/* 52710*/ /*Scope*/ 10, /*->52721*/
+/* 52711*/ OPC_CheckPatternPredicate, 115, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())
+/* 52713*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_D64_MM), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) - Complexity = 3
+ // Dst: (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 52721*/ 0, /*End of Scope*/
+/* 52722*/ 0, // EndSwitchType
+/* 52723*/ /*Scope*/ 32, /*->52756*/
+/* 52724*/ OPC_MoveChild1,
+/* 52725*/ OPC_CheckOpcode, TARGET_VAL(ISD::FEXP2),
+/* 52728*/ OPC_RecordChild0, // #1 = $wt
+/* 52729*/ OPC_MoveParent,
+/* 52730*/ OPC_SwitchType /*2 cases */, 10, MVT::v4f32,// ->52743
+/* 52733*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52735*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXP2_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) - Complexity = 6
+ // Dst: (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 52743*/ /*SwitchType*/ 10, MVT::v2f64,// ->52755
+/* 52745*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52747*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXP2_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) - Complexity = 6
+ // Dst: (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 52755*/ 0, // EndSwitchType
+/* 52756*/ 0, /*End of Scope*/
+/* 52757*/ /*Scope*/ 33, /*->52791*/
+/* 52758*/ OPC_MoveChild0,
+/* 52759*/ OPC_CheckOpcode, TARGET_VAL(ISD::FEXP2),
+/* 52762*/ OPC_RecordChild0, // #0 = $wt
+/* 52763*/ OPC_MoveParent,
+/* 52764*/ OPC_RecordChild1, // #1 = $ws
+/* 52765*/ OPC_SwitchType /*2 cases */, 10, MVT::v4f32,// ->52778
+/* 52768*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52770*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXP2_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 1, 0,
+ // Src: (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 6
+ // Dst: (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 52778*/ /*SwitchType*/ 10, MVT::v2f64,// ->52790
+/* 52780*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52782*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXP2_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 1, 0,
+ // Src: (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 6
+ // Dst: (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 52790*/ 0, // EndSwitchType
+/* 52791*/ /*Scope*/ 28, /*->52820*/
+/* 52792*/ OPC_RecordChild0, // #0 = $ws
+/* 52793*/ OPC_RecordChild1, // #1 = $wt
+/* 52794*/ OPC_SwitchType /*2 cases */, 10, MVT::v4f32,// ->52807
+/* 52797*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52799*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_W), 0,
+ MVT::v4f32, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 3
+ // Dst: (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 52807*/ /*SwitchType*/ 10, MVT::v2f64,// ->52819
+/* 52809*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52811*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMUL_D), 0,
+ MVT::v2f64, 2/*#Ops*/, 0, 1,
+ // Src: (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 3
+ // Dst: (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 52819*/ 0, // EndSwitchType
+/* 52820*/ 0, /*End of Scope*/
+/* 52821*/ /*SwitchOpcode*/ 26, TARGET_VAL(MipsISD::BuildPairF64),// ->52850
+/* 52824*/ OPC_RecordChild0, // #0 = $lo
+/* 52825*/ OPC_RecordChild1, // #1 = $hi
+/* 52826*/ OPC_Scope, 10, /*->52838*/ // 2 children in Scope
+/* 52828*/ OPC_CheckPatternPredicate, 85, // (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())
+/* 52830*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BuildPairF64), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 3
+ // Dst: (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
+/* 52838*/ /*Scope*/ 10, /*->52849*/
+/* 52839*/ OPC_CheckPatternPredicate, 86, // (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())
+/* 52841*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BuildPairF64_64), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi) - Complexity = 3
+ // Dst: (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
+/* 52849*/ 0, /*End of Scope*/
+/* 52850*/ /*SwitchOpcode*/ 107, TARGET_VAL(ISD::SINT_TO_FP),// ->52960
+/* 52853*/ OPC_RecordChild0, // #0 = $src
+/* 52854*/ OPC_Scope, 37, /*->52893*/ // 4 children in Scope
+/* 52856*/ OPC_CheckChild0Type, MVT::i32,
+/* 52858*/ OPC_SwitchType /*2 cases */, 7, MVT::f32,// ->52868
+/* 52861*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoCVT_S_W), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
+/* 52868*/ /*SwitchType*/ 22, MVT::f64,// ->52892
+/* 52870*/ OPC_Scope, 9, /*->52881*/ // 2 children in Scope
+/* 52872*/ OPC_CheckPatternPredicate, 125, // (!Subtarget->isFP64bit())
+/* 52874*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoCVT_D32_W), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
+/* 52881*/ /*Scope*/ 9, /*->52891*/
+/* 52882*/ OPC_CheckPatternPredicate, 126, // (Subtarget->isFP64bit())
+/* 52884*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoCVT_D64_W), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
+/* 52891*/ 0, /*End of Scope*/
+/* 52892*/ 0, // EndSwitchType
+/* 52893*/ /*Scope*/ 37, /*->52931*/
+/* 52894*/ OPC_CheckChild0Type, MVT::i64,
+/* 52896*/ OPC_SwitchType /*2 cases */, 9, MVT::f64,// ->52908
+/* 52899*/ OPC_CheckPatternPredicate, 126, // (Subtarget->isFP64bit())
+/* 52901*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoCVT_D64_L), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) - Complexity = 3
+ // Dst: (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
+/* 52908*/ /*SwitchType*/ 20, MVT::f32,// ->52930
+/* 52910*/ OPC_CheckPatternPredicate, 126, // (Subtarget->isFP64bit())
+/* 52912*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCVT_S_L), 0,
+ MVT::f64, 1/*#Ops*/, 0, // Results = #1
+/* 52919*/ OPC_EmitInteger, MVT::i32, Mips::sub_lo,
+/* 52922*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::EXTRACT_SUBREG), 0,
+ MVT::f32, 2/*#Ops*/, 1, 2,
+ // Src: (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src) - Complexity = 3
+ // Dst: (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
+/* 52930*/ 0, // EndSwitchType
+/* 52931*/ /*Scope*/ 13, /*->52945*/
+/* 52932*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 52934*/ OPC_CheckType, MVT::v4f32,
+/* 52936*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52938*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FFINT_S_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 3
+ // Dst: (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+/* 52945*/ /*Scope*/ 13, /*->52959*/
+/* 52946*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 52948*/ OPC_CheckType, MVT::v2f64,
+/* 52950*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 52952*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FFINT_S_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 3
+ // Dst: (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
+/* 52959*/ 0, /*End of Scope*/
+/* 52960*/ /*SwitchOpcode*/ 111, TARGET_VAL(MipsISD::TruncIntFP),// ->53074
+/* 52963*/ OPC_RecordChild0, // #0 = $src
+/* 52964*/ OPC_Scope, 26, /*->52992*/ // 3 children in Scope
+/* 52966*/ OPC_CheckChild0Type, MVT::f32,
+/* 52968*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->52980
+/* 52971*/ OPC_CheckPatternPredicate, 69, // (Subtarget->hasStandardEncoding())
+/* 52973*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_W_S), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (MipsTruncIntFP:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (TRUNC_W_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$src)
+/* 52980*/ /*SwitchType*/ 9, MVT::f64,// ->52991
+/* 52982*/ OPC_CheckPatternPredicate, 127, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())
+/* 52984*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_L_S), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (MipsTruncIntFP:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (TRUNC_L_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+/* 52991*/ 0, // EndSwitchType
+/* 52992*/ /*Scope*/ 59, /*->53052*/
+/* 52993*/ OPC_CheckChild0Type, MVT::f64,
+/* 52995*/ OPC_SwitchType /*2 cases */, 42, MVT::f32,// ->53040
+/* 52998*/ OPC_Scope, 9, /*->53009*/ // 4 children in Scope
+/* 53000*/ OPC_CheckPatternPredicate, 128, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 53002*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_W_D32), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (MipsTruncIntFP:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (TRUNC_W_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
+/* 53009*/ /*Scope*/ 9, /*->53019*/
+/* 53010*/ OPC_CheckPatternPredicate, 127, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())
+/* 53012*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_W_D64), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (MipsTruncIntFP:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (TRUNC_W_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
+/* 53019*/ /*Scope*/ 9, /*->53029*/
+/* 53020*/ OPC_CheckPatternPredicate, 39, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())
+/* 53022*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_W_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (MipsTruncIntFP:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (TRUNC_W_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
+/* 53029*/ /*Scope*/ 9, /*->53039*/
+/* 53030*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 53032*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_W_D_MMR6), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (MipsTruncIntFP:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (TRUNC_W_D_MMR6:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
+/* 53039*/ 0, /*End of Scope*/
+/* 53040*/ /*SwitchType*/ 9, MVT::f64,// ->53051
+/* 53042*/ OPC_CheckPatternPredicate, 127, // (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())
+/* 53044*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_L_D64), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (MipsTruncIntFP:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (TRUNC_L_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$src)
+/* 53051*/ 0, // EndSwitchType
+/* 53052*/ /*Scope*/ 20, /*->53073*/
+/* 53053*/ OPC_CheckChild0Type, MVT::f16,
+/* 53055*/ OPC_CheckType, MVT::f32,
+/* 53057*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53059*/ OPC_EmitNode1, TARGET_VAL(Mips::MSA_FP_EXTEND_D_PSEUDO), 0,
+ MVT::f64, 1/*#Ops*/, 0, // Results = #1
+/* 53066*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::TRUNC_W_D64), 0,
+ MVT::f32, 1/*#Ops*/, 1,
+ // Src: (MipsTruncIntFP:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) - Complexity = 3
+ // Dst: (TRUNC_W_D64:{ *:[f32] } (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws))
+/* 53073*/ 0, /*End of Scope*/
+/* 53074*/ /*SwitchOpcode*/ 10, TARGET_VAL(MipsISD::MTC1_D64),// ->53087
+/* 53077*/ OPC_RecordChild0, // #0 = $src
+/* 53078*/ OPC_CheckPatternPredicate, 129, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())
+/* 53080*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MTC1_D64), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (MipsMTC1_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) - Complexity = 3
+ // Dst: (MTC1_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
+/* 53087*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::FP_ROUND),// ->53165
+/* 53090*/ OPC_RecordChild0, // #0 = $src
+/* 53091*/ OPC_SwitchType /*2 cases */, 42, MVT::f32,// ->53136
+/* 53094*/ OPC_Scope, 9, /*->53105*/ // 4 children in Scope
+/* 53096*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 53098*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CVT_S_D32), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
+/* 53105*/ /*Scope*/ 9, /*->53115*/
+/* 53106*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 53108*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CVT_S_D64), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
+/* 53115*/ /*Scope*/ 9, /*->53125*/
+/* 53116*/ OPC_CheckPatternPredicate, 130, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())
+/* 53118*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CVT_S_D64_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
+/* 53125*/ /*Scope*/ 9, /*->53135*/
+/* 53126*/ OPC_CheckPatternPredicate, 3, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())
+/* 53128*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CVT_S_D32_MM), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
+/* 53135*/ 0, /*End of Scope*/
+/* 53136*/ /*SwitchType*/ 26, MVT::f16,// ->53164
+/* 53138*/ OPC_Scope, 11, /*->53151*/ // 2 children in Scope
+/* 53140*/ OPC_CheckChild0Type, MVT::f32,
+/* 53142*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 53144*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSA_FP_ROUND_W_PSEUDO), 0,
+ MVT::f16, 1/*#Ops*/, 0,
+ // Src: (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
+/* 53151*/ /*Scope*/ 11, /*->53163*/
+/* 53152*/ OPC_CheckChild0Type, MVT::f64,
+/* 53154*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 53156*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSA_FP_ROUND_D_PSEUDO), 0,
+ MVT::f16, 1/*#Ops*/, 0,
+ // Src: (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
+/* 53163*/ 0, /*End of Scope*/
+/* 53164*/ 0, // EndSwitchType
+/* 53165*/ /*SwitchOpcode*/ 75, TARGET_VAL(ISD::FP_EXTEND),// ->53243
+/* 53168*/ OPC_RecordChild0, // #0 = $src
+/* 53169*/ OPC_SwitchType /*2 cases */, 59, MVT::f64,// ->53231
+/* 53172*/ OPC_Scope, 44, /*->53218*/ // 2 children in Scope
+/* 53174*/ OPC_CheckChild0Type, MVT::f32,
+/* 53176*/ OPC_Scope, 9, /*->53187*/ // 4 children in Scope
+/* 53178*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 53180*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CVT_D32_S), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+/* 53187*/ /*Scope*/ 9, /*->53197*/
+/* 53188*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())
+/* 53190*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CVT_D64_S), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+/* 53197*/ /*Scope*/ 9, /*->53207*/
+/* 53198*/ OPC_CheckPatternPredicate, 130, // (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())
+/* 53200*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CVT_D64_S_MM), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+/* 53207*/ /*Scope*/ 9, /*->53217*/
+/* 53208*/ OPC_CheckPatternPredicate, 3, // (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())
+/* 53210*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::CVT_D32_S_MM), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+/* 53217*/ 0, /*End of Scope*/
+/* 53218*/ /*Scope*/ 11, /*->53230*/
+/* 53219*/ OPC_CheckChild0Type, MVT::f16,
+/* 53221*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 53223*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSA_FP_EXTEND_D_PSEUDO), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) - Complexity = 3
+ // Dst: (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
+/* 53230*/ 0, /*End of Scope*/
+/* 53231*/ /*SwitchType*/ 9, MVT::f32,// ->53242
+/* 53233*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasMSA())
+/* 53235*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MSA_FP_EXTEND_W_PSEUDO), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) - Complexity = 3
+ // Dst: (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
+/* 53242*/ 0, // EndSwitchType
+/* 53243*/ /*SwitchOpcode*/ 33, TARGET_VAL(MipsISD::FSELECT),// ->53279
+/* 53246*/ OPC_RecordChild0, // #0 = $fd_in
+/* 53247*/ OPC_CheckChild0Type, MVT::f64,
+/* 53249*/ OPC_RecordChild1, // #1 = $ft
+/* 53250*/ OPC_RecordChild2, // #2 = $fs
+/* 53251*/ OPC_CheckType, MVT::f64,
+/* 53253*/ OPC_Scope, 11, /*->53266*/ // 2 children in Scope
+/* 53255*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())
+/* 53257*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEL_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 2, 1,
+ // Src: (MipsFSelect:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (SEL_D:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 53266*/ /*Scope*/ 11, /*->53278*/
+/* 53267*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())
+/* 53269*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SEL_D_MMR6), 0,
+ MVT::f64, 3/*#Ops*/, 0, 2, 1,
+ // Src: (MipsFSelect:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (SEL_D_MMR6:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+/* 53278*/ 0, /*End of Scope*/
+/* 53279*/ /*SwitchOpcode*/ 124|128,2/*380*/, TARGET_VAL(MipsISD::VSHF),// ->53663
+/* 53283*/ OPC_Scope, 88, /*->53373*/ // 4 children in Scope
+/* 53285*/ OPC_MoveChild0,
+/* 53286*/ OPC_CheckOpcode, TARGET_VAL(ISD::BITCAST),
+/* 53289*/ OPC_MoveChild0,
+/* 53290*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 53293*/ OPC_MoveChild0,
+/* 53294*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 53297*/ OPC_Scope, 36, /*->53335*/ // 2 children in Scope
+/* 53299*/ OPC_RecordChild0, // #0 = $rt
+/* 53300*/ OPC_CheckChild0Type, MVT::i32,
+/* 53302*/ OPC_CheckChild1Same, 0,
+/* 53304*/ OPC_CheckChild2Same, 0,
+/* 53306*/ OPC_CheckChild3Same, 0,
+/* 53308*/ OPC_MoveParent,
+/* 53309*/ OPC_MoveChild1,
+/* 53310*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 53313*/ OPC_MoveParent,
+/* 53314*/ OPC_CheckType, MVT::v4i32,
+/* 53316*/ OPC_MoveParent,
+/* 53317*/ OPC_CheckType, MVT::v2i64,
+/* 53319*/ OPC_MoveParent,
+/* 53320*/ OPC_RecordChild1, // #1 = $ws
+/* 53321*/ OPC_CheckChild2Same, 1,
+/* 53323*/ OPC_CheckType, MVT::v2i64,
+/* 53325*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53327*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLAT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsVSHF:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt), (build_vector:{ *:[v4i32] }))), MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 15
+ // Dst: (SPLAT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 53335*/ /*Scope*/ 36, /*->53372*/
+/* 53336*/ OPC_MoveParent,
+/* 53337*/ OPC_MoveChild1,
+/* 53338*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 53341*/ OPC_RecordChild0, // #0 = $rt
+/* 53342*/ OPC_CheckChild0Type, MVT::i32,
+/* 53344*/ OPC_CheckChild1Same, 0,
+/* 53346*/ OPC_CheckChild2Same, 0,
+/* 53348*/ OPC_CheckChild3Same, 0,
+/* 53350*/ OPC_MoveParent,
+/* 53351*/ OPC_CheckType, MVT::v4i32,
+/* 53353*/ OPC_MoveParent,
+/* 53354*/ OPC_CheckType, MVT::v2i64,
+/* 53356*/ OPC_MoveParent,
+/* 53357*/ OPC_RecordChild1, // #1 = $ws
+/* 53358*/ OPC_CheckChild2Same, 1,
+/* 53360*/ OPC_CheckType, MVT::v2i64,
+/* 53362*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53364*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLAT_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 0,
+ // Src: (MipsVSHF:{ *:[v2i64] } (bitconvert:{ *:[v2i64] } (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] }), (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt))), MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 15
+ // Dst: (SPLAT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 53372*/ 0, /*End of Scope*/
+/* 53373*/ /*Scope*/ 83, /*->53457*/
+/* 53374*/ OPC_RecordChild0, // #0 = $n
+/* 53375*/ OPC_SwitchType /*4 cases */, 18, MVT::v16i8,// ->53396
+/* 53378*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 53380*/ OPC_RecordChild1, // #1 = $ws
+/* 53381*/ OPC_CheckChild2Same, 1,
+/* 53383*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53385*/ OPC_CheckComplexPat, /*CP*/27, /*#*/0, // selectVSplatUimm4:$n #2
+/* 53388*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLATI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (MipsVSHF:{ *:[v16i8] } vsplati8_uimm4:{ *:[v16i8] }:$n, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (SPLATI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm4:{ *:[v16i8] }:$n)
+/* 53396*/ /*SwitchType*/ 18, MVT::v8i16,// ->53416
+/* 53398*/ OPC_CheckChild0Type, MVT::v8i16,
+/* 53400*/ OPC_RecordChild1, // #1 = $ws
+/* 53401*/ OPC_CheckChild2Same, 1,
+/* 53403*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53405*/ OPC_CheckComplexPat, /*CP*/28, /*#*/0, // selectVSplatUimm3:$n #2
+/* 53408*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLATI_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (MipsVSHF:{ *:[v8i16] } vsplati16_uimm3:{ *:[v8i16] }:$n, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (SPLATI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm3:{ *:[v8i16] }:$n)
+/* 53416*/ /*SwitchType*/ 18, MVT::v4i32,// ->53436
+/* 53418*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 53420*/ OPC_RecordChild1, // #1 = $ws
+/* 53421*/ OPC_CheckChild2Same, 1,
+/* 53423*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53425*/ OPC_CheckComplexPat, /*CP*/29, /*#*/0, // selectVSplatUimm2:$n #2
+/* 53428*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLATI_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (MipsVSHF:{ *:[v4i32] } vsplati32_uimm2:{ *:[v4i32] }:$n, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (SPLATI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm2:{ *:[v4i32] }:$n)
+/* 53436*/ /*SwitchType*/ 18, MVT::v2i64,// ->53456
+/* 53438*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 53440*/ OPC_RecordChild1, // #1 = $ws
+/* 53441*/ OPC_CheckChild2Same, 1,
+/* 53443*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53445*/ OPC_CheckComplexPat, /*CP*/30, /*#*/0, // selectVSplatUimm1:$n #2
+/* 53448*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLATI_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (MipsVSHF:{ *:[v2i64] } vsplati64_uimm1:{ *:[v2i64] }:$n, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (SPLATI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm1:{ *:[v2i64] }:$n)
+/* 53456*/ 0, // EndSwitchType
+/* 53457*/ /*Scope*/ 3|128,1/*131*/, /*->53590*/
+/* 53459*/ OPC_MoveChild0,
+/* 53460*/ OPC_CheckOpcode, TARGET_VAL(ISD::BUILD_VECTOR),
+/* 53463*/ OPC_RecordChild0, // #0 = $rt
+/* 53464*/ OPC_CheckChild0Type, MVT::i32,
+/* 53466*/ OPC_CheckChild1Same, 0,
+/* 53468*/ OPC_CheckChild2Same, 0,
+/* 53470*/ OPC_CheckChild3Same, 0,
+/* 53472*/ OPC_Scope, 96, /*->53570*/ // 2 children in Scope
+/* 53474*/ OPC_MoveChild4,
+/* 53475*/ OPC_CheckSame, 0,
+/* 53477*/ OPC_MoveParent,
+/* 53478*/ OPC_MoveChild5,
+/* 53479*/ OPC_CheckSame, 0,
+/* 53481*/ OPC_MoveParent,
+/* 53482*/ OPC_MoveChild6,
+/* 53483*/ OPC_CheckSame, 0,
+/* 53485*/ OPC_MoveParent,
+/* 53486*/ OPC_MoveChild7,
+/* 53487*/ OPC_CheckSame, 0,
+/* 53489*/ OPC_MoveParent,
+/* 53490*/ OPC_Scope, 58, /*->53550*/ // 2 children in Scope
+/* 53492*/ OPC_MoveChild, 8,
+/* 53494*/ OPC_CheckSame, 0,
+/* 53496*/ OPC_MoveParent,
+/* 53497*/ OPC_MoveChild, 9,
+/* 53499*/ OPC_CheckSame, 0,
+/* 53501*/ OPC_MoveParent,
+/* 53502*/ OPC_MoveChild, 10,
+/* 53504*/ OPC_CheckSame, 0,
+/* 53506*/ OPC_MoveParent,
+/* 53507*/ OPC_MoveChild, 11,
+/* 53509*/ OPC_CheckSame, 0,
+/* 53511*/ OPC_MoveParent,
+/* 53512*/ OPC_MoveChild, 12,
+/* 53514*/ OPC_CheckSame, 0,
+/* 53516*/ OPC_MoveParent,
+/* 53517*/ OPC_MoveChild, 13,
+/* 53519*/ OPC_CheckSame, 0,
+/* 53521*/ OPC_MoveParent,
+/* 53522*/ OPC_MoveChild, 14,
+/* 53524*/ OPC_CheckSame, 0,
+/* 53526*/ OPC_MoveParent,
+/* 53527*/ OPC_MoveChild, 15,
+/* 53529*/ OPC_CheckSame, 0,
+/* 53531*/ OPC_MoveParent,
+/* 53532*/ OPC_CheckType, MVT::v16i8,
+/* 53534*/ OPC_MoveParent,
+/* 53535*/ OPC_RecordChild1, // #1 = $ws
+/* 53536*/ OPC_CheckChild2Same, 1,
+/* 53538*/ OPC_CheckType, MVT::v16i8,
+/* 53540*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53542*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLAT_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 0,
+ // Src: (MipsVSHF:{ *:[v16i8] } (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt), MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 6
+ // Dst: (SPLAT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 53550*/ /*Scope*/ 18, /*->53569*/
+/* 53551*/ OPC_CheckType, MVT::v8i16,
+/* 53553*/ OPC_MoveParent,
+/* 53554*/ OPC_RecordChild1, // #1 = $ws
+/* 53555*/ OPC_CheckChild2Same, 1,
+/* 53557*/ OPC_CheckType, MVT::v8i16,
+/* 53559*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53561*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLAT_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 0,
+ // Src: (MipsVSHF:{ *:[v8i16] } (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt), MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 6
+ // Dst: (SPLAT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 53569*/ 0, /*End of Scope*/
+/* 53570*/ /*Scope*/ 18, /*->53589*/
+/* 53571*/ OPC_CheckType, MVT::v4i32,
+/* 53573*/ OPC_MoveParent,
+/* 53574*/ OPC_RecordChild1, // #1 = $ws
+/* 53575*/ OPC_CheckChild2Same, 1,
+/* 53577*/ OPC_CheckType, MVT::v4i32,
+/* 53579*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53581*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SPLAT_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 0,
+ // Src: (MipsVSHF:{ *:[v4i32] } (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rt), MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 6
+ // Dst: (SPLAT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+/* 53589*/ 0, /*End of Scope*/
+/* 53590*/ /*Scope*/ 71, /*->53662*/
+/* 53591*/ OPC_RecordChild0, // #0 = $wd_in
+/* 53592*/ OPC_SwitchType /*4 cases */, 15, MVT::v16i8,// ->53610
+/* 53595*/ OPC_CheckChild0Type, MVT::v16i8,
+/* 53597*/ OPC_RecordChild1, // #1 = $ws
+/* 53598*/ OPC_RecordChild2, // #2 = $wt
+/* 53599*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53601*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::VSHF_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsVSHF:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (VSHF_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 53610*/ /*SwitchType*/ 15, MVT::v8i16,// ->53627
+/* 53612*/ OPC_CheckChild0Type, MVT::v8i16,
+/* 53614*/ OPC_RecordChild1, // #1 = $ws
+/* 53615*/ OPC_RecordChild2, // #2 = $wt
+/* 53616*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53618*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::VSHF_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsVSHF:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (VSHF_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 53627*/ /*SwitchType*/ 15, MVT::v4i32,// ->53644
+/* 53629*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 53631*/ OPC_RecordChild1, // #1 = $ws
+/* 53632*/ OPC_RecordChild2, // #2 = $wt
+/* 53633*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53635*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::VSHF_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsVSHF:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (VSHF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 53644*/ /*SwitchType*/ 15, MVT::v2i64,// ->53661
+/* 53646*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 53648*/ OPC_RecordChild1, // #1 = $ws
+/* 53649*/ OPC_RecordChild2, // #2 = $wt
+/* 53650*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53652*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::VSHF_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsVSHF:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (VSHF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 53661*/ 0, // EndSwitchType
+/* 53662*/ 0, /*End of Scope*/
+/* 53663*/ /*SwitchOpcode*/ 4|128,1/*132*/, TARGET_VAL(MipsISD::INSVE),// ->53799
+/* 53667*/ OPC_RecordChild0, // #0 = $wd_in
+/* 53668*/ OPC_RecordChild1, // #1 = $n
+/* 53669*/ OPC_MoveChild1,
+/* 53670*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 53673*/ OPC_Scope, 30, /*->53705*/ // 4 children in Scope
+/* 53675*/ OPC_CheckPredicate, 31, // Predicate_immZExt4
+/* 53677*/ OPC_MoveParent,
+/* 53678*/ OPC_RecordChild2, // #2 = $ws
+/* 53679*/ OPC_RecordChild3, // #3 = $n2
+/* 53680*/ OPC_MoveChild3,
+/* 53681*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 53684*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 53686*/ OPC_MoveParent,
+/* 53687*/ OPC_CheckType, MVT::v16i8,
+/* 53689*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53691*/ OPC_EmitConvertToTarget, 1,
+/* 53693*/ OPC_EmitConvertToTarget, 3,
+/* 53695*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSVE_B), 0,
+ MVT::v16i8, 4/*#Ops*/, 0, 4, 2, 5,
+ // Src: (MipsINSVE:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$n, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immz>>:$n2) - Complexity = 11
+ // Dst: (INSVE_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (imm:{ *:[i32] }):$n, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$n2)
+/* 53705*/ /*Scope*/ 30, /*->53736*/
+/* 53706*/ OPC_CheckPredicate, 32, // Predicate_immZExt3
+/* 53708*/ OPC_MoveParent,
+/* 53709*/ OPC_RecordChild2, // #2 = $ws
+/* 53710*/ OPC_RecordChild3, // #3 = $n2
+/* 53711*/ OPC_MoveChild3,
+/* 53712*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 53715*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 53717*/ OPC_MoveParent,
+/* 53718*/ OPC_CheckType, MVT::v8i16,
+/* 53720*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53722*/ OPC_EmitConvertToTarget, 1,
+/* 53724*/ OPC_EmitConvertToTarget, 3,
+/* 53726*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSVE_H), 0,
+ MVT::v8i16, 4/*#Ops*/, 0, 4, 2, 5,
+ // Src: (MipsINSVE:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$n, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immz>>:$n2) - Complexity = 11
+ // Dst: (INSVE_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (imm:{ *:[i32] }):$n, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$n2)
+/* 53736*/ /*Scope*/ 30, /*->53767*/
+/* 53737*/ OPC_CheckPredicate, 33, // Predicate_immZExt2
+/* 53739*/ OPC_MoveParent,
+/* 53740*/ OPC_RecordChild2, // #2 = $ws
+/* 53741*/ OPC_RecordChild3, // #3 = $n2
+/* 53742*/ OPC_MoveChild3,
+/* 53743*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 53746*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 53748*/ OPC_MoveParent,
+/* 53749*/ OPC_CheckType, MVT::v4i32,
+/* 53751*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53753*/ OPC_EmitConvertToTarget, 1,
+/* 53755*/ OPC_EmitConvertToTarget, 3,
+/* 53757*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSVE_W), 0,
+ MVT::v4i32, 4/*#Ops*/, 0, 4, 2, 5,
+ // Src: (MipsINSVE:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$n, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immz>>:$n2) - Complexity = 11
+ // Dst: (INSVE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (imm:{ *:[i32] }):$n, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$n2)
+/* 53767*/ /*Scope*/ 30, /*->53798*/
+/* 53768*/ OPC_CheckPredicate, 37, // Predicate_immZExt1
+/* 53770*/ OPC_MoveParent,
+/* 53771*/ OPC_RecordChild2, // #2 = $ws
+/* 53772*/ OPC_RecordChild3, // #3 = $n2
+/* 53773*/ OPC_MoveChild3,
+/* 53774*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 53777*/ OPC_CheckPredicate, 22, // Predicate_immz
+/* 53779*/ OPC_MoveParent,
+/* 53780*/ OPC_CheckType, MVT::v2i64,
+/* 53782*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53784*/ OPC_EmitConvertToTarget, 1,
+/* 53786*/ OPC_EmitConvertToTarget, 3,
+/* 53788*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSVE_D), 0,
+ MVT::v2i64, 4/*#Ops*/, 0, 4, 2, 5,
+ // Src: (MipsINSVE:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (imm:{ *:[i32] })<<P:Predicate_immZExt1>>:$n, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immz>>:$n2) - Complexity = 11
+ // Dst: (INSVE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (imm:{ *:[i32] }):$n, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$n2)
+/* 53798*/ 0, /*End of Scope*/
+/* 53799*/ /*SwitchOpcode*/ 64|128,2/*320*/, TARGET_VAL(ISD::VSELECT),// ->54123
+/* 53803*/ OPC_RecordChild0, // #0 = $m
+/* 53804*/ OPC_Scope, 36, /*->53842*/ // 9 children in Scope
+/* 53806*/ OPC_RecordChild1, // #1 = $ws
+/* 53807*/ OPC_RecordChild2, // #2 = $wd_in
+/* 53808*/ OPC_SwitchType /*2 cases */, 14, MVT::v16i8,// ->53825
+/* 53811*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53813*/ OPC_CheckComplexPat, /*CP*/31, /*#*/0, // selectVSplatMaskL:$m #3
+/* 53816*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSLI_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v16i8] } vsplat_maskl_bits_uimm3:{ *:[v16i8] }:$m, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) - Complexity = 9
+ // Dst: (BINSLI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_maskl_bits_uimm3:{ *:[v16i8] }:$m)
+/* 53825*/ /*SwitchType*/ 14, MVT::v8i16,// ->53841
+/* 53827*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53829*/ OPC_CheckComplexPat, /*CP*/32, /*#*/0, // selectVSplatMaskL:$m #3
+/* 53832*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSLI_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v8i16] } vsplat_maskl_bits_uimm4:{ *:[v8i16] }:$m, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wd_in) - Complexity = 9
+ // Dst: (BINSLI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_maskl_bits_uimm4:{ *:[v8i16] }:$m)
+/* 53841*/ 0, // EndSwitchType
+/* 53842*/ /*Scope*/ 20, /*->53863*/
+/* 53843*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 53845*/ OPC_RecordChild1, // #1 = $ws
+/* 53846*/ OPC_RecordChild2, // #2 = $wd_in
+/* 53847*/ OPC_CheckType, MVT::v4i32,
+/* 53849*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53851*/ OPC_CheckComplexPat, /*CP*/33, /*#*/0, // selectVSplatMaskL:$m #3
+/* 53854*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSLI_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v4i32] } vsplat_maskl_bits_uimm5:{ *:[v4i32] }:$m, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wd_in) - Complexity = 9
+ // Dst: (BINSLI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_maskl_bits_uimm5:{ *:[v4i32] }:$m)
+/* 53863*/ /*Scope*/ 20, /*->53884*/
+/* 53864*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 53866*/ OPC_RecordChild1, // #1 = $ws
+/* 53867*/ OPC_RecordChild2, // #2 = $wd_in
+/* 53868*/ OPC_CheckType, MVT::v2i64,
+/* 53870*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53872*/ OPC_CheckComplexPat, /*CP*/34, /*#*/0, // selectVSplatMaskL:$m #3
+/* 53875*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSLI_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v2i64] } vsplat_maskl_bits_uimm6:{ *:[v2i64] }:$m, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wd_in) - Complexity = 9
+ // Dst: (BINSLI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_maskl_bits_uimm6:{ *:[v2i64] }:$m)
+/* 53884*/ /*Scope*/ 36, /*->53921*/
+/* 53885*/ OPC_RecordChild1, // #1 = $ws
+/* 53886*/ OPC_RecordChild2, // #2 = $wd_in
+/* 53887*/ OPC_SwitchType /*2 cases */, 14, MVT::v16i8,// ->53904
+/* 53890*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53892*/ OPC_CheckComplexPat, /*CP*/35, /*#*/0, // selectVSplatMaskR:$m #3
+/* 53895*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSRI_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v16i8] } vsplat_maskr_bits_uimm3:{ *:[v16i8] }:$m, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) - Complexity = 9
+ // Dst: (BINSRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, vsplat_maskr_bits_uimm3:{ *:[v16i8] }:$m)
+/* 53904*/ /*SwitchType*/ 14, MVT::v8i16,// ->53920
+/* 53906*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53908*/ OPC_CheckComplexPat, /*CP*/36, /*#*/0, // selectVSplatMaskR:$m #3
+/* 53911*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSRI_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v8i16] } vsplat_maskr_bits_uimm4:{ *:[v8i16] }:$m, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wd_in) - Complexity = 9
+ // Dst: (BINSRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, vsplat_maskr_bits_uimm4:{ *:[v8i16] }:$m)
+/* 53920*/ 0, // EndSwitchType
+/* 53921*/ /*Scope*/ 20, /*->53942*/
+/* 53922*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 53924*/ OPC_RecordChild1, // #1 = $ws
+/* 53925*/ OPC_RecordChild2, // #2 = $wd_in
+/* 53926*/ OPC_CheckType, MVT::v4i32,
+/* 53928*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53930*/ OPC_CheckComplexPat, /*CP*/37, /*#*/0, // selectVSplatMaskR:$m #3
+/* 53933*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSRI_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v4i32] } vsplat_maskr_bits_uimm5:{ *:[v4i32] }:$m, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wd_in) - Complexity = 9
+ // Dst: (BINSRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, vsplat_maskr_bits_uimm5:{ *:[v4i32] }:$m)
+/* 53942*/ /*Scope*/ 20, /*->53963*/
+/* 53943*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 53945*/ OPC_RecordChild1, // #1 = $ws
+/* 53946*/ OPC_RecordChild2, // #2 = $wd_in
+/* 53947*/ OPC_CheckType, MVT::v2i64,
+/* 53949*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53951*/ OPC_CheckComplexPat, /*CP*/38, /*#*/0, // selectVSplatMaskR:$m #3
+/* 53954*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BINSRI_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v2i64] } vsplat_maskr_bits_uimm6:{ *:[v2i64] }:$m, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wd_in) - Complexity = 9
+ // Dst: (BINSRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, vsplat_maskr_bits_uimm6:{ *:[v2i64] }:$m)
+/* 53963*/ /*Scope*/ 92, /*->54056*/
+/* 53964*/ OPC_RecordChild1, // #1 = $ws
+/* 53965*/ OPC_RecordChild2, // #2 = $wd_in
+/* 53966*/ OPC_SwitchType /*2 cases */, 73, MVT::v16i8,// ->54042
+/* 53969*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 53971*/ OPC_Scope, 25, /*->53998*/ // 5 children in Scope
+/* 53973*/ OPC_CheckComplexPat, /*CP*/14, /*#*/0, // selectVSplatUimm8:$u8 #3
+/* 53976*/ OPC_Scope, 9, /*->53987*/ // 2 children in Scope
+/* 53978*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BMNZI_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 2, 1, 3,
+ // Src: (vselect:{ *:[v16i8] } vsplati8_uimm8:{ *:[v16i8] }:$u8, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) - Complexity = 9
+ // Dst: (BMNZI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 53987*/ /*Scope*/ 9, /*->53997*/
+/* 53988*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BMZI_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 1, 2, 3,
+ // Src: (vselect:{ *:[v16i8] } vsplati8_uimm8:{ *:[v16i8] }:$u8, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (BMZI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 53997*/ 0, /*End of Scope*/
+/* 53998*/ /*Scope*/ 12, /*->54011*/
+/* 53999*/ OPC_CheckComplexPat, /*CP*/14, /*#*/1, // selectVSplatUimm8:$u8 #3
+/* 54002*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSELI_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 2, 3,
+ // Src: (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, vsplati8_uimm8:{ *:[v16i8] }:$u8, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (BSELI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 54011*/ /*Scope*/ 9, /*->54021*/
+/* 54012*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BMNZ_V), 0,
+ MVT::v16i8, 3/*#Ops*/, 2, 1, 0,
+ // Src: (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in) - Complexity = 3
+ // Dst: (BMNZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 54021*/ /*Scope*/ 9, /*->54031*/
+/* 54022*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BMZ_V), 0,
+ MVT::v16i8, 3/*#Ops*/, 1, 2, 0,
+ // Src: (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 3
+ // Dst: (BMZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 54031*/ /*Scope*/ 9, /*->54041*/
+/* 54032*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSEL_V), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 3
+ // Dst: (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 54041*/ 0, /*End of Scope*/
+/* 54042*/ /*SwitchType*/ 11, MVT::v8i16,// ->54055
+/* 54044*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54046*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSEL_H_PSEUDO), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vselect:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$wt, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 3
+ // Dst: (BSEL_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 54055*/ 0, // EndSwitchType
+/* 54056*/ /*Scope*/ 32, /*->54089*/
+/* 54057*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 54059*/ OPC_RecordChild1, // #1 = $wt
+/* 54060*/ OPC_RecordChild2, // #2 = $ws
+/* 54061*/ OPC_SwitchType /*2 cases */, 11, MVT::v4i32,// ->54075
+/* 54064*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54066*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSEL_W_PSEUDO), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vselect:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$wt, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 3
+ // Dst: (BSEL_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 54075*/ /*SwitchType*/ 11, MVT::v4f32,// ->54088
+/* 54077*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54079*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSEL_FW_PSEUDO), 0,
+ MVT::v4f32, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vselect:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$wt, MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 3
+ // Dst: (BSEL_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 54088*/ 0, // EndSwitchType
+/* 54089*/ /*Scope*/ 32, /*->54122*/
+/* 54090*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 54092*/ OPC_RecordChild1, // #1 = $wt
+/* 54093*/ OPC_RecordChild2, // #2 = $ws
+/* 54094*/ OPC_SwitchType /*2 cases */, 11, MVT::v2i64,// ->54108
+/* 54097*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54099*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSEL_D_PSEUDO), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vselect:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$wt, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 3
+ // Dst: (BSEL_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 54108*/ /*SwitchType*/ 11, MVT::v2f64,// ->54121
+/* 54110*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54112*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::BSEL_FD_PSEUDO), 0,
+ MVT::v2f64, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vselect:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$wt, MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 3
+ // Dst: (BSEL_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 54121*/ 0, // EndSwitchType
+/* 54122*/ 0, /*End of Scope*/
+/* 54123*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::SMAX),// ->54287
+/* 54127*/ OPC_RecordChild0, // #0 = $ws
+/* 54128*/ OPC_RecordChild1, // #1 = $imm
+/* 54129*/ OPC_SwitchType /*4 cases */, 37, MVT::v16i8,// ->54169
+/* 54132*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54134*/ OPC_Scope, 11, /*->54147*/ // 3 children in Scope
+/* 54136*/ OPC_CheckComplexPat, /*CP*/20, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 54139*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm) - Complexity = 9
+ // Dst: (MAXI_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm)
+/* 54147*/ /*Scope*/ 11, /*->54159*/
+/* 54148*/ OPC_CheckComplexPat, /*CP*/20, /*#*/0, // selectVSplatSimm5:$imm #2
+/* 54151*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (smax:{ *:[v16i8] } vsplati8_simm5:{ *:[v16i8] }:$imm, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (MAXI_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm)
+/* 54159*/ /*Scope*/ 8, /*->54168*/
+/* 54160*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 54168*/ 0, /*End of Scope*/
+/* 54169*/ /*SwitchType*/ 37, MVT::v8i16,// ->54208
+/* 54171*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54173*/ OPC_Scope, 11, /*->54186*/ // 3 children in Scope
+/* 54175*/ OPC_CheckComplexPat, /*CP*/21, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 54178*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm) - Complexity = 9
+ // Dst: (MAXI_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm)
+/* 54186*/ /*Scope*/ 11, /*->54198*/
+/* 54187*/ OPC_CheckComplexPat, /*CP*/21, /*#*/0, // selectVSplatSimm5:$imm #2
+/* 54190*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (smax:{ *:[v8i16] } vsplati16_simm5:{ *:[v8i16] }:$imm, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (MAXI_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm)
+/* 54198*/ /*Scope*/ 8, /*->54207*/
+/* 54199*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 54207*/ 0, /*End of Scope*/
+/* 54208*/ /*SwitchType*/ 37, MVT::v4i32,// ->54247
+/* 54210*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54212*/ OPC_Scope, 11, /*->54225*/ // 3 children in Scope
+/* 54214*/ OPC_CheckComplexPat, /*CP*/22, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 54217*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm) - Complexity = 9
+ // Dst: (MAXI_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm)
+/* 54225*/ /*Scope*/ 11, /*->54237*/
+/* 54226*/ OPC_CheckComplexPat, /*CP*/22, /*#*/0, // selectVSplatSimm5:$imm #2
+/* 54229*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (smax:{ *:[v4i32] } vsplati32_simm5:{ *:[v4i32] }:$imm, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (MAXI_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm)
+/* 54237*/ /*Scope*/ 8, /*->54246*/
+/* 54238*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 54246*/ 0, /*End of Scope*/
+/* 54247*/ /*SwitchType*/ 37, MVT::v2i64,// ->54286
+/* 54249*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54251*/ OPC_Scope, 11, /*->54264*/ // 3 children in Scope
+/* 54253*/ OPC_CheckComplexPat, /*CP*/23, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 54256*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm) - Complexity = 9
+ // Dst: (MAXI_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm)
+/* 54264*/ /*Scope*/ 11, /*->54276*/
+/* 54265*/ OPC_CheckComplexPat, /*CP*/23, /*#*/0, // selectVSplatSimm5:$imm #2
+/* 54268*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (smax:{ *:[v2i64] } vsplati64_simm5:{ *:[v2i64] }:$imm, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (MAXI_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm)
+/* 54276*/ /*Scope*/ 8, /*->54285*/
+/* 54277*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 54285*/ 0, /*End of Scope*/
+/* 54286*/ 0, // EndSwitchType
+/* 54287*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::UMAX),// ->54451
+/* 54291*/ OPC_RecordChild0, // #0 = $ws
+/* 54292*/ OPC_RecordChild1, // #1 = $imm
+/* 54293*/ OPC_SwitchType /*4 cases */, 37, MVT::v16i8,// ->54333
+/* 54296*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54298*/ OPC_Scope, 11, /*->54311*/ // 3 children in Scope
+/* 54300*/ OPC_CheckComplexPat, /*CP*/16, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 54303*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm) - Complexity = 9
+ // Dst: (MAXI_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 54311*/ /*Scope*/ 11, /*->54323*/
+/* 54312*/ OPC_CheckComplexPat, /*CP*/16, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 54315*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (umax:{ *:[v16i8] } vsplati8_uimm5:{ *:[v16i8] }:$imm, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (MAXI_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 54323*/ /*Scope*/ 8, /*->54332*/
+/* 54324*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 54332*/ 0, /*End of Scope*/
+/* 54333*/ /*SwitchType*/ 37, MVT::v8i16,// ->54372
+/* 54335*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54337*/ OPC_Scope, 11, /*->54350*/ // 3 children in Scope
+/* 54339*/ OPC_CheckComplexPat, /*CP*/17, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 54342*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm) - Complexity = 9
+ // Dst: (MAXI_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 54350*/ /*Scope*/ 11, /*->54362*/
+/* 54351*/ OPC_CheckComplexPat, /*CP*/17, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 54354*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (umax:{ *:[v8i16] } vsplati16_uimm5:{ *:[v8i16] }:$imm, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (MAXI_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 54362*/ /*Scope*/ 8, /*->54371*/
+/* 54363*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 54371*/ 0, /*End of Scope*/
+/* 54372*/ /*SwitchType*/ 37, MVT::v4i32,// ->54411
+/* 54374*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54376*/ OPC_Scope, 11, /*->54389*/ // 3 children in Scope
+/* 54378*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 54381*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm) - Complexity = 9
+ // Dst: (MAXI_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 54389*/ /*Scope*/ 11, /*->54401*/
+/* 54390*/ OPC_CheckComplexPat, /*CP*/18, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 54393*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (umax:{ *:[v4i32] } vsplati32_uimm5:{ *:[v4i32] }:$imm, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (MAXI_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 54401*/ /*Scope*/ 8, /*->54410*/
+/* 54402*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 54410*/ 0, /*End of Scope*/
+/* 54411*/ /*SwitchType*/ 37, MVT::v2i64,// ->54450
+/* 54413*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54415*/ OPC_Scope, 11, /*->54428*/ // 3 children in Scope
+/* 54417*/ OPC_CheckComplexPat, /*CP*/19, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 54420*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm) - Complexity = 9
+ // Dst: (MAXI_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 54428*/ /*Scope*/ 11, /*->54440*/
+/* 54429*/ OPC_CheckComplexPat, /*CP*/19, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 54432*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAXI_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (umax:{ *:[v2i64] } vsplati64_uimm5:{ *:[v2i64] }:$imm, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (MAXI_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 54440*/ /*Scope*/ 8, /*->54449*/
+/* 54441*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MAX_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 54449*/ 0, /*End of Scope*/
+/* 54450*/ 0, // EndSwitchType
+/* 54451*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::SMIN),// ->54615
+/* 54455*/ OPC_RecordChild0, // #0 = $ws
+/* 54456*/ OPC_RecordChild1, // #1 = $imm
+/* 54457*/ OPC_SwitchType /*4 cases */, 37, MVT::v16i8,// ->54497
+/* 54460*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54462*/ OPC_Scope, 11, /*->54475*/ // 3 children in Scope
+/* 54464*/ OPC_CheckComplexPat, /*CP*/20, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 54467*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm) - Complexity = 9
+ // Dst: (MINI_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm)
+/* 54475*/ /*Scope*/ 11, /*->54487*/
+/* 54476*/ OPC_CheckComplexPat, /*CP*/20, /*#*/0, // selectVSplatSimm5:$imm #2
+/* 54479*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (smin:{ *:[v16i8] } vsplati8_simm5:{ *:[v16i8] }:$imm, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (MINI_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_simm5:{ *:[v16i8] }:$imm)
+/* 54487*/ /*Scope*/ 8, /*->54496*/
+/* 54488*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_S_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 54496*/ 0, /*End of Scope*/
+/* 54497*/ /*SwitchType*/ 37, MVT::v8i16,// ->54536
+/* 54499*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54501*/ OPC_Scope, 11, /*->54514*/ // 3 children in Scope
+/* 54503*/ OPC_CheckComplexPat, /*CP*/21, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 54506*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm) - Complexity = 9
+ // Dst: (MINI_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm)
+/* 54514*/ /*Scope*/ 11, /*->54526*/
+/* 54515*/ OPC_CheckComplexPat, /*CP*/21, /*#*/0, // selectVSplatSimm5:$imm #2
+/* 54518*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (smin:{ *:[v8i16] } vsplati16_simm5:{ *:[v8i16] }:$imm, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (MINI_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_simm5:{ *:[v8i16] }:$imm)
+/* 54526*/ /*Scope*/ 8, /*->54535*/
+/* 54527*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_S_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 54535*/ 0, /*End of Scope*/
+/* 54536*/ /*SwitchType*/ 37, MVT::v4i32,// ->54575
+/* 54538*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54540*/ OPC_Scope, 11, /*->54553*/ // 3 children in Scope
+/* 54542*/ OPC_CheckComplexPat, /*CP*/22, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 54545*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm) - Complexity = 9
+ // Dst: (MINI_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm)
+/* 54553*/ /*Scope*/ 11, /*->54565*/
+/* 54554*/ OPC_CheckComplexPat, /*CP*/22, /*#*/0, // selectVSplatSimm5:$imm #2
+/* 54557*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (smin:{ *:[v4i32] } vsplati32_simm5:{ *:[v4i32] }:$imm, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (MINI_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_simm5:{ *:[v4i32] }:$imm)
+/* 54565*/ /*Scope*/ 8, /*->54574*/
+/* 54566*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_S_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 54574*/ 0, /*End of Scope*/
+/* 54575*/ /*SwitchType*/ 37, MVT::v2i64,// ->54614
+/* 54577*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54579*/ OPC_Scope, 11, /*->54592*/ // 3 children in Scope
+/* 54581*/ OPC_CheckComplexPat, /*CP*/23, /*#*/1, // selectVSplatSimm5:$imm #2
+/* 54584*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm) - Complexity = 9
+ // Dst: (MINI_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm)
+/* 54592*/ /*Scope*/ 11, /*->54604*/
+/* 54593*/ OPC_CheckComplexPat, /*CP*/23, /*#*/0, // selectVSplatSimm5:$imm #2
+/* 54596*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (smin:{ *:[v2i64] } vsplati64_simm5:{ *:[v2i64] }:$imm, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (MINI_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_simm5:{ *:[v2i64] }:$imm)
+/* 54604*/ /*Scope*/ 8, /*->54613*/
+/* 54605*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_S_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 54613*/ 0, /*End of Scope*/
+/* 54614*/ 0, // EndSwitchType
+/* 54615*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::UMIN),// ->54779
+/* 54619*/ OPC_RecordChild0, // #0 = $ws
+/* 54620*/ OPC_RecordChild1, // #1 = $imm
+/* 54621*/ OPC_SwitchType /*4 cases */, 37, MVT::v16i8,// ->54661
+/* 54624*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54626*/ OPC_Scope, 11, /*->54639*/ // 3 children in Scope
+/* 54628*/ OPC_CheckComplexPat, /*CP*/16, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 54631*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm) - Complexity = 9
+ // Dst: (MINI_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 54639*/ /*Scope*/ 11, /*->54651*/
+/* 54640*/ OPC_CheckComplexPat, /*CP*/16, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 54643*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (umin:{ *:[v16i8] } vsplati8_uimm5:{ *:[v16i8] }:$imm, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (MINI_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm5:{ *:[v16i8] }:$imm)
+/* 54651*/ /*Scope*/ 8, /*->54660*/
+/* 54652*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_U_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 54660*/ 0, /*End of Scope*/
+/* 54661*/ /*SwitchType*/ 37, MVT::v8i16,// ->54700
+/* 54663*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54665*/ OPC_Scope, 11, /*->54678*/ // 3 children in Scope
+/* 54667*/ OPC_CheckComplexPat, /*CP*/17, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 54670*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 2,
+ // Src: (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm) - Complexity = 9
+ // Dst: (MINI_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 54678*/ /*Scope*/ 11, /*->54690*/
+/* 54679*/ OPC_CheckComplexPat, /*CP*/17, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 54682*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (umin:{ *:[v8i16] } vsplati16_uimm5:{ *:[v8i16] }:$imm, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 9
+ // Dst: (MINI_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, vsplati16_uimm5:{ *:[v8i16] }:$imm)
+/* 54690*/ /*Scope*/ 8, /*->54699*/
+/* 54691*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_U_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 54699*/ 0, /*End of Scope*/
+/* 54700*/ /*SwitchType*/ 37, MVT::v4i32,// ->54739
+/* 54702*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54704*/ OPC_Scope, 11, /*->54717*/ // 3 children in Scope
+/* 54706*/ OPC_CheckComplexPat, /*CP*/18, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 54709*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 2,
+ // Src: (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm) - Complexity = 9
+ // Dst: (MINI_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 54717*/ /*Scope*/ 11, /*->54729*/
+/* 54718*/ OPC_CheckComplexPat, /*CP*/18, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 54721*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (umin:{ *:[v4i32] } vsplati32_uimm5:{ *:[v4i32] }:$imm, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 9
+ // Dst: (MINI_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
+/* 54729*/ /*Scope*/ 8, /*->54738*/
+/* 54730*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_U_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 54738*/ 0, /*End of Scope*/
+/* 54739*/ /*SwitchType*/ 37, MVT::v2i64,// ->54778
+/* 54741*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54743*/ OPC_Scope, 11, /*->54756*/ // 3 children in Scope
+/* 54745*/ OPC_CheckComplexPat, /*CP*/19, /*#*/1, // selectVSplatUimm5:$imm #2
+/* 54748*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 2,
+ // Src: (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm) - Complexity = 9
+ // Dst: (MINI_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 54756*/ /*Scope*/ 11, /*->54768*/
+/* 54757*/ OPC_CheckComplexPat, /*CP*/19, /*#*/0, // selectVSplatUimm5:$imm #2
+/* 54760*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MINI_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 1, 2,
+ // Src: (umin:{ *:[v2i64] } vsplati64_uimm5:{ *:[v2i64] }:$imm, MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 9
+ // Dst: (MINI_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, vsplati64_uimm5:{ *:[v2i64] }:$imm)
+/* 54768*/ /*Scope*/ 8, /*->54777*/
+/* 54769*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MIN_U_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 54777*/ 0, /*End of Scope*/
+/* 54778*/ 0, // EndSwitchType
+/* 54779*/ /*SwitchOpcode*/ 79, TARGET_VAL(MipsISD::VNOR),// ->54861
+/* 54782*/ OPC_RecordChild0, // #0 = $ws
+/* 54783*/ OPC_RecordChild1, // #1 = $u8
+/* 54784*/ OPC_SwitchType /*4 cases */, 37, MVT::v16i8,// ->54824
+/* 54787*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54789*/ OPC_Scope, 11, /*->54802*/ // 3 children in Scope
+/* 54791*/ OPC_CheckComplexPat, /*CP*/14, /*#*/1, // selectVSplatUimm8:$u8 #2
+/* 54794*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NORI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 2,
+ // Src: (MipsVNOR:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8) - Complexity = 9
+ // Dst: (NORI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 54802*/ /*Scope*/ 11, /*->54814*/
+/* 54803*/ OPC_CheckComplexPat, /*CP*/14, /*#*/0, // selectVSplatUimm8:$u8 #2
+/* 54806*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NORI_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (MipsVNOR:{ *:[v16i8] } vsplati8_uimm8:{ *:[v16i8] }:$u8, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 9
+ // Dst: (NORI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, vsplati8_uimm8:{ *:[v16i8] }:$u8)
+/* 54814*/ /*Scope*/ 8, /*->54823*/
+/* 54815*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_V), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (MipsVNOR:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (NOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 54823*/ 0, /*End of Scope*/
+/* 54824*/ /*SwitchType*/ 10, MVT::v8i16,// ->54836
+/* 54826*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54828*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_V_H_PSEUDO), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (MipsVNOR:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (NOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 54836*/ /*SwitchType*/ 10, MVT::v4i32,// ->54848
+/* 54838*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54840*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_V_W_PSEUDO), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsVNOR:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (NOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 54848*/ /*SwitchType*/ 10, MVT::v2i64,// ->54860
+/* 54850*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54852*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::NOR_V_D_PSEUDO), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsVNOR:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (NOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 54860*/ 0, // EndSwitchType
+/* 54861*/ /*SwitchOpcode*/ 90|128,2/*346*/, TARGET_VAL(ISD::INSERT_VECTOR_ELT),// ->55211
+/* 54865*/ OPC_RecordChild0, // #0 = $wd_in
+/* 54866*/ OPC_RecordChild1, // #1 = $rs
+/* 54867*/ OPC_Scope, 29|128,1/*157*/, /*->55027*/ // 4 children in Scope
+/* 54870*/ OPC_CheckChild1Type, MVT::i32,
+/* 54872*/ OPC_RecordChild2, // #2 = $n
+/* 54873*/ OPC_Scope, 63, /*->54938*/ // 3 children in Scope
+/* 54875*/ OPC_MoveChild2,
+/* 54876*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 54879*/ OPC_Scope, 18, /*->54899*/ // 3 children in Scope
+/* 54881*/ OPC_CheckPredicate, 31, // Predicate_immZExt4Ptr
+/* 54883*/ OPC_MoveParent,
+/* 54884*/ OPC_CheckType, MVT::v16i8,
+/* 54886*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54888*/ OPC_EmitConvertToTarget, 2,
+/* 54890*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_B), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 1, 3,
+ // Src: (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[iPTR] })<<P:Predicate_immZExt4Ptr>>:$n) - Complexity = 7
+ // Dst: (INSERT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$n)
+/* 54899*/ /*Scope*/ 18, /*->54918*/
+/* 54900*/ OPC_CheckPredicate, 32, // Predicate_immZExt3Ptr
+/* 54902*/ OPC_MoveParent,
+/* 54903*/ OPC_CheckType, MVT::v8i16,
+/* 54905*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54907*/ OPC_EmitConvertToTarget, 2,
+/* 54909*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_H), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 1, 3,
+ // Src: (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[iPTR] })<<P:Predicate_immZExt3Ptr>>:$n) - Complexity = 7
+ // Dst: (INSERT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$n)
+/* 54918*/ /*Scope*/ 18, /*->54937*/
+/* 54919*/ OPC_CheckPredicate, 33, // Predicate_immZExt2Ptr
+/* 54921*/ OPC_MoveParent,
+/* 54922*/ OPC_CheckType, MVT::v4i32,
+/* 54924*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54926*/ OPC_EmitConvertToTarget, 2,
+/* 54928*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_W), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 1, 3,
+ // Src: (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[iPTR] })<<P:Predicate_immZExt2Ptr>>:$n) - Complexity = 7
+ // Dst: (INSERT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$n)
+/* 54937*/ 0, /*End of Scope*/
+/* 54938*/ /*Scope*/ 43, /*->54982*/
+/* 54939*/ OPC_CheckChild2Type, MVT::i32,
+/* 54941*/ OPC_SwitchType /*3 cases */, 11, MVT::v16i8,// ->54955
+/* 54944*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54946*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_B_VIDX_PSEUDO), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) - Complexity = 3
+ // Dst: (INSERT_B_VIDX_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
+/* 54955*/ /*SwitchType*/ 11, MVT::v8i16,// ->54968
+/* 54957*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54959*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_H_VIDX_PSEUDO), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) - Complexity = 3
+ // Dst: (INSERT_H_VIDX_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
+/* 54968*/ /*SwitchType*/ 11, MVT::v4i32,// ->54981
+/* 54970*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54972*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_W_VIDX_PSEUDO), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) - Complexity = 3
+ // Dst: (INSERT_W_VIDX_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
+/* 54981*/ 0, // EndSwitchType
+/* 54982*/ /*Scope*/ 43, /*->55026*/
+/* 54983*/ OPC_CheckChild2Type, MVT::i64,
+/* 54985*/ OPC_SwitchType /*3 cases */, 11, MVT::v16i8,// ->54999
+/* 54988*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 54990*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_B_VIDX64_PSEUDO), 0,
+ MVT::v16i8, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) - Complexity = 3
+ // Dst: (INSERT_B_VIDX64_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
+/* 54999*/ /*SwitchType*/ 11, MVT::v8i16,// ->55012
+/* 55001*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55003*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_H_VIDX64_PSEUDO), 0,
+ MVT::v8i16, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) - Complexity = 3
+ // Dst: (INSERT_H_VIDX64_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
+/* 55012*/ /*SwitchType*/ 11, MVT::v4i32,// ->55025
+/* 55014*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55016*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_W_VIDX64_PSEUDO), 0,
+ MVT::v4i32, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) - Complexity = 3
+ // Dst: (INSERT_W_VIDX64_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
+/* 55025*/ 0, // EndSwitchType
+/* 55026*/ 0, /*End of Scope*/
+/* 55027*/ /*Scope*/ 60, /*->55088*/
+/* 55028*/ OPC_CheckChild1Type, MVT::i64,
+/* 55030*/ OPC_RecordChild2, // #2 = $n
+/* 55031*/ OPC_Scope, 22, /*->55055*/ // 3 children in Scope
+/* 55033*/ OPC_MoveChild2,
+/* 55034*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 55037*/ OPC_CheckPredicate, 37, // Predicate_immZExt1Ptr
+/* 55039*/ OPC_MoveParent,
+/* 55040*/ OPC_CheckType, MVT::v2i64,
+/* 55042*/ OPC_CheckPatternPredicate, 58, // (Subtarget->hasMSA()) && (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding())
+/* 55044*/ OPC_EmitConvertToTarget, 2,
+/* 55046*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_D), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 1, 3,
+ // Src: (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[iPTR] })<<P:Predicate_immZExt1Ptr>>:$n) - Complexity = 7
+ // Dst: (INSERT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$n)
+/* 55055*/ /*Scope*/ 15, /*->55071*/
+/* 55056*/ OPC_CheckChild2Type, MVT::i32,
+/* 55058*/ OPC_CheckType, MVT::v2i64,
+/* 55060*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55062*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_D_VIDX_PSEUDO), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) - Complexity = 3
+ // Dst: (INSERT_D_VIDX_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
+/* 55071*/ /*Scope*/ 15, /*->55087*/
+/* 55072*/ OPC_CheckChild2Type, MVT::i64,
+/* 55074*/ OPC_CheckType, MVT::v2i64,
+/* 55076*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55078*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_D_VIDX64_PSEUDO), 0,
+ MVT::v2i64, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) - Complexity = 3
+ // Dst: (INSERT_D_VIDX64_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
+/* 55087*/ 0, /*End of Scope*/
+/* 55088*/ /*Scope*/ 60, /*->55149*/
+/* 55089*/ OPC_CheckChild1Type, MVT::f32,
+/* 55091*/ OPC_RecordChild2, // #2 = $n
+/* 55092*/ OPC_Scope, 22, /*->55116*/ // 3 children in Scope
+/* 55094*/ OPC_MoveChild2,
+/* 55095*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 55098*/ OPC_CheckPredicate, 33, // Predicate_immZExt2Ptr
+/* 55100*/ OPC_MoveParent,
+/* 55101*/ OPC_CheckType, MVT::v4f32,
+/* 55103*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55105*/ OPC_EmitConvertToTarget, 2,
+/* 55107*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_FW_PSEUDO), 0,
+ MVT::v4f32, 3/*#Ops*/, 0, 3, 1,
+ // Src: (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, (imm:{ *:[iPTR] })<<P:Predicate_immZExt2Ptr>>:$n) - Complexity = 7
+ // Dst: (INSERT_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, (imm:{ *:[i32] }):$n, FGR32Opnd:{ *:[f32] }:$fs)
+/* 55116*/ /*Scope*/ 15, /*->55132*/
+/* 55117*/ OPC_CheckChild2Type, MVT::i32,
+/* 55119*/ OPC_CheckType, MVT::v4f32,
+/* 55121*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55123*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_FW_VIDX_PSEUDO), 0,
+ MVT::v4f32, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR32Opnd:{ *:[i32] }:$n) - Complexity = 3
+ // Dst: (INSERT_FW_VIDX_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
+/* 55132*/ /*Scope*/ 15, /*->55148*/
+/* 55133*/ OPC_CheckChild2Type, MVT::i64,
+/* 55135*/ OPC_CheckType, MVT::v4f32,
+/* 55137*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55139*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_FW_VIDX64_PSEUDO), 0,
+ MVT::v4f32, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR64Opnd:{ *:[i64] }:$n) - Complexity = 3
+ // Dst: (INSERT_FW_VIDX64_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
+/* 55148*/ 0, /*End of Scope*/
+/* 55149*/ /*Scope*/ 60, /*->55210*/
+/* 55150*/ OPC_CheckChild1Type, MVT::f64,
+/* 55152*/ OPC_RecordChild2, // #2 = $n
+/* 55153*/ OPC_Scope, 22, /*->55177*/ // 3 children in Scope
+/* 55155*/ OPC_MoveChild2,
+/* 55156*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 55159*/ OPC_CheckPredicate, 37, // Predicate_immZExt1Ptr
+/* 55161*/ OPC_MoveParent,
+/* 55162*/ OPC_CheckType, MVT::v2f64,
+/* 55164*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55166*/ OPC_EmitConvertToTarget, 2,
+/* 55168*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_FD_PSEUDO), 0,
+ MVT::v2f64, 3/*#Ops*/, 0, 3, 1,
+ // Src: (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, (imm:{ *:[iPTR] })<<P:Predicate_immZExt1Ptr>>:$n) - Complexity = 7
+ // Dst: (INSERT_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, (imm:{ *:[i32] }):$n, FGR64Opnd:{ *:[f64] }:$fs)
+/* 55177*/ /*Scope*/ 15, /*->55193*/
+/* 55178*/ OPC_CheckChild2Type, MVT::i32,
+/* 55180*/ OPC_CheckType, MVT::v2f64,
+/* 55182*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55184*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_FD_VIDX_PSEUDO), 0,
+ MVT::v2f64, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR32Opnd:{ *:[i32] }:$n) - Complexity = 3
+ // Dst: (INSERT_FD_VIDX_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
+/* 55193*/ /*Scope*/ 15, /*->55209*/
+/* 55194*/ OPC_CheckChild2Type, MVT::i64,
+/* 55196*/ OPC_CheckType, MVT::v2f64,
+/* 55198*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55200*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::INSERT_FD_VIDX64_PSEUDO), 0,
+ MVT::v2f64, 3/*#Ops*/, 0, 2, 1,
+ // Src: (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR64Opnd:{ *:[i64] }:$n) - Complexity = 3
+ // Dst: (INSERT_FD_VIDX64_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
+/* 55209*/ 0, /*End of Scope*/
+/* 55210*/ 0, /*End of Scope*/
+/* 55211*/ /*SwitchOpcode*/ 53, TARGET_VAL(MipsISD::SHF),// ->55267
+/* 55214*/ OPC_RecordChild0, // #0 = $u8
+/* 55215*/ OPC_MoveChild0,
+/* 55216*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 55219*/ OPC_CheckPredicate, 34, // Predicate_immZExt8
+/* 55221*/ OPC_MoveParent,
+/* 55222*/ OPC_RecordChild1, // #1 = $ws
+/* 55223*/ OPC_SwitchType /*3 cases */, 12, MVT::v16i8,// ->55238
+/* 55226*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55228*/ OPC_EmitConvertToTarget, 0,
+/* 55230*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHF_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 1, 2,
+ // Src: (MipsSHF:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$u8, MSA128BOpnd:{ *:[v16i8] }:$ws) - Complexity = 7
+ // Dst: (SHF_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$u8)
+/* 55238*/ /*SwitchType*/ 12, MVT::v8i16,// ->55252
+/* 55240*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55242*/ OPC_EmitConvertToTarget, 0,
+/* 55244*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHF_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 1, 2,
+ // Src: (MipsSHF:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$u8, MSA128HOpnd:{ *:[v8i16] }:$ws) - Complexity = 7
+ // Dst: (SHF_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$u8)
+/* 55252*/ /*SwitchType*/ 12, MVT::v4i32,// ->55266
+/* 55254*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55256*/ OPC_EmitConvertToTarget, 0,
+/* 55258*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHF_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 1, 2,
+ // Src: (MipsSHF:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$u8, MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 7
+ // Dst: (SHF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$u8)
+/* 55266*/ 0, // EndSwitchType
+/* 55267*/ /*SwitchOpcode*/ 37, TARGET_VAL(MipsISD::SHLL_DSP),// ->55307
+/* 55270*/ OPC_RecordChild0, // #0 = $a
+/* 55271*/ OPC_RecordChild1, // #1 = $shamt
+/* 55272*/ OPC_MoveChild1,
+/* 55273*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 55276*/ OPC_MoveParent,
+/* 55277*/ OPC_SwitchType /*2 cases */, 12, MVT::v2i16,// ->55292
+/* 55280*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 55282*/ OPC_EmitConvertToTarget, 1,
+/* 55284*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLL_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 2,
+ // Src: (MipsSHLL_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }):$shamt) - Complexity = 6
+ // Dst: (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }):$shamt)
+/* 55292*/ /*SwitchType*/ 12, MVT::v4i8,// ->55306
+/* 55294*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 55296*/ OPC_EmitConvertToTarget, 1,
+/* 55298*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHLL_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 2,
+ // Src: (MipsSHLL_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] }):$shamt) - Complexity = 6
+ // Dst: (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] }):$shamt)
+/* 55306*/ 0, // EndSwitchType
+/* 55307*/ /*SwitchOpcode*/ 37, TARGET_VAL(MipsISD::SHRA_DSP),// ->55347
+/* 55310*/ OPC_RecordChild0, // #0 = $a
+/* 55311*/ OPC_RecordChild1, // #1 = $shamt
+/* 55312*/ OPC_MoveChild1,
+/* 55313*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 55316*/ OPC_MoveParent,
+/* 55317*/ OPC_SwitchType /*2 cases */, 12, MVT::v2i16,// ->55332
+/* 55320*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 55322*/ OPC_EmitConvertToTarget, 1,
+/* 55324*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 2,
+ // Src: (MipsSHRA_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }):$shamt) - Complexity = 6
+ // Dst: (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }):$shamt)
+/* 55332*/ /*SwitchType*/ 12, MVT::v4i8,// ->55346
+/* 55334*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 55336*/ OPC_EmitConvertToTarget, 1,
+/* 55338*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRA_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 2,
+ // Src: (MipsSHRA_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] }):$shamt) - Complexity = 6
+ // Dst: (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] }):$shamt)
+/* 55346*/ 0, // EndSwitchType
+/* 55347*/ /*SwitchOpcode*/ 37, TARGET_VAL(MipsISD::SHRL_DSP),// ->55387
+/* 55350*/ OPC_RecordChild0, // #0 = $a
+/* 55351*/ OPC_RecordChild1, // #1 = $shamt
+/* 55352*/ OPC_MoveChild1,
+/* 55353*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 55356*/ OPC_MoveParent,
+/* 55357*/ OPC_SwitchType /*2 cases */, 12, MVT::v2i16,// ->55372
+/* 55360*/ OPC_CheckPatternPredicate, 46, // (Subtarget->hasDSPR2())
+/* 55362*/ OPC_EmitConvertToTarget, 1,
+/* 55364*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRL_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 2,
+ // Src: (MipsSHRL_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }):$shamt) - Complexity = 6
+ // Dst: (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] }):$shamt)
+/* 55372*/ /*SwitchType*/ 12, MVT::v4i8,// ->55386
+/* 55374*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 55376*/ OPC_EmitConvertToTarget, 1,
+/* 55378*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::SHRL_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 2,
+ // Src: (MipsSHRL_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] }):$shamt) - Complexity = 6
+ // Dst: (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] }):$shamt)
+/* 55386*/ 0, // EndSwitchType
+/* 55387*/ /*SwitchOpcode*/ 33|128,1/*161*/, TARGET_VAL(ISD::BUILD_VECTOR),// ->55552
+/* 55391*/ OPC_RecordChild0, // #0 = $rs
+/* 55392*/ OPC_Scope, 105, /*->55499*/ // 4 children in Scope
+/* 55394*/ OPC_CheckChild0Type, MVT::i32,
+/* 55396*/ OPC_CheckChild1Same, 0,
+/* 55398*/ OPC_CheckChild2Same, 0,
+/* 55400*/ OPC_CheckChild3Same, 0,
+/* 55402*/ OPC_Scope, 82, /*->55486*/ // 2 children in Scope
+/* 55404*/ OPC_MoveChild4,
+/* 55405*/ OPC_CheckSame, 0,
+/* 55407*/ OPC_MoveParent,
+/* 55408*/ OPC_MoveChild5,
+/* 55409*/ OPC_CheckSame, 0,
+/* 55411*/ OPC_MoveParent,
+/* 55412*/ OPC_MoveChild6,
+/* 55413*/ OPC_CheckSame, 0,
+/* 55415*/ OPC_MoveParent,
+/* 55416*/ OPC_MoveChild7,
+/* 55417*/ OPC_CheckSame, 0,
+/* 55419*/ OPC_MoveParent,
+/* 55420*/ OPC_Scope, 51, /*->55473*/ // 2 children in Scope
+/* 55422*/ OPC_MoveChild, 8,
+/* 55424*/ OPC_CheckSame, 0,
+/* 55426*/ OPC_MoveParent,
+/* 55427*/ OPC_MoveChild, 9,
+/* 55429*/ OPC_CheckSame, 0,
+/* 55431*/ OPC_MoveParent,
+/* 55432*/ OPC_MoveChild, 10,
+/* 55434*/ OPC_CheckSame, 0,
+/* 55436*/ OPC_MoveParent,
+/* 55437*/ OPC_MoveChild, 11,
+/* 55439*/ OPC_CheckSame, 0,
+/* 55441*/ OPC_MoveParent,
+/* 55442*/ OPC_MoveChild, 12,
+/* 55444*/ OPC_CheckSame, 0,
+/* 55446*/ OPC_MoveParent,
+/* 55447*/ OPC_MoveChild, 13,
+/* 55449*/ OPC_CheckSame, 0,
+/* 55451*/ OPC_MoveParent,
+/* 55452*/ OPC_MoveChild, 14,
+/* 55454*/ OPC_CheckSame, 0,
+/* 55456*/ OPC_MoveParent,
+/* 55457*/ OPC_MoveChild, 15,
+/* 55459*/ OPC_CheckSame, 0,
+/* 55461*/ OPC_MoveParent,
+/* 55462*/ OPC_CheckType, MVT::v16i8,
+/* 55464*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55466*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FILL_B), 0,
+ MVT::v16i8, 1/*#Ops*/, 0,
+ // Src: (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 55473*/ /*Scope*/ 11, /*->55485*/
+/* 55474*/ OPC_CheckType, MVT::v8i16,
+/* 55476*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55478*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FILL_H), 0,
+ MVT::v8i16, 1/*#Ops*/, 0,
+ // Src: (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 55485*/ 0, /*End of Scope*/
+/* 55486*/ /*Scope*/ 11, /*->55498*/
+/* 55487*/ OPC_CheckType, MVT::v4i32,
+/* 55489*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55491*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FILL_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs) - Complexity = 3
+ // Dst: (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
+/* 55498*/ 0, /*End of Scope*/
+/* 55499*/ /*Scope*/ 15, /*->55515*/
+/* 55500*/ OPC_CheckChild0Type, MVT::i64,
+/* 55502*/ OPC_CheckChild1Same, 0,
+/* 55504*/ OPC_CheckType, MVT::v2i64,
+/* 55506*/ OPC_CheckPatternPredicate, 58, // (Subtarget->hasMSA()) && (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding())
+/* 55508*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FILL_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs) - Complexity = 3
+ // Dst: (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
+/* 55515*/ /*Scope*/ 19, /*->55535*/
+/* 55516*/ OPC_CheckChild0Type, MVT::f32,
+/* 55518*/ OPC_CheckChild1Same, 0,
+/* 55520*/ OPC_CheckChild2Same, 0,
+/* 55522*/ OPC_CheckChild3Same, 0,
+/* 55524*/ OPC_CheckType, MVT::v4f32,
+/* 55526*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55528*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FILL_FW_PSEUDO), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs) - Complexity = 3
+ // Dst: (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
+/* 55535*/ /*Scope*/ 15, /*->55551*/
+/* 55536*/ OPC_CheckChild0Type, MVT::f64,
+/* 55538*/ OPC_CheckChild1Same, 0,
+/* 55540*/ OPC_CheckType, MVT::v2f64,
+/* 55542*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55544*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FILL_FD_PSEUDO), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs) - Complexity = 3
+ // Dst: (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
+/* 55551*/ 0, /*End of Scope*/
+/* 55552*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FP_TO_SINT),// ->55580
+/* 55555*/ OPC_RecordChild0, // #0 = $ws
+/* 55556*/ OPC_SwitchType /*2 cases */, 9, MVT::v4i32,// ->55568
+/* 55559*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55561*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTRUNC_S_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 3
+ // Dst: (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 55568*/ /*SwitchType*/ 9, MVT::v2i64,// ->55579
+/* 55570*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55572*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTRUNC_S_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 3
+ // Dst: (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 55579*/ 0, // EndSwitchType
+/* 55580*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FP_TO_UINT),// ->55608
+/* 55583*/ OPC_RecordChild0, // #0 = $ws
+/* 55584*/ OPC_SwitchType /*2 cases */, 9, MVT::v4i32,// ->55596
+/* 55587*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55589*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTRUNC_U_W), 0,
+ MVT::v4i32, 1/*#Ops*/, 0,
+ // Src: (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 3
+ // Dst: (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 55596*/ /*SwitchType*/ 9, MVT::v2i64,// ->55607
+/* 55598*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55600*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FTRUNC_U_D), 0,
+ MVT::v2i64, 1/*#Ops*/, 0,
+ // Src: (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 3
+ // Dst: (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 55607*/ 0, // EndSwitchType
+/* 55608*/ /*SwitchOpcode*/ 52, TARGET_VAL(MipsISD::ILVEV),// ->55663
+/* 55611*/ OPC_RecordChild0, // #0 = $ws
+/* 55612*/ OPC_RecordChild1, // #1 = $wt
+/* 55613*/ OPC_SwitchType /*4 cases */, 10, MVT::v16i8,// ->55626
+/* 55616*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55618*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVEV_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVEV:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (ILVEV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 55626*/ /*SwitchType*/ 10, MVT::v8i16,// ->55638
+/* 55628*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55630*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVEV_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVEV:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (ILVEV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 55638*/ /*SwitchType*/ 10, MVT::v4i32,// ->55650
+/* 55640*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55642*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVEV_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVEV:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (ILVEV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 55650*/ /*SwitchType*/ 10, MVT::v2i64,// ->55662
+/* 55652*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55654*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVEV_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVEV:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (ILVEV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 55662*/ 0, // EndSwitchType
+/* 55663*/ /*SwitchOpcode*/ 52, TARGET_VAL(MipsISD::ILVL),// ->55718
+/* 55666*/ OPC_RecordChild0, // #0 = $ws
+/* 55667*/ OPC_RecordChild1, // #1 = $wt
+/* 55668*/ OPC_SwitchType /*4 cases */, 10, MVT::v16i8,// ->55681
+/* 55671*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55673*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVL_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVL:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (ILVL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 55681*/ /*SwitchType*/ 10, MVT::v8i16,// ->55693
+/* 55683*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55685*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVL_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVL:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (ILVL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 55693*/ /*SwitchType*/ 10, MVT::v4i32,// ->55705
+/* 55695*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55697*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVL_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVL:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (ILVL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 55705*/ /*SwitchType*/ 10, MVT::v2i64,// ->55717
+/* 55707*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55709*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVL_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVL:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (ILVL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 55717*/ 0, // EndSwitchType
+/* 55718*/ /*SwitchOpcode*/ 52, TARGET_VAL(MipsISD::ILVOD),// ->55773
+/* 55721*/ OPC_RecordChild0, // #0 = $ws
+/* 55722*/ OPC_RecordChild1, // #1 = $wt
+/* 55723*/ OPC_SwitchType /*4 cases */, 10, MVT::v16i8,// ->55736
+/* 55726*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55728*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVOD_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVOD:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (ILVOD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 55736*/ /*SwitchType*/ 10, MVT::v8i16,// ->55748
+/* 55738*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55740*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVOD_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVOD:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (ILVOD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 55748*/ /*SwitchType*/ 10, MVT::v4i32,// ->55760
+/* 55750*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55752*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVOD_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVOD:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (ILVOD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 55760*/ /*SwitchType*/ 10, MVT::v2i64,// ->55772
+/* 55762*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55764*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVOD_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVOD:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (ILVOD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 55772*/ 0, // EndSwitchType
+/* 55773*/ /*SwitchOpcode*/ 52, TARGET_VAL(MipsISD::ILVR),// ->55828
+/* 55776*/ OPC_RecordChild0, // #0 = $ws
+/* 55777*/ OPC_RecordChild1, // #1 = $wt
+/* 55778*/ OPC_SwitchType /*4 cases */, 10, MVT::v16i8,// ->55791
+/* 55781*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55783*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVR_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVR:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (ILVR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 55791*/ /*SwitchType*/ 10, MVT::v8i16,// ->55803
+/* 55793*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55795*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVR_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVR:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (ILVR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 55803*/ /*SwitchType*/ 10, MVT::v4i32,// ->55815
+/* 55805*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55807*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVR_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVR:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (ILVR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 55815*/ /*SwitchType*/ 10, MVT::v2i64,// ->55827
+/* 55817*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55819*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ILVR_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsILVR:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (ILVR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 55827*/ 0, // EndSwitchType
+/* 55828*/ /*SwitchOpcode*/ 52, TARGET_VAL(MipsISD::PCKEV),// ->55883
+/* 55831*/ OPC_RecordChild0, // #0 = $ws
+/* 55832*/ OPC_RecordChild1, // #1 = $wt
+/* 55833*/ OPC_SwitchType /*4 cases */, 10, MVT::v16i8,// ->55846
+/* 55836*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55838*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCKEV_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (MipsPCKEV:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (PCKEV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 55846*/ /*SwitchType*/ 10, MVT::v8i16,// ->55858
+/* 55848*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55850*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCKEV_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (MipsPCKEV:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (PCKEV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 55858*/ /*SwitchType*/ 10, MVT::v4i32,// ->55870
+/* 55860*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55862*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCKEV_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsPCKEV:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (PCKEV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 55870*/ /*SwitchType*/ 10, MVT::v2i64,// ->55882
+/* 55872*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55874*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCKEV_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsPCKEV:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (PCKEV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 55882*/ 0, // EndSwitchType
+/* 55883*/ /*SwitchOpcode*/ 52, TARGET_VAL(MipsISD::PCKOD),// ->55938
+/* 55886*/ OPC_RecordChild0, // #0 = $ws
+/* 55887*/ OPC_RecordChild1, // #1 = $wt
+/* 55888*/ OPC_SwitchType /*4 cases */, 10, MVT::v16i8,// ->55901
+/* 55891*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55893*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCKOD_B), 0,
+ MVT::v16i8, 2/*#Ops*/, 0, 1,
+ // Src: (MipsPCKOD:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) - Complexity = 3
+ // Dst: (PCKOD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+/* 55901*/ /*SwitchType*/ 10, MVT::v8i16,// ->55913
+/* 55903*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55905*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCKOD_H), 0,
+ MVT::v8i16, 2/*#Ops*/, 0, 1,
+ // Src: (MipsPCKOD:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) - Complexity = 3
+ // Dst: (PCKOD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+/* 55913*/ /*SwitchType*/ 10, MVT::v4i32,// ->55925
+/* 55915*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55917*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCKOD_W), 0,
+ MVT::v4i32, 2/*#Ops*/, 0, 1,
+ // Src: (MipsPCKOD:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) - Complexity = 3
+ // Dst: (PCKOD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+/* 55925*/ /*SwitchType*/ 10, MVT::v2i64,// ->55937
+/* 55927*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 55929*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PCKOD_D), 0,
+ MVT::v2i64, 2/*#Ops*/, 0, 1,
+ // Src: (MipsPCKOD:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) - Complexity = 3
+ // Dst: (PCKOD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+/* 55937*/ 0, // EndSwitchType
+/* 55938*/ /*SwitchOpcode*/ 67|128,2/*323*/, TARGET_VAL(MipsISD::SELECT_CC_DSP),// ->56265
+/* 55942*/ OPC_RecordChild0, // #0 = $a
+/* 55943*/ OPC_Scope, 30|128,1/*158*/, /*->56104*/ // 2 children in Scope
+/* 55946*/ OPC_CheckChild0Type, MVT::v2i16,
+/* 55948*/ OPC_RecordChild1, // #1 = $b
+/* 55949*/ OPC_RecordChild2, // #2 = $c
+/* 55950*/ OPC_RecordChild3, // #3 = $d
+/* 55951*/ OPC_MoveChild4,
+/* 55952*/ OPC_Scope, 24, /*->55978*/ // 6 children in Scope
+/* 55954*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 55956*/ OPC_MoveParent,
+/* 55957*/ OPC_CheckType, MVT::v2i16,
+/* 55959*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 55961*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_EQ_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #4
+/* 55969*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 4, 2, 3,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, v2i16:{ *:[v2i16] }:$c, v2i16:{ *:[v2i16] }:$d, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_EQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ?:{ *:[v2i16] }:$c, ?:{ *:[v2i16] }:$d)
+/* 55978*/ /*Scope*/ 24, /*->56003*/
+/* 55979*/ OPC_CheckCondCode, ISD::SETLT,
+/* 55981*/ OPC_MoveParent,
+/* 55982*/ OPC_CheckType, MVT::v2i16,
+/* 55984*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 55986*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_LT_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #4
+/* 55994*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 4, 2, 3,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, v2i16:{ *:[v2i16] }:$c, v2i16:{ *:[v2i16] }:$d, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_LT_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ?:{ *:[v2i16] }:$c, ?:{ *:[v2i16] }:$d)
+/* 56003*/ /*Scope*/ 24, /*->56028*/
+/* 56004*/ OPC_CheckCondCode, ISD::SETLE,
+/* 56006*/ OPC_MoveParent,
+/* 56007*/ OPC_CheckType, MVT::v2i16,
+/* 56009*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56011*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_LE_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56019*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 4, 2, 3,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, v2i16:{ *:[v2i16] }:$c, v2i16:{ *:[v2i16] }:$d, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_LE_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ?:{ *:[v2i16] }:$c, ?:{ *:[v2i16] }:$d)
+/* 56028*/ /*Scope*/ 24, /*->56053*/
+/* 56029*/ OPC_CheckCondCode, ISD::SETNE,
+/* 56031*/ OPC_MoveParent,
+/* 56032*/ OPC_CheckType, MVT::v2i16,
+/* 56034*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56036*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_EQ_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56044*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 4, 3, 2,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, v2i16:{ *:[v2i16] }:$c, v2i16:{ *:[v2i16] }:$d, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_EQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ?:{ *:[v2i16] }:$d, ?:{ *:[v2i16] }:$c)
+/* 56053*/ /*Scope*/ 24, /*->56078*/
+/* 56054*/ OPC_CheckCondCode, ISD::SETGE,
+/* 56056*/ OPC_MoveParent,
+/* 56057*/ OPC_CheckType, MVT::v2i16,
+/* 56059*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56061*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_LT_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56069*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 4, 3, 2,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, v2i16:{ *:[v2i16] }:$c, v2i16:{ *:[v2i16] }:$d, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_LT_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ?:{ *:[v2i16] }:$d, ?:{ *:[v2i16] }:$c)
+/* 56078*/ /*Scope*/ 24, /*->56103*/
+/* 56079*/ OPC_CheckCondCode, ISD::SETGT,
+/* 56081*/ OPC_MoveParent,
+/* 56082*/ OPC_CheckType, MVT::v2i16,
+/* 56084*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56086*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_LE_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56094*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 4, 3, 2,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, v2i16:{ *:[v2i16] }:$c, v2i16:{ *:[v2i16] }:$d, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_LE_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ?:{ *:[v2i16] }:$d, ?:{ *:[v2i16] }:$c)
+/* 56103*/ 0, /*End of Scope*/
+/* 56104*/ /*Scope*/ 30|128,1/*158*/, /*->56264*/
+/* 56106*/ OPC_CheckChild0Type, MVT::v4i8,
+/* 56108*/ OPC_RecordChild1, // #1 = $b
+/* 56109*/ OPC_RecordChild2, // #2 = $c
+/* 56110*/ OPC_RecordChild3, // #3 = $d
+/* 56111*/ OPC_MoveChild4,
+/* 56112*/ OPC_Scope, 24, /*->56138*/ // 6 children in Scope
+/* 56114*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 56116*/ OPC_MoveParent,
+/* 56117*/ OPC_CheckType, MVT::v4i8,
+/* 56119*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56121*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_EQ_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56129*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 4, 2, 3,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, v4i8:{ *:[v4i8] }:$c, v4i8:{ *:[v4i8] }:$d, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_EQ_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ?:{ *:[v4i8] }:$c, ?:{ *:[v4i8] }:$d)
+/* 56138*/ /*Scope*/ 24, /*->56163*/
+/* 56139*/ OPC_CheckCondCode, ISD::SETULT,
+/* 56141*/ OPC_MoveParent,
+/* 56142*/ OPC_CheckType, MVT::v4i8,
+/* 56144*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56146*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_LT_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56154*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 4, 2, 3,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, v4i8:{ *:[v4i8] }:$c, v4i8:{ *:[v4i8] }:$d, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_LT_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ?:{ *:[v4i8] }:$c, ?:{ *:[v4i8] }:$d)
+/* 56163*/ /*Scope*/ 24, /*->56188*/
+/* 56164*/ OPC_CheckCondCode, ISD::SETULE,
+/* 56166*/ OPC_MoveParent,
+/* 56167*/ OPC_CheckType, MVT::v4i8,
+/* 56169*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56171*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_LE_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56179*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 4, 2, 3,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, v4i8:{ *:[v4i8] }:$c, v4i8:{ *:[v4i8] }:$d, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_LE_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ?:{ *:[v4i8] }:$c, ?:{ *:[v4i8] }:$d)
+/* 56188*/ /*Scope*/ 24, /*->56213*/
+/* 56189*/ OPC_CheckCondCode, ISD::SETNE,
+/* 56191*/ OPC_MoveParent,
+/* 56192*/ OPC_CheckType, MVT::v4i8,
+/* 56194*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56196*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_EQ_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56204*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 4, 3, 2,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, v4i8:{ *:[v4i8] }:$c, v4i8:{ *:[v4i8] }:$d, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_EQ_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ?:{ *:[v4i8] }:$d, ?:{ *:[v4i8] }:$c)
+/* 56213*/ /*Scope*/ 24, /*->56238*/
+/* 56214*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 56216*/ OPC_MoveParent,
+/* 56217*/ OPC_CheckType, MVT::v4i8,
+/* 56219*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56221*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_LT_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56229*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 4, 3, 2,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, v4i8:{ *:[v4i8] }:$c, v4i8:{ *:[v4i8] }:$d, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_LT_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ?:{ *:[v4i8] }:$d, ?:{ *:[v4i8] }:$c)
+/* 56238*/ /*Scope*/ 24, /*->56263*/
+/* 56239*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 56241*/ OPC_MoveParent,
+/* 56242*/ OPC_CheckType, MVT::v4i8,
+/* 56244*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56246*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_LE_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #4
+/* 56254*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 4, 3, 2,
+ // Src: (MipsSELECT_CC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, v4i8:{ *:[v4i8] }:$c, v4i8:{ *:[v4i8] }:$d, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_LE_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ?:{ *:[v4i8] }:$d, ?:{ *:[v4i8] }:$c)
+/* 56263*/ 0, /*End of Scope*/
+/* 56264*/ 0, /*End of Scope*/
+/* 56265*/ /*SwitchOpcode*/ 123|128,5/*763*/, TARGET_VAL(MipsISD::SETCC_DSP),// ->57032
+/* 56269*/ OPC_RecordChild0, // #0 = $a
+/* 56270*/ OPC_Scope, 122|128,2/*378*/, /*->56651*/ // 2 children in Scope
+/* 56273*/ OPC_CheckChild0Type, MVT::v2i16,
+/* 56275*/ OPC_RecordChild1, // #1 = $b
+/* 56276*/ OPC_MoveChild2,
+/* 56277*/ OPC_Scope, 61, /*->56340*/ // 6 children in Scope
+/* 56279*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 56281*/ OPC_MoveParent,
+/* 56282*/ OPC_CheckType, MVT::v2i16,
+/* 56284*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56286*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_EQ_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56294*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56297*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56309*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 56317*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56320*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i16, 2/*#Ops*/, 5, 6, // Results = #7
+/* 56328*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
+/* 56331*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 2, 7, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_EQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), (COPY_TO_REGCLASS:{ *:[v2i16] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }), ZERO:{ *:[v2i16] })
+/* 56340*/ /*Scope*/ 61, /*->56402*/
+/* 56341*/ OPC_CheckCondCode, ISD::SETLT,
+/* 56343*/ OPC_MoveParent,
+/* 56344*/ OPC_CheckType, MVT::v2i16,
+/* 56346*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56348*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_LT_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56356*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56359*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56371*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 56379*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56382*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i16, 2/*#Ops*/, 5, 6, // Results = #7
+/* 56390*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
+/* 56393*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 2, 7, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_LT_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), (COPY_TO_REGCLASS:{ *:[v2i16] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }), ZERO:{ *:[v2i16] })
+/* 56402*/ /*Scope*/ 61, /*->56464*/
+/* 56403*/ OPC_CheckCondCode, ISD::SETLE,
+/* 56405*/ OPC_MoveParent,
+/* 56406*/ OPC_CheckType, MVT::v2i16,
+/* 56408*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56410*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_LE_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56418*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56421*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56433*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 56441*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56444*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i16, 2/*#Ops*/, 5, 6, // Results = #7
+/* 56452*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
+/* 56455*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 2, 7, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_LE_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), (COPY_TO_REGCLASS:{ *:[v2i16] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }), ZERO:{ *:[v2i16] })
+/* 56464*/ /*Scope*/ 61, /*->56526*/
+/* 56465*/ OPC_CheckCondCode, ISD::SETNE,
+/* 56467*/ OPC_MoveParent,
+/* 56468*/ OPC_CheckType, MVT::v2i16,
+/* 56470*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56472*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_EQ_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56480*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
+/* 56483*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56486*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56498*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 56506*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56509*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i16, 2/*#Ops*/, 6, 7, // Results = #8
+/* 56517*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 2, 3, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_EQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ZERO:{ *:[v2i16] }, (COPY_TO_REGCLASS:{ *:[v2i16] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }))
+/* 56526*/ /*Scope*/ 61, /*->56588*/
+/* 56527*/ OPC_CheckCondCode, ISD::SETGE,
+/* 56529*/ OPC_MoveParent,
+/* 56530*/ OPC_CheckType, MVT::v2i16,
+/* 56532*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56534*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_LT_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56542*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
+/* 56545*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56548*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56560*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 56568*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56571*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i16, 2/*#Ops*/, 6, 7, // Results = #8
+/* 56579*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 2, 3, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_LT_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ZERO:{ *:[v2i16] }, (COPY_TO_REGCLASS:{ *:[v2i16] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }))
+/* 56588*/ /*Scope*/ 61, /*->56650*/
+/* 56589*/ OPC_CheckCondCode, ISD::SETGT,
+/* 56591*/ OPC_MoveParent,
+/* 56592*/ OPC_CheckType, MVT::v2i16,
+/* 56594*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56596*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMP_LE_PH), 0,
+ MVT::v2i16, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56604*/ OPC_EmitRegister, MVT::v2i16, Mips::ZERO,
+/* 56607*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56610*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56622*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 56630*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56633*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v2i16, 2/*#Ops*/, 6, 7, // Results = #8
+/* 56641*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_PH), 0,
+ MVT::v2i16, 3/*#Ops*/, 2, 3, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_PH:{ *:[v2i16] } (PseudoCMP_LE_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b), ZERO:{ *:[v2i16] }, (COPY_TO_REGCLASS:{ *:[v2i16] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }))
+/* 56650*/ 0, /*End of Scope*/
+/* 56651*/ /*Scope*/ 122|128,2/*378*/, /*->57031*/
+/* 56653*/ OPC_CheckChild0Type, MVT::v4i8,
+/* 56655*/ OPC_RecordChild1, // #1 = $b
+/* 56656*/ OPC_MoveChild2,
+/* 56657*/ OPC_Scope, 61, /*->56720*/ // 6 children in Scope
+/* 56659*/ OPC_CheckCondCode, ISD::SETEQ,
+/* 56661*/ OPC_MoveParent,
+/* 56662*/ OPC_CheckType, MVT::v4i8,
+/* 56664*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56666*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_EQ_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56674*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56677*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56689*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 56697*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56700*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i8, 2/*#Ops*/, 5, 6, // Results = #7
+/* 56708*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
+/* 56711*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 2, 7, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_EQ_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), (COPY_TO_REGCLASS:{ *:[v4i8] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }), ZERO:{ *:[v4i8] })
+/* 56720*/ /*Scope*/ 61, /*->56782*/
+/* 56721*/ OPC_CheckCondCode, ISD::SETULT,
+/* 56723*/ OPC_MoveParent,
+/* 56724*/ OPC_CheckType, MVT::v4i8,
+/* 56726*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56728*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_LT_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56736*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56739*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56751*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 56759*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56762*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i8, 2/*#Ops*/, 5, 6, // Results = #7
+/* 56770*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
+/* 56773*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 2, 7, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_LT_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), (COPY_TO_REGCLASS:{ *:[v4i8] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }), ZERO:{ *:[v4i8] })
+/* 56782*/ /*Scope*/ 61, /*->56844*/
+/* 56783*/ OPC_CheckCondCode, ISD::SETULE,
+/* 56785*/ OPC_MoveParent,
+/* 56786*/ OPC_CheckType, MVT::v4i8,
+/* 56788*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56790*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_LE_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56798*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56801*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56813*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4, // Results = #5
+/* 56821*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56824*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i8, 2/*#Ops*/, 5, 6, // Results = #7
+/* 56832*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
+/* 56835*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 2, 7, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_LE_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), (COPY_TO_REGCLASS:{ *:[v4i8] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }), ZERO:{ *:[v4i8] })
+/* 56844*/ /*Scope*/ 61, /*->56906*/
+/* 56845*/ OPC_CheckCondCode, ISD::SETNE,
+/* 56847*/ OPC_MoveParent,
+/* 56848*/ OPC_CheckType, MVT::v4i8,
+/* 56850*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56852*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_EQ_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56860*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
+/* 56863*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56866*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56878*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 56886*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56889*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i8, 2/*#Ops*/, 6, 7, // Results = #8
+/* 56897*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 2, 3, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_EQ_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ZERO:{ *:[v4i8] }, (COPY_TO_REGCLASS:{ *:[v4i8] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }))
+/* 56906*/ /*Scope*/ 61, /*->56968*/
+/* 56907*/ OPC_CheckCondCode, ISD::SETUGE,
+/* 56909*/ OPC_MoveParent,
+/* 56910*/ OPC_CheckType, MVT::v4i8,
+/* 56912*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56914*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_LT_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56922*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
+/* 56925*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56928*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 56940*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 56948*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 56951*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i8, 2/*#Ops*/, 6, 7, // Results = #8
+/* 56959*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 2, 3, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_LT_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ZERO:{ *:[v4i8] }, (COPY_TO_REGCLASS:{ *:[v4i8] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }))
+/* 56968*/ /*Scope*/ 61, /*->57030*/
+/* 56969*/ OPC_CheckCondCode, ISD::SETUGT,
+/* 56971*/ OPC_MoveParent,
+/* 56972*/ OPC_CheckType, MVT::v4i8,
+/* 56974*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasDSP())
+/* 56976*/ OPC_EmitNode1, TARGET_VAL(Mips::PseudoCMPU_LE_QB), 0,
+ MVT::v4i8, 2/*#Ops*/, 0, 1, // Results = #2
+/* 56984*/ OPC_EmitRegister, MVT::v4i8, Mips::ZERO,
+/* 56987*/ OPC_EmitRegister, MVT::i32, Mips::ZERO,
+/* 56990*/ OPC_EmitInteger, MVT::i32, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1/*18446744073709551615*/,
+/* 57002*/ OPC_EmitNode1, TARGET_VAL(Mips::ADDiu), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5, // Results = #6
+/* 57010*/ OPC_EmitInteger, MVT::i32, Mips::DSPRRegClassID,
+/* 57013*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+ MVT::v4i8, 2/*#Ops*/, 6, 7, // Results = #8
+/* 57021*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::PseudoPICK_QB), 0,
+ MVT::v4i8, 3/*#Ops*/, 2, 3, 8,
+ // Src: (MipsSETCC_DSP:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (PseudoPICK_QB:{ *:[v4i8] } (PseudoCMPU_LE_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b), ZERO:{ *:[v4i8] }, (COPY_TO_REGCLASS:{ *:[v4i8] } (ADDiu:{ *:[i32] } ZERO:{ *:[i32] }, -1:{ *:[i32] }), DSPR:{ *:[i32] }))
+/* 57030*/ 0, /*End of Scope*/
+/* 57031*/ 0, /*End of Scope*/
+/* 57032*/ /*SwitchOpcode*/ 29, TARGET_VAL(ISD::UINT_TO_FP),// ->57064
+/* 57035*/ OPC_RecordChild0, // #0 = $ws
+/* 57036*/ OPC_SwitchType /*2 cases */, 11, MVT::v4f32,// ->57050
+/* 57039*/ OPC_CheckChild0Type, MVT::v4i32,
+/* 57041*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57043*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FFINT_U_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) - Complexity = 3
+ // Dst: (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+/* 57050*/ /*SwitchType*/ 11, MVT::v2f64,// ->57063
+/* 57052*/ OPC_CheckChild0Type, MVT::v2i64,
+/* 57054*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57056*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FFINT_U_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) - Complexity = 3
+ // Dst: (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
+/* 57063*/ 0, // EndSwitchType
+/* 57064*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FLOG2),// ->57092
+/* 57067*/ OPC_RecordChild0, // #0 = $ws
+/* 57068*/ OPC_SwitchType /*2 cases */, 9, MVT::v4f32,// ->57080
+/* 57071*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57073*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FLOG2_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 3
+ // Dst: (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 57080*/ /*SwitchType*/ 9, MVT::v2f64,// ->57091
+/* 57082*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57084*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FLOG2_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 3
+ // Dst: (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 57091*/ 0, // EndSwitchType
+/* 57092*/ /*SwitchOpcode*/ 31, TARGET_VAL(ISD::FMA),// ->57126
+/* 57095*/ OPC_RecordChild0, // #0 = $wd_in
+/* 57096*/ OPC_RecordChild1, // #1 = $ws
+/* 57097*/ OPC_RecordChild2, // #2 = $wt
+/* 57098*/ OPC_SwitchType /*2 cases */, 11, MVT::v4f32,// ->57112
+/* 57101*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57103*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMADD_W), 0,
+ MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 3
+ // Dst: (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 57112*/ /*SwitchType*/ 11, MVT::v2f64,// ->57125
+/* 57114*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57116*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMADD_D), 0,
+ MVT::v2f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 3
+ // Dst: (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 57125*/ 0, // EndSwitchType
+/* 57126*/ /*SwitchOpcode*/ 31, TARGET_VAL(MipsISD::FMS),// ->57160
+/* 57129*/ OPC_RecordChild0, // #0 = $wd_in
+/* 57130*/ OPC_RecordChild1, // #1 = $ws
+/* 57131*/ OPC_RecordChild2, // #2 = $wt
+/* 57132*/ OPC_SwitchType /*2 cases */, 11, MVT::v4f32,// ->57146
+/* 57135*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57137*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMSUB_W), 0,
+ MVT::v4f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsFMS:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) - Complexity = 3
+ // Dst: (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+/* 57146*/ /*SwitchType*/ 11, MVT::v2f64,// ->57159
+/* 57148*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57150*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FMSUB_D), 0,
+ MVT::v2f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (MipsFMS:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) - Complexity = 3
+ // Dst: (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+/* 57159*/ 0, // EndSwitchType
+/* 57160*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FRINT),// ->57188
+/* 57163*/ OPC_RecordChild0, // #0 = $ws
+/* 57164*/ OPC_SwitchType /*2 cases */, 9, MVT::v4f32,// ->57176
+/* 57167*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57169*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FRINT_W), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) - Complexity = 3
+ // Dst: (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+/* 57176*/ /*SwitchType*/ 9, MVT::v2f64,// ->57187
+/* 57178*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57180*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FRINT_D), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) - Complexity = 3
+ // Dst: (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+/* 57187*/ 0, // EndSwitchType
+/* 57188*/ /*SwitchOpcode*/ 25, TARGET_VAL(ISD::FEXP2),// ->57216
+/* 57191*/ OPC_RecordChild0, // #0 = $ws
+/* 57192*/ OPC_SwitchType /*2 cases */, 9, MVT::v4f32,// ->57204
+/* 57195*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57197*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXP2_W_1_PSEUDO), 0,
+ MVT::v4f32, 1/*#Ops*/, 0,
+ // Src: (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) - Complexity = 3
+ // Dst: (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
+/* 57204*/ /*SwitchType*/ 9, MVT::v2f64,// ->57215
+/* 57206*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())
+/* 57208*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::FEXP2_D_1_PSEUDO), 0,
+ MVT::v2f64, 1/*#Ops*/, 0,
+ // Src: (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) - Complexity = 3
+ // Dst: (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
+/* 57215*/ 0, // EndSwitchType
+/* 57216*/ 0, // EndSwitchOpcode
+ 0
+ }; // Total Array size is 57218 bytes
+
+ // Opcode Histogram:
+ // #OPC_Scope = 697
+ // #OPC_RecordNode = 57
+ // #OPC_RecordChild = 1892
+ // #OPC_RecordMemRef = 20
+ // #OPC_CaptureGlueInput = 10
+ // #OPC_MoveChild = 1404
+ // #OPC_MoveParent = 2435
+ // #OPC_CheckSame = 24
+ // #OPC_CheckChildSame = 26
+ // #OPC_CheckPatternPredicate = 2285
+ // #OPC_CheckPredicate = 1151
+ // #OPC_CheckOpcode = 1213
+ // #OPC_SwitchOpcode = 39
+ // #OPC_CheckType = 1842
+ // #OPC_SwitchType = 181
+ // #OPC_CheckChildType = 235
+ // #OPC_CheckInteger = 0
+ // #OPC_CheckChildInteger = 336
+ // #OPC_CheckCondCode = 505
+ // #OPC_CheckValueType = 29
+ // #OPC_CheckComplexPat = 276
+ // #OPC_CheckAndImm = 1
+ // #OPC_CheckOrImm = 0
+ // #OPC_CheckFoldableChainNode = 0
+ // #OPC_EmitInteger = 111
+ // #OPC_EmitStringInteger = 224
+ // #OPC_EmitRegister = 124
+ // #OPC_EmitConvertToTarget = 343
+ // #OPC_EmitMergeInputChains = 493
+ // #OPC_EmitCopyToReg = 0
+ // #OPC_EmitNode = 583
+ // #OPC_EmitNodeXForm = 99
+ // #OPC_CompleteMatch = 0
+ // #OPC_MorphNodeTo = 2412
+
+ #undef TARGET_VAL
+ SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckPatternPredicate(unsigned PredNo) const override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckPatternPredicate(unsigned PredNo) const
+#if DAGISEL_INLINE
+ override
+#endif
+{
+ switch (PredNo) {
+ default: llvm_unreachable("Invalid predicate in table?");
+ case 0: return (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit());
+ case 1: return (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode());
+ case 2: return (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode());
+ case 3: return (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit());
+ case 4: return (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isTargetNaCl()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 5: return (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 6: return (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode());
+ case 7: return (Subtarget->inMicroMipsMode());
+ case 8: return (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isTargetNaCl()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 9: return (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6());
+ case 10: return (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 11: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 12: return (Subtarget->hasStandardEncoding()) && (!Subtarget->hasCnMips()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 13: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasCnMips()) && (!Subtarget->inMicroMipsMode());
+ case 14: return (Subtarget->inMips16Mode());
+ case 15: return (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode());
+ case 16: return (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode());
+ case 17: return (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat());
+ case 18: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode());
+ case 19: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode());
+ case 20: return (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit());
+ case 21: return (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat());
+ case 22: return (Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode());
+ case 23: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode());
+ case 24: return (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding());
+ case 25: return (Subtarget->hasMSA());
+ case 26: return (Subtarget->hasDSP());
+ case 27: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit());
+ case 28: return (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6());
+ case 29: return (Subtarget->hasCnMips());
+ case 30: return (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding());
+ case 31: return (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode());
+ case 32: return (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding());
+ case 33: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 34: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 35: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 36: return (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips4_32());
+ case 37: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 38: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 39: return (Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6());
+ case 40: return (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode());
+ case 41: return (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips4_32());
+ case 42: return (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips4_32());
+ case 43: return (Subtarget->hasEVA()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6());
+ case 44: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 45: return (Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode());
+ case 46: return (Subtarget->hasDSPR2());
+ case 47: return (Subtarget->hasDSPR2()) && (Subtarget->inMicroMipsMode());
+ case 48: return (Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode());
+ case 49: return (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 50: return (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding());
+ case 51: return (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6());
+ case 52: return (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode());
+ case 53: return (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode());
+ case 54: return (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode());
+ case 55: return (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (!Subtarget->inMicroMipsMode());
+ case 56: return (Subtarget->hasCnMips()) && (Subtarget->hasMips64()) && (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode());
+ case 57: return (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode());
+ case 58: return (Subtarget->hasMSA()) && (Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding());
+ case 59: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode());
+ case 60: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64());
+ case 61: return (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode());
+ case 62: return (Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat());
+ case 63: return (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 64: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode());
+ case 65: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding());
+ case 66: return (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP());
+ case 67: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode());
+ case 68: return (Subtarget->hasMSA()) && (Subtarget->isGP64bit());
+ case 69: return (Subtarget->hasStandardEncoding());
+ case 70: return (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode());
+ case 71: return (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard());
+ case 72: return (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode());
+ case 73: return (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard());
+ case 74: return (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 75: return (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard());
+ case 76: return (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode());
+ case 77: return (Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard());
+ case 78: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 79: return (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard());
+ case 80: return (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode());
+ case 81: return (Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard());
+ case 82: return (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 83: return (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 84: return (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 85: return (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode());
+ case 86: return (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode());
+ case 87: return (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard());
+ case 88: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 89: return (!Subtarget->inMips16Mode());
+ case 90: return (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 91: return (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!TM.isPositionIndependent());
+ case 92: return (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!TM.isPositionIndependent());
+ case 93: return (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (TM.isPositionIndependent());
+ case 94: return (Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding());
+ case 95: return (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 96: return (Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 97: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode());
+ case 98: return (Subtarget->hasMSA()) && (Subtarget->isLittle());
+ case 99: return (Subtarget->hasMSA()) && (!Subtarget->isLittle());
+ case 100: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 101: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 102: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 103: return (Subtarget->hasMips4_32()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 104: return (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6());
+ case 105: return (Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding());
+ case 106: return (Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 107: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 108: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 109: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 110: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 111: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 112: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 113: return (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode());
+ case 114: return (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode());
+ case 115: return (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat());
+ case 116: return (TM.Options.AllowFPOpFusion == FPOpFusion::Fast) && (Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding());
+ case 117: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 118: return (!Subtarget->disableMadd4()) && (Subtarget->inMicroMipsMode()) && (Subtarget->inMicroMipsMode()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips32r6());
+ case 119: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 120: return (!Subtarget->disableMadd4()) && (Subtarget->hasMips4_32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6());
+ case 121: return (!Subtarget->disableMadd4()) && (Subtarget->inMicroMipsMode()) && (Subtarget->inMicroMipsMode()) && (TM.Options.NoNaNsFPMath) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips32r6());
+ case 122: return (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat());
+ case 123: return (Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (Subtarget->isGP64bit());
+ case 124: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode());
+ case 125: return (!Subtarget->isFP64bit());
+ case 126: return (Subtarget->isFP64bit());
+ case 127: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit());
+ case 128: return (Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode());
+ case 129: return (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit());
+ case 130: return (Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit());
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckNodePredicate(SDNode *Node, unsigned PredNo) const
+#if DAGISEL_INLINE
+ override
+#endif
+{
+ switch (PredNo) {
+ default: llvm_unreachable("Invalid predicate in table?");
+ case 0: {
+ // Predicate_unindexedstore
+ SDNode *N = Node;
+if (cast<StoreSDNode>(N)->getAddressingMode() != ISD::UNINDEXED) return false;
+return true;
+
+ }
+ case 1: {
+ // Predicate_store
+ SDNode *N = Node;
+ if (cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 2: {
+ // Predicate_truncstore
+ SDNode *N = Node;
+ if (!cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 3: {
+ // Predicate_truncstorei8
+ SDNode *N = Node;
+if (cast<StoreSDNode>(N)->getMemoryVT() != MVT::i8) return false;
+return true;
+
+ }
+ case 4: {
+ // Predicate_truncstorei16
+ SDNode *N = Node;
+if (cast<StoreSDNode>(N)->getMemoryVT() != MVT::i16) return false;
+return true;
+
+ }
+ case 5: {
+ // Predicate_truncstorei32
+ SDNode *N = Node;
+if (cast<StoreSDNode>(N)->getMemoryVT() != MVT::i32) return false;
+return true;
+
+ }
+ case 6: {
+ // Predicate_unindexedload
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getAddressingMode() != ISD::UNINDEXED) return false;
+return true;
+
+ }
+ case 7: {
+ // Predicate_zextload
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
+return true;
+
+ }
+ case 8: {
+ // Predicate_zextloadi8
+ // Predicate_sextloadi8
+ // Predicate_extloadi8
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getMemoryVT() != MVT::i8) return false;
+return true;
+
+ }
+ case 9: {
+ // Predicate_zextloadi16
+ // Predicate_sextloadi16
+ // Predicate_extloadi16
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getMemoryVT() != MVT::i16) return false;
+return true;
+
+ }
+ case 10: {
+ // Predicate_sextload
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
+return true;
+
+ }
+ case 11: {
+ // Predicate_load
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD) return false;
+return true;
+
+ }
+ case 12: {
+ // Predicate_extload
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
+return true;
+
+ }
+ case 13: {
+ // Predicate_extloadi1
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getMemoryVT() != MVT::i1) return false;
+return true;
+
+ }
+ case 14: {
+ // Predicate_sextloadi32
+ // Predicate_zextloadi32
+ // Predicate_extloadi32
+ SDNode *N = Node;
+if (cast<LoadSDNode>(N)->getMemoryVT() != MVT::i32) return false;
+return true;
+
+ }
+ case 15: {
+ // Predicate_immZExt5_64
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+ return Imm == (Imm & 0x1f);
+ }
+ case 16: {
+ // Predicate_PowerOf2LO
+ auto *N = cast<ConstantSDNode>(Node);
+
+ if (N->getValueType(0) == MVT::i64) {
+ uint64_t Imm = N->getZExtValue();
+ return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm;
+ }
+ else
+ return false;
+
+ }
+ case 17: {
+ // Predicate_PowerOf2HI
+ auto *N = cast<ConstantSDNode>(Node);
+
+ if (N->getValueType(0) == MVT::i64) {
+ uint64_t Imm = N->getZExtValue();
+ return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm;
+ }
+ else
+ return false;
+
+ }
+ case 18: {
+ // Predicate_PowerOf2LO_i32
+ auto *N = cast<ConstantSDNode>(Node);
+
+ if (N->getValueType(0) == MVT::i32) {
+ uint64_t Imm = N->getZExtValue();
+ return isPowerOf2_32(Imm) && isUInt<32>(Imm);
+ }
+ else
+ return false;
+
+ }
+ case 19: {
+ // Predicate_immSExt16
+ auto *N = cast<ConstantSDNode>(Node);
+ return isInt<16>(N->getSExtValue());
+ }
+ case 20: {
+ // Predicate_immSExt16Plus1
+ auto *N = cast<ConstantSDNode>(Node);
+
+ return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
+
+ }
+ case 21: {
+ // Predicate_immZExt16
+ auto *N = cast<ConstantSDNode>(Node);
+
+ if (N->getValueType(0) == MVT::i32)
+ return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
+ else
+ return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
+
+ }
+ case 22: {
+ // Predicate_immz
+ auto *N = cast<ConstantSDNode>(Node);
+ return N->getSExtValue() == 0;
+ }
+ case 23: {
+ // Predicate_immZExt16_64
+ auto *N = cast<ConstantSDNode>(Node);
+ return isUInt<16>(N->getZExtValue());
+ }
+ case 24: {
+ // Predicate_atomic_load_8
+ // Predicate_atomic_store_8
+ // Predicate_atomic_load_add_8
+ // Predicate_atomic_load_sub_8
+ // Predicate_atomic_load_and_8
+ // Predicate_atomic_load_or_8
+ // Predicate_atomic_load_xor_8
+ // Predicate_atomic_load_nand_8
+ // Predicate_atomic_swap_8
+ // Predicate_atomic_cmp_swap_8
+ SDNode *N = Node;
+if (cast<AtomicSDNode>(N)->getMemoryVT() != MVT::i8) return false;
+return true;
+
+ }
+ case 25: {
+ // Predicate_atomic_load_16
+ // Predicate_atomic_store_16
+ // Predicate_atomic_load_add_16
+ // Predicate_atomic_load_sub_16
+ // Predicate_atomic_load_and_16
+ // Predicate_atomic_load_or_16
+ // Predicate_atomic_load_xor_16
+ // Predicate_atomic_load_nand_16
+ // Predicate_atomic_swap_16
+ // Predicate_atomic_cmp_swap_16
+ SDNode *N = Node;
+if (cast<AtomicSDNode>(N)->getMemoryVT() != MVT::i16) return false;
+return true;
+
+ }
+ case 26: {
+ // Predicate_atomic_load_32
+ // Predicate_atomic_store_32
+ // Predicate_atomic_load_add_32
+ // Predicate_atomic_load_sub_32
+ // Predicate_atomic_load_and_32
+ // Predicate_atomic_load_or_32
+ // Predicate_atomic_load_xor_32
+ // Predicate_atomic_load_nand_32
+ // Predicate_atomic_swap_32
+ // Predicate_atomic_cmp_swap_32
+ SDNode *N = Node;
+if (cast<AtomicSDNode>(N)->getMemoryVT() != MVT::i32) return false;
+return true;
+
+ }
+ case 27: {
+ // Predicate_atomic_load_64
+ // Predicate_atomic_store_64
+ // Predicate_atomic_load_add_64
+ // Predicate_atomic_load_sub_64
+ // Predicate_atomic_load_and_64
+ // Predicate_atomic_load_or_64
+ // Predicate_atomic_load_xor_64
+ // Predicate_atomic_load_nand_64
+ // Predicate_atomic_swap_64
+ // Predicate_atomic_cmp_swap_64
+ SDNode *N = Node;
+if (cast<AtomicSDNode>(N)->getMemoryVT() != MVT::i64) return false;
+return true;
+
+ }
+ case 28: {
+ // Predicate_immZExt5
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return Imm == (Imm & 0x1f);
+ }
+ case 29: {
+ // Predicate_immZExt10
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<10>(Imm);
+ }
+ case 30: {
+ // Predicate_immZExt7
+ auto *N = cast<ConstantSDNode>(Node);
+ return isUInt<7>(N->getZExtValue());
+ }
+ case 31: {
+ // Predicate_immZExt4
+ // Predicate_immZExt4Ptr
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<4>(Imm);
+ }
+ case 32: {
+ // Predicate_immZExt3
+ // Predicate_immZExt3Ptr
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<3>(Imm);
+ }
+ case 33: {
+ // Predicate_immZExt2
+ // Predicate_immZExt2Ptr
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<2>(Imm);
+ }
+ case 34: {
+ // Predicate_immZExt8
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<8>(Imm);
+ }
+ case 35: {
+ // Predicate_immSExt10
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isInt<10>(Imm);
+ }
+ case 36: {
+ // Predicate_immZExt6
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return Imm == (Imm & 0x3f);
+ }
+ case 37: {
+ // Predicate_immZExt1
+ // Predicate_immZExt1Ptr
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<1>(Imm);
+ }
+ case 38: {
+ // Predicate_vsplat_imm_eq_1
+ SDNode *N = Node;
+
+ APInt Imm;
+ EVT EltTy = N->getValueType(0).getVectorElementType();
+
+ return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
+ Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
+
+ }
+ case 39: {
+ // Predicate_immi32Cst7
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<32>(Imm) && Imm == 7;
+ }
+ case 40: {
+ // Predicate_immi32Cst15
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<32>(Imm) && Imm == 15;
+ }
+ case 41: {
+ // Predicate_immi32Cst31
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<32>(Imm) && Imm == 31;
+ }
+ case 42: {
+ // Predicate_vsplati64_imm_eq_1
+ SDNode *N = Node;
+
+ APInt Imm;
+ SDNode *BV = N->getOperand(0).getNode();
+ EVT EltTy = N->getValueType(0).getVectorElementType();
+
+ return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
+ Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
+
+ }
+ case 43: {
+ // Predicate_vsplati64_imm_eq_63
+ SDNode *N = Node;
+
+ APInt Imm;
+ SDNode *BV = N->getOperand(0).getNode();
+ EVT EltTy = N->getValueType(0).getVectorElementType();
+
+ return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
+ Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63;
+
+ }
+ case 44: {
+ // Predicate_immZExt5Plus1
+ auto *N = cast<ConstantSDNode>(Node);
+
+ return isUInt<5>(N->getZExtValue() - 1);
+
+ }
+ case 45: {
+ // Predicate_immZExt5Plus33
+ auto *N = cast<ConstantSDNode>(Node);
+
+ return isUInt<5>(N->getZExtValue() - 33);
+
+ }
+ case 46: {
+ // Predicate_immZExt5Plus32
+ auto *N = cast<ConstantSDNode>(Node);
+
+ return isUInt<5>(N->getZExtValue() - 32);
+
+ }
+ case 47: {
+ // Predicate_immZExtAndi16
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
+ Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
+ Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
+ }
+ case 48: {
+ // Predicate_immAllOnesV
+ SDNode *N = Node;
+
+ return ISD::isBuildVectorAllOnes(N);
+
+ }
+ case 49: {
+ // Predicate_immSExt10_64
+ auto *N = cast<ConstantSDNode>(Node);
+ return isInt<10>(N->getSExtValue());
+ }
+ case 50: {
+ // Predicate_immZExt2Lsa
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<2>(Imm - 1);
+ }
+ case 51: {
+ // Predicate_immSExt8
+ auto *N = cast<ConstantSDNode>(Node);
+ return isInt<8>(N->getSExtValue());
+ }
+ case 52: {
+ // Predicate_immSExtAddiur2
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return Imm == 1 || Imm == -1 ||
+ ((Imm % 4 == 0) &&
+ Imm < 28 && Imm > 0);
+ }
+ case 53: {
+ // Predicate_immSExtAddius5
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return Imm >= -8 && Imm <= 7;
+ }
+ case 54: {
+ // Predicate_immZExt2Shift
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return Imm >= 1 && Imm <= 8;
+ }
+ case 55: {
+ // Predicate_assertzext_lt_i32
+ SDNode *N = Node;
+
+ return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
+
+ }
+ case 56: {
+ // Predicate_immSExt6
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isInt<6>(Imm);
+ }
+ case 57: {
+ // Predicate_LUiPred
+ auto *N = cast<ConstantSDNode>(Node);
+
+ int64_t Val = N->getSExtValue();
+ return !isInt<16>(Val) && isInt<32>(Val) && !(Val & 0xffff);
+
+ }
+ case 58: {
+ // Predicate_ORiPred
+ auto *N = cast<ConstantSDNode>(Node);
+
+ return isUInt<16>(N->getZExtValue()) && !isInt<16>(N->getSExtValue());
+
+ }
+ case 59: {
+ // Predicate_immLi16
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return Imm >= -1 && Imm <= 126;
+ }
+ case 60: {
+ // Predicate_LUiORiPred
+ auto *N = cast<ConstantSDNode>(Node);
+
+ int64_t SVal = N->getSExtValue();
+ return isInt<32>(SVal) && (SVal & 0xffff);
+
+ }
+ case 61: {
+ // Predicate_immZExt32Low16Zero
+ auto *N = cast<ConstantSDNode>(Node);
+
+ uint64_t Val = N->getZExtValue();
+ return isUInt<32>(Val) && !(Val & 0xffff);
+
+ }
+ case 62: {
+ // Predicate_immZExt32
+ auto *N = cast<ConstantSDNode>(Node);
+ return isUInt<32>(N->getZExtValue());
+ }
+ case 63: {
+ // Predicate_fpimm0
+ auto *N = cast<ConstantFPSDNode>(Node);
+
+ return N->isExactlyValue(+0.0);
+
+ }
+ case 64: {
+ // Predicate_fpimm0neg
+ auto *N = cast<ConstantFPSDNode>(Node);
+
+ return N->isExactlyValue(-0.0);
+
+ }
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckComplexPattern(SDNode *Root, SDNode *Parent,
+ SDValue N, unsigned PatternNo,
+ SmallVectorImpl<std::pair<SDValue, SDNode*>> &Result) override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckComplexPattern(SDNode *Root, SDNode *Parent,
+ SDValue N, unsigned PatternNo,
+ SmallVectorImpl<std::pair<SDValue, SDNode*>> &Result)
+#if DAGISEL_INLINE
+ override
+#endif
+{
+ unsigned NextRes = Result.size();
+ switch (PatternNo) {
+ default: llvm_unreachable("Invalid pattern # in table?");
+ case 0:
+ Result.resize(NextRes+2);
+ return selectAddrRegImm(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 1:
+ Result.resize(NextRes+2);
+ return selectIntAddr(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 2:
+ Result.resize(NextRes+2);
+ return selectAddrDefault(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 3:
+ Result.resize(NextRes+2);
+ return selectAddr16(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 4:
+ Result.resize(NextRes+2);
+ return selectAddr16SP(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 5:
+ Result.resize(NextRes+2);
+ return selectIntAddrLSL2MM(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 6:
+ Result.resize(NextRes+2);
+ return selectIntAddr11MM(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 7:
+ Result.resize(NextRes+2);
+ return selectIntAddr16MM(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 8:
+ Result.resize(NextRes+2);
+ return selectIntAddrSImm10(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 9:
+ Result.resize(NextRes+2);
+ return selectIntAddrSImm10Lsl1(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 10:
+ Result.resize(NextRes+2);
+ return selectIntAddrSImm10Lsl2(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 11:
+ Result.resize(NextRes+2);
+ return selectIntAddrSImm10Lsl3(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 12:
+ Result.resize(NextRes+2);
+ return selectIntAddr12MM(N, Result[NextRes+0].first, Result[NextRes+1].first);
+ case 13:
+ Result.resize(NextRes+1);
+ return selectVSplatUimmPow2(N, Result[NextRes+0].first);
+ case 14:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm8(N, Result[NextRes+0].first);
+ case 15:
+ Result.resize(NextRes+1);
+ return selectVSplatUimmInvPow2(N, Result[NextRes+0].first);
+ case 16:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm5(N, Result[NextRes+0].first);
+ case 17:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm5(N, Result[NextRes+0].first);
+ case 18:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm5(N, Result[NextRes+0].first);
+ case 19:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm5(N, Result[NextRes+0].first);
+ case 20:
+ Result.resize(NextRes+1);
+ return selectVSplatSimm5(N, Result[NextRes+0].first);
+ case 21:
+ Result.resize(NextRes+1);
+ return selectVSplatSimm5(N, Result[NextRes+0].first);
+ case 22:
+ Result.resize(NextRes+1);
+ return selectVSplatSimm5(N, Result[NextRes+0].first);
+ case 23:
+ Result.resize(NextRes+1);
+ return selectVSplatSimm5(N, Result[NextRes+0].first);
+ case 24:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm3(N, Result[NextRes+0].first);
+ case 25:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm4(N, Result[NextRes+0].first);
+ case 26:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm6(N, Result[NextRes+0].first);
+ case 27:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm4(N, Result[NextRes+0].first);
+ case 28:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm3(N, Result[NextRes+0].first);
+ case 29:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm2(N, Result[NextRes+0].first);
+ case 30:
+ Result.resize(NextRes+1);
+ return selectVSplatUimm1(N, Result[NextRes+0].first);
+ case 31:
+ Result.resize(NextRes+1);
+ return selectVSplatMaskL(N, Result[NextRes+0].first);
+ case 32:
+ Result.resize(NextRes+1);
+ return selectVSplatMaskL(N, Result[NextRes+0].first);
+ case 33:
+ Result.resize(NextRes+1);
+ return selectVSplatMaskL(N, Result[NextRes+0].first);
+ case 34:
+ Result.resize(NextRes+1);
+ return selectVSplatMaskL(N, Result[NextRes+0].first);
+ case 35:
+ Result.resize(NextRes+1);
+ return selectVSplatMaskR(N, Result[NextRes+0].first);
+ case 36:
+ Result.resize(NextRes+1);
+ return selectVSplatMaskR(N, Result[NextRes+0].first);
+ case 37:
+ Result.resize(NextRes+1);
+ return selectVSplatMaskR(N, Result[NextRes+0].first);
+ case 38:
+ Result.resize(NextRes+1);
+ return selectVSplatMaskR(N, Result[NextRes+0].first);
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+SDValue DAGISEL_CLASS_COLONCOLON RunSDNodeXForm(SDValue V, unsigned XFormNo)
+#if DAGISEL_INLINE
+ override
+#endif
+{
+ switch (XFormNo) {
+ default: llvm_unreachable("Invalid xform # in table?");
+ case 0: { // Log2LO
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return getImm(N, Log2_64((unsigned) N->getZExtValue()));
+
+ }
+ case 1: { // Log2HI
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
+
+ }
+ case 2: { // Plus1
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+ return getImm(N, N->getSExtValue() + 1);
+ }
+ case 3: { // LO16
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return getImm(N, N->getZExtValue() & 0xFFFF);
+
+ }
+ case 4: { // immZExt5To31
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return getImm(N, 31 - N->getZExtValue());
+
+ }
+ case 5: { // HI16
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
+
+ }
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+
+#ifdef DAGISEL_INLINE
+#undef DAGISEL_INLINE
+#endif
+#ifdef DAGISEL_CLASS_COLONCOLON
+#undef DAGISEL_CLASS_COLONCOLON
+#endif
+#ifdef GET_DAGISEL_DECL
+#undef GET_DAGISEL_DECL
+#endif
+#ifdef GET_DAGISEL_BODY
+#undef GET_DAGISEL_BODY
+#endif
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenDisassemblerTables.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenDisassemblerTables.inc
new file mode 100644
index 0000000..4a25dac
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenDisassemblerTables.inc
@@ -0,0 +1,10398 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* * Mips Disassembler *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#include "llvm/MC/MCInst.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/LEB128.h"
+#include "llvm/Support/raw_ostream.h"
+#include <assert.h>
+
+namespace llvm {
+
+// Helper function for extracting fields from encoded instructions.
+template<typename InsnType>
+#if defined(_MSC_VER) && !defined(__clang__)
+__declspec(noinline)
+#endif
+static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
+ unsigned numBits) {
+ assert(startBit + numBits <= (sizeof(InsnType)*8) &&
+ "Instruction field out of bounds!");
+ InsnType fieldMask;
+ if (numBits == sizeof(InsnType)*8)
+ fieldMask = (InsnType)(-1LL);
+ else
+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
+ return (insn & fieldMask) >> startBit;
+}
+
+static const uint8_t DecoderTable16[] = {
+/* 0 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 3 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 17
+/* 8 */ MCD::OPC_CheckPredicate, 0, 71, 2, 0, // Skip to: 596
+/* 13 */ MCD::OPC_Decode, 196, 6, 0, // Opcode: Bimm16
+/* 17 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 31
+/* 22 */ MCD::OPC_CheckPredicate, 0, 57, 2, 0, // Skip to: 596
+/* 27 */ MCD::OPC_Decode, 194, 6, 1, // Opcode: BeqzRxImm16
+/* 31 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 45
+/* 36 */ MCD::OPC_CheckPredicate, 0, 43, 2, 0, // Skip to: 596
+/* 41 */ MCD::OPC_Decode, 198, 6, 1, // Opcode: BnezRxImm16
+/* 45 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 59
+/* 50 */ MCD::OPC_CheckPredicate, 0, 29, 2, 0, // Skip to: 596
+/* 55 */ MCD::OPC_Decode, 129, 5, 2, // Opcode: AddiuRxRxImm16
+/* 59 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 73
+/* 64 */ MCD::OPC_CheckPredicate, 0, 15, 2, 0, // Skip to: 596
+/* 69 */ MCD::OPC_Decode, 221, 19, 1, // Opcode: SltiRxImm16
+/* 73 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 87
+/* 78 */ MCD::OPC_CheckPredicate, 0, 1, 2, 0, // Skip to: 596
+/* 83 */ MCD::OPC_Decode, 223, 19, 1, // Opcode: SltiuRxImm16
+/* 87 */ MCD::OPC_FilterValue, 12, 73, 0, 0, // Skip to: 165
+/* 92 */ MCD::OPC_ExtractField, 8, 3, // Inst{10-8} ...
+/* 95 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 109
+/* 100 */ MCD::OPC_CheckPredicate, 0, 235, 1, 0, // Skip to: 596
+/* 105 */ MCD::OPC_Decode, 201, 6, 0, // Opcode: Bteqz16
+/* 109 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 123
+/* 114 */ MCD::OPC_CheckPredicate, 0, 221, 1, 0, // Skip to: 596
+/* 119 */ MCD::OPC_Decode, 203, 6, 0, // Opcode: Btnez16
+/* 123 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 137
+/* 128 */ MCD::OPC_CheckPredicate, 0, 207, 1, 0, // Skip to: 596
+/* 133 */ MCD::OPC_Decode, 132, 5, 0, // Opcode: AddiuSpImm16
+/* 137 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 151
+/* 142 */ MCD::OPC_CheckPredicate, 0, 193, 1, 0, // Skip to: 596
+/* 147 */ MCD::OPC_Decode, 235, 15, 3, // Opcode: Move32R16
+/* 151 */ MCD::OPC_FilterValue, 7, 184, 1, 0, // Skip to: 596
+/* 156 */ MCD::OPC_CheckPredicate, 0, 179, 1, 0, // Skip to: 596
+/* 161 */ MCD::OPC_Decode, 236, 15, 4, // Opcode: MoveR3216
+/* 165 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 179
+/* 170 */ MCD::OPC_CheckPredicate, 0, 165, 1, 0, // Skip to: 596
+/* 175 */ MCD::OPC_Decode, 191, 13, 1, // Opcode: LiRxImm16
+/* 179 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 193
+/* 184 */ MCD::OPC_CheckPredicate, 0, 151, 1, 0, // Skip to: 596
+/* 189 */ MCD::OPC_Decode, 134, 9, 1, // Opcode: CmpiRxImm16
+/* 193 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 207
+/* 198 */ MCD::OPC_CheckPredicate, 0, 137, 1, 0, // Skip to: 596
+/* 203 */ MCD::OPC_Decode, 194, 13, 1, // Opcode: LwRxPcTcp16
+/* 207 */ MCD::OPC_FilterValue, 28, 31, 0, 0, // Skip to: 243
+/* 212 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 215 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 229
+/* 220 */ MCD::OPC_CheckPredicate, 0, 115, 1, 0, // Skip to: 596
+/* 225 */ MCD::OPC_Decode, 134, 5, 5, // Opcode: AdduRxRyRz16
+/* 229 */ MCD::OPC_FilterValue, 3, 106, 1, 0, // Skip to: 596
+/* 234 */ MCD::OPC_CheckPredicate, 0, 101, 1, 0, // Skip to: 596
+/* 239 */ MCD::OPC_Decode, 230, 19, 5, // Opcode: SubuRxRyRz16
+/* 243 */ MCD::OPC_FilterValue, 29, 92, 1, 0, // Skip to: 596
+/* 248 */ MCD::OPC_ExtractField, 0, 5, // Inst{4-0} ...
+/* 251 */ MCD::OPC_FilterValue, 0, 73, 0, 0, // Skip to: 329
+/* 256 */ MCD::OPC_ExtractField, 5, 3, // Inst{7-5} ...
+/* 259 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 273
+/* 264 */ MCD::OPC_CheckPredicate, 0, 71, 1, 0, // Skip to: 596
+/* 269 */ MCD::OPC_Decode, 198, 12, 0, // Opcode: JumpLinkReg16
+/* 273 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 294
+/* 278 */ MCD::OPC_CheckPredicate, 0, 57, 1, 0, // Skip to: 596
+/* 283 */ MCD::OPC_CheckField, 8, 3, 0, 50, 1, 0, // Skip to: 596
+/* 290 */ MCD::OPC_Decode, 195, 12, 0, // Opcode: JrRa16
+/* 294 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 308
+/* 299 */ MCD::OPC_CheckPredicate, 0, 36, 1, 0, // Skip to: 596
+/* 304 */ MCD::OPC_Decode, 197, 12, 1, // Opcode: JrcRx16
+/* 308 */ MCD::OPC_FilterValue, 7, 27, 1, 0, // Skip to: 596
+/* 313 */ MCD::OPC_CheckPredicate, 0, 22, 1, 0, // Skip to: 596
+/* 318 */ MCD::OPC_CheckField, 8, 3, 0, 15, 1, 0, // Skip to: 596
+/* 325 */ MCD::OPC_Decode, 196, 12, 0, // Opcode: JrcRa16
+/* 329 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 343
+/* 334 */ MCD::OPC_CheckPredicate, 0, 1, 1, 0, // Skip to: 596
+/* 339 */ MCD::OPC_Decode, 220, 19, 6, // Opcode: SltRxRy16
+/* 343 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 357
+/* 348 */ MCD::OPC_CheckPredicate, 0, 243, 0, 0, // Skip to: 596
+/* 353 */ MCD::OPC_Decode, 225, 19, 6, // Opcode: SltuRxRy16
+/* 357 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 371
+/* 362 */ MCD::OPC_CheckPredicate, 0, 229, 0, 0, // Skip to: 596
+/* 367 */ MCD::OPC_Decode, 219, 19, 7, // Opcode: SllvRxRy16
+/* 371 */ MCD::OPC_FilterValue, 5, 16, 0, 0, // Skip to: 392
+/* 376 */ MCD::OPC_CheckPredicate, 0, 215, 0, 0, // Skip to: 596
+/* 381 */ MCD::OPC_CheckField, 5, 6, 0, 208, 0, 0, // Skip to: 596
+/* 388 */ MCD::OPC_Decode, 200, 6, 0, // Opcode: Break16
+/* 392 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 406
+/* 397 */ MCD::OPC_CheckPredicate, 0, 194, 0, 0, // Skip to: 596
+/* 402 */ MCD::OPC_Decode, 229, 19, 7, // Opcode: SrlvRxRy16
+/* 406 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 420
+/* 411 */ MCD::OPC_CheckPredicate, 0, 180, 0, 0, // Skip to: 596
+/* 416 */ MCD::OPC_Decode, 227, 19, 7, // Opcode: SravRxRy16
+/* 420 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 434
+/* 425 */ MCD::OPC_CheckPredicate, 0, 166, 0, 0, // Skip to: 596
+/* 430 */ MCD::OPC_Decode, 133, 9, 6, // Opcode: CmpRxRy16
+/* 434 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 448
+/* 439 */ MCD::OPC_CheckPredicate, 0, 152, 0, 0, // Skip to: 596
+/* 444 */ MCD::OPC_Decode, 135, 5, 7, // Opcode: AndRxRxRy16
+/* 448 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 462
+/* 453 */ MCD::OPC_CheckPredicate, 0, 138, 0, 0, // Skip to: 596
+/* 458 */ MCD::OPC_Decode, 149, 16, 7, // Opcode: OrRxRxRy16
+/* 462 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 476
+/* 467 */ MCD::OPC_CheckPredicate, 0, 124, 0, 0, // Skip to: 596
+/* 472 */ MCD::OPC_Decode, 194, 20, 7, // Opcode: XorRxRxRy16
+/* 476 */ MCD::OPC_FilterValue, 15, 9, 0, 0, // Skip to: 490
+/* 481 */ MCD::OPC_CheckPredicate, 0, 110, 0, 0, // Skip to: 596
+/* 486 */ MCD::OPC_Decode, 136, 16, 6, // Opcode: NotRxRy16
+/* 490 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 504
+/* 495 */ MCD::OPC_CheckPredicate, 0, 96, 0, 0, // Skip to: 596
+/* 500 */ MCD::OPC_Decode, 233, 15, 1, // Opcode: Mfhi16
+/* 504 */ MCD::OPC_FilterValue, 17, 31, 0, 0, // Skip to: 540
+/* 509 */ MCD::OPC_ExtractField, 5, 3, // Inst{7-5} ...
+/* 512 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 526
+/* 517 */ MCD::OPC_CheckPredicate, 0, 74, 0, 0, // Skip to: 596
+/* 522 */ MCD::OPC_Decode, 215, 19, 2, // Opcode: SebRx16
+/* 526 */ MCD::OPC_FilterValue, 5, 65, 0, 0, // Skip to: 596
+/* 531 */ MCD::OPC_CheckPredicate, 0, 60, 0, 0, // Skip to: 596
+/* 536 */ MCD::OPC_Decode, 216, 19, 2, // Opcode: SehRx16
+/* 540 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 554
+/* 545 */ MCD::OPC_CheckPredicate, 0, 46, 0, 0, // Skip to: 596
+/* 550 */ MCD::OPC_Decode, 234, 15, 1, // Opcode: Mflo16
+/* 554 */ MCD::OPC_FilterValue, 26, 9, 0, 0, // Skip to: 568
+/* 559 */ MCD::OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 596
+/* 564 */ MCD::OPC_Decode, 143, 10, 6, // Opcode: DivRxRy16
+/* 568 */ MCD::OPC_FilterValue, 27, 9, 0, 0, // Skip to: 582
+/* 573 */ MCD::OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 596
+/* 578 */ MCD::OPC_Decode, 144, 10, 6, // Opcode: DivuRxRy16
+/* 582 */ MCD::OPC_FilterValue, 29, 9, 0, 0, // Skip to: 596
+/* 587 */ MCD::OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 596
+/* 592 */ MCD::OPC_Decode, 135, 16, 6, // Opcode: NegRxRy16
+/* 596 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTable32[] = {
+/* 0 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 3 */ MCD::OPC_FilterValue, 1, 23, 0, 0, // Skip to: 31
+/* 8 */ MCD::OPC_CheckPredicate, 0, 2, 2, 0, // Skip to: 527
+/* 13 */ MCD::OPC_CheckField, 27, 5, 30, 251, 1, 0, // Skip to: 527
+/* 20 */ MCD::OPC_CheckField, 5, 3, 0, 244, 1, 0, // Skip to: 527
+/* 27 */ MCD::OPC_Decode, 128, 5, 1, // Opcode: AddiuRxPcImmX16
+/* 31 */ MCD::OPC_FilterValue, 2, 23, 0, 0, // Skip to: 59
+/* 36 */ MCD::OPC_CheckPredicate, 0, 230, 1, 0, // Skip to: 527
+/* 41 */ MCD::OPC_CheckField, 27, 5, 30, 223, 1, 0, // Skip to: 527
+/* 48 */ MCD::OPC_CheckField, 5, 6, 0, 216, 1, 0, // Skip to: 527
+/* 55 */ MCD::OPC_Decode, 197, 6, 8, // Opcode: BimmX16
+/* 59 */ MCD::OPC_FilterValue, 4, 23, 0, 0, // Skip to: 87
+/* 64 */ MCD::OPC_CheckPredicate, 0, 202, 1, 0, // Skip to: 527
+/* 69 */ MCD::OPC_CheckField, 27, 5, 30, 195, 1, 0, // Skip to: 527
+/* 76 */ MCD::OPC_CheckField, 5, 3, 0, 188, 1, 0, // Skip to: 527
+/* 83 */ MCD::OPC_Decode, 195, 6, 1, // Opcode: BeqzRxImmX16
+/* 87 */ MCD::OPC_FilterValue, 5, 23, 0, 0, // Skip to: 115
+/* 92 */ MCD::OPC_CheckPredicate, 0, 174, 1, 0, // Skip to: 527
+/* 97 */ MCD::OPC_CheckField, 27, 5, 30, 167, 1, 0, // Skip to: 527
+/* 104 */ MCD::OPC_CheckField, 5, 3, 0, 160, 1, 0, // Skip to: 527
+/* 111 */ MCD::OPC_Decode, 199, 6, 1, // Opcode: BnezRxImmX16
+/* 115 */ MCD::OPC_FilterValue, 6, 106, 0, 0, // Skip to: 226
+/* 120 */ MCD::OPC_ExtractField, 27, 5, // Inst{31-27} ...
+/* 123 */ MCD::OPC_FilterValue, 30, 143, 1, 0, // Skip to: 527
+/* 128 */ MCD::OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 131 */ MCD::OPC_FilterValue, 0, 45, 0, 0, // Skip to: 181
+/* 136 */ MCD::OPC_ExtractField, 0, 5, // Inst{4-0} ...
+/* 139 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 153
+/* 144 */ MCD::OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 181
+/* 149 */ MCD::OPC_Decode, 218, 19, 6, // Opcode: SllX16
+/* 153 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 167
+/* 158 */ MCD::OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 181
+/* 163 */ MCD::OPC_Decode, 228, 19, 6, // Opcode: SrlX16
+/* 167 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 181
+/* 172 */ MCD::OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 181
+/* 177 */ MCD::OPC_Decode, 226, 19, 6, // Opcode: SraX16
+/* 181 */ MCD::OPC_ExtractField, 5, 6, // Inst{10-5} ...
+/* 184 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 198
+/* 189 */ MCD::OPC_CheckPredicate, 0, 77, 1, 0, // Skip to: 527
+/* 194 */ MCD::OPC_Decode, 202, 6, 0, // Opcode: BteqzX16
+/* 198 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 212
+/* 203 */ MCD::OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 527
+/* 208 */ MCD::OPC_Decode, 204, 6, 0, // Opcode: BtnezX16
+/* 212 */ MCD::OPC_FilterValue, 24, 54, 1, 0, // Skip to: 527
+/* 217 */ MCD::OPC_CheckPredicate, 0, 49, 1, 0, // Skip to: 527
+/* 222 */ MCD::OPC_Decode, 133, 5, 0, // Opcode: AddiuSpImmX16
+/* 226 */ MCD::OPC_FilterValue, 8, 23, 0, 0, // Skip to: 254
+/* 231 */ MCD::OPC_CheckPredicate, 0, 35, 1, 0, // Skip to: 527
+/* 236 */ MCD::OPC_CheckField, 27, 5, 30, 28, 1, 0, // Skip to: 527
+/* 243 */ MCD::OPC_CheckField, 4, 1, 0, 21, 1, 0, // Skip to: 527
+/* 250 */ MCD::OPC_Decode, 131, 5, 9, // Opcode: AddiuRxRyOffMemX16
+/* 254 */ MCD::OPC_FilterValue, 9, 23, 0, 0, // Skip to: 282
+/* 259 */ MCD::OPC_CheckPredicate, 0, 7, 1, 0, // Skip to: 527
+/* 264 */ MCD::OPC_CheckField, 27, 5, 30, 0, 1, 0, // Skip to: 527
+/* 271 */ MCD::OPC_CheckField, 5, 3, 0, 249, 0, 0, // Skip to: 527
+/* 278 */ MCD::OPC_Decode, 255, 4, 1, // Opcode: AddiuRxImmX16
+/* 282 */ MCD::OPC_FilterValue, 10, 23, 0, 0, // Skip to: 310
+/* 287 */ MCD::OPC_CheckPredicate, 0, 235, 0, 0, // Skip to: 527
+/* 292 */ MCD::OPC_CheckField, 27, 5, 30, 228, 0, 0, // Skip to: 527
+/* 299 */ MCD::OPC_CheckField, 5, 3, 0, 221, 0, 0, // Skip to: 527
+/* 306 */ MCD::OPC_Decode, 222, 19, 1, // Opcode: SltiRxImmX16
+/* 310 */ MCD::OPC_FilterValue, 11, 23, 0, 0, // Skip to: 338
+/* 315 */ MCD::OPC_CheckPredicate, 0, 207, 0, 0, // Skip to: 527
+/* 320 */ MCD::OPC_CheckField, 27, 5, 30, 200, 0, 0, // Skip to: 527
+/* 327 */ MCD::OPC_CheckField, 5, 3, 0, 193, 0, 0, // Skip to: 527
+/* 334 */ MCD::OPC_Decode, 224, 19, 1, // Opcode: SltiuRxImmX16
+/* 338 */ MCD::OPC_FilterValue, 13, 23, 0, 0, // Skip to: 366
+/* 343 */ MCD::OPC_CheckPredicate, 0, 179, 0, 0, // Skip to: 527
+/* 348 */ MCD::OPC_CheckField, 27, 5, 30, 172, 0, 0, // Skip to: 527
+/* 355 */ MCD::OPC_CheckField, 5, 3, 0, 165, 0, 0, // Skip to: 527
+/* 362 */ MCD::OPC_Decode, 193, 13, 1, // Opcode: LiRxImmX16
+/* 366 */ MCD::OPC_FilterValue, 14, 23, 0, 0, // Skip to: 394
+/* 371 */ MCD::OPC_CheckPredicate, 0, 151, 0, 0, // Skip to: 527
+/* 376 */ MCD::OPC_CheckField, 27, 5, 30, 144, 0, 0, // Skip to: 527
+/* 383 */ MCD::OPC_CheckField, 5, 3, 0, 137, 0, 0, // Skip to: 527
+/* 390 */ MCD::OPC_Decode, 135, 9, 1, // Opcode: CmpiRxImmX16
+/* 394 */ MCD::OPC_FilterValue, 18, 16, 0, 0, // Skip to: 415
+/* 399 */ MCD::OPC_CheckPredicate, 0, 123, 0, 0, // Skip to: 527
+/* 404 */ MCD::OPC_CheckField, 27, 5, 30, 116, 0, 0, // Skip to: 527
+/* 411 */ MCD::OPC_Decode, 197, 13, 9, // Opcode: LwRxSpImmX16
+/* 415 */ MCD::OPC_FilterValue, 22, 23, 0, 0, // Skip to: 443
+/* 420 */ MCD::OPC_CheckPredicate, 0, 102, 0, 0, // Skip to: 527
+/* 425 */ MCD::OPC_CheckField, 27, 5, 30, 95, 0, 0, // Skip to: 527
+/* 432 */ MCD::OPC_CheckField, 5, 3, 0, 88, 0, 0, // Skip to: 527
+/* 439 */ MCD::OPC_Decode, 195, 13, 1, // Opcode: LwRxPcTcpX16
+/* 443 */ MCD::OPC_FilterValue, 24, 16, 0, 0, // Skip to: 464
+/* 448 */ MCD::OPC_CheckPredicate, 0, 74, 0, 0, // Skip to: 527
+/* 453 */ MCD::OPC_CheckField, 27, 5, 30, 67, 0, 0, // Skip to: 527
+/* 460 */ MCD::OPC_Decode, 214, 19, 9, // Opcode: SbRxRyOffMemX16
+/* 464 */ MCD::OPC_FilterValue, 25, 16, 0, 0, // Skip to: 485
+/* 469 */ MCD::OPC_CheckPredicate, 0, 53, 0, 0, // Skip to: 527
+/* 474 */ MCD::OPC_CheckField, 27, 5, 30, 46, 0, 0, // Skip to: 527
+/* 481 */ MCD::OPC_Decode, 217, 19, 9, // Opcode: ShRxRyOffMemX16
+/* 485 */ MCD::OPC_FilterValue, 26, 16, 0, 0, // Skip to: 506
+/* 490 */ MCD::OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 527
+/* 495 */ MCD::OPC_CheckField, 27, 5, 30, 25, 0, 0, // Skip to: 527
+/* 502 */ MCD::OPC_Decode, 232, 19, 9, // Opcode: SwRxSpImmX16
+/* 506 */ MCD::OPC_FilterValue, 27, 16, 0, 0, // Skip to: 527
+/* 511 */ MCD::OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 527
+/* 516 */ MCD::OPC_CheckField, 27, 5, 30, 4, 0, 0, // Skip to: 527
+/* 523 */ MCD::OPC_Decode, 231, 19, 9, // Opcode: SwRxRyOffMemX16
+/* 527 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableCOP3_32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 51, 9, 0, 0, // Skip to: 17
+/* 8 */ MCD::OPC_CheckPredicate, 1, 46, 0, 0, // Skip to: 59
+/* 13 */ MCD::OPC_Decode, 154, 13, 10, // Opcode: LWC3
+/* 17 */ MCD::OPC_FilterValue, 55, 9, 0, 0, // Skip to: 31
+/* 22 */ MCD::OPC_CheckPredicate, 2, 32, 0, 0, // Skip to: 59
+/* 27 */ MCD::OPC_Decode, 222, 12, 10, // Opcode: LDC3
+/* 31 */ MCD::OPC_FilterValue, 59, 9, 0, 0, // Skip to: 45
+/* 36 */ MCD::OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 59
+/* 41 */ MCD::OPC_Decode, 179, 19, 10, // Opcode: SWC3
+/* 45 */ MCD::OPC_FilterValue, 63, 9, 0, 0, // Skip to: 59
+/* 50 */ MCD::OPC_CheckPredicate, 2, 4, 0, 0, // Skip to: 59
+/* 55 */ MCD::OPC_Decode, 177, 17, 10, // Opcode: SDC3
+/* 59 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableCnMips32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 18, 31, 0, 0, // Skip to: 39
+/* 8 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 11 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25
+/* 16 */ MCD::OPC_CheckPredicate, 3, 239, 1, 0, // Skip to: 516
+/* 21 */ MCD::OPC_Decode, 181, 9, 11, // Opcode: DMFC2_OCTEON
+/* 25 */ MCD::OPC_FilterValue, 5, 230, 1, 0, // Skip to: 516
+/* 30 */ MCD::OPC_CheckPredicate, 3, 225, 1, 0, // Skip to: 516
+/* 35 */ MCD::OPC_Decode, 189, 9, 11, // Opcode: DMTC2_OCTEON
+/* 39 */ MCD::OPC_FilterValue, 28, 160, 1, 0, // Skip to: 460
+/* 44 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 47 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 68
+/* 52 */ MCD::OPC_CheckPredicate, 3, 203, 1, 0, // Skip to: 516
+/* 57 */ MCD::OPC_CheckField, 6, 5, 0, 196, 1, 0, // Skip to: 516
+/* 64 */ MCD::OPC_Decode, 193, 9, 12, // Opcode: DMUL
+/* 68 */ MCD::OPC_FilterValue, 8, 16, 0, 0, // Skip to: 89
+/* 73 */ MCD::OPC_CheckPredicate, 3, 182, 1, 0, // Skip to: 516
+/* 78 */ MCD::OPC_CheckField, 6, 15, 0, 175, 1, 0, // Skip to: 516
+/* 85 */ MCD::OPC_Decode, 176, 15, 13, // Opcode: MTM0
+/* 89 */ MCD::OPC_FilterValue, 9, 16, 0, 0, // Skip to: 110
+/* 94 */ MCD::OPC_CheckPredicate, 3, 161, 1, 0, // Skip to: 516
+/* 99 */ MCD::OPC_CheckField, 6, 15, 0, 154, 1, 0, // Skip to: 516
+/* 106 */ MCD::OPC_Decode, 179, 15, 13, // Opcode: MTP0
+/* 110 */ MCD::OPC_FilterValue, 10, 16, 0, 0, // Skip to: 131
+/* 115 */ MCD::OPC_CheckPredicate, 3, 140, 1, 0, // Skip to: 516
+/* 120 */ MCD::OPC_CheckField, 6, 15, 0, 133, 1, 0, // Skip to: 516
+/* 127 */ MCD::OPC_Decode, 180, 15, 13, // Opcode: MTP1
+/* 131 */ MCD::OPC_FilterValue, 11, 16, 0, 0, // Skip to: 152
+/* 136 */ MCD::OPC_CheckPredicate, 3, 119, 1, 0, // Skip to: 516
+/* 141 */ MCD::OPC_CheckField, 6, 15, 0, 112, 1, 0, // Skip to: 516
+/* 148 */ MCD::OPC_Decode, 181, 15, 13, // Opcode: MTP2
+/* 152 */ MCD::OPC_FilterValue, 12, 16, 0, 0, // Skip to: 173
+/* 157 */ MCD::OPC_CheckPredicate, 3, 98, 1, 0, // Skip to: 516
+/* 162 */ MCD::OPC_CheckField, 6, 15, 0, 91, 1, 0, // Skip to: 516
+/* 169 */ MCD::OPC_Decode, 177, 15, 13, // Opcode: MTM1
+/* 173 */ MCD::OPC_FilterValue, 13, 16, 0, 0, // Skip to: 194
+/* 178 */ MCD::OPC_CheckPredicate, 3, 77, 1, 0, // Skip to: 516
+/* 183 */ MCD::OPC_CheckField, 6, 15, 0, 70, 1, 0, // Skip to: 516
+/* 190 */ MCD::OPC_Decode, 178, 15, 13, // Opcode: MTM2
+/* 194 */ MCD::OPC_FilterValue, 15, 16, 0, 0, // Skip to: 215
+/* 199 */ MCD::OPC_CheckPredicate, 3, 56, 1, 0, // Skip to: 516
+/* 204 */ MCD::OPC_CheckField, 6, 5, 0, 49, 1, 0, // Skip to: 516
+/* 211 */ MCD::OPC_Decode, 168, 20, 12, // Opcode: VMULU
+/* 215 */ MCD::OPC_FilterValue, 16, 16, 0, 0, // Skip to: 236
+/* 220 */ MCD::OPC_CheckPredicate, 3, 35, 1, 0, // Skip to: 516
+/* 225 */ MCD::OPC_CheckField, 6, 5, 0, 28, 1, 0, // Skip to: 516
+/* 232 */ MCD::OPC_Decode, 167, 20, 12, // Opcode: VMM0
+/* 236 */ MCD::OPC_FilterValue, 17, 16, 0, 0, // Skip to: 257
+/* 241 */ MCD::OPC_CheckPredicate, 3, 14, 1, 0, // Skip to: 516
+/* 246 */ MCD::OPC_CheckField, 6, 5, 0, 7, 1, 0, // Skip to: 516
+/* 253 */ MCD::OPC_Decode, 166, 20, 12, // Opcode: V3MULU
+/* 257 */ MCD::OPC_FilterValue, 40, 16, 0, 0, // Skip to: 278
+/* 262 */ MCD::OPC_CheckPredicate, 3, 249, 0, 0, // Skip to: 516
+/* 267 */ MCD::OPC_CheckField, 6, 5, 0, 242, 0, 0, // Skip to: 516
+/* 274 */ MCD::OPC_Decode, 137, 5, 12, // Opcode: BADDu
+/* 278 */ MCD::OPC_FilterValue, 42, 16, 0, 0, // Skip to: 299
+/* 283 */ MCD::OPC_CheckPredicate, 3, 228, 0, 0, // Skip to: 516
+/* 288 */ MCD::OPC_CheckField, 6, 5, 0, 221, 0, 0, // Skip to: 516
+/* 295 */ MCD::OPC_Decode, 208, 17, 12, // Opcode: SEQ
+/* 299 */ MCD::OPC_FilterValue, 43, 16, 0, 0, // Skip to: 320
+/* 304 */ MCD::OPC_CheckPredicate, 3, 207, 0, 0, // Skip to: 516
+/* 309 */ MCD::OPC_CheckField, 6, 5, 0, 200, 0, 0, // Skip to: 516
+/* 316 */ MCD::OPC_Decode, 178, 18, 12, // Opcode: SNE
+/* 320 */ MCD::OPC_FilterValue, 44, 23, 0, 0, // Skip to: 348
+/* 325 */ MCD::OPC_CheckPredicate, 3, 186, 0, 0, // Skip to: 516
+/* 330 */ MCD::OPC_CheckField, 16, 5, 0, 179, 0, 0, // Skip to: 516
+/* 337 */ MCD::OPC_CheckField, 6, 5, 0, 172, 0, 0, // Skip to: 516
+/* 344 */ MCD::OPC_Decode, 171, 16, 14, // Opcode: POP
+/* 348 */ MCD::OPC_FilterValue, 45, 23, 0, 0, // Skip to: 376
+/* 353 */ MCD::OPC_CheckPredicate, 3, 158, 0, 0, // Skip to: 516
+/* 358 */ MCD::OPC_CheckField, 16, 5, 0, 151, 0, 0, // Skip to: 516
+/* 365 */ MCD::OPC_CheckField, 6, 5, 0, 144, 0, 0, // Skip to: 516
+/* 372 */ MCD::OPC_Decode, 226, 9, 15, // Opcode: DPOP
+/* 376 */ MCD::OPC_FilterValue, 46, 9, 0, 0, // Skip to: 390
+/* 381 */ MCD::OPC_CheckPredicate, 3, 130, 0, 0, // Skip to: 516
+/* 386 */ MCD::OPC_Decode, 209, 17, 16, // Opcode: SEQi
+/* 390 */ MCD::OPC_FilterValue, 47, 9, 0, 0, // Skip to: 404
+/* 395 */ MCD::OPC_CheckPredicate, 3, 116, 0, 0, // Skip to: 516
+/* 400 */ MCD::OPC_Decode, 179, 18, 16, // Opcode: SNEi
+/* 404 */ MCD::OPC_FilterValue, 50, 9, 0, 0, // Skip to: 418
+/* 409 */ MCD::OPC_CheckPredicate, 4, 102, 0, 0, // Skip to: 516
+/* 414 */ MCD::OPC_Decode, 234, 6, 17, // Opcode: CINS
+/* 418 */ MCD::OPC_FilterValue, 51, 9, 0, 0, // Skip to: 432
+/* 423 */ MCD::OPC_CheckPredicate, 4, 88, 0, 0, // Skip to: 516
+/* 428 */ MCD::OPC_Decode, 235, 6, 17, // Opcode: CINS32
+/* 432 */ MCD::OPC_FilterValue, 58, 9, 0, 0, // Skip to: 446
+/* 437 */ MCD::OPC_CheckPredicate, 4, 74, 0, 0, // Skip to: 516
+/* 442 */ MCD::OPC_Decode, 185, 10, 17, // Opcode: EXTS
+/* 446 */ MCD::OPC_FilterValue, 59, 65, 0, 0, // Skip to: 516
+/* 451 */ MCD::OPC_CheckPredicate, 4, 60, 0, 0, // Skip to: 516
+/* 456 */ MCD::OPC_Decode, 186, 10, 17, // Opcode: EXTS32
+/* 460 */ MCD::OPC_FilterValue, 50, 9, 0, 0, // Skip to: 474
+/* 465 */ MCD::OPC_CheckPredicate, 3, 46, 0, 0, // Skip to: 516
+/* 470 */ MCD::OPC_Decode, 143, 5, 18, // Opcode: BBIT0
+/* 474 */ MCD::OPC_FilterValue, 54, 9, 0, 0, // Skip to: 488
+/* 479 */ MCD::OPC_CheckPredicate, 3, 32, 0, 0, // Skip to: 516
+/* 484 */ MCD::OPC_Decode, 144, 5, 18, // Opcode: BBIT032
+/* 488 */ MCD::OPC_FilterValue, 58, 9, 0, 0, // Skip to: 502
+/* 493 */ MCD::OPC_CheckPredicate, 3, 18, 0, 0, // Skip to: 516
+/* 498 */ MCD::OPC_Decode, 145, 5, 18, // Opcode: BBIT1
+/* 502 */ MCD::OPC_FilterValue, 62, 9, 0, 0, // Skip to: 516
+/* 507 */ MCD::OPC_CheckPredicate, 3, 4, 0, 0, // Skip to: 516
+/* 512 */ MCD::OPC_Decode, 146, 5, 18, // Opcode: BBIT132
+/* 516 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMips16[] = {
+/* 0 */ MCD::OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 3 */ MCD::OPC_FilterValue, 1, 31, 0, 0, // Skip to: 39
+/* 8 */ MCD::OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25
+/* 16 */ MCD::OPC_CheckPredicate, 5, 114, 2, 0, // Skip to: 647
+/* 21 */ MCD::OPC_Decode, 170, 4, 19, // Opcode: ADDU16_MM
+/* 25 */ MCD::OPC_FilterValue, 1, 105, 2, 0, // Skip to: 647
+/* 30 */ MCD::OPC_CheckPredicate, 5, 100, 2, 0, // Skip to: 647
+/* 35 */ MCD::OPC_Decode, 140, 19, 19, // Opcode: SUBU16_MM
+/* 39 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 53
+/* 44 */ MCD::OPC_CheckPredicate, 6, 86, 2, 0, // Skip to: 647
+/* 49 */ MCD::OPC_Decode, 203, 12, 20, // Opcode: LBU16_MM
+/* 53 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 67
+/* 58 */ MCD::OPC_CheckPredicate, 5, 72, 2, 0, // Skip to: 647
+/* 63 */ MCD::OPC_Decode, 204, 14, 21, // Opcode: MOVE16_MM
+/* 67 */ MCD::OPC_FilterValue, 9, 31, 0, 0, // Skip to: 103
+/* 72 */ MCD::OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 75 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 89
+/* 80 */ MCD::OPC_CheckPredicate, 5, 50, 2, 0, // Skip to: 647
+/* 85 */ MCD::OPC_Decode, 150, 18, 22, // Opcode: SLL16_MM
+/* 89 */ MCD::OPC_FilterValue, 1, 41, 2, 0, // Skip to: 647
+/* 94 */ MCD::OPC_CheckPredicate, 5, 36, 2, 0, // Skip to: 647
+/* 99 */ MCD::OPC_Decode, 209, 18, 22, // Opcode: SRL16_MM
+/* 103 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 117
+/* 108 */ MCD::OPC_CheckPredicate, 6, 22, 2, 0, // Skip to: 647
+/* 113 */ MCD::OPC_Decode, 243, 12, 20, // Opcode: LHU16_MM
+/* 117 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 131
+/* 122 */ MCD::OPC_CheckPredicate, 5, 8, 2, 0, // Skip to: 647
+/* 127 */ MCD::OPC_Decode, 215, 4, 23, // Opcode: ANDI16_MM
+/* 131 */ MCD::OPC_FilterValue, 17, 8, 1, 0, // Skip to: 400
+/* 136 */ MCD::OPC_ExtractField, 6, 4, // Inst{9-6} ...
+/* 139 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 153
+/* 144 */ MCD::OPC_CheckPredicate, 5, 242, 1, 0, // Skip to: 647
+/* 149 */ MCD::OPC_Decode, 133, 16, 24, // Opcode: NOT16_MM
+/* 153 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 167
+/* 158 */ MCD::OPC_CheckPredicate, 5, 228, 1, 0, // Skip to: 647
+/* 163 */ MCD::OPC_Decode, 183, 20, 25, // Opcode: XOR16_MM
+/* 167 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 181
+/* 172 */ MCD::OPC_CheckPredicate, 5, 214, 1, 0, // Skip to: 647
+/* 177 */ MCD::OPC_Decode, 212, 4, 25, // Opcode: AND16_MM
+/* 181 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 195
+/* 186 */ MCD::OPC_CheckPredicate, 5, 200, 1, 0, // Skip to: 647
+/* 191 */ MCD::OPC_Decode, 138, 16, 25, // Opcode: OR16_MM
+/* 195 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 209
+/* 200 */ MCD::OPC_CheckPredicate, 5, 186, 1, 0, // Skip to: 647
+/* 205 */ MCD::OPC_Decode, 165, 13, 26, // Opcode: LWM16_MM
+/* 209 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 223
+/* 214 */ MCD::OPC_CheckPredicate, 5, 172, 1, 0, // Skip to: 647
+/* 219 */ MCD::OPC_Decode, 189, 19, 26, // Opcode: SWM16_MM
+/* 223 */ MCD::OPC_FilterValue, 6, 31, 0, 0, // Skip to: 259
+/* 228 */ MCD::OPC_ExtractField, 5, 1, // Inst{5} ...
+/* 231 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 245
+/* 236 */ MCD::OPC_CheckPredicate, 5, 150, 1, 0, // Skip to: 647
+/* 241 */ MCD::OPC_Decode, 181, 12, 27, // Opcode: JR16_MM
+/* 245 */ MCD::OPC_FilterValue, 1, 141, 1, 0, // Skip to: 647
+/* 250 */ MCD::OPC_CheckPredicate, 5, 136, 1, 0, // Skip to: 647
+/* 255 */ MCD::OPC_Decode, 184, 12, 27, // Opcode: JRC16_MM
+/* 259 */ MCD::OPC_FilterValue, 7, 31, 0, 0, // Skip to: 295
+/* 264 */ MCD::OPC_ExtractField, 5, 1, // Inst{5} ...
+/* 267 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281
+/* 272 */ MCD::OPC_CheckPredicate, 5, 114, 1, 0, // Skip to: 647
+/* 277 */ MCD::OPC_Decode, 160, 12, 27, // Opcode: JALR16_MM
+/* 281 */ MCD::OPC_FilterValue, 1, 105, 1, 0, // Skip to: 647
+/* 286 */ MCD::OPC_CheckPredicate, 5, 100, 1, 0, // Skip to: 647
+/* 291 */ MCD::OPC_Decode, 165, 12, 27, // Opcode: JALRS16_MM
+/* 295 */ MCD::OPC_FilterValue, 8, 16, 0, 0, // Skip to: 316
+/* 300 */ MCD::OPC_CheckPredicate, 5, 86, 1, 0, // Skip to: 647
+/* 305 */ MCD::OPC_CheckField, 5, 1, 0, 79, 1, 0, // Skip to: 647
+/* 312 */ MCD::OPC_Decode, 150, 14, 27, // Opcode: MFHI16_MM
+/* 316 */ MCD::OPC_FilterValue, 9, 16, 0, 0, // Skip to: 337
+/* 321 */ MCD::OPC_CheckPredicate, 5, 65, 1, 0, // Skip to: 647
+/* 326 */ MCD::OPC_CheckField, 5, 1, 0, 58, 1, 0, // Skip to: 647
+/* 333 */ MCD::OPC_Decode, 156, 14, 27, // Opcode: MFLO16_MM
+/* 337 */ MCD::OPC_FilterValue, 10, 16, 0, 0, // Skip to: 358
+/* 342 */ MCD::OPC_CheckPredicate, 5, 44, 1, 0, // Skip to: 647
+/* 347 */ MCD::OPC_CheckField, 4, 2, 0, 37, 1, 0, // Skip to: 647
+/* 354 */ MCD::OPC_Decode, 175, 6, 28, // Opcode: BREAK16_MM
+/* 358 */ MCD::OPC_FilterValue, 11, 16, 0, 0, // Skip to: 379
+/* 363 */ MCD::OPC_CheckPredicate, 5, 23, 1, 0, // Skip to: 647
+/* 368 */ MCD::OPC_CheckField, 4, 2, 0, 16, 1, 0, // Skip to: 647
+/* 375 */ MCD::OPC_Decode, 165, 17, 28, // Opcode: SDBBP16_MM
+/* 379 */ MCD::OPC_FilterValue, 12, 7, 1, 0, // Skip to: 647
+/* 384 */ MCD::OPC_CheckPredicate, 5, 2, 1, 0, // Skip to: 647
+/* 389 */ MCD::OPC_CheckField, 5, 1, 0, 251, 0, 0, // Skip to: 647
+/* 396 */ MCD::OPC_Decode, 183, 12, 29, // Opcode: JRADDIUSP
+/* 400 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 414
+/* 405 */ MCD::OPC_CheckPredicate, 6, 237, 0, 0, // Skip to: 647
+/* 410 */ MCD::OPC_Decode, 176, 13, 30, // Opcode: LWSP_MM
+/* 414 */ MCD::OPC_FilterValue, 19, 31, 0, 0, // Skip to: 450
+/* 419 */ MCD::OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 422 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 436
+/* 427 */ MCD::OPC_CheckPredicate, 6, 215, 0, 0, // Skip to: 647
+/* 432 */ MCD::OPC_Decode, 139, 4, 31, // Opcode: ADDIUS5_MM
+/* 436 */ MCD::OPC_FilterValue, 1, 206, 0, 0, // Skip to: 647
+/* 441 */ MCD::OPC_CheckPredicate, 6, 201, 0, 0, // Skip to: 647
+/* 446 */ MCD::OPC_Decode, 140, 4, 32, // Opcode: ADDIUSP_MM
+/* 450 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 464
+/* 455 */ MCD::OPC_CheckPredicate, 6, 187, 0, 0, // Skip to: 647
+/* 460 */ MCD::OPC_Decode, 159, 13, 33, // Opcode: LWGP_MM
+/* 464 */ MCD::OPC_FilterValue, 26, 9, 0, 0, // Skip to: 478
+/* 469 */ MCD::OPC_CheckPredicate, 6, 173, 0, 0, // Skip to: 647
+/* 474 */ MCD::OPC_Decode, 147, 13, 20, // Opcode: LW16_MM
+/* 478 */ MCD::OPC_FilterValue, 27, 31, 0, 0, // Skip to: 514
+/* 483 */ MCD::OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 486 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 500
+/* 491 */ MCD::OPC_CheckPredicate, 6, 151, 0, 0, // Skip to: 647
+/* 496 */ MCD::OPC_Decode, 138, 4, 34, // Opcode: ADDIUR2_MM
+/* 500 */ MCD::OPC_FilterValue, 1, 142, 0, 0, // Skip to: 647
+/* 505 */ MCD::OPC_CheckPredicate, 6, 137, 0, 0, // Skip to: 647
+/* 510 */ MCD::OPC_Decode, 137, 4, 35, // Opcode: ADDIUR1SP_MM
+/* 514 */ MCD::OPC_FilterValue, 33, 16, 0, 0, // Skip to: 535
+/* 519 */ MCD::OPC_CheckPredicate, 5, 123, 0, 0, // Skip to: 647
+/* 524 */ MCD::OPC_CheckField, 0, 1, 0, 116, 0, 0, // Skip to: 647
+/* 531 */ MCD::OPC_Decode, 206, 14, 36, // Opcode: MOVEP_MM
+/* 535 */ MCD::OPC_FilterValue, 34, 9, 0, 0, // Skip to: 549
+/* 540 */ MCD::OPC_CheckPredicate, 5, 102, 0, 0, // Skip to: 647
+/* 545 */ MCD::OPC_Decode, 146, 17, 20, // Opcode: SB16_MM
+/* 549 */ MCD::OPC_FilterValue, 35, 9, 0, 0, // Skip to: 563
+/* 554 */ MCD::OPC_CheckPredicate, 5, 88, 0, 0, // Skip to: 647
+/* 559 */ MCD::OPC_Decode, 178, 5, 37, // Opcode: BEQZ16_MM
+/* 563 */ MCD::OPC_FilterValue, 42, 9, 0, 0, // Skip to: 577
+/* 568 */ MCD::OPC_CheckPredicate, 5, 74, 0, 0, // Skip to: 647
+/* 573 */ MCD::OPC_Decode, 211, 17, 20, // Opcode: SH16_MM
+/* 577 */ MCD::OPC_FilterValue, 43, 9, 0, 0, // Skip to: 591
+/* 582 */ MCD::OPC_CheckPredicate, 5, 60, 0, 0, // Skip to: 647
+/* 587 */ MCD::OPC_Decode, 153, 6, 37, // Opcode: BNEZ16_MM
+/* 591 */ MCD::OPC_FilterValue, 50, 9, 0, 0, // Skip to: 605
+/* 596 */ MCD::OPC_CheckPredicate, 5, 46, 0, 0, // Skip to: 647
+/* 601 */ MCD::OPC_Decode, 198, 19, 30, // Opcode: SWSP_MM
+/* 605 */ MCD::OPC_FilterValue, 51, 9, 0, 0, // Skip to: 619
+/* 610 */ MCD::OPC_CheckPredicate, 6, 32, 0, 0, // Skip to: 647
+/* 615 */ MCD::OPC_Decode, 136, 5, 38, // Opcode: B16_MM
+/* 619 */ MCD::OPC_FilterValue, 58, 9, 0, 0, // Skip to: 633
+/* 624 */ MCD::OPC_CheckPredicate, 5, 18, 0, 0, // Skip to: 647
+/* 629 */ MCD::OPC_Decode, 171, 19, 20, // Opcode: SW16_MM
+/* 633 */ MCD::OPC_FilterValue, 59, 9, 0, 0, // Skip to: 647
+/* 638 */ MCD::OPC_CheckPredicate, 5, 4, 0, 0, // Skip to: 647
+/* 643 */ MCD::OPC_Decode, 252, 12, 39, // Opcode: LI16_MM
+/* 647 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMips32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 238, 14, 0, // Skip to: 3830
+/* 8 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 104, 0, 0, // Skip to: 120
+/* 16 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 19 */ MCD::OPC_FilterValue, 0, 54, 0, 0, // Skip to: 78
+/* 24 */ MCD::OPC_ExtractField, 11, 15, // Inst{25-11} ...
+/* 27 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41
+/* 32 */ MCD::OPC_CheckPredicate, 6, 32, 0, 0, // Skip to: 69
+/* 37 */ MCD::OPC_Decode, 231, 18, 0, // Opcode: SSNOP_MM
+/* 41 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55
+/* 46 */ MCD::OPC_CheckPredicate, 6, 18, 0, 0, // Skip to: 69
+/* 51 */ MCD::OPC_Decode, 146, 10, 0, // Opcode: EHB_MM
+/* 55 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69
+/* 60 */ MCD::OPC_CheckPredicate, 6, 4, 0, 0, // Skip to: 69
+/* 65 */ MCD::OPC_Decode, 153, 16, 0, // Opcode: PAUSE_MM
+/* 69 */ MCD::OPC_CheckPredicate, 6, 37, 25, 0, // Skip to: 6511
+/* 74 */ MCD::OPC_Decode, 163, 18, 40, // Opcode: SLL_MM
+/* 78 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 92
+/* 83 */ MCD::OPC_CheckPredicate, 6, 23, 25, 0, // Skip to: 6511
+/* 88 */ MCD::OPC_Decode, 228, 18, 40, // Opcode: SRL_MM
+/* 92 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 106
+/* 97 */ MCD::OPC_CheckPredicate, 6, 9, 25, 0, // Skip to: 6511
+/* 102 */ MCD::OPC_Decode, 206, 18, 40, // Opcode: SRA_MM
+/* 106 */ MCD::OPC_FilterValue, 3, 0, 25, 0, // Skip to: 6511
+/* 111 */ MCD::OPC_CheckPredicate, 6, 251, 24, 0, // Skip to: 6511
+/* 116 */ MCD::OPC_Decode, 245, 16, 40, // Opcode: ROTR_MM
+/* 120 */ MCD::OPC_FilterValue, 5, 227, 0, 0, // Skip to: 352
+/* 125 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 128 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 149
+/* 133 */ MCD::OPC_CheckPredicate, 7, 229, 24, 0, // Skip to: 6511
+/* 138 */ MCD::OPC_CheckField, 11, 5, 0, 222, 24, 0, // Skip to: 6511
+/* 145 */ MCD::OPC_Decode, 177, 7, 41, // Opcode: CMP_EQ_PH_MM
+/* 149 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 170
+/* 154 */ MCD::OPC_CheckPredicate, 7, 208, 24, 0, // Skip to: 6511
+/* 159 */ MCD::OPC_CheckField, 11, 5, 0, 201, 24, 0, // Skip to: 6511
+/* 166 */ MCD::OPC_Decode, 191, 7, 41, // Opcode: CMP_LT_PH_MM
+/* 170 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 191
+/* 175 */ MCD::OPC_CheckPredicate, 7, 187, 24, 0, // Skip to: 6511
+/* 180 */ MCD::OPC_CheckField, 11, 5, 0, 180, 24, 0, // Skip to: 6511
+/* 187 */ MCD::OPC_Decode, 185, 7, 41, // Opcode: CMP_LE_PH_MM
+/* 191 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 205
+/* 196 */ MCD::OPC_CheckPredicate, 8, 166, 24, 0, // Skip to: 6511
+/* 201 */ MCD::OPC_Decode, 155, 7, 42, // Opcode: CMPGDU_EQ_QB_MMR2
+/* 205 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 219
+/* 210 */ MCD::OPC_CheckPredicate, 8, 152, 24, 0, // Skip to: 6511
+/* 215 */ MCD::OPC_Decode, 159, 7, 42, // Opcode: CMPGDU_LT_QB_MMR2
+/* 219 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 233
+/* 224 */ MCD::OPC_CheckPredicate, 8, 138, 24, 0, // Skip to: 6511
+/* 229 */ MCD::OPC_Decode, 157, 7, 42, // Opcode: CMPGDU_LE_QB_MMR2
+/* 233 */ MCD::OPC_FilterValue, 9, 16, 0, 0, // Skip to: 254
+/* 238 */ MCD::OPC_CheckPredicate, 7, 124, 24, 0, // Skip to: 6511
+/* 243 */ MCD::OPC_CheckField, 11, 5, 0, 117, 24, 0, // Skip to: 6511
+/* 250 */ MCD::OPC_Decode, 167, 7, 41, // Opcode: CMPU_EQ_QB_MM
+/* 254 */ MCD::OPC_FilterValue, 10, 16, 0, 0, // Skip to: 275
+/* 259 */ MCD::OPC_CheckPredicate, 7, 103, 24, 0, // Skip to: 6511
+/* 264 */ MCD::OPC_CheckField, 11, 5, 0, 96, 24, 0, // Skip to: 6511
+/* 271 */ MCD::OPC_Decode, 171, 7, 41, // Opcode: CMPU_LT_QB_MM
+/* 275 */ MCD::OPC_FilterValue, 11, 16, 0, 0, // Skip to: 296
+/* 280 */ MCD::OPC_CheckPredicate, 7, 82, 24, 0, // Skip to: 6511
+/* 285 */ MCD::OPC_CheckField, 11, 5, 0, 75, 24, 0, // Skip to: 6511
+/* 292 */ MCD::OPC_Decode, 169, 7, 41, // Opcode: CMPU_LE_QB_MM
+/* 296 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 310
+/* 301 */ MCD::OPC_CheckPredicate, 7, 61, 24, 0, // Skip to: 6511
+/* 306 */ MCD::OPC_Decode, 155, 4, 43, // Opcode: ADDQ_S_W_MM
+/* 310 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 324
+/* 315 */ MCD::OPC_CheckPredicate, 7, 47, 24, 0, // Skip to: 6511
+/* 320 */ MCD::OPC_Decode, 251, 18, 43, // Opcode: SUBQ_S_W_MM
+/* 324 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 338
+/* 329 */ MCD::OPC_CheckPredicate, 7, 33, 24, 0, // Skip to: 6511
+/* 334 */ MCD::OPC_Decode, 157, 4, 43, // Opcode: ADDSC_MM
+/* 338 */ MCD::OPC_FilterValue, 15, 24, 24, 0, // Skip to: 6511
+/* 343 */ MCD::OPC_CheckPredicate, 7, 19, 24, 0, // Skip to: 6511
+/* 348 */ MCD::OPC_Decode, 194, 4, 43, // Opcode: ADDWC_MM
+/* 352 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 366
+/* 357 */ MCD::OPC_CheckPredicate, 6, 5, 24, 0, // Skip to: 6511
+/* 362 */ MCD::OPC_Decode, 177, 6, 44, // Opcode: BREAK_MM
+/* 366 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 380
+/* 371 */ MCD::OPC_CheckPredicate, 5, 247, 23, 0, // Skip to: 6511
+/* 376 */ MCD::OPC_Decode, 155, 12, 45, // Opcode: INS_MM
+/* 380 */ MCD::OPC_FilterValue, 13, 167, 1, 0, // Skip to: 808
+/* 385 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 388 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 402
+/* 393 */ MCD::OPC_CheckPredicate, 7, 225, 23, 0, // Skip to: 6511
+/* 398 */ MCD::OPC_Decode, 151, 4, 46, // Opcode: ADDQ_PH_MM
+/* 402 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 416
+/* 407 */ MCD::OPC_CheckPredicate, 8, 211, 23, 0, // Skip to: 6511
+/* 412 */ MCD::OPC_Decode, 143, 4, 46, // Opcode: ADDQH_PH_MMR2
+/* 416 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 430
+/* 421 */ MCD::OPC_CheckPredicate, 8, 197, 23, 0, // Skip to: 6511
+/* 426 */ MCD::OPC_Decode, 149, 4, 43, // Opcode: ADDQH_W_MMR2
+/* 430 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 444
+/* 435 */ MCD::OPC_CheckPredicate, 7, 183, 23, 0, // Skip to: 6511
+/* 440 */ MCD::OPC_Decode, 180, 4, 46, // Opcode: ADDU_QB_MM
+/* 444 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 458
+/* 449 */ MCD::OPC_CheckPredicate, 8, 169, 23, 0, // Skip to: 6511
+/* 454 */ MCD::OPC_Decode, 178, 4, 46, // Opcode: ADDU_PH_MMR2
+/* 458 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 472
+/* 463 */ MCD::OPC_CheckPredicate, 8, 155, 23, 0, // Skip to: 6511
+/* 468 */ MCD::OPC_Decode, 173, 4, 46, // Opcode: ADDUH_QB_MMR2
+/* 472 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 486
+/* 477 */ MCD::OPC_CheckPredicate, 7, 141, 23, 0, // Skip to: 6511
+/* 482 */ MCD::OPC_Decode, 240, 17, 47, // Opcode: SHRAV_PH_MM
+/* 486 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 500
+/* 491 */ MCD::OPC_CheckPredicate, 8, 127, 23, 0, // Skip to: 6511
+/* 496 */ MCD::OPC_Decode, 242, 17, 47, // Opcode: SHRAV_QB_MMR2
+/* 500 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 514
+/* 505 */ MCD::OPC_CheckPredicate, 7, 113, 23, 0, // Skip to: 6511
+/* 510 */ MCD::OPC_Decode, 247, 18, 46, // Opcode: SUBQ_PH_MM
+/* 514 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 528
+/* 519 */ MCD::OPC_CheckPredicate, 8, 99, 23, 0, // Skip to: 6511
+/* 524 */ MCD::OPC_Decode, 239, 18, 46, // Opcode: SUBQH_PH_MMR2
+/* 528 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 542
+/* 533 */ MCD::OPC_CheckPredicate, 8, 85, 23, 0, // Skip to: 6511
+/* 538 */ MCD::OPC_Decode, 245, 18, 43, // Opcode: SUBQH_W_MMR2
+/* 542 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 556
+/* 547 */ MCD::OPC_CheckPredicate, 7, 71, 23, 0, // Skip to: 6511
+/* 552 */ MCD::OPC_Decode, 150, 19, 46, // Opcode: SUBU_QB_MM
+/* 556 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 570
+/* 561 */ MCD::OPC_CheckPredicate, 8, 57, 23, 0, // Skip to: 6511
+/* 566 */ MCD::OPC_Decode, 148, 19, 46, // Opcode: SUBU_PH_MMR2
+/* 570 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 584
+/* 575 */ MCD::OPC_CheckPredicate, 8, 43, 23, 0, // Skip to: 6511
+/* 580 */ MCD::OPC_Decode, 143, 19, 46, // Opcode: SUBUH_QB_MMR2
+/* 584 */ MCD::OPC_FilterValue, 15, 9, 0, 0, // Skip to: 598
+/* 589 */ MCD::OPC_CheckPredicate, 8, 29, 23, 0, // Skip to: 6511
+/* 594 */ MCD::OPC_Decode, 203, 16, 48, // Opcode: PRECR_SRA_PH_W_MMR2
+/* 598 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 612
+/* 603 */ MCD::OPC_CheckPredicate, 7, 15, 23, 0, // Skip to: 6511
+/* 608 */ MCD::OPC_Decode, 153, 4, 46, // Opcode: ADDQ_S_PH_MM
+/* 612 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 626
+/* 617 */ MCD::OPC_CheckPredicate, 8, 1, 23, 0, // Skip to: 6511
+/* 622 */ MCD::OPC_Decode, 145, 4, 46, // Opcode: ADDQH_R_PH_MMR2
+/* 626 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 640
+/* 631 */ MCD::OPC_CheckPredicate, 8, 243, 22, 0, // Skip to: 6511
+/* 636 */ MCD::OPC_Decode, 147, 4, 43, // Opcode: ADDQH_R_W_MMR2
+/* 640 */ MCD::OPC_FilterValue, 19, 9, 0, 0, // Skip to: 654
+/* 645 */ MCD::OPC_CheckPredicate, 7, 229, 22, 0, // Skip to: 6511
+/* 650 */ MCD::OPC_Decode, 184, 4, 46, // Opcode: ADDU_S_QB_MM
+/* 654 */ MCD::OPC_FilterValue, 20, 9, 0, 0, // Skip to: 668
+/* 659 */ MCD::OPC_CheckPredicate, 8, 215, 22, 0, // Skip to: 6511
+/* 664 */ MCD::OPC_Decode, 182, 4, 46, // Opcode: ADDU_S_PH_MMR2
+/* 668 */ MCD::OPC_FilterValue, 21, 9, 0, 0, // Skip to: 682
+/* 673 */ MCD::OPC_CheckPredicate, 8, 201, 22, 0, // Skip to: 6511
+/* 678 */ MCD::OPC_Decode, 175, 4, 46, // Opcode: ADDUH_R_QB_MMR2
+/* 682 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 696
+/* 687 */ MCD::OPC_CheckPredicate, 7, 187, 22, 0, // Skip to: 6511
+/* 692 */ MCD::OPC_Decode, 244, 17, 47, // Opcode: SHRAV_R_PH_MM
+/* 696 */ MCD::OPC_FilterValue, 23, 9, 0, 0, // Skip to: 710
+/* 701 */ MCD::OPC_CheckPredicate, 8, 173, 22, 0, // Skip to: 6511
+/* 706 */ MCD::OPC_Decode, 246, 17, 47, // Opcode: SHRAV_R_QB_MMR2
+/* 710 */ MCD::OPC_FilterValue, 24, 9, 0, 0, // Skip to: 724
+/* 715 */ MCD::OPC_CheckPredicate, 7, 159, 22, 0, // Skip to: 6511
+/* 720 */ MCD::OPC_Decode, 249, 18, 46, // Opcode: SUBQ_S_PH_MM
+/* 724 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 738
+/* 729 */ MCD::OPC_CheckPredicate, 8, 145, 22, 0, // Skip to: 6511
+/* 734 */ MCD::OPC_Decode, 241, 18, 46, // Opcode: SUBQH_R_PH_MMR2
+/* 738 */ MCD::OPC_FilterValue, 26, 9, 0, 0, // Skip to: 752
+/* 743 */ MCD::OPC_CheckPredicate, 8, 131, 22, 0, // Skip to: 6511
+/* 748 */ MCD::OPC_Decode, 243, 18, 43, // Opcode: SUBQH_R_W_MMR2
+/* 752 */ MCD::OPC_FilterValue, 27, 9, 0, 0, // Skip to: 766
+/* 757 */ MCD::OPC_CheckPredicate, 7, 117, 22, 0, // Skip to: 6511
+/* 762 */ MCD::OPC_Decode, 154, 19, 46, // Opcode: SUBU_S_QB_MM
+/* 766 */ MCD::OPC_FilterValue, 28, 9, 0, 0, // Skip to: 780
+/* 771 */ MCD::OPC_CheckPredicate, 8, 103, 22, 0, // Skip to: 6511
+/* 776 */ MCD::OPC_Decode, 152, 19, 46, // Opcode: SUBU_S_PH_MMR2
+/* 780 */ MCD::OPC_FilterValue, 29, 9, 0, 0, // Skip to: 794
+/* 785 */ MCD::OPC_CheckPredicate, 8, 89, 22, 0, // Skip to: 6511
+/* 790 */ MCD::OPC_Decode, 145, 19, 46, // Opcode: SUBUH_R_QB_MMR2
+/* 794 */ MCD::OPC_FilterValue, 31, 80, 22, 0, // Skip to: 6511
+/* 799 */ MCD::OPC_CheckPredicate, 8, 75, 22, 0, // Skip to: 6511
+/* 804 */ MCD::OPC_Decode, 205, 16, 48, // Opcode: PRECR_SRA_R_PH_W_MMR2
+/* 808 */ MCD::OPC_FilterValue, 14, 31, 0, 0, // Skip to: 844
+/* 813 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 816 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 830
+/* 821 */ MCD::OPC_CheckPredicate, 7, 53, 22, 0, // Skip to: 6511
+/* 826 */ MCD::OPC_Decode, 224, 17, 47, // Opcode: SHLLV_PH_MM
+/* 830 */ MCD::OPC_FilterValue, 16, 44, 22, 0, // Skip to: 6511
+/* 835 */ MCD::OPC_CheckPredicate, 7, 39, 22, 0, // Skip to: 6511
+/* 840 */ MCD::OPC_Decode, 228, 17, 47, // Opcode: SHLLV_S_PH_MM
+/* 844 */ MCD::OPC_FilterValue, 16, 213, 0, 0, // Skip to: 1062
+/* 849 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 852 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 866
+/* 857 */ MCD::OPC_CheckPredicate, 6, 17, 22, 0, // Skip to: 6511
+/* 862 */ MCD::OPC_Decode, 159, 18, 49, // Opcode: SLLV_MM
+/* 866 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 880
+/* 871 */ MCD::OPC_CheckPredicate, 6, 3, 22, 0, // Skip to: 6511
+/* 876 */ MCD::OPC_Decode, 224, 18, 49, // Opcode: SRLV_MM
+/* 880 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 894
+/* 885 */ MCD::OPC_CheckPredicate, 6, 245, 21, 0, // Skip to: 6511
+/* 890 */ MCD::OPC_Decode, 202, 18, 49, // Opcode: SRAV_MM
+/* 894 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 908
+/* 899 */ MCD::OPC_CheckPredicate, 6, 231, 21, 0, // Skip to: 6511
+/* 904 */ MCD::OPC_Decode, 244, 16, 49, // Opcode: ROTRV_MM
+/* 908 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 922
+/* 913 */ MCD::OPC_CheckPredicate, 5, 217, 21, 0, // Skip to: 6511
+/* 918 */ MCD::OPC_Decode, 199, 4, 43, // Opcode: ADD_MM
+/* 922 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 936
+/* 927 */ MCD::OPC_CheckPredicate, 5, 203, 21, 0, // Skip to: 6511
+/* 932 */ MCD::OPC_Decode, 206, 4, 43, // Opcode: ADDu_MM
+/* 936 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 950
+/* 941 */ MCD::OPC_CheckPredicate, 5, 189, 21, 0, // Skip to: 6511
+/* 946 */ MCD::OPC_Decode, 163, 19, 43, // Opcode: SUB_MM
+/* 950 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 964
+/* 955 */ MCD::OPC_CheckPredicate, 5, 175, 21, 0, // Skip to: 6511
+/* 960 */ MCD::OPC_Decode, 166, 19, 43, // Opcode: SUBu_MM
+/* 964 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 978
+/* 969 */ MCD::OPC_CheckPredicate, 5, 161, 21, 0, // Skip to: 6511
+/* 974 */ MCD::OPC_Decode, 224, 15, 43, // Opcode: MUL_MM
+/* 978 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 992
+/* 983 */ MCD::OPC_CheckPredicate, 5, 147, 21, 0, // Skip to: 6511
+/* 988 */ MCD::OPC_Decode, 219, 4, 43, // Opcode: AND_MM
+/* 992 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1006
+/* 997 */ MCD::OPC_CheckPredicate, 5, 133, 21, 0, // Skip to: 6511
+/* 1002 */ MCD::OPC_Decode, 143, 16, 43, // Opcode: OR_MM
+/* 1006 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1020
+/* 1011 */ MCD::OPC_CheckPredicate, 5, 119, 21, 0, // Skip to: 6511
+/* 1016 */ MCD::OPC_Decode, 130, 16, 43, // Opcode: NOR_MM
+/* 1020 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1034
+/* 1025 */ MCD::OPC_CheckPredicate, 5, 105, 21, 0, // Skip to: 6511
+/* 1030 */ MCD::OPC_Decode, 188, 20, 43, // Opcode: XOR_MM
+/* 1034 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1048
+/* 1039 */ MCD::OPC_CheckPredicate, 6, 91, 21, 0, // Skip to: 6511
+/* 1044 */ MCD::OPC_Decode, 168, 18, 43, // Opcode: SLT_MM
+/* 1048 */ MCD::OPC_FilterValue, 14, 82, 21, 0, // Skip to: 6511
+/* 1053 */ MCD::OPC_CheckPredicate, 6, 77, 21, 0, // Skip to: 6511
+/* 1058 */ MCD::OPC_Decode, 177, 18, 43, // Opcode: SLTu_MM
+/* 1062 */ MCD::OPC_FilterValue, 21, 199, 0, 0, // Skip to: 1266
+/* 1067 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 1070 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1084
+/* 1075 */ MCD::OPC_CheckPredicate, 7, 55, 21, 0, // Skip to: 6511
+/* 1080 */ MCD::OPC_Decode, 193, 15, 46, // Opcode: MULEU_S_PH_QBL_MM
+/* 1084 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1098
+/* 1089 */ MCD::OPC_CheckPredicate, 7, 41, 21, 0, // Skip to: 6511
+/* 1094 */ MCD::OPC_Decode, 195, 15, 46, // Opcode: MULEU_S_PH_QBR_MM
+/* 1098 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1112
+/* 1103 */ MCD::OPC_CheckPredicate, 7, 27, 21, 0, // Skip to: 6511
+/* 1108 */ MCD::OPC_Decode, 197, 15, 46, // Opcode: MULQ_RS_PH_MM
+/* 1112 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1126
+/* 1117 */ MCD::OPC_CheckPredicate, 8, 13, 21, 0, // Skip to: 6511
+/* 1122 */ MCD::OPC_Decode, 201, 15, 46, // Opcode: MULQ_S_PH_MMR2
+/* 1126 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1140
+/* 1131 */ MCD::OPC_CheckPredicate, 8, 255, 20, 0, // Skip to: 6511
+/* 1136 */ MCD::OPC_Decode, 199, 15, 43, // Opcode: MULQ_RS_W_MMR2
+/* 1140 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 1154
+/* 1145 */ MCD::OPC_CheckPredicate, 8, 241, 20, 0, // Skip to: 6511
+/* 1150 */ MCD::OPC_Decode, 203, 15, 43, // Opcode: MULQ_S_W_MMR2
+/* 1154 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 1168
+/* 1159 */ MCD::OPC_CheckPredicate, 8, 227, 20, 0, // Skip to: 6511
+/* 1164 */ MCD::OPC_Decode, 226, 4, 50, // Opcode: APPEND_MMR2
+/* 1168 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 1182
+/* 1173 */ MCD::OPC_CheckPredicate, 8, 213, 20, 0, // Skip to: 6511
+/* 1178 */ MCD::OPC_Decode, 214, 16, 50, // Opcode: PREPEND_MMR2
+/* 1182 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 1196
+/* 1187 */ MCD::OPC_CheckPredicate, 7, 199, 20, 0, // Skip to: 6511
+/* 1192 */ MCD::OPC_Decode, 192, 14, 43, // Opcode: MODSUB_MM
+/* 1196 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1210
+/* 1201 */ MCD::OPC_CheckPredicate, 7, 185, 20, 0, // Skip to: 6511
+/* 1206 */ MCD::OPC_Decode, 248, 17, 49, // Opcode: SHRAV_R_W_MM
+/* 1210 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1224
+/* 1215 */ MCD::OPC_CheckPredicate, 8, 171, 20, 0, // Skip to: 6511
+/* 1220 */ MCD::OPC_Decode, 132, 18, 47, // Opcode: SHRLV_PH_MMR2
+/* 1224 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 1238
+/* 1229 */ MCD::OPC_CheckPredicate, 7, 157, 20, 0, // Skip to: 6511
+/* 1234 */ MCD::OPC_Decode, 134, 18, 47, // Opcode: SHRLV_QB_MM
+/* 1238 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1252
+/* 1243 */ MCD::OPC_CheckPredicate, 7, 143, 20, 0, // Skip to: 6511
+/* 1248 */ MCD::OPC_Decode, 226, 17, 47, // Opcode: SHLLV_QB_MM
+/* 1252 */ MCD::OPC_FilterValue, 15, 134, 20, 0, // Skip to: 6511
+/* 1257 */ MCD::OPC_CheckPredicate, 7, 129, 20, 0, // Skip to: 6511
+/* 1262 */ MCD::OPC_Decode, 230, 17, 49, // Opcode: SHLLV_S_W_MM
+/* 1266 */ MCD::OPC_FilterValue, 24, 45, 0, 0, // Skip to: 1316
+/* 1271 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 1274 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1288
+/* 1279 */ MCD::OPC_CheckPredicate, 5, 107, 20, 0, // Skip to: 6511
+/* 1284 */ MCD::OPC_Decode, 226, 14, 51, // Opcode: MOVN_I_MM
+/* 1288 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1302
+/* 1293 */ MCD::OPC_CheckPredicate, 5, 93, 20, 0, // Skip to: 6511
+/* 1298 */ MCD::OPC_Decode, 246, 14, 51, // Opcode: MOVZ_I_MM
+/* 1302 */ MCD::OPC_FilterValue, 4, 84, 20, 0, // Skip to: 6511
+/* 1307 */ MCD::OPC_CheckPredicate, 6, 79, 20, 0, // Skip to: 6511
+/* 1312 */ MCD::OPC_Decode, 182, 13, 52, // Opcode: LWXS_MM
+/* 1316 */ MCD::OPC_FilterValue, 29, 23, 0, 0, // Skip to: 1344
+/* 1321 */ MCD::OPC_CheckPredicate, 7, 65, 20, 0, // Skip to: 6511
+/* 1326 */ MCD::OPC_CheckField, 22, 4, 0, 58, 20, 0, // Skip to: 6511
+/* 1333 */ MCD::OPC_CheckField, 6, 8, 0, 51, 20, 0, // Skip to: 6511
+/* 1340 */ MCD::OPC_Decode, 222, 17, 53, // Opcode: SHILO_MM
+/* 1344 */ MCD::OPC_FilterValue, 37, 73, 0, 0, // Skip to: 1422
+/* 1349 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 1352 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1366
+/* 1357 */ MCD::OPC_CheckPredicate, 7, 29, 20, 0, // Skip to: 6511
+/* 1362 */ MCD::OPC_Decode, 189, 15, 42, // Opcode: MULEQ_S_W_PHL_MM
+/* 1366 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1380
+/* 1371 */ MCD::OPC_CheckPredicate, 7, 15, 20, 0, // Skip to: 6511
+/* 1376 */ MCD::OPC_Decode, 191, 15, 42, // Opcode: MULEQ_S_W_PHR_MM
+/* 1380 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1394
+/* 1385 */ MCD::OPC_CheckPredicate, 7, 1, 20, 0, // Skip to: 6511
+/* 1390 */ MCD::OPC_Decode, 245, 12, 52, // Opcode: LHX_MM
+/* 1394 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1408
+/* 1399 */ MCD::OPC_CheckPredicate, 7, 243, 19, 0, // Skip to: 6511
+/* 1404 */ MCD::OPC_Decode, 183, 13, 52, // Opcode: LWX_MM
+/* 1408 */ MCD::OPC_FilterValue, 8, 234, 19, 0, // Skip to: 6511
+/* 1413 */ MCD::OPC_CheckPredicate, 7, 229, 19, 0, // Skip to: 6511
+/* 1418 */ MCD::OPC_Decode, 205, 12, 52, // Opcode: LBUX_MM
+/* 1422 */ MCD::OPC_FilterValue, 44, 9, 0, 0, // Skip to: 1436
+/* 1427 */ MCD::OPC_CheckPredicate, 5, 215, 19, 0, // Skip to: 6511
+/* 1432 */ MCD::OPC_Decode, 187, 10, 54, // Opcode: EXT_MM
+/* 1436 */ MCD::OPC_FilterValue, 45, 143, 0, 0, // Skip to: 1584
+/* 1441 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 1444 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1458
+/* 1449 */ MCD::OPC_CheckPredicate, 8, 193, 19, 0, // Skip to: 6511
+/* 1454 */ MCD::OPC_Decode, 227, 15, 46, // Opcode: MUL_PH_MMR2
+/* 1458 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1472
+/* 1463 */ MCD::OPC_CheckPredicate, 8, 179, 19, 0, // Skip to: 6511
+/* 1468 */ MCD::OPC_Decode, 201, 16, 46, // Opcode: PRECR_QB_PH_MMR2
+/* 1472 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1486
+/* 1477 */ MCD::OPC_CheckPredicate, 7, 165, 19, 0, // Skip to: 6511
+/* 1482 */ MCD::OPC_Decode, 197, 16, 46, // Opcode: PRECRQ_QB_PH_MM
+/* 1486 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 1500
+/* 1491 */ MCD::OPC_CheckPredicate, 7, 151, 19, 0, // Skip to: 6511
+/* 1496 */ MCD::OPC_Decode, 195, 16, 55, // Opcode: PRECRQ_PH_W_MM
+/* 1500 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1514
+/* 1505 */ MCD::OPC_CheckPredicate, 7, 137, 19, 0, // Skip to: 6511
+/* 1510 */ MCD::OPC_Decode, 199, 16, 55, // Opcode: PRECRQ_RS_PH_W_MM
+/* 1514 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1528
+/* 1519 */ MCD::OPC_CheckPredicate, 7, 123, 19, 0, // Skip to: 6511
+/* 1524 */ MCD::OPC_Decode, 193, 16, 46, // Opcode: PRECRQU_S_QB_PH_MM
+/* 1528 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1542
+/* 1533 */ MCD::OPC_CheckPredicate, 7, 109, 19, 0, // Skip to: 6511
+/* 1538 */ MCD::OPC_Decode, 151, 16, 46, // Opcode: PACKRL_PH_MM
+/* 1542 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 1556
+/* 1547 */ MCD::OPC_CheckPredicate, 7, 95, 19, 0, // Skip to: 6511
+/* 1552 */ MCD::OPC_Decode, 170, 16, 46, // Opcode: PICK_QB_MM
+/* 1556 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 1570
+/* 1561 */ MCD::OPC_CheckPredicate, 7, 81, 19, 0, // Skip to: 6511
+/* 1566 */ MCD::OPC_Decode, 168, 16, 46, // Opcode: PICK_PH_MM
+/* 1570 */ MCD::OPC_FilterValue, 16, 72, 19, 0, // Skip to: 6511
+/* 1575 */ MCD::OPC_CheckPredicate, 8, 67, 19, 0, // Skip to: 6511
+/* 1580 */ MCD::OPC_Decode, 232, 15, 46, // Opcode: MUL_S_PH_MMR2
+/* 1584 */ MCD::OPC_FilterValue, 52, 45, 0, 0, // Skip to: 1634
+/* 1589 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 1592 */ MCD::OPC_FilterValue, 19, 16, 0, 0, // Skip to: 1613
+/* 1597 */ MCD::OPC_CheckPredicate, 9, 45, 19, 0, // Skip to: 6511
+/* 1602 */ MCD::OPC_CheckField, 14, 2, 0, 38, 19, 0, // Skip to: 6511
+/* 1609 */ MCD::OPC_Decode, 148, 14, 56, // Opcode: MFHGC0_MM
+/* 1613 */ MCD::OPC_FilterValue, 27, 29, 19, 0, // Skip to: 6511
+/* 1618 */ MCD::OPC_CheckPredicate, 9, 24, 19, 0, // Skip to: 6511
+/* 1623 */ MCD::OPC_CheckField, 14, 2, 0, 17, 19, 0, // Skip to: 6511
+/* 1630 */ MCD::OPC_Decode, 163, 15, 57, // Opcode: MTHGC0_MM
+/* 1634 */ MCD::OPC_FilterValue, 53, 109, 0, 0, // Skip to: 1748
+/* 1639 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 1642 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 1656
+/* 1647 */ MCD::OPC_CheckPredicate, 7, 251, 18, 0, // Skip to: 6511
+/* 1652 */ MCD::OPC_Decode, 130, 18, 40, // Opcode: SHRA_R_W_MM
+/* 1656 */ MCD::OPC_FilterValue, 12, 16, 0, 0, // Skip to: 1677
+/* 1661 */ MCD::OPC_CheckPredicate, 7, 237, 18, 0, // Skip to: 6511
+/* 1666 */ MCD::OPC_CheckField, 11, 1, 0, 230, 18, 0, // Skip to: 6511
+/* 1673 */ MCD::OPC_Decode, 250, 17, 58, // Opcode: SHRA_PH_MM
+/* 1677 */ MCD::OPC_FilterValue, 14, 31, 0, 0, // Skip to: 1713
+/* 1682 */ MCD::OPC_ExtractField, 11, 1, // Inst{11} ...
+/* 1685 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1699
+/* 1690 */ MCD::OPC_CheckPredicate, 7, 208, 18, 0, // Skip to: 6511
+/* 1695 */ MCD::OPC_Decode, 232, 17, 58, // Opcode: SHLL_PH_MM
+/* 1699 */ MCD::OPC_FilterValue, 1, 199, 18, 0, // Skip to: 6511
+/* 1704 */ MCD::OPC_CheckPredicate, 7, 194, 18, 0, // Skip to: 6511
+/* 1709 */ MCD::OPC_Decode, 236, 17, 58, // Opcode: SHLL_S_PH_MM
+/* 1713 */ MCD::OPC_FilterValue, 15, 9, 0, 0, // Skip to: 1727
+/* 1718 */ MCD::OPC_CheckPredicate, 7, 180, 18, 0, // Skip to: 6511
+/* 1723 */ MCD::OPC_Decode, 238, 17, 40, // Opcode: SHLL_S_W_MM
+/* 1727 */ MCD::OPC_FilterValue, 28, 171, 18, 0, // Skip to: 6511
+/* 1732 */ MCD::OPC_CheckPredicate, 7, 166, 18, 0, // Skip to: 6511
+/* 1737 */ MCD::OPC_CheckField, 11, 1, 0, 159, 18, 0, // Skip to: 6511
+/* 1744 */ MCD::OPC_Decode, 254, 17, 58, // Opcode: SHRA_R_PH_MM
+/* 1748 */ MCD::OPC_FilterValue, 60, 8, 8, 0, // Skip to: 3809
+/* 1753 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 1756 */ MCD::OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1792
+/* 1761 */ MCD::OPC_ExtractField, 11, 1, // Inst{11} ...
+/* 1764 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1778
+/* 1769 */ MCD::OPC_CheckPredicate, 6, 129, 18, 0, // Skip to: 6511
+/* 1774 */ MCD::OPC_Decode, 236, 19, 59, // Opcode: TEQ_MM
+/* 1778 */ MCD::OPC_FilterValue, 1, 120, 18, 0, // Skip to: 6511
+/* 1783 */ MCD::OPC_CheckPredicate, 6, 115, 18, 0, // Skip to: 6511
+/* 1788 */ MCD::OPC_Decode, 147, 20, 59, // Opcode: TLT_MM
+/* 1792 */ MCD::OPC_FilterValue, 1, 131, 0, 0, // Skip to: 1928
+/* 1797 */ MCD::OPC_ExtractField, 11, 2, // Inst{12-11} ...
+/* 1800 */ MCD::OPC_FilterValue, 0, 45, 0, 0, // Skip to: 1850
+/* 1805 */ MCD::OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 1808 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1829
+/* 1813 */ MCD::OPC_CheckPredicate, 7, 85, 18, 0, // Skip to: 6511
+/* 1818 */ MCD::OPC_CheckField, 21, 5, 0, 78, 18, 0, // Skip to: 6511
+/* 1825 */ MCD::OPC_Decode, 153, 14, 60, // Opcode: MFHI_DSP_MM
+/* 1829 */ MCD::OPC_FilterValue, 1, 69, 18, 0, // Skip to: 6511
+/* 1834 */ MCD::OPC_CheckPredicate, 7, 64, 18, 0, // Skip to: 6511
+/* 1839 */ MCD::OPC_CheckField, 21, 5, 0, 57, 18, 0, // Skip to: 6511
+/* 1846 */ MCD::OPC_Decode, 167, 15, 61, // Opcode: MTHI_DSP_MM
+/* 1850 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1864
+/* 1855 */ MCD::OPC_CheckPredicate, 7, 43, 18, 0, // Skip to: 6511
+/* 1860 */ MCD::OPC_Decode, 234, 17, 62, // Opcode: SHLL_QB_MM
+/* 1864 */ MCD::OPC_FilterValue, 2, 45, 0, 0, // Skip to: 1914
+/* 1869 */ MCD::OPC_ExtractField, 13, 1, // Inst{13} ...
+/* 1872 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1893
+/* 1877 */ MCD::OPC_CheckPredicate, 7, 21, 18, 0, // Skip to: 6511
+/* 1882 */ MCD::OPC_CheckField, 21, 5, 0, 14, 18, 0, // Skip to: 6511
+/* 1889 */ MCD::OPC_Decode, 159, 14, 60, // Opcode: MFLO_DSP_MM
+/* 1893 */ MCD::OPC_FilterValue, 1, 5, 18, 0, // Skip to: 6511
+/* 1898 */ MCD::OPC_CheckPredicate, 7, 0, 18, 0, // Skip to: 6511
+/* 1903 */ MCD::OPC_CheckField, 21, 5, 0, 249, 17, 0, // Skip to: 6511
+/* 1910 */ MCD::OPC_Decode, 174, 15, 63, // Opcode: MTLO_DSP_MM
+/* 1914 */ MCD::OPC_FilterValue, 3, 240, 17, 0, // Skip to: 6511
+/* 1919 */ MCD::OPC_CheckPredicate, 7, 235, 17, 0, // Skip to: 6511
+/* 1924 */ MCD::OPC_Decode, 138, 18, 62, // Opcode: SHRL_QB_MM
+/* 1928 */ MCD::OPC_FilterValue, 2, 101, 0, 0, // Skip to: 2034
+/* 1933 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 1936 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1950
+/* 1941 */ MCD::OPC_CheckPredicate, 8, 213, 17, 0, // Skip to: 6511
+/* 1946 */ MCD::OPC_Decode, 225, 9, 64, // Opcode: DPA_W_PH_MMR2
+/* 1950 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1964
+/* 1955 */ MCD::OPC_CheckPredicate, 8, 199, 17, 0, // Skip to: 6511
+/* 1960 */ MCD::OPC_Decode, 142, 5, 65, // Opcode: BALIGN_MMR2
+/* 1964 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1978
+/* 1969 */ MCD::OPC_CheckPredicate, 8, 185, 17, 0, // Skip to: 6511
+/* 1974 */ MCD::OPC_Decode, 223, 9, 64, // Opcode: DPAX_W_PH_MMR2
+/* 1978 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1992
+/* 1983 */ MCD::OPC_CheckPredicate, 7, 171, 17, 0, // Skip to: 6511
+/* 1988 */ MCD::OPC_Decode, 219, 9, 64, // Opcode: DPAU_H_QBL_MM
+/* 1992 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2006
+/* 1997 */ MCD::OPC_CheckPredicate, 7, 157, 17, 0, // Skip to: 6511
+/* 2002 */ MCD::OPC_Decode, 167, 10, 66, // Opcode: EXTPV_MM
+/* 2006 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2020
+/* 2011 */ MCD::OPC_CheckPredicate, 7, 143, 17, 0, // Skip to: 6511
+/* 2016 */ MCD::OPC_Decode, 221, 9, 64, // Opcode: DPAU_H_QBR_MM
+/* 2020 */ MCD::OPC_FilterValue, 7, 134, 17, 0, // Skip to: 6511
+/* 2025 */ MCD::OPC_CheckPredicate, 7, 129, 17, 0, // Skip to: 6511
+/* 2030 */ MCD::OPC_Decode, 164, 10, 66, // Opcode: EXTPDPV_MM
+/* 2034 */ MCD::OPC_FilterValue, 4, 171, 0, 0, // Skip to: 2210
+/* 2039 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 2042 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2056
+/* 2047 */ MCD::OPC_CheckPredicate, 8, 107, 17, 0, // Skip to: 6511
+/* 2052 */ MCD::OPC_Decode, 130, 4, 67, // Opcode: ABSQ_S_QB_MMR2
+/* 2056 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2070
+/* 2061 */ MCD::OPC_CheckPredicate, 7, 93, 17, 0, // Skip to: 6511
+/* 2066 */ MCD::OPC_Decode, 128, 4, 67, // Opcode: ABSQ_S_PH_MM
+/* 2070 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2084
+/* 2075 */ MCD::OPC_CheckPredicate, 7, 79, 17, 0, // Skip to: 6511
+/* 2080 */ MCD::OPC_Decode, 132, 4, 68, // Opcode: ABSQ_S_W_MM
+/* 2084 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2098
+/* 2089 */ MCD::OPC_CheckPredicate, 7, 65, 17, 0, // Skip to: 6511
+/* 2094 */ MCD::OPC_Decode, 232, 5, 68, // Opcode: BITREV_MM
+/* 2098 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2112
+/* 2103 */ MCD::OPC_CheckPredicate, 7, 51, 17, 0, // Skip to: 6511
+/* 2108 */ MCD::OPC_Decode, 154, 12, 69, // Opcode: INSV_MM
+/* 2112 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2126
+/* 2117 */ MCD::OPC_CheckPredicate, 7, 37, 17, 0, // Skip to: 6511
+/* 2122 */ MCD::OPC_Decode, 181, 16, 70, // Opcode: PRECEQ_W_PHL_MM
+/* 2126 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2140
+/* 2131 */ MCD::OPC_CheckPredicate, 7, 23, 17, 0, // Skip to: 6511
+/* 2136 */ MCD::OPC_Decode, 183, 16, 70, // Opcode: PRECEQ_W_PHR_MM
+/* 2140 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2154
+/* 2145 */ MCD::OPC_CheckPredicate, 7, 9, 17, 0, // Skip to: 6511
+/* 2150 */ MCD::OPC_Decode, 175, 16, 67, // Opcode: PRECEQU_PH_QBL_MM
+/* 2154 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 2168
+/* 2159 */ MCD::OPC_CheckPredicate, 7, 251, 16, 0, // Skip to: 6511
+/* 2164 */ MCD::OPC_Decode, 179, 16, 67, // Opcode: PRECEQU_PH_QBR_MM
+/* 2168 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 2182
+/* 2173 */ MCD::OPC_CheckPredicate, 7, 237, 16, 0, // Skip to: 6511
+/* 2178 */ MCD::OPC_Decode, 187, 16, 67, // Opcode: PRECEU_PH_QBL_MM
+/* 2182 */ MCD::OPC_FilterValue, 26, 9, 0, 0, // Skip to: 2196
+/* 2187 */ MCD::OPC_CheckPredicate, 7, 223, 16, 0, // Skip to: 6511
+/* 2192 */ MCD::OPC_Decode, 191, 16, 67, // Opcode: PRECEU_PH_QBR_MM
+/* 2196 */ MCD::OPC_FilterValue, 30, 214, 16, 0, // Skip to: 6511
+/* 2201 */ MCD::OPC_CheckPredicate, 7, 209, 16, 0, // Skip to: 6511
+/* 2206 */ MCD::OPC_Decode, 216, 16, 70, // Opcode: RADDU_W_QB_MM
+/* 2210 */ MCD::OPC_FilterValue, 5, 87, 0, 0, // Skip to: 2302
+/* 2215 */ MCD::OPC_ExtractField, 11, 15, // Inst{25-11} ...
+/* 2218 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2232
+/* 2223 */ MCD::OPC_CheckPredicate, 9, 187, 16, 0, // Skip to: 6511
+/* 2228 */ MCD::OPC_Decode, 250, 19, 0, // Opcode: TLBGP_MM
+/* 2232 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2246
+/* 2237 */ MCD::OPC_CheckPredicate, 9, 173, 16, 0, // Skip to: 6511
+/* 2242 */ MCD::OPC_Decode, 252, 19, 0, // Opcode: TLBGR_MM
+/* 2246 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2260
+/* 2251 */ MCD::OPC_CheckPredicate, 9, 159, 16, 0, // Skip to: 6511
+/* 2256 */ MCD::OPC_Decode, 254, 19, 0, // Opcode: TLBGWI_MM
+/* 2260 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2274
+/* 2265 */ MCD::OPC_CheckPredicate, 9, 145, 16, 0, // Skip to: 6511
+/* 2270 */ MCD::OPC_Decode, 128, 20, 0, // Opcode: TLBGWR_MM
+/* 2274 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2288
+/* 2279 */ MCD::OPC_CheckPredicate, 9, 131, 16, 0, // Skip to: 6511
+/* 2284 */ MCD::OPC_Decode, 248, 19, 0, // Opcode: TLBGINV_MM
+/* 2288 */ MCD::OPC_FilterValue, 10, 122, 16, 0, // Skip to: 6511
+/* 2293 */ MCD::OPC_CheckPredicate, 9, 117, 16, 0, // Skip to: 6511
+/* 2298 */ MCD::OPC_Decode, 247, 19, 0, // Opcode: TLBGINVF_MM
+/* 2302 */ MCD::OPC_FilterValue, 7, 31, 0, 0, // Skip to: 2338
+/* 2307 */ MCD::OPC_ExtractField, 11, 2, // Inst{12-11} ...
+/* 2310 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2324
+/* 2315 */ MCD::OPC_CheckPredicate, 8, 95, 16, 0, // Skip to: 6511
+/* 2320 */ MCD::OPC_Decode, 252, 17, 62, // Opcode: SHRA_QB_MMR2
+/* 2324 */ MCD::OPC_FilterValue, 2, 86, 16, 0, // Skip to: 6511
+/* 2329 */ MCD::OPC_CheckPredicate, 8, 81, 16, 0, // Skip to: 6511
+/* 2334 */ MCD::OPC_Decode, 128, 18, 62, // Opcode: SHRA_R_QB_MMR2
+/* 2338 */ MCD::OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2374
+/* 2343 */ MCD::OPC_ExtractField, 11, 1, // Inst{11} ...
+/* 2346 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2360
+/* 2351 */ MCD::OPC_CheckPredicate, 6, 59, 16, 0, // Skip to: 6511
+/* 2356 */ MCD::OPC_Decode, 244, 19, 59, // Opcode: TGE_MM
+/* 2360 */ MCD::OPC_FilterValue, 1, 50, 16, 0, // Skip to: 6511
+/* 2365 */ MCD::OPC_CheckPredicate, 6, 45, 16, 0, // Skip to: 6511
+/* 2370 */ MCD::OPC_Decode, 146, 20, 59, // Opcode: TLTU_MM
+/* 2374 */ MCD::OPC_FilterValue, 9, 101, 0, 0, // Skip to: 2480
+/* 2379 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 2382 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2403
+/* 2387 */ MCD::OPC_CheckPredicate, 7, 23, 16, 0, // Skip to: 6511
+/* 2392 */ MCD::OPC_CheckField, 21, 5, 0, 16, 16, 0, // Skip to: 6511
+/* 2399 */ MCD::OPC_Decode, 170, 15, 71, // Opcode: MTHLIP_MM
+/* 2403 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2417
+/* 2408 */ MCD::OPC_CheckPredicate, 7, 2, 16, 0, // Skip to: 6511
+/* 2413 */ MCD::OPC_Decode, 230, 13, 64, // Opcode: MAQ_S_W_PHR_MM
+/* 2417 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2438
+/* 2422 */ MCD::OPC_CheckPredicate, 7, 244, 15, 0, // Skip to: 6511
+/* 2427 */ MCD::OPC_CheckField, 21, 5, 0, 237, 15, 0, // Skip to: 6511
+/* 2434 */ MCD::OPC_Decode, 221, 17, 71, // Opcode: SHILOV_MM
+/* 2438 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2452
+/* 2443 */ MCD::OPC_CheckPredicate, 7, 223, 15, 0, // Skip to: 6511
+/* 2448 */ MCD::OPC_Decode, 228, 13, 64, // Opcode: MAQ_S_W_PHL_MM
+/* 2452 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2466
+/* 2457 */ MCD::OPC_CheckPredicate, 7, 209, 15, 0, // Skip to: 6511
+/* 2462 */ MCD::OPC_Decode, 226, 13, 64, // Opcode: MAQ_SA_W_PHR_MM
+/* 2466 */ MCD::OPC_FilterValue, 7, 200, 15, 0, // Skip to: 6511
+/* 2471 */ MCD::OPC_CheckPredicate, 7, 195, 15, 0, // Skip to: 6511
+/* 2476 */ MCD::OPC_Decode, 224, 13, 64, // Opcode: MAQ_SA_W_PHL_MM
+/* 2480 */ MCD::OPC_FilterValue, 10, 115, 0, 0, // Skip to: 2600
+/* 2485 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 2488 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2502
+/* 2493 */ MCD::OPC_CheckPredicate, 7, 173, 15, 0, // Skip to: 6511
+/* 2498 */ MCD::OPC_Decode, 217, 9, 64, // Opcode: DPAQ_S_W_PH_MM
+/* 2502 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2516
+/* 2507 */ MCD::OPC_CheckPredicate, 7, 159, 15, 0, // Skip to: 6511
+/* 2512 */ MCD::OPC_Decode, 217, 13, 64, // Opcode: MADD_DSP_MM
+/* 2516 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2530
+/* 2521 */ MCD::OPC_CheckPredicate, 7, 145, 15, 0, // Skip to: 6511
+/* 2526 */ MCD::OPC_Decode, 215, 9, 64, // Opcode: DPAQ_SA_L_W_MM
+/* 2530 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2544
+/* 2535 */ MCD::OPC_CheckPredicate, 7, 131, 15, 0, // Skip to: 6511
+/* 2540 */ MCD::OPC_Decode, 207, 13, 64, // Opcode: MADDU_DSP_MM
+/* 2544 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2558
+/* 2549 */ MCD::OPC_CheckPredicate, 8, 117, 15, 0, // Skip to: 6511
+/* 2554 */ MCD::OPC_Decode, 213, 9, 64, // Opcode: DPAQX_S_W_PH_MMR2
+/* 2558 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2572
+/* 2563 */ MCD::OPC_CheckPredicate, 7, 103, 15, 0, // Skip to: 6511
+/* 2568 */ MCD::OPC_Decode, 140, 15, 64, // Opcode: MSUB_DSP_MM
+/* 2572 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2586
+/* 2577 */ MCD::OPC_CheckPredicate, 8, 89, 15, 0, // Skip to: 6511
+/* 2582 */ MCD::OPC_Decode, 211, 9, 64, // Opcode: DPAQX_SA_W_PH_MMR2
+/* 2586 */ MCD::OPC_FilterValue, 7, 80, 15, 0, // Skip to: 6511
+/* 2591 */ MCD::OPC_CheckPredicate, 7, 75, 15, 0, // Skip to: 6511
+/* 2596 */ MCD::OPC_Decode, 130, 15, 64, // Opcode: MSUBU_DSP_MM
+/* 2600 */ MCD::OPC_FilterValue, 12, 27, 1, 0, // Skip to: 2888
+/* 2605 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 2608 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2622
+/* 2613 */ MCD::OPC_CheckPredicate, 7, 53, 15, 0, // Skip to: 6511
+/* 2618 */ MCD::OPC_Decode, 231, 16, 72, // Opcode: REPLV_PH_MM
+/* 2622 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2636
+/* 2627 */ MCD::OPC_CheckPredicate, 7, 39, 15, 0, // Skip to: 6511
+/* 2632 */ MCD::OPC_Decode, 233, 16, 72, // Opcode: REPLV_QB_MM
+/* 2636 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2650
+/* 2641 */ MCD::OPC_CheckPredicate, 6, 25, 15, 0, // Skip to: 6511
+/* 2646 */ MCD::OPC_Decode, 186, 17, 68, // Opcode: SEB_MM
+/* 2650 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2664
+/* 2655 */ MCD::OPC_CheckPredicate, 6, 11, 15, 0, // Skip to: 6511
+/* 2660 */ MCD::OPC_Decode, 189, 17, 68, // Opcode: SEH_MM
+/* 2664 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2678
+/* 2669 */ MCD::OPC_CheckPredicate, 6, 253, 14, 0, // Skip to: 6511
+/* 2674 */ MCD::OPC_Decode, 131, 7, 68, // Opcode: CLO_MM
+/* 2678 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 2692
+/* 2683 */ MCD::OPC_CheckPredicate, 6, 239, 14, 0, // Skip to: 6511
+/* 2688 */ MCD::OPC_Decode, 151, 7, 68, // Opcode: CLZ_MM
+/* 2692 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2706
+/* 2697 */ MCD::OPC_CheckPredicate, 5, 225, 14, 0, // Skip to: 6511
+/* 2702 */ MCD::OPC_Decode, 221, 16, 73, // Opcode: RDHWR_MM
+/* 2706 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2720
+/* 2711 */ MCD::OPC_CheckPredicate, 7, 211, 14, 0, // Skip to: 6511
+/* 2716 */ MCD::OPC_Decode, 174, 16, 67, // Opcode: PRECEQU_PH_QBLA_MM
+/* 2720 */ MCD::OPC_FilterValue, 15, 9, 0, 0, // Skip to: 2734
+/* 2725 */ MCD::OPC_CheckPredicate, 6, 197, 14, 0, // Skip to: 6511
+/* 2730 */ MCD::OPC_Decode, 180, 20, 68, // Opcode: WSBH_MM
+/* 2734 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 2748
+/* 2739 */ MCD::OPC_CheckPredicate, 5, 183, 14, 0, // Skip to: 6511
+/* 2744 */ MCD::OPC_Decode, 215, 15, 74, // Opcode: MULT_MM
+/* 2748 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 2762
+/* 2753 */ MCD::OPC_CheckPredicate, 7, 169, 14, 0, // Skip to: 6511
+/* 2758 */ MCD::OPC_Decode, 178, 16, 67, // Opcode: PRECEQU_PH_QBRA_MM
+/* 2762 */ MCD::OPC_FilterValue, 19, 9, 0, 0, // Skip to: 2776
+/* 2767 */ MCD::OPC_CheckPredicate, 5, 155, 14, 0, // Skip to: 6511
+/* 2772 */ MCD::OPC_Decode, 217, 15, 74, // Opcode: MULTu_MM
+/* 2776 */ MCD::OPC_FilterValue, 21, 9, 0, 0, // Skip to: 2790
+/* 2781 */ MCD::OPC_CheckPredicate, 5, 141, 14, 0, // Skip to: 6511
+/* 2786 */ MCD::OPC_Decode, 179, 17, 74, // Opcode: SDIV_MM
+/* 2790 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 2804
+/* 2795 */ MCD::OPC_CheckPredicate, 7, 127, 14, 0, // Skip to: 6511
+/* 2800 */ MCD::OPC_Decode, 186, 16, 67, // Opcode: PRECEU_PH_QBLA_MM
+/* 2804 */ MCD::OPC_FilterValue, 23, 9, 0, 0, // Skip to: 2818
+/* 2809 */ MCD::OPC_CheckPredicate, 5, 113, 14, 0, // Skip to: 6511
+/* 2814 */ MCD::OPC_Decode, 165, 20, 74, // Opcode: UDIV_MM
+/* 2818 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 2832
+/* 2823 */ MCD::OPC_CheckPredicate, 5, 99, 14, 0, // Skip to: 6511
+/* 2828 */ MCD::OPC_Decode, 218, 13, 74, // Opcode: MADD_MM
+/* 2832 */ MCD::OPC_FilterValue, 26, 9, 0, 0, // Skip to: 2846
+/* 2837 */ MCD::OPC_CheckPredicate, 7, 85, 14, 0, // Skip to: 6511
+/* 2842 */ MCD::OPC_Decode, 190, 16, 67, // Opcode: PRECEU_PH_QBRA_MM
+/* 2846 */ MCD::OPC_FilterValue, 27, 9, 0, 0, // Skip to: 2860
+/* 2851 */ MCD::OPC_CheckPredicate, 5, 71, 14, 0, // Skip to: 6511
+/* 2856 */ MCD::OPC_Decode, 208, 13, 74, // Opcode: MADDU_MM
+/* 2860 */ MCD::OPC_FilterValue, 29, 9, 0, 0, // Skip to: 2874
+/* 2865 */ MCD::OPC_CheckPredicate, 5, 57, 14, 0, // Skip to: 6511
+/* 2870 */ MCD::OPC_Decode, 141, 15, 74, // Opcode: MSUB_MM
+/* 2874 */ MCD::OPC_FilterValue, 31, 48, 14, 0, // Skip to: 6511
+/* 2879 */ MCD::OPC_CheckPredicate, 5, 43, 14, 0, // Skip to: 6511
+/* 2884 */ MCD::OPC_Decode, 131, 15, 74, // Opcode: MSUBU_MM
+/* 2888 */ MCD::OPC_FilterValue, 13, 206, 0, 0, // Skip to: 3099
+/* 2893 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 2896 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2917
+/* 2901 */ MCD::OPC_CheckPredicate, 6, 21, 14, 0, // Skip to: 6511
+/* 2906 */ MCD::OPC_CheckField, 16, 10, 0, 14, 14, 0, // Skip to: 6511
+/* 2913 */ MCD::OPC_Decode, 134, 20, 0, // Opcode: TLBP_MM
+/* 2917 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2938
+/* 2922 */ MCD::OPC_CheckPredicate, 6, 0, 14, 0, // Skip to: 6511
+/* 2927 */ MCD::OPC_CheckField, 16, 10, 0, 249, 13, 0, // Skip to: 6511
+/* 2934 */ MCD::OPC_Decode, 136, 20, 0, // Opcode: TLBR_MM
+/* 2938 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2959
+/* 2943 */ MCD::OPC_CheckPredicate, 6, 235, 13, 0, // Skip to: 6511
+/* 2948 */ MCD::OPC_CheckField, 16, 10, 0, 228, 13, 0, // Skip to: 6511
+/* 2955 */ MCD::OPC_Decode, 138, 20, 0, // Opcode: TLBWI_MM
+/* 2959 */ MCD::OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2980
+/* 2964 */ MCD::OPC_CheckPredicate, 6, 214, 13, 0, // Skip to: 6511
+/* 2969 */ MCD::OPC_CheckField, 16, 10, 0, 207, 13, 0, // Skip to: 6511
+/* 2976 */ MCD::OPC_Decode, 140, 20, 0, // Opcode: TLBWR_MM
+/* 2980 */ MCD::OPC_FilterValue, 13, 16, 0, 0, // Skip to: 3001
+/* 2985 */ MCD::OPC_CheckPredicate, 6, 193, 13, 0, // Skip to: 6511
+/* 2990 */ MCD::OPC_CheckField, 21, 5, 0, 186, 13, 0, // Skip to: 6511
+/* 2997 */ MCD::OPC_Decode, 208, 19, 75, // Opcode: SYNC_MM
+/* 3001 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 3015
+/* 3006 */ MCD::OPC_CheckPredicate, 6, 172, 13, 0, // Skip to: 6511
+/* 3011 */ MCD::OPC_Decode, 211, 19, 76, // Opcode: SYSCALL_MM
+/* 3015 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 3029
+/* 3020 */ MCD::OPC_CheckPredicate, 6, 158, 13, 0, // Skip to: 6511
+/* 3025 */ MCD::OPC_Decode, 174, 20, 76, // Opcode: WAIT_MM
+/* 3029 */ MCD::OPC_FilterValue, 24, 9, 0, 0, // Skip to: 3043
+/* 3034 */ MCD::OPC_CheckPredicate, 9, 144, 13, 0, // Skip to: 6511
+/* 3039 */ MCD::OPC_Decode, 255, 11, 76, // Opcode: HYPCALL_MM
+/* 3043 */ MCD::OPC_FilterValue, 27, 9, 0, 0, // Skip to: 3057
+/* 3048 */ MCD::OPC_CheckPredicate, 6, 130, 13, 0, // Skip to: 6511
+/* 3053 */ MCD::OPC_Decode, 167, 17, 76, // Opcode: SDBBP_MM
+/* 3057 */ MCD::OPC_FilterValue, 28, 16, 0, 0, // Skip to: 3078
+/* 3062 */ MCD::OPC_CheckPredicate, 6, 116, 13, 0, // Skip to: 6511
+/* 3067 */ MCD::OPC_CheckField, 16, 10, 0, 109, 13, 0, // Skip to: 6511
+/* 3074 */ MCD::OPC_Decode, 152, 9, 0, // Opcode: DERET_MM
+/* 3078 */ MCD::OPC_FilterValue, 30, 100, 13, 0, // Skip to: 6511
+/* 3083 */ MCD::OPC_CheckPredicate, 6, 95, 13, 0, // Skip to: 6511
+/* 3088 */ MCD::OPC_CheckField, 16, 10, 0, 88, 13, 0, // Skip to: 6511
+/* 3095 */ MCD::OPC_Decode, 155, 10, 0, // Opcode: ERET_MM
+/* 3099 */ MCD::OPC_FilterValue, 15, 16, 0, 0, // Skip to: 3120
+/* 3104 */ MCD::OPC_CheckPredicate, 8, 74, 13, 0, // Skip to: 6511
+/* 3109 */ MCD::OPC_CheckField, 11, 1, 0, 67, 13, 0, // Skip to: 6511
+/* 3116 */ MCD::OPC_Decode, 136, 18, 58, // Opcode: SHRL_PH_MMR2
+/* 3120 */ MCD::OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3156
+/* 3125 */ MCD::OPC_ExtractField, 11, 1, // Inst{11} ...
+/* 3128 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3142
+/* 3133 */ MCD::OPC_CheckPredicate, 6, 45, 13, 0, // Skip to: 6511
+/* 3138 */ MCD::OPC_Decode, 243, 19, 59, // Opcode: TGEU_MM
+/* 3142 */ MCD::OPC_FilterValue, 1, 36, 13, 0, // Skip to: 6511
+/* 3147 */ MCD::OPC_CheckPredicate, 6, 31, 13, 0, // Skip to: 6511
+/* 3152 */ MCD::OPC_Decode, 151, 20, 59, // Opcode: TNE_MM
+/* 3156 */ MCD::OPC_FilterValue, 18, 115, 0, 0, // Skip to: 3276
+/* 3161 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 3164 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3178
+/* 3169 */ MCD::OPC_CheckPredicate, 8, 9, 13, 0, // Skip to: 6511
+/* 3174 */ MCD::OPC_Decode, 248, 9, 64, // Opcode: DPS_W_PH_MMR2
+/* 3178 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3192
+/* 3183 */ MCD::OPC_CheckPredicate, 7, 251, 12, 0, // Skip to: 6511
+/* 3188 */ MCD::OPC_Decode, 214, 15, 77, // Opcode: MULT_DSP_MM
+/* 3192 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3206
+/* 3197 */ MCD::OPC_CheckPredicate, 8, 237, 12, 0, // Skip to: 6511
+/* 3202 */ MCD::OPC_Decode, 246, 9, 64, // Opcode: DPSX_W_PH_MMR2
+/* 3206 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3220
+/* 3211 */ MCD::OPC_CheckPredicate, 7, 223, 12, 0, // Skip to: 6511
+/* 3216 */ MCD::OPC_Decode, 212, 15, 77, // Opcode: MULTU_DSP_MM
+/* 3220 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3234
+/* 3225 */ MCD::OPC_CheckPredicate, 7, 209, 12, 0, // Skip to: 6511
+/* 3230 */ MCD::OPC_Decode, 242, 9, 64, // Opcode: DPSU_H_QBL_MM
+/* 3234 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3248
+/* 3239 */ MCD::OPC_CheckPredicate, 8, 195, 12, 0, // Skip to: 6511
+/* 3244 */ MCD::OPC_Decode, 209, 15, 64, // Opcode: MULSA_W_PH_MMR2
+/* 3248 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3262
+/* 3253 */ MCD::OPC_CheckPredicate, 7, 181, 12, 0, // Skip to: 6511
+/* 3258 */ MCD::OPC_Decode, 244, 9, 64, // Opcode: DPSU_H_QBR_MM
+/* 3262 */ MCD::OPC_FilterValue, 7, 172, 12, 0, // Skip to: 6511
+/* 3267 */ MCD::OPC_CheckPredicate, 7, 167, 12, 0, // Skip to: 6511
+/* 3272 */ MCD::OPC_Decode, 207, 15, 64, // Opcode: MULSAQ_S_W_PH_MM
+/* 3276 */ MCD::OPC_FilterValue, 19, 16, 0, 0, // Skip to: 3297
+/* 3281 */ MCD::OPC_CheckPredicate, 9, 153, 12, 0, // Skip to: 6511
+/* 3286 */ MCD::OPC_CheckField, 14, 2, 0, 146, 12, 0, // Skip to: 6511
+/* 3293 */ MCD::OPC_Decode, 140, 14, 56, // Opcode: MFGC0_MM
+/* 3297 */ MCD::OPC_FilterValue, 20, 31, 0, 0, // Skip to: 3333
+/* 3302 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 3305 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 3319
+/* 3310 */ MCD::OPC_CheckPredicate, 6, 124, 12, 0, // Skip to: 6511
+/* 3315 */ MCD::OPC_Decode, 232, 6, 78, // Opcode: CFC2_MM
+/* 3319 */ MCD::OPC_FilterValue, 27, 115, 12, 0, // Skip to: 6511
+/* 3324 */ MCD::OPC_CheckPredicate, 6, 110, 12, 0, // Skip to: 6511
+/* 3329 */ MCD::OPC_Decode, 131, 8, 79, // Opcode: CTC2_MM
+/* 3333 */ MCD::OPC_FilterValue, 21, 87, 0, 0, // Skip to: 3425
+/* 3338 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 3341 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3362
+/* 3346 */ MCD::OPC_CheckPredicate, 5, 88, 12, 0, // Skip to: 6511
+/* 3351 */ MCD::OPC_CheckField, 21, 5, 0, 81, 12, 0, // Skip to: 6511
+/* 3358 */ MCD::OPC_Decode, 154, 14, 80, // Opcode: MFHI_MM
+/* 3362 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 3383
+/* 3367 */ MCD::OPC_CheckPredicate, 5, 67, 12, 0, // Skip to: 6511
+/* 3372 */ MCD::OPC_CheckField, 21, 5, 0, 60, 12, 0, // Skip to: 6511
+/* 3379 */ MCD::OPC_Decode, 160, 14, 80, // Opcode: MFLO_MM
+/* 3383 */ MCD::OPC_FilterValue, 5, 16, 0, 0, // Skip to: 3404
+/* 3388 */ MCD::OPC_CheckPredicate, 5, 46, 12, 0, // Skip to: 6511
+/* 3393 */ MCD::OPC_CheckField, 21, 5, 0, 39, 12, 0, // Skip to: 6511
+/* 3400 */ MCD::OPC_Decode, 168, 15, 80, // Opcode: MTHI_MM
+/* 3404 */ MCD::OPC_FilterValue, 7, 30, 12, 0, // Skip to: 6511
+/* 3409 */ MCD::OPC_CheckPredicate, 5, 25, 12, 0, // Skip to: 6511
+/* 3414 */ MCD::OPC_CheckField, 21, 5, 0, 18, 12, 0, // Skip to: 6511
+/* 3421 */ MCD::OPC_Decode, 175, 15, 80, // Opcode: MTLO_MM
+/* 3425 */ MCD::OPC_FilterValue, 23, 16, 0, 0, // Skip to: 3446
+/* 3430 */ MCD::OPC_CheckPredicate, 7, 4, 12, 0, // Skip to: 6511
+/* 3435 */ MCD::OPC_CheckField, 11, 2, 0, 253, 11, 0, // Skip to: 6511
+/* 3442 */ MCD::OPC_Decode, 237, 16, 81, // Opcode: REPL_QB_MM
+/* 3446 */ MCD::OPC_FilterValue, 25, 115, 0, 0, // Skip to: 3566
+/* 3451 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 3454 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3468
+/* 3459 */ MCD::OPC_CheckPredicate, 7, 231, 11, 0, // Skip to: 6511
+/* 3464 */ MCD::OPC_Decode, 218, 16, 82, // Opcode: RDDSP_MM
+/* 3468 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3482
+/* 3473 */ MCD::OPC_CheckPredicate, 7, 217, 11, 0, // Skip to: 6511
+/* 3478 */ MCD::OPC_Decode, 184, 10, 83, // Opcode: EXTR_W_MM
+/* 3482 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3496
+/* 3487 */ MCD::OPC_CheckPredicate, 7, 203, 11, 0, // Skip to: 6511
+/* 3492 */ MCD::OPC_Decode, 177, 20, 82, // Opcode: WRDSP_MM
+/* 3496 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3510
+/* 3501 */ MCD::OPC_CheckPredicate, 7, 189, 11, 0, // Skip to: 6511
+/* 3506 */ MCD::OPC_Decode, 180, 10, 83, // Opcode: EXTR_R_W_MM
+/* 3510 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3524
+/* 3515 */ MCD::OPC_CheckPredicate, 7, 175, 11, 0, // Skip to: 6511
+/* 3520 */ MCD::OPC_Decode, 168, 10, 83, // Opcode: EXTP_MM
+/* 3524 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3538
+/* 3529 */ MCD::OPC_CheckPredicate, 7, 161, 11, 0, // Skip to: 6511
+/* 3534 */ MCD::OPC_Decode, 178, 10, 83, // Opcode: EXTR_RS_W_MM
+/* 3538 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3552
+/* 3543 */ MCD::OPC_CheckPredicate, 7, 147, 11, 0, // Skip to: 6511
+/* 3548 */ MCD::OPC_Decode, 165, 10, 83, // Opcode: EXTPDP_MM
+/* 3552 */ MCD::OPC_FilterValue, 7, 138, 11, 0, // Skip to: 6511
+/* 3557 */ MCD::OPC_CheckPredicate, 7, 133, 11, 0, // Skip to: 6511
+/* 3562 */ MCD::OPC_Decode, 182, 10, 83, // Opcode: EXTR_S_H_MM
+/* 3566 */ MCD::OPC_FilterValue, 26, 115, 0, 0, // Skip to: 3686
+/* 3571 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 3574 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3588
+/* 3579 */ MCD::OPC_CheckPredicate, 7, 111, 11, 0, // Skip to: 6511
+/* 3584 */ MCD::OPC_Decode, 234, 9, 64, // Opcode: DPSQ_S_W_PH_MM
+/* 3588 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3602
+/* 3593 */ MCD::OPC_CheckPredicate, 7, 97, 11, 0, // Skip to: 6511
+/* 3598 */ MCD::OPC_Decode, 176, 10, 66, // Opcode: EXTRV_W_MM
+/* 3602 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3616
+/* 3607 */ MCD::OPC_CheckPredicate, 7, 83, 11, 0, // Skip to: 6511
+/* 3612 */ MCD::OPC_Decode, 232, 9, 64, // Opcode: DPSQ_SA_L_W_MM
+/* 3616 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3630
+/* 3621 */ MCD::OPC_CheckPredicate, 7, 69, 11, 0, // Skip to: 6511
+/* 3626 */ MCD::OPC_Decode, 172, 10, 66, // Opcode: EXTRV_R_W_MM
+/* 3630 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3644
+/* 3635 */ MCD::OPC_CheckPredicate, 8, 55, 11, 0, // Skip to: 6511
+/* 3640 */ MCD::OPC_Decode, 230, 9, 64, // Opcode: DPSQX_S_W_PH_MMR2
+/* 3644 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3658
+/* 3649 */ MCD::OPC_CheckPredicate, 7, 41, 11, 0, // Skip to: 6511
+/* 3654 */ MCD::OPC_Decode, 170, 10, 66, // Opcode: EXTRV_RS_W_MM
+/* 3658 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3672
+/* 3663 */ MCD::OPC_CheckPredicate, 8, 27, 11, 0, // Skip to: 6511
+/* 3668 */ MCD::OPC_Decode, 228, 9, 64, // Opcode: DPSQX_SA_W_PH_MMR2
+/* 3672 */ MCD::OPC_FilterValue, 7, 18, 11, 0, // Skip to: 6511
+/* 3677 */ MCD::OPC_CheckPredicate, 7, 13, 11, 0, // Skip to: 6511
+/* 3682 */ MCD::OPC_Decode, 174, 10, 66, // Opcode: EXTRV_S_H_MM
+/* 3686 */ MCD::OPC_FilterValue, 27, 16, 0, 0, // Skip to: 3707
+/* 3691 */ MCD::OPC_CheckPredicate, 9, 255, 10, 0, // Skip to: 6511
+/* 3696 */ MCD::OPC_CheckField, 14, 2, 0, 248, 10, 0, // Skip to: 6511
+/* 3703 */ MCD::OPC_Decode, 155, 15, 57, // Opcode: MTGC0_MM
+/* 3707 */ MCD::OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3759
+/* 3712 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 3715 */ MCD::OPC_FilterValue, 1, 25, 0, 0, // Skip to: 3745
+/* 3720 */ MCD::OPC_CheckPredicate, 5, 11, 0, 0, // Skip to: 3736
+/* 3725 */ MCD::OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3736
+/* 3732 */ MCD::OPC_Decode, 191, 12, 80, // Opcode: JR_MM
+/* 3736 */ MCD::OPC_CheckPredicate, 5, 210, 10, 0, // Skip to: 6511
+/* 3741 */ MCD::OPC_Decode, 169, 12, 68, // Opcode: JALR_MM
+/* 3745 */ MCD::OPC_FilterValue, 9, 201, 10, 0, // Skip to: 6511
+/* 3750 */ MCD::OPC_CheckPredicate, 5, 196, 10, 0, // Skip to: 6511
+/* 3755 */ MCD::OPC_Decode, 166, 12, 68, // Opcode: JALRS_MM
+/* 3759 */ MCD::OPC_FilterValue, 29, 187, 10, 0, // Skip to: 6511
+/* 3764 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 3767 */ MCD::OPC_FilterValue, 8, 16, 0, 0, // Skip to: 3788
+/* 3772 */ MCD::OPC_CheckPredicate, 6, 174, 10, 0, // Skip to: 6511
+/* 3777 */ MCD::OPC_CheckField, 21, 5, 0, 167, 10, 0, // Skip to: 6511
+/* 3784 */ MCD::OPC_Decode, 174, 9, 80, // Opcode: DI_MM
+/* 3788 */ MCD::OPC_FilterValue, 10, 158, 10, 0, // Skip to: 6511
+/* 3793 */ MCD::OPC_CheckPredicate, 6, 153, 10, 0, // Skip to: 6511
+/* 3798 */ MCD::OPC_CheckField, 21, 5, 0, 146, 10, 0, // Skip to: 6511
+/* 3805 */ MCD::OPC_Decode, 149, 10, 80, // Opcode: EI_MM
+/* 3809 */ MCD::OPC_FilterValue, 61, 137, 10, 0, // Skip to: 6511
+/* 3814 */ MCD::OPC_CheckPredicate, 7, 132, 10, 0, // Skip to: 6511
+/* 3819 */ MCD::OPC_CheckField, 6, 5, 0, 125, 10, 0, // Skip to: 6511
+/* 3826 */ MCD::OPC_Decode, 235, 16, 84, // Opcode: REPL_PH_MM
+/* 3830 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3844
+/* 3835 */ MCD::OPC_CheckPredicate, 5, 111, 10, 0, // Skip to: 6511
+/* 3840 */ MCD::OPC_Decode, 202, 4, 85, // Opcode: ADDi_MM
+/* 3844 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3858
+/* 3849 */ MCD::OPC_CheckPredicate, 6, 97, 10, 0, // Skip to: 6511
+/* 3854 */ MCD::OPC_Decode, 213, 12, 86, // Opcode: LBu_MM
+/* 3858 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3872
+/* 3863 */ MCD::OPC_CheckPredicate, 6, 83, 10, 0, // Skip to: 6511
+/* 3868 */ MCD::OPC_Decode, 151, 17, 86, // Opcode: SB_MM
+/* 3872 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 3886
+/* 3877 */ MCD::OPC_CheckPredicate, 6, 69, 10, 0, // Skip to: 6511
+/* 3882 */ MCD::OPC_Decode, 207, 12, 86, // Opcode: LB_MM
+/* 3886 */ MCD::OPC_FilterValue, 8, 73, 0, 0, // Skip to: 3964
+/* 3891 */ MCD::OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 3894 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3908
+/* 3899 */ MCD::OPC_CheckPredicate, 6, 47, 10, 0, // Skip to: 6511
+/* 3904 */ MCD::OPC_Decode, 170, 13, 87, // Opcode: LWP_MM
+/* 3908 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 3922
+/* 3913 */ MCD::OPC_CheckPredicate, 6, 33, 10, 0, // Skip to: 6511
+/* 3918 */ MCD::OPC_Decode, 167, 13, 87, // Opcode: LWM32_MM
+/* 3922 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 3936
+/* 3927 */ MCD::OPC_CheckPredicate, 5, 19, 10, 0, // Skip to: 6511
+/* 3932 */ MCD::OPC_Decode, 208, 6, 88, // Opcode: CACHE_MM
+/* 3936 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 3950
+/* 3941 */ MCD::OPC_CheckPredicate, 6, 5, 10, 0, // Skip to: 6511
+/* 3946 */ MCD::OPC_Decode, 192, 19, 87, // Opcode: SWP_MM
+/* 3950 */ MCD::OPC_FilterValue, 13, 252, 9, 0, // Skip to: 6511
+/* 3955 */ MCD::OPC_CheckPredicate, 6, 247, 9, 0, // Skip to: 6511
+/* 3960 */ MCD::OPC_Decode, 191, 19, 87, // Opcode: SWM32_MM
+/* 3964 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 3978
+/* 3969 */ MCD::OPC_CheckPredicate, 5, 233, 9, 0, // Skip to: 6511
+/* 3974 */ MCD::OPC_Decode, 204, 4, 85, // Opcode: ADDiu_MM
+/* 3978 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 3992
+/* 3983 */ MCD::OPC_CheckPredicate, 6, 219, 9, 0, // Skip to: 6511
+/* 3988 */ MCD::OPC_Decode, 251, 12, 86, // Opcode: LHu_MM
+/* 3992 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4006
+/* 3997 */ MCD::OPC_CheckPredicate, 6, 205, 9, 0, // Skip to: 6511
+/* 4002 */ MCD::OPC_Decode, 139, 18, 86, // Opcode: SH_MM
+/* 4006 */ MCD::OPC_FilterValue, 15, 9, 0, 0, // Skip to: 4020
+/* 4011 */ MCD::OPC_CheckPredicate, 6, 191, 9, 0, // Skip to: 6511
+/* 4016 */ MCD::OPC_Decode, 246, 12, 86, // Opcode: LH_MM
+/* 4020 */ MCD::OPC_FilterValue, 16, 83, 1, 0, // Skip to: 4364
+/* 4025 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 4028 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4042
+/* 4033 */ MCD::OPC_CheckPredicate, 5, 169, 9, 0, // Skip to: 6511
+/* 4038 */ MCD::OPC_Decode, 134, 6, 89, // Opcode: BLTZ_MM
+/* 4042 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4056
+/* 4047 */ MCD::OPC_CheckPredicate, 5, 155, 9, 0, // Skip to: 6511
+/* 4052 */ MCD::OPC_Decode, 129, 6, 89, // Opcode: BLTZAL_MM
+/* 4056 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4070
+/* 4061 */ MCD::OPC_CheckPredicate, 5, 141, 9, 0, // Skip to: 6511
+/* 4066 */ MCD::OPC_Decode, 205, 5, 89, // Opcode: BGEZ_MM
+/* 4070 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 4084
+/* 4075 */ MCD::OPC_CheckPredicate, 5, 127, 9, 0, // Skip to: 6511
+/* 4080 */ MCD::OPC_Decode, 200, 5, 89, // Opcode: BGEZAL_MM
+/* 4084 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4098
+/* 4089 */ MCD::OPC_CheckPredicate, 5, 113, 9, 0, // Skip to: 6511
+/* 4094 */ MCD::OPC_Decode, 243, 5, 89, // Opcode: BLEZ_MM
+/* 4098 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4112
+/* 4103 */ MCD::OPC_CheckPredicate, 5, 99, 9, 0, // Skip to: 6511
+/* 4108 */ MCD::OPC_Decode, 159, 6, 89, // Opcode: BNEZC_MM
+/* 4112 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4126
+/* 4117 */ MCD::OPC_CheckPredicate, 5, 85, 9, 0, // Skip to: 6511
+/* 4122 */ MCD::OPC_Decode, 214, 5, 89, // Opcode: BGTZ_MM
+/* 4126 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 4140
+/* 4131 */ MCD::OPC_CheckPredicate, 5, 71, 9, 0, // Skip to: 6511
+/* 4136 */ MCD::OPC_Decode, 184, 5, 89, // Opcode: BEQZC_MM
+/* 4140 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 4154
+/* 4145 */ MCD::OPC_CheckPredicate, 5, 57, 9, 0, // Skip to: 6511
+/* 4150 */ MCD::OPC_Decode, 144, 20, 90, // Opcode: TLTI_MM
+/* 4154 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 4168
+/* 4159 */ MCD::OPC_CheckPredicate, 5, 43, 9, 0, // Skip to: 6511
+/* 4164 */ MCD::OPC_Decode, 241, 19, 90, // Opcode: TGEI_MM
+/* 4168 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 4182
+/* 4173 */ MCD::OPC_CheckPredicate, 5, 29, 9, 0, // Skip to: 6511
+/* 4178 */ MCD::OPC_Decode, 143, 20, 90, // Opcode: TLTIU_MM
+/* 4182 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 4196
+/* 4187 */ MCD::OPC_CheckPredicate, 5, 15, 9, 0, // Skip to: 6511
+/* 4192 */ MCD::OPC_Decode, 240, 19, 90, // Opcode: TGEIU_MM
+/* 4196 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 4210
+/* 4201 */ MCD::OPC_CheckPredicate, 5, 1, 9, 0, // Skip to: 6511
+/* 4206 */ MCD::OPC_Decode, 150, 20, 90, // Opcode: TNEI_MM
+/* 4210 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 4224
+/* 4215 */ MCD::OPC_CheckPredicate, 5, 243, 8, 0, // Skip to: 6511
+/* 4220 */ MCD::OPC_Decode, 145, 13, 91, // Opcode: LUi_MM
+/* 4224 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4238
+/* 4229 */ MCD::OPC_CheckPredicate, 5, 229, 8, 0, // Skip to: 6511
+/* 4234 */ MCD::OPC_Decode, 235, 19, 90, // Opcode: TEQI_MM
+/* 4238 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 4252
+/* 4243 */ MCD::OPC_CheckPredicate, 5, 215, 8, 0, // Skip to: 6511
+/* 4248 */ MCD::OPC_Decode, 206, 19, 92, // Opcode: SYNCI_MM
+/* 4252 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 4266
+/* 4257 */ MCD::OPC_CheckPredicate, 5, 201, 8, 0, // Skip to: 6511
+/* 4262 */ MCD::OPC_Decode, 128, 6, 89, // Opcode: BLTZALS_MM
+/* 4266 */ MCD::OPC_FilterValue, 19, 9, 0, 0, // Skip to: 4280
+/* 4271 */ MCD::OPC_CheckPredicate, 5, 187, 8, 0, // Skip to: 6511
+/* 4276 */ MCD::OPC_Decode, 199, 5, 89, // Opcode: BGEZALS_MM
+/* 4280 */ MCD::OPC_FilterValue, 25, 16, 0, 0, // Skip to: 4301
+/* 4285 */ MCD::OPC_CheckPredicate, 10, 173, 8, 0, // Skip to: 6511
+/* 4290 */ MCD::OPC_CheckField, 16, 5, 0, 166, 8, 0, // Skip to: 6511
+/* 4297 */ MCD::OPC_Decode, 172, 6, 93, // Opcode: BPOSGE32C_MMR3
+/* 4301 */ MCD::OPC_FilterValue, 27, 16, 0, 0, // Skip to: 4322
+/* 4306 */ MCD::OPC_CheckPredicate, 11, 152, 8, 0, // Skip to: 6511
+/* 4311 */ MCD::OPC_CheckField, 16, 5, 0, 145, 8, 0, // Skip to: 6511
+/* 4318 */ MCD::OPC_Decode, 173, 6, 94, // Opcode: BPOSGE32_MM
+/* 4322 */ MCD::OPC_FilterValue, 28, 16, 0, 0, // Skip to: 4343
+/* 4327 */ MCD::OPC_CheckPredicate, 12, 131, 8, 0, // Skip to: 6511
+/* 4332 */ MCD::OPC_CheckField, 16, 2, 0, 124, 8, 0, // Skip to: 6511
+/* 4339 */ MCD::OPC_Decode, 153, 5, 95, // Opcode: BC1F_MM
+/* 4343 */ MCD::OPC_FilterValue, 29, 115, 8, 0, // Skip to: 6511
+/* 4348 */ MCD::OPC_CheckPredicate, 12, 110, 8, 0, // Skip to: 6511
+/* 4353 */ MCD::OPC_CheckField, 16, 2, 0, 103, 8, 0, // Skip to: 6511
+/* 4360 */ MCD::OPC_Decode, 158, 5, 95, // Opcode: BC1T_MM
+/* 4364 */ MCD::OPC_FilterValue, 20, 9, 0, 0, // Skip to: 4378
+/* 4369 */ MCD::OPC_CheckPredicate, 5, 89, 8, 0, // Skip to: 6511
+/* 4374 */ MCD::OPC_Decode, 148, 16, 96, // Opcode: ORi_MM
+/* 4378 */ MCD::OPC_FilterValue, 21, 197, 5, 0, // Skip to: 5860
+/* 4383 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 4386 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4400
+/* 4391 */ MCD::OPC_CheckPredicate, 13, 67, 8, 0, // Skip to: 6511
+/* 4396 */ MCD::OPC_Decode, 222, 13, 97, // Opcode: MADD_S_MM
+/* 4400 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4414
+/* 4405 */ MCD::OPC_CheckPredicate, 13, 53, 8, 0, // Skip to: 6511
+/* 4410 */ MCD::OPC_Decode, 249, 15, 97, // Opcode: NMADD_S_MM
+/* 4414 */ MCD::OPC_FilterValue, 8, 59, 0, 0, // Skip to: 4478
+/* 4419 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 4422 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4436
+/* 4427 */ MCD::OPC_CheckPredicate, 12, 31, 8, 0, // Skip to: 6511
+/* 4432 */ MCD::OPC_Decode, 181, 13, 98, // Opcode: LWXC1_MM
+/* 4436 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 4450
+/* 4441 */ MCD::OPC_CheckPredicate, 12, 17, 8, 0, // Skip to: 6511
+/* 4446 */ MCD::OPC_Decode, 201, 19, 98, // Opcode: SWXC1_MM
+/* 4450 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4464
+/* 4455 */ MCD::OPC_CheckPredicate, 14, 3, 8, 0, // Skip to: 6511
+/* 4460 */ MCD::OPC_Decode, 142, 13, 99, // Opcode: LUXC1_MM
+/* 4464 */ MCD::OPC_FilterValue, 6, 250, 7, 0, // Skip to: 6511
+/* 4469 */ MCD::OPC_CheckPredicate, 14, 245, 7, 0, // Skip to: 6511
+/* 4474 */ MCD::OPC_Decode, 169, 19, 99, // Opcode: SUXC1_MM
+/* 4478 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 4492
+/* 4483 */ MCD::OPC_CheckPredicate, 15, 231, 7, 0, // Skip to: 6511
+/* 4488 */ MCD::OPC_Decode, 214, 13, 100, // Opcode: MADD_D32_MM
+/* 4492 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 4506
+/* 4497 */ MCD::OPC_CheckPredicate, 15, 217, 7, 0, // Skip to: 6511
+/* 4502 */ MCD::OPC_Decode, 246, 15, 100, // Opcode: NMADD_D32_MM
+/* 4506 */ MCD::OPC_FilterValue, 32, 101, 0, 0, // Skip to: 4612
+/* 4511 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 4514 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4535
+/* 4519 */ MCD::OPC_CheckPredicate, 12, 195, 7, 0, // Skip to: 6511
+/* 4524 */ MCD::OPC_CheckField, 11, 2, 0, 188, 7, 0, // Skip to: 6511
+/* 4531 */ MCD::OPC_Decode, 216, 14, 101, // Opcode: MOVF_S_MM
+/* 4535 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4556
+/* 4540 */ MCD::OPC_CheckPredicate, 12, 174, 7, 0, // Skip to: 6511
+/* 4545 */ MCD::OPC_CheckField, 11, 2, 0, 167, 7, 0, // Skip to: 6511
+/* 4552 */ MCD::OPC_Decode, 236, 14, 101, // Opcode: MOVT_S_MM
+/* 4556 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4570
+/* 4561 */ MCD::OPC_CheckPredicate, 5, 153, 7, 0, // Skip to: 6511
+/* 4566 */ MCD::OPC_Decode, 209, 16, 102, // Opcode: PREFX_MM
+/* 4570 */ MCD::OPC_FilterValue, 8, 16, 0, 0, // Skip to: 4591
+/* 4575 */ MCD::OPC_CheckPredicate, 16, 139, 7, 0, // Skip to: 6511
+/* 4580 */ MCD::OPC_CheckField, 11, 2, 0, 132, 7, 0, // Skip to: 6511
+/* 4587 */ MCD::OPC_Decode, 210, 14, 103, // Opcode: MOVF_D32_MM
+/* 4591 */ MCD::OPC_FilterValue, 9, 123, 7, 0, // Skip to: 6511
+/* 4596 */ MCD::OPC_CheckPredicate, 16, 118, 7, 0, // Skip to: 6511
+/* 4601 */ MCD::OPC_CheckField, 11, 2, 0, 111, 7, 0, // Skip to: 6511
+/* 4608 */ MCD::OPC_Decode, 230, 14, 103, // Opcode: MOVT_D32_MM
+/* 4612 */ MCD::OPC_FilterValue, 33, 9, 0, 0, // Skip to: 4626
+/* 4617 */ MCD::OPC_CheckPredicate, 13, 97, 7, 0, // Skip to: 6511
+/* 4622 */ MCD::OPC_Decode, 145, 15, 97, // Opcode: MSUB_S_MM
+/* 4626 */ MCD::OPC_FilterValue, 34, 9, 0, 0, // Skip to: 4640
+/* 4631 */ MCD::OPC_CheckPredicate, 13, 83, 7, 0, // Skip to: 6511
+/* 4636 */ MCD::OPC_Decode, 254, 15, 97, // Opcode: NMSUB_S_MM
+/* 4640 */ MCD::OPC_FilterValue, 41, 9, 0, 0, // Skip to: 4654
+/* 4645 */ MCD::OPC_CheckPredicate, 15, 69, 7, 0, // Skip to: 6511
+/* 4650 */ MCD::OPC_Decode, 137, 15, 100, // Opcode: MSUB_D32_MM
+/* 4654 */ MCD::OPC_FilterValue, 42, 9, 0, 0, // Skip to: 4668
+/* 4659 */ MCD::OPC_CheckPredicate, 15, 55, 7, 0, // Skip to: 6511
+/* 4664 */ MCD::OPC_Decode, 251, 15, 100, // Opcode: NMSUB_D32_MM
+/* 4668 */ MCD::OPC_FilterValue, 48, 59, 0, 0, // Skip to: 4732
+/* 4673 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 4676 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4690
+/* 4681 */ MCD::OPC_CheckPredicate, 17, 33, 7, 0, // Skip to: 6511
+/* 4686 */ MCD::OPC_Decode, 197, 10, 104, // Opcode: FADD_D32_MM
+/* 4690 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4704
+/* 4695 */ MCD::OPC_CheckPredicate, 17, 19, 7, 0, // Skip to: 6511
+/* 4700 */ MCD::OPC_Decode, 211, 11, 104, // Opcode: FSUB_D32_MM
+/* 4704 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4718
+/* 4709 */ MCD::OPC_CheckPredicate, 17, 5, 7, 0, // Skip to: 6511
+/* 4714 */ MCD::OPC_Decode, 168, 11, 104, // Opcode: FMUL_D32_MM
+/* 4718 */ MCD::OPC_FilterValue, 7, 252, 6, 0, // Skip to: 6511
+/* 4723 */ MCD::OPC_CheckPredicate, 17, 247, 6, 0, // Skip to: 6511
+/* 4728 */ MCD::OPC_Decode, 235, 10, 104, // Opcode: FDIV_D32_MM
+/* 4732 */ MCD::OPC_FilterValue, 56, 59, 0, 0, // Skip to: 4796
+/* 4737 */ MCD::OPC_ExtractField, 6, 4, // Inst{9-6} ...
+/* 4740 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4754
+/* 4745 */ MCD::OPC_CheckPredicate, 12, 225, 6, 0, // Skip to: 6511
+/* 4750 */ MCD::OPC_Decode, 228, 14, 105, // Opcode: MOVN_I_S_MM
+/* 4754 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4768
+/* 4759 */ MCD::OPC_CheckPredicate, 12, 211, 6, 0, // Skip to: 6511
+/* 4764 */ MCD::OPC_Decode, 248, 14, 105, // Opcode: MOVZ_I_S_MM
+/* 4768 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4782
+/* 4773 */ MCD::OPC_CheckPredicate, 16, 197, 6, 0, // Skip to: 6511
+/* 4778 */ MCD::OPC_Decode, 222, 14, 106, // Opcode: MOVN_I_D32_MM
+/* 4782 */ MCD::OPC_FilterValue, 5, 188, 6, 0, // Skip to: 6511
+/* 4787 */ MCD::OPC_CheckPredicate, 16, 183, 6, 0, // Skip to: 6511
+/* 4792 */ MCD::OPC_Decode, 242, 14, 106, // Opcode: MOVZ_I_D32_MM
+/* 4796 */ MCD::OPC_FilterValue, 59, 91, 2, 0, // Skip to: 5404
+/* 4801 */ MCD::OPC_ExtractField, 6, 7, // Inst{12-6} ...
+/* 4804 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4825
+/* 4809 */ MCD::OPC_CheckPredicate, 18, 161, 6, 0, // Skip to: 6511
+/* 4814 */ MCD::OPC_CheckField, 13, 3, 1, 154, 6, 0, // Skip to: 6511
+/* 4821 */ MCD::OPC_Decode, 135, 14, 107, // Opcode: MFC1_MM
+/* 4825 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4846
+/* 4830 */ MCD::OPC_CheckPredicate, 17, 140, 6, 0, // Skip to: 6511
+/* 4835 */ MCD::OPC_CheckField, 13, 3, 1, 133, 6, 0, // Skip to: 6511
+/* 4842 */ MCD::OPC_Decode, 158, 11, 108, // Opcode: FMOV_D32_MM
+/* 4846 */ MCD::OPC_FilterValue, 4, 31, 0, 0, // Skip to: 4882
+/* 4851 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 4854 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4868
+/* 4859 */ MCD::OPC_CheckPredicate, 19, 111, 6, 0, // Skip to: 6511
+/* 4864 */ MCD::OPC_Decode, 147, 8, 109, // Opcode: CVT_L_S_MM
+/* 4868 */ MCD::OPC_FilterValue, 2, 102, 6, 0, // Skip to: 6511
+/* 4873 */ MCD::OPC_CheckPredicate, 19, 97, 6, 0, // Skip to: 6511
+/* 4878 */ MCD::OPC_Decode, 144, 8, 110, // Opcode: CVT_L_D64_MM
+/* 4882 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4896
+/* 4887 */ MCD::OPC_CheckPredicate, 12, 83, 6, 0, // Skip to: 6511
+/* 4892 */ MCD::OPC_Decode, 214, 14, 111, // Opcode: MOVF_I_MM
+/* 4896 */ MCD::OPC_FilterValue, 8, 31, 0, 0, // Skip to: 4932
+/* 4901 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 4904 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4918
+/* 4909 */ MCD::OPC_CheckPredicate, 20, 61, 6, 0, // Skip to: 6511
+/* 4914 */ MCD::OPC_Decode, 134, 17, 112, // Opcode: RSQRT_S_MM
+/* 4918 */ MCD::OPC_FilterValue, 2, 52, 6, 0, // Skip to: 6511
+/* 4923 */ MCD::OPC_CheckPredicate, 17, 47, 6, 0, // Skip to: 6511
+/* 4928 */ MCD::OPC_Decode, 130, 17, 108, // Opcode: RSQRT_D32_MM
+/* 4932 */ MCD::OPC_FilterValue, 13, 31, 0, 0, // Skip to: 4968
+/* 4937 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 4940 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4954
+/* 4945 */ MCD::OPC_CheckPredicate, 18, 25, 6, 0, // Skip to: 6511
+/* 4950 */ MCD::OPC_Decode, 194, 10, 112, // Opcode: FABS_S_MM
+/* 4954 */ MCD::OPC_FilterValue, 1, 16, 6, 0, // Skip to: 6511
+/* 4959 */ MCD::OPC_CheckPredicate, 17, 11, 6, 0, // Skip to: 6511
+/* 4964 */ MCD::OPC_Decode, 190, 10, 108, // Opcode: FABS_D32_MM
+/* 4968 */ MCD::OPC_FilterValue, 32, 16, 0, 0, // Skip to: 4989
+/* 4973 */ MCD::OPC_CheckPredicate, 18, 253, 5, 0, // Skip to: 6511
+/* 4978 */ MCD::OPC_CheckField, 13, 3, 1, 246, 5, 0, // Skip to: 6511
+/* 4985 */ MCD::OPC_Decode, 150, 15, 113, // Opcode: MTC1_MM
+/* 4989 */ MCD::OPC_FilterValue, 36, 31, 0, 0, // Skip to: 5025
+/* 4994 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 4997 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5011
+/* 5002 */ MCD::OPC_CheckPredicate, 18, 224, 5, 0, // Skip to: 6511
+/* 5007 */ MCD::OPC_Decode, 163, 8, 112, // Opcode: CVT_W_S_MM
+/* 5011 */ MCD::OPC_FilterValue, 2, 215, 5, 0, // Skip to: 6511
+/* 5016 */ MCD::OPC_CheckPredicate, 17, 210, 5, 0, // Skip to: 6511
+/* 5021 */ MCD::OPC_Decode, 159, 8, 114, // Opcode: CVT_W_D32_MM
+/* 5025 */ MCD::OPC_FilterValue, 37, 9, 0, 0, // Skip to: 5039
+/* 5030 */ MCD::OPC_CheckPredicate, 12, 196, 5, 0, // Skip to: 6511
+/* 5035 */ MCD::OPC_Decode, 234, 14, 111, // Opcode: MOVT_I_MM
+/* 5039 */ MCD::OPC_FilterValue, 40, 31, 0, 0, // Skip to: 5075
+/* 5044 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 5047 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5061
+/* 5052 */ MCD::OPC_CheckPredicate, 18, 174, 5, 0, // Skip to: 6511
+/* 5057 */ MCD::OPC_Decode, 207, 11, 112, // Opcode: FSQRT_S_MM
+/* 5061 */ MCD::OPC_FilterValue, 2, 165, 5, 0, // Skip to: 6511
+/* 5066 */ MCD::OPC_CheckPredicate, 17, 160, 5, 0, // Skip to: 6511
+/* 5071 */ MCD::OPC_Decode, 203, 11, 108, // Opcode: FSQRT_D32_MM
+/* 5075 */ MCD::OPC_FilterValue, 44, 59, 0, 0, // Skip to: 5139
+/* 5080 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 5083 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5097
+/* 5088 */ MCD::OPC_CheckPredicate, 18, 138, 5, 0, // Skip to: 6511
+/* 5093 */ MCD::OPC_Decode, 145, 11, 112, // Opcode: FLOOR_W_S_MM
+/* 5097 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5111
+/* 5102 */ MCD::OPC_CheckPredicate, 18, 124, 5, 0, // Skip to: 6511
+/* 5107 */ MCD::OPC_Decode, 161, 20, 112, // Opcode: TRUNC_W_S_MM
+/* 5111 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5125
+/* 5116 */ MCD::OPC_CheckPredicate, 17, 110, 5, 0, // Skip to: 6511
+/* 5121 */ MCD::OPC_Decode, 143, 11, 114, // Opcode: FLOOR_W_MM
+/* 5125 */ MCD::OPC_FilterValue, 3, 101, 5, 0, // Skip to: 6511
+/* 5130 */ MCD::OPC_CheckPredicate, 17, 96, 5, 0, // Skip to: 6511
+/* 5135 */ MCD::OPC_Decode, 159, 20, 114, // Opcode: TRUNC_W_MM
+/* 5139 */ MCD::OPC_FilterValue, 45, 16, 0, 0, // Skip to: 5160
+/* 5144 */ MCD::OPC_CheckPredicate, 17, 82, 5, 0, // Skip to: 6511
+/* 5149 */ MCD::OPC_CheckField, 13, 3, 1, 75, 5, 0, // Skip to: 6511
+/* 5156 */ MCD::OPC_Decode, 176, 11, 108, // Opcode: FNEG_D32_MM
+/* 5160 */ MCD::OPC_FilterValue, 64, 31, 0, 0, // Skip to: 5196
+/* 5165 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 5168 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5182
+/* 5173 */ MCD::OPC_CheckPredicate, 18, 53, 5, 0, // Skip to: 6511
+/* 5178 */ MCD::OPC_Decode, 231, 6, 115, // Opcode: CFC1_MM
+/* 5182 */ MCD::OPC_FilterValue, 1, 44, 5, 0, // Skip to: 6511
+/* 5187 */ MCD::OPC_CheckPredicate, 17, 39, 5, 0, // Skip to: 6511
+/* 5192 */ MCD::OPC_Decode, 143, 14, 116, // Opcode: MFHC1_D32_MM
+/* 5196 */ MCD::OPC_FilterValue, 72, 31, 0, 0, // Skip to: 5232
+/* 5201 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 5204 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5218
+/* 5209 */ MCD::OPC_CheckPredicate, 18, 17, 5, 0, // Skip to: 6511
+/* 5214 */ MCD::OPC_Decode, 229, 16, 112, // Opcode: RECIP_S_MM
+/* 5218 */ MCD::OPC_FilterValue, 2, 8, 5, 0, // Skip to: 6511
+/* 5223 */ MCD::OPC_CheckPredicate, 17, 3, 5, 0, // Skip to: 6511
+/* 5228 */ MCD::OPC_Decode, 225, 16, 108, // Opcode: RECIP_D32_MM
+/* 5232 */ MCD::OPC_FilterValue, 77, 31, 0, 0, // Skip to: 5268
+/* 5237 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 5240 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5254
+/* 5245 */ MCD::OPC_CheckPredicate, 17, 237, 4, 0, // Skip to: 6511
+/* 5250 */ MCD::OPC_Decode, 134, 8, 117, // Opcode: CVT_D32_S_MM
+/* 5254 */ MCD::OPC_FilterValue, 1, 228, 4, 0, // Skip to: 6511
+/* 5259 */ MCD::OPC_CheckPredicate, 17, 223, 4, 0, // Skip to: 6511
+/* 5264 */ MCD::OPC_Decode, 136, 8, 117, // Opcode: CVT_D32_W_MM
+/* 5268 */ MCD::OPC_FilterValue, 96, 31, 0, 0, // Skip to: 5304
+/* 5273 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 5276 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5290
+/* 5281 */ MCD::OPC_CheckPredicate, 18, 201, 4, 0, // Skip to: 6511
+/* 5286 */ MCD::OPC_Decode, 130, 8, 118, // Opcode: CTC1_MM
+/* 5290 */ MCD::OPC_FilterValue, 1, 192, 4, 0, // Skip to: 6511
+/* 5295 */ MCD::OPC_CheckPredicate, 17, 187, 4, 0, // Skip to: 6511
+/* 5300 */ MCD::OPC_Decode, 158, 15, 119, // Opcode: MTHC1_D32_MM
+/* 5304 */ MCD::OPC_FilterValue, 108, 59, 0, 0, // Skip to: 5368
+/* 5309 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 5312 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5326
+/* 5317 */ MCD::OPC_CheckPredicate, 18, 165, 4, 0, // Skip to: 6511
+/* 5322 */ MCD::OPC_Decode, 220, 6, 112, // Opcode: CEIL_W_S_MM
+/* 5326 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5340
+/* 5331 */ MCD::OPC_CheckPredicate, 18, 151, 4, 0, // Skip to: 6511
+/* 5336 */ MCD::OPC_Decode, 255, 16, 112, // Opcode: ROUND_W_S_MM
+/* 5340 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5354
+/* 5345 */ MCD::OPC_CheckPredicate, 17, 137, 4, 0, // Skip to: 6511
+/* 5350 */ MCD::OPC_Decode, 218, 6, 114, // Opcode: CEIL_W_MM
+/* 5354 */ MCD::OPC_FilterValue, 3, 128, 4, 0, // Skip to: 6511
+/* 5359 */ MCD::OPC_CheckPredicate, 17, 123, 4, 0, // Skip to: 6511
+/* 5364 */ MCD::OPC_Decode, 253, 16, 114, // Opcode: ROUND_W_MM
+/* 5368 */ MCD::OPC_FilterValue, 109, 114, 4, 0, // Skip to: 6511
+/* 5373 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 5376 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5390
+/* 5381 */ MCD::OPC_CheckPredicate, 17, 101, 4, 0, // Skip to: 6511
+/* 5386 */ MCD::OPC_Decode, 150, 8, 114, // Opcode: CVT_S_D32_MM
+/* 5390 */ MCD::OPC_FilterValue, 1, 92, 4, 0, // Skip to: 6511
+/* 5395 */ MCD::OPC_CheckPredicate, 18, 87, 4, 0, // Skip to: 6511
+/* 5400 */ MCD::OPC_Decode, 156, 8, 112, // Opcode: CVT_S_W_MM
+/* 5404 */ MCD::OPC_FilterValue, 60, 78, 4, 0, // Skip to: 6511
+/* 5409 */ MCD::OPC_ExtractField, 6, 7, // Inst{12-6} ...
+/* 5412 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5426
+/* 5417 */ MCD::OPC_CheckPredicate, 12, 65, 4, 0, // Skip to: 6511
+/* 5422 */ MCD::OPC_Decode, 176, 8, 120, // Opcode: C_F_S_MM
+/* 5426 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5440
+/* 5431 */ MCD::OPC_CheckPredicate, 12, 51, 4, 0, // Skip to: 6511
+/* 5436 */ MCD::OPC_Decode, 132, 9, 120, // Opcode: C_UN_S_MM
+/* 5440 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5454
+/* 5445 */ MCD::OPC_CheckPredicate, 12, 37, 4, 0, // Skip to: 6511
+/* 5450 */ MCD::OPC_Decode, 170, 8, 120, // Opcode: C_EQ_S_MM
+/* 5454 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 5468
+/* 5459 */ MCD::OPC_CheckPredicate, 12, 23, 4, 0, // Skip to: 6511
+/* 5464 */ MCD::OPC_Decode, 242, 8, 120, // Opcode: C_UEQ_S_MM
+/* 5468 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5482
+/* 5473 */ MCD::OPC_CheckPredicate, 12, 9, 4, 0, // Skip to: 6511
+/* 5478 */ MCD::OPC_Decode, 224, 8, 120, // Opcode: C_OLT_S_MM
+/* 5482 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5496
+/* 5487 */ MCD::OPC_CheckPredicate, 12, 251, 3, 0, // Skip to: 6511
+/* 5492 */ MCD::OPC_Decode, 254, 8, 120, // Opcode: C_ULT_S_MM
+/* 5496 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5510
+/* 5501 */ MCD::OPC_CheckPredicate, 12, 237, 3, 0, // Skip to: 6511
+/* 5506 */ MCD::OPC_Decode, 218, 8, 120, // Opcode: C_OLE_S_MM
+/* 5510 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 5524
+/* 5515 */ MCD::OPC_CheckPredicate, 12, 223, 3, 0, // Skip to: 6511
+/* 5520 */ MCD::OPC_Decode, 248, 8, 120, // Opcode: C_ULE_S_MM
+/* 5524 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 5538
+/* 5529 */ MCD::OPC_CheckPredicate, 12, 209, 3, 0, // Skip to: 6511
+/* 5534 */ MCD::OPC_Decode, 236, 8, 120, // Opcode: C_SF_S_MM
+/* 5538 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 5552
+/* 5543 */ MCD::OPC_CheckPredicate, 12, 195, 3, 0, // Skip to: 6511
+/* 5548 */ MCD::OPC_Decode, 200, 8, 120, // Opcode: C_NGLE_S_MM
+/* 5552 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 5566
+/* 5557 */ MCD::OPC_CheckPredicate, 12, 181, 3, 0, // Skip to: 6511
+/* 5562 */ MCD::OPC_Decode, 230, 8, 120, // Opcode: C_SEQ_S_MM
+/* 5566 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 5580
+/* 5571 */ MCD::OPC_CheckPredicate, 12, 167, 3, 0, // Skip to: 6511
+/* 5576 */ MCD::OPC_Decode, 206, 8, 120, // Opcode: C_NGL_S_MM
+/* 5580 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 5594
+/* 5585 */ MCD::OPC_CheckPredicate, 12, 153, 3, 0, // Skip to: 6511
+/* 5590 */ MCD::OPC_Decode, 188, 8, 120, // Opcode: C_LT_S_MM
+/* 5594 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 5608
+/* 5599 */ MCD::OPC_CheckPredicate, 12, 139, 3, 0, // Skip to: 6511
+/* 5604 */ MCD::OPC_Decode, 194, 8, 120, // Opcode: C_NGE_S_MM
+/* 5608 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 5622
+/* 5613 */ MCD::OPC_CheckPredicate, 12, 125, 3, 0, // Skip to: 6511
+/* 5618 */ MCD::OPC_Decode, 182, 8, 120, // Opcode: C_LE_S_MM
+/* 5622 */ MCD::OPC_FilterValue, 15, 9, 0, 0, // Skip to: 5636
+/* 5627 */ MCD::OPC_CheckPredicate, 12, 111, 3, 0, // Skip to: 6511
+/* 5632 */ MCD::OPC_Decode, 212, 8, 120, // Opcode: C_NGT_S_MM
+/* 5636 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 5650
+/* 5641 */ MCD::OPC_CheckPredicate, 16, 97, 3, 0, // Skip to: 6511
+/* 5646 */ MCD::OPC_Decode, 172, 8, 121, // Opcode: C_F_D32_MM
+/* 5650 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 5664
+/* 5655 */ MCD::OPC_CheckPredicate, 16, 83, 3, 0, // Skip to: 6511
+/* 5660 */ MCD::OPC_Decode, 128, 9, 121, // Opcode: C_UN_D32_MM
+/* 5664 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 5678
+/* 5669 */ MCD::OPC_CheckPredicate, 16, 69, 3, 0, // Skip to: 6511
+/* 5674 */ MCD::OPC_Decode, 166, 8, 121, // Opcode: C_EQ_D32_MM
+/* 5678 */ MCD::OPC_FilterValue, 19, 9, 0, 0, // Skip to: 5692
+/* 5683 */ MCD::OPC_CheckPredicate, 16, 55, 3, 0, // Skip to: 6511
+/* 5688 */ MCD::OPC_Decode, 238, 8, 121, // Opcode: C_UEQ_D32_MM
+/* 5692 */ MCD::OPC_FilterValue, 20, 9, 0, 0, // Skip to: 5706
+/* 5697 */ MCD::OPC_CheckPredicate, 16, 41, 3, 0, // Skip to: 6511
+/* 5702 */ MCD::OPC_Decode, 220, 8, 121, // Opcode: C_OLT_D32_MM
+/* 5706 */ MCD::OPC_FilterValue, 21, 9, 0, 0, // Skip to: 5720
+/* 5711 */ MCD::OPC_CheckPredicate, 16, 27, 3, 0, // Skip to: 6511
+/* 5716 */ MCD::OPC_Decode, 250, 8, 121, // Opcode: C_ULT_D32_MM
+/* 5720 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 5734
+/* 5725 */ MCD::OPC_CheckPredicate, 16, 13, 3, 0, // Skip to: 6511
+/* 5730 */ MCD::OPC_Decode, 214, 8, 121, // Opcode: C_OLE_D32_MM
+/* 5734 */ MCD::OPC_FilterValue, 23, 9, 0, 0, // Skip to: 5748
+/* 5739 */ MCD::OPC_CheckPredicate, 16, 255, 2, 0, // Skip to: 6511
+/* 5744 */ MCD::OPC_Decode, 244, 8, 121, // Opcode: C_ULE_D32_MM
+/* 5748 */ MCD::OPC_FilterValue, 24, 9, 0, 0, // Skip to: 5762
+/* 5753 */ MCD::OPC_CheckPredicate, 16, 241, 2, 0, // Skip to: 6511
+/* 5758 */ MCD::OPC_Decode, 232, 8, 121, // Opcode: C_SF_D32_MM
+/* 5762 */ MCD::OPC_FilterValue, 25, 9, 0, 0, // Skip to: 5776
+/* 5767 */ MCD::OPC_CheckPredicate, 16, 227, 2, 0, // Skip to: 6511
+/* 5772 */ MCD::OPC_Decode, 196, 8, 121, // Opcode: C_NGLE_D32_MM
+/* 5776 */ MCD::OPC_FilterValue, 26, 9, 0, 0, // Skip to: 5790
+/* 5781 */ MCD::OPC_CheckPredicate, 16, 213, 2, 0, // Skip to: 6511
+/* 5786 */ MCD::OPC_Decode, 226, 8, 121, // Opcode: C_SEQ_D32_MM
+/* 5790 */ MCD::OPC_FilterValue, 27, 9, 0, 0, // Skip to: 5804
+/* 5795 */ MCD::OPC_CheckPredicate, 16, 199, 2, 0, // Skip to: 6511
+/* 5800 */ MCD::OPC_Decode, 202, 8, 121, // Opcode: C_NGL_D32_MM
+/* 5804 */ MCD::OPC_FilterValue, 28, 9, 0, 0, // Skip to: 5818
+/* 5809 */ MCD::OPC_CheckPredicate, 16, 185, 2, 0, // Skip to: 6511
+/* 5814 */ MCD::OPC_Decode, 184, 8, 121, // Opcode: C_LT_D32_MM
+/* 5818 */ MCD::OPC_FilterValue, 29, 9, 0, 0, // Skip to: 5832
+/* 5823 */ MCD::OPC_CheckPredicate, 16, 171, 2, 0, // Skip to: 6511
+/* 5828 */ MCD::OPC_Decode, 190, 8, 121, // Opcode: C_NGE_D32_MM
+/* 5832 */ MCD::OPC_FilterValue, 30, 9, 0, 0, // Skip to: 5846
+/* 5837 */ MCD::OPC_CheckPredicate, 16, 157, 2, 0, // Skip to: 6511
+/* 5842 */ MCD::OPC_Decode, 178, 8, 121, // Opcode: C_LE_D32_MM
+/* 5846 */ MCD::OPC_FilterValue, 31, 148, 2, 0, // Skip to: 6511
+/* 5851 */ MCD::OPC_CheckPredicate, 16, 143, 2, 0, // Skip to: 6511
+/* 5856 */ MCD::OPC_Decode, 208, 8, 121, // Opcode: C_NGT_D32_MM
+/* 5860 */ MCD::OPC_FilterValue, 22, 48, 0, 0, // Skip to: 5913
+/* 5865 */ MCD::OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 5868 */ MCD::OPC_FilterValue, 197, 1, 9, 0, 0, // Skip to: 5883
+/* 5874 */ MCD::OPC_CheckPredicate, 7, 120, 2, 0, // Skip to: 6511
+/* 5879 */ MCD::OPC_Decode, 161, 7, 42, // Opcode: CMPGU_EQ_QB_MM
+/* 5883 */ MCD::OPC_FilterValue, 133, 2, 9, 0, 0, // Skip to: 5898
+/* 5889 */ MCD::OPC_CheckPredicate, 7, 105, 2, 0, // Skip to: 6511
+/* 5894 */ MCD::OPC_Decode, 165, 7, 42, // Opcode: CMPGU_LT_QB_MM
+/* 5898 */ MCD::OPC_FilterValue, 197, 2, 95, 2, 0, // Skip to: 6511
+/* 5904 */ MCD::OPC_CheckPredicate, 7, 90, 2, 0, // Skip to: 6511
+/* 5909 */ MCD::OPC_Decode, 163, 7, 42, // Opcode: CMPGU_LE_QB_MM
+/* 5913 */ MCD::OPC_FilterValue, 24, 99, 1, 0, // Skip to: 6273
+/* 5918 */ MCD::OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 5921 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5935
+/* 5926 */ MCD::OPC_CheckPredicate, 5, 68, 2, 0, // Skip to: 6511
+/* 5931 */ MCD::OPC_Decode, 164, 13, 87, // Opcode: LWL_MM
+/* 5935 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5949
+/* 5940 */ MCD::OPC_CheckPredicate, 5, 54, 2, 0, // Skip to: 6511
+/* 5945 */ MCD::OPC_Decode, 175, 13, 87, // Opcode: LWR_MM
+/* 5949 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5963
+/* 5954 */ MCD::OPC_CheckPredicate, 5, 40, 2, 0, // Skip to: 6511
+/* 5959 */ MCD::OPC_Decode, 210, 16, 88, // Opcode: PREF_MM
+/* 5963 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 5977
+/* 5968 */ MCD::OPC_CheckPredicate, 5, 26, 2, 0, // Skip to: 6511
+/* 5973 */ MCD::OPC_Decode, 133, 13, 87, // Opcode: LL_MM
+/* 5977 */ MCD::OPC_FilterValue, 6, 115, 0, 0, // Skip to: 6097
+/* 5982 */ MCD::OPC_ExtractField, 9, 3, // Inst{11-9} ...
+/* 5985 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5999
+/* 5990 */ MCD::OPC_CheckPredicate, 21, 4, 2, 0, // Skip to: 6511
+/* 5995 */ MCD::OPC_Decode, 212, 12, 122, // Opcode: LBuE_MM
+/* 5999 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6013
+/* 6004 */ MCD::OPC_CheckPredicate, 21, 246, 1, 0, // Skip to: 6511
+/* 6009 */ MCD::OPC_Decode, 250, 12, 122, // Opcode: LHuE_MM
+/* 6013 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6027
+/* 6018 */ MCD::OPC_CheckPredicate, 22, 232, 1, 0, // Skip to: 6511
+/* 6023 */ MCD::OPC_Decode, 163, 13, 122, // Opcode: LWLE_MM
+/* 6027 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 6041
+/* 6032 */ MCD::OPC_CheckPredicate, 22, 218, 1, 0, // Skip to: 6511
+/* 6037 */ MCD::OPC_Decode, 174, 13, 122, // Opcode: LWRE_MM
+/* 6041 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 6055
+/* 6046 */ MCD::OPC_CheckPredicate, 21, 204, 1, 0, // Skip to: 6511
+/* 6051 */ MCD::OPC_Decode, 202, 12, 122, // Opcode: LBE_MM
+/* 6055 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 6069
+/* 6060 */ MCD::OPC_CheckPredicate, 21, 190, 1, 0, // Skip to: 6511
+/* 6065 */ MCD::OPC_Decode, 242, 12, 122, // Opcode: LHE_MM
+/* 6069 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 6083
+/* 6074 */ MCD::OPC_CheckPredicate, 21, 176, 1, 0, // Skip to: 6511
+/* 6079 */ MCD::OPC_Decode, 132, 13, 122, // Opcode: LLE_MM
+/* 6083 */ MCD::OPC_FilterValue, 7, 167, 1, 0, // Skip to: 6511
+/* 6088 */ MCD::OPC_CheckPredicate, 21, 162, 1, 0, // Skip to: 6511
+/* 6093 */ MCD::OPC_Decode, 158, 13, 122, // Opcode: LWE_MM
+/* 6097 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6111
+/* 6102 */ MCD::OPC_CheckPredicate, 5, 148, 1, 0, // Skip to: 6511
+/* 6107 */ MCD::OPC_Decode, 188, 19, 87, // Opcode: SWL_MM
+/* 6111 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6125
+/* 6116 */ MCD::OPC_CheckPredicate, 5, 134, 1, 0, // Skip to: 6511
+/* 6121 */ MCD::OPC_Decode, 197, 19, 87, // Opcode: SWR_MM
+/* 6125 */ MCD::OPC_FilterValue, 10, 115, 0, 0, // Skip to: 6245
+/* 6130 */ MCD::OPC_ExtractField, 9, 3, // Inst{11-9} ...
+/* 6133 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6147
+/* 6138 */ MCD::OPC_CheckPredicate, 22, 112, 1, 0, // Skip to: 6511
+/* 6143 */ MCD::OPC_Decode, 187, 19, 122, // Opcode: SWLE_MM
+/* 6147 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6161
+/* 6152 */ MCD::OPC_CheckPredicate, 22, 98, 1, 0, // Skip to: 6511
+/* 6157 */ MCD::OPC_Decode, 196, 19, 122, // Opcode: SWRE_MM
+/* 6161 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6175
+/* 6166 */ MCD::OPC_CheckPredicate, 21, 84, 1, 0, // Skip to: 6511
+/* 6171 */ MCD::OPC_Decode, 208, 16, 123, // Opcode: PREFE_MM
+/* 6175 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 6189
+/* 6180 */ MCD::OPC_CheckPredicate, 21, 70, 1, 0, // Skip to: 6511
+/* 6185 */ MCD::OPC_Decode, 207, 6, 123, // Opcode: CACHEE_MM
+/* 6189 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 6203
+/* 6194 */ MCD::OPC_CheckPredicate, 21, 56, 1, 0, // Skip to: 6511
+/* 6199 */ MCD::OPC_Decode, 150, 17, 122, // Opcode: SBE_MM
+/* 6203 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 6217
+/* 6208 */ MCD::OPC_CheckPredicate, 21, 42, 1, 0, // Skip to: 6511
+/* 6213 */ MCD::OPC_Decode, 215, 17, 122, // Opcode: SHE_MM
+/* 6217 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 6231
+/* 6222 */ MCD::OPC_CheckPredicate, 21, 28, 1, 0, // Skip to: 6511
+/* 6227 */ MCD::OPC_Decode, 159, 17, 122, // Opcode: SCE_MM
+/* 6231 */ MCD::OPC_FilterValue, 7, 19, 1, 0, // Skip to: 6511
+/* 6236 */ MCD::OPC_CheckPredicate, 21, 14, 1, 0, // Skip to: 6511
+/* 6241 */ MCD::OPC_Decode, 183, 19, 122, // Opcode: SWE_MM
+/* 6245 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6259
+/* 6250 */ MCD::OPC_CheckPredicate, 5, 0, 1, 0, // Skip to: 6511
+/* 6255 */ MCD::OPC_Decode, 160, 17, 87, // Opcode: SC_MM
+/* 6259 */ MCD::OPC_FilterValue, 14, 247, 0, 0, // Skip to: 6511
+/* 6264 */ MCD::OPC_CheckPredicate, 5, 242, 0, 0, // Skip to: 6511
+/* 6269 */ MCD::OPC_Decode, 178, 13, 87, // Opcode: LWU_MM
+/* 6273 */ MCD::OPC_FilterValue, 28, 9, 0, 0, // Skip to: 6287
+/* 6278 */ MCD::OPC_CheckPredicate, 5, 228, 0, 0, // Skip to: 6511
+/* 6283 */ MCD::OPC_Decode, 193, 20, 96, // Opcode: XORi_MM
+/* 6287 */ MCD::OPC_FilterValue, 29, 9, 0, 0, // Skip to: 6301
+/* 6292 */ MCD::OPC_CheckPredicate, 5, 214, 0, 0, // Skip to: 6511
+/* 6297 */ MCD::OPC_Decode, 170, 12, 124, // Opcode: JALS_MM
+/* 6301 */ MCD::OPC_FilterValue, 30, 9, 0, 0, // Skip to: 6315
+/* 6306 */ MCD::OPC_CheckPredicate, 5, 200, 0, 0, // Skip to: 6511
+/* 6311 */ MCD::OPC_Decode, 135, 4, 125, // Opcode: ADDIUPC_MM
+/* 6315 */ MCD::OPC_FilterValue, 36, 9, 0, 0, // Skip to: 6329
+/* 6320 */ MCD::OPC_CheckPredicate, 6, 186, 0, 0, // Skip to: 6511
+/* 6325 */ MCD::OPC_Decode, 171, 18, 85, // Opcode: SLTi_MM
+/* 6329 */ MCD::OPC_FilterValue, 37, 9, 0, 0, // Skip to: 6343
+/* 6334 */ MCD::OPC_CheckPredicate, 5, 172, 0, 0, // Skip to: 6511
+/* 6339 */ MCD::OPC_Decode, 186, 5, 126, // Opcode: BEQ_MM
+/* 6343 */ MCD::OPC_FilterValue, 38, 9, 0, 0, // Skip to: 6357
+/* 6348 */ MCD::OPC_CheckPredicate, 18, 158, 0, 0, // Skip to: 6511
+/* 6353 */ MCD::OPC_Decode, 175, 19, 127, // Opcode: SWC1_MM
+/* 6357 */ MCD::OPC_FilterValue, 39, 9, 0, 0, // Skip to: 6371
+/* 6362 */ MCD::OPC_CheckPredicate, 18, 144, 0, 0, // Skip to: 6511
+/* 6367 */ MCD::OPC_Decode, 150, 13, 127, // Opcode: LWC1_MM
+/* 6371 */ MCD::OPC_FilterValue, 44, 9, 0, 0, // Skip to: 6385
+/* 6376 */ MCD::OPC_CheckPredicate, 6, 130, 0, 0, // Skip to: 6511
+/* 6381 */ MCD::OPC_Decode, 174, 18, 85, // Opcode: SLTiu_MM
+/* 6385 */ MCD::OPC_FilterValue, 45, 9, 0, 0, // Skip to: 6399
+/* 6390 */ MCD::OPC_CheckPredicate, 5, 116, 0, 0, // Skip to: 6511
+/* 6395 */ MCD::OPC_Decode, 161, 6, 126, // Opcode: BNE_MM
+/* 6399 */ MCD::OPC_FilterValue, 46, 9, 0, 0, // Skip to: 6413
+/* 6404 */ MCD::OPC_CheckPredicate, 17, 102, 0, 0, // Skip to: 6511
+/* 6409 */ MCD::OPC_Decode, 173, 17, 127, // Opcode: SDC1_MM
+/* 6413 */ MCD::OPC_FilterValue, 47, 9, 0, 0, // Skip to: 6427
+/* 6418 */ MCD::OPC_CheckPredicate, 17, 88, 0, 0, // Skip to: 6511
+/* 6423 */ MCD::OPC_Decode, 218, 12, 127, // Opcode: LDC1_MM
+/* 6427 */ MCD::OPC_FilterValue, 52, 9, 0, 0, // Skip to: 6441
+/* 6432 */ MCD::OPC_CheckPredicate, 5, 74, 0, 0, // Skip to: 6511
+/* 6437 */ MCD::OPC_Decode, 224, 4, 96, // Opcode: ANDi_MM
+/* 6441 */ MCD::OPC_FilterValue, 53, 9, 0, 0, // Skip to: 6455
+/* 6446 */ MCD::OPC_CheckPredicate, 5, 60, 0, 0, // Skip to: 6511
+/* 6451 */ MCD::OPC_Decode, 192, 12, 124, // Opcode: J_MM
+/* 6455 */ MCD::OPC_FilterValue, 60, 9, 0, 0, // Skip to: 6469
+/* 6460 */ MCD::OPC_CheckPredicate, 5, 46, 0, 0, // Skip to: 6511
+/* 6465 */ MCD::OPC_Decode, 172, 12, 124, // Opcode: JALX_MM
+/* 6469 */ MCD::OPC_FilterValue, 61, 9, 0, 0, // Skip to: 6483
+/* 6474 */ MCD::OPC_CheckPredicate, 5, 32, 0, 0, // Skip to: 6511
+/* 6479 */ MCD::OPC_Decode, 173, 12, 124, // Opcode: JAL_MM
+/* 6483 */ MCD::OPC_FilterValue, 62, 9, 0, 0, // Skip to: 6497
+/* 6488 */ MCD::OPC_CheckPredicate, 6, 18, 0, 0, // Skip to: 6511
+/* 6493 */ MCD::OPC_Decode, 202, 19, 86, // Opcode: SW_MM
+/* 6497 */ MCD::OPC_FilterValue, 63, 9, 0, 0, // Skip to: 6511
+/* 6502 */ MCD::OPC_CheckPredicate, 6, 4, 0, 0, // Skip to: 6511
+/* 6507 */ MCD::OPC_Decode, 184, 13, 86, // Opcode: LW_MM
+/* 6511 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMipsDSP32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 62, 10, 0, 0, // Skip to: 18
+/* 8 */ MCD::OPC_CheckPredicate, 7, 20, 0, 0, // Skip to: 33
+/* 13 */ MCD::OPC_Decode, 181, 19, 128, 1, // Opcode: SWDSP_MM
+/* 18 */ MCD::OPC_FilterValue, 63, 10, 0, 0, // Skip to: 33
+/* 23 */ MCD::OPC_CheckPredicate, 7, 5, 0, 0, // Skip to: 33
+/* 28 */ MCD::OPC_Decode, 156, 13, 128, 1, // Opcode: LWDSP_MM
+/* 33 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMipsFP6432[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 21, 24, 1, 0, // Skip to: 288
+/* 8 */ MCD::OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 11 */ MCD::OPC_FilterValue, 59, 33, 0, 0, // Skip to: 49
+/* 16 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 19 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 34
+/* 24 */ MCD::OPC_CheckPredicate, 19, 31, 1, 0, // Skip to: 316
+/* 29 */ MCD::OPC_Decode, 145, 14, 129, 1, // Opcode: MFHC1_D64_MM
+/* 34 */ MCD::OPC_FilterValue, 7, 21, 1, 0, // Skip to: 316
+/* 39 */ MCD::OPC_CheckPredicate, 19, 16, 1, 0, // Skip to: 316
+/* 44 */ MCD::OPC_Decode, 160, 15, 130, 1, // Opcode: MTHC1_D64_MM
+/* 49 */ MCD::OPC_FilterValue, 123, 16, 0, 0, // Skip to: 70
+/* 54 */ MCD::OPC_CheckPredicate, 19, 1, 1, 0, // Skip to: 316
+/* 59 */ MCD::OPC_CheckField, 11, 5, 4, 250, 0, 0, // Skip to: 316
+/* 66 */ MCD::OPC_Decode, 160, 11, 110, // Opcode: FMOV_D64_MM
+/* 70 */ MCD::OPC_FilterValue, 176, 2, 10, 0, 0, // Skip to: 86
+/* 76 */ MCD::OPC_CheckPredicate, 19, 235, 0, 0, // Skip to: 316
+/* 81 */ MCD::OPC_Decode, 199, 10, 131, 1, // Opcode: FADD_D64_MM
+/* 86 */ MCD::OPC_FilterValue, 187, 2, 17, 0, 0, // Skip to: 109
+/* 92 */ MCD::OPC_CheckPredicate, 19, 219, 0, 0, // Skip to: 316
+/* 97 */ MCD::OPC_CheckField, 11, 5, 9, 212, 0, 0, // Skip to: 316
+/* 104 */ MCD::OPC_Decode, 161, 8, 132, 1, // Opcode: CVT_W_D64_MM
+/* 109 */ MCD::OPC_FilterValue, 240, 2, 10, 0, 0, // Skip to: 125
+/* 115 */ MCD::OPC_CheckPredicate, 19, 196, 0, 0, // Skip to: 316
+/* 120 */ MCD::OPC_Decode, 213, 11, 131, 1, // Opcode: FSUB_D64_MM
+/* 125 */ MCD::OPC_FilterValue, 176, 3, 10, 0, 0, // Skip to: 141
+/* 131 */ MCD::OPC_CheckPredicate, 19, 180, 0, 0, // Skip to: 316
+/* 136 */ MCD::OPC_Decode, 170, 11, 131, 1, // Opcode: FMUL_D64_MM
+/* 141 */ MCD::OPC_FilterValue, 240, 3, 10, 0, 0, // Skip to: 157
+/* 147 */ MCD::OPC_CheckPredicate, 19, 164, 0, 0, // Skip to: 316
+/* 152 */ MCD::OPC_Decode, 237, 10, 131, 1, // Opcode: FDIV_D64_MM
+/* 157 */ MCD::OPC_FilterValue, 187, 4, 45, 0, 0, // Skip to: 208
+/* 163 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 166 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 180
+/* 171 */ MCD::OPC_CheckPredicate, 19, 140, 0, 0, // Skip to: 316
+/* 176 */ MCD::OPC_Decode, 132, 17, 110, // Opcode: RSQRT_D64_MM
+/* 180 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 194
+/* 185 */ MCD::OPC_CheckPredicate, 19, 126, 0, 0, // Skip to: 316
+/* 190 */ MCD::OPC_Decode, 205, 11, 110, // Opcode: FSQRT_D64_MM
+/* 194 */ MCD::OPC_FilterValue, 10, 117, 0, 0, // Skip to: 316
+/* 199 */ MCD::OPC_CheckPredicate, 19, 112, 0, 0, // Skip to: 316
+/* 204 */ MCD::OPC_Decode, 227, 16, 110, // Opcode: RECIP_D64_MM
+/* 208 */ MCD::OPC_FilterValue, 251, 6, 102, 0, 0, // Skip to: 316
+/* 214 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 217 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 231
+/* 222 */ MCD::OPC_CheckPredicate, 19, 89, 0, 0, // Skip to: 316
+/* 227 */ MCD::OPC_Decode, 139, 8, 109, // Opcode: CVT_D64_S_MM
+/* 231 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 246
+/* 236 */ MCD::OPC_CheckPredicate, 19, 75, 0, 0, // Skip to: 316
+/* 241 */ MCD::OPC_Decode, 152, 8, 132, 1, // Opcode: CVT_S_D64_MM
+/* 246 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 260
+/* 251 */ MCD::OPC_CheckPredicate, 19, 60, 0, 0, // Skip to: 316
+/* 256 */ MCD::OPC_Decode, 192, 10, 110, // Opcode: FABS_D64_MM
+/* 260 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 274
+/* 265 */ MCD::OPC_CheckPredicate, 19, 46, 0, 0, // Skip to: 316
+/* 270 */ MCD::OPC_Decode, 178, 11, 110, // Opcode: FNEG_D64_MM
+/* 274 */ MCD::OPC_FilterValue, 6, 37, 0, 0, // Skip to: 316
+/* 279 */ MCD::OPC_CheckPredicate, 19, 32, 0, 0, // Skip to: 316
+/* 284 */ MCD::OPC_Decode, 141, 8, 109, // Opcode: CVT_D64_W_MM
+/* 288 */ MCD::OPC_FilterValue, 46, 9, 0, 0, // Skip to: 302
+/* 293 */ MCD::OPC_CheckPredicate, 23, 18, 0, 0, // Skip to: 316
+/* 298 */ MCD::OPC_Decode, 172, 17, 127, // Opcode: SDC1_D64_MMR6
+/* 302 */ MCD::OPC_FilterValue, 47, 9, 0, 0, // Skip to: 316
+/* 307 */ MCD::OPC_CheckPredicate, 23, 4, 0, 0, // Skip to: 316
+/* 312 */ MCD::OPC_Decode, 217, 12, 127, // Opcode: LDC1_D64_MMR6
+/* 316 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMipsR616[] = {
+/* 0 */ MCD::OPC_ExtractField, 10, 6, // Inst{15-10} ...
+/* 3 */ MCD::OPC_FilterValue, 1, 33, 0, 0, // Skip to: 41
+/* 8 */ MCD::OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26
+/* 16 */ MCD::OPC_CheckPredicate, 24, 174, 1, 0, // Skip to: 451
+/* 21 */ MCD::OPC_Decode, 171, 4, 133, 1, // Opcode: ADDU16_MMR6
+/* 26 */ MCD::OPC_FilterValue, 1, 164, 1, 0, // Skip to: 451
+/* 31 */ MCD::OPC_CheckPredicate, 24, 159, 1, 0, // Skip to: 451
+/* 36 */ MCD::OPC_Decode, 141, 19, 133, 1, // Opcode: SUBU16_MMR6
+/* 41 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55
+/* 46 */ MCD::OPC_CheckPredicate, 24, 144, 1, 0, // Skip to: 451
+/* 51 */ MCD::OPC_Decode, 205, 14, 21, // Opcode: MOVE16_MMR6
+/* 55 */ MCD::OPC_FilterValue, 9, 31, 0, 0, // Skip to: 91
+/* 60 */ MCD::OPC_ExtractField, 0, 1, // Inst{0} ...
+/* 63 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 77
+/* 68 */ MCD::OPC_CheckPredicate, 24, 122, 1, 0, // Skip to: 451
+/* 73 */ MCD::OPC_Decode, 151, 18, 22, // Opcode: SLL16_MMR6
+/* 77 */ MCD::OPC_FilterValue, 1, 113, 1, 0, // Skip to: 451
+/* 82 */ MCD::OPC_CheckPredicate, 24, 108, 1, 0, // Skip to: 451
+/* 87 */ MCD::OPC_Decode, 210, 18, 22, // Opcode: SRL16_MMR6
+/* 91 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 105
+/* 96 */ MCD::OPC_CheckPredicate, 24, 94, 1, 0, // Skip to: 451
+/* 101 */ MCD::OPC_Decode, 216, 4, 23, // Opcode: ANDI16_MMR6
+/* 105 */ MCD::OPC_FilterValue, 17, 229, 0, 0, // Skip to: 339
+/* 110 */ MCD::OPC_ExtractField, 2, 1, // Inst{2} ...
+/* 113 */ MCD::OPC_FilterValue, 0, 206, 0, 0, // Skip to: 324
+/* 118 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 121 */ MCD::OPC_FilterValue, 0, 33, 0, 0, // Skip to: 159
+/* 126 */ MCD::OPC_ExtractField, 3, 1, // Inst{3} ...
+/* 129 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 144
+/* 134 */ MCD::OPC_CheckPredicate, 24, 56, 1, 0, // Skip to: 451
+/* 139 */ MCD::OPC_Decode, 134, 16, 134, 1, // Opcode: NOT16_MMR6
+/* 144 */ MCD::OPC_FilterValue, 1, 46, 1, 0, // Skip to: 451
+/* 149 */ MCD::OPC_CheckPredicate, 24, 41, 1, 0, // Skip to: 451
+/* 154 */ MCD::OPC_Decode, 184, 20, 135, 1, // Opcode: XOR16_MMR6
+/* 159 */ MCD::OPC_FilterValue, 1, 33, 0, 0, // Skip to: 197
+/* 164 */ MCD::OPC_ExtractField, 3, 1, // Inst{3} ...
+/* 167 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 182
+/* 172 */ MCD::OPC_CheckPredicate, 24, 18, 1, 0, // Skip to: 451
+/* 177 */ MCD::OPC_Decode, 213, 4, 135, 1, // Opcode: AND16_MMR6
+/* 182 */ MCD::OPC_FilterValue, 1, 8, 1, 0, // Skip to: 451
+/* 187 */ MCD::OPC_CheckPredicate, 24, 3, 1, 0, // Skip to: 451
+/* 192 */ MCD::OPC_Decode, 139, 16, 135, 1, // Opcode: OR16_MMR6
+/* 197 */ MCD::OPC_FilterValue, 2, 31, 0, 0, // Skip to: 233
+/* 202 */ MCD::OPC_ExtractField, 3, 1, // Inst{3} ...
+/* 205 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 219
+/* 210 */ MCD::OPC_CheckPredicate, 24, 236, 0, 0, // Skip to: 451
+/* 215 */ MCD::OPC_Decode, 166, 13, 26, // Opcode: LWM16_MMR6
+/* 219 */ MCD::OPC_FilterValue, 1, 227, 0, 0, // Skip to: 451
+/* 224 */ MCD::OPC_CheckPredicate, 24, 222, 0, 0, // Skip to: 451
+/* 229 */ MCD::OPC_Decode, 190, 19, 26, // Opcode: SWM16_MMR6
+/* 233 */ MCD::OPC_FilterValue, 3, 213, 0, 0, // Skip to: 451
+/* 238 */ MCD::OPC_ExtractField, 3, 2, // Inst{4-3} ...
+/* 241 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 256
+/* 246 */ MCD::OPC_CheckPredicate, 24, 200, 0, 0, // Skip to: 451
+/* 251 */ MCD::OPC_Decode, 185, 12, 136, 1, // Opcode: JRC16_MMR6
+/* 256 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 271
+/* 261 */ MCD::OPC_CheckPredicate, 24, 185, 0, 0, // Skip to: 451
+/* 266 */ MCD::OPC_Decode, 162, 12, 136, 1, // Opcode: JALRC16_MMR6
+/* 271 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 286
+/* 276 */ MCD::OPC_CheckPredicate, 24, 170, 0, 0, // Skip to: 451
+/* 281 */ MCD::OPC_Decode, 186, 12, 137, 1, // Opcode: JRCADDIUSP_MMR6
+/* 286 */ MCD::OPC_FilterValue, 3, 160, 0, 0, // Skip to: 451
+/* 291 */ MCD::OPC_ExtractField, 5, 1, // Inst{5} ...
+/* 294 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 309
+/* 299 */ MCD::OPC_CheckPredicate, 24, 147, 0, 0, // Skip to: 451
+/* 304 */ MCD::OPC_Decode, 176, 6, 138, 1, // Opcode: BREAK16_MMR6
+/* 309 */ MCD::OPC_FilterValue, 1, 137, 0, 0, // Skip to: 451
+/* 314 */ MCD::OPC_CheckPredicate, 24, 132, 0, 0, // Skip to: 451
+/* 319 */ MCD::OPC_Decode, 166, 17, 138, 1, // Opcode: SDBBP16_MMR6
+/* 324 */ MCD::OPC_FilterValue, 1, 122, 0, 0, // Skip to: 451
+/* 329 */ MCD::OPC_CheckPredicate, 24, 117, 0, 0, // Skip to: 451
+/* 334 */ MCD::OPC_Decode, 207, 14, 139, 1, // Opcode: MOVEP_MMR6
+/* 339 */ MCD::OPC_FilterValue, 34, 9, 0, 0, // Skip to: 353
+/* 344 */ MCD::OPC_CheckPredicate, 24, 102, 0, 0, // Skip to: 451
+/* 349 */ MCD::OPC_Decode, 147, 17, 20, // Opcode: SB16_MMR6
+/* 353 */ MCD::OPC_FilterValue, 35, 9, 0, 0, // Skip to: 367
+/* 358 */ MCD::OPC_CheckPredicate, 24, 88, 0, 0, // Skip to: 451
+/* 363 */ MCD::OPC_Decode, 182, 5, 37, // Opcode: BEQZC16_MMR6
+/* 367 */ MCD::OPC_FilterValue, 42, 9, 0, 0, // Skip to: 381
+/* 372 */ MCD::OPC_CheckPredicate, 24, 74, 0, 0, // Skip to: 451
+/* 377 */ MCD::OPC_Decode, 212, 17, 20, // Opcode: SH16_MMR6
+/* 381 */ MCD::OPC_FilterValue, 43, 9, 0, 0, // Skip to: 395
+/* 386 */ MCD::OPC_CheckPredicate, 24, 60, 0, 0, // Skip to: 451
+/* 391 */ MCD::OPC_Decode, 157, 6, 37, // Opcode: BNEZC16_MMR6
+/* 395 */ MCD::OPC_FilterValue, 50, 9, 0, 0, // Skip to: 409
+/* 400 */ MCD::OPC_CheckPredicate, 24, 46, 0, 0, // Skip to: 451
+/* 405 */ MCD::OPC_Decode, 199, 19, 30, // Opcode: SWSP_MMR6
+/* 409 */ MCD::OPC_FilterValue, 51, 9, 0, 0, // Skip to: 423
+/* 414 */ MCD::OPC_CheckPredicate, 24, 32, 0, 0, // Skip to: 451
+/* 419 */ MCD::OPC_Decode, 148, 5, 38, // Opcode: BC16_MMR6
+/* 423 */ MCD::OPC_FilterValue, 58, 9, 0, 0, // Skip to: 437
+/* 428 */ MCD::OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 451
+/* 433 */ MCD::OPC_Decode, 172, 19, 20, // Opcode: SW16_MMR6
+/* 437 */ MCD::OPC_FilterValue, 59, 9, 0, 0, // Skip to: 451
+/* 442 */ MCD::OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 451
+/* 447 */ MCD::OPC_Decode, 253, 12, 39, // Opcode: LI16_MMR6
+/* 451 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMipsR632[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 76, 4, 0, // Skip to: 1108
+/* 8 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 112, 0, 0, // Skip to: 128
+/* 16 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 19 */ MCD::OPC_FilterValue, 0, 54, 0, 0, // Skip to: 78
+/* 24 */ MCD::OPC_ExtractField, 11, 15, // Inst{25-11} ...
+/* 27 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41
+/* 32 */ MCD::OPC_CheckPredicate, 24, 32, 0, 0, // Skip to: 69
+/* 37 */ MCD::OPC_Decode, 232, 18, 0, // Opcode: SSNOP_MMR6
+/* 41 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55
+/* 46 */ MCD::OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 69
+/* 51 */ MCD::OPC_Decode, 147, 10, 0, // Opcode: EHB_MMR6
+/* 55 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69
+/* 60 */ MCD::OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 69
+/* 65 */ MCD::OPC_Decode, 154, 16, 0, // Opcode: PAUSE_MMR6
+/* 69 */ MCD::OPC_CheckPredicate, 24, 40, 12, 0, // Skip to: 3186
+/* 74 */ MCD::OPC_Decode, 164, 18, 40, // Opcode: SLL_MMR6
+/* 78 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 92
+/* 83 */ MCD::OPC_CheckPredicate, 24, 26, 12, 0, // Skip to: 3186
+/* 88 */ MCD::OPC_Decode, 194, 17, 43, // Opcode: SELEQZ_MMR6
+/* 92 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 106
+/* 97 */ MCD::OPC_CheckPredicate, 24, 12, 12, 0, // Skip to: 3186
+/* 102 */ MCD::OPC_Decode, 201, 17, 43, // Opcode: SELNEZ_MMR6
+/* 106 */ MCD::OPC_FilterValue, 7, 3, 12, 0, // Skip to: 3186
+/* 111 */ MCD::OPC_CheckPredicate, 24, 254, 11, 0, // Skip to: 3186
+/* 116 */ MCD::OPC_CheckField, 14, 2, 0, 247, 11, 0, // Skip to: 3186
+/* 123 */ MCD::OPC_Decode, 222, 16, 140, 1, // Opcode: RDHWR_MMR6
+/* 128 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 142
+/* 133 */ MCD::OPC_CheckPredicate, 24, 232, 11, 0, // Skip to: 3186
+/* 138 */ MCD::OPC_Decode, 178, 6, 44, // Opcode: BREAK_MMR6
+/* 142 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 156
+/* 147 */ MCD::OPC_CheckPredicate, 24, 218, 11, 0, // Skip to: 3186
+/* 152 */ MCD::OPC_Decode, 156, 12, 45, // Opcode: INS_MMR6
+/* 156 */ MCD::OPC_FilterValue, 15, 17, 0, 0, // Skip to: 178
+/* 161 */ MCD::OPC_CheckPredicate, 24, 204, 11, 0, // Skip to: 3186
+/* 166 */ MCD::OPC_CheckField, 6, 3, 0, 197, 11, 0, // Skip to: 3186
+/* 173 */ MCD::OPC_Decode, 137, 13, 141, 1, // Opcode: LSA_MMR6
+/* 178 */ MCD::OPC_FilterValue, 16, 136, 0, 0, // Skip to: 319
+/* 183 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 186 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 207
+/* 191 */ MCD::OPC_CheckPredicate, 24, 174, 11, 0, // Skip to: 3186
+/* 196 */ MCD::OPC_CheckField, 16, 5, 0, 167, 11, 0, // Skip to: 3186
+/* 203 */ MCD::OPC_Decode, 152, 7, 14, // Opcode: CLZ_MMR6
+/* 207 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 221
+/* 212 */ MCD::OPC_CheckPredicate, 24, 153, 11, 0, // Skip to: 3186
+/* 217 */ MCD::OPC_Decode, 200, 4, 43, // Opcode: ADD_MMR6
+/* 221 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 235
+/* 226 */ MCD::OPC_CheckPredicate, 24, 139, 11, 0, // Skip to: 3186
+/* 231 */ MCD::OPC_Decode, 176, 4, 43, // Opcode: ADDU_MMR6
+/* 235 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 249
+/* 240 */ MCD::OPC_CheckPredicate, 24, 125, 11, 0, // Skip to: 3186
+/* 245 */ MCD::OPC_Decode, 164, 19, 43, // Opcode: SUB_MMR6
+/* 249 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 263
+/* 254 */ MCD::OPC_CheckPredicate, 24, 111, 11, 0, // Skip to: 3186
+/* 259 */ MCD::OPC_Decode, 146, 19, 43, // Opcode: SUBU_MMR6
+/* 263 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 277
+/* 268 */ MCD::OPC_CheckPredicate, 24, 97, 11, 0, // Skip to: 3186
+/* 273 */ MCD::OPC_Decode, 220, 4, 43, // Opcode: AND_MMR6
+/* 277 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 291
+/* 282 */ MCD::OPC_CheckPredicate, 24, 83, 11, 0, // Skip to: 3186
+/* 287 */ MCD::OPC_Decode, 144, 16, 43, // Opcode: OR_MMR6
+/* 291 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 305
+/* 296 */ MCD::OPC_CheckPredicate, 24, 69, 11, 0, // Skip to: 3186
+/* 301 */ MCD::OPC_Decode, 131, 16, 43, // Opcode: NOR_MMR6
+/* 305 */ MCD::OPC_FilterValue, 12, 60, 11, 0, // Skip to: 3186
+/* 310 */ MCD::OPC_CheckPredicate, 24, 55, 11, 0, // Skip to: 3186
+/* 315 */ MCD::OPC_Decode, 189, 20, 43, // Opcode: XOR_MMR6
+/* 319 */ MCD::OPC_FilterValue, 24, 115, 0, 0, // Skip to: 439
+/* 324 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 327 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 341
+/* 332 */ MCD::OPC_CheckPredicate, 24, 33, 11, 0, // Skip to: 3186
+/* 337 */ MCD::OPC_Decode, 225, 15, 43, // Opcode: MUL_MMR6
+/* 341 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 355
+/* 346 */ MCD::OPC_CheckPredicate, 24, 19, 11, 0, // Skip to: 3186
+/* 351 */ MCD::OPC_Decode, 186, 15, 43, // Opcode: MUH_MMR6
+/* 355 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 369
+/* 360 */ MCD::OPC_CheckPredicate, 24, 5, 11, 0, // Skip to: 3186
+/* 365 */ MCD::OPC_Decode, 219, 15, 43, // Opcode: MULU_MMR6
+/* 369 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 383
+/* 374 */ MCD::OPC_CheckPredicate, 24, 247, 10, 0, // Skip to: 3186
+/* 379 */ MCD::OPC_Decode, 185, 15, 43, // Opcode: MUHU_MMR6
+/* 383 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 397
+/* 388 */ MCD::OPC_CheckPredicate, 24, 233, 10, 0, // Skip to: 3186
+/* 393 */ MCD::OPC_Decode, 165, 9, 43, // Opcode: DIV_MMR6
+/* 397 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 411
+/* 402 */ MCD::OPC_CheckPredicate, 24, 219, 10, 0, // Skip to: 3186
+/* 407 */ MCD::OPC_Decode, 195, 14, 43, // Opcode: MOD_MMR6
+/* 411 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 425
+/* 416 */ MCD::OPC_CheckPredicate, 24, 205, 10, 0, // Skip to: 3186
+/* 421 */ MCD::OPC_Decode, 164, 9, 43, // Opcode: DIVU_MMR6
+/* 425 */ MCD::OPC_FilterValue, 7, 196, 10, 0, // Skip to: 3186
+/* 430 */ MCD::OPC_CheckPredicate, 24, 191, 10, 0, // Skip to: 3186
+/* 435 */ MCD::OPC_Decode, 194, 14, 43, // Opcode: MODU_MMR6
+/* 439 */ MCD::OPC_FilterValue, 31, 17, 0, 0, // Skip to: 461
+/* 444 */ MCD::OPC_CheckPredicate, 24, 177, 10, 0, // Skip to: 3186
+/* 449 */ MCD::OPC_CheckField, 6, 3, 0, 170, 10, 0, // Skip to: 3186
+/* 456 */ MCD::OPC_Decode, 208, 4, 142, 1, // Opcode: ALIGN_MMR6
+/* 461 */ MCD::OPC_FilterValue, 44, 9, 0, 0, // Skip to: 475
+/* 466 */ MCD::OPC_CheckPredicate, 24, 155, 10, 0, // Skip to: 3186
+/* 471 */ MCD::OPC_Decode, 188, 10, 54, // Opcode: EXT_MMR6
+/* 475 */ MCD::OPC_FilterValue, 52, 45, 0, 0, // Skip to: 525
+/* 480 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 483 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 504
+/* 488 */ MCD::OPC_CheckPredicate, 24, 133, 10, 0, // Skip to: 3186
+/* 493 */ MCD::OPC_CheckField, 14, 2, 0, 126, 10, 0, // Skip to: 3186
+/* 500 */ MCD::OPC_Decode, 141, 14, 56, // Opcode: MFHC0_MMR6
+/* 504 */ MCD::OPC_FilterValue, 11, 117, 10, 0, // Skip to: 3186
+/* 509 */ MCD::OPC_CheckPredicate, 24, 112, 10, 0, // Skip to: 3186
+/* 514 */ MCD::OPC_CheckField, 14, 2, 0, 105, 10, 0, // Skip to: 3186
+/* 521 */ MCD::OPC_Decode, 156, 15, 57, // Opcode: MTHC0_MMR6
+/* 525 */ MCD::OPC_FilterValue, 60, 96, 10, 0, // Skip to: 3186
+/* 530 */ MCD::OPC_ExtractField, 14, 2, // Inst{15-14} ...
+/* 533 */ MCD::OPC_FilterValue, 0, 138, 0, 0, // Skip to: 676
+/* 538 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 541 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 555
+/* 546 */ MCD::OPC_CheckPredicate, 24, 75, 10, 0, // Skip to: 3186
+/* 551 */ MCD::OPC_Decode, 132, 14, 56, // Opcode: MFC0_MMR6
+/* 555 */ MCD::OPC_FilterValue, 5, 45, 0, 0, // Skip to: 605
+/* 560 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 563 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 584
+/* 568 */ MCD::OPC_CheckPredicate, 24, 53, 10, 0, // Skip to: 3186
+/* 573 */ MCD::OPC_CheckField, 21, 5, 0, 46, 10, 0, // Skip to: 3186
+/* 580 */ MCD::OPC_Decode, 142, 10, 80, // Opcode: DVP_MMR6
+/* 584 */ MCD::OPC_FilterValue, 7, 37, 10, 0, // Skip to: 3186
+/* 589 */ MCD::OPC_CheckPredicate, 24, 32, 10, 0, // Skip to: 3186
+/* 594 */ MCD::OPC_CheckField, 21, 5, 0, 25, 10, 0, // Skip to: 3186
+/* 601 */ MCD::OPC_Decode, 159, 10, 80, // Opcode: EVP_MMR6
+/* 605 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 619
+/* 610 */ MCD::OPC_CheckPredicate, 24, 11, 10, 0, // Skip to: 3186
+/* 615 */ MCD::OPC_Decode, 147, 15, 57, // Opcode: MTC0_MMR6
+/* 619 */ MCD::OPC_FilterValue, 12, 16, 0, 0, // Skip to: 640
+/* 624 */ MCD::OPC_CheckPredicate, 24, 253, 9, 0, // Skip to: 3186
+/* 629 */ MCD::OPC_CheckField, 11, 3, 1, 246, 9, 0, // Skip to: 3186
+/* 636 */ MCD::OPC_Decode, 234, 5, 74, // Opcode: BITSWAP_MMR6
+/* 640 */ MCD::OPC_FilterValue, 28, 237, 9, 0, // Skip to: 3186
+/* 645 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 648 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 662
+/* 653 */ MCD::OPC_CheckPredicate, 24, 224, 9, 0, // Skip to: 3186
+/* 658 */ MCD::OPC_Decode, 164, 12, 68, // Opcode: JALRC_MMR6
+/* 662 */ MCD::OPC_FilterValue, 3, 215, 9, 0, // Skip to: 3186
+/* 667 */ MCD::OPC_CheckPredicate, 24, 210, 9, 0, // Skip to: 3186
+/* 672 */ MCD::OPC_Decode, 163, 12, 68, // Opcode: JALRC_HB_MMR6
+/* 676 */ MCD::OPC_FilterValue, 1, 10, 1, 0, // Skip to: 947
+/* 681 */ MCD::OPC_ExtractField, 11, 3, // Inst{13-11} ...
+/* 684 */ MCD::OPC_FilterValue, 0, 45, 0, 0, // Skip to: 734
+/* 689 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 692 */ MCD::OPC_FilterValue, 13, 16, 0, 0, // Skip to: 713
+/* 697 */ MCD::OPC_CheckPredicate, 24, 180, 9, 0, // Skip to: 3186
+/* 702 */ MCD::OPC_CheckField, 16, 10, 0, 173, 9, 0, // Skip to: 3186
+/* 709 */ MCD::OPC_Decode, 132, 20, 0, // Opcode: TLBINV_MMR6
+/* 713 */ MCD::OPC_FilterValue, 29, 164, 9, 0, // Skip to: 3186
+/* 718 */ MCD::OPC_CheckPredicate, 24, 159, 9, 0, // Skip to: 3186
+/* 723 */ MCD::OPC_CheckField, 21, 5, 0, 152, 9, 0, // Skip to: 3186
+/* 730 */ MCD::OPC_Decode, 175, 9, 80, // Opcode: DI_MMR6
+/* 734 */ MCD::OPC_FilterValue, 1, 31, 0, 0, // Skip to: 770
+/* 739 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 742 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 756
+/* 747 */ MCD::OPC_CheckPredicate, 24, 130, 9, 0, // Skip to: 3186
+/* 752 */ MCD::OPC_Decode, 132, 7, 68, // Opcode: CLO_MMR6
+/* 756 */ MCD::OPC_FilterValue, 20, 121, 9, 0, // Skip to: 3186
+/* 761 */ MCD::OPC_CheckPredicate, 24, 116, 9, 0, // Skip to: 3186
+/* 766 */ MCD::OPC_Decode, 138, 14, 78, // Opcode: MFC2_MMR6
+/* 770 */ MCD::OPC_FilterValue, 2, 45, 0, 0, // Skip to: 820
+/* 775 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 778 */ MCD::OPC_FilterValue, 13, 16, 0, 0, // Skip to: 799
+/* 783 */ MCD::OPC_CheckPredicate, 24, 94, 9, 0, // Skip to: 3186
+/* 788 */ MCD::OPC_CheckField, 16, 10, 0, 87, 9, 0, // Skip to: 3186
+/* 795 */ MCD::OPC_Decode, 131, 20, 0, // Opcode: TLBINVF_MMR6
+/* 799 */ MCD::OPC_FilterValue, 29, 78, 9, 0, // Skip to: 3186
+/* 804 */ MCD::OPC_CheckPredicate, 24, 73, 9, 0, // Skip to: 3186
+/* 809 */ MCD::OPC_CheckField, 21, 5, 0, 66, 9, 0, // Skip to: 3186
+/* 816 */ MCD::OPC_Decode, 150, 10, 80, // Opcode: EI_MMR6
+/* 820 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 841
+/* 825 */ MCD::OPC_CheckPredicate, 24, 52, 9, 0, // Skip to: 3186
+/* 830 */ MCD::OPC_CheckField, 6, 5, 20, 45, 9, 0, // Skip to: 3186
+/* 837 */ MCD::OPC_Decode, 153, 15, 79, // Opcode: MTC2_MMR6
+/* 841 */ MCD::OPC_FilterValue, 4, 23, 0, 0, // Skip to: 869
+/* 846 */ MCD::OPC_CheckPredicate, 25, 31, 9, 0, // Skip to: 3186
+/* 851 */ MCD::OPC_CheckField, 21, 5, 0, 24, 9, 0, // Skip to: 3186
+/* 858 */ MCD::OPC_CheckField, 6, 3, 5, 17, 9, 0, // Skip to: 3186
+/* 865 */ MCD::OPC_Decode, 239, 11, 80, // Opcode: GINVI_MMR6
+/* 869 */ MCD::OPC_FilterValue, 5, 23, 0, 0, // Skip to: 897
+/* 874 */ MCD::OPC_CheckPredicate, 24, 3, 9, 0, // Skip to: 3186
+/* 879 */ MCD::OPC_CheckField, 21, 5, 0, 252, 8, 0, // Skip to: 3186
+/* 886 */ MCD::OPC_CheckField, 6, 5, 13, 245, 8, 0, // Skip to: 3186
+/* 893 */ MCD::OPC_Decode, 209, 19, 75, // Opcode: SYNC_MMR6
+/* 897 */ MCD::OPC_FilterValue, 6, 24, 0, 0, // Skip to: 926
+/* 902 */ MCD::OPC_CheckPredicate, 25, 231, 8, 0, // Skip to: 3186
+/* 907 */ MCD::OPC_CheckField, 21, 5, 0, 224, 8, 0, // Skip to: 3186
+/* 914 */ MCD::OPC_CheckField, 6, 3, 5, 217, 8, 0, // Skip to: 3186
+/* 921 */ MCD::OPC_Decode, 241, 11, 143, 1, // Opcode: GINVT_MMR6
+/* 926 */ MCD::OPC_FilterValue, 7, 207, 8, 0, // Skip to: 3186
+/* 931 */ MCD::OPC_CheckPredicate, 24, 202, 8, 0, // Skip to: 3186
+/* 936 */ MCD::OPC_CheckField, 6, 5, 12, 195, 8, 0, // Skip to: 3186
+/* 943 */ MCD::OPC_Decode, 181, 20, 68, // Opcode: WSBH_MMR6
+/* 947 */ MCD::OPC_FilterValue, 2, 45, 0, 0, // Skip to: 997
+/* 952 */ MCD::OPC_ExtractField, 6, 8, // Inst{13-6} ...
+/* 955 */ MCD::OPC_FilterValue, 52, 9, 0, 0, // Skip to: 969
+/* 960 */ MCD::OPC_CheckPredicate, 24, 173, 8, 0, // Skip to: 3186
+/* 965 */ MCD::OPC_Decode, 146, 14, 78, // Opcode: MFHC2_MMR6
+/* 969 */ MCD::OPC_FilterValue, 77, 9, 0, 0, // Skip to: 983
+/* 974 */ MCD::OPC_CheckPredicate, 24, 159, 8, 0, // Skip to: 3186
+/* 979 */ MCD::OPC_Decode, 175, 20, 76, // Opcode: WAIT_MMR6
+/* 983 */ MCD::OPC_FilterValue, 116, 150, 8, 0, // Skip to: 3186
+/* 988 */ MCD::OPC_CheckPredicate, 24, 145, 8, 0, // Skip to: 3186
+/* 993 */ MCD::OPC_Decode, 161, 15, 79, // Opcode: MTHC2_MMR6
+/* 997 */ MCD::OPC_FilterValue, 3, 136, 8, 0, // Skip to: 3186
+/* 1002 */ MCD::OPC_ExtractField, 6, 8, // Inst{13-6} ...
+/* 1005 */ MCD::OPC_FilterValue, 109, 9, 0, 0, // Skip to: 1019
+/* 1010 */ MCD::OPC_CheckPredicate, 24, 123, 8, 0, // Skip to: 3186
+/* 1015 */ MCD::OPC_Decode, 168, 17, 76, // Opcode: SDBBP_MMR6
+/* 1019 */ MCD::OPC_FilterValue, 133, 1, 9, 0, 0, // Skip to: 1034
+/* 1025 */ MCD::OPC_CheckPredicate, 24, 108, 8, 0, // Skip to: 3186
+/* 1030 */ MCD::OPC_Decode, 223, 16, 68, // Opcode: RDPGPR_MMR6
+/* 1034 */ MCD::OPC_FilterValue, 141, 1, 16, 0, 0, // Skip to: 1056
+/* 1040 */ MCD::OPC_CheckPredicate, 24, 93, 8, 0, // Skip to: 3186
+/* 1045 */ MCD::OPC_CheckField, 16, 10, 0, 86, 8, 0, // Skip to: 3186
+/* 1052 */ MCD::OPC_Decode, 153, 9, 0, // Opcode: DERET_MMR6
+/* 1056 */ MCD::OPC_FilterValue, 197, 1, 9, 0, 0, // Skip to: 1071
+/* 1062 */ MCD::OPC_CheckPredicate, 24, 71, 8, 0, // Skip to: 3186
+/* 1067 */ MCD::OPC_Decode, 178, 20, 68, // Opcode: WRPGPR_MMR6
+/* 1071 */ MCD::OPC_FilterValue, 205, 1, 61, 8, 0, // Skip to: 3186
+/* 1077 */ MCD::OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 1080 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1094
+/* 1085 */ MCD::OPC_CheckPredicate, 24, 48, 8, 0, // Skip to: 3186
+/* 1090 */ MCD::OPC_Decode, 156, 10, 0, // Opcode: ERET_MMR6
+/* 1094 */ MCD::OPC_FilterValue, 1, 39, 8, 0, // Skip to: 3186
+/* 1099 */ MCD::OPC_CheckPredicate, 24, 34, 8, 0, // Skip to: 3186
+/* 1104 */ MCD::OPC_Decode, 154, 10, 0, // Opcode: ERETNC_MMR6
+/* 1108 */ MCD::OPC_FilterValue, 4, 26, 0, 0, // Skip to: 1139
+/* 1113 */ MCD::OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 1130
+/* 1118 */ MCD::OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 1130
+/* 1125 */ MCD::OPC_Decode, 139, 13, 144, 1, // Opcode: LUI_MMR6
+/* 1130 */ MCD::OPC_CheckPredicate, 24, 3, 8, 0, // Skip to: 3186
+/* 1135 */ MCD::OPC_Decode, 238, 4, 96, // Opcode: AUI_MMR6
+/* 1139 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1154
+/* 1144 */ MCD::OPC_CheckPredicate, 24, 245, 7, 0, // Skip to: 3186
+/* 1149 */ MCD::OPC_Decode, 206, 12, 145, 1, // Opcode: LBU_MMR6
+/* 1154 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1168
+/* 1159 */ MCD::OPC_CheckPredicate, 24, 230, 7, 0, // Skip to: 3186
+/* 1164 */ MCD::OPC_Decode, 152, 17, 86, // Opcode: SB_MMR6
+/* 1168 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1183
+/* 1173 */ MCD::OPC_CheckPredicate, 24, 216, 7, 0, // Skip to: 3186
+/* 1178 */ MCD::OPC_Decode, 208, 12, 145, 1, // Opcode: LB_MMR6
+/* 1183 */ MCD::OPC_FilterValue, 8, 105, 0, 0, // Skip to: 1293
+/* 1188 */ MCD::OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 1191 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1213
+/* 1196 */ MCD::OPC_CheckPredicate, 24, 193, 7, 0, // Skip to: 3186
+/* 1201 */ MCD::OPC_CheckField, 11, 1, 0, 186, 7, 0, // Skip to: 3186
+/* 1208 */ MCD::OPC_Decode, 152, 13, 146, 1, // Opcode: LWC2_MMR6
+/* 1213 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1235
+/* 1218 */ MCD::OPC_CheckPredicate, 24, 171, 7, 0, // Skip to: 3186
+/* 1223 */ MCD::OPC_CheckField, 11, 1, 0, 164, 7, 0, // Skip to: 3186
+/* 1230 */ MCD::OPC_Decode, 220, 12, 146, 1, // Opcode: LDC2_MMR6
+/* 1235 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1249
+/* 1240 */ MCD::OPC_CheckPredicate, 24, 149, 7, 0, // Skip to: 3186
+/* 1245 */ MCD::OPC_Decode, 209, 6, 88, // Opcode: CACHE_MMR6
+/* 1249 */ MCD::OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1271
+/* 1254 */ MCD::OPC_CheckPredicate, 24, 135, 7, 0, // Skip to: 3186
+/* 1259 */ MCD::OPC_CheckField, 11, 1, 0, 128, 7, 0, // Skip to: 3186
+/* 1266 */ MCD::OPC_Decode, 177, 19, 146, 1, // Opcode: SWC2_MMR6
+/* 1271 */ MCD::OPC_FilterValue, 10, 118, 7, 0, // Skip to: 3186
+/* 1276 */ MCD::OPC_CheckPredicate, 24, 113, 7, 0, // Skip to: 3186
+/* 1281 */ MCD::OPC_CheckField, 11, 1, 0, 106, 7, 0, // Skip to: 3186
+/* 1288 */ MCD::OPC_Decode, 175, 17, 146, 1, // Opcode: SDC2_MMR6
+/* 1293 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 1307
+/* 1298 */ MCD::OPC_CheckPredicate, 24, 91, 7, 0, // Skip to: 3186
+/* 1303 */ MCD::OPC_Decode, 141, 4, 85, // Opcode: ADDIU_MMR6
+/* 1307 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 1321
+/* 1312 */ MCD::OPC_CheckPredicate, 24, 77, 7, 0, // Skip to: 3186
+/* 1317 */ MCD::OPC_Decode, 140, 18, 86, // Opcode: SH_MMR6
+/* 1321 */ MCD::OPC_FilterValue, 16, 78, 0, 0, // Skip to: 1404
+/* 1326 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 1329 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1344
+/* 1334 */ MCD::OPC_CheckPredicate, 26, 55, 7, 0, // Skip to: 3186
+/* 1339 */ MCD::OPC_Decode, 150, 5, 147, 1, // Opcode: BC1EQZC_MMR6
+/* 1344 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1359
+/* 1349 */ MCD::OPC_CheckPredicate, 26, 40, 7, 0, // Skip to: 3186
+/* 1354 */ MCD::OPC_Decode, 155, 5, 147, 1, // Opcode: BC1NEZC_MMR6
+/* 1359 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1374
+/* 1364 */ MCD::OPC_CheckPredicate, 24, 25, 7, 0, // Skip to: 3186
+/* 1369 */ MCD::OPC_Decode, 160, 5, 148, 1, // Opcode: BC2EQZC_MMR6
+/* 1374 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1389
+/* 1379 */ MCD::OPC_CheckPredicate, 24, 10, 7, 0, // Skip to: 3186
+/* 1384 */ MCD::OPC_Decode, 162, 5, 148, 1, // Opcode: BC2NEZC_MMR6
+/* 1389 */ MCD::OPC_FilterValue, 12, 0, 7, 0, // Skip to: 3186
+/* 1394 */ MCD::OPC_CheckPredicate, 24, 251, 6, 0, // Skip to: 3186
+/* 1399 */ MCD::OPC_Decode, 207, 19, 149, 1, // Opcode: SYNCI_MMR6
+/* 1404 */ MCD::OPC_FilterValue, 20, 9, 0, 0, // Skip to: 1418
+/* 1409 */ MCD::OPC_CheckPredicate, 24, 236, 6, 0, // Skip to: 3186
+/* 1414 */ MCD::OPC_Decode, 142, 16, 96, // Opcode: ORI_MMR6
+/* 1418 */ MCD::OPC_FilterValue, 21, 71, 5, 0, // Skip to: 2774
+/* 1423 */ MCD::OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 1426 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1441
+/* 1431 */ MCD::OPC_CheckPredicate, 26, 214, 6, 0, // Skip to: 3186
+/* 1436 */ MCD::OPC_Decode, 184, 14, 150, 1, // Opcode: MIN_S_MMR6
+/* 1441 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1456
+/* 1446 */ MCD::OPC_CheckPredicate, 26, 199, 6, 0, // Skip to: 3186
+/* 1451 */ MCD::OPC_Decode, 173, 7, 151, 1, // Opcode: CMP_AF_S_MMR6
+/* 1456 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1471
+/* 1461 */ MCD::OPC_CheckPredicate, 26, 184, 6, 0, // Skip to: 3186
+/* 1466 */ MCD::OPC_Decode, 253, 13, 150, 1, // Opcode: MAX_S_MMR6
+/* 1471 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 1486
+/* 1476 */ MCD::OPC_CheckPredicate, 26, 169, 6, 0, // Skip to: 3186
+/* 1481 */ MCD::OPC_Decode, 172, 7, 152, 1, // Opcode: CMP_AF_D_MMR6
+/* 1486 */ MCD::OPC_FilterValue, 32, 17, 0, 0, // Skip to: 1508
+/* 1491 */ MCD::OPC_CheckPredicate, 24, 154, 6, 0, // Skip to: 3186
+/* 1496 */ MCD::OPC_CheckField, 11, 5, 0, 147, 6, 0, // Skip to: 3186
+/* 1503 */ MCD::OPC_Decode, 241, 16, 153, 1, // Opcode: RINT_S_MMR6
+/* 1508 */ MCD::OPC_FilterValue, 35, 10, 0, 0, // Skip to: 1523
+/* 1513 */ MCD::OPC_CheckPredicate, 26, 132, 6, 0, // Skip to: 3186
+/* 1518 */ MCD::OPC_Decode, 165, 14, 150, 1, // Opcode: MINA_S_MMR6
+/* 1523 */ MCD::OPC_FilterValue, 43, 10, 0, 0, // Skip to: 1538
+/* 1528 */ MCD::OPC_CheckPredicate, 26, 117, 6, 0, // Skip to: 3186
+/* 1533 */ MCD::OPC_Decode, 234, 13, 150, 1, // Opcode: MAXA_S_MMR6
+/* 1538 */ MCD::OPC_FilterValue, 48, 10, 0, 0, // Skip to: 1553
+/* 1543 */ MCD::OPC_CheckPredicate, 26, 102, 6, 0, // Skip to: 3186
+/* 1548 */ MCD::OPC_Decode, 202, 10, 154, 1, // Opcode: FADD_S_MMR6
+/* 1553 */ MCD::OPC_FilterValue, 56, 10, 0, 0, // Skip to: 1568
+/* 1558 */ MCD::OPC_CheckPredicate, 24, 87, 6, 0, // Skip to: 3186
+/* 1563 */ MCD::OPC_Decode, 196, 17, 150, 1, // Opcode: SELEQZ_S_MMR6
+/* 1568 */ MCD::OPC_FilterValue, 59, 31, 0, 0, // Skip to: 1604
+/* 1573 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 1576 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1590
+/* 1581 */ MCD::OPC_CheckPredicate, 26, 64, 6, 0, // Skip to: 3186
+/* 1586 */ MCD::OPC_Decode, 136, 14, 107, // Opcode: MFC1_MMR6
+/* 1590 */ MCD::OPC_FilterValue, 5, 55, 6, 0, // Skip to: 3186
+/* 1595 */ MCD::OPC_CheckPredicate, 26, 50, 6, 0, // Skip to: 3186
+/* 1600 */ MCD::OPC_Decode, 151, 15, 113, // Opcode: MTC1_MMR6
+/* 1604 */ MCD::OPC_FilterValue, 69, 10, 0, 0, // Skip to: 1619
+/* 1609 */ MCD::OPC_CheckPredicate, 26, 36, 6, 0, // Skip to: 3186
+/* 1614 */ MCD::OPC_Decode, 241, 7, 151, 1, // Opcode: CMP_UN_S_MMR6
+/* 1619 */ MCD::OPC_FilterValue, 85, 10, 0, 0, // Skip to: 1634
+/* 1624 */ MCD::OPC_CheckPredicate, 26, 21, 6, 0, // Skip to: 3186
+/* 1629 */ MCD::OPC_Decode, 239, 7, 152, 1, // Opcode: CMP_UN_D_MMR6
+/* 1634 */ MCD::OPC_FilterValue, 96, 17, 0, 0, // Skip to: 1656
+/* 1639 */ MCD::OPC_CheckPredicate, 24, 6, 6, 0, // Skip to: 3186
+/* 1644 */ MCD::OPC_CheckField, 11, 5, 0, 255, 5, 0, // Skip to: 3186
+/* 1651 */ MCD::OPC_Decode, 241, 6, 153, 1, // Opcode: CLASS_S_MMR6
+/* 1656 */ MCD::OPC_FilterValue, 112, 10, 0, 0, // Skip to: 1671
+/* 1661 */ MCD::OPC_CheckPredicate, 26, 240, 5, 0, // Skip to: 3186
+/* 1666 */ MCD::OPC_Decode, 216, 11, 154, 1, // Opcode: FSUB_S_MMR6
+/* 1671 */ MCD::OPC_FilterValue, 120, 10, 0, 0, // Skip to: 1686
+/* 1676 */ MCD::OPC_CheckPredicate, 24, 225, 5, 0, // Skip to: 3186
+/* 1681 */ MCD::OPC_Decode, 203, 17, 150, 1, // Opcode: SELNEZ_S_MMR6
+/* 1686 */ MCD::OPC_FilterValue, 123, 16, 0, 0, // Skip to: 1707
+/* 1691 */ MCD::OPC_CheckPredicate, 26, 210, 5, 0, // Skip to: 3186
+/* 1696 */ MCD::OPC_CheckField, 11, 5, 0, 203, 5, 0, // Skip to: 3186
+/* 1703 */ MCD::OPC_Decode, 163, 11, 112, // Opcode: FMOV_S_MMR6
+/* 1707 */ MCD::OPC_FilterValue, 133, 1, 10, 0, 0, // Skip to: 1723
+/* 1713 */ MCD::OPC_CheckPredicate, 26, 188, 5, 0, // Skip to: 3186
+/* 1718 */ MCD::OPC_Decode, 179, 7, 151, 1, // Opcode: CMP_EQ_S_MMR6
+/* 1723 */ MCD::OPC_FilterValue, 149, 1, 10, 0, 0, // Skip to: 1739
+/* 1729 */ MCD::OPC_CheckPredicate, 26, 172, 5, 0, // Skip to: 3186
+/* 1734 */ MCD::OPC_Decode, 175, 7, 152, 1, // Opcode: CMP_EQ_D_MMR6
+/* 1739 */ MCD::OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 1755
+/* 1745 */ MCD::OPC_CheckPredicate, 26, 156, 5, 0, // Skip to: 3186
+/* 1750 */ MCD::OPC_Decode, 173, 11, 154, 1, // Opcode: FMUL_S_MMR6
+/* 1755 */ MCD::OPC_FilterValue, 184, 1, 10, 0, 0, // Skip to: 1771
+/* 1761 */ MCD::OPC_CheckPredicate, 24, 140, 5, 0, // Skip to: 3186
+/* 1766 */ MCD::OPC_Decode, 207, 17, 155, 1, // Opcode: SEL_S_MMR6
+/* 1771 */ MCD::OPC_FilterValue, 197, 1, 10, 0, 0, // Skip to: 1787
+/* 1777 */ MCD::OPC_CheckPredicate, 26, 124, 5, 0, // Skip to: 3186
+/* 1782 */ MCD::OPC_Decode, 229, 7, 151, 1, // Opcode: CMP_UEQ_S_MMR6
+/* 1787 */ MCD::OPC_FilterValue, 213, 1, 10, 0, 0, // Skip to: 1803
+/* 1793 */ MCD::OPC_CheckPredicate, 26, 108, 5, 0, // Skip to: 3186
+/* 1798 */ MCD::OPC_Decode, 227, 7, 152, 1, // Opcode: CMP_UEQ_D_MMR6
+/* 1803 */ MCD::OPC_FilterValue, 240, 1, 10, 0, 0, // Skip to: 1819
+/* 1809 */ MCD::OPC_CheckPredicate, 26, 92, 5, 0, // Skip to: 3186
+/* 1814 */ MCD::OPC_Decode, 240, 10, 154, 1, // Opcode: FDIV_S_MMR6
+/* 1819 */ MCD::OPC_FilterValue, 133, 2, 10, 0, 0, // Skip to: 1835
+/* 1825 */ MCD::OPC_CheckPredicate, 26, 76, 5, 0, // Skip to: 3186
+/* 1830 */ MCD::OPC_Decode, 193, 7, 151, 1, // Opcode: CMP_LT_S_MMR6
+/* 1835 */ MCD::OPC_FilterValue, 149, 2, 10, 0, 0, // Skip to: 1851
+/* 1841 */ MCD::OPC_CheckPredicate, 26, 60, 5, 0, // Skip to: 3186
+/* 1846 */ MCD::OPC_Decode, 189, 7, 152, 1, // Opcode: CMP_LT_D_MMR6
+/* 1851 */ MCD::OPC_FilterValue, 187, 2, 45, 0, 0, // Skip to: 1902
+/* 1857 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 1860 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1874
+/* 1865 */ MCD::OPC_CheckPredicate, 26, 36, 5, 0, // Skip to: 3186
+/* 1870 */ MCD::OPC_Decode, 148, 8, 109, // Opcode: CVT_L_S_MMR6
+/* 1874 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1888
+/* 1879 */ MCD::OPC_CheckPredicate, 26, 22, 5, 0, // Skip to: 3186
+/* 1884 */ MCD::OPC_Decode, 164, 8, 112, // Opcode: CVT_W_S_MMR6
+/* 1888 */ MCD::OPC_FilterValue, 8, 13, 5, 0, // Skip to: 3186
+/* 1893 */ MCD::OPC_CheckPredicate, 26, 8, 5, 0, // Skip to: 3186
+/* 1898 */ MCD::OPC_Decode, 145, 8, 110, // Opcode: CVT_L_D_MMR6
+/* 1902 */ MCD::OPC_FilterValue, 197, 2, 10, 0, 0, // Skip to: 1918
+/* 1908 */ MCD::OPC_CheckPredicate, 26, 249, 4, 0, // Skip to: 3186
+/* 1913 */ MCD::OPC_Decode, 237, 7, 151, 1, // Opcode: CMP_ULT_S_MMR6
+/* 1918 */ MCD::OPC_FilterValue, 213, 2, 10, 0, 0, // Skip to: 1934
+/* 1924 */ MCD::OPC_CheckPredicate, 26, 233, 4, 0, // Skip to: 3186
+/* 1929 */ MCD::OPC_Decode, 235, 7, 152, 1, // Opcode: CMP_ULT_D_MMR6
+/* 1934 */ MCD::OPC_FilterValue, 133, 3, 10, 0, 0, // Skip to: 1950
+/* 1940 */ MCD::OPC_CheckPredicate, 26, 217, 4, 0, // Skip to: 3186
+/* 1945 */ MCD::OPC_Decode, 187, 7, 151, 1, // Opcode: CMP_LE_S_MMR6
+/* 1950 */ MCD::OPC_FilterValue, 149, 3, 10, 0, 0, // Skip to: 1966
+/* 1956 */ MCD::OPC_CheckPredicate, 26, 201, 4, 0, // Skip to: 3186
+/* 1961 */ MCD::OPC_Decode, 183, 7, 152, 1, // Opcode: CMP_LE_D_MMR6
+/* 1966 */ MCD::OPC_FilterValue, 184, 3, 10, 0, 0, // Skip to: 1982
+/* 1972 */ MCD::OPC_CheckPredicate, 26, 185, 4, 0, // Skip to: 3186
+/* 1977 */ MCD::OPC_Decode, 202, 13, 156, 1, // Opcode: MADDF_S_MMR6
+/* 1982 */ MCD::OPC_FilterValue, 197, 3, 10, 0, 0, // Skip to: 1998
+/* 1988 */ MCD::OPC_CheckPredicate, 26, 169, 4, 0, // Skip to: 3186
+/* 1993 */ MCD::OPC_Decode, 233, 7, 151, 1, // Opcode: CMP_ULE_S_MMR6
+/* 1998 */ MCD::OPC_FilterValue, 213, 3, 10, 0, 0, // Skip to: 2014
+/* 2004 */ MCD::OPC_CheckPredicate, 26, 153, 4, 0, // Skip to: 3186
+/* 2009 */ MCD::OPC_Decode, 231, 7, 152, 1, // Opcode: CMP_ULE_D_MMR6
+/* 2014 */ MCD::OPC_FilterValue, 248, 3, 10, 0, 0, // Skip to: 2030
+/* 2020 */ MCD::OPC_CheckPredicate, 26, 137, 4, 0, // Skip to: 3186
+/* 2025 */ MCD::OPC_Decode, 253, 14, 156, 1, // Opcode: MSUBF_S_MMR6
+/* 2030 */ MCD::OPC_FilterValue, 131, 4, 10, 0, 0, // Skip to: 2046
+/* 2036 */ MCD::OPC_CheckPredicate, 26, 121, 4, 0, // Skip to: 3186
+/* 2041 */ MCD::OPC_Decode, 179, 14, 131, 1, // Opcode: MIN_D_MMR6
+/* 2046 */ MCD::OPC_FilterValue, 133, 4, 10, 0, 0, // Skip to: 2062
+/* 2052 */ MCD::OPC_CheckPredicate, 26, 105, 4, 0, // Skip to: 3186
+/* 2057 */ MCD::OPC_Decode, 197, 7, 151, 1, // Opcode: CMP_SAF_S_MMR6
+/* 2062 */ MCD::OPC_FilterValue, 139, 4, 10, 0, 0, // Skip to: 2078
+/* 2068 */ MCD::OPC_CheckPredicate, 26, 89, 4, 0, // Skip to: 3186
+/* 2073 */ MCD::OPC_Decode, 248, 13, 131, 1, // Opcode: MAX_D_MMR6
+/* 2078 */ MCD::OPC_FilterValue, 149, 4, 10, 0, 0, // Skip to: 2094
+/* 2084 */ MCD::OPC_CheckPredicate, 26, 73, 4, 0, // Skip to: 3186
+/* 2089 */ MCD::OPC_Decode, 195, 7, 152, 1, // Opcode: CMP_SAF_D_MMR6
+/* 2094 */ MCD::OPC_FilterValue, 160, 4, 17, 0, 0, // Skip to: 2117
+/* 2100 */ MCD::OPC_CheckPredicate, 24, 57, 4, 0, // Skip to: 3186
+/* 2105 */ MCD::OPC_CheckField, 11, 5, 0, 50, 4, 0, // Skip to: 3186
+/* 2112 */ MCD::OPC_Decode, 239, 16, 157, 1, // Opcode: RINT_D_MMR6
+/* 2117 */ MCD::OPC_FilterValue, 163, 4, 10, 0, 0, // Skip to: 2133
+/* 2123 */ MCD::OPC_CheckPredicate, 26, 34, 4, 0, // Skip to: 3186
+/* 2128 */ MCD::OPC_Decode, 163, 14, 131, 1, // Opcode: MINA_D_MMR6
+/* 2133 */ MCD::OPC_FilterValue, 171, 4, 10, 0, 0, // Skip to: 2149
+/* 2139 */ MCD::OPC_CheckPredicate, 26, 18, 4, 0, // Skip to: 3186
+/* 2144 */ MCD::OPC_Decode, 232, 13, 131, 1, // Opcode: MAXA_D_MMR6
+/* 2149 */ MCD::OPC_FilterValue, 184, 4, 10, 0, 0, // Skip to: 2165
+/* 2155 */ MCD::OPC_CheckPredicate, 24, 2, 4, 0, // Skip to: 3186
+/* 2160 */ MCD::OPC_Decode, 193, 17, 131, 1, // Opcode: SELEQZ_D_MMR6
+/* 2165 */ MCD::OPC_FilterValue, 197, 4, 10, 0, 0, // Skip to: 2181
+/* 2171 */ MCD::OPC_CheckPredicate, 26, 242, 3, 0, // Skip to: 3186
+/* 2176 */ MCD::OPC_Decode, 225, 7, 151, 1, // Opcode: CMP_SUN_S_MMR6
+/* 2181 */ MCD::OPC_FilterValue, 213, 4, 10, 0, 0, // Skip to: 2197
+/* 2187 */ MCD::OPC_CheckPredicate, 26, 226, 3, 0, // Skip to: 3186
+/* 2192 */ MCD::OPC_Decode, 223, 7, 152, 1, // Opcode: CMP_SUN_D_MMR6
+/* 2197 */ MCD::OPC_FilterValue, 224, 4, 17, 0, 0, // Skip to: 2220
+/* 2203 */ MCD::OPC_CheckPredicate, 24, 210, 3, 0, // Skip to: 3186
+/* 2208 */ MCD::OPC_CheckField, 11, 5, 0, 203, 3, 0, // Skip to: 3186
+/* 2215 */ MCD::OPC_Decode, 239, 6, 157, 1, // Opcode: CLASS_D_MMR6
+/* 2220 */ MCD::OPC_FilterValue, 248, 4, 10, 0, 0, // Skip to: 2236
+/* 2226 */ MCD::OPC_CheckPredicate, 24, 187, 3, 0, // Skip to: 3186
+/* 2231 */ MCD::OPC_Decode, 200, 17, 131, 1, // Opcode: SELNEZ_D_MMR6
+/* 2236 */ MCD::OPC_FilterValue, 133, 5, 10, 0, 0, // Skip to: 2252
+/* 2242 */ MCD::OPC_CheckPredicate, 26, 171, 3, 0, // Skip to: 3186
+/* 2247 */ MCD::OPC_Decode, 201, 7, 151, 1, // Opcode: CMP_SEQ_S_MMR6
+/* 2252 */ MCD::OPC_FilterValue, 149, 5, 10, 0, 0, // Skip to: 2268
+/* 2258 */ MCD::OPC_CheckPredicate, 26, 155, 3, 0, // Skip to: 3186
+/* 2263 */ MCD::OPC_Decode, 199, 7, 152, 1, // Opcode: CMP_SEQ_D_MMR6
+/* 2268 */ MCD::OPC_FilterValue, 184, 5, 10, 0, 0, // Skip to: 2284
+/* 2274 */ MCD::OPC_CheckPredicate, 24, 139, 3, 0, // Skip to: 3186
+/* 2279 */ MCD::OPC_Decode, 205, 17, 158, 1, // Opcode: SEL_D_MMR6
+/* 2284 */ MCD::OPC_FilterValue, 197, 5, 10, 0, 0, // Skip to: 2300
+/* 2290 */ MCD::OPC_CheckPredicate, 26, 123, 3, 0, // Skip to: 3186
+/* 2295 */ MCD::OPC_Decode, 213, 7, 151, 1, // Opcode: CMP_SUEQ_S_MMR6
+/* 2300 */ MCD::OPC_FilterValue, 213, 5, 10, 0, 0, // Skip to: 2316
+/* 2306 */ MCD::OPC_CheckPredicate, 26, 107, 3, 0, // Skip to: 3186
+/* 2311 */ MCD::OPC_Decode, 211, 7, 152, 1, // Opcode: CMP_SUEQ_D_MMR6
+/* 2316 */ MCD::OPC_FilterValue, 133, 6, 10, 0, 0, // Skip to: 2332
+/* 2322 */ MCD::OPC_CheckPredicate, 26, 91, 3, 0, // Skip to: 3186
+/* 2327 */ MCD::OPC_Decode, 209, 7, 151, 1, // Opcode: CMP_SLT_S_MMR6
+/* 2332 */ MCD::OPC_FilterValue, 149, 6, 10, 0, 0, // Skip to: 2348
+/* 2338 */ MCD::OPC_CheckPredicate, 26, 75, 3, 0, // Skip to: 3186
+/* 2343 */ MCD::OPC_Decode, 207, 7, 152, 1, // Opcode: CMP_SLT_D_MMR6
+/* 2348 */ MCD::OPC_FilterValue, 187, 6, 227, 0, 0, // Skip to: 2581
+/* 2354 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 2357 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2371
+/* 2362 */ MCD::OPC_CheckPredicate, 26, 51, 3, 0, // Skip to: 3186
+/* 2367 */ MCD::OPC_Decode, 139, 11, 109, // Opcode: FLOOR_L_S_MMR6
+/* 2371 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2385
+/* 2376 */ MCD::OPC_CheckPredicate, 26, 37, 3, 0, // Skip to: 3186
+/* 2381 */ MCD::OPC_Decode, 146, 11, 112, // Opcode: FLOOR_W_S_MMR6
+/* 2385 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2399
+/* 2390 */ MCD::OPC_CheckPredicate, 26, 23, 3, 0, // Skip to: 3186
+/* 2395 */ MCD::OPC_Decode, 214, 6, 109, // Opcode: CEIL_L_S_MMR6
+/* 2399 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2413
+/* 2404 */ MCD::OPC_CheckPredicate, 26, 9, 3, 0, // Skip to: 3186
+/* 2409 */ MCD::OPC_Decode, 221, 6, 112, // Opcode: CEIL_W_S_MMR6
+/* 2413 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2427
+/* 2418 */ MCD::OPC_CheckPredicate, 26, 251, 2, 0, // Skip to: 3186
+/* 2423 */ MCD::OPC_Decode, 155, 20, 109, // Opcode: TRUNC_L_S_MMR6
+/* 2427 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2441
+/* 2432 */ MCD::OPC_CheckPredicate, 26, 237, 2, 0, // Skip to: 3186
+/* 2437 */ MCD::OPC_Decode, 162, 20, 112, // Opcode: TRUNC_W_S_MMR6
+/* 2441 */ MCD::OPC_FilterValue, 6, 9, 0, 0, // Skip to: 2455
+/* 2446 */ MCD::OPC_CheckPredicate, 26, 223, 2, 0, // Skip to: 3186
+/* 2451 */ MCD::OPC_Decode, 249, 16, 109, // Opcode: ROUND_L_S_MMR6
+/* 2455 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2469
+/* 2460 */ MCD::OPC_CheckPredicate, 26, 209, 2, 0, // Skip to: 3186
+/* 2465 */ MCD::OPC_Decode, 128, 17, 112, // Opcode: ROUND_W_S_MMR6
+/* 2469 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2483
+/* 2474 */ MCD::OPC_CheckPredicate, 26, 195, 2, 0, // Skip to: 3186
+/* 2479 */ MCD::OPC_Decode, 137, 11, 110, // Opcode: FLOOR_L_D_MMR6
+/* 2483 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2497
+/* 2488 */ MCD::OPC_CheckPredicate, 26, 181, 2, 0, // Skip to: 3186
+/* 2493 */ MCD::OPC_Decode, 142, 11, 114, // Opcode: FLOOR_W_D_MMR6
+/* 2497 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2511
+/* 2502 */ MCD::OPC_CheckPredicate, 26, 167, 2, 0, // Skip to: 3186
+/* 2507 */ MCD::OPC_Decode, 212, 6, 110, // Opcode: CEIL_L_D_MMR6
+/* 2511 */ MCD::OPC_FilterValue, 11, 9, 0, 0, // Skip to: 2525
+/* 2516 */ MCD::OPC_CheckPredicate, 26, 153, 2, 0, // Skip to: 3186
+/* 2521 */ MCD::OPC_Decode, 217, 6, 114, // Opcode: CEIL_W_D_MMR6
+/* 2525 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2539
+/* 2530 */ MCD::OPC_CheckPredicate, 26, 139, 2, 0, // Skip to: 3186
+/* 2535 */ MCD::OPC_Decode, 153, 20, 110, // Opcode: TRUNC_L_D_MMR6
+/* 2539 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2553
+/* 2544 */ MCD::OPC_CheckPredicate, 26, 125, 2, 0, // Skip to: 3186
+/* 2549 */ MCD::OPC_Decode, 158, 20, 114, // Opcode: TRUNC_W_D_MMR6
+/* 2553 */ MCD::OPC_FilterValue, 14, 9, 0, 0, // Skip to: 2567
+/* 2558 */ MCD::OPC_CheckPredicate, 26, 111, 2, 0, // Skip to: 3186
+/* 2563 */ MCD::OPC_Decode, 247, 16, 110, // Opcode: ROUND_L_D_MMR6
+/* 2567 */ MCD::OPC_FilterValue, 15, 102, 2, 0, // Skip to: 3186
+/* 2572 */ MCD::OPC_CheckPredicate, 26, 97, 2, 0, // Skip to: 3186
+/* 2577 */ MCD::OPC_Decode, 252, 16, 110, // Opcode: ROUND_W_D_MMR6
+/* 2581 */ MCD::OPC_FilterValue, 197, 6, 10, 0, 0, // Skip to: 2597
+/* 2587 */ MCD::OPC_CheckPredicate, 26, 82, 2, 0, // Skip to: 3186
+/* 2592 */ MCD::OPC_Decode, 221, 7, 151, 1, // Opcode: CMP_SULT_S_MMR6
+/* 2597 */ MCD::OPC_FilterValue, 213, 6, 10, 0, 0, // Skip to: 2613
+/* 2603 */ MCD::OPC_CheckPredicate, 26, 66, 2, 0, // Skip to: 3186
+/* 2608 */ MCD::OPC_Decode, 219, 7, 152, 1, // Opcode: CMP_SULT_D_MMR6
+/* 2613 */ MCD::OPC_FilterValue, 251, 6, 59, 0, 0, // Skip to: 2678
+/* 2619 */ MCD::OPC_ExtractField, 11, 5, // Inst{15-11} ...
+/* 2622 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2636
+/* 2627 */ MCD::OPC_CheckPredicate, 26, 42, 2, 0, // Skip to: 3186
+/* 2632 */ MCD::OPC_Decode, 181, 11, 112, // Opcode: FNEG_S_MMR6
+/* 2636 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 2650
+/* 2641 */ MCD::OPC_CheckPredicate, 26, 28, 2, 0, // Skip to: 3186
+/* 2646 */ MCD::OPC_Decode, 157, 8, 112, // Opcode: CVT_S_W_MMR6
+/* 2650 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 2664
+/* 2655 */ MCD::OPC_CheckPredicate, 23, 14, 2, 0, // Skip to: 3186
+/* 2660 */ MCD::OPC_Decode, 142, 8, 110, // Opcode: CVT_D_L_MMR6
+/* 2664 */ MCD::OPC_FilterValue, 11, 5, 2, 0, // Skip to: 3186
+/* 2669 */ MCD::OPC_CheckPredicate, 23, 0, 2, 0, // Skip to: 3186
+/* 2674 */ MCD::OPC_Decode, 154, 8, 109, // Opcode: CVT_S_L_MMR6
+/* 2678 */ MCD::OPC_FilterValue, 133, 7, 10, 0, 0, // Skip to: 2694
+/* 2684 */ MCD::OPC_CheckPredicate, 26, 241, 1, 0, // Skip to: 3186
+/* 2689 */ MCD::OPC_Decode, 205, 7, 151, 1, // Opcode: CMP_SLE_S_MMR6
+/* 2694 */ MCD::OPC_FilterValue, 149, 7, 10, 0, 0, // Skip to: 2710
+/* 2700 */ MCD::OPC_CheckPredicate, 26, 225, 1, 0, // Skip to: 3186
+/* 2705 */ MCD::OPC_Decode, 203, 7, 152, 1, // Opcode: CMP_SLE_D_MMR6
+/* 2710 */ MCD::OPC_FilterValue, 184, 7, 10, 0, 0, // Skip to: 2726
+/* 2716 */ MCD::OPC_CheckPredicate, 26, 209, 1, 0, // Skip to: 3186
+/* 2721 */ MCD::OPC_Decode, 200, 13, 158, 1, // Opcode: MADDF_D_MMR6
+/* 2726 */ MCD::OPC_FilterValue, 197, 7, 10, 0, 0, // Skip to: 2742
+/* 2732 */ MCD::OPC_CheckPredicate, 26, 193, 1, 0, // Skip to: 3186
+/* 2737 */ MCD::OPC_Decode, 217, 7, 151, 1, // Opcode: CMP_SULE_S_MMR6
+/* 2742 */ MCD::OPC_FilterValue, 213, 7, 10, 0, 0, // Skip to: 2758
+/* 2748 */ MCD::OPC_CheckPredicate, 26, 177, 1, 0, // Skip to: 3186
+/* 2753 */ MCD::OPC_Decode, 215, 7, 152, 1, // Opcode: CMP_SULE_D_MMR6
+/* 2758 */ MCD::OPC_FilterValue, 248, 7, 166, 1, 0, // Skip to: 3186
+/* 2764 */ MCD::OPC_CheckPredicate, 26, 161, 1, 0, // Skip to: 3186
+/* 2769 */ MCD::OPC_Decode, 251, 14, 158, 1, // Opcode: MSUBF_D_MMR6
+/* 2774 */ MCD::OPC_FilterValue, 24, 59, 0, 0, // Skip to: 2838
+/* 2779 */ MCD::OPC_ExtractField, 12, 4, // Inst{15-12} ...
+/* 2782 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2796
+/* 2787 */ MCD::OPC_CheckPredicate, 24, 138, 1, 0, // Skip to: 3186
+/* 2792 */ MCD::OPC_Decode, 211, 16, 88, // Opcode: PREF_MMR6
+/* 2796 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2817
+/* 2801 */ MCD::OPC_CheckPredicate, 24, 124, 1, 0, // Skip to: 3186
+/* 2806 */ MCD::OPC_CheckField, 9, 3, 0, 117, 1, 0, // Skip to: 3186
+/* 2813 */ MCD::OPC_Decode, 134, 13, 122, // Opcode: LL_MMR6
+/* 2817 */ MCD::OPC_FilterValue, 11, 108, 1, 0, // Skip to: 3186
+/* 2822 */ MCD::OPC_CheckPredicate, 24, 103, 1, 0, // Skip to: 3186
+/* 2827 */ MCD::OPC_CheckField, 9, 3, 0, 96, 1, 0, // Skip to: 3186
+/* 2834 */ MCD::OPC_Decode, 161, 17, 122, // Opcode: SC_MMR6
+/* 2838 */ MCD::OPC_FilterValue, 28, 9, 0, 0, // Skip to: 2852
+/* 2843 */ MCD::OPC_CheckPredicate, 24, 82, 1, 0, // Skip to: 3186
+/* 2848 */ MCD::OPC_Decode, 187, 20, 96, // Opcode: XORI_MMR6
+/* 2852 */ MCD::OPC_FilterValue, 29, 27, 0, 0, // Skip to: 2884
+/* 2857 */ MCD::OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2874
+/* 2862 */ MCD::OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2874
+/* 2869 */ MCD::OPC_Decode, 180, 5, 159, 1, // Opcode: BEQZALC_MMR6
+/* 2874 */ MCD::OPC_CheckPredicate, 24, 51, 1, 0, // Skip to: 3186
+/* 2879 */ MCD::OPC_Decode, 176, 5, 159, 1, // Opcode: BEQC_MMR6
+/* 2884 */ MCD::OPC_FilterValue, 30, 71, 0, 0, // Skip to: 2960
+/* 2889 */ MCD::OPC_ExtractField, 19, 2, // Inst{20-19} ...
+/* 2892 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2907
+/* 2897 */ MCD::OPC_CheckPredicate, 24, 28, 1, 0, // Skip to: 3186
+/* 2902 */ MCD::OPC_Decode, 136, 4, 160, 1, // Opcode: ADDIUPC_MMR6
+/* 2907 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2922
+/* 2912 */ MCD::OPC_CheckPredicate, 24, 13, 1, 0, // Skip to: 3186
+/* 2917 */ MCD::OPC_Decode, 169, 13, 160, 1, // Opcode: LWPC_MMR6
+/* 2922 */ MCD::OPC_FilterValue, 3, 3, 1, 0, // Skip to: 3186
+/* 2927 */ MCD::OPC_ExtractField, 16, 3, // Inst{18-16} ...
+/* 2930 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2945
+/* 2935 */ MCD::OPC_CheckPredicate, 24, 246, 0, 0, // Skip to: 3186
+/* 2940 */ MCD::OPC_Decode, 237, 4, 161, 1, // Opcode: AUIPC_MMR6
+/* 2945 */ MCD::OPC_FilterValue, 7, 236, 0, 0, // Skip to: 3186
+/* 2950 */ MCD::OPC_CheckPredicate, 24, 231, 0, 0, // Skip to: 3186
+/* 2955 */ MCD::OPC_Decode, 210, 4, 161, 1, // Opcode: ALUIPC_MMR6
+/* 2960 */ MCD::OPC_FilterValue, 31, 27, 0, 0, // Skip to: 2992
+/* 2965 */ MCD::OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2982
+/* 2970 */ MCD::OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2982
+/* 2977 */ MCD::OPC_Decode, 155, 6, 162, 1, // Opcode: BNEZALC_MMR6
+/* 2982 */ MCD::OPC_CheckPredicate, 24, 199, 0, 0, // Skip to: 3186
+/* 2987 */ MCD::OPC_Decode, 143, 6, 162, 1, // Opcode: BNEC_MMR6
+/* 2992 */ MCD::OPC_FilterValue, 32, 26, 0, 0, // Skip to: 3023
+/* 2997 */ MCD::OPC_CheckPredicate, 24, 11, 0, 0, // Skip to: 3013
+/* 3002 */ MCD::OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3013
+/* 3009 */ MCD::OPC_Decode, 176, 12, 91, // Opcode: JIALC_MMR6
+/* 3013 */ MCD::OPC_CheckPredicate, 24, 168, 0, 0, // Skip to: 3186
+/* 3018 */ MCD::OPC_Decode, 185, 5, 163, 1, // Opcode: BEQZC_MMR6
+/* 3023 */ MCD::OPC_FilterValue, 37, 10, 0, 0, // Skip to: 3038
+/* 3028 */ MCD::OPC_CheckPredicate, 24, 153, 0, 0, // Skip to: 3186
+/* 3033 */ MCD::OPC_Decode, 171, 5, 164, 1, // Opcode: BC_MMR6
+/* 3038 */ MCD::OPC_FilterValue, 40, 26, 0, 0, // Skip to: 3069
+/* 3043 */ MCD::OPC_CheckPredicate, 24, 11, 0, 0, // Skip to: 3059
+/* 3048 */ MCD::OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 3059
+/* 3055 */ MCD::OPC_Decode, 179, 12, 91, // Opcode: JIC_MMR6
+/* 3059 */ MCD::OPC_CheckPredicate, 24, 122, 0, 0, // Skip to: 3186
+/* 3064 */ MCD::OPC_Decode, 160, 6, 163, 1, // Opcode: BNEZC_MMR6
+/* 3069 */ MCD::OPC_FilterValue, 45, 10, 0, 0, // Skip to: 3084
+/* 3074 */ MCD::OPC_CheckPredicate, 24, 107, 0, 0, // Skip to: 3186
+/* 3079 */ MCD::OPC_Decode, 140, 5, 164, 1, // Opcode: BALC_MMR6
+/* 3084 */ MCD::OPC_FilterValue, 48, 10, 0, 0, // Skip to: 3099
+/* 3089 */ MCD::OPC_CheckPredicate, 24, 92, 0, 0, // Skip to: 3186
+/* 3094 */ MCD::OPC_Decode, 192, 5, 165, 1, // Opcode: BGEUC_MMR6
+/* 3099 */ MCD::OPC_FilterValue, 52, 9, 0, 0, // Skip to: 3113
+/* 3104 */ MCD::OPC_CheckPredicate, 24, 77, 0, 0, // Skip to: 3186
+/* 3109 */ MCD::OPC_Decode, 218, 4, 96, // Opcode: ANDI_MMR6
+/* 3113 */ MCD::OPC_FilterValue, 53, 10, 0, 0, // Skip to: 3128
+/* 3118 */ MCD::OPC_CheckPredicate, 24, 63, 0, 0, // Skip to: 3186
+/* 3123 */ MCD::OPC_Decode, 246, 5, 166, 1, // Opcode: BLTC_MMR6
+/* 3128 */ MCD::OPC_FilterValue, 56, 10, 0, 0, // Skip to: 3143
+/* 3133 */ MCD::OPC_CheckPredicate, 24, 48, 0, 0, // Skip to: 3186
+/* 3138 */ MCD::OPC_Decode, 249, 5, 167, 1, // Opcode: BLTUC_MMR6
+/* 3143 */ MCD::OPC_FilterValue, 61, 10, 0, 0, // Skip to: 3158
+/* 3148 */ MCD::OPC_CheckPredicate, 24, 33, 0, 0, // Skip to: 3186
+/* 3153 */ MCD::OPC_Decode, 189, 5, 168, 1, // Opcode: BGEC_MMR6
+/* 3158 */ MCD::OPC_FilterValue, 62, 9, 0, 0, // Skip to: 3172
+/* 3163 */ MCD::OPC_CheckPredicate, 24, 18, 0, 0, // Skip to: 3186
+/* 3168 */ MCD::OPC_Decode, 203, 19, 86, // Opcode: SW_MMR6
+/* 3172 */ MCD::OPC_FilterValue, 63, 9, 0, 0, // Skip to: 3186
+/* 3177 */ MCD::OPC_CheckPredicate, 24, 4, 0, 0, // Skip to: 3186
+/* 3182 */ MCD::OPC_Decode, 185, 13, 86, // Opcode: LW_MMR6
+/* 3186 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMicroMipsR6_Ambiguous32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 18
+/* 8 */ MCD::OPC_CheckPredicate, 24, 84, 0, 0, // Skip to: 97
+/* 13 */ MCD::OPC_Decode, 170, 6, 159, 1, // Opcode: BOVC_MMR6
+/* 18 */ MCD::OPC_FilterValue, 31, 10, 0, 0, // Skip to: 33
+/* 23 */ MCD::OPC_CheckPredicate, 24, 69, 0, 0, // Skip to: 97
+/* 28 */ MCD::OPC_Decode, 163, 6, 162, 1, // Opcode: BNVC_MMR6
+/* 33 */ MCD::OPC_FilterValue, 48, 27, 0, 0, // Skip to: 65
+/* 38 */ MCD::OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 55
+/* 43 */ MCD::OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 55
+/* 50 */ MCD::OPC_Decode, 238, 5, 165, 1, // Opcode: BLEZALC_MMR6
+/* 55 */ MCD::OPC_CheckPredicate, 24, 37, 0, 0, // Skip to: 97
+/* 60 */ MCD::OPC_Decode, 197, 5, 165, 1, // Opcode: BGEZALC_MMR6
+/* 65 */ MCD::OPC_FilterValue, 56, 27, 0, 0, // Skip to: 97
+/* 70 */ MCD::OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 87
+/* 75 */ MCD::OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 87
+/* 82 */ MCD::OPC_Decode, 209, 5, 167, 1, // Opcode: BGTZALC_MMR6
+/* 87 */ MCD::OPC_CheckPredicate, 24, 5, 0, 0, // Skip to: 97
+/* 92 */ MCD::OPC_Decode, 254, 5, 167, 1, // Opcode: BLTZALC_MMR6
+/* 97 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 101, 4, 0, // Skip to: 1133
+/* 8 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 63, 0, 0, // Skip to: 79
+/* 16 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 19 */ MCD::OPC_FilterValue, 0, 178, 66, 0, // Skip to: 17098
+/* 24 */ MCD::OPC_ExtractField, 6, 15, // Inst{20-6} ...
+/* 27 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 41
+/* 32 */ MCD::OPC_CheckPredicate, 27, 32, 0, 0, // Skip to: 69
+/* 37 */ MCD::OPC_Decode, 230, 18, 0, // Opcode: SSNOP
+/* 41 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 55
+/* 46 */ MCD::OPC_CheckPredicate, 27, 18, 0, 0, // Skip to: 69
+/* 51 */ MCD::OPC_Decode, 145, 10, 0, // Opcode: EHB
+/* 55 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 69
+/* 60 */ MCD::OPC_CheckPredicate, 28, 4, 0, 0, // Skip to: 69
+/* 65 */ MCD::OPC_Decode, 152, 16, 0, // Opcode: PAUSE
+/* 69 */ MCD::OPC_CheckPredicate, 27, 128, 66, 0, // Skip to: 17098
+/* 74 */ MCD::OPC_Decode, 149, 18, 169, 1, // Opcode: SLL
+/* 79 */ MCD::OPC_FilterValue, 1, 47, 0, 0, // Skip to: 131
+/* 84 */ MCD::OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 87 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 109
+/* 92 */ MCD::OPC_CheckPredicate, 29, 105, 66, 0, // Skip to: 17098
+/* 97 */ MCD::OPC_CheckField, 6, 5, 0, 98, 66, 0, // Skip to: 17098
+/* 104 */ MCD::OPC_Decode, 212, 14, 170, 1, // Opcode: MOVF_I
+/* 109 */ MCD::OPC_FilterValue, 1, 88, 66, 0, // Skip to: 17098
+/* 114 */ MCD::OPC_CheckPredicate, 29, 83, 66, 0, // Skip to: 17098
+/* 119 */ MCD::OPC_CheckField, 6, 5, 0, 76, 66, 0, // Skip to: 17098
+/* 126 */ MCD::OPC_Decode, 232, 14, 170, 1, // Opcode: MOVT_I
+/* 131 */ MCD::OPC_FilterValue, 2, 33, 0, 0, // Skip to: 169
+/* 136 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 139 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 154
+/* 144 */ MCD::OPC_CheckPredicate, 27, 53, 66, 0, // Skip to: 17098
+/* 149 */ MCD::OPC_Decode, 208, 18, 169, 1, // Opcode: SRL
+/* 154 */ MCD::OPC_FilterValue, 1, 43, 66, 0, // Skip to: 17098
+/* 159 */ MCD::OPC_CheckPredicate, 28, 38, 66, 0, // Skip to: 17098
+/* 164 */ MCD::OPC_Decode, 242, 16, 169, 1, // Opcode: ROTR
+/* 169 */ MCD::OPC_FilterValue, 3, 17, 0, 0, // Skip to: 191
+/* 174 */ MCD::OPC_CheckPredicate, 27, 23, 66, 0, // Skip to: 17098
+/* 179 */ MCD::OPC_CheckField, 21, 5, 0, 16, 66, 0, // Skip to: 17098
+/* 186 */ MCD::OPC_Decode, 188, 18, 169, 1, // Opcode: SRA
+/* 191 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 212
+/* 196 */ MCD::OPC_CheckPredicate, 27, 1, 66, 0, // Skip to: 17098
+/* 201 */ MCD::OPC_CheckField, 6, 5, 0, 250, 65, 0, // Skip to: 17098
+/* 208 */ MCD::OPC_Decode, 158, 18, 43, // Opcode: SLLV
+/* 212 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 234
+/* 217 */ MCD::OPC_CheckPredicate, 30, 236, 65, 0, // Skip to: 17098
+/* 222 */ MCD::OPC_CheckField, 8, 3, 0, 229, 65, 0, // Skip to: 17098
+/* 229 */ MCD::OPC_Decode, 136, 13, 171, 1, // Opcode: LSA
+/* 234 */ MCD::OPC_FilterValue, 6, 31, 0, 0, // Skip to: 270
+/* 239 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 242 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 256
+/* 247 */ MCD::OPC_CheckPredicate, 27, 206, 65, 0, // Skip to: 17098
+/* 252 */ MCD::OPC_Decode, 223, 18, 43, // Opcode: SRLV
+/* 256 */ MCD::OPC_FilterValue, 1, 197, 65, 0, // Skip to: 17098
+/* 261 */ MCD::OPC_CheckPredicate, 28, 192, 65, 0, // Skip to: 17098
+/* 266 */ MCD::OPC_Decode, 243, 16, 43, // Opcode: ROTRV
+/* 270 */ MCD::OPC_FilterValue, 7, 16, 0, 0, // Skip to: 291
+/* 275 */ MCD::OPC_CheckPredicate, 27, 178, 65, 0, // Skip to: 17098
+/* 280 */ MCD::OPC_CheckField, 6, 5, 0, 171, 65, 0, // Skip to: 17098
+/* 287 */ MCD::OPC_Decode, 201, 18, 43, // Opcode: SRAV
+/* 291 */ MCD::OPC_FilterValue, 8, 33, 0, 0, // Skip to: 329
+/* 296 */ MCD::OPC_ExtractField, 6, 15, // Inst{20-6} ...
+/* 299 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 314
+/* 304 */ MCD::OPC_CheckPredicate, 31, 149, 65, 0, // Skip to: 17098
+/* 309 */ MCD::OPC_Decode, 180, 12, 172, 1, // Opcode: JR
+/* 314 */ MCD::OPC_FilterValue, 16, 139, 65, 0, // Skip to: 17098
+/* 319 */ MCD::OPC_CheckPredicate, 32, 134, 65, 0, // Skip to: 17098
+/* 324 */ MCD::OPC_Decode, 187, 12, 172, 1, // Opcode: JR_HB
+/* 329 */ MCD::OPC_FilterValue, 9, 45, 0, 0, // Skip to: 379
+/* 334 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 337 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 358
+/* 342 */ MCD::OPC_CheckPredicate, 33, 111, 65, 0, // Skip to: 17098
+/* 347 */ MCD::OPC_CheckField, 16, 5, 0, 104, 65, 0, // Skip to: 17098
+/* 354 */ MCD::OPC_Decode, 159, 12, 14, // Opcode: JALR
+/* 358 */ MCD::OPC_FilterValue, 16, 95, 65, 0, // Skip to: 17098
+/* 363 */ MCD::OPC_CheckPredicate, 34, 90, 65, 0, // Skip to: 17098
+/* 368 */ MCD::OPC_CheckField, 16, 5, 0, 83, 65, 0, // Skip to: 17098
+/* 375 */ MCD::OPC_Decode, 167, 12, 14, // Opcode: JALR_HB
+/* 379 */ MCD::OPC_FilterValue, 10, 17, 0, 0, // Skip to: 401
+/* 384 */ MCD::OPC_CheckPredicate, 35, 69, 65, 0, // Skip to: 17098
+/* 389 */ MCD::OPC_CheckField, 6, 5, 0, 62, 65, 0, // Skip to: 17098
+/* 396 */ MCD::OPC_Decode, 244, 14, 173, 1, // Opcode: MOVZ_I_I
+/* 401 */ MCD::OPC_FilterValue, 11, 17, 0, 0, // Skip to: 423
+/* 406 */ MCD::OPC_CheckPredicate, 35, 47, 65, 0, // Skip to: 17098
+/* 411 */ MCD::OPC_CheckField, 6, 5, 0, 40, 65, 0, // Skip to: 17098
+/* 418 */ MCD::OPC_Decode, 224, 14, 173, 1, // Opcode: MOVN_I_I
+/* 423 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 438
+/* 428 */ MCD::OPC_CheckPredicate, 27, 25, 65, 0, // Skip to: 17098
+/* 433 */ MCD::OPC_Decode, 210, 19, 174, 1, // Opcode: SYSCALL
+/* 438 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 452
+/* 443 */ MCD::OPC_CheckPredicate, 27, 10, 65, 0, // Skip to: 17098
+/* 448 */ MCD::OPC_Decode, 174, 6, 44, // Opcode: BREAK
+/* 452 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 467
+/* 457 */ MCD::OPC_CheckPredicate, 36, 252, 64, 0, // Skip to: 17098
+/* 462 */ MCD::OPC_Decode, 204, 19, 175, 1, // Opcode: SYNC
+/* 467 */ MCD::OPC_FilterValue, 16, 51, 0, 0, // Skip to: 523
+/* 472 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 475 */ MCD::OPC_FilterValue, 0, 234, 64, 0, // Skip to: 17098
+/* 480 */ MCD::OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 483 */ MCD::OPC_FilterValue, 0, 226, 64, 0, // Skip to: 17098
+/* 488 */ MCD::OPC_ExtractField, 23, 3, // Inst{25-23} ...
+/* 491 */ MCD::OPC_FilterValue, 0, 218, 64, 0, // Skip to: 17098
+/* 496 */ MCD::OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 513
+/* 501 */ MCD::OPC_CheckField, 21, 2, 0, 5, 0, 0, // Skip to: 513
+/* 508 */ MCD::OPC_Decode, 149, 14, 176, 1, // Opcode: MFHI
+/* 513 */ MCD::OPC_CheckPredicate, 37, 196, 64, 0, // Skip to: 17098
+/* 518 */ MCD::OPC_Decode, 152, 14, 177, 1, // Opcode: MFHI_DSP
+/* 523 */ MCD::OPC_FilterValue, 17, 43, 0, 0, // Skip to: 571
+/* 528 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 531 */ MCD::OPC_FilterValue, 0, 178, 64, 0, // Skip to: 17098
+/* 536 */ MCD::OPC_ExtractField, 13, 8, // Inst{20-13} ...
+/* 539 */ MCD::OPC_FilterValue, 0, 170, 64, 0, // Skip to: 17098
+/* 544 */ MCD::OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 561
+/* 549 */ MCD::OPC_CheckField, 11, 2, 0, 5, 0, 0, // Skip to: 561
+/* 556 */ MCD::OPC_Decode, 164, 15, 172, 1, // Opcode: MTHI
+/* 561 */ MCD::OPC_CheckPredicate, 37, 148, 64, 0, // Skip to: 17098
+/* 566 */ MCD::OPC_Decode, 166, 15, 178, 1, // Opcode: MTHI_DSP
+/* 571 */ MCD::OPC_FilterValue, 18, 51, 0, 0, // Skip to: 627
+/* 576 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 579 */ MCD::OPC_FilterValue, 0, 130, 64, 0, // Skip to: 17098
+/* 584 */ MCD::OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 587 */ MCD::OPC_FilterValue, 0, 122, 64, 0, // Skip to: 17098
+/* 592 */ MCD::OPC_ExtractField, 23, 3, // Inst{25-23} ...
+/* 595 */ MCD::OPC_FilterValue, 0, 114, 64, 0, // Skip to: 17098
+/* 600 */ MCD::OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 617
+/* 605 */ MCD::OPC_CheckField, 21, 2, 0, 5, 0, 0, // Skip to: 617
+/* 612 */ MCD::OPC_Decode, 155, 14, 176, 1, // Opcode: MFLO
+/* 617 */ MCD::OPC_CheckPredicate, 37, 92, 64, 0, // Skip to: 17098
+/* 622 */ MCD::OPC_Decode, 158, 14, 177, 1, // Opcode: MFLO_DSP
+/* 627 */ MCD::OPC_FilterValue, 19, 43, 0, 0, // Skip to: 675
+/* 632 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 635 */ MCD::OPC_FilterValue, 0, 74, 64, 0, // Skip to: 17098
+/* 640 */ MCD::OPC_ExtractField, 13, 8, // Inst{20-13} ...
+/* 643 */ MCD::OPC_FilterValue, 0, 66, 64, 0, // Skip to: 17098
+/* 648 */ MCD::OPC_CheckPredicate, 31, 12, 0, 0, // Skip to: 665
+/* 653 */ MCD::OPC_CheckField, 11, 2, 0, 5, 0, 0, // Skip to: 665
+/* 660 */ MCD::OPC_Decode, 171, 15, 172, 1, // Opcode: MTLO
+/* 665 */ MCD::OPC_CheckPredicate, 37, 44, 64, 0, // Skip to: 17098
+/* 670 */ MCD::OPC_Decode, 173, 15, 179, 1, // Opcode: MTLO_DSP
+/* 675 */ MCD::OPC_FilterValue, 21, 17, 0, 0, // Skip to: 697
+/* 680 */ MCD::OPC_CheckPredicate, 38, 29, 64, 0, // Skip to: 17098
+/* 685 */ MCD::OPC_CheckField, 8, 3, 0, 22, 64, 0, // Skip to: 17098
+/* 692 */ MCD::OPC_Decode, 176, 9, 180, 1, // Opcode: DLSA
+/* 697 */ MCD::OPC_FilterValue, 24, 42, 0, 0, // Skip to: 744
+/* 702 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 705 */ MCD::OPC_FilterValue, 0, 4, 64, 0, // Skip to: 17098
+/* 710 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 713 */ MCD::OPC_FilterValue, 0, 252, 63, 0, // Skip to: 17098
+/* 718 */ MCD::OPC_CheckPredicate, 31, 11, 0, 0, // Skip to: 734
+/* 723 */ MCD::OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 734
+/* 730 */ MCD::OPC_Decode, 210, 15, 68, // Opcode: MULT
+/* 734 */ MCD::OPC_CheckPredicate, 37, 231, 63, 0, // Skip to: 17098
+/* 739 */ MCD::OPC_Decode, 213, 15, 181, 1, // Opcode: MULT_DSP
+/* 744 */ MCD::OPC_FilterValue, 25, 42, 0, 0, // Skip to: 791
+/* 749 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 752 */ MCD::OPC_FilterValue, 0, 213, 63, 0, // Skip to: 17098
+/* 757 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 760 */ MCD::OPC_FilterValue, 0, 205, 63, 0, // Skip to: 17098
+/* 765 */ MCD::OPC_CheckPredicate, 31, 11, 0, 0, // Skip to: 781
+/* 770 */ MCD::OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 781
+/* 777 */ MCD::OPC_Decode, 216, 15, 68, // Opcode: MULTu
+/* 781 */ MCD::OPC_CheckPredicate, 37, 184, 63, 0, // Skip to: 17098
+/* 786 */ MCD::OPC_Decode, 211, 15, 181, 1, // Opcode: MULTU_DSP
+/* 791 */ MCD::OPC_FilterValue, 26, 16, 0, 0, // Skip to: 812
+/* 796 */ MCD::OPC_CheckPredicate, 31, 169, 63, 0, // Skip to: 17098
+/* 801 */ MCD::OPC_CheckField, 6, 10, 0, 162, 63, 0, // Skip to: 17098
+/* 808 */ MCD::OPC_Decode, 178, 17, 68, // Opcode: SDIV
+/* 812 */ MCD::OPC_FilterValue, 27, 16, 0, 0, // Skip to: 833
+/* 817 */ MCD::OPC_CheckPredicate, 31, 148, 63, 0, // Skip to: 17098
+/* 822 */ MCD::OPC_CheckField, 6, 10, 0, 141, 63, 0, // Skip to: 17098
+/* 829 */ MCD::OPC_Decode, 164, 20, 68, // Opcode: UDIV
+/* 833 */ MCD::OPC_FilterValue, 32, 16, 0, 0, // Skip to: 854
+/* 838 */ MCD::OPC_CheckPredicate, 27, 127, 63, 0, // Skip to: 17098
+/* 843 */ MCD::OPC_CheckField, 6, 5, 0, 120, 63, 0, // Skip to: 17098
+/* 850 */ MCD::OPC_Decode, 133, 4, 49, // Opcode: ADD
+/* 854 */ MCD::OPC_FilterValue, 33, 16, 0, 0, // Skip to: 875
+/* 859 */ MCD::OPC_CheckPredicate, 27, 106, 63, 0, // Skip to: 17098
+/* 864 */ MCD::OPC_CheckField, 6, 5, 0, 99, 63, 0, // Skip to: 17098
+/* 871 */ MCD::OPC_Decode, 205, 4, 49, // Opcode: ADDu
+/* 875 */ MCD::OPC_FilterValue, 34, 16, 0, 0, // Skip to: 896
+/* 880 */ MCD::OPC_CheckPredicate, 27, 85, 63, 0, // Skip to: 17098
+/* 885 */ MCD::OPC_CheckField, 6, 5, 0, 78, 63, 0, // Skip to: 17098
+/* 892 */ MCD::OPC_Decode, 237, 18, 49, // Opcode: SUB
+/* 896 */ MCD::OPC_FilterValue, 35, 16, 0, 0, // Skip to: 917
+/* 901 */ MCD::OPC_CheckPredicate, 27, 64, 63, 0, // Skip to: 17098
+/* 906 */ MCD::OPC_CheckField, 6, 5, 0, 57, 63, 0, // Skip to: 17098
+/* 913 */ MCD::OPC_Decode, 165, 19, 49, // Opcode: SUBu
+/* 917 */ MCD::OPC_FilterValue, 36, 16, 0, 0, // Skip to: 938
+/* 922 */ MCD::OPC_CheckPredicate, 27, 43, 63, 0, // Skip to: 17098
+/* 927 */ MCD::OPC_CheckField, 6, 5, 0, 36, 63, 0, // Skip to: 17098
+/* 934 */ MCD::OPC_Decode, 211, 4, 49, // Opcode: AND
+/* 938 */ MCD::OPC_FilterValue, 37, 16, 0, 0, // Skip to: 959
+/* 943 */ MCD::OPC_CheckPredicate, 27, 22, 63, 0, // Skip to: 17098
+/* 948 */ MCD::OPC_CheckField, 6, 5, 0, 15, 63, 0, // Skip to: 17098
+/* 955 */ MCD::OPC_Decode, 137, 16, 49, // Opcode: OR
+/* 959 */ MCD::OPC_FilterValue, 38, 16, 0, 0, // Skip to: 980
+/* 964 */ MCD::OPC_CheckPredicate, 27, 1, 63, 0, // Skip to: 17098
+/* 969 */ MCD::OPC_CheckField, 6, 5, 0, 250, 62, 0, // Skip to: 17098
+/* 976 */ MCD::OPC_Decode, 182, 20, 49, // Opcode: XOR
+/* 980 */ MCD::OPC_FilterValue, 39, 16, 0, 0, // Skip to: 1001
+/* 985 */ MCD::OPC_CheckPredicate, 27, 236, 62, 0, // Skip to: 17098
+/* 990 */ MCD::OPC_CheckField, 6, 5, 0, 229, 62, 0, // Skip to: 17098
+/* 997 */ MCD::OPC_Decode, 255, 15, 49, // Opcode: NOR
+/* 1001 */ MCD::OPC_FilterValue, 42, 16, 0, 0, // Skip to: 1022
+/* 1006 */ MCD::OPC_CheckPredicate, 27, 215, 62, 0, // Skip to: 17098
+/* 1011 */ MCD::OPC_CheckField, 6, 5, 0, 208, 62, 0, // Skip to: 17098
+/* 1018 */ MCD::OPC_Decode, 166, 18, 49, // Opcode: SLT
+/* 1022 */ MCD::OPC_FilterValue, 43, 16, 0, 0, // Skip to: 1043
+/* 1027 */ MCD::OPC_CheckPredicate, 27, 194, 62, 0, // Skip to: 17098
+/* 1032 */ MCD::OPC_CheckField, 6, 5, 0, 187, 62, 0, // Skip to: 17098
+/* 1039 */ MCD::OPC_Decode, 175, 18, 49, // Opcode: SLTu
+/* 1043 */ MCD::OPC_FilterValue, 48, 10, 0, 0, // Skip to: 1058
+/* 1048 */ MCD::OPC_CheckPredicate, 36, 173, 62, 0, // Skip to: 17098
+/* 1053 */ MCD::OPC_Decode, 237, 19, 182, 1, // Opcode: TGE
+/* 1058 */ MCD::OPC_FilterValue, 49, 10, 0, 0, // Skip to: 1073
+/* 1063 */ MCD::OPC_CheckPredicate, 36, 158, 62, 0, // Skip to: 17098
+/* 1068 */ MCD::OPC_Decode, 242, 19, 182, 1, // Opcode: TGEU
+/* 1073 */ MCD::OPC_FilterValue, 50, 10, 0, 0, // Skip to: 1088
+/* 1078 */ MCD::OPC_CheckPredicate, 36, 143, 62, 0, // Skip to: 17098
+/* 1083 */ MCD::OPC_Decode, 141, 20, 182, 1, // Opcode: TLT
+/* 1088 */ MCD::OPC_FilterValue, 51, 10, 0, 0, // Skip to: 1103
+/* 1093 */ MCD::OPC_CheckPredicate, 36, 128, 62, 0, // Skip to: 17098
+/* 1098 */ MCD::OPC_Decode, 145, 20, 182, 1, // Opcode: TLTU
+/* 1103 */ MCD::OPC_FilterValue, 52, 10, 0, 0, // Skip to: 1118
+/* 1108 */ MCD::OPC_CheckPredicate, 36, 113, 62, 0, // Skip to: 17098
+/* 1113 */ MCD::OPC_Decode, 233, 19, 182, 1, // Opcode: TEQ
+/* 1118 */ MCD::OPC_FilterValue, 54, 103, 62, 0, // Skip to: 17098
+/* 1123 */ MCD::OPC_CheckPredicate, 36, 98, 62, 0, // Skip to: 17098
+/* 1128 */ MCD::OPC_Decode, 148, 20, 182, 1, // Opcode: TNE
+/* 1133 */ MCD::OPC_FilterValue, 1, 250, 0, 0, // Skip to: 1388
+/* 1138 */ MCD::OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 1141 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1156
+/* 1146 */ MCD::OPC_CheckPredicate, 27, 75, 62, 0, // Skip to: 17098
+/* 1151 */ MCD::OPC_Decode, 250, 5, 183, 1, // Opcode: BLTZ
+/* 1156 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1171
+/* 1161 */ MCD::OPC_CheckPredicate, 27, 60, 62, 0, // Skip to: 17098
+/* 1166 */ MCD::OPC_Decode, 193, 5, 183, 1, // Opcode: BGEZ
+/* 1171 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1186
+/* 1176 */ MCD::OPC_CheckPredicate, 39, 45, 62, 0, // Skip to: 17098
+/* 1181 */ MCD::OPC_Decode, 133, 6, 183, 1, // Opcode: BLTZL
+/* 1186 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1201
+/* 1191 */ MCD::OPC_CheckPredicate, 39, 30, 62, 0, // Skip to: 17098
+/* 1196 */ MCD::OPC_Decode, 204, 5, 183, 1, // Opcode: BGEZL
+/* 1201 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1216
+/* 1206 */ MCD::OPC_CheckPredicate, 39, 15, 62, 0, // Skip to: 17098
+/* 1211 */ MCD::OPC_Decode, 238, 19, 161, 1, // Opcode: TGEI
+/* 1216 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1231
+/* 1221 */ MCD::OPC_CheckPredicate, 39, 0, 62, 0, // Skip to: 17098
+/* 1226 */ MCD::OPC_Decode, 239, 19, 161, 1, // Opcode: TGEIU
+/* 1231 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1246
+/* 1236 */ MCD::OPC_CheckPredicate, 39, 241, 61, 0, // Skip to: 17098
+/* 1241 */ MCD::OPC_Decode, 142, 20, 161, 1, // Opcode: TLTI
+/* 1246 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1261
+/* 1251 */ MCD::OPC_CheckPredicate, 39, 226, 61, 0, // Skip to: 17098
+/* 1256 */ MCD::OPC_Decode, 163, 20, 161, 1, // Opcode: TTLTIU
+/* 1261 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1276
+/* 1266 */ MCD::OPC_CheckPredicate, 39, 211, 61, 0, // Skip to: 17098
+/* 1271 */ MCD::OPC_Decode, 234, 19, 161, 1, // Opcode: TEQI
+/* 1276 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1291
+/* 1281 */ MCD::OPC_CheckPredicate, 39, 196, 61, 0, // Skip to: 17098
+/* 1286 */ MCD::OPC_Decode, 149, 20, 161, 1, // Opcode: TNEI
+/* 1291 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 1306
+/* 1296 */ MCD::OPC_CheckPredicate, 31, 181, 61, 0, // Skip to: 17098
+/* 1301 */ MCD::OPC_Decode, 252, 5, 183, 1, // Opcode: BLTZAL
+/* 1306 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 1321
+/* 1311 */ MCD::OPC_CheckPredicate, 31, 166, 61, 0, // Skip to: 17098
+/* 1316 */ MCD::OPC_Decode, 195, 5, 183, 1, // Opcode: BGEZAL
+/* 1321 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 1336
+/* 1326 */ MCD::OPC_CheckPredicate, 39, 151, 61, 0, // Skip to: 17098
+/* 1331 */ MCD::OPC_Decode, 255, 5, 183, 1, // Opcode: BLTZALL
+/* 1336 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 1351
+/* 1341 */ MCD::OPC_CheckPredicate, 39, 136, 61, 0, // Skip to: 17098
+/* 1346 */ MCD::OPC_Decode, 198, 5, 183, 1, // Opcode: BGEZALL
+/* 1351 */ MCD::OPC_FilterValue, 28, 17, 0, 0, // Skip to: 1373
+/* 1356 */ MCD::OPC_CheckPredicate, 40, 121, 61, 0, // Skip to: 17098
+/* 1361 */ MCD::OPC_CheckField, 21, 5, 0, 114, 61, 0, // Skip to: 17098
+/* 1368 */ MCD::OPC_Decode, 171, 6, 184, 1, // Opcode: BPOSGE32
+/* 1373 */ MCD::OPC_FilterValue, 31, 104, 61, 0, // Skip to: 17098
+/* 1378 */ MCD::OPC_CheckPredicate, 28, 99, 61, 0, // Skip to: 17098
+/* 1383 */ MCD::OPC_Decode, 205, 19, 185, 1, // Opcode: SYNCI
+/* 1388 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1403
+/* 1393 */ MCD::OPC_CheckPredicate, 27, 84, 61, 0, // Skip to: 17098
+/* 1398 */ MCD::OPC_Decode, 157, 12, 186, 1, // Opcode: J
+/* 1403 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1418
+/* 1408 */ MCD::OPC_CheckPredicate, 27, 69, 61, 0, // Skip to: 17098
+/* 1413 */ MCD::OPC_Decode, 158, 12, 186, 1, // Opcode: JAL
+/* 1418 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1433
+/* 1423 */ MCD::OPC_CheckPredicate, 27, 54, 61, 0, // Skip to: 17098
+/* 1428 */ MCD::OPC_Decode, 172, 5, 187, 1, // Opcode: BEQ
+/* 1433 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1448
+/* 1438 */ MCD::OPC_CheckPredicate, 27, 39, 61, 0, // Skip to: 17098
+/* 1443 */ MCD::OPC_Decode, 139, 6, 187, 1, // Opcode: BNE
+/* 1448 */ MCD::OPC_FilterValue, 6, 17, 0, 0, // Skip to: 1470
+/* 1453 */ MCD::OPC_CheckPredicate, 27, 24, 61, 0, // Skip to: 17098
+/* 1458 */ MCD::OPC_CheckField, 16, 5, 0, 17, 61, 0, // Skip to: 17098
+/* 1465 */ MCD::OPC_Decode, 235, 5, 183, 1, // Opcode: BLEZ
+/* 1470 */ MCD::OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1492
+/* 1475 */ MCD::OPC_CheckPredicate, 27, 2, 61, 0, // Skip to: 17098
+/* 1480 */ MCD::OPC_CheckField, 16, 5, 0, 251, 60, 0, // Skip to: 17098
+/* 1487 */ MCD::OPC_Decode, 206, 5, 183, 1, // Opcode: BGTZ
+/* 1492 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1507
+/* 1497 */ MCD::OPC_CheckPredicate, 31, 236, 60, 0, // Skip to: 17098
+/* 1502 */ MCD::OPC_Decode, 201, 4, 188, 1, // Opcode: ADDi
+/* 1507 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1522
+/* 1512 */ MCD::OPC_CheckPredicate, 27, 221, 60, 0, // Skip to: 17098
+/* 1517 */ MCD::OPC_Decode, 203, 4, 188, 1, // Opcode: ADDiu
+/* 1522 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1537
+/* 1527 */ MCD::OPC_CheckPredicate, 27, 206, 60, 0, // Skip to: 17098
+/* 1532 */ MCD::OPC_Decode, 169, 18, 188, 1, // Opcode: SLTi
+/* 1537 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1552
+/* 1542 */ MCD::OPC_CheckPredicate, 27, 191, 60, 0, // Skip to: 17098
+/* 1547 */ MCD::OPC_Decode, 172, 18, 188, 1, // Opcode: SLTiu
+/* 1552 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1567
+/* 1557 */ MCD::OPC_CheckPredicate, 27, 176, 60, 0, // Skip to: 17098
+/* 1562 */ MCD::OPC_Decode, 222, 4, 189, 1, // Opcode: ANDi
+/* 1567 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1582
+/* 1572 */ MCD::OPC_CheckPredicate, 27, 161, 60, 0, // Skip to: 17098
+/* 1577 */ MCD::OPC_Decode, 146, 16, 189, 1, // Opcode: ORi
+/* 1582 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1597
+/* 1587 */ MCD::OPC_CheckPredicate, 27, 146, 60, 0, // Skip to: 17098
+/* 1592 */ MCD::OPC_Decode, 191, 20, 189, 1, // Opcode: XORi
+/* 1597 */ MCD::OPC_FilterValue, 15, 16, 0, 0, // Skip to: 1618
+/* 1602 */ MCD::OPC_CheckPredicate, 27, 131, 60, 0, // Skip to: 17098
+/* 1607 */ MCD::OPC_CheckField, 21, 5, 0, 124, 60, 0, // Skip to: 17098
+/* 1614 */ MCD::OPC_Decode, 143, 13, 91, // Opcode: LUi
+/* 1618 */ MCD::OPC_FilterValue, 16, 187, 2, 0, // Skip to: 2322
+/* 1623 */ MCD::OPC_ExtractField, 3, 1, // Inst{3} ...
+/* 1626 */ MCD::OPC_FilterValue, 0, 190, 1, 0, // Skip to: 2077
+/* 1631 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 1634 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1656
+/* 1639 */ MCD::OPC_CheckPredicate, 27, 94, 60, 0, // Skip to: 17098
+/* 1644 */ MCD::OPC_CheckField, 4, 7, 0, 87, 60, 0, // Skip to: 17098
+/* 1651 */ MCD::OPC_Decode, 131, 14, 190, 1, // Opcode: MFC0
+/* 1656 */ MCD::OPC_FilterValue, 3, 63, 0, 0, // Skip to: 1724
+/* 1661 */ MCD::OPC_ExtractField, 4, 7, // Inst{10-4} ...
+/* 1664 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1679
+/* 1669 */ MCD::OPC_CheckPredicate, 41, 64, 60, 0, // Skip to: 17098
+/* 1674 */ MCD::OPC_Decode, 139, 14, 190, 1, // Opcode: MFGC0
+/* 1679 */ MCD::OPC_FilterValue, 32, 10, 0, 0, // Skip to: 1694
+/* 1684 */ MCD::OPC_CheckPredicate, 41, 49, 60, 0, // Skip to: 17098
+/* 1689 */ MCD::OPC_Decode, 154, 15, 191, 1, // Opcode: MTGC0
+/* 1694 */ MCD::OPC_FilterValue, 64, 10, 0, 0, // Skip to: 1709
+/* 1699 */ MCD::OPC_CheckPredicate, 41, 34, 60, 0, // Skip to: 17098
+/* 1704 */ MCD::OPC_Decode, 147, 14, 190, 1, // Opcode: MFHGC0
+/* 1709 */ MCD::OPC_FilterValue, 96, 24, 60, 0, // Skip to: 17098
+/* 1714 */ MCD::OPC_CheckPredicate, 41, 19, 60, 0, // Skip to: 17098
+/* 1719 */ MCD::OPC_Decode, 162, 15, 191, 1, // Opcode: MTHGC0
+/* 1724 */ MCD::OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1746
+/* 1729 */ MCD::OPC_CheckPredicate, 27, 4, 60, 0, // Skip to: 17098
+/* 1734 */ MCD::OPC_CheckField, 4, 7, 0, 253, 59, 0, // Skip to: 17098
+/* 1741 */ MCD::OPC_Decode, 146, 15, 191, 1, // Opcode: MTC0
+/* 1746 */ MCD::OPC_FilterValue, 8, 17, 0, 0, // Skip to: 1768
+/* 1751 */ MCD::OPC_CheckPredicate, 42, 238, 59, 0, // Skip to: 17098
+/* 1756 */ MCD::OPC_CheckField, 6, 5, 0, 231, 59, 0, // Skip to: 17098
+/* 1763 */ MCD::OPC_Decode, 161, 14, 192, 1, // Opcode: MFTR
+/* 1768 */ MCD::OPC_FilterValue, 11, 133, 0, 0, // Skip to: 1906
+/* 1773 */ MCD::OPC_ExtractField, 4, 12, // Inst{15-4} ...
+/* 1776 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1797
+/* 1781 */ MCD::OPC_CheckPredicate, 42, 208, 59, 0, // Skip to: 17098
+/* 1786 */ MCD::OPC_CheckField, 0, 3, 1, 201, 59, 0, // Skip to: 17098
+/* 1793 */ MCD::OPC_Decode, 141, 10, 80, // Opcode: DVPE
+/* 1797 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 1818
+/* 1802 */ MCD::OPC_CheckPredicate, 42, 187, 59, 0, // Skip to: 17098
+/* 1807 */ MCD::OPC_CheckField, 0, 3, 1, 180, 59, 0, // Skip to: 17098
+/* 1814 */ MCD::OPC_Decode, 158, 10, 80, // Opcode: EVPE
+/* 1818 */ MCD::OPC_FilterValue, 188, 1, 16, 0, 0, // Skip to: 1840
+/* 1824 */ MCD::OPC_CheckPredicate, 42, 165, 59, 0, // Skip to: 17098
+/* 1829 */ MCD::OPC_CheckField, 0, 3, 1, 158, 59, 0, // Skip to: 17098
+/* 1836 */ MCD::OPC_Decode, 185, 9, 80, // Opcode: DMT
+/* 1840 */ MCD::OPC_FilterValue, 190, 1, 16, 0, 0, // Skip to: 1862
+/* 1846 */ MCD::OPC_CheckPredicate, 42, 143, 59, 0, // Skip to: 17098
+/* 1851 */ MCD::OPC_CheckField, 0, 3, 1, 136, 59, 0, // Skip to: 17098
+/* 1858 */ MCD::OPC_Decode, 151, 10, 80, // Opcode: EMT
+/* 1862 */ MCD::OPC_FilterValue, 128, 12, 16, 0, 0, // Skip to: 1884
+/* 1868 */ MCD::OPC_CheckPredicate, 28, 121, 59, 0, // Skip to: 17098
+/* 1873 */ MCD::OPC_CheckField, 0, 3, 0, 114, 59, 0, // Skip to: 17098
+/* 1880 */ MCD::OPC_Decode, 158, 9, 80, // Opcode: DI
+/* 1884 */ MCD::OPC_FilterValue, 130, 12, 104, 59, 0, // Skip to: 17098
+/* 1890 */ MCD::OPC_CheckPredicate, 28, 99, 59, 0, // Skip to: 17098
+/* 1895 */ MCD::OPC_CheckField, 0, 3, 0, 92, 59, 0, // Skip to: 17098
+/* 1902 */ MCD::OPC_Decode, 148, 10, 80, // Opcode: EI
+/* 1906 */ MCD::OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1928
+/* 1911 */ MCD::OPC_CheckPredicate, 42, 78, 59, 0, // Skip to: 17098
+/* 1916 */ MCD::OPC_CheckField, 6, 5, 0, 71, 59, 0, // Skip to: 17098
+/* 1923 */ MCD::OPC_Decode, 182, 15, 192, 1, // Opcode: MTTR
+/* 1928 */ MCD::OPC_FilterValue, 16, 61, 59, 0, // Skip to: 17098
+/* 1933 */ MCD::OPC_ExtractField, 0, 3, // Inst{2-0} ...
+/* 1936 */ MCD::OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1972
+/* 1941 */ MCD::OPC_ExtractField, 4, 17, // Inst{20-4} ...
+/* 1944 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 1958
+/* 1949 */ MCD::OPC_CheckPredicate, 41, 40, 59, 0, // Skip to: 17098
+/* 1954 */ MCD::OPC_Decode, 249, 19, 0, // Opcode: TLBGP
+/* 1958 */ MCD::OPC_FilterValue, 2, 31, 59, 0, // Skip to: 17098
+/* 1963 */ MCD::OPC_CheckPredicate, 43, 26, 59, 0, // Skip to: 17098
+/* 1968 */ MCD::OPC_Decode, 173, 20, 0, // Opcode: WAIT
+/* 1972 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 1993
+/* 1977 */ MCD::OPC_CheckPredicate, 27, 12, 59, 0, // Skip to: 17098
+/* 1982 */ MCD::OPC_CheckField, 4, 17, 0, 5, 59, 0, // Skip to: 17098
+/* 1989 */ MCD::OPC_Decode, 135, 20, 0, // Opcode: TLBR
+/* 1993 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 2014
+/* 1998 */ MCD::OPC_CheckPredicate, 27, 247, 58, 0, // Skip to: 17098
+/* 2003 */ MCD::OPC_CheckField, 4, 17, 0, 240, 58, 0, // Skip to: 17098
+/* 2010 */ MCD::OPC_Decode, 137, 20, 0, // Opcode: TLBWI
+/* 2014 */ MCD::OPC_FilterValue, 3, 16, 0, 0, // Skip to: 2035
+/* 2019 */ MCD::OPC_CheckPredicate, 44, 226, 58, 0, // Skip to: 17098
+/* 2024 */ MCD::OPC_CheckField, 4, 17, 0, 219, 58, 0, // Skip to: 17098
+/* 2031 */ MCD::OPC_Decode, 129, 20, 0, // Opcode: TLBINV
+/* 2035 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2056
+/* 2040 */ MCD::OPC_CheckPredicate, 44, 205, 58, 0, // Skip to: 17098
+/* 2045 */ MCD::OPC_CheckField, 4, 17, 0, 198, 58, 0, // Skip to: 17098
+/* 2052 */ MCD::OPC_Decode, 130, 20, 0, // Opcode: TLBINVF
+/* 2056 */ MCD::OPC_FilterValue, 6, 189, 58, 0, // Skip to: 17098
+/* 2061 */ MCD::OPC_CheckPredicate, 27, 184, 58, 0, // Skip to: 17098
+/* 2066 */ MCD::OPC_CheckField, 4, 17, 0, 177, 58, 0, // Skip to: 17098
+/* 2073 */ MCD::OPC_Decode, 139, 20, 0, // Opcode: TLBWR
+/* 2077 */ MCD::OPC_FilterValue, 1, 168, 58, 0, // Skip to: 17098
+/* 2082 */ MCD::OPC_ExtractField, 0, 3, // Inst{2-0} ...
+/* 2085 */ MCD::OPC_FilterValue, 0, 88, 0, 0, // Skip to: 2178
+/* 2090 */ MCD::OPC_ExtractField, 4, 2, // Inst{5-4} ...
+/* 2093 */ MCD::OPC_FilterValue, 0, 18, 0, 0, // Skip to: 2116
+/* 2098 */ MCD::OPC_CheckPredicate, 27, 147, 58, 0, // Skip to: 17098
+/* 2103 */ MCD::OPC_CheckField, 6, 20, 128, 128, 32, 138, 58, 0, // Skip to: 17098
+/* 2112 */ MCD::OPC_Decode, 133, 20, 0, // Opcode: TLBP
+/* 2116 */ MCD::OPC_FilterValue, 1, 35, 0, 0, // Skip to: 2156
+/* 2121 */ MCD::OPC_ExtractField, 6, 20, // Inst{25-6} ...
+/* 2124 */ MCD::OPC_FilterValue, 128, 128, 32, 9, 0, 0, // Skip to: 2140
+/* 2131 */ MCD::OPC_CheckPredicate, 43, 114, 58, 0, // Skip to: 17098
+/* 2136 */ MCD::OPC_Decode, 152, 10, 0, // Opcode: ERET
+/* 2140 */ MCD::OPC_FilterValue, 129, 128, 32, 103, 58, 0, // Skip to: 17098
+/* 2147 */ MCD::OPC_CheckPredicate, 45, 98, 58, 0, // Skip to: 17098
+/* 2152 */ MCD::OPC_Decode, 153, 10, 0, // Opcode: ERETNC
+/* 2156 */ MCD::OPC_FilterValue, 2, 89, 58, 0, // Skip to: 17098
+/* 2161 */ MCD::OPC_CheckPredicate, 41, 84, 58, 0, // Skip to: 17098
+/* 2166 */ MCD::OPC_CheckField, 25, 1, 1, 77, 58, 0, // Skip to: 17098
+/* 2173 */ MCD::OPC_Decode, 254, 11, 193, 1, // Opcode: HYPCALL
+/* 2178 */ MCD::OPC_FilterValue, 1, 19, 0, 0, // Skip to: 2202
+/* 2183 */ MCD::OPC_CheckPredicate, 41, 62, 58, 0, // Skip to: 17098
+/* 2188 */ MCD::OPC_CheckField, 4, 22, 128, 128, 128, 1, 52, 58, 0, // Skip to: 17098
+/* 2198 */ MCD::OPC_Decode, 251, 19, 0, // Opcode: TLBGR
+/* 2202 */ MCD::OPC_FilterValue, 2, 19, 0, 0, // Skip to: 2226
+/* 2207 */ MCD::OPC_CheckPredicate, 41, 38, 58, 0, // Skip to: 17098
+/* 2212 */ MCD::OPC_CheckField, 4, 22, 128, 128, 128, 1, 28, 58, 0, // Skip to: 17098
+/* 2222 */ MCD::OPC_Decode, 253, 19, 0, // Opcode: TLBGWI
+/* 2226 */ MCD::OPC_FilterValue, 3, 19, 0, 0, // Skip to: 2250
+/* 2231 */ MCD::OPC_CheckPredicate, 41, 14, 58, 0, // Skip to: 17098
+/* 2236 */ MCD::OPC_CheckField, 4, 22, 128, 128, 128, 1, 4, 58, 0, // Skip to: 17098
+/* 2246 */ MCD::OPC_Decode, 245, 19, 0, // Opcode: TLBGINV
+/* 2250 */ MCD::OPC_FilterValue, 4, 19, 0, 0, // Skip to: 2274
+/* 2255 */ MCD::OPC_CheckPredicate, 41, 246, 57, 0, // Skip to: 17098
+/* 2260 */ MCD::OPC_CheckField, 4, 22, 128, 128, 128, 1, 236, 57, 0, // Skip to: 17098
+/* 2270 */ MCD::OPC_Decode, 246, 19, 0, // Opcode: TLBGINVF
+/* 2274 */ MCD::OPC_FilterValue, 6, 19, 0, 0, // Skip to: 2298
+/* 2279 */ MCD::OPC_CheckPredicate, 41, 222, 57, 0, // Skip to: 17098
+/* 2284 */ MCD::OPC_CheckField, 4, 22, 128, 128, 128, 1, 212, 57, 0, // Skip to: 17098
+/* 2294 */ MCD::OPC_Decode, 255, 19, 0, // Opcode: TLBGWR
+/* 2298 */ MCD::OPC_FilterValue, 7, 203, 57, 0, // Skip to: 17098
+/* 2303 */ MCD::OPC_CheckPredicate, 46, 198, 57, 0, // Skip to: 17098
+/* 2308 */ MCD::OPC_CheckField, 4, 22, 129, 128, 128, 1, 188, 57, 0, // Skip to: 17098
+/* 2318 */ MCD::OPC_Decode, 151, 9, 0, // Opcode: DERET
+/* 2322 */ MCD::OPC_FilterValue, 17, 205, 7, 0, // Skip to: 4324
+/* 2327 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 2330 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2352
+/* 2335 */ MCD::OPC_CheckPredicate, 47, 166, 57, 0, // Skip to: 17098
+/* 2340 */ MCD::OPC_CheckField, 0, 11, 0, 159, 57, 0, // Skip to: 17098
+/* 2347 */ MCD::OPC_Decode, 133, 14, 194, 1, // Opcode: MFC1
+/* 2352 */ MCD::OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2374
+/* 2357 */ MCD::OPC_CheckPredicate, 48, 144, 57, 0, // Skip to: 17098
+/* 2362 */ MCD::OPC_CheckField, 0, 11, 0, 137, 57, 0, // Skip to: 17098
+/* 2369 */ MCD::OPC_Decode, 179, 9, 195, 1, // Opcode: DMFC1
+/* 2374 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 2396
+/* 2379 */ MCD::OPC_CheckPredicate, 47, 122, 57, 0, // Skip to: 17098
+/* 2384 */ MCD::OPC_CheckField, 0, 11, 0, 115, 57, 0, // Skip to: 17098
+/* 2391 */ MCD::OPC_Decode, 230, 6, 196, 1, // Opcode: CFC1
+/* 2396 */ MCD::OPC_FilterValue, 3, 17, 0, 0, // Skip to: 2418
+/* 2401 */ MCD::OPC_CheckPredicate, 49, 100, 57, 0, // Skip to: 17098
+/* 2406 */ MCD::OPC_CheckField, 0, 11, 0, 93, 57, 0, // Skip to: 17098
+/* 2413 */ MCD::OPC_Decode, 142, 14, 197, 1, // Opcode: MFHC1_D32
+/* 2418 */ MCD::OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2440
+/* 2423 */ MCD::OPC_CheckPredicate, 47, 78, 57, 0, // Skip to: 17098
+/* 2428 */ MCD::OPC_CheckField, 0, 11, 0, 71, 57, 0, // Skip to: 17098
+/* 2435 */ MCD::OPC_Decode, 148, 15, 198, 1, // Opcode: MTC1
+/* 2440 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2462
+/* 2445 */ MCD::OPC_CheckPredicate, 48, 56, 57, 0, // Skip to: 17098
+/* 2450 */ MCD::OPC_CheckField, 0, 11, 0, 49, 57, 0, // Skip to: 17098
+/* 2457 */ MCD::OPC_Decode, 187, 9, 199, 1, // Opcode: DMTC1
+/* 2462 */ MCD::OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2484
+/* 2467 */ MCD::OPC_CheckPredicate, 47, 34, 57, 0, // Skip to: 17098
+/* 2472 */ MCD::OPC_CheckField, 0, 11, 0, 27, 57, 0, // Skip to: 17098
+/* 2479 */ MCD::OPC_Decode, 129, 8, 200, 1, // Opcode: CTC1
+/* 2484 */ MCD::OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2506
+/* 2489 */ MCD::OPC_CheckPredicate, 49, 12, 57, 0, // Skip to: 17098
+/* 2494 */ MCD::OPC_CheckField, 0, 11, 0, 5, 57, 0, // Skip to: 17098
+/* 2501 */ MCD::OPC_Decode, 157, 15, 201, 1, // Opcode: MTHC1_D32
+/* 2506 */ MCD::OPC_FilterValue, 8, 63, 0, 0, // Skip to: 2574
+/* 2511 */ MCD::OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 2514 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2529
+/* 2519 */ MCD::OPC_CheckPredicate, 50, 238, 56, 0, // Skip to: 17098
+/* 2524 */ MCD::OPC_Decode, 151, 5, 202, 1, // Opcode: BC1F
+/* 2529 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2544
+/* 2534 */ MCD::OPC_CheckPredicate, 50, 223, 56, 0, // Skip to: 17098
+/* 2539 */ MCD::OPC_Decode, 156, 5, 202, 1, // Opcode: BC1T
+/* 2544 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2559
+/* 2549 */ MCD::OPC_CheckPredicate, 51, 208, 56, 0, // Skip to: 17098
+/* 2554 */ MCD::OPC_Decode, 152, 5, 202, 1, // Opcode: BC1FL
+/* 2559 */ MCD::OPC_FilterValue, 3, 198, 56, 0, // Skip to: 17098
+/* 2564 */ MCD::OPC_CheckPredicate, 51, 193, 56, 0, // Skip to: 17098
+/* 2569 */ MCD::OPC_Decode, 157, 5, 202, 1, // Opcode: BC1TL
+/* 2574 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 2589
+/* 2579 */ MCD::OPC_CheckPredicate, 30, 178, 56, 0, // Skip to: 17098
+/* 2584 */ MCD::OPC_Decode, 192, 6, 203, 1, // Opcode: BZ_V
+/* 2589 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2604
+/* 2594 */ MCD::OPC_CheckPredicate, 30, 163, 56, 0, // Skip to: 17098
+/* 2599 */ MCD::OPC_Decode, 167, 6, 203, 1, // Opcode: BNZ_V
+/* 2604 */ MCD::OPC_FilterValue, 16, 1, 3, 0, // Skip to: 3378
+/* 2609 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 2612 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2627
+/* 2617 */ MCD::OPC_CheckPredicate, 47, 140, 56, 0, // Skip to: 17098
+/* 2622 */ MCD::OPC_Decode, 200, 10, 204, 1, // Opcode: FADD_S
+/* 2627 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2642
+/* 2632 */ MCD::OPC_CheckPredicate, 47, 125, 56, 0, // Skip to: 17098
+/* 2637 */ MCD::OPC_Decode, 214, 11, 204, 1, // Opcode: FSUB_S
+/* 2642 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2657
+/* 2647 */ MCD::OPC_CheckPredicate, 47, 110, 56, 0, // Skip to: 17098
+/* 2652 */ MCD::OPC_Decode, 171, 11, 204, 1, // Opcode: FMUL_S
+/* 2657 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2672
+/* 2662 */ MCD::OPC_CheckPredicate, 47, 95, 56, 0, // Skip to: 17098
+/* 2667 */ MCD::OPC_Decode, 238, 10, 204, 1, // Opcode: FDIV_S
+/* 2672 */ MCD::OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2694
+/* 2677 */ MCD::OPC_CheckPredicate, 52, 80, 56, 0, // Skip to: 17098
+/* 2682 */ MCD::OPC_CheckField, 16, 5, 0, 73, 56, 0, // Skip to: 17098
+/* 2689 */ MCD::OPC_Decode, 206, 11, 205, 1, // Opcode: FSQRT_S
+/* 2694 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2716
+/* 2699 */ MCD::OPC_CheckPredicate, 47, 58, 56, 0, // Skip to: 17098
+/* 2704 */ MCD::OPC_CheckField, 16, 5, 0, 51, 56, 0, // Skip to: 17098
+/* 2711 */ MCD::OPC_Decode, 193, 10, 205, 1, // Opcode: FABS_S
+/* 2716 */ MCD::OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2738
+/* 2721 */ MCD::OPC_CheckPredicate, 47, 36, 56, 0, // Skip to: 17098
+/* 2726 */ MCD::OPC_CheckField, 16, 5, 0, 29, 56, 0, // Skip to: 17098
+/* 2733 */ MCD::OPC_Decode, 161, 11, 205, 1, // Opcode: FMOV_S
+/* 2738 */ MCD::OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2760
+/* 2743 */ MCD::OPC_CheckPredicate, 20, 14, 56, 0, // Skip to: 17098
+/* 2748 */ MCD::OPC_CheckField, 16, 5, 0, 7, 56, 0, // Skip to: 17098
+/* 2755 */ MCD::OPC_Decode, 179, 11, 205, 1, // Opcode: FNEG_S
+/* 2760 */ MCD::OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2782
+/* 2765 */ MCD::OPC_CheckPredicate, 52, 248, 55, 0, // Skip to: 17098
+/* 2770 */ MCD::OPC_CheckField, 16, 5, 0, 241, 55, 0, // Skip to: 17098
+/* 2777 */ MCD::OPC_Decode, 254, 16, 205, 1, // Opcode: ROUND_W_S
+/* 2782 */ MCD::OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2804
+/* 2787 */ MCD::OPC_CheckPredicate, 52, 226, 55, 0, // Skip to: 17098
+/* 2792 */ MCD::OPC_CheckField, 16, 5, 0, 219, 55, 0, // Skip to: 17098
+/* 2799 */ MCD::OPC_Decode, 160, 20, 205, 1, // Opcode: TRUNC_W_S
+/* 2804 */ MCD::OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2826
+/* 2809 */ MCD::OPC_CheckPredicate, 52, 204, 55, 0, // Skip to: 17098
+/* 2814 */ MCD::OPC_CheckField, 16, 5, 0, 197, 55, 0, // Skip to: 17098
+/* 2821 */ MCD::OPC_Decode, 219, 6, 205, 1, // Opcode: CEIL_W_S
+/* 2826 */ MCD::OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2848
+/* 2831 */ MCD::OPC_CheckPredicate, 52, 182, 55, 0, // Skip to: 17098
+/* 2836 */ MCD::OPC_CheckField, 16, 5, 0, 175, 55, 0, // Skip to: 17098
+/* 2843 */ MCD::OPC_Decode, 144, 11, 205, 1, // Opcode: FLOOR_W_S
+/* 2848 */ MCD::OPC_FilterValue, 17, 33, 0, 0, // Skip to: 2886
+/* 2853 */ MCD::OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 2856 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2871
+/* 2861 */ MCD::OPC_CheckPredicate, 29, 152, 55, 0, // Skip to: 17098
+/* 2866 */ MCD::OPC_Decode, 215, 14, 206, 1, // Opcode: MOVF_S
+/* 2871 */ MCD::OPC_FilterValue, 1, 142, 55, 0, // Skip to: 17098
+/* 2876 */ MCD::OPC_CheckPredicate, 29, 137, 55, 0, // Skip to: 17098
+/* 2881 */ MCD::OPC_Decode, 235, 14, 206, 1, // Opcode: MOVT_S
+/* 2886 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 2901
+/* 2891 */ MCD::OPC_CheckPredicate, 29, 122, 55, 0, // Skip to: 17098
+/* 2896 */ MCD::OPC_Decode, 247, 14, 207, 1, // Opcode: MOVZ_I_S
+/* 2901 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 2916
+/* 2906 */ MCD::OPC_CheckPredicate, 29, 107, 55, 0, // Skip to: 17098
+/* 2911 */ MCD::OPC_Decode, 227, 14, 207, 1, // Opcode: MOVN_I_S
+/* 2916 */ MCD::OPC_FilterValue, 21, 17, 0, 0, // Skip to: 2938
+/* 2921 */ MCD::OPC_CheckPredicate, 53, 92, 55, 0, // Skip to: 17098
+/* 2926 */ MCD::OPC_CheckField, 16, 5, 0, 85, 55, 0, // Skip to: 17098
+/* 2933 */ MCD::OPC_Decode, 228, 16, 205, 1, // Opcode: RECIP_S
+/* 2938 */ MCD::OPC_FilterValue, 22, 17, 0, 0, // Skip to: 2960
+/* 2943 */ MCD::OPC_CheckPredicate, 53, 70, 55, 0, // Skip to: 17098
+/* 2948 */ MCD::OPC_CheckField, 16, 5, 0, 63, 55, 0, // Skip to: 17098
+/* 2955 */ MCD::OPC_Decode, 133, 17, 205, 1, // Opcode: RSQRT_S
+/* 2960 */ MCD::OPC_FilterValue, 33, 17, 0, 0, // Skip to: 2982
+/* 2965 */ MCD::OPC_CheckPredicate, 54, 48, 55, 0, // Skip to: 17098
+/* 2970 */ MCD::OPC_CheckField, 16, 5, 0, 41, 55, 0, // Skip to: 17098
+/* 2977 */ MCD::OPC_Decode, 133, 8, 208, 1, // Opcode: CVT_D32_S
+/* 2982 */ MCD::OPC_FilterValue, 36, 17, 0, 0, // Skip to: 3004
+/* 2987 */ MCD::OPC_CheckPredicate, 47, 26, 55, 0, // Skip to: 17098
+/* 2992 */ MCD::OPC_CheckField, 16, 5, 0, 19, 55, 0, // Skip to: 17098
+/* 2999 */ MCD::OPC_Decode, 162, 8, 205, 1, // Opcode: CVT_W_S
+/* 3004 */ MCD::OPC_FilterValue, 37, 17, 0, 0, // Skip to: 3026
+/* 3009 */ MCD::OPC_CheckPredicate, 55, 4, 55, 0, // Skip to: 17098
+/* 3014 */ MCD::OPC_CheckField, 16, 5, 0, 253, 54, 0, // Skip to: 17098
+/* 3021 */ MCD::OPC_Decode, 146, 8, 209, 1, // Opcode: CVT_L_S
+/* 3026 */ MCD::OPC_FilterValue, 48, 17, 0, 0, // Skip to: 3048
+/* 3031 */ MCD::OPC_CheckPredicate, 50, 238, 54, 0, // Skip to: 17098
+/* 3036 */ MCD::OPC_CheckField, 6, 2, 0, 231, 54, 0, // Skip to: 17098
+/* 3043 */ MCD::OPC_Decode, 175, 8, 210, 1, // Opcode: C_F_S
+/* 3048 */ MCD::OPC_FilterValue, 49, 17, 0, 0, // Skip to: 3070
+/* 3053 */ MCD::OPC_CheckPredicate, 50, 216, 54, 0, // Skip to: 17098
+/* 3058 */ MCD::OPC_CheckField, 6, 2, 0, 209, 54, 0, // Skip to: 17098
+/* 3065 */ MCD::OPC_Decode, 131, 9, 210, 1, // Opcode: C_UN_S
+/* 3070 */ MCD::OPC_FilterValue, 50, 17, 0, 0, // Skip to: 3092
+/* 3075 */ MCD::OPC_CheckPredicate, 50, 194, 54, 0, // Skip to: 17098
+/* 3080 */ MCD::OPC_CheckField, 6, 2, 0, 187, 54, 0, // Skip to: 17098
+/* 3087 */ MCD::OPC_Decode, 169, 8, 210, 1, // Opcode: C_EQ_S
+/* 3092 */ MCD::OPC_FilterValue, 51, 17, 0, 0, // Skip to: 3114
+/* 3097 */ MCD::OPC_CheckPredicate, 50, 172, 54, 0, // Skip to: 17098
+/* 3102 */ MCD::OPC_CheckField, 6, 2, 0, 165, 54, 0, // Skip to: 17098
+/* 3109 */ MCD::OPC_Decode, 241, 8, 210, 1, // Opcode: C_UEQ_S
+/* 3114 */ MCD::OPC_FilterValue, 52, 17, 0, 0, // Skip to: 3136
+/* 3119 */ MCD::OPC_CheckPredicate, 50, 150, 54, 0, // Skip to: 17098
+/* 3124 */ MCD::OPC_CheckField, 6, 2, 0, 143, 54, 0, // Skip to: 17098
+/* 3131 */ MCD::OPC_Decode, 223, 8, 210, 1, // Opcode: C_OLT_S
+/* 3136 */ MCD::OPC_FilterValue, 53, 17, 0, 0, // Skip to: 3158
+/* 3141 */ MCD::OPC_CheckPredicate, 50, 128, 54, 0, // Skip to: 17098
+/* 3146 */ MCD::OPC_CheckField, 6, 2, 0, 121, 54, 0, // Skip to: 17098
+/* 3153 */ MCD::OPC_Decode, 253, 8, 210, 1, // Opcode: C_ULT_S
+/* 3158 */ MCD::OPC_FilterValue, 54, 17, 0, 0, // Skip to: 3180
+/* 3163 */ MCD::OPC_CheckPredicate, 50, 106, 54, 0, // Skip to: 17098
+/* 3168 */ MCD::OPC_CheckField, 6, 2, 0, 99, 54, 0, // Skip to: 17098
+/* 3175 */ MCD::OPC_Decode, 217, 8, 210, 1, // Opcode: C_OLE_S
+/* 3180 */ MCD::OPC_FilterValue, 55, 17, 0, 0, // Skip to: 3202
+/* 3185 */ MCD::OPC_CheckPredicate, 50, 84, 54, 0, // Skip to: 17098
+/* 3190 */ MCD::OPC_CheckField, 6, 2, 0, 77, 54, 0, // Skip to: 17098
+/* 3197 */ MCD::OPC_Decode, 247, 8, 210, 1, // Opcode: C_ULE_S
+/* 3202 */ MCD::OPC_FilterValue, 56, 17, 0, 0, // Skip to: 3224
+/* 3207 */ MCD::OPC_CheckPredicate, 50, 62, 54, 0, // Skip to: 17098
+/* 3212 */ MCD::OPC_CheckField, 6, 2, 0, 55, 54, 0, // Skip to: 17098
+/* 3219 */ MCD::OPC_Decode, 235, 8, 210, 1, // Opcode: C_SF_S
+/* 3224 */ MCD::OPC_FilterValue, 57, 17, 0, 0, // Skip to: 3246
+/* 3229 */ MCD::OPC_CheckPredicate, 50, 40, 54, 0, // Skip to: 17098
+/* 3234 */ MCD::OPC_CheckField, 6, 2, 0, 33, 54, 0, // Skip to: 17098
+/* 3241 */ MCD::OPC_Decode, 199, 8, 210, 1, // Opcode: C_NGLE_S
+/* 3246 */ MCD::OPC_FilterValue, 58, 17, 0, 0, // Skip to: 3268
+/* 3251 */ MCD::OPC_CheckPredicate, 50, 18, 54, 0, // Skip to: 17098
+/* 3256 */ MCD::OPC_CheckField, 6, 2, 0, 11, 54, 0, // Skip to: 17098
+/* 3263 */ MCD::OPC_Decode, 229, 8, 210, 1, // Opcode: C_SEQ_S
+/* 3268 */ MCD::OPC_FilterValue, 59, 17, 0, 0, // Skip to: 3290
+/* 3273 */ MCD::OPC_CheckPredicate, 50, 252, 53, 0, // Skip to: 17098
+/* 3278 */ MCD::OPC_CheckField, 6, 2, 0, 245, 53, 0, // Skip to: 17098
+/* 3285 */ MCD::OPC_Decode, 205, 8, 210, 1, // Opcode: C_NGL_S
+/* 3290 */ MCD::OPC_FilterValue, 60, 17, 0, 0, // Skip to: 3312
+/* 3295 */ MCD::OPC_CheckPredicate, 50, 230, 53, 0, // Skip to: 17098
+/* 3300 */ MCD::OPC_CheckField, 6, 2, 0, 223, 53, 0, // Skip to: 17098
+/* 3307 */ MCD::OPC_Decode, 187, 8, 210, 1, // Opcode: C_LT_S
+/* 3312 */ MCD::OPC_FilterValue, 61, 17, 0, 0, // Skip to: 3334
+/* 3317 */ MCD::OPC_CheckPredicate, 50, 208, 53, 0, // Skip to: 17098
+/* 3322 */ MCD::OPC_CheckField, 6, 2, 0, 201, 53, 0, // Skip to: 17098
+/* 3329 */ MCD::OPC_Decode, 193, 8, 210, 1, // Opcode: C_NGE_S
+/* 3334 */ MCD::OPC_FilterValue, 62, 17, 0, 0, // Skip to: 3356
+/* 3339 */ MCD::OPC_CheckPredicate, 50, 186, 53, 0, // Skip to: 17098
+/* 3344 */ MCD::OPC_CheckField, 6, 2, 0, 179, 53, 0, // Skip to: 17098
+/* 3351 */ MCD::OPC_Decode, 181, 8, 210, 1, // Opcode: C_LE_S
+/* 3356 */ MCD::OPC_FilterValue, 63, 169, 53, 0, // Skip to: 17098
+/* 3361 */ MCD::OPC_CheckPredicate, 50, 164, 53, 0, // Skip to: 17098
+/* 3366 */ MCD::OPC_CheckField, 6, 2, 0, 157, 53, 0, // Skip to: 17098
+/* 3373 */ MCD::OPC_Decode, 211, 8, 210, 1, // Opcode: C_NGT_S
+/* 3378 */ MCD::OPC_FilterValue, 17, 1, 3, 0, // Skip to: 4152
+/* 3383 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 3386 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3401
+/* 3391 */ MCD::OPC_CheckPredicate, 54, 134, 53, 0, // Skip to: 17098
+/* 3396 */ MCD::OPC_Decode, 196, 10, 211, 1, // Opcode: FADD_D32
+/* 3401 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3416
+/* 3406 */ MCD::OPC_CheckPredicate, 54, 119, 53, 0, // Skip to: 17098
+/* 3411 */ MCD::OPC_Decode, 210, 11, 211, 1, // Opcode: FSUB_D32
+/* 3416 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 3431
+/* 3421 */ MCD::OPC_CheckPredicate, 54, 104, 53, 0, // Skip to: 17098
+/* 3426 */ MCD::OPC_Decode, 167, 11, 211, 1, // Opcode: FMUL_D32
+/* 3431 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 3446
+/* 3436 */ MCD::OPC_CheckPredicate, 54, 89, 53, 0, // Skip to: 17098
+/* 3441 */ MCD::OPC_Decode, 234, 10, 211, 1, // Opcode: FDIV_D32
+/* 3446 */ MCD::OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3468
+/* 3451 */ MCD::OPC_CheckPredicate, 56, 74, 53, 0, // Skip to: 17098
+/* 3456 */ MCD::OPC_CheckField, 16, 5, 0, 67, 53, 0, // Skip to: 17098
+/* 3463 */ MCD::OPC_Decode, 202, 11, 212, 1, // Opcode: FSQRT_D32
+/* 3468 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3490
+/* 3473 */ MCD::OPC_CheckPredicate, 54, 52, 53, 0, // Skip to: 17098
+/* 3478 */ MCD::OPC_CheckField, 16, 5, 0, 45, 53, 0, // Skip to: 17098
+/* 3485 */ MCD::OPC_Decode, 189, 10, 212, 1, // Opcode: FABS_D32
+/* 3490 */ MCD::OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3512
+/* 3495 */ MCD::OPC_CheckPredicate, 54, 30, 53, 0, // Skip to: 17098
+/* 3500 */ MCD::OPC_CheckField, 16, 5, 0, 23, 53, 0, // Skip to: 17098
+/* 3507 */ MCD::OPC_Decode, 157, 11, 212, 1, // Opcode: FMOV_D32
+/* 3512 */ MCD::OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3534
+/* 3517 */ MCD::OPC_CheckPredicate, 54, 8, 53, 0, // Skip to: 17098
+/* 3522 */ MCD::OPC_CheckField, 16, 5, 0, 1, 53, 0, // Skip to: 17098
+/* 3529 */ MCD::OPC_Decode, 175, 11, 212, 1, // Opcode: FNEG_D32
+/* 3534 */ MCD::OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3556
+/* 3539 */ MCD::OPC_CheckPredicate, 56, 242, 52, 0, // Skip to: 17098
+/* 3544 */ MCD::OPC_CheckField, 16, 5, 0, 235, 52, 0, // Skip to: 17098
+/* 3551 */ MCD::OPC_Decode, 250, 16, 213, 1, // Opcode: ROUND_W_D32
+/* 3556 */ MCD::OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3578
+/* 3561 */ MCD::OPC_CheckPredicate, 56, 220, 52, 0, // Skip to: 17098
+/* 3566 */ MCD::OPC_CheckField, 16, 5, 0, 213, 52, 0, // Skip to: 17098
+/* 3573 */ MCD::OPC_Decode, 156, 20, 213, 1, // Opcode: TRUNC_W_D32
+/* 3578 */ MCD::OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3600
+/* 3583 */ MCD::OPC_CheckPredicate, 56, 198, 52, 0, // Skip to: 17098
+/* 3588 */ MCD::OPC_CheckField, 16, 5, 0, 191, 52, 0, // Skip to: 17098
+/* 3595 */ MCD::OPC_Decode, 215, 6, 213, 1, // Opcode: CEIL_W_D32
+/* 3600 */ MCD::OPC_FilterValue, 15, 17, 0, 0, // Skip to: 3622
+/* 3605 */ MCD::OPC_CheckPredicate, 56, 176, 52, 0, // Skip to: 17098
+/* 3610 */ MCD::OPC_CheckField, 16, 5, 0, 169, 52, 0, // Skip to: 17098
+/* 3617 */ MCD::OPC_Decode, 140, 11, 213, 1, // Opcode: FLOOR_W_D32
+/* 3622 */ MCD::OPC_FilterValue, 17, 33, 0, 0, // Skip to: 3660
+/* 3627 */ MCD::OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 3630 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3645
+/* 3635 */ MCD::OPC_CheckPredicate, 57, 146, 52, 0, // Skip to: 17098
+/* 3640 */ MCD::OPC_Decode, 209, 14, 214, 1, // Opcode: MOVF_D32
+/* 3645 */ MCD::OPC_FilterValue, 1, 136, 52, 0, // Skip to: 17098
+/* 3650 */ MCD::OPC_CheckPredicate, 57, 131, 52, 0, // Skip to: 17098
+/* 3655 */ MCD::OPC_Decode, 229, 14, 214, 1, // Opcode: MOVT_D32
+/* 3660 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 3675
+/* 3665 */ MCD::OPC_CheckPredicate, 57, 116, 52, 0, // Skip to: 17098
+/* 3670 */ MCD::OPC_Decode, 241, 14, 215, 1, // Opcode: MOVZ_I_D32
+/* 3675 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 3690
+/* 3680 */ MCD::OPC_CheckPredicate, 57, 101, 52, 0, // Skip to: 17098
+/* 3685 */ MCD::OPC_Decode, 221, 14, 215, 1, // Opcode: MOVN_I_D32
+/* 3690 */ MCD::OPC_FilterValue, 21, 17, 0, 0, // Skip to: 3712
+/* 3695 */ MCD::OPC_CheckPredicate, 58, 86, 52, 0, // Skip to: 17098
+/* 3700 */ MCD::OPC_CheckField, 16, 5, 0, 79, 52, 0, // Skip to: 17098
+/* 3707 */ MCD::OPC_Decode, 224, 16, 212, 1, // Opcode: RECIP_D32
+/* 3712 */ MCD::OPC_FilterValue, 22, 17, 0, 0, // Skip to: 3734
+/* 3717 */ MCD::OPC_CheckPredicate, 58, 64, 52, 0, // Skip to: 17098
+/* 3722 */ MCD::OPC_CheckField, 16, 5, 0, 57, 52, 0, // Skip to: 17098
+/* 3729 */ MCD::OPC_Decode, 129, 17, 212, 1, // Opcode: RSQRT_D32
+/* 3734 */ MCD::OPC_FilterValue, 32, 17, 0, 0, // Skip to: 3756
+/* 3739 */ MCD::OPC_CheckPredicate, 54, 42, 52, 0, // Skip to: 17098
+/* 3744 */ MCD::OPC_CheckField, 16, 5, 0, 35, 52, 0, // Skip to: 17098
+/* 3751 */ MCD::OPC_Decode, 149, 8, 213, 1, // Opcode: CVT_S_D32
+/* 3756 */ MCD::OPC_FilterValue, 36, 17, 0, 0, // Skip to: 3778
+/* 3761 */ MCD::OPC_CheckPredicate, 54, 20, 52, 0, // Skip to: 17098
+/* 3766 */ MCD::OPC_CheckField, 16, 5, 0, 13, 52, 0, // Skip to: 17098
+/* 3773 */ MCD::OPC_Decode, 158, 8, 213, 1, // Opcode: CVT_W_D32
+/* 3778 */ MCD::OPC_FilterValue, 37, 17, 0, 0, // Skip to: 3800
+/* 3783 */ MCD::OPC_CheckPredicate, 55, 254, 51, 0, // Skip to: 17098
+/* 3788 */ MCD::OPC_CheckField, 16, 5, 0, 247, 51, 0, // Skip to: 17098
+/* 3795 */ MCD::OPC_Decode, 143, 8, 216, 1, // Opcode: CVT_L_D64
+/* 3800 */ MCD::OPC_FilterValue, 48, 17, 0, 0, // Skip to: 3822
+/* 3805 */ MCD::OPC_CheckPredicate, 59, 232, 51, 0, // Skip to: 17098
+/* 3810 */ MCD::OPC_CheckField, 6, 2, 0, 225, 51, 0, // Skip to: 17098
+/* 3817 */ MCD::OPC_Decode, 171, 8, 217, 1, // Opcode: C_F_D32
+/* 3822 */ MCD::OPC_FilterValue, 49, 17, 0, 0, // Skip to: 3844
+/* 3827 */ MCD::OPC_CheckPredicate, 59, 210, 51, 0, // Skip to: 17098
+/* 3832 */ MCD::OPC_CheckField, 6, 2, 0, 203, 51, 0, // Skip to: 17098
+/* 3839 */ MCD::OPC_Decode, 255, 8, 217, 1, // Opcode: C_UN_D32
+/* 3844 */ MCD::OPC_FilterValue, 50, 17, 0, 0, // Skip to: 3866
+/* 3849 */ MCD::OPC_CheckPredicate, 59, 188, 51, 0, // Skip to: 17098
+/* 3854 */ MCD::OPC_CheckField, 6, 2, 0, 181, 51, 0, // Skip to: 17098
+/* 3861 */ MCD::OPC_Decode, 165, 8, 217, 1, // Opcode: C_EQ_D32
+/* 3866 */ MCD::OPC_FilterValue, 51, 17, 0, 0, // Skip to: 3888
+/* 3871 */ MCD::OPC_CheckPredicate, 59, 166, 51, 0, // Skip to: 17098
+/* 3876 */ MCD::OPC_CheckField, 6, 2, 0, 159, 51, 0, // Skip to: 17098
+/* 3883 */ MCD::OPC_Decode, 237, 8, 217, 1, // Opcode: C_UEQ_D32
+/* 3888 */ MCD::OPC_FilterValue, 52, 17, 0, 0, // Skip to: 3910
+/* 3893 */ MCD::OPC_CheckPredicate, 59, 144, 51, 0, // Skip to: 17098
+/* 3898 */ MCD::OPC_CheckField, 6, 2, 0, 137, 51, 0, // Skip to: 17098
+/* 3905 */ MCD::OPC_Decode, 219, 8, 217, 1, // Opcode: C_OLT_D32
+/* 3910 */ MCD::OPC_FilterValue, 53, 17, 0, 0, // Skip to: 3932
+/* 3915 */ MCD::OPC_CheckPredicate, 59, 122, 51, 0, // Skip to: 17098
+/* 3920 */ MCD::OPC_CheckField, 6, 2, 0, 115, 51, 0, // Skip to: 17098
+/* 3927 */ MCD::OPC_Decode, 249, 8, 217, 1, // Opcode: C_ULT_D32
+/* 3932 */ MCD::OPC_FilterValue, 54, 17, 0, 0, // Skip to: 3954
+/* 3937 */ MCD::OPC_CheckPredicate, 59, 100, 51, 0, // Skip to: 17098
+/* 3942 */ MCD::OPC_CheckField, 6, 2, 0, 93, 51, 0, // Skip to: 17098
+/* 3949 */ MCD::OPC_Decode, 213, 8, 217, 1, // Opcode: C_OLE_D32
+/* 3954 */ MCD::OPC_FilterValue, 55, 17, 0, 0, // Skip to: 3976
+/* 3959 */ MCD::OPC_CheckPredicate, 59, 78, 51, 0, // Skip to: 17098
+/* 3964 */ MCD::OPC_CheckField, 6, 2, 0, 71, 51, 0, // Skip to: 17098
+/* 3971 */ MCD::OPC_Decode, 243, 8, 217, 1, // Opcode: C_ULE_D32
+/* 3976 */ MCD::OPC_FilterValue, 56, 17, 0, 0, // Skip to: 3998
+/* 3981 */ MCD::OPC_CheckPredicate, 59, 56, 51, 0, // Skip to: 17098
+/* 3986 */ MCD::OPC_CheckField, 6, 2, 0, 49, 51, 0, // Skip to: 17098
+/* 3993 */ MCD::OPC_Decode, 231, 8, 217, 1, // Opcode: C_SF_D32
+/* 3998 */ MCD::OPC_FilterValue, 57, 17, 0, 0, // Skip to: 4020
+/* 4003 */ MCD::OPC_CheckPredicate, 59, 34, 51, 0, // Skip to: 17098
+/* 4008 */ MCD::OPC_CheckField, 6, 2, 0, 27, 51, 0, // Skip to: 17098
+/* 4015 */ MCD::OPC_Decode, 195, 8, 217, 1, // Opcode: C_NGLE_D32
+/* 4020 */ MCD::OPC_FilterValue, 58, 17, 0, 0, // Skip to: 4042
+/* 4025 */ MCD::OPC_CheckPredicate, 59, 12, 51, 0, // Skip to: 17098
+/* 4030 */ MCD::OPC_CheckField, 6, 2, 0, 5, 51, 0, // Skip to: 17098
+/* 4037 */ MCD::OPC_Decode, 225, 8, 217, 1, // Opcode: C_SEQ_D32
+/* 4042 */ MCD::OPC_FilterValue, 59, 17, 0, 0, // Skip to: 4064
+/* 4047 */ MCD::OPC_CheckPredicate, 59, 246, 50, 0, // Skip to: 17098
+/* 4052 */ MCD::OPC_CheckField, 6, 2, 0, 239, 50, 0, // Skip to: 17098
+/* 4059 */ MCD::OPC_Decode, 201, 8, 217, 1, // Opcode: C_NGL_D32
+/* 4064 */ MCD::OPC_FilterValue, 60, 17, 0, 0, // Skip to: 4086
+/* 4069 */ MCD::OPC_CheckPredicate, 59, 224, 50, 0, // Skip to: 17098
+/* 4074 */ MCD::OPC_CheckField, 6, 2, 0, 217, 50, 0, // Skip to: 17098
+/* 4081 */ MCD::OPC_Decode, 183, 8, 217, 1, // Opcode: C_LT_D32
+/* 4086 */ MCD::OPC_FilterValue, 61, 17, 0, 0, // Skip to: 4108
+/* 4091 */ MCD::OPC_CheckPredicate, 59, 202, 50, 0, // Skip to: 17098
+/* 4096 */ MCD::OPC_CheckField, 6, 2, 0, 195, 50, 0, // Skip to: 17098
+/* 4103 */ MCD::OPC_Decode, 189, 8, 217, 1, // Opcode: C_NGE_D32
+/* 4108 */ MCD::OPC_FilterValue, 62, 17, 0, 0, // Skip to: 4130
+/* 4113 */ MCD::OPC_CheckPredicate, 59, 180, 50, 0, // Skip to: 17098
+/* 4118 */ MCD::OPC_CheckField, 6, 2, 0, 173, 50, 0, // Skip to: 17098
+/* 4125 */ MCD::OPC_Decode, 177, 8, 217, 1, // Opcode: C_LE_D32
+/* 4130 */ MCD::OPC_FilterValue, 63, 163, 50, 0, // Skip to: 17098
+/* 4135 */ MCD::OPC_CheckPredicate, 59, 158, 50, 0, // Skip to: 17098
+/* 4140 */ MCD::OPC_CheckField, 6, 2, 0, 151, 50, 0, // Skip to: 17098
+/* 4147 */ MCD::OPC_Decode, 207, 8, 217, 1, // Opcode: C_NGT_D32
+/* 4152 */ MCD::OPC_FilterValue, 20, 47, 0, 0, // Skip to: 4204
+/* 4157 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 4160 */ MCD::OPC_FilterValue, 32, 17, 0, 0, // Skip to: 4182
+/* 4165 */ MCD::OPC_CheckPredicate, 47, 128, 50, 0, // Skip to: 17098
+/* 4170 */ MCD::OPC_CheckField, 16, 5, 0, 121, 50, 0, // Skip to: 17098
+/* 4177 */ MCD::OPC_Decode, 155, 8, 205, 1, // Opcode: CVT_S_W
+/* 4182 */ MCD::OPC_FilterValue, 33, 111, 50, 0, // Skip to: 17098
+/* 4187 */ MCD::OPC_CheckPredicate, 54, 106, 50, 0, // Skip to: 17098
+/* 4192 */ MCD::OPC_CheckField, 16, 5, 0, 99, 50, 0, // Skip to: 17098
+/* 4199 */ MCD::OPC_Decode, 135, 8, 208, 1, // Opcode: CVT_D32_W
+/* 4204 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 4219
+/* 4209 */ MCD::OPC_CheckPredicate, 30, 84, 50, 0, // Skip to: 17098
+/* 4214 */ MCD::OPC_Decode, 189, 6, 203, 1, // Opcode: BZ_B
+/* 4219 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 4234
+/* 4224 */ MCD::OPC_CheckPredicate, 30, 69, 50, 0, // Skip to: 17098
+/* 4229 */ MCD::OPC_Decode, 191, 6, 218, 1, // Opcode: BZ_H
+/* 4234 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 4249
+/* 4239 */ MCD::OPC_CheckPredicate, 30, 54, 50, 0, // Skip to: 17098
+/* 4244 */ MCD::OPC_Decode, 193, 6, 219, 1, // Opcode: BZ_W
+/* 4249 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 4264
+/* 4254 */ MCD::OPC_CheckPredicate, 30, 39, 50, 0, // Skip to: 17098
+/* 4259 */ MCD::OPC_Decode, 190, 6, 220, 1, // Opcode: BZ_D
+/* 4264 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 4279
+/* 4269 */ MCD::OPC_CheckPredicate, 30, 24, 50, 0, // Skip to: 17098
+/* 4274 */ MCD::OPC_Decode, 164, 6, 203, 1, // Opcode: BNZ_B
+/* 4279 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 4294
+/* 4284 */ MCD::OPC_CheckPredicate, 30, 9, 50, 0, // Skip to: 17098
+/* 4289 */ MCD::OPC_Decode, 166, 6, 218, 1, // Opcode: BNZ_H
+/* 4294 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 4309
+/* 4299 */ MCD::OPC_CheckPredicate, 30, 250, 49, 0, // Skip to: 17098
+/* 4304 */ MCD::OPC_Decode, 168, 6, 219, 1, // Opcode: BNZ_W
+/* 4309 */ MCD::OPC_FilterValue, 31, 240, 49, 0, // Skip to: 17098
+/* 4314 */ MCD::OPC_CheckPredicate, 30, 235, 49, 0, // Skip to: 17098
+/* 4319 */ MCD::OPC_Decode, 165, 6, 220, 1, // Opcode: BNZ_D
+/* 4324 */ MCD::OPC_FilterValue, 18, 47, 0, 0, // Skip to: 4376
+/* 4329 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 4332 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4354
+/* 4337 */ MCD::OPC_CheckPredicate, 27, 212, 49, 0, // Skip to: 17098
+/* 4342 */ MCD::OPC_CheckField, 3, 8, 0, 205, 49, 0, // Skip to: 17098
+/* 4349 */ MCD::OPC_Decode, 137, 14, 221, 1, // Opcode: MFC2
+/* 4354 */ MCD::OPC_FilterValue, 4, 195, 49, 0, // Skip to: 17098
+/* 4359 */ MCD::OPC_CheckPredicate, 27, 190, 49, 0, // Skip to: 17098
+/* 4364 */ MCD::OPC_CheckField, 3, 8, 0, 183, 49, 0, // Skip to: 17098
+/* 4371 */ MCD::OPC_Decode, 152, 15, 222, 1, // Opcode: MTC2
+/* 4376 */ MCD::OPC_FilterValue, 19, 255, 0, 0, // Skip to: 4636
+/* 4381 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 4384 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4406
+/* 4389 */ MCD::OPC_CheckPredicate, 60, 160, 49, 0, // Skip to: 17098
+/* 4394 */ MCD::OPC_CheckField, 11, 5, 0, 153, 49, 0, // Skip to: 17098
+/* 4401 */ MCD::OPC_Decode, 180, 13, 223, 1, // Opcode: LWXC1
+/* 4406 */ MCD::OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4428
+/* 4411 */ MCD::OPC_CheckPredicate, 61, 138, 49, 0, // Skip to: 17098
+/* 4416 */ MCD::OPC_CheckField, 11, 5, 0, 131, 49, 0, // Skip to: 17098
+/* 4423 */ MCD::OPC_Decode, 230, 12, 224, 1, // Opcode: LDXC1
+/* 4428 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4450
+/* 4433 */ MCD::OPC_CheckPredicate, 62, 116, 49, 0, // Skip to: 17098
+/* 4438 */ MCD::OPC_CheckField, 11, 5, 0, 109, 49, 0, // Skip to: 17098
+/* 4445 */ MCD::OPC_Decode, 140, 13, 224, 1, // Opcode: LUXC1
+/* 4450 */ MCD::OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4472
+/* 4455 */ MCD::OPC_CheckPredicate, 60, 94, 49, 0, // Skip to: 17098
+/* 4460 */ MCD::OPC_CheckField, 6, 5, 0, 87, 49, 0, // Skip to: 17098
+/* 4467 */ MCD::OPC_Decode, 200, 19, 225, 1, // Opcode: SWXC1
+/* 4472 */ MCD::OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4494
+/* 4477 */ MCD::OPC_CheckPredicate, 61, 72, 49, 0, // Skip to: 17098
+/* 4482 */ MCD::OPC_CheckField, 6, 5, 0, 65, 49, 0, // Skip to: 17098
+/* 4489 */ MCD::OPC_Decode, 182, 17, 226, 1, // Opcode: SDXC1
+/* 4494 */ MCD::OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4516
+/* 4499 */ MCD::OPC_CheckPredicate, 62, 50, 49, 0, // Skip to: 17098
+/* 4504 */ MCD::OPC_CheckField, 6, 5, 0, 43, 49, 0, // Skip to: 17098
+/* 4511 */ MCD::OPC_Decode, 167, 19, 226, 1, // Opcode: SUXC1
+/* 4516 */ MCD::OPC_FilterValue, 32, 10, 0, 0, // Skip to: 4531
+/* 4521 */ MCD::OPC_CheckPredicate, 63, 28, 49, 0, // Skip to: 17098
+/* 4526 */ MCD::OPC_Decode, 221, 13, 227, 1, // Opcode: MADD_S
+/* 4531 */ MCD::OPC_FilterValue, 33, 10, 0, 0, // Skip to: 4546
+/* 4536 */ MCD::OPC_CheckPredicate, 64, 13, 49, 0, // Skip to: 17098
+/* 4541 */ MCD::OPC_Decode, 213, 13, 228, 1, // Opcode: MADD_D32
+/* 4546 */ MCD::OPC_FilterValue, 40, 10, 0, 0, // Skip to: 4561
+/* 4551 */ MCD::OPC_CheckPredicate, 63, 254, 48, 0, // Skip to: 17098
+/* 4556 */ MCD::OPC_Decode, 144, 15, 227, 1, // Opcode: MSUB_S
+/* 4561 */ MCD::OPC_FilterValue, 41, 10, 0, 0, // Skip to: 4576
+/* 4566 */ MCD::OPC_CheckPredicate, 64, 239, 48, 0, // Skip to: 17098
+/* 4571 */ MCD::OPC_Decode, 136, 15, 228, 1, // Opcode: MSUB_D32
+/* 4576 */ MCD::OPC_FilterValue, 48, 10, 0, 0, // Skip to: 4591
+/* 4581 */ MCD::OPC_CheckPredicate, 65, 224, 48, 0, // Skip to: 17098
+/* 4586 */ MCD::OPC_Decode, 248, 15, 227, 1, // Opcode: NMADD_S
+/* 4591 */ MCD::OPC_FilterValue, 49, 10, 0, 0, // Skip to: 4606
+/* 4596 */ MCD::OPC_CheckPredicate, 66, 209, 48, 0, // Skip to: 17098
+/* 4601 */ MCD::OPC_Decode, 245, 15, 228, 1, // Opcode: NMADD_D32
+/* 4606 */ MCD::OPC_FilterValue, 56, 10, 0, 0, // Skip to: 4621
+/* 4611 */ MCD::OPC_CheckPredicate, 65, 194, 48, 0, // Skip to: 17098
+/* 4616 */ MCD::OPC_Decode, 253, 15, 227, 1, // Opcode: NMSUB_S
+/* 4621 */ MCD::OPC_FilterValue, 57, 184, 48, 0, // Skip to: 17098
+/* 4626 */ MCD::OPC_CheckPredicate, 66, 179, 48, 0, // Skip to: 17098
+/* 4631 */ MCD::OPC_Decode, 250, 15, 228, 1, // Opcode: NMSUB_D32
+/* 4636 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 4651
+/* 4641 */ MCD::OPC_CheckPredicate, 39, 164, 48, 0, // Skip to: 17098
+/* 4646 */ MCD::OPC_Decode, 177, 5, 187, 1, // Opcode: BEQL
+/* 4651 */ MCD::OPC_FilterValue, 21, 107, 0, 0, // Skip to: 4763
+/* 4656 */ MCD::OPC_ExtractField, 0, 16, // Inst{15-0} ...
+/* 4659 */ MCD::OPC_FilterValue, 123, 9, 0, 0, // Skip to: 4673
+/* 4664 */ MCD::OPC_CheckPredicate, 18, 19, 0, 0, // Skip to: 4688
+/* 4669 */ MCD::OPC_Decode, 162, 11, 112, // Opcode: FMOV_S_MM
+/* 4673 */ MCD::OPC_FilterValue, 251, 22, 9, 0, 0, // Skip to: 4688
+/* 4679 */ MCD::OPC_CheckPredicate, 18, 4, 0, 0, // Skip to: 4688
+/* 4684 */ MCD::OPC_Decode, 180, 11, 112, // Opcode: FNEG_S_MM
+/* 4688 */ MCD::OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 4691 */ MCD::OPC_FilterValue, 48, 10, 0, 0, // Skip to: 4706
+/* 4696 */ MCD::OPC_CheckPredicate, 18, 52, 0, 0, // Skip to: 4753
+/* 4701 */ MCD::OPC_Decode, 201, 10, 150, 1, // Opcode: FADD_S_MM
+/* 4706 */ MCD::OPC_FilterValue, 112, 10, 0, 0, // Skip to: 4721
+/* 4711 */ MCD::OPC_CheckPredicate, 18, 37, 0, 0, // Skip to: 4753
+/* 4716 */ MCD::OPC_Decode, 215, 11, 150, 1, // Opcode: FSUB_S_MM
+/* 4721 */ MCD::OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 4737
+/* 4727 */ MCD::OPC_CheckPredicate, 18, 21, 0, 0, // Skip to: 4753
+/* 4732 */ MCD::OPC_Decode, 172, 11, 150, 1, // Opcode: FMUL_S_MM
+/* 4737 */ MCD::OPC_FilterValue, 240, 1, 10, 0, 0, // Skip to: 4753
+/* 4743 */ MCD::OPC_CheckPredicate, 18, 5, 0, 0, // Skip to: 4753
+/* 4748 */ MCD::OPC_Decode, 239, 10, 150, 1, // Opcode: FDIV_S_MM
+/* 4753 */ MCD::OPC_CheckPredicate, 39, 52, 48, 0, // Skip to: 17098
+/* 4758 */ MCD::OPC_Decode, 152, 6, 187, 1, // Opcode: BNEL
+/* 4763 */ MCD::OPC_FilterValue, 22, 17, 0, 0, // Skip to: 4785
+/* 4768 */ MCD::OPC_CheckPredicate, 39, 37, 48, 0, // Skip to: 17098
+/* 4773 */ MCD::OPC_CheckField, 16, 5, 0, 30, 48, 0, // Skip to: 17098
+/* 4780 */ MCD::OPC_Decode, 242, 5, 183, 1, // Opcode: BLEZL
+/* 4785 */ MCD::OPC_FilterValue, 23, 17, 0, 0, // Skip to: 4807
+/* 4790 */ MCD::OPC_CheckPredicate, 39, 15, 48, 0, // Skip to: 17098
+/* 4795 */ MCD::OPC_CheckField, 16, 5, 0, 8, 48, 0, // Skip to: 17098
+/* 4802 */ MCD::OPC_Decode, 213, 5, 183, 1, // Opcode: BGTZL
+/* 4807 */ MCD::OPC_FilterValue, 28, 15, 1, 0, // Skip to: 5083
+/* 4812 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 4815 */ MCD::OPC_FilterValue, 0, 42, 0, 0, // Skip to: 4862
+/* 4820 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 4823 */ MCD::OPC_FilterValue, 0, 238, 47, 0, // Skip to: 17098
+/* 4828 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 4831 */ MCD::OPC_FilterValue, 0, 230, 47, 0, // Skip to: 17098
+/* 4836 */ MCD::OPC_CheckPredicate, 67, 11, 0, 0, // Skip to: 4852
+/* 4841 */ MCD::OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4852
+/* 4848 */ MCD::OPC_Decode, 198, 13, 68, // Opcode: MADD
+/* 4852 */ MCD::OPC_CheckPredicate, 37, 209, 47, 0, // Skip to: 17098
+/* 4857 */ MCD::OPC_Decode, 216, 13, 229, 1, // Opcode: MADD_DSP
+/* 4862 */ MCD::OPC_FilterValue, 1, 42, 0, 0, // Skip to: 4909
+/* 4867 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 4870 */ MCD::OPC_FilterValue, 0, 191, 47, 0, // Skip to: 17098
+/* 4875 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 4878 */ MCD::OPC_FilterValue, 0, 183, 47, 0, // Skip to: 17098
+/* 4883 */ MCD::OPC_CheckPredicate, 67, 11, 0, 0, // Skip to: 4899
+/* 4888 */ MCD::OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4899
+/* 4895 */ MCD::OPC_Decode, 205, 13, 68, // Opcode: MADDU
+/* 4899 */ MCD::OPC_CheckPredicate, 37, 162, 47, 0, // Skip to: 17098
+/* 4904 */ MCD::OPC_Decode, 206, 13, 229, 1, // Opcode: MADDU_DSP
+/* 4909 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 4930
+/* 4914 */ MCD::OPC_CheckPredicate, 67, 147, 47, 0, // Skip to: 17098
+/* 4919 */ MCD::OPC_CheckField, 6, 5, 0, 140, 47, 0, // Skip to: 17098
+/* 4926 */ MCD::OPC_Decode, 187, 15, 49, // Opcode: MUL
+/* 4930 */ MCD::OPC_FilterValue, 4, 42, 0, 0, // Skip to: 4977
+/* 4935 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 4938 */ MCD::OPC_FilterValue, 0, 123, 47, 0, // Skip to: 17098
+/* 4943 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 4946 */ MCD::OPC_FilterValue, 0, 115, 47, 0, // Skip to: 17098
+/* 4951 */ MCD::OPC_CheckPredicate, 67, 11, 0, 0, // Skip to: 4967
+/* 4956 */ MCD::OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 4967
+/* 4963 */ MCD::OPC_Decode, 249, 14, 68, // Opcode: MSUB
+/* 4967 */ MCD::OPC_CheckPredicate, 37, 94, 47, 0, // Skip to: 17098
+/* 4972 */ MCD::OPC_Decode, 139, 15, 229, 1, // Opcode: MSUB_DSP
+/* 4977 */ MCD::OPC_FilterValue, 5, 42, 0, 0, // Skip to: 5024
+/* 4982 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 4985 */ MCD::OPC_FilterValue, 0, 76, 47, 0, // Skip to: 17098
+/* 4990 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 4993 */ MCD::OPC_FilterValue, 0, 68, 47, 0, // Skip to: 17098
+/* 4998 */ MCD::OPC_CheckPredicate, 67, 11, 0, 0, // Skip to: 5014
+/* 5003 */ MCD::OPC_CheckField, 11, 2, 0, 4, 0, 0, // Skip to: 5014
+/* 5010 */ MCD::OPC_Decode, 128, 15, 68, // Opcode: MSUBU
+/* 5014 */ MCD::OPC_CheckPredicate, 37, 47, 47, 0, // Skip to: 17098
+/* 5019 */ MCD::OPC_Decode, 129, 15, 229, 1, // Opcode: MSUBU_DSP
+/* 5024 */ MCD::OPC_FilterValue, 32, 17, 0, 0, // Skip to: 5046
+/* 5029 */ MCD::OPC_CheckPredicate, 67, 32, 47, 0, // Skip to: 17098
+/* 5034 */ MCD::OPC_CheckField, 6, 5, 0, 25, 47, 0, // Skip to: 17098
+/* 5041 */ MCD::OPC_Decode, 150, 7, 230, 1, // Opcode: CLZ
+/* 5046 */ MCD::OPC_FilterValue, 33, 17, 0, 0, // Skip to: 5068
+/* 5051 */ MCD::OPC_CheckPredicate, 67, 10, 47, 0, // Skip to: 17098
+/* 5056 */ MCD::OPC_CheckField, 6, 5, 0, 3, 47, 0, // Skip to: 17098
+/* 5063 */ MCD::OPC_Decode, 130, 7, 230, 1, // Opcode: CLO
+/* 5068 */ MCD::OPC_FilterValue, 63, 249, 46, 0, // Skip to: 17098
+/* 5073 */ MCD::OPC_CheckPredicate, 67, 244, 46, 0, // Skip to: 17098
+/* 5078 */ MCD::OPC_Decode, 164, 17, 174, 1, // Opcode: SDBBP
+/* 5083 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 5098
+/* 5088 */ MCD::OPC_CheckPredicate, 67, 229, 46, 0, // Skip to: 17098
+/* 5093 */ MCD::OPC_Decode, 171, 12, 186, 1, // Opcode: JALX
+/* 5098 */ MCD::OPC_FilterValue, 30, 201, 32, 0, // Skip to: 13496
+/* 5103 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 5106 */ MCD::OPC_FilterValue, 0, 63, 0, 0, // Skip to: 5174
+/* 5111 */ MCD::OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 5114 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5129
+/* 5119 */ MCD::OPC_CheckPredicate, 30, 198, 46, 0, // Skip to: 17098
+/* 5124 */ MCD::OPC_Decode, 217, 4, 231, 1, // Opcode: ANDI_B
+/* 5129 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5144
+/* 5134 */ MCD::OPC_CheckPredicate, 30, 183, 46, 0, // Skip to: 17098
+/* 5139 */ MCD::OPC_Decode, 141, 16, 231, 1, // Opcode: ORI_B
+/* 5144 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5159
+/* 5149 */ MCD::OPC_CheckPredicate, 30, 168, 46, 0, // Skip to: 17098
+/* 5154 */ MCD::OPC_Decode, 129, 16, 231, 1, // Opcode: NORI_B
+/* 5159 */ MCD::OPC_FilterValue, 3, 158, 46, 0, // Skip to: 17098
+/* 5164 */ MCD::OPC_CheckPredicate, 30, 153, 46, 0, // Skip to: 17098
+/* 5169 */ MCD::OPC_Decode, 186, 20, 231, 1, // Opcode: XORI_B
+/* 5174 */ MCD::OPC_FilterValue, 1, 48, 0, 0, // Skip to: 5227
+/* 5179 */ MCD::OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 5182 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5197
+/* 5187 */ MCD::OPC_CheckPredicate, 30, 130, 46, 0, // Skip to: 17098
+/* 5192 */ MCD::OPC_Decode, 135, 6, 232, 1, // Opcode: BMNZI_B
+/* 5197 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5212
+/* 5202 */ MCD::OPC_CheckPredicate, 30, 115, 46, 0, // Skip to: 17098
+/* 5207 */ MCD::OPC_Decode, 137, 6, 232, 1, // Opcode: BMZI_B
+/* 5212 */ MCD::OPC_FilterValue, 2, 105, 46, 0, // Skip to: 17098
+/* 5217 */ MCD::OPC_CheckPredicate, 30, 100, 46, 0, // Skip to: 17098
+/* 5222 */ MCD::OPC_Decode, 179, 6, 232, 1, // Opcode: BSELI_B
+/* 5227 */ MCD::OPC_FilterValue, 2, 48, 0, 0, // Skip to: 5280
+/* 5232 */ MCD::OPC_ExtractField, 24, 2, // Inst{25-24} ...
+/* 5235 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5250
+/* 5240 */ MCD::OPC_CheckPredicate, 30, 77, 46, 0, // Skip to: 17098
+/* 5245 */ MCD::OPC_Decode, 216, 17, 231, 1, // Opcode: SHF_B
+/* 5250 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5265
+/* 5255 */ MCD::OPC_CheckPredicate, 30, 62, 46, 0, // Skip to: 17098
+/* 5260 */ MCD::OPC_Decode, 217, 17, 233, 1, // Opcode: SHF_H
+/* 5265 */ MCD::OPC_FilterValue, 2, 52, 46, 0, // Skip to: 17098
+/* 5270 */ MCD::OPC_CheckPredicate, 30, 47, 46, 0, // Skip to: 17098
+/* 5275 */ MCD::OPC_Decode, 218, 17, 234, 1, // Opcode: SHF_W
+/* 5280 */ MCD::OPC_FilterValue, 6, 107, 1, 0, // Skip to: 5648
+/* 5285 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 5288 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5303
+/* 5293 */ MCD::OPC_CheckPredicate, 30, 24, 46, 0, // Skip to: 17098
+/* 5298 */ MCD::OPC_Decode, 185, 4, 235, 1, // Opcode: ADDVI_B
+/* 5303 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5318
+/* 5308 */ MCD::OPC_CheckPredicate, 30, 9, 46, 0, // Skip to: 17098
+/* 5313 */ MCD::OPC_Decode, 187, 4, 236, 1, // Opcode: ADDVI_H
+/* 5318 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5333
+/* 5323 */ MCD::OPC_CheckPredicate, 30, 250, 45, 0, // Skip to: 17098
+/* 5328 */ MCD::OPC_Decode, 188, 4, 237, 1, // Opcode: ADDVI_W
+/* 5333 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5348
+/* 5338 */ MCD::OPC_CheckPredicate, 30, 235, 45, 0, // Skip to: 17098
+/* 5343 */ MCD::OPC_Decode, 186, 4, 238, 1, // Opcode: ADDVI_D
+/* 5348 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 5363
+/* 5353 */ MCD::OPC_CheckPredicate, 30, 220, 45, 0, // Skip to: 17098
+/* 5358 */ MCD::OPC_Decode, 155, 19, 235, 1, // Opcode: SUBVI_B
+/* 5363 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 5378
+/* 5368 */ MCD::OPC_CheckPredicate, 30, 205, 45, 0, // Skip to: 17098
+/* 5373 */ MCD::OPC_Decode, 157, 19, 236, 1, // Opcode: SUBVI_H
+/* 5378 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 5393
+/* 5383 */ MCD::OPC_CheckPredicate, 30, 190, 45, 0, // Skip to: 17098
+/* 5388 */ MCD::OPC_Decode, 158, 19, 237, 1, // Opcode: SUBVI_W
+/* 5393 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 5408
+/* 5398 */ MCD::OPC_CheckPredicate, 30, 175, 45, 0, // Skip to: 17098
+/* 5403 */ MCD::OPC_Decode, 156, 19, 238, 1, // Opcode: SUBVI_D
+/* 5408 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 5423
+/* 5413 */ MCD::OPC_CheckPredicate, 30, 160, 45, 0, // Skip to: 17098
+/* 5418 */ MCD::OPC_Decode, 235, 13, 235, 1, // Opcode: MAXI_S_B
+/* 5423 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 5438
+/* 5428 */ MCD::OPC_CheckPredicate, 30, 145, 45, 0, // Skip to: 17098
+/* 5433 */ MCD::OPC_Decode, 237, 13, 236, 1, // Opcode: MAXI_S_H
+/* 5438 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 5453
+/* 5443 */ MCD::OPC_CheckPredicate, 30, 130, 45, 0, // Skip to: 17098
+/* 5448 */ MCD::OPC_Decode, 238, 13, 237, 1, // Opcode: MAXI_S_W
+/* 5453 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 5468
+/* 5458 */ MCD::OPC_CheckPredicate, 30, 115, 45, 0, // Skip to: 17098
+/* 5463 */ MCD::OPC_Decode, 236, 13, 238, 1, // Opcode: MAXI_S_D
+/* 5468 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 5483
+/* 5473 */ MCD::OPC_CheckPredicate, 30, 100, 45, 0, // Skip to: 17098
+/* 5478 */ MCD::OPC_Decode, 239, 13, 235, 1, // Opcode: MAXI_U_B
+/* 5483 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5498
+/* 5488 */ MCD::OPC_CheckPredicate, 30, 85, 45, 0, // Skip to: 17098
+/* 5493 */ MCD::OPC_Decode, 241, 13, 236, 1, // Opcode: MAXI_U_H
+/* 5498 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 5513
+/* 5503 */ MCD::OPC_CheckPredicate, 30, 70, 45, 0, // Skip to: 17098
+/* 5508 */ MCD::OPC_Decode, 242, 13, 237, 1, // Opcode: MAXI_U_W
+/* 5513 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5528
+/* 5518 */ MCD::OPC_CheckPredicate, 30, 55, 45, 0, // Skip to: 17098
+/* 5523 */ MCD::OPC_Decode, 240, 13, 238, 1, // Opcode: MAXI_U_D
+/* 5528 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 5543
+/* 5533 */ MCD::OPC_CheckPredicate, 30, 40, 45, 0, // Skip to: 17098
+/* 5538 */ MCD::OPC_Decode, 166, 14, 235, 1, // Opcode: MINI_S_B
+/* 5543 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 5558
+/* 5548 */ MCD::OPC_CheckPredicate, 30, 25, 45, 0, // Skip to: 17098
+/* 5553 */ MCD::OPC_Decode, 168, 14, 236, 1, // Opcode: MINI_S_H
+/* 5558 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 5573
+/* 5563 */ MCD::OPC_CheckPredicate, 30, 10, 45, 0, // Skip to: 17098
+/* 5568 */ MCD::OPC_Decode, 169, 14, 237, 1, // Opcode: MINI_S_W
+/* 5573 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 5588
+/* 5578 */ MCD::OPC_CheckPredicate, 30, 251, 44, 0, // Skip to: 17098
+/* 5583 */ MCD::OPC_Decode, 167, 14, 238, 1, // Opcode: MINI_S_D
+/* 5588 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 5603
+/* 5593 */ MCD::OPC_CheckPredicate, 30, 236, 44, 0, // Skip to: 17098
+/* 5598 */ MCD::OPC_Decode, 170, 14, 235, 1, // Opcode: MINI_U_B
+/* 5603 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 5618
+/* 5608 */ MCD::OPC_CheckPredicate, 30, 221, 44, 0, // Skip to: 17098
+/* 5613 */ MCD::OPC_Decode, 172, 14, 236, 1, // Opcode: MINI_U_H
+/* 5618 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 5633
+/* 5623 */ MCD::OPC_CheckPredicate, 30, 206, 44, 0, // Skip to: 17098
+/* 5628 */ MCD::OPC_Decode, 173, 14, 237, 1, // Opcode: MINI_U_W
+/* 5633 */ MCD::OPC_FilterValue, 23, 196, 44, 0, // Skip to: 17098
+/* 5638 */ MCD::OPC_CheckPredicate, 30, 191, 44, 0, // Skip to: 17098
+/* 5643 */ MCD::OPC_Decode, 171, 14, 238, 1, // Opcode: MINI_U_D
+/* 5648 */ MCD::OPC_FilterValue, 7, 107, 1, 0, // Skip to: 6016
+/* 5653 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 5656 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5671
+/* 5661 */ MCD::OPC_CheckPredicate, 30, 168, 44, 0, // Skip to: 17098
+/* 5666 */ MCD::OPC_Decode, 222, 6, 235, 1, // Opcode: CEQI_B
+/* 5671 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5686
+/* 5676 */ MCD::OPC_CheckPredicate, 30, 153, 44, 0, // Skip to: 17098
+/* 5681 */ MCD::OPC_Decode, 224, 6, 236, 1, // Opcode: CEQI_H
+/* 5686 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 5701
+/* 5691 */ MCD::OPC_CheckPredicate, 30, 138, 44, 0, // Skip to: 17098
+/* 5696 */ MCD::OPC_Decode, 225, 6, 237, 1, // Opcode: CEQI_W
+/* 5701 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 5716
+/* 5706 */ MCD::OPC_CheckPredicate, 30, 123, 44, 0, // Skip to: 17098
+/* 5711 */ MCD::OPC_Decode, 223, 6, 238, 1, // Opcode: CEQI_D
+/* 5716 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 5731
+/* 5721 */ MCD::OPC_CheckPredicate, 30, 108, 44, 0, // Skip to: 17098
+/* 5726 */ MCD::OPC_Decode, 134, 7, 235, 1, // Opcode: CLTI_S_B
+/* 5731 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 5746
+/* 5736 */ MCD::OPC_CheckPredicate, 30, 93, 44, 0, // Skip to: 17098
+/* 5741 */ MCD::OPC_Decode, 136, 7, 236, 1, // Opcode: CLTI_S_H
+/* 5746 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 5761
+/* 5751 */ MCD::OPC_CheckPredicate, 30, 78, 44, 0, // Skip to: 17098
+/* 5756 */ MCD::OPC_Decode, 137, 7, 237, 1, // Opcode: CLTI_S_W
+/* 5761 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 5776
+/* 5766 */ MCD::OPC_CheckPredicate, 30, 63, 44, 0, // Skip to: 17098
+/* 5771 */ MCD::OPC_Decode, 135, 7, 238, 1, // Opcode: CLTI_S_D
+/* 5776 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 5791
+/* 5781 */ MCD::OPC_CheckPredicate, 30, 48, 44, 0, // Skip to: 17098
+/* 5786 */ MCD::OPC_Decode, 138, 7, 235, 1, // Opcode: CLTI_U_B
+/* 5791 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5806
+/* 5796 */ MCD::OPC_CheckPredicate, 30, 33, 44, 0, // Skip to: 17098
+/* 5801 */ MCD::OPC_Decode, 140, 7, 236, 1, // Opcode: CLTI_U_H
+/* 5806 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 5821
+/* 5811 */ MCD::OPC_CheckPredicate, 30, 18, 44, 0, // Skip to: 17098
+/* 5816 */ MCD::OPC_Decode, 141, 7, 237, 1, // Opcode: CLTI_U_W
+/* 5821 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5836
+/* 5826 */ MCD::OPC_CheckPredicate, 30, 3, 44, 0, // Skip to: 17098
+/* 5831 */ MCD::OPC_Decode, 139, 7, 238, 1, // Opcode: CLTI_U_D
+/* 5836 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 5851
+/* 5841 */ MCD::OPC_CheckPredicate, 30, 244, 43, 0, // Skip to: 17098
+/* 5846 */ MCD::OPC_Decode, 242, 6, 235, 1, // Opcode: CLEI_S_B
+/* 5851 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 5866
+/* 5856 */ MCD::OPC_CheckPredicate, 30, 229, 43, 0, // Skip to: 17098
+/* 5861 */ MCD::OPC_Decode, 244, 6, 236, 1, // Opcode: CLEI_S_H
+/* 5866 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 5881
+/* 5871 */ MCD::OPC_CheckPredicate, 30, 214, 43, 0, // Skip to: 17098
+/* 5876 */ MCD::OPC_Decode, 245, 6, 237, 1, // Opcode: CLEI_S_W
+/* 5881 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 5896
+/* 5886 */ MCD::OPC_CheckPredicate, 30, 199, 43, 0, // Skip to: 17098
+/* 5891 */ MCD::OPC_Decode, 243, 6, 238, 1, // Opcode: CLEI_S_D
+/* 5896 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 5911
+/* 5901 */ MCD::OPC_CheckPredicate, 30, 184, 43, 0, // Skip to: 17098
+/* 5906 */ MCD::OPC_Decode, 246, 6, 235, 1, // Opcode: CLEI_U_B
+/* 5911 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 5926
+/* 5916 */ MCD::OPC_CheckPredicate, 30, 169, 43, 0, // Skip to: 17098
+/* 5921 */ MCD::OPC_Decode, 248, 6, 236, 1, // Opcode: CLEI_U_H
+/* 5926 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 5941
+/* 5931 */ MCD::OPC_CheckPredicate, 30, 154, 43, 0, // Skip to: 17098
+/* 5936 */ MCD::OPC_Decode, 249, 6, 237, 1, // Opcode: CLEI_U_W
+/* 5941 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 5956
+/* 5946 */ MCD::OPC_CheckPredicate, 30, 139, 43, 0, // Skip to: 17098
+/* 5951 */ MCD::OPC_Decode, 247, 6, 238, 1, // Opcode: CLEI_U_D
+/* 5956 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 5971
+/* 5961 */ MCD::OPC_CheckPredicate, 30, 124, 43, 0, // Skip to: 17098
+/* 5966 */ MCD::OPC_Decode, 223, 12, 239, 1, // Opcode: LDI_B
+/* 5971 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 5986
+/* 5976 */ MCD::OPC_CheckPredicate, 30, 109, 43, 0, // Skip to: 17098
+/* 5981 */ MCD::OPC_Decode, 225, 12, 240, 1, // Opcode: LDI_H
+/* 5986 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 6001
+/* 5991 */ MCD::OPC_CheckPredicate, 30, 94, 43, 0, // Skip to: 17098
+/* 5996 */ MCD::OPC_Decode, 226, 12, 241, 1, // Opcode: LDI_W
+/* 6001 */ MCD::OPC_FilterValue, 27, 84, 43, 0, // Skip to: 17098
+/* 6006 */ MCD::OPC_CheckPredicate, 30, 79, 43, 0, // Skip to: 17098
+/* 6011 */ MCD::OPC_Decode, 224, 12, 242, 1, // Opcode: LDI_D
+/* 6016 */ MCD::OPC_FilterValue, 9, 155, 2, 0, // Skip to: 6688
+/* 6021 */ MCD::OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 6024 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6039
+/* 6029 */ MCD::OPC_CheckPredicate, 30, 56, 43, 0, // Skip to: 17098
+/* 6034 */ MCD::OPC_Decode, 155, 18, 243, 1, // Opcode: SLLI_D
+/* 6039 */ MCD::OPC_FilterValue, 1, 63, 0, 0, // Skip to: 6107
+/* 6044 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6047 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6062
+/* 6052 */ MCD::OPC_CheckPredicate, 30, 33, 43, 0, // Skip to: 17098
+/* 6057 */ MCD::OPC_Decode, 157, 18, 237, 1, // Opcode: SLLI_W
+/* 6062 */ MCD::OPC_FilterValue, 1, 23, 43, 0, // Skip to: 17098
+/* 6067 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6070 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6085
+/* 6075 */ MCD::OPC_CheckPredicate, 30, 10, 43, 0, // Skip to: 17098
+/* 6080 */ MCD::OPC_Decode, 156, 18, 244, 1, // Opcode: SLLI_H
+/* 6085 */ MCD::OPC_FilterValue, 1, 0, 43, 0, // Skip to: 17098
+/* 6090 */ MCD::OPC_CheckPredicate, 30, 251, 42, 0, // Skip to: 17098
+/* 6095 */ MCD::OPC_CheckField, 19, 1, 0, 244, 42, 0, // Skip to: 17098
+/* 6102 */ MCD::OPC_Decode, 154, 18, 245, 1, // Opcode: SLLI_B
+/* 6107 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6122
+/* 6112 */ MCD::OPC_CheckPredicate, 30, 229, 42, 0, // Skip to: 17098
+/* 6117 */ MCD::OPC_Decode, 190, 18, 243, 1, // Opcode: SRAI_D
+/* 6122 */ MCD::OPC_FilterValue, 3, 63, 0, 0, // Skip to: 6190
+/* 6127 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6130 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6145
+/* 6135 */ MCD::OPC_CheckPredicate, 30, 206, 42, 0, // Skip to: 17098
+/* 6140 */ MCD::OPC_Decode, 192, 18, 237, 1, // Opcode: SRAI_W
+/* 6145 */ MCD::OPC_FilterValue, 1, 196, 42, 0, // Skip to: 17098
+/* 6150 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6153 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6168
+/* 6158 */ MCD::OPC_CheckPredicate, 30, 183, 42, 0, // Skip to: 17098
+/* 6163 */ MCD::OPC_Decode, 191, 18, 244, 1, // Opcode: SRAI_H
+/* 6168 */ MCD::OPC_FilterValue, 1, 173, 42, 0, // Skip to: 17098
+/* 6173 */ MCD::OPC_CheckPredicate, 30, 168, 42, 0, // Skip to: 17098
+/* 6178 */ MCD::OPC_CheckField, 19, 1, 0, 161, 42, 0, // Skip to: 17098
+/* 6185 */ MCD::OPC_Decode, 189, 18, 245, 1, // Opcode: SRAI_B
+/* 6190 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6205
+/* 6195 */ MCD::OPC_CheckPredicate, 30, 146, 42, 0, // Skip to: 17098
+/* 6200 */ MCD::OPC_Decode, 212, 18, 243, 1, // Opcode: SRLI_D
+/* 6205 */ MCD::OPC_FilterValue, 5, 63, 0, 0, // Skip to: 6273
+/* 6210 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6213 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6228
+/* 6218 */ MCD::OPC_CheckPredicate, 30, 123, 42, 0, // Skip to: 17098
+/* 6223 */ MCD::OPC_Decode, 214, 18, 237, 1, // Opcode: SRLI_W
+/* 6228 */ MCD::OPC_FilterValue, 1, 113, 42, 0, // Skip to: 17098
+/* 6233 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6236 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6251
+/* 6241 */ MCD::OPC_CheckPredicate, 30, 100, 42, 0, // Skip to: 17098
+/* 6246 */ MCD::OPC_Decode, 213, 18, 244, 1, // Opcode: SRLI_H
+/* 6251 */ MCD::OPC_FilterValue, 1, 90, 42, 0, // Skip to: 17098
+/* 6256 */ MCD::OPC_CheckPredicate, 30, 85, 42, 0, // Skip to: 17098
+/* 6261 */ MCD::OPC_CheckField, 19, 1, 0, 78, 42, 0, // Skip to: 17098
+/* 6268 */ MCD::OPC_Decode, 211, 18, 245, 1, // Opcode: SRLI_B
+/* 6273 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6288
+/* 6278 */ MCD::OPC_CheckPredicate, 30, 63, 42, 0, // Skip to: 17098
+/* 6283 */ MCD::OPC_Decode, 164, 5, 243, 1, // Opcode: BCLRI_D
+/* 6288 */ MCD::OPC_FilterValue, 7, 63, 0, 0, // Skip to: 6356
+/* 6293 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6296 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6311
+/* 6301 */ MCD::OPC_CheckPredicate, 30, 40, 42, 0, // Skip to: 17098
+/* 6306 */ MCD::OPC_Decode, 166, 5, 237, 1, // Opcode: BCLRI_W
+/* 6311 */ MCD::OPC_FilterValue, 1, 30, 42, 0, // Skip to: 17098
+/* 6316 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6319 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6334
+/* 6324 */ MCD::OPC_CheckPredicate, 30, 17, 42, 0, // Skip to: 17098
+/* 6329 */ MCD::OPC_Decode, 165, 5, 244, 1, // Opcode: BCLRI_H
+/* 6334 */ MCD::OPC_FilterValue, 1, 7, 42, 0, // Skip to: 17098
+/* 6339 */ MCD::OPC_CheckPredicate, 30, 2, 42, 0, // Skip to: 17098
+/* 6344 */ MCD::OPC_CheckField, 19, 1, 0, 251, 41, 0, // Skip to: 17098
+/* 6351 */ MCD::OPC_Decode, 163, 5, 245, 1, // Opcode: BCLRI_B
+/* 6356 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 6371
+/* 6361 */ MCD::OPC_CheckPredicate, 30, 236, 41, 0, // Skip to: 17098
+/* 6366 */ MCD::OPC_Decode, 182, 6, 243, 1, // Opcode: BSETI_D
+/* 6371 */ MCD::OPC_FilterValue, 9, 63, 0, 0, // Skip to: 6439
+/* 6376 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6379 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6394
+/* 6384 */ MCD::OPC_CheckPredicate, 30, 213, 41, 0, // Skip to: 17098
+/* 6389 */ MCD::OPC_Decode, 184, 6, 237, 1, // Opcode: BSETI_W
+/* 6394 */ MCD::OPC_FilterValue, 1, 203, 41, 0, // Skip to: 17098
+/* 6399 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6402 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6417
+/* 6407 */ MCD::OPC_CheckPredicate, 30, 190, 41, 0, // Skip to: 17098
+/* 6412 */ MCD::OPC_Decode, 183, 6, 244, 1, // Opcode: BSETI_H
+/* 6417 */ MCD::OPC_FilterValue, 1, 180, 41, 0, // Skip to: 17098
+/* 6422 */ MCD::OPC_CheckPredicate, 30, 175, 41, 0, // Skip to: 17098
+/* 6427 */ MCD::OPC_CheckField, 19, 1, 0, 168, 41, 0, // Skip to: 17098
+/* 6434 */ MCD::OPC_Decode, 181, 6, 245, 1, // Opcode: BSETI_B
+/* 6439 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 6454
+/* 6444 */ MCD::OPC_CheckPredicate, 30, 153, 41, 0, // Skip to: 17098
+/* 6449 */ MCD::OPC_Decode, 145, 6, 243, 1, // Opcode: BNEGI_D
+/* 6454 */ MCD::OPC_FilterValue, 11, 63, 0, 0, // Skip to: 6522
+/* 6459 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6462 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6477
+/* 6467 */ MCD::OPC_CheckPredicate, 30, 130, 41, 0, // Skip to: 17098
+/* 6472 */ MCD::OPC_Decode, 147, 6, 237, 1, // Opcode: BNEGI_W
+/* 6477 */ MCD::OPC_FilterValue, 1, 120, 41, 0, // Skip to: 17098
+/* 6482 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6485 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6500
+/* 6490 */ MCD::OPC_CheckPredicate, 30, 107, 41, 0, // Skip to: 17098
+/* 6495 */ MCD::OPC_Decode, 146, 6, 244, 1, // Opcode: BNEGI_H
+/* 6500 */ MCD::OPC_FilterValue, 1, 97, 41, 0, // Skip to: 17098
+/* 6505 */ MCD::OPC_CheckPredicate, 30, 92, 41, 0, // Skip to: 17098
+/* 6510 */ MCD::OPC_CheckField, 19, 1, 0, 85, 41, 0, // Skip to: 17098
+/* 6517 */ MCD::OPC_Decode, 144, 6, 245, 1, // Opcode: BNEGI_B
+/* 6522 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 6537
+/* 6527 */ MCD::OPC_CheckPredicate, 30, 70, 41, 0, // Skip to: 17098
+/* 6532 */ MCD::OPC_Decode, 216, 5, 246, 1, // Opcode: BINSLI_D
+/* 6537 */ MCD::OPC_FilterValue, 13, 63, 0, 0, // Skip to: 6605
+/* 6542 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6545 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6560
+/* 6550 */ MCD::OPC_CheckPredicate, 30, 47, 41, 0, // Skip to: 17098
+/* 6555 */ MCD::OPC_Decode, 218, 5, 247, 1, // Opcode: BINSLI_W
+/* 6560 */ MCD::OPC_FilterValue, 1, 37, 41, 0, // Skip to: 17098
+/* 6565 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6568 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6583
+/* 6573 */ MCD::OPC_CheckPredicate, 30, 24, 41, 0, // Skip to: 17098
+/* 6578 */ MCD::OPC_Decode, 217, 5, 248, 1, // Opcode: BINSLI_H
+/* 6583 */ MCD::OPC_FilterValue, 1, 14, 41, 0, // Skip to: 17098
+/* 6588 */ MCD::OPC_CheckPredicate, 30, 9, 41, 0, // Skip to: 17098
+/* 6593 */ MCD::OPC_CheckField, 19, 1, 0, 2, 41, 0, // Skip to: 17098
+/* 6600 */ MCD::OPC_Decode, 215, 5, 249, 1, // Opcode: BINSLI_B
+/* 6605 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 6620
+/* 6610 */ MCD::OPC_CheckPredicate, 30, 243, 40, 0, // Skip to: 17098
+/* 6615 */ MCD::OPC_Decode, 224, 5, 246, 1, // Opcode: BINSRI_D
+/* 6620 */ MCD::OPC_FilterValue, 15, 233, 40, 0, // Skip to: 17098
+/* 6625 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6628 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6643
+/* 6633 */ MCD::OPC_CheckPredicate, 30, 220, 40, 0, // Skip to: 17098
+/* 6638 */ MCD::OPC_Decode, 226, 5, 247, 1, // Opcode: BINSRI_W
+/* 6643 */ MCD::OPC_FilterValue, 1, 210, 40, 0, // Skip to: 17098
+/* 6648 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6651 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6666
+/* 6656 */ MCD::OPC_CheckPredicate, 30, 197, 40, 0, // Skip to: 17098
+/* 6661 */ MCD::OPC_Decode, 225, 5, 248, 1, // Opcode: BINSRI_H
+/* 6666 */ MCD::OPC_FilterValue, 1, 187, 40, 0, // Skip to: 17098
+/* 6671 */ MCD::OPC_CheckPredicate, 30, 182, 40, 0, // Skip to: 17098
+/* 6676 */ MCD::OPC_CheckField, 19, 1, 0, 175, 40, 0, // Skip to: 17098
+/* 6683 */ MCD::OPC_Decode, 223, 5, 249, 1, // Opcode: BINSRI_B
+/* 6688 */ MCD::OPC_FilterValue, 10, 79, 1, 0, // Skip to: 7028
+/* 6693 */ MCD::OPC_ExtractField, 22, 4, // Inst{25-22} ...
+/* 6696 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6711
+/* 6701 */ MCD::OPC_CheckPredicate, 30, 152, 40, 0, // Skip to: 17098
+/* 6706 */ MCD::OPC_Decode, 138, 17, 243, 1, // Opcode: SAT_S_D
+/* 6711 */ MCD::OPC_FilterValue, 1, 63, 0, 0, // Skip to: 6779
+/* 6716 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6719 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6734
+/* 6724 */ MCD::OPC_CheckPredicate, 30, 129, 40, 0, // Skip to: 17098
+/* 6729 */ MCD::OPC_Decode, 140, 17, 237, 1, // Opcode: SAT_S_W
+/* 6734 */ MCD::OPC_FilterValue, 1, 119, 40, 0, // Skip to: 17098
+/* 6739 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6742 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6757
+/* 6747 */ MCD::OPC_CheckPredicate, 30, 106, 40, 0, // Skip to: 17098
+/* 6752 */ MCD::OPC_Decode, 139, 17, 244, 1, // Opcode: SAT_S_H
+/* 6757 */ MCD::OPC_FilterValue, 1, 96, 40, 0, // Skip to: 17098
+/* 6762 */ MCD::OPC_CheckPredicate, 30, 91, 40, 0, // Skip to: 17098
+/* 6767 */ MCD::OPC_CheckField, 19, 1, 0, 84, 40, 0, // Skip to: 17098
+/* 6774 */ MCD::OPC_Decode, 137, 17, 245, 1, // Opcode: SAT_S_B
+/* 6779 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6794
+/* 6784 */ MCD::OPC_CheckPredicate, 30, 69, 40, 0, // Skip to: 17098
+/* 6789 */ MCD::OPC_Decode, 142, 17, 243, 1, // Opcode: SAT_U_D
+/* 6794 */ MCD::OPC_FilterValue, 3, 63, 0, 0, // Skip to: 6862
+/* 6799 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6802 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6817
+/* 6807 */ MCD::OPC_CheckPredicate, 30, 46, 40, 0, // Skip to: 17098
+/* 6812 */ MCD::OPC_Decode, 144, 17, 237, 1, // Opcode: SAT_U_W
+/* 6817 */ MCD::OPC_FilterValue, 1, 36, 40, 0, // Skip to: 17098
+/* 6822 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6825 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6840
+/* 6830 */ MCD::OPC_CheckPredicate, 30, 23, 40, 0, // Skip to: 17098
+/* 6835 */ MCD::OPC_Decode, 143, 17, 244, 1, // Opcode: SAT_U_H
+/* 6840 */ MCD::OPC_FilterValue, 1, 13, 40, 0, // Skip to: 17098
+/* 6845 */ MCD::OPC_CheckPredicate, 30, 8, 40, 0, // Skip to: 17098
+/* 6850 */ MCD::OPC_CheckField, 19, 1, 0, 1, 40, 0, // Skip to: 17098
+/* 6857 */ MCD::OPC_Decode, 141, 17, 245, 1, // Opcode: SAT_U_B
+/* 6862 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 6877
+/* 6867 */ MCD::OPC_CheckPredicate, 30, 242, 39, 0, // Skip to: 17098
+/* 6872 */ MCD::OPC_Decode, 194, 18, 243, 1, // Opcode: SRARI_D
+/* 6877 */ MCD::OPC_FilterValue, 5, 63, 0, 0, // Skip to: 6945
+/* 6882 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6885 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6900
+/* 6890 */ MCD::OPC_CheckPredicate, 30, 219, 39, 0, // Skip to: 17098
+/* 6895 */ MCD::OPC_Decode, 196, 18, 237, 1, // Opcode: SRARI_W
+/* 6900 */ MCD::OPC_FilterValue, 1, 209, 39, 0, // Skip to: 17098
+/* 6905 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6908 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6923
+/* 6913 */ MCD::OPC_CheckPredicate, 30, 196, 39, 0, // Skip to: 17098
+/* 6918 */ MCD::OPC_Decode, 195, 18, 244, 1, // Opcode: SRARI_H
+/* 6923 */ MCD::OPC_FilterValue, 1, 186, 39, 0, // Skip to: 17098
+/* 6928 */ MCD::OPC_CheckPredicate, 30, 181, 39, 0, // Skip to: 17098
+/* 6933 */ MCD::OPC_CheckField, 19, 1, 0, 174, 39, 0, // Skip to: 17098
+/* 6940 */ MCD::OPC_Decode, 193, 18, 245, 1, // Opcode: SRARI_B
+/* 6945 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 6960
+/* 6950 */ MCD::OPC_CheckPredicate, 30, 159, 39, 0, // Skip to: 17098
+/* 6955 */ MCD::OPC_Decode, 216, 18, 243, 1, // Opcode: SRLRI_D
+/* 6960 */ MCD::OPC_FilterValue, 7, 149, 39, 0, // Skip to: 17098
+/* 6965 */ MCD::OPC_ExtractField, 21, 1, // Inst{21} ...
+/* 6968 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6983
+/* 6973 */ MCD::OPC_CheckPredicate, 30, 136, 39, 0, // Skip to: 17098
+/* 6978 */ MCD::OPC_Decode, 218, 18, 237, 1, // Opcode: SRLRI_W
+/* 6983 */ MCD::OPC_FilterValue, 1, 126, 39, 0, // Skip to: 17098
+/* 6988 */ MCD::OPC_ExtractField, 20, 1, // Inst{20} ...
+/* 6991 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7006
+/* 6996 */ MCD::OPC_CheckPredicate, 30, 113, 39, 0, // Skip to: 17098
+/* 7001 */ MCD::OPC_Decode, 217, 18, 244, 1, // Opcode: SRLRI_H
+/* 7006 */ MCD::OPC_FilterValue, 1, 103, 39, 0, // Skip to: 17098
+/* 7011 */ MCD::OPC_CheckPredicate, 30, 98, 39, 0, // Skip to: 17098
+/* 7016 */ MCD::OPC_CheckField, 19, 1, 0, 91, 39, 0, // Skip to: 17098
+/* 7023 */ MCD::OPC_Decode, 215, 18, 245, 1, // Opcode: SRLRI_B
+/* 7028 */ MCD::OPC_FilterValue, 13, 227, 1, 0, // Skip to: 7516
+/* 7033 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 7036 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7051
+/* 7041 */ MCD::OPC_CheckPredicate, 30, 68, 39, 0, // Skip to: 17098
+/* 7046 */ MCD::OPC_Decode, 160, 18, 250, 1, // Opcode: SLL_B
+/* 7051 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7066
+/* 7056 */ MCD::OPC_CheckPredicate, 30, 53, 39, 0, // Skip to: 17098
+/* 7061 */ MCD::OPC_Decode, 162, 18, 251, 1, // Opcode: SLL_H
+/* 7066 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7081
+/* 7071 */ MCD::OPC_CheckPredicate, 30, 38, 39, 0, // Skip to: 17098
+/* 7076 */ MCD::OPC_Decode, 165, 18, 252, 1, // Opcode: SLL_W
+/* 7081 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7096
+/* 7086 */ MCD::OPC_CheckPredicate, 30, 23, 39, 0, // Skip to: 17098
+/* 7091 */ MCD::OPC_Decode, 161, 18, 253, 1, // Opcode: SLL_D
+/* 7096 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 7111
+/* 7101 */ MCD::OPC_CheckPredicate, 30, 8, 39, 0, // Skip to: 17098
+/* 7106 */ MCD::OPC_Decode, 203, 18, 250, 1, // Opcode: SRA_B
+/* 7111 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 7126
+/* 7116 */ MCD::OPC_CheckPredicate, 30, 249, 38, 0, // Skip to: 17098
+/* 7121 */ MCD::OPC_Decode, 205, 18, 251, 1, // Opcode: SRA_H
+/* 7126 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 7141
+/* 7131 */ MCD::OPC_CheckPredicate, 30, 234, 38, 0, // Skip to: 17098
+/* 7136 */ MCD::OPC_Decode, 207, 18, 252, 1, // Opcode: SRA_W
+/* 7141 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 7156
+/* 7146 */ MCD::OPC_CheckPredicate, 30, 219, 38, 0, // Skip to: 17098
+/* 7151 */ MCD::OPC_Decode, 204, 18, 253, 1, // Opcode: SRA_D
+/* 7156 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 7171
+/* 7161 */ MCD::OPC_CheckPredicate, 30, 204, 38, 0, // Skip to: 17098
+/* 7166 */ MCD::OPC_Decode, 225, 18, 250, 1, // Opcode: SRL_B
+/* 7171 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 7186
+/* 7176 */ MCD::OPC_CheckPredicate, 30, 189, 38, 0, // Skip to: 17098
+/* 7181 */ MCD::OPC_Decode, 227, 18, 251, 1, // Opcode: SRL_H
+/* 7186 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 7201
+/* 7191 */ MCD::OPC_CheckPredicate, 30, 174, 38, 0, // Skip to: 17098
+/* 7196 */ MCD::OPC_Decode, 229, 18, 252, 1, // Opcode: SRL_W
+/* 7201 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 7216
+/* 7206 */ MCD::OPC_CheckPredicate, 30, 159, 38, 0, // Skip to: 17098
+/* 7211 */ MCD::OPC_Decode, 226, 18, 253, 1, // Opcode: SRL_D
+/* 7216 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 7231
+/* 7221 */ MCD::OPC_CheckPredicate, 30, 144, 38, 0, // Skip to: 17098
+/* 7226 */ MCD::OPC_Decode, 167, 5, 250, 1, // Opcode: BCLR_B
+/* 7231 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 7246
+/* 7236 */ MCD::OPC_CheckPredicate, 30, 129, 38, 0, // Skip to: 17098
+/* 7241 */ MCD::OPC_Decode, 169, 5, 251, 1, // Opcode: BCLR_H
+/* 7246 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7261
+/* 7251 */ MCD::OPC_CheckPredicate, 30, 114, 38, 0, // Skip to: 17098
+/* 7256 */ MCD::OPC_Decode, 170, 5, 252, 1, // Opcode: BCLR_W
+/* 7261 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 7276
+/* 7266 */ MCD::OPC_CheckPredicate, 30, 99, 38, 0, // Skip to: 17098
+/* 7271 */ MCD::OPC_Decode, 168, 5, 253, 1, // Opcode: BCLR_D
+/* 7276 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 7291
+/* 7281 */ MCD::OPC_CheckPredicate, 30, 84, 38, 0, // Skip to: 17098
+/* 7286 */ MCD::OPC_Decode, 185, 6, 250, 1, // Opcode: BSET_B
+/* 7291 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 7306
+/* 7296 */ MCD::OPC_CheckPredicate, 30, 69, 38, 0, // Skip to: 17098
+/* 7301 */ MCD::OPC_Decode, 187, 6, 251, 1, // Opcode: BSET_H
+/* 7306 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 7321
+/* 7311 */ MCD::OPC_CheckPredicate, 30, 54, 38, 0, // Skip to: 17098
+/* 7316 */ MCD::OPC_Decode, 188, 6, 252, 1, // Opcode: BSET_W
+/* 7321 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 7336
+/* 7326 */ MCD::OPC_CheckPredicate, 30, 39, 38, 0, // Skip to: 17098
+/* 7331 */ MCD::OPC_Decode, 186, 6, 253, 1, // Opcode: BSET_D
+/* 7336 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 7351
+/* 7341 */ MCD::OPC_CheckPredicate, 30, 24, 38, 0, // Skip to: 17098
+/* 7346 */ MCD::OPC_Decode, 148, 6, 250, 1, // Opcode: BNEG_B
+/* 7351 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 7366
+/* 7356 */ MCD::OPC_CheckPredicate, 30, 9, 38, 0, // Skip to: 17098
+/* 7361 */ MCD::OPC_Decode, 150, 6, 251, 1, // Opcode: BNEG_H
+/* 7366 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 7381
+/* 7371 */ MCD::OPC_CheckPredicate, 30, 250, 37, 0, // Skip to: 17098
+/* 7376 */ MCD::OPC_Decode, 151, 6, 252, 1, // Opcode: BNEG_W
+/* 7381 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 7396
+/* 7386 */ MCD::OPC_CheckPredicate, 30, 235, 37, 0, // Skip to: 17098
+/* 7391 */ MCD::OPC_Decode, 149, 6, 253, 1, // Opcode: BNEG_D
+/* 7396 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 7411
+/* 7401 */ MCD::OPC_CheckPredicate, 30, 220, 37, 0, // Skip to: 17098
+/* 7406 */ MCD::OPC_Decode, 219, 5, 254, 1, // Opcode: BINSL_B
+/* 7411 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 7426
+/* 7416 */ MCD::OPC_CheckPredicate, 30, 205, 37, 0, // Skip to: 17098
+/* 7421 */ MCD::OPC_Decode, 221, 5, 255, 1, // Opcode: BINSL_H
+/* 7426 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 7441
+/* 7431 */ MCD::OPC_CheckPredicate, 30, 190, 37, 0, // Skip to: 17098
+/* 7436 */ MCD::OPC_Decode, 222, 5, 128, 2, // Opcode: BINSL_W
+/* 7441 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 7456
+/* 7446 */ MCD::OPC_CheckPredicate, 30, 175, 37, 0, // Skip to: 17098
+/* 7451 */ MCD::OPC_Decode, 220, 5, 129, 2, // Opcode: BINSL_D
+/* 7456 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 7471
+/* 7461 */ MCD::OPC_CheckPredicate, 30, 160, 37, 0, // Skip to: 17098
+/* 7466 */ MCD::OPC_Decode, 227, 5, 254, 1, // Opcode: BINSR_B
+/* 7471 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 7486
+/* 7476 */ MCD::OPC_CheckPredicate, 30, 145, 37, 0, // Skip to: 17098
+/* 7481 */ MCD::OPC_Decode, 229, 5, 255, 1, // Opcode: BINSR_H
+/* 7486 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 7501
+/* 7491 */ MCD::OPC_CheckPredicate, 30, 130, 37, 0, // Skip to: 17098
+/* 7496 */ MCD::OPC_Decode, 230, 5, 128, 2, // Opcode: BINSR_W
+/* 7501 */ MCD::OPC_FilterValue, 31, 120, 37, 0, // Skip to: 17098
+/* 7506 */ MCD::OPC_CheckPredicate, 30, 115, 37, 0, // Skip to: 17098
+/* 7511 */ MCD::OPC_Decode, 228, 5, 129, 2, // Opcode: BINSR_D
+/* 7516 */ MCD::OPC_FilterValue, 14, 227, 1, 0, // Skip to: 8004
+/* 7521 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 7524 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7539
+/* 7529 */ MCD::OPC_CheckPredicate, 30, 92, 37, 0, // Skip to: 17098
+/* 7534 */ MCD::OPC_Decode, 189, 4, 250, 1, // Opcode: ADDV_B
+/* 7539 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7554
+/* 7544 */ MCD::OPC_CheckPredicate, 30, 77, 37, 0, // Skip to: 17098
+/* 7549 */ MCD::OPC_Decode, 191, 4, 251, 1, // Opcode: ADDV_H
+/* 7554 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7569
+/* 7559 */ MCD::OPC_CheckPredicate, 30, 62, 37, 0, // Skip to: 17098
+/* 7564 */ MCD::OPC_Decode, 192, 4, 252, 1, // Opcode: ADDV_W
+/* 7569 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 7584
+/* 7574 */ MCD::OPC_CheckPredicate, 30, 47, 37, 0, // Skip to: 17098
+/* 7579 */ MCD::OPC_Decode, 190, 4, 253, 1, // Opcode: ADDV_D
+/* 7584 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 7599
+/* 7589 */ MCD::OPC_CheckPredicate, 30, 32, 37, 0, // Skip to: 17098
+/* 7594 */ MCD::OPC_Decode, 159, 19, 250, 1, // Opcode: SUBV_B
+/* 7599 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 7614
+/* 7604 */ MCD::OPC_CheckPredicate, 30, 17, 37, 0, // Skip to: 17098
+/* 7609 */ MCD::OPC_Decode, 161, 19, 251, 1, // Opcode: SUBV_H
+/* 7614 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 7629
+/* 7619 */ MCD::OPC_CheckPredicate, 30, 2, 37, 0, // Skip to: 17098
+/* 7624 */ MCD::OPC_Decode, 162, 19, 252, 1, // Opcode: SUBV_W
+/* 7629 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 7644
+/* 7634 */ MCD::OPC_CheckPredicate, 30, 243, 36, 0, // Skip to: 17098
+/* 7639 */ MCD::OPC_Decode, 160, 19, 253, 1, // Opcode: SUBV_D
+/* 7644 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 7659
+/* 7649 */ MCD::OPC_CheckPredicate, 30, 228, 36, 0, // Skip to: 17098
+/* 7654 */ MCD::OPC_Decode, 250, 13, 250, 1, // Opcode: MAX_S_B
+/* 7659 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 7674
+/* 7664 */ MCD::OPC_CheckPredicate, 30, 213, 36, 0, // Skip to: 17098
+/* 7669 */ MCD::OPC_Decode, 252, 13, 251, 1, // Opcode: MAX_S_H
+/* 7674 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 7689
+/* 7679 */ MCD::OPC_CheckPredicate, 30, 198, 36, 0, // Skip to: 17098
+/* 7684 */ MCD::OPC_Decode, 254, 13, 252, 1, // Opcode: MAX_S_W
+/* 7689 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 7704
+/* 7694 */ MCD::OPC_CheckPredicate, 30, 183, 36, 0, // Skip to: 17098
+/* 7699 */ MCD::OPC_Decode, 251, 13, 253, 1, // Opcode: MAX_S_D
+/* 7704 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 7719
+/* 7709 */ MCD::OPC_CheckPredicate, 30, 168, 36, 0, // Skip to: 17098
+/* 7714 */ MCD::OPC_Decode, 255, 13, 250, 1, // Opcode: MAX_U_B
+/* 7719 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 7734
+/* 7724 */ MCD::OPC_CheckPredicate, 30, 153, 36, 0, // Skip to: 17098
+/* 7729 */ MCD::OPC_Decode, 129, 14, 251, 1, // Opcode: MAX_U_H
+/* 7734 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7749
+/* 7739 */ MCD::OPC_CheckPredicate, 30, 138, 36, 0, // Skip to: 17098
+/* 7744 */ MCD::OPC_Decode, 130, 14, 252, 1, // Opcode: MAX_U_W
+/* 7749 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 7764
+/* 7754 */ MCD::OPC_CheckPredicate, 30, 123, 36, 0, // Skip to: 17098
+/* 7759 */ MCD::OPC_Decode, 128, 14, 253, 1, // Opcode: MAX_U_D
+/* 7764 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 7779
+/* 7769 */ MCD::OPC_CheckPredicate, 30, 108, 36, 0, // Skip to: 17098
+/* 7774 */ MCD::OPC_Decode, 181, 14, 250, 1, // Opcode: MIN_S_B
+/* 7779 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 7794
+/* 7784 */ MCD::OPC_CheckPredicate, 30, 93, 36, 0, // Skip to: 17098
+/* 7789 */ MCD::OPC_Decode, 183, 14, 251, 1, // Opcode: MIN_S_H
+/* 7794 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 7809
+/* 7799 */ MCD::OPC_CheckPredicate, 30, 78, 36, 0, // Skip to: 17098
+/* 7804 */ MCD::OPC_Decode, 185, 14, 252, 1, // Opcode: MIN_S_W
+/* 7809 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 7824
+/* 7814 */ MCD::OPC_CheckPredicate, 30, 63, 36, 0, // Skip to: 17098
+/* 7819 */ MCD::OPC_Decode, 182, 14, 253, 1, // Opcode: MIN_S_D
+/* 7824 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 7839
+/* 7829 */ MCD::OPC_CheckPredicate, 30, 48, 36, 0, // Skip to: 17098
+/* 7834 */ MCD::OPC_Decode, 186, 14, 250, 1, // Opcode: MIN_U_B
+/* 7839 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 7854
+/* 7844 */ MCD::OPC_CheckPredicate, 30, 33, 36, 0, // Skip to: 17098
+/* 7849 */ MCD::OPC_Decode, 188, 14, 251, 1, // Opcode: MIN_U_H
+/* 7854 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 7869
+/* 7859 */ MCD::OPC_CheckPredicate, 30, 18, 36, 0, // Skip to: 17098
+/* 7864 */ MCD::OPC_Decode, 189, 14, 252, 1, // Opcode: MIN_U_W
+/* 7869 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 7884
+/* 7874 */ MCD::OPC_CheckPredicate, 30, 3, 36, 0, // Skip to: 17098
+/* 7879 */ MCD::OPC_Decode, 187, 14, 253, 1, // Opcode: MIN_U_D
+/* 7884 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 7899
+/* 7889 */ MCD::OPC_CheckPredicate, 30, 244, 35, 0, // Skip to: 17098
+/* 7894 */ MCD::OPC_Decode, 243, 13, 250, 1, // Opcode: MAX_A_B
+/* 7899 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 7914
+/* 7904 */ MCD::OPC_CheckPredicate, 30, 229, 35, 0, // Skip to: 17098
+/* 7909 */ MCD::OPC_Decode, 245, 13, 251, 1, // Opcode: MAX_A_H
+/* 7914 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 7929
+/* 7919 */ MCD::OPC_CheckPredicate, 30, 214, 35, 0, // Skip to: 17098
+/* 7924 */ MCD::OPC_Decode, 246, 13, 252, 1, // Opcode: MAX_A_W
+/* 7929 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 7944
+/* 7934 */ MCD::OPC_CheckPredicate, 30, 199, 35, 0, // Skip to: 17098
+/* 7939 */ MCD::OPC_Decode, 244, 13, 253, 1, // Opcode: MAX_A_D
+/* 7944 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 7959
+/* 7949 */ MCD::OPC_CheckPredicate, 30, 184, 35, 0, // Skip to: 17098
+/* 7954 */ MCD::OPC_Decode, 174, 14, 250, 1, // Opcode: MIN_A_B
+/* 7959 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 7974
+/* 7964 */ MCD::OPC_CheckPredicate, 30, 169, 35, 0, // Skip to: 17098
+/* 7969 */ MCD::OPC_Decode, 176, 14, 251, 1, // Opcode: MIN_A_H
+/* 7974 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 7989
+/* 7979 */ MCD::OPC_CheckPredicate, 30, 154, 35, 0, // Skip to: 17098
+/* 7984 */ MCD::OPC_Decode, 177, 14, 252, 1, // Opcode: MIN_A_W
+/* 7989 */ MCD::OPC_FilterValue, 31, 144, 35, 0, // Skip to: 17098
+/* 7994 */ MCD::OPC_CheckPredicate, 30, 139, 35, 0, // Skip to: 17098
+/* 7999 */ MCD::OPC_Decode, 175, 14, 253, 1, // Opcode: MIN_A_D
+/* 8004 */ MCD::OPC_FilterValue, 15, 47, 1, 0, // Skip to: 8312
+/* 8009 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 8012 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8027
+/* 8017 */ MCD::OPC_CheckPredicate, 30, 116, 35, 0, // Skip to: 17098
+/* 8022 */ MCD::OPC_Decode, 226, 6, 250, 1, // Opcode: CEQ_B
+/* 8027 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8042
+/* 8032 */ MCD::OPC_CheckPredicate, 30, 101, 35, 0, // Skip to: 17098
+/* 8037 */ MCD::OPC_Decode, 228, 6, 251, 1, // Opcode: CEQ_H
+/* 8042 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8057
+/* 8047 */ MCD::OPC_CheckPredicate, 30, 86, 35, 0, // Skip to: 17098
+/* 8052 */ MCD::OPC_Decode, 229, 6, 252, 1, // Opcode: CEQ_W
+/* 8057 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8072
+/* 8062 */ MCD::OPC_CheckPredicate, 30, 71, 35, 0, // Skip to: 17098
+/* 8067 */ MCD::OPC_Decode, 227, 6, 253, 1, // Opcode: CEQ_D
+/* 8072 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8087
+/* 8077 */ MCD::OPC_CheckPredicate, 30, 56, 35, 0, // Skip to: 17098
+/* 8082 */ MCD::OPC_Decode, 142, 7, 250, 1, // Opcode: CLT_S_B
+/* 8087 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8102
+/* 8092 */ MCD::OPC_CheckPredicate, 30, 41, 35, 0, // Skip to: 17098
+/* 8097 */ MCD::OPC_Decode, 144, 7, 251, 1, // Opcode: CLT_S_H
+/* 8102 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8117
+/* 8107 */ MCD::OPC_CheckPredicate, 30, 26, 35, 0, // Skip to: 17098
+/* 8112 */ MCD::OPC_Decode, 145, 7, 252, 1, // Opcode: CLT_S_W
+/* 8117 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8132
+/* 8122 */ MCD::OPC_CheckPredicate, 30, 11, 35, 0, // Skip to: 17098
+/* 8127 */ MCD::OPC_Decode, 143, 7, 253, 1, // Opcode: CLT_S_D
+/* 8132 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 8147
+/* 8137 */ MCD::OPC_CheckPredicate, 30, 252, 34, 0, // Skip to: 17098
+/* 8142 */ MCD::OPC_Decode, 146, 7, 250, 1, // Opcode: CLT_U_B
+/* 8147 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 8162
+/* 8152 */ MCD::OPC_CheckPredicate, 30, 237, 34, 0, // Skip to: 17098
+/* 8157 */ MCD::OPC_Decode, 148, 7, 251, 1, // Opcode: CLT_U_H
+/* 8162 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 8177
+/* 8167 */ MCD::OPC_CheckPredicate, 30, 222, 34, 0, // Skip to: 17098
+/* 8172 */ MCD::OPC_Decode, 149, 7, 252, 1, // Opcode: CLT_U_W
+/* 8177 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 8192
+/* 8182 */ MCD::OPC_CheckPredicate, 30, 207, 34, 0, // Skip to: 17098
+/* 8187 */ MCD::OPC_Decode, 147, 7, 253, 1, // Opcode: CLT_U_D
+/* 8192 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 8207
+/* 8197 */ MCD::OPC_CheckPredicate, 30, 192, 34, 0, // Skip to: 17098
+/* 8202 */ MCD::OPC_Decode, 250, 6, 250, 1, // Opcode: CLE_S_B
+/* 8207 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 8222
+/* 8212 */ MCD::OPC_CheckPredicate, 30, 177, 34, 0, // Skip to: 17098
+/* 8217 */ MCD::OPC_Decode, 252, 6, 251, 1, // Opcode: CLE_S_H
+/* 8222 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 8237
+/* 8227 */ MCD::OPC_CheckPredicate, 30, 162, 34, 0, // Skip to: 17098
+/* 8232 */ MCD::OPC_Decode, 253, 6, 252, 1, // Opcode: CLE_S_W
+/* 8237 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 8252
+/* 8242 */ MCD::OPC_CheckPredicate, 30, 147, 34, 0, // Skip to: 17098
+/* 8247 */ MCD::OPC_Decode, 251, 6, 253, 1, // Opcode: CLE_S_D
+/* 8252 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 8267
+/* 8257 */ MCD::OPC_CheckPredicate, 30, 132, 34, 0, // Skip to: 17098
+/* 8262 */ MCD::OPC_Decode, 254, 6, 250, 1, // Opcode: CLE_U_B
+/* 8267 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 8282
+/* 8272 */ MCD::OPC_CheckPredicate, 30, 117, 34, 0, // Skip to: 17098
+/* 8277 */ MCD::OPC_Decode, 128, 7, 251, 1, // Opcode: CLE_U_H
+/* 8282 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 8297
+/* 8287 */ MCD::OPC_CheckPredicate, 30, 102, 34, 0, // Skip to: 17098
+/* 8292 */ MCD::OPC_Decode, 129, 7, 252, 1, // Opcode: CLE_U_W
+/* 8297 */ MCD::OPC_FilterValue, 23, 92, 34, 0, // Skip to: 17098
+/* 8302 */ MCD::OPC_CheckPredicate, 30, 87, 34, 0, // Skip to: 17098
+/* 8307 */ MCD::OPC_Decode, 255, 6, 253, 1, // Opcode: CLE_U_D
+/* 8312 */ MCD::OPC_FilterValue, 16, 227, 1, 0, // Skip to: 8800
+/* 8317 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 8320 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8335
+/* 8325 */ MCD::OPC_CheckPredicate, 30, 64, 34, 0, // Skip to: 17098
+/* 8330 */ MCD::OPC_Decode, 195, 4, 250, 1, // Opcode: ADD_A_B
+/* 8335 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8350
+/* 8340 */ MCD::OPC_CheckPredicate, 30, 49, 34, 0, // Skip to: 17098
+/* 8345 */ MCD::OPC_Decode, 197, 4, 251, 1, // Opcode: ADD_A_H
+/* 8350 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8365
+/* 8355 */ MCD::OPC_CheckPredicate, 30, 34, 34, 0, // Skip to: 17098
+/* 8360 */ MCD::OPC_Decode, 198, 4, 252, 1, // Opcode: ADD_A_W
+/* 8365 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8380
+/* 8370 */ MCD::OPC_CheckPredicate, 30, 19, 34, 0, // Skip to: 17098
+/* 8375 */ MCD::OPC_Decode, 196, 4, 253, 1, // Opcode: ADD_A_D
+/* 8380 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 8395
+/* 8385 */ MCD::OPC_CheckPredicate, 30, 4, 34, 0, // Skip to: 17098
+/* 8390 */ MCD::OPC_Decode, 158, 4, 250, 1, // Opcode: ADDS_A_B
+/* 8395 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 8410
+/* 8400 */ MCD::OPC_CheckPredicate, 30, 245, 33, 0, // Skip to: 17098
+/* 8405 */ MCD::OPC_Decode, 160, 4, 251, 1, // Opcode: ADDS_A_H
+/* 8410 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 8425
+/* 8415 */ MCD::OPC_CheckPredicate, 30, 230, 33, 0, // Skip to: 17098
+/* 8420 */ MCD::OPC_Decode, 161, 4, 252, 1, // Opcode: ADDS_A_W
+/* 8425 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 8440
+/* 8430 */ MCD::OPC_CheckPredicate, 30, 215, 33, 0, // Skip to: 17098
+/* 8435 */ MCD::OPC_Decode, 159, 4, 253, 1, // Opcode: ADDS_A_D
+/* 8440 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8455
+/* 8445 */ MCD::OPC_CheckPredicate, 30, 200, 33, 0, // Skip to: 17098
+/* 8450 */ MCD::OPC_Decode, 162, 4, 250, 1, // Opcode: ADDS_S_B
+/* 8455 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8470
+/* 8460 */ MCD::OPC_CheckPredicate, 30, 185, 33, 0, // Skip to: 17098
+/* 8465 */ MCD::OPC_Decode, 164, 4, 251, 1, // Opcode: ADDS_S_H
+/* 8470 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8485
+/* 8475 */ MCD::OPC_CheckPredicate, 30, 170, 33, 0, // Skip to: 17098
+/* 8480 */ MCD::OPC_Decode, 165, 4, 252, 1, // Opcode: ADDS_S_W
+/* 8485 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8500
+/* 8490 */ MCD::OPC_CheckPredicate, 30, 155, 33, 0, // Skip to: 17098
+/* 8495 */ MCD::OPC_Decode, 163, 4, 253, 1, // Opcode: ADDS_S_D
+/* 8500 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 8515
+/* 8505 */ MCD::OPC_CheckPredicate, 30, 140, 33, 0, // Skip to: 17098
+/* 8510 */ MCD::OPC_Decode, 166, 4, 250, 1, // Opcode: ADDS_U_B
+/* 8515 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 8530
+/* 8520 */ MCD::OPC_CheckPredicate, 30, 125, 33, 0, // Skip to: 17098
+/* 8525 */ MCD::OPC_Decode, 168, 4, 251, 1, // Opcode: ADDS_U_H
+/* 8530 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 8545
+/* 8535 */ MCD::OPC_CheckPredicate, 30, 110, 33, 0, // Skip to: 17098
+/* 8540 */ MCD::OPC_Decode, 169, 4, 252, 1, // Opcode: ADDS_U_W
+/* 8545 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 8560
+/* 8550 */ MCD::OPC_CheckPredicate, 30, 95, 33, 0, // Skip to: 17098
+/* 8555 */ MCD::OPC_Decode, 167, 4, 253, 1, // Opcode: ADDS_U_D
+/* 8560 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 8575
+/* 8565 */ MCD::OPC_CheckPredicate, 30, 80, 33, 0, // Skip to: 17098
+/* 8570 */ MCD::OPC_Decode, 247, 4, 250, 1, // Opcode: AVE_S_B
+/* 8575 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 8590
+/* 8580 */ MCD::OPC_CheckPredicate, 30, 65, 33, 0, // Skip to: 17098
+/* 8585 */ MCD::OPC_Decode, 249, 4, 251, 1, // Opcode: AVE_S_H
+/* 8590 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 8605
+/* 8595 */ MCD::OPC_CheckPredicate, 30, 50, 33, 0, // Skip to: 17098
+/* 8600 */ MCD::OPC_Decode, 250, 4, 252, 1, // Opcode: AVE_S_W
+/* 8605 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 8620
+/* 8610 */ MCD::OPC_CheckPredicate, 30, 35, 33, 0, // Skip to: 17098
+/* 8615 */ MCD::OPC_Decode, 248, 4, 253, 1, // Opcode: AVE_S_D
+/* 8620 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 8635
+/* 8625 */ MCD::OPC_CheckPredicate, 30, 20, 33, 0, // Skip to: 17098
+/* 8630 */ MCD::OPC_Decode, 251, 4, 250, 1, // Opcode: AVE_U_B
+/* 8635 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 8650
+/* 8640 */ MCD::OPC_CheckPredicate, 30, 5, 33, 0, // Skip to: 17098
+/* 8645 */ MCD::OPC_Decode, 253, 4, 251, 1, // Opcode: AVE_U_H
+/* 8650 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 8665
+/* 8655 */ MCD::OPC_CheckPredicate, 30, 246, 32, 0, // Skip to: 17098
+/* 8660 */ MCD::OPC_Decode, 254, 4, 252, 1, // Opcode: AVE_U_W
+/* 8665 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 8680
+/* 8670 */ MCD::OPC_CheckPredicate, 30, 231, 32, 0, // Skip to: 17098
+/* 8675 */ MCD::OPC_Decode, 252, 4, 253, 1, // Opcode: AVE_U_D
+/* 8680 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 8695
+/* 8685 */ MCD::OPC_CheckPredicate, 30, 216, 32, 0, // Skip to: 17098
+/* 8690 */ MCD::OPC_Decode, 239, 4, 250, 1, // Opcode: AVER_S_B
+/* 8695 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 8710
+/* 8700 */ MCD::OPC_CheckPredicate, 30, 201, 32, 0, // Skip to: 17098
+/* 8705 */ MCD::OPC_Decode, 241, 4, 251, 1, // Opcode: AVER_S_H
+/* 8710 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 8725
+/* 8715 */ MCD::OPC_CheckPredicate, 30, 186, 32, 0, // Skip to: 17098
+/* 8720 */ MCD::OPC_Decode, 242, 4, 252, 1, // Opcode: AVER_S_W
+/* 8725 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 8740
+/* 8730 */ MCD::OPC_CheckPredicate, 30, 171, 32, 0, // Skip to: 17098
+/* 8735 */ MCD::OPC_Decode, 240, 4, 253, 1, // Opcode: AVER_S_D
+/* 8740 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 8755
+/* 8745 */ MCD::OPC_CheckPredicate, 30, 156, 32, 0, // Skip to: 17098
+/* 8750 */ MCD::OPC_Decode, 243, 4, 250, 1, // Opcode: AVER_U_B
+/* 8755 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 8770
+/* 8760 */ MCD::OPC_CheckPredicate, 30, 141, 32, 0, // Skip to: 17098
+/* 8765 */ MCD::OPC_Decode, 245, 4, 251, 1, // Opcode: AVER_U_H
+/* 8770 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 8785
+/* 8775 */ MCD::OPC_CheckPredicate, 30, 126, 32, 0, // Skip to: 17098
+/* 8780 */ MCD::OPC_Decode, 246, 4, 252, 1, // Opcode: AVER_U_W
+/* 8785 */ MCD::OPC_FilterValue, 31, 116, 32, 0, // Skip to: 17098
+/* 8790 */ MCD::OPC_CheckPredicate, 30, 111, 32, 0, // Skip to: 17098
+/* 8795 */ MCD::OPC_Decode, 244, 4, 253, 1, // Opcode: AVER_U_D
+/* 8800 */ MCD::OPC_FilterValue, 17, 107, 1, 0, // Skip to: 9168
+/* 8805 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 8808 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8823
+/* 8813 */ MCD::OPC_CheckPredicate, 30, 88, 32, 0, // Skip to: 17098
+/* 8818 */ MCD::OPC_Decode, 132, 19, 250, 1, // Opcode: SUBS_S_B
+/* 8823 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8838
+/* 8828 */ MCD::OPC_CheckPredicate, 30, 73, 32, 0, // Skip to: 17098
+/* 8833 */ MCD::OPC_Decode, 134, 19, 251, 1, // Opcode: SUBS_S_H
+/* 8838 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8853
+/* 8843 */ MCD::OPC_CheckPredicate, 30, 58, 32, 0, // Skip to: 17098
+/* 8848 */ MCD::OPC_Decode, 135, 19, 252, 1, // Opcode: SUBS_S_W
+/* 8853 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 8868
+/* 8858 */ MCD::OPC_CheckPredicate, 30, 43, 32, 0, // Skip to: 17098
+/* 8863 */ MCD::OPC_Decode, 133, 19, 253, 1, // Opcode: SUBS_S_D
+/* 8868 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 8883
+/* 8873 */ MCD::OPC_CheckPredicate, 30, 28, 32, 0, // Skip to: 17098
+/* 8878 */ MCD::OPC_Decode, 136, 19, 250, 1, // Opcode: SUBS_U_B
+/* 8883 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 8898
+/* 8888 */ MCD::OPC_CheckPredicate, 30, 13, 32, 0, // Skip to: 17098
+/* 8893 */ MCD::OPC_Decode, 138, 19, 251, 1, // Opcode: SUBS_U_H
+/* 8898 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 8913
+/* 8903 */ MCD::OPC_CheckPredicate, 30, 254, 31, 0, // Skip to: 17098
+/* 8908 */ MCD::OPC_Decode, 139, 19, 252, 1, // Opcode: SUBS_U_W
+/* 8913 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 8928
+/* 8918 */ MCD::OPC_CheckPredicate, 30, 239, 31, 0, // Skip to: 17098
+/* 8923 */ MCD::OPC_Decode, 137, 19, 253, 1, // Opcode: SUBS_U_D
+/* 8928 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 8943
+/* 8933 */ MCD::OPC_CheckPredicate, 30, 224, 31, 0, // Skip to: 17098
+/* 8938 */ MCD::OPC_Decode, 252, 18, 250, 1, // Opcode: SUBSUS_U_B
+/* 8943 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 8958
+/* 8948 */ MCD::OPC_CheckPredicate, 30, 209, 31, 0, // Skip to: 17098
+/* 8953 */ MCD::OPC_Decode, 254, 18, 251, 1, // Opcode: SUBSUS_U_H
+/* 8958 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 8973
+/* 8963 */ MCD::OPC_CheckPredicate, 30, 194, 31, 0, // Skip to: 17098
+/* 8968 */ MCD::OPC_Decode, 255, 18, 252, 1, // Opcode: SUBSUS_U_W
+/* 8973 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 8988
+/* 8978 */ MCD::OPC_CheckPredicate, 30, 179, 31, 0, // Skip to: 17098
+/* 8983 */ MCD::OPC_Decode, 253, 18, 253, 1, // Opcode: SUBSUS_U_D
+/* 8988 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 9003
+/* 8993 */ MCD::OPC_CheckPredicate, 30, 164, 31, 0, // Skip to: 17098
+/* 8998 */ MCD::OPC_Decode, 128, 19, 250, 1, // Opcode: SUBSUU_S_B
+/* 9003 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9018
+/* 9008 */ MCD::OPC_CheckPredicate, 30, 149, 31, 0, // Skip to: 17098
+/* 9013 */ MCD::OPC_Decode, 130, 19, 251, 1, // Opcode: SUBSUU_S_H
+/* 9018 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9033
+/* 9023 */ MCD::OPC_CheckPredicate, 30, 134, 31, 0, // Skip to: 17098
+/* 9028 */ MCD::OPC_Decode, 131, 19, 252, 1, // Opcode: SUBSUU_S_W
+/* 9033 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 9048
+/* 9038 */ MCD::OPC_CheckPredicate, 30, 119, 31, 0, // Skip to: 17098
+/* 9043 */ MCD::OPC_Decode, 129, 19, 253, 1, // Opcode: SUBSUU_S_D
+/* 9048 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 9063
+/* 9053 */ MCD::OPC_CheckPredicate, 30, 104, 31, 0, // Skip to: 17098
+/* 9058 */ MCD::OPC_Decode, 227, 4, 250, 1, // Opcode: ASUB_S_B
+/* 9063 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9078
+/* 9068 */ MCD::OPC_CheckPredicate, 30, 89, 31, 0, // Skip to: 17098
+/* 9073 */ MCD::OPC_Decode, 229, 4, 251, 1, // Opcode: ASUB_S_H
+/* 9078 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9093
+/* 9083 */ MCD::OPC_CheckPredicate, 30, 74, 31, 0, // Skip to: 17098
+/* 9088 */ MCD::OPC_Decode, 230, 4, 252, 1, // Opcode: ASUB_S_W
+/* 9093 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9108
+/* 9098 */ MCD::OPC_CheckPredicate, 30, 59, 31, 0, // Skip to: 17098
+/* 9103 */ MCD::OPC_Decode, 228, 4, 253, 1, // Opcode: ASUB_S_D
+/* 9108 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 9123
+/* 9113 */ MCD::OPC_CheckPredicate, 30, 44, 31, 0, // Skip to: 17098
+/* 9118 */ MCD::OPC_Decode, 231, 4, 250, 1, // Opcode: ASUB_U_B
+/* 9123 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9138
+/* 9128 */ MCD::OPC_CheckPredicate, 30, 29, 31, 0, // Skip to: 17098
+/* 9133 */ MCD::OPC_Decode, 233, 4, 251, 1, // Opcode: ASUB_U_H
+/* 9138 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9153
+/* 9143 */ MCD::OPC_CheckPredicate, 30, 14, 31, 0, // Skip to: 17098
+/* 9148 */ MCD::OPC_Decode, 234, 4, 252, 1, // Opcode: ASUB_U_W
+/* 9153 */ MCD::OPC_FilterValue, 23, 4, 31, 0, // Skip to: 17098
+/* 9158 */ MCD::OPC_CheckPredicate, 30, 255, 30, 0, // Skip to: 17098
+/* 9163 */ MCD::OPC_Decode, 232, 4, 253, 1, // Opcode: ASUB_U_D
+/* 9168 */ MCD::OPC_FilterValue, 18, 167, 1, 0, // Skip to: 9596
+/* 9173 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 9176 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9191
+/* 9181 */ MCD::OPC_CheckPredicate, 30, 232, 30, 0, // Skip to: 17098
+/* 9186 */ MCD::OPC_Decode, 220, 15, 250, 1, // Opcode: MULV_B
+/* 9191 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9206
+/* 9196 */ MCD::OPC_CheckPredicate, 30, 217, 30, 0, // Skip to: 17098
+/* 9201 */ MCD::OPC_Decode, 222, 15, 251, 1, // Opcode: MULV_H
+/* 9206 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9221
+/* 9211 */ MCD::OPC_CheckPredicate, 30, 202, 30, 0, // Skip to: 17098
+/* 9216 */ MCD::OPC_Decode, 223, 15, 252, 1, // Opcode: MULV_W
+/* 9221 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9236
+/* 9226 */ MCD::OPC_CheckPredicate, 30, 187, 30, 0, // Skip to: 17098
+/* 9231 */ MCD::OPC_Decode, 221, 15, 253, 1, // Opcode: MULV_D
+/* 9236 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9251
+/* 9241 */ MCD::OPC_CheckPredicate, 30, 172, 30, 0, // Skip to: 17098
+/* 9246 */ MCD::OPC_Decode, 209, 13, 254, 1, // Opcode: MADDV_B
+/* 9251 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9266
+/* 9256 */ MCD::OPC_CheckPredicate, 30, 157, 30, 0, // Skip to: 17098
+/* 9261 */ MCD::OPC_Decode, 211, 13, 255, 1, // Opcode: MADDV_H
+/* 9266 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9281
+/* 9271 */ MCD::OPC_CheckPredicate, 30, 142, 30, 0, // Skip to: 17098
+/* 9276 */ MCD::OPC_Decode, 212, 13, 128, 2, // Opcode: MADDV_W
+/* 9281 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9296
+/* 9286 */ MCD::OPC_CheckPredicate, 30, 127, 30, 0, // Skip to: 17098
+/* 9291 */ MCD::OPC_Decode, 210, 13, 129, 2, // Opcode: MADDV_D
+/* 9296 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 9311
+/* 9301 */ MCD::OPC_CheckPredicate, 30, 112, 30, 0, // Skip to: 17098
+/* 9306 */ MCD::OPC_Decode, 132, 15, 254, 1, // Opcode: MSUBV_B
+/* 9311 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9326
+/* 9316 */ MCD::OPC_CheckPredicate, 30, 97, 30, 0, // Skip to: 17098
+/* 9321 */ MCD::OPC_Decode, 134, 15, 255, 1, // Opcode: MSUBV_H
+/* 9326 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9341
+/* 9331 */ MCD::OPC_CheckPredicate, 30, 82, 30, 0, // Skip to: 17098
+/* 9336 */ MCD::OPC_Decode, 135, 15, 128, 2, // Opcode: MSUBV_W
+/* 9341 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9356
+/* 9346 */ MCD::OPC_CheckPredicate, 30, 67, 30, 0, // Skip to: 17098
+/* 9351 */ MCD::OPC_Decode, 133, 15, 129, 2, // Opcode: MSUBV_D
+/* 9356 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 9371
+/* 9361 */ MCD::OPC_CheckPredicate, 30, 52, 30, 0, // Skip to: 17098
+/* 9366 */ MCD::OPC_Decode, 166, 9, 250, 1, // Opcode: DIV_S_B
+/* 9371 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9386
+/* 9376 */ MCD::OPC_CheckPredicate, 30, 37, 30, 0, // Skip to: 17098
+/* 9381 */ MCD::OPC_Decode, 168, 9, 251, 1, // Opcode: DIV_S_H
+/* 9386 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9401
+/* 9391 */ MCD::OPC_CheckPredicate, 30, 22, 30, 0, // Skip to: 17098
+/* 9396 */ MCD::OPC_Decode, 169, 9, 252, 1, // Opcode: DIV_S_W
+/* 9401 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9416
+/* 9406 */ MCD::OPC_CheckPredicate, 30, 7, 30, 0, // Skip to: 17098
+/* 9411 */ MCD::OPC_Decode, 167, 9, 253, 1, // Opcode: DIV_S_D
+/* 9416 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 9431
+/* 9421 */ MCD::OPC_CheckPredicate, 30, 248, 29, 0, // Skip to: 17098
+/* 9426 */ MCD::OPC_Decode, 170, 9, 250, 1, // Opcode: DIV_U_B
+/* 9431 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9446
+/* 9436 */ MCD::OPC_CheckPredicate, 30, 233, 29, 0, // Skip to: 17098
+/* 9441 */ MCD::OPC_Decode, 172, 9, 251, 1, // Opcode: DIV_U_H
+/* 9446 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9461
+/* 9451 */ MCD::OPC_CheckPredicate, 30, 218, 29, 0, // Skip to: 17098
+/* 9456 */ MCD::OPC_Decode, 173, 9, 252, 1, // Opcode: DIV_U_W
+/* 9461 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 9476
+/* 9466 */ MCD::OPC_CheckPredicate, 30, 203, 29, 0, // Skip to: 17098
+/* 9471 */ MCD::OPC_Decode, 171, 9, 253, 1, // Opcode: DIV_U_D
+/* 9476 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 9491
+/* 9481 */ MCD::OPC_CheckPredicate, 30, 188, 29, 0, // Skip to: 17098
+/* 9486 */ MCD::OPC_Decode, 196, 14, 250, 1, // Opcode: MOD_S_B
+/* 9491 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 9506
+/* 9496 */ MCD::OPC_CheckPredicate, 30, 173, 29, 0, // Skip to: 17098
+/* 9501 */ MCD::OPC_Decode, 198, 14, 251, 1, // Opcode: MOD_S_H
+/* 9506 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 9521
+/* 9511 */ MCD::OPC_CheckPredicate, 30, 158, 29, 0, // Skip to: 17098
+/* 9516 */ MCD::OPC_Decode, 199, 14, 252, 1, // Opcode: MOD_S_W
+/* 9521 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 9536
+/* 9526 */ MCD::OPC_CheckPredicate, 30, 143, 29, 0, // Skip to: 17098
+/* 9531 */ MCD::OPC_Decode, 197, 14, 253, 1, // Opcode: MOD_S_D
+/* 9536 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 9551
+/* 9541 */ MCD::OPC_CheckPredicate, 30, 128, 29, 0, // Skip to: 17098
+/* 9546 */ MCD::OPC_Decode, 200, 14, 250, 1, // Opcode: MOD_U_B
+/* 9551 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 9566
+/* 9556 */ MCD::OPC_CheckPredicate, 30, 113, 29, 0, // Skip to: 17098
+/* 9561 */ MCD::OPC_Decode, 202, 14, 251, 1, // Opcode: MOD_U_H
+/* 9566 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 9581
+/* 9571 */ MCD::OPC_CheckPredicate, 30, 98, 29, 0, // Skip to: 17098
+/* 9576 */ MCD::OPC_Decode, 203, 14, 252, 1, // Opcode: MOD_U_W
+/* 9581 */ MCD::OPC_FilterValue, 31, 88, 29, 0, // Skip to: 17098
+/* 9586 */ MCD::OPC_CheckPredicate, 30, 83, 29, 0, // Skip to: 17098
+/* 9591 */ MCD::OPC_Decode, 201, 14, 253, 1, // Opcode: MOD_U_D
+/* 9596 */ MCD::OPC_FilterValue, 19, 17, 1, 0, // Skip to: 9874
+/* 9601 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 9604 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9619
+/* 9609 */ MCD::OPC_CheckPredicate, 30, 60, 29, 0, // Skip to: 17098
+/* 9614 */ MCD::OPC_Decode, 199, 9, 130, 2, // Opcode: DOTP_S_H
+/* 9619 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9634
+/* 9624 */ MCD::OPC_CheckPredicate, 30, 45, 29, 0, // Skip to: 17098
+/* 9629 */ MCD::OPC_Decode, 200, 9, 131, 2, // Opcode: DOTP_S_W
+/* 9634 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9649
+/* 9639 */ MCD::OPC_CheckPredicate, 30, 30, 29, 0, // Skip to: 17098
+/* 9644 */ MCD::OPC_Decode, 198, 9, 132, 2, // Opcode: DOTP_S_D
+/* 9649 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9664
+/* 9654 */ MCD::OPC_CheckPredicate, 30, 15, 29, 0, // Skip to: 17098
+/* 9659 */ MCD::OPC_Decode, 202, 9, 130, 2, // Opcode: DOTP_U_H
+/* 9664 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9679
+/* 9669 */ MCD::OPC_CheckPredicate, 30, 0, 29, 0, // Skip to: 17098
+/* 9674 */ MCD::OPC_Decode, 203, 9, 131, 2, // Opcode: DOTP_U_W
+/* 9679 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 9694
+/* 9684 */ MCD::OPC_CheckPredicate, 30, 241, 28, 0, // Skip to: 17098
+/* 9689 */ MCD::OPC_Decode, 201, 9, 132, 2, // Opcode: DOTP_U_D
+/* 9694 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 9709
+/* 9699 */ MCD::OPC_CheckPredicate, 30, 226, 28, 0, // Skip to: 17098
+/* 9704 */ MCD::OPC_Decode, 205, 9, 133, 2, // Opcode: DPADD_S_H
+/* 9709 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 9724
+/* 9714 */ MCD::OPC_CheckPredicate, 30, 211, 28, 0, // Skip to: 17098
+/* 9719 */ MCD::OPC_Decode, 206, 9, 134, 2, // Opcode: DPADD_S_W
+/* 9724 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 9739
+/* 9729 */ MCD::OPC_CheckPredicate, 30, 196, 28, 0, // Skip to: 17098
+/* 9734 */ MCD::OPC_Decode, 204, 9, 135, 2, // Opcode: DPADD_S_D
+/* 9739 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 9754
+/* 9744 */ MCD::OPC_CheckPredicate, 30, 181, 28, 0, // Skip to: 17098
+/* 9749 */ MCD::OPC_Decode, 208, 9, 133, 2, // Opcode: DPADD_U_H
+/* 9754 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9769
+/* 9759 */ MCD::OPC_CheckPredicate, 30, 166, 28, 0, // Skip to: 17098
+/* 9764 */ MCD::OPC_Decode, 209, 9, 134, 2, // Opcode: DPADD_U_W
+/* 9769 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 9784
+/* 9774 */ MCD::OPC_CheckPredicate, 30, 151, 28, 0, // Skip to: 17098
+/* 9779 */ MCD::OPC_Decode, 207, 9, 135, 2, // Opcode: DPADD_U_D
+/* 9784 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 9799
+/* 9789 */ MCD::OPC_CheckPredicate, 30, 136, 28, 0, // Skip to: 17098
+/* 9794 */ MCD::OPC_Decode, 236, 9, 133, 2, // Opcode: DPSUB_S_H
+/* 9799 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 9814
+/* 9804 */ MCD::OPC_CheckPredicate, 30, 121, 28, 0, // Skip to: 17098
+/* 9809 */ MCD::OPC_Decode, 237, 9, 134, 2, // Opcode: DPSUB_S_W
+/* 9814 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 9829
+/* 9819 */ MCD::OPC_CheckPredicate, 30, 106, 28, 0, // Skip to: 17098
+/* 9824 */ MCD::OPC_Decode, 235, 9, 135, 2, // Opcode: DPSUB_S_D
+/* 9829 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 9844
+/* 9834 */ MCD::OPC_CheckPredicate, 30, 91, 28, 0, // Skip to: 17098
+/* 9839 */ MCD::OPC_Decode, 239, 9, 133, 2, // Opcode: DPSUB_U_H
+/* 9844 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 9859
+/* 9849 */ MCD::OPC_CheckPredicate, 30, 76, 28, 0, // Skip to: 17098
+/* 9854 */ MCD::OPC_Decode, 240, 9, 134, 2, // Opcode: DPSUB_U_W
+/* 9859 */ MCD::OPC_FilterValue, 23, 66, 28, 0, // Skip to: 17098
+/* 9864 */ MCD::OPC_CheckPredicate, 30, 61, 28, 0, // Skip to: 17098
+/* 9869 */ MCD::OPC_Decode, 238, 9, 135, 2, // Opcode: DPSUB_U_D
+/* 9874 */ MCD::OPC_FilterValue, 20, 227, 1, 0, // Skip to: 10362
+/* 9879 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 9882 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9897
+/* 9887 */ MCD::OPC_CheckPredicate, 30, 38, 28, 0, // Skip to: 17098
+/* 9892 */ MCD::OPC_Decode, 145, 18, 136, 2, // Opcode: SLD_B
+/* 9897 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9912
+/* 9902 */ MCD::OPC_CheckPredicate, 30, 23, 28, 0, // Skip to: 17098
+/* 9907 */ MCD::OPC_Decode, 147, 18, 137, 2, // Opcode: SLD_H
+/* 9912 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9927
+/* 9917 */ MCD::OPC_CheckPredicate, 30, 8, 28, 0, // Skip to: 17098
+/* 9922 */ MCD::OPC_Decode, 148, 18, 138, 2, // Opcode: SLD_W
+/* 9927 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 9942
+/* 9932 */ MCD::OPC_CheckPredicate, 30, 249, 27, 0, // Skip to: 17098
+/* 9937 */ MCD::OPC_Decode, 146, 18, 139, 2, // Opcode: SLD_D
+/* 9942 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 9957
+/* 9947 */ MCD::OPC_CheckPredicate, 30, 234, 27, 0, // Skip to: 17098
+/* 9952 */ MCD::OPC_Decode, 184, 18, 140, 2, // Opcode: SPLAT_B
+/* 9957 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 9972
+/* 9962 */ MCD::OPC_CheckPredicate, 30, 219, 27, 0, // Skip to: 17098
+/* 9967 */ MCD::OPC_Decode, 186, 18, 141, 2, // Opcode: SPLAT_H
+/* 9972 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 9987
+/* 9977 */ MCD::OPC_CheckPredicate, 30, 204, 27, 0, // Skip to: 17098
+/* 9982 */ MCD::OPC_Decode, 187, 18, 142, 2, // Opcode: SPLAT_W
+/* 9987 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 10002
+/* 9992 */ MCD::OPC_CheckPredicate, 30, 189, 27, 0, // Skip to: 17098
+/* 9997 */ MCD::OPC_Decode, 185, 18, 143, 2, // Opcode: SPLAT_D
+/* 10002 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10017
+/* 10007 */ MCD::OPC_CheckPredicate, 30, 174, 27, 0, // Skip to: 17098
+/* 10012 */ MCD::OPC_Decode, 155, 16, 250, 1, // Opcode: PCKEV_B
+/* 10017 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 10032
+/* 10022 */ MCD::OPC_CheckPredicate, 30, 159, 27, 0, // Skip to: 17098
+/* 10027 */ MCD::OPC_Decode, 157, 16, 251, 1, // Opcode: PCKEV_H
+/* 10032 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 10047
+/* 10037 */ MCD::OPC_CheckPredicate, 30, 144, 27, 0, // Skip to: 17098
+/* 10042 */ MCD::OPC_Decode, 158, 16, 252, 1, // Opcode: PCKEV_W
+/* 10047 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 10062
+/* 10052 */ MCD::OPC_CheckPredicate, 30, 129, 27, 0, // Skip to: 17098
+/* 10057 */ MCD::OPC_Decode, 156, 16, 253, 1, // Opcode: PCKEV_D
+/* 10062 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 10077
+/* 10067 */ MCD::OPC_CheckPredicate, 30, 114, 27, 0, // Skip to: 17098
+/* 10072 */ MCD::OPC_Decode, 159, 16, 250, 1, // Opcode: PCKOD_B
+/* 10077 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 10092
+/* 10082 */ MCD::OPC_CheckPredicate, 30, 99, 27, 0, // Skip to: 17098
+/* 10087 */ MCD::OPC_Decode, 161, 16, 251, 1, // Opcode: PCKOD_H
+/* 10092 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10107
+/* 10097 */ MCD::OPC_CheckPredicate, 30, 84, 27, 0, // Skip to: 17098
+/* 10102 */ MCD::OPC_Decode, 162, 16, 252, 1, // Opcode: PCKOD_W
+/* 10107 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 10122
+/* 10112 */ MCD::OPC_CheckPredicate, 30, 69, 27, 0, // Skip to: 17098
+/* 10117 */ MCD::OPC_Decode, 160, 16, 253, 1, // Opcode: PCKOD_D
+/* 10122 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 10137
+/* 10127 */ MCD::OPC_CheckPredicate, 30, 54, 27, 0, // Skip to: 17098
+/* 10132 */ MCD::OPC_Decode, 132, 12, 250, 1, // Opcode: ILVL_B
+/* 10137 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 10152
+/* 10142 */ MCD::OPC_CheckPredicate, 30, 39, 27, 0, // Skip to: 17098
+/* 10147 */ MCD::OPC_Decode, 134, 12, 251, 1, // Opcode: ILVL_H
+/* 10152 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 10167
+/* 10157 */ MCD::OPC_CheckPredicate, 30, 24, 27, 0, // Skip to: 17098
+/* 10162 */ MCD::OPC_Decode, 135, 12, 252, 1, // Opcode: ILVL_W
+/* 10167 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 10182
+/* 10172 */ MCD::OPC_CheckPredicate, 30, 9, 27, 0, // Skip to: 17098
+/* 10177 */ MCD::OPC_Decode, 133, 12, 253, 1, // Opcode: ILVL_D
+/* 10182 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 10197
+/* 10187 */ MCD::OPC_CheckPredicate, 30, 250, 26, 0, // Skip to: 17098
+/* 10192 */ MCD::OPC_Decode, 140, 12, 250, 1, // Opcode: ILVR_B
+/* 10197 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 10212
+/* 10202 */ MCD::OPC_CheckPredicate, 30, 235, 26, 0, // Skip to: 17098
+/* 10207 */ MCD::OPC_Decode, 142, 12, 251, 1, // Opcode: ILVR_H
+/* 10212 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 10227
+/* 10217 */ MCD::OPC_CheckPredicate, 30, 220, 26, 0, // Skip to: 17098
+/* 10222 */ MCD::OPC_Decode, 143, 12, 252, 1, // Opcode: ILVR_W
+/* 10227 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 10242
+/* 10232 */ MCD::OPC_CheckPredicate, 30, 205, 26, 0, // Skip to: 17098
+/* 10237 */ MCD::OPC_Decode, 141, 12, 253, 1, // Opcode: ILVR_D
+/* 10242 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 10257
+/* 10247 */ MCD::OPC_CheckPredicate, 30, 190, 26, 0, // Skip to: 17098
+/* 10252 */ MCD::OPC_Decode, 128, 12, 250, 1, // Opcode: ILVEV_B
+/* 10257 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 10272
+/* 10262 */ MCD::OPC_CheckPredicate, 30, 175, 26, 0, // Skip to: 17098
+/* 10267 */ MCD::OPC_Decode, 130, 12, 251, 1, // Opcode: ILVEV_H
+/* 10272 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 10287
+/* 10277 */ MCD::OPC_CheckPredicate, 30, 160, 26, 0, // Skip to: 17098
+/* 10282 */ MCD::OPC_Decode, 131, 12, 252, 1, // Opcode: ILVEV_W
+/* 10287 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 10302
+/* 10292 */ MCD::OPC_CheckPredicate, 30, 145, 26, 0, // Skip to: 17098
+/* 10297 */ MCD::OPC_Decode, 129, 12, 253, 1, // Opcode: ILVEV_D
+/* 10302 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 10317
+/* 10307 */ MCD::OPC_CheckPredicate, 30, 130, 26, 0, // Skip to: 17098
+/* 10312 */ MCD::OPC_Decode, 136, 12, 250, 1, // Opcode: ILVOD_B
+/* 10317 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 10332
+/* 10322 */ MCD::OPC_CheckPredicate, 30, 115, 26, 0, // Skip to: 17098
+/* 10327 */ MCD::OPC_Decode, 138, 12, 251, 1, // Opcode: ILVOD_H
+/* 10332 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 10347
+/* 10337 */ MCD::OPC_CheckPredicate, 30, 100, 26, 0, // Skip to: 17098
+/* 10342 */ MCD::OPC_Decode, 139, 12, 252, 1, // Opcode: ILVOD_W
+/* 10347 */ MCD::OPC_FilterValue, 31, 90, 26, 0, // Skip to: 17098
+/* 10352 */ MCD::OPC_CheckPredicate, 30, 85, 26, 0, // Skip to: 17098
+/* 10357 */ MCD::OPC_Decode, 137, 12, 253, 1, // Opcode: ILVOD_D
+/* 10362 */ MCD::OPC_FilterValue, 21, 107, 1, 0, // Skip to: 10730
+/* 10367 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 10370 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10385
+/* 10375 */ MCD::OPC_CheckPredicate, 30, 62, 26, 0, // Skip to: 17098
+/* 10380 */ MCD::OPC_Decode, 169, 20, 254, 1, // Opcode: VSHF_B
+/* 10385 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10400
+/* 10390 */ MCD::OPC_CheckPredicate, 30, 47, 26, 0, // Skip to: 17098
+/* 10395 */ MCD::OPC_Decode, 171, 20, 255, 1, // Opcode: VSHF_H
+/* 10400 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10415
+/* 10405 */ MCD::OPC_CheckPredicate, 30, 32, 26, 0, // Skip to: 17098
+/* 10410 */ MCD::OPC_Decode, 172, 20, 128, 2, // Opcode: VSHF_W
+/* 10415 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 10430
+/* 10420 */ MCD::OPC_CheckPredicate, 30, 17, 26, 0, // Skip to: 17098
+/* 10425 */ MCD::OPC_Decode, 170, 20, 129, 2, // Opcode: VSHF_D
+/* 10430 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 10445
+/* 10435 */ MCD::OPC_CheckPredicate, 30, 2, 26, 0, // Skip to: 17098
+/* 10440 */ MCD::OPC_Decode, 197, 18, 250, 1, // Opcode: SRAR_B
+/* 10445 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 10460
+/* 10450 */ MCD::OPC_CheckPredicate, 30, 243, 25, 0, // Skip to: 17098
+/* 10455 */ MCD::OPC_Decode, 199, 18, 251, 1, // Opcode: SRAR_H
+/* 10460 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 10475
+/* 10465 */ MCD::OPC_CheckPredicate, 30, 228, 25, 0, // Skip to: 17098
+/* 10470 */ MCD::OPC_Decode, 200, 18, 252, 1, // Opcode: SRAR_W
+/* 10475 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 10490
+/* 10480 */ MCD::OPC_CheckPredicate, 30, 213, 25, 0, // Skip to: 17098
+/* 10485 */ MCD::OPC_Decode, 198, 18, 253, 1, // Opcode: SRAR_D
+/* 10490 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10505
+/* 10495 */ MCD::OPC_CheckPredicate, 30, 198, 25, 0, // Skip to: 17098
+/* 10500 */ MCD::OPC_Decode, 219, 18, 250, 1, // Opcode: SRLR_B
+/* 10505 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 10520
+/* 10510 */ MCD::OPC_CheckPredicate, 30, 183, 25, 0, // Skip to: 17098
+/* 10515 */ MCD::OPC_Decode, 221, 18, 251, 1, // Opcode: SRLR_H
+/* 10520 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 10535
+/* 10525 */ MCD::OPC_CheckPredicate, 30, 168, 25, 0, // Skip to: 17098
+/* 10530 */ MCD::OPC_Decode, 222, 18, 252, 1, // Opcode: SRLR_W
+/* 10535 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 10550
+/* 10540 */ MCD::OPC_CheckPredicate, 30, 153, 25, 0, // Skip to: 17098
+/* 10545 */ MCD::OPC_Decode, 220, 18, 253, 1, // Opcode: SRLR_D
+/* 10550 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 10565
+/* 10555 */ MCD::OPC_CheckPredicate, 30, 138, 25, 0, // Skip to: 17098
+/* 10560 */ MCD::OPC_Decode, 243, 11, 130, 2, // Opcode: HADD_S_H
+/* 10565 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 10580
+/* 10570 */ MCD::OPC_CheckPredicate, 30, 123, 25, 0, // Skip to: 17098
+/* 10575 */ MCD::OPC_Decode, 244, 11, 131, 2, // Opcode: HADD_S_W
+/* 10580 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 10595
+/* 10585 */ MCD::OPC_CheckPredicate, 30, 108, 25, 0, // Skip to: 17098
+/* 10590 */ MCD::OPC_Decode, 242, 11, 132, 2, // Opcode: HADD_S_D
+/* 10595 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 10610
+/* 10600 */ MCD::OPC_CheckPredicate, 30, 93, 25, 0, // Skip to: 17098
+/* 10605 */ MCD::OPC_Decode, 246, 11, 130, 2, // Opcode: HADD_U_H
+/* 10610 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 10625
+/* 10615 */ MCD::OPC_CheckPredicate, 30, 78, 25, 0, // Skip to: 17098
+/* 10620 */ MCD::OPC_Decode, 247, 11, 131, 2, // Opcode: HADD_U_W
+/* 10625 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 10640
+/* 10630 */ MCD::OPC_CheckPredicate, 30, 63, 25, 0, // Skip to: 17098
+/* 10635 */ MCD::OPC_Decode, 245, 11, 132, 2, // Opcode: HADD_U_D
+/* 10640 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 10655
+/* 10645 */ MCD::OPC_CheckPredicate, 30, 48, 25, 0, // Skip to: 17098
+/* 10650 */ MCD::OPC_Decode, 249, 11, 130, 2, // Opcode: HSUB_S_H
+/* 10655 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 10670
+/* 10660 */ MCD::OPC_CheckPredicate, 30, 33, 25, 0, // Skip to: 17098
+/* 10665 */ MCD::OPC_Decode, 250, 11, 131, 2, // Opcode: HSUB_S_W
+/* 10670 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 10685
+/* 10675 */ MCD::OPC_CheckPredicate, 30, 18, 25, 0, // Skip to: 17098
+/* 10680 */ MCD::OPC_Decode, 248, 11, 132, 2, // Opcode: HSUB_S_D
+/* 10685 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 10700
+/* 10690 */ MCD::OPC_CheckPredicate, 30, 3, 25, 0, // Skip to: 17098
+/* 10695 */ MCD::OPC_Decode, 252, 11, 130, 2, // Opcode: HSUB_U_H
+/* 10700 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 10715
+/* 10705 */ MCD::OPC_CheckPredicate, 30, 244, 24, 0, // Skip to: 17098
+/* 10710 */ MCD::OPC_Decode, 253, 11, 131, 2, // Opcode: HSUB_U_W
+/* 10715 */ MCD::OPC_FilterValue, 31, 234, 24, 0, // Skip to: 17098
+/* 10720 */ MCD::OPC_CheckPredicate, 30, 229, 24, 0, // Skip to: 17098
+/* 10725 */ MCD::OPC_Decode, 251, 11, 132, 2, // Opcode: HSUB_U_D
+/* 10730 */ MCD::OPC_FilterValue, 25, 26, 2, 0, // Skip to: 11273
+/* 10735 */ MCD::OPC_ExtractField, 20, 6, // Inst{25-20} ...
+/* 10738 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10753
+/* 10743 */ MCD::OPC_CheckPredicate, 30, 206, 24, 0, // Skip to: 17098
+/* 10748 */ MCD::OPC_Decode, 141, 18, 144, 2, // Opcode: SLDI_B
+/* 10753 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10775
+/* 10758 */ MCD::OPC_CheckPredicate, 30, 191, 24, 0, // Skip to: 17098
+/* 10763 */ MCD::OPC_CheckField, 19, 1, 0, 184, 24, 0, // Skip to: 17098
+/* 10770 */ MCD::OPC_Decode, 143, 18, 145, 2, // Opcode: SLDI_H
+/* 10775 */ MCD::OPC_FilterValue, 3, 62, 0, 0, // Skip to: 10842
+/* 10780 */ MCD::OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 10783 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10798
+/* 10788 */ MCD::OPC_CheckPredicate, 30, 161, 24, 0, // Skip to: 17098
+/* 10793 */ MCD::OPC_Decode, 144, 18, 146, 2, // Opcode: SLDI_W
+/* 10798 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10820
+/* 10803 */ MCD::OPC_CheckPredicate, 30, 146, 24, 0, // Skip to: 17098
+/* 10808 */ MCD::OPC_CheckField, 17, 1, 0, 139, 24, 0, // Skip to: 17098
+/* 10815 */ MCD::OPC_Decode, 142, 18, 147, 2, // Opcode: SLDI_D
+/* 10820 */ MCD::OPC_FilterValue, 3, 129, 24, 0, // Skip to: 17098
+/* 10825 */ MCD::OPC_CheckPredicate, 30, 124, 24, 0, // Skip to: 17098
+/* 10830 */ MCD::OPC_CheckField, 16, 2, 2, 117, 24, 0, // Skip to: 17098
+/* 10837 */ MCD::OPC_Decode, 132, 8, 148, 2, // Opcode: CTCMSA
+/* 10842 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 10857
+/* 10847 */ MCD::OPC_CheckPredicate, 30, 102, 24, 0, // Skip to: 17098
+/* 10852 */ MCD::OPC_Decode, 180, 18, 149, 2, // Opcode: SPLATI_B
+/* 10857 */ MCD::OPC_FilterValue, 6, 17, 0, 0, // Skip to: 10879
+/* 10862 */ MCD::OPC_CheckPredicate, 30, 87, 24, 0, // Skip to: 17098
+/* 10867 */ MCD::OPC_CheckField, 19, 1, 0, 80, 24, 0, // Skip to: 17098
+/* 10874 */ MCD::OPC_Decode, 182, 18, 150, 2, // Opcode: SPLATI_H
+/* 10879 */ MCD::OPC_FilterValue, 7, 62, 0, 0, // Skip to: 10946
+/* 10884 */ MCD::OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 10887 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10902
+/* 10892 */ MCD::OPC_CheckPredicate, 30, 57, 24, 0, // Skip to: 17098
+/* 10897 */ MCD::OPC_Decode, 183, 18, 151, 2, // Opcode: SPLATI_W
+/* 10902 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 10924
+/* 10907 */ MCD::OPC_CheckPredicate, 30, 42, 24, 0, // Skip to: 17098
+/* 10912 */ MCD::OPC_CheckField, 17, 1, 0, 35, 24, 0, // Skip to: 17098
+/* 10919 */ MCD::OPC_Decode, 181, 18, 152, 2, // Opcode: SPLATI_D
+/* 10924 */ MCD::OPC_FilterValue, 3, 25, 24, 0, // Skip to: 17098
+/* 10929 */ MCD::OPC_CheckPredicate, 30, 20, 24, 0, // Skip to: 17098
+/* 10934 */ MCD::OPC_CheckField, 16, 2, 2, 13, 24, 0, // Skip to: 17098
+/* 10941 */ MCD::OPC_Decode, 233, 6, 153, 2, // Opcode: CFCMSA
+/* 10946 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 10961
+/* 10951 */ MCD::OPC_CheckPredicate, 30, 254, 23, 0, // Skip to: 17098
+/* 10956 */ MCD::OPC_Decode, 242, 7, 154, 2, // Opcode: COPY_S_B
+/* 10961 */ MCD::OPC_FilterValue, 10, 17, 0, 0, // Skip to: 10983
+/* 10966 */ MCD::OPC_CheckPredicate, 30, 239, 23, 0, // Skip to: 17098
+/* 10971 */ MCD::OPC_CheckField, 19, 1, 0, 232, 23, 0, // Skip to: 17098
+/* 10978 */ MCD::OPC_Decode, 244, 7, 155, 2, // Opcode: COPY_S_H
+/* 10983 */ MCD::OPC_FilterValue, 11, 62, 0, 0, // Skip to: 11050
+/* 10988 */ MCD::OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 10991 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11006
+/* 10996 */ MCD::OPC_CheckPredicate, 30, 209, 23, 0, // Skip to: 17098
+/* 11001 */ MCD::OPC_Decode, 245, 7, 156, 2, // Opcode: COPY_S_W
+/* 11006 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 11028
+/* 11011 */ MCD::OPC_CheckPredicate, 38, 194, 23, 0, // Skip to: 17098
+/* 11016 */ MCD::OPC_CheckField, 17, 1, 0, 187, 23, 0, // Skip to: 17098
+/* 11023 */ MCD::OPC_Decode, 243, 7, 157, 2, // Opcode: COPY_S_D
+/* 11028 */ MCD::OPC_FilterValue, 3, 177, 23, 0, // Skip to: 17098
+/* 11033 */ MCD::OPC_CheckPredicate, 30, 172, 23, 0, // Skip to: 17098
+/* 11038 */ MCD::OPC_CheckField, 16, 2, 2, 165, 23, 0, // Skip to: 17098
+/* 11045 */ MCD::OPC_Decode, 208, 14, 158, 2, // Opcode: MOVE_V
+/* 11050 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 11065
+/* 11055 */ MCD::OPC_CheckPredicate, 30, 150, 23, 0, // Skip to: 17098
+/* 11060 */ MCD::OPC_Decode, 246, 7, 154, 2, // Opcode: COPY_U_B
+/* 11065 */ MCD::OPC_FilterValue, 14, 17, 0, 0, // Skip to: 11087
+/* 11070 */ MCD::OPC_CheckPredicate, 30, 135, 23, 0, // Skip to: 17098
+/* 11075 */ MCD::OPC_CheckField, 19, 1, 0, 128, 23, 0, // Skip to: 17098
+/* 11082 */ MCD::OPC_Decode, 247, 7, 155, 2, // Opcode: COPY_U_H
+/* 11087 */ MCD::OPC_FilterValue, 15, 17, 0, 0, // Skip to: 11109
+/* 11092 */ MCD::OPC_CheckPredicate, 38, 113, 23, 0, // Skip to: 17098
+/* 11097 */ MCD::OPC_CheckField, 18, 2, 0, 106, 23, 0, // Skip to: 17098
+/* 11104 */ MCD::OPC_Decode, 248, 7, 156, 2, // Opcode: COPY_U_W
+/* 11109 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11124
+/* 11114 */ MCD::OPC_CheckPredicate, 30, 91, 23, 0, // Skip to: 17098
+/* 11119 */ MCD::OPC_Decode, 145, 12, 159, 2, // Opcode: INSERT_B
+/* 11124 */ MCD::OPC_FilterValue, 18, 17, 0, 0, // Skip to: 11146
+/* 11129 */ MCD::OPC_CheckPredicate, 30, 76, 23, 0, // Skip to: 17098
+/* 11134 */ MCD::OPC_CheckField, 19, 1, 0, 69, 23, 0, // Skip to: 17098
+/* 11141 */ MCD::OPC_Decode, 147, 12, 160, 2, // Opcode: INSERT_H
+/* 11146 */ MCD::OPC_FilterValue, 19, 40, 0, 0, // Skip to: 11191
+/* 11151 */ MCD::OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 11154 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11169
+/* 11159 */ MCD::OPC_CheckPredicate, 30, 46, 23, 0, // Skip to: 17098
+/* 11164 */ MCD::OPC_Decode, 148, 12, 161, 2, // Opcode: INSERT_W
+/* 11169 */ MCD::OPC_FilterValue, 2, 36, 23, 0, // Skip to: 17098
+/* 11174 */ MCD::OPC_CheckPredicate, 38, 31, 23, 0, // Skip to: 17098
+/* 11179 */ MCD::OPC_CheckField, 17, 1, 0, 24, 23, 0, // Skip to: 17098
+/* 11186 */ MCD::OPC_Decode, 146, 12, 162, 2, // Opcode: INSERT_D
+/* 11191 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 11206
+/* 11196 */ MCD::OPC_CheckPredicate, 30, 9, 23, 0, // Skip to: 17098
+/* 11201 */ MCD::OPC_Decode, 150, 12, 163, 2, // Opcode: INSVE_B
+/* 11206 */ MCD::OPC_FilterValue, 22, 17, 0, 0, // Skip to: 11228
+/* 11211 */ MCD::OPC_CheckPredicate, 30, 250, 22, 0, // Skip to: 17098
+/* 11216 */ MCD::OPC_CheckField, 19, 1, 0, 243, 22, 0, // Skip to: 17098
+/* 11223 */ MCD::OPC_Decode, 152, 12, 163, 2, // Opcode: INSVE_H
+/* 11228 */ MCD::OPC_FilterValue, 23, 233, 22, 0, // Skip to: 17098
+/* 11233 */ MCD::OPC_ExtractField, 18, 2, // Inst{19-18} ...
+/* 11236 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11251
+/* 11241 */ MCD::OPC_CheckPredicate, 30, 220, 22, 0, // Skip to: 17098
+/* 11246 */ MCD::OPC_Decode, 153, 12, 163, 2, // Opcode: INSVE_W
+/* 11251 */ MCD::OPC_FilterValue, 2, 210, 22, 0, // Skip to: 17098
+/* 11256 */ MCD::OPC_CheckPredicate, 30, 205, 22, 0, // Skip to: 17098
+/* 11261 */ MCD::OPC_CheckField, 17, 1, 0, 198, 22, 0, // Skip to: 17098
+/* 11268 */ MCD::OPC_Decode, 151, 12, 163, 2, // Opcode: INSVE_D
+/* 11273 */ MCD::OPC_FilterValue, 26, 227, 1, 0, // Skip to: 11761
+/* 11278 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 11281 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11296
+/* 11286 */ MCD::OPC_CheckPredicate, 30, 175, 22, 0, // Skip to: 17098
+/* 11291 */ MCD::OPC_Decode, 205, 10, 252, 1, // Opcode: FCAF_W
+/* 11296 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11311
+/* 11301 */ MCD::OPC_CheckPredicate, 30, 160, 22, 0, // Skip to: 17098
+/* 11306 */ MCD::OPC_Decode, 204, 10, 253, 1, // Opcode: FCAF_D
+/* 11311 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11326
+/* 11316 */ MCD::OPC_CheckPredicate, 30, 145, 22, 0, // Skip to: 17098
+/* 11321 */ MCD::OPC_Decode, 232, 10, 252, 1, // Opcode: FCUN_W
+/* 11326 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 11341
+/* 11331 */ MCD::OPC_CheckPredicate, 30, 130, 22, 0, // Skip to: 17098
+/* 11336 */ MCD::OPC_Decode, 231, 10, 253, 1, // Opcode: FCUN_D
+/* 11341 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 11356
+/* 11346 */ MCD::OPC_CheckPredicate, 30, 115, 22, 0, // Skip to: 17098
+/* 11351 */ MCD::OPC_Decode, 207, 10, 252, 1, // Opcode: FCEQ_W
+/* 11356 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 11371
+/* 11361 */ MCD::OPC_CheckPredicate, 30, 100, 22, 0, // Skip to: 17098
+/* 11366 */ MCD::OPC_Decode, 206, 10, 253, 1, // Opcode: FCEQ_D
+/* 11371 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 11386
+/* 11376 */ MCD::OPC_CheckPredicate, 30, 85, 22, 0, // Skip to: 17098
+/* 11381 */ MCD::OPC_Decode, 224, 10, 252, 1, // Opcode: FCUEQ_W
+/* 11386 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 11401
+/* 11391 */ MCD::OPC_CheckPredicate, 30, 70, 22, 0, // Skip to: 17098
+/* 11396 */ MCD::OPC_Decode, 223, 10, 253, 1, // Opcode: FCUEQ_D
+/* 11401 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 11416
+/* 11406 */ MCD::OPC_CheckPredicate, 30, 55, 22, 0, // Skip to: 17098
+/* 11411 */ MCD::OPC_Decode, 213, 10, 252, 1, // Opcode: FCLT_W
+/* 11416 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 11431
+/* 11421 */ MCD::OPC_CheckPredicate, 30, 40, 22, 0, // Skip to: 17098
+/* 11426 */ MCD::OPC_Decode, 212, 10, 253, 1, // Opcode: FCLT_D
+/* 11431 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 11446
+/* 11436 */ MCD::OPC_CheckPredicate, 30, 25, 22, 0, // Skip to: 17098
+/* 11441 */ MCD::OPC_Decode, 228, 10, 252, 1, // Opcode: FCULT_W
+/* 11446 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 11461
+/* 11451 */ MCD::OPC_CheckPredicate, 30, 10, 22, 0, // Skip to: 17098
+/* 11456 */ MCD::OPC_Decode, 227, 10, 253, 1, // Opcode: FCULT_D
+/* 11461 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 11476
+/* 11466 */ MCD::OPC_CheckPredicate, 30, 251, 21, 0, // Skip to: 17098
+/* 11471 */ MCD::OPC_Decode, 211, 10, 252, 1, // Opcode: FCLE_W
+/* 11476 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 11491
+/* 11481 */ MCD::OPC_CheckPredicate, 30, 236, 21, 0, // Skip to: 17098
+/* 11486 */ MCD::OPC_Decode, 210, 10, 253, 1, // Opcode: FCLE_D
+/* 11491 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11506
+/* 11496 */ MCD::OPC_CheckPredicate, 30, 221, 21, 0, // Skip to: 17098
+/* 11501 */ MCD::OPC_Decode, 226, 10, 252, 1, // Opcode: FCULE_W
+/* 11506 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 11521
+/* 11511 */ MCD::OPC_CheckPredicate, 30, 206, 21, 0, // Skip to: 17098
+/* 11516 */ MCD::OPC_Decode, 225, 10, 253, 1, // Opcode: FCULE_D
+/* 11521 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11536
+/* 11526 */ MCD::OPC_CheckPredicate, 30, 191, 21, 0, // Skip to: 17098
+/* 11531 */ MCD::OPC_Decode, 190, 11, 252, 1, // Opcode: FSAF_W
+/* 11536 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 11551
+/* 11541 */ MCD::OPC_CheckPredicate, 30, 176, 21, 0, // Skip to: 17098
+/* 11546 */ MCD::OPC_Decode, 189, 11, 253, 1, // Opcode: FSAF_D
+/* 11551 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 11566
+/* 11556 */ MCD::OPC_CheckPredicate, 30, 161, 21, 0, // Skip to: 17098
+/* 11561 */ MCD::OPC_Decode, 227, 11, 252, 1, // Opcode: FSUN_W
+/* 11566 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 11581
+/* 11571 */ MCD::OPC_CheckPredicate, 30, 146, 21, 0, // Skip to: 17098
+/* 11576 */ MCD::OPC_Decode, 226, 11, 253, 1, // Opcode: FSUN_D
+/* 11581 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 11596
+/* 11586 */ MCD::OPC_CheckPredicate, 30, 131, 21, 0, // Skip to: 17098
+/* 11591 */ MCD::OPC_Decode, 192, 11, 252, 1, // Opcode: FSEQ_W
+/* 11596 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 11611
+/* 11601 */ MCD::OPC_CheckPredicate, 30, 116, 21, 0, // Skip to: 17098
+/* 11606 */ MCD::OPC_Decode, 191, 11, 253, 1, // Opcode: FSEQ_D
+/* 11611 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 11626
+/* 11616 */ MCD::OPC_CheckPredicate, 30, 101, 21, 0, // Skip to: 17098
+/* 11621 */ MCD::OPC_Decode, 219, 11, 252, 1, // Opcode: FSUEQ_W
+/* 11626 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 11641
+/* 11631 */ MCD::OPC_CheckPredicate, 30, 86, 21, 0, // Skip to: 17098
+/* 11636 */ MCD::OPC_Decode, 218, 11, 253, 1, // Opcode: FSUEQ_D
+/* 11641 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 11656
+/* 11646 */ MCD::OPC_CheckPredicate, 30, 71, 21, 0, // Skip to: 17098
+/* 11651 */ MCD::OPC_Decode, 196, 11, 252, 1, // Opcode: FSLT_W
+/* 11656 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 11671
+/* 11661 */ MCD::OPC_CheckPredicate, 30, 56, 21, 0, // Skip to: 17098
+/* 11666 */ MCD::OPC_Decode, 195, 11, 253, 1, // Opcode: FSLT_D
+/* 11671 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 11686
+/* 11676 */ MCD::OPC_CheckPredicate, 30, 41, 21, 0, // Skip to: 17098
+/* 11681 */ MCD::OPC_Decode, 223, 11, 252, 1, // Opcode: FSULT_W
+/* 11686 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 11701
+/* 11691 */ MCD::OPC_CheckPredicate, 30, 26, 21, 0, // Skip to: 17098
+/* 11696 */ MCD::OPC_Decode, 222, 11, 253, 1, // Opcode: FSULT_D
+/* 11701 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 11716
+/* 11706 */ MCD::OPC_CheckPredicate, 30, 11, 21, 0, // Skip to: 17098
+/* 11711 */ MCD::OPC_Decode, 194, 11, 252, 1, // Opcode: FSLE_W
+/* 11716 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 11731
+/* 11721 */ MCD::OPC_CheckPredicate, 30, 252, 20, 0, // Skip to: 17098
+/* 11726 */ MCD::OPC_Decode, 193, 11, 253, 1, // Opcode: FSLE_D
+/* 11731 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 11746
+/* 11736 */ MCD::OPC_CheckPredicate, 30, 237, 20, 0, // Skip to: 17098
+/* 11741 */ MCD::OPC_Decode, 221, 11, 252, 1, // Opcode: FSULE_W
+/* 11746 */ MCD::OPC_FilterValue, 31, 227, 20, 0, // Skip to: 17098
+/* 11751 */ MCD::OPC_CheckPredicate, 30, 222, 20, 0, // Skip to: 17098
+/* 11756 */ MCD::OPC_Decode, 220, 11, 253, 1, // Opcode: FSULE_D
+/* 11761 */ MCD::OPC_FilterValue, 27, 137, 1, 0, // Skip to: 12159
+/* 11766 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 11769 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11784
+/* 11774 */ MCD::OPC_CheckPredicate, 30, 199, 20, 0, // Skip to: 17098
+/* 11779 */ MCD::OPC_Decode, 203, 10, 252, 1, // Opcode: FADD_W
+/* 11784 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 11799
+/* 11789 */ MCD::OPC_CheckPredicate, 30, 184, 20, 0, // Skip to: 17098
+/* 11794 */ MCD::OPC_Decode, 195, 10, 253, 1, // Opcode: FADD_D
+/* 11799 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 11814
+/* 11804 */ MCD::OPC_CheckPredicate, 30, 169, 20, 0, // Skip to: 17098
+/* 11809 */ MCD::OPC_Decode, 217, 11, 252, 1, // Opcode: FSUB_W
+/* 11814 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 11829
+/* 11819 */ MCD::OPC_CheckPredicate, 30, 154, 20, 0, // Skip to: 17098
+/* 11824 */ MCD::OPC_Decode, 209, 11, 253, 1, // Opcode: FSUB_D
+/* 11829 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 11844
+/* 11834 */ MCD::OPC_CheckPredicate, 30, 139, 20, 0, // Skip to: 17098
+/* 11839 */ MCD::OPC_Decode, 174, 11, 252, 1, // Opcode: FMUL_W
+/* 11844 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 11859
+/* 11849 */ MCD::OPC_CheckPredicate, 30, 124, 20, 0, // Skip to: 17098
+/* 11854 */ MCD::OPC_Decode, 166, 11, 253, 1, // Opcode: FMUL_D
+/* 11859 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 11874
+/* 11864 */ MCD::OPC_CheckPredicate, 30, 109, 20, 0, // Skip to: 17098
+/* 11869 */ MCD::OPC_Decode, 241, 10, 252, 1, // Opcode: FDIV_W
+/* 11874 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 11889
+/* 11879 */ MCD::OPC_CheckPredicate, 30, 94, 20, 0, // Skip to: 17098
+/* 11884 */ MCD::OPC_Decode, 233, 10, 253, 1, // Opcode: FDIV_D
+/* 11889 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 11904
+/* 11894 */ MCD::OPC_CheckPredicate, 30, 79, 20, 0, // Skip to: 17098
+/* 11899 */ MCD::OPC_Decode, 148, 11, 128, 2, // Opcode: FMADD_W
+/* 11904 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 11919
+/* 11909 */ MCD::OPC_CheckPredicate, 30, 64, 20, 0, // Skip to: 17098
+/* 11914 */ MCD::OPC_Decode, 147, 11, 129, 2, // Opcode: FMADD_D
+/* 11919 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 11934
+/* 11924 */ MCD::OPC_CheckPredicate, 30, 49, 20, 0, // Skip to: 17098
+/* 11929 */ MCD::OPC_Decode, 165, 11, 128, 2, // Opcode: FMSUB_W
+/* 11934 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 11949
+/* 11939 */ MCD::OPC_CheckPredicate, 30, 34, 20, 0, // Skip to: 17098
+/* 11944 */ MCD::OPC_Decode, 164, 11, 129, 2, // Opcode: FMSUB_D
+/* 11949 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11964
+/* 11954 */ MCD::OPC_CheckPredicate, 30, 19, 20, 0, // Skip to: 17098
+/* 11959 */ MCD::OPC_Decode, 245, 10, 252, 1, // Opcode: FEXP2_W
+/* 11964 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 11979
+/* 11969 */ MCD::OPC_CheckPredicate, 30, 4, 20, 0, // Skip to: 17098
+/* 11974 */ MCD::OPC_Decode, 244, 10, 253, 1, // Opcode: FEXP2_D
+/* 11979 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 11994
+/* 11984 */ MCD::OPC_CheckPredicate, 30, 245, 19, 0, // Skip to: 17098
+/* 11989 */ MCD::OPC_Decode, 242, 10, 164, 2, // Opcode: FEXDO_H
+/* 11994 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 12009
+/* 11999 */ MCD::OPC_CheckPredicate, 30, 230, 19, 0, // Skip to: 17098
+/* 12004 */ MCD::OPC_Decode, 243, 10, 165, 2, // Opcode: FEXDO_W
+/* 12009 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 12024
+/* 12014 */ MCD::OPC_CheckPredicate, 30, 215, 19, 0, // Skip to: 17098
+/* 12019 */ MCD::OPC_Decode, 232, 11, 164, 2, // Opcode: FTQ_H
+/* 12024 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 12039
+/* 12029 */ MCD::OPC_CheckPredicate, 30, 200, 19, 0, // Skip to: 17098
+/* 12034 */ MCD::OPC_Decode, 233, 11, 165, 2, // Opcode: FTQ_W
+/* 12039 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 12054
+/* 12044 */ MCD::OPC_CheckPredicate, 30, 185, 19, 0, // Skip to: 17098
+/* 12049 */ MCD::OPC_Decode, 156, 11, 252, 1, // Opcode: FMIN_W
+/* 12054 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 12069
+/* 12059 */ MCD::OPC_CheckPredicate, 30, 170, 19, 0, // Skip to: 17098
+/* 12064 */ MCD::OPC_Decode, 155, 11, 253, 1, // Opcode: FMIN_D
+/* 12069 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 12084
+/* 12074 */ MCD::OPC_CheckPredicate, 30, 155, 19, 0, // Skip to: 17098
+/* 12079 */ MCD::OPC_Decode, 154, 11, 252, 1, // Opcode: FMIN_A_W
+/* 12084 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 12099
+/* 12089 */ MCD::OPC_CheckPredicate, 30, 140, 19, 0, // Skip to: 17098
+/* 12094 */ MCD::OPC_Decode, 153, 11, 253, 1, // Opcode: FMIN_A_D
+/* 12099 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 12114
+/* 12104 */ MCD::OPC_CheckPredicate, 30, 125, 19, 0, // Skip to: 17098
+/* 12109 */ MCD::OPC_Decode, 152, 11, 252, 1, // Opcode: FMAX_W
+/* 12114 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 12129
+/* 12119 */ MCD::OPC_CheckPredicate, 30, 110, 19, 0, // Skip to: 17098
+/* 12124 */ MCD::OPC_Decode, 151, 11, 253, 1, // Opcode: FMAX_D
+/* 12129 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 12144
+/* 12134 */ MCD::OPC_CheckPredicate, 30, 95, 19, 0, // Skip to: 17098
+/* 12139 */ MCD::OPC_Decode, 150, 11, 252, 1, // Opcode: FMAX_A_W
+/* 12144 */ MCD::OPC_FilterValue, 31, 85, 19, 0, // Skip to: 17098
+/* 12149 */ MCD::OPC_CheckPredicate, 30, 80, 19, 0, // Skip to: 17098
+/* 12154 */ MCD::OPC_Decode, 149, 11, 253, 1, // Opcode: FMAX_A_D
+/* 12159 */ MCD::OPC_FilterValue, 28, 107, 1, 0, // Skip to: 12527
+/* 12164 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 12167 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12182
+/* 12172 */ MCD::OPC_CheckPredicate, 30, 57, 19, 0, // Skip to: 17098
+/* 12177 */ MCD::OPC_Decode, 222, 10, 252, 1, // Opcode: FCOR_W
+/* 12182 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12197
+/* 12187 */ MCD::OPC_CheckPredicate, 30, 42, 19, 0, // Skip to: 17098
+/* 12192 */ MCD::OPC_Decode, 221, 10, 253, 1, // Opcode: FCOR_D
+/* 12197 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12212
+/* 12202 */ MCD::OPC_CheckPredicate, 30, 27, 19, 0, // Skip to: 17098
+/* 12207 */ MCD::OPC_Decode, 230, 10, 252, 1, // Opcode: FCUNE_W
+/* 12212 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12227
+/* 12217 */ MCD::OPC_CheckPredicate, 30, 12, 19, 0, // Skip to: 17098
+/* 12222 */ MCD::OPC_Decode, 229, 10, 253, 1, // Opcode: FCUNE_D
+/* 12227 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12242
+/* 12232 */ MCD::OPC_CheckPredicate, 30, 253, 18, 0, // Skip to: 17098
+/* 12237 */ MCD::OPC_Decode, 220, 10, 252, 1, // Opcode: FCNE_W
+/* 12242 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 12257
+/* 12247 */ MCD::OPC_CheckPredicate, 30, 238, 18, 0, // Skip to: 17098
+/* 12252 */ MCD::OPC_Decode, 219, 10, 253, 1, // Opcode: FCNE_D
+/* 12257 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 12272
+/* 12262 */ MCD::OPC_CheckPredicate, 30, 223, 18, 0, // Skip to: 17098
+/* 12267 */ MCD::OPC_Decode, 228, 15, 251, 1, // Opcode: MUL_Q_H
+/* 12272 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 12287
+/* 12277 */ MCD::OPC_CheckPredicate, 30, 208, 18, 0, // Skip to: 17098
+/* 12282 */ MCD::OPC_Decode, 229, 15, 252, 1, // Opcode: MUL_Q_W
+/* 12287 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 12302
+/* 12292 */ MCD::OPC_CheckPredicate, 30, 193, 18, 0, // Skip to: 17098
+/* 12297 */ MCD::OPC_Decode, 219, 13, 255, 1, // Opcode: MADD_Q_H
+/* 12302 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 12317
+/* 12307 */ MCD::OPC_CheckPredicate, 30, 178, 18, 0, // Skip to: 17098
+/* 12312 */ MCD::OPC_Decode, 220, 13, 128, 2, // Opcode: MADD_Q_W
+/* 12317 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 12332
+/* 12322 */ MCD::OPC_CheckPredicate, 30, 163, 18, 0, // Skip to: 17098
+/* 12327 */ MCD::OPC_Decode, 142, 15, 255, 1, // Opcode: MSUB_Q_H
+/* 12332 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 12347
+/* 12337 */ MCD::OPC_CheckPredicate, 30, 148, 18, 0, // Skip to: 17098
+/* 12342 */ MCD::OPC_Decode, 143, 15, 128, 2, // Opcode: MSUB_Q_W
+/* 12347 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 12362
+/* 12352 */ MCD::OPC_CheckPredicate, 30, 133, 18, 0, // Skip to: 17098
+/* 12357 */ MCD::OPC_Decode, 200, 11, 252, 1, // Opcode: FSOR_W
+/* 12362 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 12377
+/* 12367 */ MCD::OPC_CheckPredicate, 30, 118, 18, 0, // Skip to: 17098
+/* 12372 */ MCD::OPC_Decode, 199, 11, 253, 1, // Opcode: FSOR_D
+/* 12377 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 12392
+/* 12382 */ MCD::OPC_CheckPredicate, 30, 103, 18, 0, // Skip to: 17098
+/* 12387 */ MCD::OPC_Decode, 225, 11, 252, 1, // Opcode: FSUNE_W
+/* 12392 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 12407
+/* 12397 */ MCD::OPC_CheckPredicate, 30, 88, 18, 0, // Skip to: 17098
+/* 12402 */ MCD::OPC_Decode, 224, 11, 253, 1, // Opcode: FSUNE_D
+/* 12407 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 12422
+/* 12412 */ MCD::OPC_CheckPredicate, 30, 73, 18, 0, // Skip to: 17098
+/* 12417 */ MCD::OPC_Decode, 198, 11, 252, 1, // Opcode: FSNE_W
+/* 12422 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 12437
+/* 12427 */ MCD::OPC_CheckPredicate, 30, 58, 18, 0, // Skip to: 17098
+/* 12432 */ MCD::OPC_Decode, 197, 11, 253, 1, // Opcode: FSNE_D
+/* 12437 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 12452
+/* 12442 */ MCD::OPC_CheckPredicate, 30, 43, 18, 0, // Skip to: 17098
+/* 12447 */ MCD::OPC_Decode, 204, 15, 251, 1, // Opcode: MULR_Q_H
+/* 12452 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 12467
+/* 12457 */ MCD::OPC_CheckPredicate, 30, 28, 18, 0, // Skip to: 17098
+/* 12462 */ MCD::OPC_Decode, 205, 15, 252, 1, // Opcode: MULR_Q_W
+/* 12467 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 12482
+/* 12472 */ MCD::OPC_CheckPredicate, 30, 13, 18, 0, // Skip to: 17098
+/* 12477 */ MCD::OPC_Decode, 203, 13, 255, 1, // Opcode: MADDR_Q_H
+/* 12482 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 12497
+/* 12487 */ MCD::OPC_CheckPredicate, 30, 254, 17, 0, // Skip to: 17098
+/* 12492 */ MCD::OPC_Decode, 204, 13, 128, 2, // Opcode: MADDR_Q_W
+/* 12497 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 12512
+/* 12502 */ MCD::OPC_CheckPredicate, 30, 239, 17, 0, // Skip to: 17098
+/* 12507 */ MCD::OPC_Decode, 254, 14, 255, 1, // Opcode: MSUBR_Q_H
+/* 12512 */ MCD::OPC_FilterValue, 29, 229, 17, 0, // Skip to: 17098
+/* 12517 */ MCD::OPC_CheckPredicate, 30, 224, 17, 0, // Skip to: 17098
+/* 12522 */ MCD::OPC_Decode, 255, 14, 128, 2, // Opcode: MSUBR_Q_W
+/* 12527 */ MCD::OPC_FilterValue, 30, 76, 3, 0, // Skip to: 13376
+/* 12532 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 12535 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12550
+/* 12540 */ MCD::OPC_CheckPredicate, 30, 201, 17, 0, // Skip to: 17098
+/* 12545 */ MCD::OPC_Decode, 221, 4, 250, 1, // Opcode: AND_V
+/* 12550 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12565
+/* 12555 */ MCD::OPC_CheckPredicate, 30, 186, 17, 0, // Skip to: 17098
+/* 12560 */ MCD::OPC_Decode, 145, 16, 250, 1, // Opcode: OR_V
+/* 12565 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12580
+/* 12570 */ MCD::OPC_CheckPredicate, 30, 171, 17, 0, // Skip to: 17098
+/* 12575 */ MCD::OPC_Decode, 132, 16, 250, 1, // Opcode: NOR_V
+/* 12580 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12595
+/* 12585 */ MCD::OPC_CheckPredicate, 30, 156, 17, 0, // Skip to: 17098
+/* 12590 */ MCD::OPC_Decode, 190, 20, 250, 1, // Opcode: XOR_V
+/* 12595 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12610
+/* 12600 */ MCD::OPC_CheckPredicate, 30, 141, 17, 0, // Skip to: 17098
+/* 12605 */ MCD::OPC_Decode, 136, 6, 254, 1, // Opcode: BMNZ_V
+/* 12610 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12625
+/* 12615 */ MCD::OPC_CheckPredicate, 30, 126, 17, 0, // Skip to: 17098
+/* 12620 */ MCD::OPC_Decode, 138, 6, 254, 1, // Opcode: BMZ_V
+/* 12625 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12640
+/* 12630 */ MCD::OPC_CheckPredicate, 30, 111, 17, 0, // Skip to: 17098
+/* 12635 */ MCD::OPC_Decode, 180, 6, 254, 1, // Opcode: BSEL_V
+/* 12640 */ MCD::OPC_FilterValue, 24, 243, 0, 0, // Skip to: 12888
+/* 12645 */ MCD::OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 12648 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12663
+/* 12653 */ MCD::OPC_CheckPredicate, 30, 88, 17, 0, // Skip to: 17098
+/* 12658 */ MCD::OPC_Decode, 130, 11, 166, 2, // Opcode: FILL_B
+/* 12663 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12678
+/* 12668 */ MCD::OPC_CheckPredicate, 30, 73, 17, 0, // Skip to: 17098
+/* 12673 */ MCD::OPC_Decode, 132, 11, 167, 2, // Opcode: FILL_H
+/* 12678 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12693
+/* 12683 */ MCD::OPC_CheckPredicate, 30, 58, 17, 0, // Skip to: 17098
+/* 12688 */ MCD::OPC_Decode, 133, 11, 168, 2, // Opcode: FILL_W
+/* 12693 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12708
+/* 12698 */ MCD::OPC_CheckPredicate, 38, 43, 17, 0, // Skip to: 17098
+/* 12703 */ MCD::OPC_Decode, 131, 11, 169, 2, // Opcode: FILL_D
+/* 12708 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12723
+/* 12713 */ MCD::OPC_CheckPredicate, 30, 28, 17, 0, // Skip to: 17098
+/* 12718 */ MCD::OPC_Decode, 163, 16, 158, 2, // Opcode: PCNT_B
+/* 12723 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12738
+/* 12728 */ MCD::OPC_CheckPredicate, 30, 13, 17, 0, // Skip to: 17098
+/* 12733 */ MCD::OPC_Decode, 165, 16, 170, 2, // Opcode: PCNT_H
+/* 12738 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 12753
+/* 12743 */ MCD::OPC_CheckPredicate, 30, 254, 16, 0, // Skip to: 17098
+/* 12748 */ MCD::OPC_Decode, 166, 16, 171, 2, // Opcode: PCNT_W
+/* 12753 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 12768
+/* 12758 */ MCD::OPC_CheckPredicate, 30, 239, 16, 0, // Skip to: 17098
+/* 12763 */ MCD::OPC_Decode, 164, 16, 172, 2, // Opcode: PCNT_D
+/* 12768 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 12783
+/* 12773 */ MCD::OPC_CheckPredicate, 30, 224, 16, 0, // Skip to: 17098
+/* 12778 */ MCD::OPC_Decode, 237, 15, 158, 2, // Opcode: NLOC_B
+/* 12783 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 12798
+/* 12788 */ MCD::OPC_CheckPredicate, 30, 209, 16, 0, // Skip to: 17098
+/* 12793 */ MCD::OPC_Decode, 239, 15, 170, 2, // Opcode: NLOC_H
+/* 12798 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 12813
+/* 12803 */ MCD::OPC_CheckPredicate, 30, 194, 16, 0, // Skip to: 17098
+/* 12808 */ MCD::OPC_Decode, 240, 15, 171, 2, // Opcode: NLOC_W
+/* 12813 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 12828
+/* 12818 */ MCD::OPC_CheckPredicate, 30, 179, 16, 0, // Skip to: 17098
+/* 12823 */ MCD::OPC_Decode, 238, 15, 172, 2, // Opcode: NLOC_D
+/* 12828 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 12843
+/* 12833 */ MCD::OPC_CheckPredicate, 30, 164, 16, 0, // Skip to: 17098
+/* 12838 */ MCD::OPC_Decode, 241, 15, 158, 2, // Opcode: NLZC_B
+/* 12843 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 12858
+/* 12848 */ MCD::OPC_CheckPredicate, 30, 149, 16, 0, // Skip to: 17098
+/* 12853 */ MCD::OPC_Decode, 243, 15, 170, 2, // Opcode: NLZC_H
+/* 12858 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 12873
+/* 12863 */ MCD::OPC_CheckPredicate, 30, 134, 16, 0, // Skip to: 17098
+/* 12868 */ MCD::OPC_Decode, 244, 15, 171, 2, // Opcode: NLZC_W
+/* 12873 */ MCD::OPC_FilterValue, 15, 124, 16, 0, // Skip to: 17098
+/* 12878 */ MCD::OPC_CheckPredicate, 30, 119, 16, 0, // Skip to: 17098
+/* 12883 */ MCD::OPC_Decode, 242, 15, 172, 2, // Opcode: NLZC_D
+/* 12888 */ MCD::OPC_FilterValue, 25, 109, 16, 0, // Skip to: 17098
+/* 12893 */ MCD::OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 12896 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12911
+/* 12901 */ MCD::OPC_CheckPredicate, 30, 96, 16, 0, // Skip to: 17098
+/* 12906 */ MCD::OPC_Decode, 209, 10, 171, 2, // Opcode: FCLASS_W
+/* 12911 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 12926
+/* 12916 */ MCD::OPC_CheckPredicate, 30, 81, 16, 0, // Skip to: 17098
+/* 12921 */ MCD::OPC_Decode, 208, 10, 172, 2, // Opcode: FCLASS_D
+/* 12926 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 12941
+/* 12931 */ MCD::OPC_CheckPredicate, 30, 66, 16, 0, // Skip to: 17098
+/* 12936 */ MCD::OPC_Decode, 235, 11, 171, 2, // Opcode: FTRUNC_S_W
+/* 12941 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 12956
+/* 12946 */ MCD::OPC_CheckPredicate, 30, 51, 16, 0, // Skip to: 17098
+/* 12951 */ MCD::OPC_Decode, 234, 11, 172, 2, // Opcode: FTRUNC_S_D
+/* 12956 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 12971
+/* 12961 */ MCD::OPC_CheckPredicate, 30, 36, 16, 0, // Skip to: 17098
+/* 12966 */ MCD::OPC_Decode, 237, 11, 171, 2, // Opcode: FTRUNC_U_W
+/* 12971 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 12986
+/* 12976 */ MCD::OPC_CheckPredicate, 30, 21, 16, 0, // Skip to: 17098
+/* 12981 */ MCD::OPC_Decode, 236, 11, 172, 2, // Opcode: FTRUNC_U_D
+/* 12986 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 13001
+/* 12991 */ MCD::OPC_CheckPredicate, 30, 6, 16, 0, // Skip to: 17098
+/* 12996 */ MCD::OPC_Decode, 208, 11, 171, 2, // Opcode: FSQRT_W
+/* 13001 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 13016
+/* 13006 */ MCD::OPC_CheckPredicate, 30, 247, 15, 0, // Skip to: 17098
+/* 13011 */ MCD::OPC_Decode, 201, 11, 172, 2, // Opcode: FSQRT_D
+/* 13016 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 13031
+/* 13021 */ MCD::OPC_CheckPredicate, 30, 232, 15, 0, // Skip to: 17098
+/* 13026 */ MCD::OPC_Decode, 188, 11, 171, 2, // Opcode: FRSQRT_W
+/* 13031 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 13046
+/* 13036 */ MCD::OPC_CheckPredicate, 30, 217, 15, 0, // Skip to: 17098
+/* 13041 */ MCD::OPC_Decode, 187, 11, 172, 2, // Opcode: FRSQRT_D
+/* 13046 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 13061
+/* 13051 */ MCD::OPC_CheckPredicate, 30, 202, 15, 0, // Skip to: 17098
+/* 13056 */ MCD::OPC_Decode, 184, 11, 171, 2, // Opcode: FRCP_W
+/* 13061 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 13076
+/* 13066 */ MCD::OPC_CheckPredicate, 30, 187, 15, 0, // Skip to: 17098
+/* 13071 */ MCD::OPC_Decode, 183, 11, 172, 2, // Opcode: FRCP_D
+/* 13076 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 13091
+/* 13081 */ MCD::OPC_CheckPredicate, 30, 172, 15, 0, // Skip to: 17098
+/* 13086 */ MCD::OPC_Decode, 186, 11, 171, 2, // Opcode: FRINT_W
+/* 13091 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 13106
+/* 13096 */ MCD::OPC_CheckPredicate, 30, 157, 15, 0, // Skip to: 17098
+/* 13101 */ MCD::OPC_Decode, 185, 11, 172, 2, // Opcode: FRINT_D
+/* 13106 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 13121
+/* 13111 */ MCD::OPC_CheckPredicate, 30, 142, 15, 0, // Skip to: 17098
+/* 13116 */ MCD::OPC_Decode, 135, 11, 171, 2, // Opcode: FLOG2_W
+/* 13121 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 13136
+/* 13126 */ MCD::OPC_CheckPredicate, 30, 127, 15, 0, // Skip to: 17098
+/* 13131 */ MCD::OPC_Decode, 134, 11, 172, 2, // Opcode: FLOG2_D
+/* 13136 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 13151
+/* 13141 */ MCD::OPC_CheckPredicate, 30, 112, 15, 0, // Skip to: 17098
+/* 13146 */ MCD::OPC_Decode, 247, 10, 173, 2, // Opcode: FEXUPL_W
+/* 13151 */ MCD::OPC_FilterValue, 17, 10, 0, 0, // Skip to: 13166
+/* 13156 */ MCD::OPC_CheckPredicate, 30, 97, 15, 0, // Skip to: 17098
+/* 13161 */ MCD::OPC_Decode, 246, 10, 174, 2, // Opcode: FEXUPL_D
+/* 13166 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 13181
+/* 13171 */ MCD::OPC_CheckPredicate, 30, 82, 15, 0, // Skip to: 17098
+/* 13176 */ MCD::OPC_Decode, 249, 10, 173, 2, // Opcode: FEXUPR_W
+/* 13181 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 13196
+/* 13186 */ MCD::OPC_CheckPredicate, 30, 67, 15, 0, // Skip to: 17098
+/* 13191 */ MCD::OPC_Decode, 248, 10, 174, 2, // Opcode: FEXUPR_D
+/* 13196 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 13211
+/* 13201 */ MCD::OPC_CheckPredicate, 30, 52, 15, 0, // Skip to: 17098
+/* 13206 */ MCD::OPC_Decode, 255, 10, 173, 2, // Opcode: FFQL_W
+/* 13211 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 13226
+/* 13216 */ MCD::OPC_CheckPredicate, 30, 37, 15, 0, // Skip to: 17098
+/* 13221 */ MCD::OPC_Decode, 254, 10, 174, 2, // Opcode: FFQL_D
+/* 13226 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 13241
+/* 13231 */ MCD::OPC_CheckPredicate, 30, 22, 15, 0, // Skip to: 17098
+/* 13236 */ MCD::OPC_Decode, 129, 11, 173, 2, // Opcode: FFQR_W
+/* 13241 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 13256
+/* 13246 */ MCD::OPC_CheckPredicate, 30, 7, 15, 0, // Skip to: 17098
+/* 13251 */ MCD::OPC_Decode, 128, 11, 174, 2, // Opcode: FFQR_D
+/* 13256 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 13271
+/* 13261 */ MCD::OPC_CheckPredicate, 30, 248, 14, 0, // Skip to: 17098
+/* 13266 */ MCD::OPC_Decode, 229, 11, 171, 2, // Opcode: FTINT_S_W
+/* 13271 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 13286
+/* 13276 */ MCD::OPC_CheckPredicate, 30, 233, 14, 0, // Skip to: 17098
+/* 13281 */ MCD::OPC_Decode, 228, 11, 172, 2, // Opcode: FTINT_S_D
+/* 13286 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 13301
+/* 13291 */ MCD::OPC_CheckPredicate, 30, 218, 14, 0, // Skip to: 17098
+/* 13296 */ MCD::OPC_Decode, 231, 11, 171, 2, // Opcode: FTINT_U_W
+/* 13301 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 13316
+/* 13306 */ MCD::OPC_CheckPredicate, 30, 203, 14, 0, // Skip to: 17098
+/* 13311 */ MCD::OPC_Decode, 230, 11, 172, 2, // Opcode: FTINT_U_D
+/* 13316 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 13331
+/* 13321 */ MCD::OPC_CheckPredicate, 30, 188, 14, 0, // Skip to: 17098
+/* 13326 */ MCD::OPC_Decode, 251, 10, 171, 2, // Opcode: FFINT_S_W
+/* 13331 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 13346
+/* 13336 */ MCD::OPC_CheckPredicate, 30, 173, 14, 0, // Skip to: 17098
+/* 13341 */ MCD::OPC_Decode, 250, 10, 172, 2, // Opcode: FFINT_S_D
+/* 13346 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 13361
+/* 13351 */ MCD::OPC_CheckPredicate, 30, 158, 14, 0, // Skip to: 17098
+/* 13356 */ MCD::OPC_Decode, 253, 10, 171, 2, // Opcode: FFINT_U_W
+/* 13361 */ MCD::OPC_FilterValue, 31, 148, 14, 0, // Skip to: 17098
+/* 13366 */ MCD::OPC_CheckPredicate, 30, 143, 14, 0, // Skip to: 17098
+/* 13371 */ MCD::OPC_Decode, 252, 10, 172, 2, // Opcode: FFINT_U_D
+/* 13376 */ MCD::OPC_FilterValue, 32, 10, 0, 0, // Skip to: 13391
+/* 13381 */ MCD::OPC_CheckPredicate, 30, 128, 14, 0, // Skip to: 17098
+/* 13386 */ MCD::OPC_Decode, 232, 12, 175, 2, // Opcode: LD_B
+/* 13391 */ MCD::OPC_FilterValue, 33, 10, 0, 0, // Skip to: 13406
+/* 13396 */ MCD::OPC_CheckPredicate, 30, 113, 14, 0, // Skip to: 17098
+/* 13401 */ MCD::OPC_Decode, 234, 12, 175, 2, // Opcode: LD_H
+/* 13406 */ MCD::OPC_FilterValue, 34, 10, 0, 0, // Skip to: 13421
+/* 13411 */ MCD::OPC_CheckPredicate, 30, 98, 14, 0, // Skip to: 17098
+/* 13416 */ MCD::OPC_Decode, 235, 12, 175, 2, // Opcode: LD_W
+/* 13421 */ MCD::OPC_FilterValue, 35, 10, 0, 0, // Skip to: 13436
+/* 13426 */ MCD::OPC_CheckPredicate, 30, 83, 14, 0, // Skip to: 17098
+/* 13431 */ MCD::OPC_Decode, 233, 12, 175, 2, // Opcode: LD_D
+/* 13436 */ MCD::OPC_FilterValue, 36, 10, 0, 0, // Skip to: 13451
+/* 13441 */ MCD::OPC_CheckPredicate, 30, 68, 14, 0, // Skip to: 17098
+/* 13446 */ MCD::OPC_Decode, 233, 18, 175, 2, // Opcode: ST_B
+/* 13451 */ MCD::OPC_FilterValue, 37, 10, 0, 0, // Skip to: 13466
+/* 13456 */ MCD::OPC_CheckPredicate, 30, 53, 14, 0, // Skip to: 17098
+/* 13461 */ MCD::OPC_Decode, 235, 18, 175, 2, // Opcode: ST_H
+/* 13466 */ MCD::OPC_FilterValue, 38, 10, 0, 0, // Skip to: 13481
+/* 13471 */ MCD::OPC_CheckPredicate, 30, 38, 14, 0, // Skip to: 17098
+/* 13476 */ MCD::OPC_Decode, 236, 18, 175, 2, // Opcode: ST_W
+/* 13481 */ MCD::OPC_FilterValue, 39, 28, 14, 0, // Skip to: 17098
+/* 13486 */ MCD::OPC_CheckPredicate, 30, 23, 14, 0, // Skip to: 17098
+/* 13491 */ MCD::OPC_Decode, 234, 18, 175, 2, // Opcode: ST_D
+/* 13496 */ MCD::OPC_FilterValue, 31, 165, 12, 0, // Skip to: 16738
+/* 13501 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 13504 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13519
+/* 13509 */ MCD::OPC_CheckPredicate, 28, 0, 14, 0, // Skip to: 17098
+/* 13514 */ MCD::OPC_Decode, 160, 10, 176, 2, // Opcode: EXT
+/* 13519 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13534
+/* 13524 */ MCD::OPC_CheckPredicate, 28, 241, 13, 0, // Skip to: 17098
+/* 13529 */ MCD::OPC_Decode, 144, 12, 177, 2, // Opcode: INS
+/* 13534 */ MCD::OPC_FilterValue, 8, 17, 0, 0, // Skip to: 13556
+/* 13539 */ MCD::OPC_CheckPredicate, 42, 226, 13, 0, // Skip to: 17098
+/* 13544 */ MCD::OPC_CheckField, 6, 5, 0, 219, 13, 0, // Skip to: 17098
+/* 13551 */ MCD::OPC_Decode, 182, 11, 178, 2, // Opcode: FORK
+/* 13556 */ MCD::OPC_FilterValue, 9, 23, 0, 0, // Skip to: 13584
+/* 13561 */ MCD::OPC_CheckPredicate, 42, 204, 13, 0, // Skip to: 17098
+/* 13566 */ MCD::OPC_CheckField, 16, 5, 0, 197, 13, 0, // Skip to: 17098
+/* 13573 */ MCD::OPC_CheckField, 6, 5, 0, 190, 13, 0, // Skip to: 17098
+/* 13580 */ MCD::OPC_Decode, 195, 20, 14, // Opcode: YIELD
+/* 13584 */ MCD::OPC_FilterValue, 10, 48, 0, 0, // Skip to: 13637
+/* 13589 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 13592 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13607
+/* 13597 */ MCD::OPC_CheckPredicate, 37, 168, 13, 0, // Skip to: 17098
+/* 13602 */ MCD::OPC_Decode, 179, 13, 179, 2, // Opcode: LWX
+/* 13607 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13622
+/* 13612 */ MCD::OPC_CheckPredicate, 37, 153, 13, 0, // Skip to: 17098
+/* 13617 */ MCD::OPC_Decode, 244, 12, 179, 2, // Opcode: LHX
+/* 13622 */ MCD::OPC_FilterValue, 6, 143, 13, 0, // Skip to: 17098
+/* 13627 */ MCD::OPC_CheckPredicate, 37, 138, 13, 0, // Skip to: 17098
+/* 13632 */ MCD::OPC_Decode, 204, 12, 179, 2, // Opcode: LBUX
+/* 13637 */ MCD::OPC_FilterValue, 12, 17, 0, 0, // Skip to: 13659
+/* 13642 */ MCD::OPC_CheckPredicate, 37, 123, 13, 0, // Skip to: 17098
+/* 13647 */ MCD::OPC_CheckField, 6, 10, 0, 116, 13, 0, // Skip to: 17098
+/* 13654 */ MCD::OPC_Decode, 149, 12, 180, 2, // Opcode: INSV
+/* 13659 */ MCD::OPC_FilterValue, 16, 109, 1, 0, // Skip to: 14029
+/* 13664 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 13667 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13682
+/* 13672 */ MCD::OPC_CheckPredicate, 37, 93, 13, 0, // Skip to: 17098
+/* 13677 */ MCD::OPC_Decode, 179, 4, 181, 2, // Opcode: ADDU_QB
+/* 13682 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 13697
+/* 13687 */ MCD::OPC_CheckPredicate, 37, 78, 13, 0, // Skip to: 17098
+/* 13692 */ MCD::OPC_Decode, 149, 19, 181, 2, // Opcode: SUBU_QB
+/* 13697 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 13712
+/* 13702 */ MCD::OPC_CheckPredicate, 37, 63, 13, 0, // Skip to: 17098
+/* 13707 */ MCD::OPC_Decode, 183, 4, 181, 2, // Opcode: ADDU_S_QB
+/* 13712 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 13727
+/* 13717 */ MCD::OPC_CheckPredicate, 37, 48, 13, 0, // Skip to: 17098
+/* 13722 */ MCD::OPC_Decode, 153, 19, 181, 2, // Opcode: SUBU_S_QB
+/* 13727 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 13742
+/* 13732 */ MCD::OPC_CheckPredicate, 37, 33, 13, 0, // Skip to: 17098
+/* 13737 */ MCD::OPC_Decode, 192, 15, 181, 2, // Opcode: MULEU_S_PH_QBL
+/* 13742 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 13757
+/* 13747 */ MCD::OPC_CheckPredicate, 37, 18, 13, 0, // Skip to: 17098
+/* 13752 */ MCD::OPC_Decode, 194, 15, 181, 2, // Opcode: MULEU_S_PH_QBR
+/* 13757 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 13772
+/* 13762 */ MCD::OPC_CheckPredicate, 68, 3, 13, 0, // Skip to: 17098
+/* 13767 */ MCD::OPC_Decode, 177, 4, 181, 2, // Opcode: ADDU_PH
+/* 13772 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 13787
+/* 13777 */ MCD::OPC_CheckPredicate, 68, 244, 12, 0, // Skip to: 17098
+/* 13782 */ MCD::OPC_Decode, 147, 19, 181, 2, // Opcode: SUBU_PH
+/* 13787 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 13802
+/* 13792 */ MCD::OPC_CheckPredicate, 37, 229, 12, 0, // Skip to: 17098
+/* 13797 */ MCD::OPC_Decode, 150, 4, 181, 2, // Opcode: ADDQ_PH
+/* 13802 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 13817
+/* 13807 */ MCD::OPC_CheckPredicate, 37, 214, 12, 0, // Skip to: 17098
+/* 13812 */ MCD::OPC_Decode, 246, 18, 181, 2, // Opcode: SUBQ_PH
+/* 13817 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 13832
+/* 13822 */ MCD::OPC_CheckPredicate, 68, 199, 12, 0, // Skip to: 17098
+/* 13827 */ MCD::OPC_Decode, 181, 4, 181, 2, // Opcode: ADDU_S_PH
+/* 13832 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 13847
+/* 13837 */ MCD::OPC_CheckPredicate, 68, 184, 12, 0, // Skip to: 17098
+/* 13842 */ MCD::OPC_Decode, 151, 19, 181, 2, // Opcode: SUBU_S_PH
+/* 13847 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 13862
+/* 13852 */ MCD::OPC_CheckPredicate, 37, 169, 12, 0, // Skip to: 17098
+/* 13857 */ MCD::OPC_Decode, 152, 4, 181, 2, // Opcode: ADDQ_S_PH
+/* 13862 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 13877
+/* 13867 */ MCD::OPC_CheckPredicate, 37, 154, 12, 0, // Skip to: 17098
+/* 13872 */ MCD::OPC_Decode, 248, 18, 181, 2, // Opcode: SUBQ_S_PH
+/* 13877 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 13891
+/* 13882 */ MCD::OPC_CheckPredicate, 37, 139, 12, 0, // Skip to: 17098
+/* 13887 */ MCD::OPC_Decode, 156, 4, 49, // Opcode: ADDSC
+/* 13891 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 13905
+/* 13896 */ MCD::OPC_CheckPredicate, 37, 125, 12, 0, // Skip to: 17098
+/* 13901 */ MCD::OPC_Decode, 193, 4, 49, // Opcode: ADDWC
+/* 13905 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 13919
+/* 13910 */ MCD::OPC_CheckPredicate, 37, 111, 12, 0, // Skip to: 17098
+/* 13915 */ MCD::OPC_Decode, 191, 14, 49, // Opcode: MODSUB
+/* 13919 */ MCD::OPC_FilterValue, 20, 17, 0, 0, // Skip to: 13941
+/* 13924 */ MCD::OPC_CheckPredicate, 37, 97, 12, 0, // Skip to: 17098
+/* 13929 */ MCD::OPC_CheckField, 16, 5, 0, 90, 12, 0, // Skip to: 17098
+/* 13936 */ MCD::OPC_Decode, 215, 16, 182, 2, // Opcode: RADDU_W_QB
+/* 13941 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 13955
+/* 13946 */ MCD::OPC_CheckPredicate, 37, 75, 12, 0, // Skip to: 17098
+/* 13951 */ MCD::OPC_Decode, 154, 4, 49, // Opcode: ADDQ_S_W
+/* 13955 */ MCD::OPC_FilterValue, 23, 9, 0, 0, // Skip to: 13969
+/* 13960 */ MCD::OPC_CheckPredicate, 37, 61, 12, 0, // Skip to: 17098
+/* 13965 */ MCD::OPC_Decode, 250, 18, 49, // Opcode: SUBQ_S_W
+/* 13969 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 13984
+/* 13974 */ MCD::OPC_CheckPredicate, 37, 47, 12, 0, // Skip to: 17098
+/* 13979 */ MCD::OPC_Decode, 188, 15, 183, 2, // Opcode: MULEQ_S_W_PHL
+/* 13984 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 13999
+/* 13989 */ MCD::OPC_CheckPredicate, 37, 32, 12, 0, // Skip to: 17098
+/* 13994 */ MCD::OPC_Decode, 190, 15, 183, 2, // Opcode: MULEQ_S_W_PHR
+/* 13999 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 14014
+/* 14004 */ MCD::OPC_CheckPredicate, 68, 17, 12, 0, // Skip to: 17098
+/* 14009 */ MCD::OPC_Decode, 200, 15, 181, 2, // Opcode: MULQ_S_PH
+/* 14014 */ MCD::OPC_FilterValue, 31, 7, 12, 0, // Skip to: 17098
+/* 14019 */ MCD::OPC_CheckPredicate, 37, 2, 12, 0, // Skip to: 17098
+/* 14024 */ MCD::OPC_Decode, 196, 15, 181, 2, // Opcode: MULQ_RS_PH
+/* 14029 */ MCD::OPC_FilterValue, 17, 113, 1, 0, // Skip to: 14403
+/* 14034 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 14037 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14058
+/* 14042 */ MCD::OPC_CheckPredicate, 37, 235, 11, 0, // Skip to: 17098
+/* 14047 */ MCD::OPC_CheckField, 11, 5, 0, 228, 11, 0, // Skip to: 17098
+/* 14054 */ MCD::OPC_Decode, 166, 7, 67, // Opcode: CMPU_EQ_QB
+/* 14058 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 14079
+/* 14063 */ MCD::OPC_CheckPredicate, 37, 214, 11, 0, // Skip to: 17098
+/* 14068 */ MCD::OPC_CheckField, 11, 5, 0, 207, 11, 0, // Skip to: 17098
+/* 14075 */ MCD::OPC_Decode, 170, 7, 67, // Opcode: CMPU_LT_QB
+/* 14079 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 14100
+/* 14084 */ MCD::OPC_CheckPredicate, 37, 193, 11, 0, // Skip to: 17098
+/* 14089 */ MCD::OPC_CheckField, 11, 5, 0, 186, 11, 0, // Skip to: 17098
+/* 14096 */ MCD::OPC_Decode, 168, 7, 67, // Opcode: CMPU_LE_QB
+/* 14100 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14115
+/* 14105 */ MCD::OPC_CheckPredicate, 37, 172, 11, 0, // Skip to: 17098
+/* 14110 */ MCD::OPC_Decode, 169, 16, 181, 2, // Opcode: PICK_QB
+/* 14115 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 14130
+/* 14120 */ MCD::OPC_CheckPredicate, 37, 157, 11, 0, // Skip to: 17098
+/* 14125 */ MCD::OPC_Decode, 160, 7, 183, 2, // Opcode: CMPGU_EQ_QB
+/* 14130 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 14145
+/* 14135 */ MCD::OPC_CheckPredicate, 37, 142, 11, 0, // Skip to: 17098
+/* 14140 */ MCD::OPC_Decode, 164, 7, 183, 2, // Opcode: CMPGU_LT_QB
+/* 14145 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 14160
+/* 14150 */ MCD::OPC_CheckPredicate, 37, 127, 11, 0, // Skip to: 17098
+/* 14155 */ MCD::OPC_Decode, 162, 7, 183, 2, // Opcode: CMPGU_LE_QB
+/* 14160 */ MCD::OPC_FilterValue, 8, 16, 0, 0, // Skip to: 14181
+/* 14165 */ MCD::OPC_CheckPredicate, 37, 112, 11, 0, // Skip to: 17098
+/* 14170 */ MCD::OPC_CheckField, 11, 5, 0, 105, 11, 0, // Skip to: 17098
+/* 14177 */ MCD::OPC_Decode, 176, 7, 67, // Opcode: CMP_EQ_PH
+/* 14181 */ MCD::OPC_FilterValue, 9, 16, 0, 0, // Skip to: 14202
+/* 14186 */ MCD::OPC_CheckPredicate, 37, 91, 11, 0, // Skip to: 17098
+/* 14191 */ MCD::OPC_CheckField, 11, 5, 0, 84, 11, 0, // Skip to: 17098
+/* 14198 */ MCD::OPC_Decode, 190, 7, 67, // Opcode: CMP_LT_PH
+/* 14202 */ MCD::OPC_FilterValue, 10, 16, 0, 0, // Skip to: 14223
+/* 14207 */ MCD::OPC_CheckPredicate, 37, 70, 11, 0, // Skip to: 17098
+/* 14212 */ MCD::OPC_CheckField, 11, 5, 0, 63, 11, 0, // Skip to: 17098
+/* 14219 */ MCD::OPC_Decode, 184, 7, 67, // Opcode: CMP_LE_PH
+/* 14223 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 14238
+/* 14228 */ MCD::OPC_CheckPredicate, 37, 49, 11, 0, // Skip to: 17098
+/* 14233 */ MCD::OPC_Decode, 167, 16, 181, 2, // Opcode: PICK_PH
+/* 14238 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 14253
+/* 14243 */ MCD::OPC_CheckPredicate, 37, 34, 11, 0, // Skip to: 17098
+/* 14248 */ MCD::OPC_Decode, 196, 16, 181, 2, // Opcode: PRECRQ_QB_PH
+/* 14253 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 14268
+/* 14258 */ MCD::OPC_CheckPredicate, 68, 19, 11, 0, // Skip to: 17098
+/* 14263 */ MCD::OPC_Decode, 200, 16, 181, 2, // Opcode: PRECR_QB_PH
+/* 14268 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 14283
+/* 14273 */ MCD::OPC_CheckPredicate, 37, 4, 11, 0, // Skip to: 17098
+/* 14278 */ MCD::OPC_Decode, 150, 16, 181, 2, // Opcode: PACKRL_PH
+/* 14283 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 14298
+/* 14288 */ MCD::OPC_CheckPredicate, 37, 245, 10, 0, // Skip to: 17098
+/* 14293 */ MCD::OPC_Decode, 192, 16, 181, 2, // Opcode: PRECRQU_S_QB_PH
+/* 14298 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 14313
+/* 14303 */ MCD::OPC_CheckPredicate, 37, 230, 10, 0, // Skip to: 17098
+/* 14308 */ MCD::OPC_Decode, 194, 16, 184, 2, // Opcode: PRECRQ_PH_W
+/* 14313 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 14328
+/* 14318 */ MCD::OPC_CheckPredicate, 37, 215, 10, 0, // Skip to: 17098
+/* 14323 */ MCD::OPC_Decode, 198, 16, 184, 2, // Opcode: PRECRQ_RS_PH_W
+/* 14328 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 14343
+/* 14333 */ MCD::OPC_CheckPredicate, 68, 200, 10, 0, // Skip to: 17098
+/* 14338 */ MCD::OPC_Decode, 154, 7, 183, 2, // Opcode: CMPGDU_EQ_QB
+/* 14343 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 14358
+/* 14348 */ MCD::OPC_CheckPredicate, 68, 185, 10, 0, // Skip to: 17098
+/* 14353 */ MCD::OPC_Decode, 158, 7, 183, 2, // Opcode: CMPGDU_LT_QB
+/* 14358 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 14373
+/* 14363 */ MCD::OPC_CheckPredicate, 68, 170, 10, 0, // Skip to: 17098
+/* 14368 */ MCD::OPC_Decode, 156, 7, 183, 2, // Opcode: CMPGDU_LE_QB
+/* 14373 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 14388
+/* 14378 */ MCD::OPC_CheckPredicate, 68, 155, 10, 0, // Skip to: 17098
+/* 14383 */ MCD::OPC_Decode, 202, 16, 185, 2, // Opcode: PRECR_SRA_PH_W
+/* 14388 */ MCD::OPC_FilterValue, 31, 145, 10, 0, // Skip to: 17098
+/* 14393 */ MCD::OPC_CheckPredicate, 68, 140, 10, 0, // Skip to: 17098
+/* 14398 */ MCD::OPC_Decode, 204, 16, 185, 2, // Opcode: PRECR_SRA_R_PH_W
+/* 14403 */ MCD::OPC_FilterValue, 18, 128, 1, 0, // Skip to: 14792
+/* 14408 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 14411 */ MCD::OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14433
+/* 14416 */ MCD::OPC_CheckPredicate, 68, 117, 10, 0, // Skip to: 17098
+/* 14421 */ MCD::OPC_CheckField, 21, 5, 0, 110, 10, 0, // Skip to: 17098
+/* 14428 */ MCD::OPC_Decode, 129, 4, 186, 2, // Opcode: ABSQ_S_QB
+/* 14433 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14448
+/* 14438 */ MCD::OPC_CheckPredicate, 37, 95, 10, 0, // Skip to: 17098
+/* 14443 */ MCD::OPC_Decode, 236, 16, 187, 2, // Opcode: REPL_QB
+/* 14448 */ MCD::OPC_FilterValue, 3, 17, 0, 0, // Skip to: 14470
+/* 14453 */ MCD::OPC_CheckPredicate, 37, 80, 10, 0, // Skip to: 17098
+/* 14458 */ MCD::OPC_CheckField, 21, 5, 0, 73, 10, 0, // Skip to: 17098
+/* 14465 */ MCD::OPC_Decode, 232, 16, 188, 2, // Opcode: REPLV_QB
+/* 14470 */ MCD::OPC_FilterValue, 4, 17, 0, 0, // Skip to: 14492
+/* 14475 */ MCD::OPC_CheckPredicate, 37, 58, 10, 0, // Skip to: 17098
+/* 14480 */ MCD::OPC_CheckField, 21, 5, 0, 51, 10, 0, // Skip to: 17098
+/* 14487 */ MCD::OPC_Decode, 172, 16, 186, 2, // Opcode: PRECEQU_PH_QBL
+/* 14492 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 14514
+/* 14497 */ MCD::OPC_CheckPredicate, 37, 36, 10, 0, // Skip to: 17098
+/* 14502 */ MCD::OPC_CheckField, 21, 5, 0, 29, 10, 0, // Skip to: 17098
+/* 14509 */ MCD::OPC_Decode, 176, 16, 186, 2, // Opcode: PRECEQU_PH_QBR
+/* 14514 */ MCD::OPC_FilterValue, 6, 17, 0, 0, // Skip to: 14536
+/* 14519 */ MCD::OPC_CheckPredicate, 37, 14, 10, 0, // Skip to: 17098
+/* 14524 */ MCD::OPC_CheckField, 21, 5, 0, 7, 10, 0, // Skip to: 17098
+/* 14531 */ MCD::OPC_Decode, 173, 16, 186, 2, // Opcode: PRECEQU_PH_QBLA
+/* 14536 */ MCD::OPC_FilterValue, 7, 17, 0, 0, // Skip to: 14558
+/* 14541 */ MCD::OPC_CheckPredicate, 37, 248, 9, 0, // Skip to: 17098
+/* 14546 */ MCD::OPC_CheckField, 21, 5, 0, 241, 9, 0, // Skip to: 17098
+/* 14553 */ MCD::OPC_Decode, 177, 16, 186, 2, // Opcode: PRECEQU_PH_QBRA
+/* 14558 */ MCD::OPC_FilterValue, 9, 17, 0, 0, // Skip to: 14580
+/* 14563 */ MCD::OPC_CheckPredicate, 37, 226, 9, 0, // Skip to: 17098
+/* 14568 */ MCD::OPC_CheckField, 21, 5, 0, 219, 9, 0, // Skip to: 17098
+/* 14575 */ MCD::OPC_Decode, 255, 3, 186, 2, // Opcode: ABSQ_S_PH
+/* 14580 */ MCD::OPC_FilterValue, 10, 9, 0, 0, // Skip to: 14594
+/* 14585 */ MCD::OPC_CheckPredicate, 37, 204, 9, 0, // Skip to: 17098
+/* 14590 */ MCD::OPC_Decode, 234, 16, 84, // Opcode: REPL_PH
+/* 14594 */ MCD::OPC_FilterValue, 11, 17, 0, 0, // Skip to: 14616
+/* 14599 */ MCD::OPC_CheckPredicate, 37, 190, 9, 0, // Skip to: 17098
+/* 14604 */ MCD::OPC_CheckField, 21, 5, 0, 183, 9, 0, // Skip to: 17098
+/* 14611 */ MCD::OPC_Decode, 230, 16, 188, 2, // Opcode: REPLV_PH
+/* 14616 */ MCD::OPC_FilterValue, 12, 17, 0, 0, // Skip to: 14638
+/* 14621 */ MCD::OPC_CheckPredicate, 37, 168, 9, 0, // Skip to: 17098
+/* 14626 */ MCD::OPC_CheckField, 21, 5, 0, 161, 9, 0, // Skip to: 17098
+/* 14633 */ MCD::OPC_Decode, 180, 16, 189, 2, // Opcode: PRECEQ_W_PHL
+/* 14638 */ MCD::OPC_FilterValue, 13, 17, 0, 0, // Skip to: 14660
+/* 14643 */ MCD::OPC_CheckPredicate, 37, 146, 9, 0, // Skip to: 17098
+/* 14648 */ MCD::OPC_CheckField, 21, 5, 0, 139, 9, 0, // Skip to: 17098
+/* 14655 */ MCD::OPC_Decode, 182, 16, 189, 2, // Opcode: PRECEQ_W_PHR
+/* 14660 */ MCD::OPC_FilterValue, 17, 17, 0, 0, // Skip to: 14682
+/* 14665 */ MCD::OPC_CheckPredicate, 37, 124, 9, 0, // Skip to: 17098
+/* 14670 */ MCD::OPC_CheckField, 21, 5, 0, 117, 9, 0, // Skip to: 17098
+/* 14677 */ MCD::OPC_Decode, 131, 4, 190, 2, // Opcode: ABSQ_S_W
+/* 14682 */ MCD::OPC_FilterValue, 27, 17, 0, 0, // Skip to: 14704
+/* 14687 */ MCD::OPC_CheckPredicate, 37, 102, 9, 0, // Skip to: 17098
+/* 14692 */ MCD::OPC_CheckField, 21, 5, 0, 95, 9, 0, // Skip to: 17098
+/* 14699 */ MCD::OPC_Decode, 231, 5, 190, 2, // Opcode: BITREV
+/* 14704 */ MCD::OPC_FilterValue, 28, 17, 0, 0, // Skip to: 14726
+/* 14709 */ MCD::OPC_CheckPredicate, 37, 80, 9, 0, // Skip to: 17098
+/* 14714 */ MCD::OPC_CheckField, 21, 5, 0, 73, 9, 0, // Skip to: 17098
+/* 14721 */ MCD::OPC_Decode, 184, 16, 186, 2, // Opcode: PRECEU_PH_QBL
+/* 14726 */ MCD::OPC_FilterValue, 29, 17, 0, 0, // Skip to: 14748
+/* 14731 */ MCD::OPC_CheckPredicate, 37, 58, 9, 0, // Skip to: 17098
+/* 14736 */ MCD::OPC_CheckField, 21, 5, 0, 51, 9, 0, // Skip to: 17098
+/* 14743 */ MCD::OPC_Decode, 188, 16, 186, 2, // Opcode: PRECEU_PH_QBR
+/* 14748 */ MCD::OPC_FilterValue, 30, 17, 0, 0, // Skip to: 14770
+/* 14753 */ MCD::OPC_CheckPredicate, 37, 36, 9, 0, // Skip to: 17098
+/* 14758 */ MCD::OPC_CheckField, 21, 5, 0, 29, 9, 0, // Skip to: 17098
+/* 14765 */ MCD::OPC_Decode, 185, 16, 186, 2, // Opcode: PRECEU_PH_QBLA
+/* 14770 */ MCD::OPC_FilterValue, 31, 19, 9, 0, // Skip to: 17098
+/* 14775 */ MCD::OPC_CheckPredicate, 37, 14, 9, 0, // Skip to: 17098
+/* 14780 */ MCD::OPC_CheckField, 21, 5, 0, 7, 9, 0, // Skip to: 17098
+/* 14787 */ MCD::OPC_Decode, 189, 16, 186, 2, // Opcode: PRECEU_PH_QBRA
+/* 14792 */ MCD::OPC_FilterValue, 19, 75, 1, 0, // Skip to: 15128
+/* 14797 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 14800 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14815
+/* 14805 */ MCD::OPC_CheckPredicate, 37, 240, 8, 0, // Skip to: 17098
+/* 14810 */ MCD::OPC_Decode, 233, 17, 191, 2, // Opcode: SHLL_QB
+/* 14815 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 14830
+/* 14820 */ MCD::OPC_CheckPredicate, 37, 225, 8, 0, // Skip to: 17098
+/* 14825 */ MCD::OPC_Decode, 137, 18, 191, 2, // Opcode: SHRL_QB
+/* 14830 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 14845
+/* 14835 */ MCD::OPC_CheckPredicate, 37, 210, 8, 0, // Skip to: 17098
+/* 14840 */ MCD::OPC_Decode, 225, 17, 192, 2, // Opcode: SHLLV_QB
+/* 14845 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 14860
+/* 14850 */ MCD::OPC_CheckPredicate, 37, 195, 8, 0, // Skip to: 17098
+/* 14855 */ MCD::OPC_Decode, 133, 18, 192, 2, // Opcode: SHRLV_QB
+/* 14860 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 14875
+/* 14865 */ MCD::OPC_CheckPredicate, 68, 180, 8, 0, // Skip to: 17098
+/* 14870 */ MCD::OPC_Decode, 251, 17, 191, 2, // Opcode: SHRA_QB
+/* 14875 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 14890
+/* 14880 */ MCD::OPC_CheckPredicate, 68, 165, 8, 0, // Skip to: 17098
+/* 14885 */ MCD::OPC_Decode, 255, 17, 191, 2, // Opcode: SHRA_R_QB
+/* 14890 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 14905
+/* 14895 */ MCD::OPC_CheckPredicate, 68, 150, 8, 0, // Skip to: 17098
+/* 14900 */ MCD::OPC_Decode, 241, 17, 192, 2, // Opcode: SHRAV_QB
+/* 14905 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 14920
+/* 14910 */ MCD::OPC_CheckPredicate, 68, 135, 8, 0, // Skip to: 17098
+/* 14915 */ MCD::OPC_Decode, 245, 17, 192, 2, // Opcode: SHRAV_R_QB
+/* 14920 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 14935
+/* 14925 */ MCD::OPC_CheckPredicate, 37, 120, 8, 0, // Skip to: 17098
+/* 14930 */ MCD::OPC_Decode, 231, 17, 191, 2, // Opcode: SHLL_PH
+/* 14935 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 14950
+/* 14940 */ MCD::OPC_CheckPredicate, 37, 105, 8, 0, // Skip to: 17098
+/* 14945 */ MCD::OPC_Decode, 249, 17, 191, 2, // Opcode: SHRA_PH
+/* 14950 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 14965
+/* 14955 */ MCD::OPC_CheckPredicate, 37, 90, 8, 0, // Skip to: 17098
+/* 14960 */ MCD::OPC_Decode, 223, 17, 192, 2, // Opcode: SHLLV_PH
+/* 14965 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 14980
+/* 14970 */ MCD::OPC_CheckPredicate, 37, 75, 8, 0, // Skip to: 17098
+/* 14975 */ MCD::OPC_Decode, 239, 17, 192, 2, // Opcode: SHRAV_PH
+/* 14980 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 14995
+/* 14985 */ MCD::OPC_CheckPredicate, 37, 60, 8, 0, // Skip to: 17098
+/* 14990 */ MCD::OPC_Decode, 235, 17, 191, 2, // Opcode: SHLL_S_PH
+/* 14995 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 15010
+/* 15000 */ MCD::OPC_CheckPredicate, 37, 45, 8, 0, // Skip to: 17098
+/* 15005 */ MCD::OPC_Decode, 253, 17, 191, 2, // Opcode: SHRA_R_PH
+/* 15010 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 15025
+/* 15015 */ MCD::OPC_CheckPredicate, 37, 30, 8, 0, // Skip to: 17098
+/* 15020 */ MCD::OPC_Decode, 227, 17, 192, 2, // Opcode: SHLLV_S_PH
+/* 15025 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 15040
+/* 15030 */ MCD::OPC_CheckPredicate, 37, 15, 8, 0, // Skip to: 17098
+/* 15035 */ MCD::OPC_Decode, 243, 17, 192, 2, // Opcode: SHRAV_R_PH
+/* 15040 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 15055
+/* 15045 */ MCD::OPC_CheckPredicate, 37, 0, 8, 0, // Skip to: 17098
+/* 15050 */ MCD::OPC_Decode, 237, 17, 193, 2, // Opcode: SHLL_S_W
+/* 15055 */ MCD::OPC_FilterValue, 21, 10, 0, 0, // Skip to: 15070
+/* 15060 */ MCD::OPC_CheckPredicate, 37, 241, 7, 0, // Skip to: 17098
+/* 15065 */ MCD::OPC_Decode, 129, 18, 193, 2, // Opcode: SHRA_R_W
+/* 15070 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 15084
+/* 15075 */ MCD::OPC_CheckPredicate, 37, 226, 7, 0, // Skip to: 17098
+/* 15080 */ MCD::OPC_Decode, 229, 17, 43, // Opcode: SHLLV_S_W
+/* 15084 */ MCD::OPC_FilterValue, 23, 9, 0, 0, // Skip to: 15098
+/* 15089 */ MCD::OPC_CheckPredicate, 37, 212, 7, 0, // Skip to: 17098
+/* 15094 */ MCD::OPC_Decode, 247, 17, 43, // Opcode: SHRAV_R_W
+/* 15098 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 15113
+/* 15103 */ MCD::OPC_CheckPredicate, 68, 198, 7, 0, // Skip to: 17098
+/* 15108 */ MCD::OPC_Decode, 135, 18, 191, 2, // Opcode: SHRL_PH
+/* 15113 */ MCD::OPC_FilterValue, 27, 188, 7, 0, // Skip to: 17098
+/* 15118 */ MCD::OPC_CheckPredicate, 68, 183, 7, 0, // Skip to: 17098
+/* 15123 */ MCD::OPC_Decode, 131, 18, 192, 2, // Opcode: SHRLV_PH
+/* 15128 */ MCD::OPC_FilterValue, 24, 237, 0, 0, // Skip to: 15370
+/* 15133 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 15136 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 15151
+/* 15141 */ MCD::OPC_CheckPredicate, 68, 160, 7, 0, // Skip to: 17098
+/* 15146 */ MCD::OPC_Decode, 172, 4, 181, 2, // Opcode: ADDUH_QB
+/* 15151 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 15166
+/* 15156 */ MCD::OPC_CheckPredicate, 68, 145, 7, 0, // Skip to: 17098
+/* 15161 */ MCD::OPC_Decode, 142, 19, 181, 2, // Opcode: SUBUH_QB
+/* 15166 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 15181
+/* 15171 */ MCD::OPC_CheckPredicate, 68, 130, 7, 0, // Skip to: 17098
+/* 15176 */ MCD::OPC_Decode, 174, 4, 181, 2, // Opcode: ADDUH_R_QB
+/* 15181 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 15196
+/* 15186 */ MCD::OPC_CheckPredicate, 68, 115, 7, 0, // Skip to: 17098
+/* 15191 */ MCD::OPC_Decode, 144, 19, 181, 2, // Opcode: SUBUH_R_QB
+/* 15196 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 15211
+/* 15201 */ MCD::OPC_CheckPredicate, 68, 100, 7, 0, // Skip to: 17098
+/* 15206 */ MCD::OPC_Decode, 142, 4, 181, 2, // Opcode: ADDQH_PH
+/* 15211 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 15226
+/* 15216 */ MCD::OPC_CheckPredicate, 68, 85, 7, 0, // Skip to: 17098
+/* 15221 */ MCD::OPC_Decode, 238, 18, 181, 2, // Opcode: SUBQH_PH
+/* 15226 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 15241
+/* 15231 */ MCD::OPC_CheckPredicate, 68, 70, 7, 0, // Skip to: 17098
+/* 15236 */ MCD::OPC_Decode, 144, 4, 181, 2, // Opcode: ADDQH_R_PH
+/* 15241 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 15256
+/* 15246 */ MCD::OPC_CheckPredicate, 68, 55, 7, 0, // Skip to: 17098
+/* 15251 */ MCD::OPC_Decode, 240, 18, 181, 2, // Opcode: SUBQH_R_PH
+/* 15256 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 15271
+/* 15261 */ MCD::OPC_CheckPredicate, 68, 40, 7, 0, // Skip to: 17098
+/* 15266 */ MCD::OPC_Decode, 226, 15, 181, 2, // Opcode: MUL_PH
+/* 15271 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 15286
+/* 15276 */ MCD::OPC_CheckPredicate, 68, 25, 7, 0, // Skip to: 17098
+/* 15281 */ MCD::OPC_Decode, 231, 15, 181, 2, // Opcode: MUL_S_PH
+/* 15286 */ MCD::OPC_FilterValue, 16, 9, 0, 0, // Skip to: 15300
+/* 15291 */ MCD::OPC_CheckPredicate, 68, 10, 7, 0, // Skip to: 17098
+/* 15296 */ MCD::OPC_Decode, 148, 4, 49, // Opcode: ADDQH_W
+/* 15300 */ MCD::OPC_FilterValue, 17, 9, 0, 0, // Skip to: 15314
+/* 15305 */ MCD::OPC_CheckPredicate, 68, 252, 6, 0, // Skip to: 17098
+/* 15310 */ MCD::OPC_Decode, 244, 18, 49, // Opcode: SUBQH_W
+/* 15314 */ MCD::OPC_FilterValue, 18, 9, 0, 0, // Skip to: 15328
+/* 15319 */ MCD::OPC_CheckPredicate, 68, 238, 6, 0, // Skip to: 17098
+/* 15324 */ MCD::OPC_Decode, 146, 4, 49, // Opcode: ADDQH_R_W
+/* 15328 */ MCD::OPC_FilterValue, 19, 9, 0, 0, // Skip to: 15342
+/* 15333 */ MCD::OPC_CheckPredicate, 68, 224, 6, 0, // Skip to: 17098
+/* 15338 */ MCD::OPC_Decode, 242, 18, 49, // Opcode: SUBQH_R_W
+/* 15342 */ MCD::OPC_FilterValue, 22, 9, 0, 0, // Skip to: 15356
+/* 15347 */ MCD::OPC_CheckPredicate, 68, 210, 6, 0, // Skip to: 17098
+/* 15352 */ MCD::OPC_Decode, 202, 15, 49, // Opcode: MULQ_S_W
+/* 15356 */ MCD::OPC_FilterValue, 23, 201, 6, 0, // Skip to: 17098
+/* 15361 */ MCD::OPC_CheckPredicate, 68, 196, 6, 0, // Skip to: 17098
+/* 15366 */ MCD::OPC_Decode, 198, 15, 49, // Opcode: MULQ_RS_W
+/* 15370 */ MCD::OPC_FilterValue, 25, 17, 0, 0, // Skip to: 15392
+/* 15375 */ MCD::OPC_CheckPredicate, 69, 182, 6, 0, // Skip to: 17098
+/* 15380 */ MCD::OPC_CheckField, 6, 1, 0, 175, 6, 0, // Skip to: 17098
+/* 15387 */ MCD::OPC_Decode, 162, 13, 194, 2, // Opcode: LWLE
+/* 15392 */ MCD::OPC_FilterValue, 26, 17, 0, 0, // Skip to: 15414
+/* 15397 */ MCD::OPC_CheckPredicate, 69, 160, 6, 0, // Skip to: 17098
+/* 15402 */ MCD::OPC_CheckField, 6, 1, 0, 153, 6, 0, // Skip to: 17098
+/* 15409 */ MCD::OPC_Decode, 173, 13, 194, 2, // Opcode: LWRE
+/* 15414 */ MCD::OPC_FilterValue, 27, 17, 0, 0, // Skip to: 15436
+/* 15419 */ MCD::OPC_CheckPredicate, 44, 138, 6, 0, // Skip to: 17098
+/* 15424 */ MCD::OPC_CheckField, 6, 1, 0, 131, 6, 0, // Skip to: 17098
+/* 15431 */ MCD::OPC_Decode, 206, 6, 195, 2, // Opcode: CACHEE
+/* 15436 */ MCD::OPC_FilterValue, 28, 17, 0, 0, // Skip to: 15458
+/* 15441 */ MCD::OPC_CheckPredicate, 44, 116, 6, 0, // Skip to: 17098
+/* 15446 */ MCD::OPC_CheckField, 6, 1, 0, 109, 6, 0, // Skip to: 17098
+/* 15453 */ MCD::OPC_Decode, 149, 17, 194, 2, // Opcode: SBE
+/* 15458 */ MCD::OPC_FilterValue, 29, 17, 0, 0, // Skip to: 15480
+/* 15463 */ MCD::OPC_CheckPredicate, 44, 94, 6, 0, // Skip to: 17098
+/* 15468 */ MCD::OPC_CheckField, 6, 1, 0, 87, 6, 0, // Skip to: 17098
+/* 15475 */ MCD::OPC_Decode, 214, 17, 194, 2, // Opcode: SHE
+/* 15480 */ MCD::OPC_FilterValue, 30, 17, 0, 0, // Skip to: 15502
+/* 15485 */ MCD::OPC_CheckPredicate, 44, 72, 6, 0, // Skip to: 17098
+/* 15490 */ MCD::OPC_CheckField, 6, 1, 0, 65, 6, 0, // Skip to: 17098
+/* 15497 */ MCD::OPC_Decode, 158, 17, 194, 2, // Opcode: SCE
+/* 15502 */ MCD::OPC_FilterValue, 31, 17, 0, 0, // Skip to: 15524
+/* 15507 */ MCD::OPC_CheckPredicate, 44, 50, 6, 0, // Skip to: 17098
+/* 15512 */ MCD::OPC_CheckField, 6, 1, 0, 43, 6, 0, // Skip to: 17098
+/* 15519 */ MCD::OPC_Decode, 182, 19, 194, 2, // Opcode: SWE
+/* 15524 */ MCD::OPC_FilterValue, 32, 69, 0, 0, // Skip to: 15598
+/* 15529 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 15532 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 15554
+/* 15537 */ MCD::OPC_CheckPredicate, 28, 20, 6, 0, // Skip to: 17098
+/* 15542 */ MCD::OPC_CheckField, 21, 5, 0, 13, 6, 0, // Skip to: 17098
+/* 15549 */ MCD::OPC_Decode, 179, 20, 190, 2, // Opcode: WSBH
+/* 15554 */ MCD::OPC_FilterValue, 16, 17, 0, 0, // Skip to: 15576
+/* 15559 */ MCD::OPC_CheckPredicate, 28, 254, 5, 0, // Skip to: 17098
+/* 15564 */ MCD::OPC_CheckField, 21, 5, 0, 247, 5, 0, // Skip to: 17098
+/* 15571 */ MCD::OPC_Decode, 184, 17, 190, 2, // Opcode: SEB
+/* 15576 */ MCD::OPC_FilterValue, 24, 237, 5, 0, // Skip to: 17098
+/* 15581 */ MCD::OPC_CheckPredicate, 28, 232, 5, 0, // Skip to: 17098
+/* 15586 */ MCD::OPC_CheckField, 21, 5, 0, 225, 5, 0, // Skip to: 17098
+/* 15593 */ MCD::OPC_Decode, 187, 17, 190, 2, // Opcode: SEH
+/* 15598 */ MCD::OPC_FilterValue, 33, 17, 0, 0, // Skip to: 15620
+/* 15603 */ MCD::OPC_CheckPredicate, 69, 210, 5, 0, // Skip to: 17098
+/* 15608 */ MCD::OPC_CheckField, 6, 1, 0, 203, 5, 0, // Skip to: 17098
+/* 15615 */ MCD::OPC_Decode, 186, 19, 194, 2, // Opcode: SWLE
+/* 15620 */ MCD::OPC_FilterValue, 34, 17, 0, 0, // Skip to: 15642
+/* 15625 */ MCD::OPC_CheckPredicate, 69, 188, 5, 0, // Skip to: 17098
+/* 15630 */ MCD::OPC_CheckField, 6, 1, 0, 181, 5, 0, // Skip to: 17098
+/* 15637 */ MCD::OPC_Decode, 195, 19, 194, 2, // Opcode: SWRE
+/* 15642 */ MCD::OPC_FilterValue, 35, 17, 0, 0, // Skip to: 15664
+/* 15647 */ MCD::OPC_CheckPredicate, 44, 166, 5, 0, // Skip to: 17098
+/* 15652 */ MCD::OPC_CheckField, 6, 1, 0, 159, 5, 0, // Skip to: 17098
+/* 15659 */ MCD::OPC_Decode, 207, 16, 195, 2, // Opcode: PREFE
+/* 15664 */ MCD::OPC_FilterValue, 40, 17, 0, 0, // Skip to: 15686
+/* 15669 */ MCD::OPC_CheckPredicate, 44, 144, 5, 0, // Skip to: 17098
+/* 15674 */ MCD::OPC_CheckField, 6, 1, 0, 137, 5, 0, // Skip to: 17098
+/* 15681 */ MCD::OPC_Decode, 211, 12, 194, 2, // Opcode: LBuE
+/* 15686 */ MCD::OPC_FilterValue, 41, 17, 0, 0, // Skip to: 15708
+/* 15691 */ MCD::OPC_CheckPredicate, 44, 122, 5, 0, // Skip to: 17098
+/* 15696 */ MCD::OPC_CheckField, 6, 1, 0, 115, 5, 0, // Skip to: 17098
+/* 15703 */ MCD::OPC_Decode, 249, 12, 194, 2, // Opcode: LHuE
+/* 15708 */ MCD::OPC_FilterValue, 44, 17, 0, 0, // Skip to: 15730
+/* 15713 */ MCD::OPC_CheckPredicate, 44, 100, 5, 0, // Skip to: 17098
+/* 15718 */ MCD::OPC_CheckField, 6, 1, 0, 93, 5, 0, // Skip to: 17098
+/* 15725 */ MCD::OPC_Decode, 201, 12, 194, 2, // Opcode: LBE
+/* 15730 */ MCD::OPC_FilterValue, 45, 17, 0, 0, // Skip to: 15752
+/* 15735 */ MCD::OPC_CheckPredicate, 44, 78, 5, 0, // Skip to: 17098
+/* 15740 */ MCD::OPC_CheckField, 6, 1, 0, 71, 5, 0, // Skip to: 17098
+/* 15747 */ MCD::OPC_Decode, 241, 12, 194, 2, // Opcode: LHE
+/* 15752 */ MCD::OPC_FilterValue, 46, 17, 0, 0, // Skip to: 15774
+/* 15757 */ MCD::OPC_CheckPredicate, 44, 56, 5, 0, // Skip to: 17098
+/* 15762 */ MCD::OPC_CheckField, 6, 1, 0, 49, 5, 0, // Skip to: 17098
+/* 15769 */ MCD::OPC_Decode, 131, 13, 194, 2, // Opcode: LLE
+/* 15774 */ MCD::OPC_FilterValue, 47, 17, 0, 0, // Skip to: 15796
+/* 15779 */ MCD::OPC_CheckPredicate, 44, 34, 5, 0, // Skip to: 17098
+/* 15784 */ MCD::OPC_CheckField, 6, 1, 0, 27, 5, 0, // Skip to: 17098
+/* 15791 */ MCD::OPC_Decode, 157, 13, 194, 2, // Opcode: LWE
+/* 15796 */ MCD::OPC_FilterValue, 48, 231, 1, 0, // Skip to: 16288
+/* 15801 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 15804 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 15826
+/* 15809 */ MCD::OPC_CheckPredicate, 68, 4, 5, 0, // Skip to: 17098
+/* 15814 */ MCD::OPC_CheckField, 13, 3, 0, 253, 4, 0, // Skip to: 17098
+/* 15821 */ MCD::OPC_Decode, 224, 9, 229, 1, // Opcode: DPA_W_PH
+/* 15826 */ MCD::OPC_FilterValue, 1, 17, 0, 0, // Skip to: 15848
+/* 15831 */ MCD::OPC_CheckPredicate, 68, 238, 4, 0, // Skip to: 17098
+/* 15836 */ MCD::OPC_CheckField, 13, 3, 0, 231, 4, 0, // Skip to: 17098
+/* 15843 */ MCD::OPC_Decode, 247, 9, 229, 1, // Opcode: DPS_W_PH
+/* 15848 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 15870
+/* 15853 */ MCD::OPC_CheckPredicate, 68, 216, 4, 0, // Skip to: 17098
+/* 15858 */ MCD::OPC_CheckField, 13, 3, 0, 209, 4, 0, // Skip to: 17098
+/* 15865 */ MCD::OPC_Decode, 208, 15, 229, 1, // Opcode: MULSA_W_PH
+/* 15870 */ MCD::OPC_FilterValue, 3, 17, 0, 0, // Skip to: 15892
+/* 15875 */ MCD::OPC_CheckPredicate, 37, 194, 4, 0, // Skip to: 17098
+/* 15880 */ MCD::OPC_CheckField, 13, 3, 0, 187, 4, 0, // Skip to: 17098
+/* 15887 */ MCD::OPC_Decode, 218, 9, 229, 1, // Opcode: DPAU_H_QBL
+/* 15892 */ MCD::OPC_FilterValue, 4, 17, 0, 0, // Skip to: 15914
+/* 15897 */ MCD::OPC_CheckPredicate, 37, 172, 4, 0, // Skip to: 17098
+/* 15902 */ MCD::OPC_CheckField, 13, 3, 0, 165, 4, 0, // Skip to: 17098
+/* 15909 */ MCD::OPC_Decode, 216, 9, 229, 1, // Opcode: DPAQ_S_W_PH
+/* 15914 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 15936
+/* 15919 */ MCD::OPC_CheckPredicate, 37, 150, 4, 0, // Skip to: 17098
+/* 15924 */ MCD::OPC_CheckField, 13, 3, 0, 143, 4, 0, // Skip to: 17098
+/* 15931 */ MCD::OPC_Decode, 233, 9, 229, 1, // Opcode: DPSQ_S_W_PH
+/* 15936 */ MCD::OPC_FilterValue, 6, 17, 0, 0, // Skip to: 15958
+/* 15941 */ MCD::OPC_CheckPredicate, 37, 128, 4, 0, // Skip to: 17098
+/* 15946 */ MCD::OPC_CheckField, 13, 3, 0, 121, 4, 0, // Skip to: 17098
+/* 15953 */ MCD::OPC_Decode, 206, 15, 229, 1, // Opcode: MULSAQ_S_W_PH
+/* 15958 */ MCD::OPC_FilterValue, 7, 17, 0, 0, // Skip to: 15980
+/* 15963 */ MCD::OPC_CheckPredicate, 37, 106, 4, 0, // Skip to: 17098
+/* 15968 */ MCD::OPC_CheckField, 13, 3, 0, 99, 4, 0, // Skip to: 17098
+/* 15975 */ MCD::OPC_Decode, 220, 9, 229, 1, // Opcode: DPAU_H_QBR
+/* 15980 */ MCD::OPC_FilterValue, 8, 17, 0, 0, // Skip to: 16002
+/* 15985 */ MCD::OPC_CheckPredicate, 68, 84, 4, 0, // Skip to: 17098
+/* 15990 */ MCD::OPC_CheckField, 13, 3, 0, 77, 4, 0, // Skip to: 17098
+/* 15997 */ MCD::OPC_Decode, 222, 9, 229, 1, // Opcode: DPAX_W_PH
+/* 16002 */ MCD::OPC_FilterValue, 9, 17, 0, 0, // Skip to: 16024
+/* 16007 */ MCD::OPC_CheckPredicate, 68, 62, 4, 0, // Skip to: 17098
+/* 16012 */ MCD::OPC_CheckField, 13, 3, 0, 55, 4, 0, // Skip to: 17098
+/* 16019 */ MCD::OPC_Decode, 245, 9, 229, 1, // Opcode: DPSX_W_PH
+/* 16024 */ MCD::OPC_FilterValue, 11, 17, 0, 0, // Skip to: 16046
+/* 16029 */ MCD::OPC_CheckPredicate, 37, 40, 4, 0, // Skip to: 17098
+/* 16034 */ MCD::OPC_CheckField, 13, 3, 0, 33, 4, 0, // Skip to: 17098
+/* 16041 */ MCD::OPC_Decode, 241, 9, 229, 1, // Opcode: DPSU_H_QBL
+/* 16046 */ MCD::OPC_FilterValue, 12, 17, 0, 0, // Skip to: 16068
+/* 16051 */ MCD::OPC_CheckPredicate, 37, 18, 4, 0, // Skip to: 17098
+/* 16056 */ MCD::OPC_CheckField, 13, 3, 0, 11, 4, 0, // Skip to: 17098
+/* 16063 */ MCD::OPC_Decode, 214, 9, 229, 1, // Opcode: DPAQ_SA_L_W
+/* 16068 */ MCD::OPC_FilterValue, 13, 17, 0, 0, // Skip to: 16090
+/* 16073 */ MCD::OPC_CheckPredicate, 37, 252, 3, 0, // Skip to: 17098
+/* 16078 */ MCD::OPC_CheckField, 13, 3, 0, 245, 3, 0, // Skip to: 17098
+/* 16085 */ MCD::OPC_Decode, 231, 9, 229, 1, // Opcode: DPSQ_SA_L_W
+/* 16090 */ MCD::OPC_FilterValue, 15, 17, 0, 0, // Skip to: 16112
+/* 16095 */ MCD::OPC_CheckPredicate, 37, 230, 3, 0, // Skip to: 17098
+/* 16100 */ MCD::OPC_CheckField, 13, 3, 0, 223, 3, 0, // Skip to: 17098
+/* 16107 */ MCD::OPC_Decode, 243, 9, 229, 1, // Opcode: DPSU_H_QBR
+/* 16112 */ MCD::OPC_FilterValue, 16, 17, 0, 0, // Skip to: 16134
+/* 16117 */ MCD::OPC_CheckPredicate, 37, 208, 3, 0, // Skip to: 17098
+/* 16122 */ MCD::OPC_CheckField, 13, 3, 0, 201, 3, 0, // Skip to: 17098
+/* 16129 */ MCD::OPC_Decode, 223, 13, 229, 1, // Opcode: MAQ_SA_W_PHL
+/* 16134 */ MCD::OPC_FilterValue, 18, 17, 0, 0, // Skip to: 16156
+/* 16139 */ MCD::OPC_CheckPredicate, 37, 186, 3, 0, // Skip to: 17098
+/* 16144 */ MCD::OPC_CheckField, 13, 3, 0, 179, 3, 0, // Skip to: 17098
+/* 16151 */ MCD::OPC_Decode, 225, 13, 229, 1, // Opcode: MAQ_SA_W_PHR
+/* 16156 */ MCD::OPC_FilterValue, 20, 17, 0, 0, // Skip to: 16178
+/* 16161 */ MCD::OPC_CheckPredicate, 37, 164, 3, 0, // Skip to: 17098
+/* 16166 */ MCD::OPC_CheckField, 13, 3, 0, 157, 3, 0, // Skip to: 17098
+/* 16173 */ MCD::OPC_Decode, 227, 13, 229, 1, // Opcode: MAQ_S_W_PHL
+/* 16178 */ MCD::OPC_FilterValue, 22, 17, 0, 0, // Skip to: 16200
+/* 16183 */ MCD::OPC_CheckPredicate, 37, 142, 3, 0, // Skip to: 17098
+/* 16188 */ MCD::OPC_CheckField, 13, 3, 0, 135, 3, 0, // Skip to: 17098
+/* 16195 */ MCD::OPC_Decode, 229, 13, 229, 1, // Opcode: MAQ_S_W_PHR
+/* 16200 */ MCD::OPC_FilterValue, 24, 17, 0, 0, // Skip to: 16222
+/* 16205 */ MCD::OPC_CheckPredicate, 68, 120, 3, 0, // Skip to: 17098
+/* 16210 */ MCD::OPC_CheckField, 13, 3, 0, 113, 3, 0, // Skip to: 17098
+/* 16217 */ MCD::OPC_Decode, 212, 9, 229, 1, // Opcode: DPAQX_S_W_PH
+/* 16222 */ MCD::OPC_FilterValue, 25, 17, 0, 0, // Skip to: 16244
+/* 16227 */ MCD::OPC_CheckPredicate, 68, 98, 3, 0, // Skip to: 17098
+/* 16232 */ MCD::OPC_CheckField, 13, 3, 0, 91, 3, 0, // Skip to: 17098
+/* 16239 */ MCD::OPC_Decode, 229, 9, 229, 1, // Opcode: DPSQX_S_W_PH
+/* 16244 */ MCD::OPC_FilterValue, 26, 17, 0, 0, // Skip to: 16266
+/* 16249 */ MCD::OPC_CheckPredicate, 68, 76, 3, 0, // Skip to: 17098
+/* 16254 */ MCD::OPC_CheckField, 13, 3, 0, 69, 3, 0, // Skip to: 17098
+/* 16261 */ MCD::OPC_Decode, 210, 9, 229, 1, // Opcode: DPAQX_SA_W_PH
+/* 16266 */ MCD::OPC_FilterValue, 27, 59, 3, 0, // Skip to: 17098
+/* 16271 */ MCD::OPC_CheckPredicate, 68, 54, 3, 0, // Skip to: 17098
+/* 16276 */ MCD::OPC_CheckField, 13, 3, 0, 47, 3, 0, // Skip to: 17098
+/* 16283 */ MCD::OPC_Decode, 227, 9, 229, 1, // Opcode: DPSQX_SA_W_PH
+/* 16288 */ MCD::OPC_FilterValue, 49, 48, 0, 0, // Skip to: 16341
+/* 16293 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 16296 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16311
+/* 16301 */ MCD::OPC_CheckPredicate, 68, 24, 3, 0, // Skip to: 17098
+/* 16306 */ MCD::OPC_Decode, 225, 4, 196, 2, // Opcode: APPEND
+/* 16311 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 16326
+/* 16316 */ MCD::OPC_CheckPredicate, 68, 9, 3, 0, // Skip to: 17098
+/* 16321 */ MCD::OPC_Decode, 213, 16, 196, 2, // Opcode: PREPEND
+/* 16326 */ MCD::OPC_FilterValue, 16, 255, 2, 0, // Skip to: 17098
+/* 16331 */ MCD::OPC_CheckPredicate, 68, 250, 2, 0, // Skip to: 17098
+/* 16336 */ MCD::OPC_Decode, 141, 5, 196, 2, // Opcode: BALIGN
+/* 16341 */ MCD::OPC_FilterValue, 56, 107, 1, 0, // Skip to: 16709
+/* 16346 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 16349 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16371
+/* 16354 */ MCD::OPC_CheckPredicate, 37, 227, 2, 0, // Skip to: 17098
+/* 16359 */ MCD::OPC_CheckField, 13, 3, 0, 220, 2, 0, // Skip to: 17098
+/* 16366 */ MCD::OPC_Decode, 183, 10, 197, 2, // Opcode: EXTR_W
+/* 16371 */ MCD::OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16393
+/* 16376 */ MCD::OPC_CheckPredicate, 37, 205, 2, 0, // Skip to: 17098
+/* 16381 */ MCD::OPC_CheckField, 13, 3, 0, 198, 2, 0, // Skip to: 17098
+/* 16388 */ MCD::OPC_Decode, 175, 10, 198, 2, // Opcode: EXTRV_W
+/* 16393 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16415
+/* 16398 */ MCD::OPC_CheckPredicate, 37, 183, 2, 0, // Skip to: 17098
+/* 16403 */ MCD::OPC_CheckField, 13, 3, 0, 176, 2, 0, // Skip to: 17098
+/* 16410 */ MCD::OPC_Decode, 161, 10, 197, 2, // Opcode: EXTP
+/* 16415 */ MCD::OPC_FilterValue, 3, 17, 0, 0, // Skip to: 16437
+/* 16420 */ MCD::OPC_CheckPredicate, 37, 161, 2, 0, // Skip to: 17098
+/* 16425 */ MCD::OPC_CheckField, 13, 3, 0, 154, 2, 0, // Skip to: 17098
+/* 16432 */ MCD::OPC_Decode, 166, 10, 198, 2, // Opcode: EXTPV
+/* 16437 */ MCD::OPC_FilterValue, 4, 17, 0, 0, // Skip to: 16459
+/* 16442 */ MCD::OPC_CheckPredicate, 37, 139, 2, 0, // Skip to: 17098
+/* 16447 */ MCD::OPC_CheckField, 13, 3, 0, 132, 2, 0, // Skip to: 17098
+/* 16454 */ MCD::OPC_Decode, 179, 10, 197, 2, // Opcode: EXTR_R_W
+/* 16459 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 16481
+/* 16464 */ MCD::OPC_CheckPredicate, 37, 117, 2, 0, // Skip to: 17098
+/* 16469 */ MCD::OPC_CheckField, 13, 3, 0, 110, 2, 0, // Skip to: 17098
+/* 16476 */ MCD::OPC_Decode, 171, 10, 198, 2, // Opcode: EXTRV_R_W
+/* 16481 */ MCD::OPC_FilterValue, 6, 17, 0, 0, // Skip to: 16503
+/* 16486 */ MCD::OPC_CheckPredicate, 37, 95, 2, 0, // Skip to: 17098
+/* 16491 */ MCD::OPC_CheckField, 13, 3, 0, 88, 2, 0, // Skip to: 17098
+/* 16498 */ MCD::OPC_Decode, 177, 10, 197, 2, // Opcode: EXTR_RS_W
+/* 16503 */ MCD::OPC_FilterValue, 7, 17, 0, 0, // Skip to: 16525
+/* 16508 */ MCD::OPC_CheckPredicate, 37, 73, 2, 0, // Skip to: 17098
+/* 16513 */ MCD::OPC_CheckField, 13, 3, 0, 66, 2, 0, // Skip to: 17098
+/* 16520 */ MCD::OPC_Decode, 169, 10, 198, 2, // Opcode: EXTRV_RS_W
+/* 16525 */ MCD::OPC_FilterValue, 10, 17, 0, 0, // Skip to: 16547
+/* 16530 */ MCD::OPC_CheckPredicate, 37, 51, 2, 0, // Skip to: 17098
+/* 16535 */ MCD::OPC_CheckField, 13, 3, 0, 44, 2, 0, // Skip to: 17098
+/* 16542 */ MCD::OPC_Decode, 162, 10, 197, 2, // Opcode: EXTPDP
+/* 16547 */ MCD::OPC_FilterValue, 11, 17, 0, 0, // Skip to: 16569
+/* 16552 */ MCD::OPC_CheckPredicate, 37, 29, 2, 0, // Skip to: 17098
+/* 16557 */ MCD::OPC_CheckField, 13, 3, 0, 22, 2, 0, // Skip to: 17098
+/* 16564 */ MCD::OPC_Decode, 163, 10, 198, 2, // Opcode: EXTPDPV
+/* 16569 */ MCD::OPC_FilterValue, 14, 17, 0, 0, // Skip to: 16591
+/* 16574 */ MCD::OPC_CheckPredicate, 37, 7, 2, 0, // Skip to: 17098
+/* 16579 */ MCD::OPC_CheckField, 13, 3, 0, 0, 2, 0, // Skip to: 17098
+/* 16586 */ MCD::OPC_Decode, 181, 10, 197, 2, // Opcode: EXTR_S_H
+/* 16591 */ MCD::OPC_FilterValue, 15, 17, 0, 0, // Skip to: 16613
+/* 16596 */ MCD::OPC_CheckPredicate, 37, 241, 1, 0, // Skip to: 17098
+/* 16601 */ MCD::OPC_CheckField, 13, 3, 0, 234, 1, 0, // Skip to: 17098
+/* 16608 */ MCD::OPC_Decode, 173, 10, 198, 2, // Opcode: EXTRV_S_H
+/* 16613 */ MCD::OPC_FilterValue, 18, 10, 0, 0, // Skip to: 16628
+/* 16618 */ MCD::OPC_CheckPredicate, 37, 219, 1, 0, // Skip to: 17098
+/* 16623 */ MCD::OPC_Decode, 217, 16, 199, 2, // Opcode: RDDSP
+/* 16628 */ MCD::OPC_FilterValue, 19, 10, 0, 0, // Skip to: 16643
+/* 16633 */ MCD::OPC_CheckPredicate, 40, 204, 1, 0, // Skip to: 17098
+/* 16638 */ MCD::OPC_Decode, 176, 20, 200, 2, // Opcode: WRDSP
+/* 16643 */ MCD::OPC_FilterValue, 26, 17, 0, 0, // Skip to: 16665
+/* 16648 */ MCD::OPC_CheckPredicate, 37, 189, 1, 0, // Skip to: 17098
+/* 16653 */ MCD::OPC_CheckField, 13, 7, 0, 182, 1, 0, // Skip to: 17098
+/* 16660 */ MCD::OPC_Decode, 219, 17, 201, 2, // Opcode: SHILO
+/* 16665 */ MCD::OPC_FilterValue, 27, 17, 0, 0, // Skip to: 16687
+/* 16670 */ MCD::OPC_CheckPredicate, 37, 167, 1, 0, // Skip to: 17098
+/* 16675 */ MCD::OPC_CheckField, 13, 8, 0, 160, 1, 0, // Skip to: 17098
+/* 16682 */ MCD::OPC_Decode, 220, 17, 202, 2, // Opcode: SHILOV
+/* 16687 */ MCD::OPC_FilterValue, 31, 150, 1, 0, // Skip to: 17098
+/* 16692 */ MCD::OPC_CheckPredicate, 37, 145, 1, 0, // Skip to: 17098
+/* 16697 */ MCD::OPC_CheckField, 13, 8, 0, 138, 1, 0, // Skip to: 17098
+/* 16704 */ MCD::OPC_Decode, 169, 15, 202, 2, // Opcode: MTHLIP
+/* 16709 */ MCD::OPC_FilterValue, 59, 128, 1, 0, // Skip to: 17098
+/* 16714 */ MCD::OPC_CheckPredicate, 27, 123, 1, 0, // Skip to: 17098
+/* 16719 */ MCD::OPC_CheckField, 21, 5, 0, 116, 1, 0, // Skip to: 17098
+/* 16726 */ MCD::OPC_CheckField, 9, 2, 0, 109, 1, 0, // Skip to: 17098
+/* 16733 */ MCD::OPC_Decode, 219, 16, 203, 2, // Opcode: RDHWR
+/* 16738 */ MCD::OPC_FilterValue, 32, 10, 0, 0, // Skip to: 16753
+/* 16743 */ MCD::OPC_CheckPredicate, 27, 94, 1, 0, // Skip to: 17098
+/* 16748 */ MCD::OPC_Decode, 199, 12, 128, 1, // Opcode: LB
+/* 16753 */ MCD::OPC_FilterValue, 33, 10, 0, 0, // Skip to: 16768
+/* 16758 */ MCD::OPC_CheckPredicate, 27, 79, 1, 0, // Skip to: 17098
+/* 16763 */ MCD::OPC_Decode, 239, 12, 128, 1, // Opcode: LH
+/* 16768 */ MCD::OPC_FilterValue, 34, 10, 0, 0, // Skip to: 16783
+/* 16773 */ MCD::OPC_CheckPredicate, 31, 64, 1, 0, // Skip to: 17098
+/* 16778 */ MCD::OPC_Decode, 160, 13, 128, 1, // Opcode: LWL
+/* 16783 */ MCD::OPC_FilterValue, 35, 10, 0, 0, // Skip to: 16798
+/* 16788 */ MCD::OPC_CheckPredicate, 27, 49, 1, 0, // Skip to: 17098
+/* 16793 */ MCD::OPC_Decode, 146, 13, 128, 1, // Opcode: LW
+/* 16798 */ MCD::OPC_FilterValue, 36, 10, 0, 0, // Skip to: 16813
+/* 16803 */ MCD::OPC_CheckPredicate, 27, 34, 1, 0, // Skip to: 17098
+/* 16808 */ MCD::OPC_Decode, 209, 12, 128, 1, // Opcode: LBu
+/* 16813 */ MCD::OPC_FilterValue, 37, 10, 0, 0, // Skip to: 16828
+/* 16818 */ MCD::OPC_CheckPredicate, 27, 19, 1, 0, // Skip to: 17098
+/* 16823 */ MCD::OPC_Decode, 247, 12, 128, 1, // Opcode: LHu
+/* 16828 */ MCD::OPC_FilterValue, 38, 10, 0, 0, // Skip to: 16843
+/* 16833 */ MCD::OPC_CheckPredicate, 31, 4, 1, 0, // Skip to: 17098
+/* 16838 */ MCD::OPC_Decode, 171, 13, 128, 1, // Opcode: LWR
+/* 16843 */ MCD::OPC_FilterValue, 40, 10, 0, 0, // Skip to: 16858
+/* 16848 */ MCD::OPC_CheckPredicate, 27, 245, 0, 0, // Skip to: 17098
+/* 16853 */ MCD::OPC_Decode, 145, 17, 128, 1, // Opcode: SB
+/* 16858 */ MCD::OPC_FilterValue, 41, 10, 0, 0, // Skip to: 16873
+/* 16863 */ MCD::OPC_CheckPredicate, 27, 230, 0, 0, // Skip to: 17098
+/* 16868 */ MCD::OPC_Decode, 210, 17, 128, 1, // Opcode: SH
+/* 16873 */ MCD::OPC_FilterValue, 42, 10, 0, 0, // Skip to: 16888
+/* 16878 */ MCD::OPC_CheckPredicate, 31, 215, 0, 0, // Skip to: 17098
+/* 16883 */ MCD::OPC_Decode, 184, 19, 128, 1, // Opcode: SWL
+/* 16888 */ MCD::OPC_FilterValue, 43, 10, 0, 0, // Skip to: 16903
+/* 16893 */ MCD::OPC_CheckPredicate, 27, 200, 0, 0, // Skip to: 17098
+/* 16898 */ MCD::OPC_Decode, 170, 19, 128, 1, // Opcode: SW
+/* 16903 */ MCD::OPC_FilterValue, 46, 10, 0, 0, // Skip to: 16918
+/* 16908 */ MCD::OPC_CheckPredicate, 31, 185, 0, 0, // Skip to: 17098
+/* 16913 */ MCD::OPC_Decode, 193, 19, 128, 1, // Opcode: SWR
+/* 16918 */ MCD::OPC_FilterValue, 47, 10, 0, 0, // Skip to: 16933
+/* 16923 */ MCD::OPC_CheckPredicate, 70, 170, 0, 0, // Skip to: 17098
+/* 16928 */ MCD::OPC_Decode, 205, 6, 204, 2, // Opcode: CACHE
+/* 16933 */ MCD::OPC_FilterValue, 48, 10, 0, 0, // Skip to: 16948
+/* 16938 */ MCD::OPC_CheckPredicate, 71, 155, 0, 0, // Skip to: 17098
+/* 16943 */ MCD::OPC_Decode, 254, 12, 128, 1, // Opcode: LL
+/* 16948 */ MCD::OPC_FilterValue, 49, 10, 0, 0, // Skip to: 16963
+/* 16953 */ MCD::OPC_CheckPredicate, 47, 140, 0, 0, // Skip to: 17098
+/* 16958 */ MCD::OPC_Decode, 149, 13, 205, 2, // Opcode: LWC1
+/* 16963 */ MCD::OPC_FilterValue, 50, 10, 0, 0, // Skip to: 16978
+/* 16968 */ MCD::OPC_CheckPredicate, 31, 125, 0, 0, // Skip to: 17098
+/* 16973 */ MCD::OPC_Decode, 151, 13, 206, 2, // Opcode: LWC2
+/* 16978 */ MCD::OPC_FilterValue, 51, 10, 0, 0, // Skip to: 16993
+/* 16983 */ MCD::OPC_CheckPredicate, 70, 110, 0, 0, // Skip to: 17098
+/* 16988 */ MCD::OPC_Decode, 206, 16, 204, 2, // Opcode: PREF
+/* 16993 */ MCD::OPC_FilterValue, 53, 10, 0, 0, // Skip to: 17008
+/* 16998 */ MCD::OPC_CheckPredicate, 56, 95, 0, 0, // Skip to: 17098
+/* 17003 */ MCD::OPC_Decode, 215, 12, 205, 2, // Opcode: LDC1
+/* 17008 */ MCD::OPC_FilterValue, 54, 10, 0, 0, // Skip to: 17023
+/* 17013 */ MCD::OPC_CheckPredicate, 39, 80, 0, 0, // Skip to: 17098
+/* 17018 */ MCD::OPC_Decode, 219, 12, 206, 2, // Opcode: LDC2
+/* 17023 */ MCD::OPC_FilterValue, 56, 10, 0, 0, // Skip to: 17038
+/* 17028 */ MCD::OPC_CheckPredicate, 71, 65, 0, 0, // Skip to: 17098
+/* 17033 */ MCD::OPC_Decode, 153, 17, 128, 1, // Opcode: SC
+/* 17038 */ MCD::OPC_FilterValue, 57, 10, 0, 0, // Skip to: 17053
+/* 17043 */ MCD::OPC_CheckPredicate, 47, 50, 0, 0, // Skip to: 17098
+/* 17048 */ MCD::OPC_Decode, 174, 19, 205, 2, // Opcode: SWC1
+/* 17053 */ MCD::OPC_FilterValue, 58, 10, 0, 0, // Skip to: 17068
+/* 17058 */ MCD::OPC_CheckPredicate, 31, 35, 0, 0, // Skip to: 17098
+/* 17063 */ MCD::OPC_Decode, 176, 19, 206, 2, // Opcode: SWC2
+/* 17068 */ MCD::OPC_FilterValue, 61, 10, 0, 0, // Skip to: 17083
+/* 17073 */ MCD::OPC_CheckPredicate, 56, 20, 0, 0, // Skip to: 17098
+/* 17078 */ MCD::OPC_Decode, 170, 17, 205, 2, // Opcode: SDC1
+/* 17083 */ MCD::OPC_FilterValue, 62, 10, 0, 0, // Skip to: 17098
+/* 17088 */ MCD::OPC_CheckPredicate, 39, 5, 0, 0, // Skip to: 17098
+/* 17093 */ MCD::OPC_Decode, 174, 17, 206, 2, // Opcode: SDC2
+/* 17098 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32_64_PTR6432[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 24
+/* 8 */ MCD::OPC_CheckPredicate, 72, 41, 0, 0, // Skip to: 54
+/* 13 */ MCD::OPC_CheckField, 0, 21, 8, 34, 0, 0, // Skip to: 54
+/* 20 */ MCD::OPC_Decode, 182, 12, 13, // Opcode: JR64
+/* 24 */ MCD::OPC_FilterValue, 48, 10, 0, 0, // Skip to: 39
+/* 29 */ MCD::OPC_CheckPredicate, 73, 20, 0, 0, // Skip to: 54
+/* 34 */ MCD::OPC_Decode, 255, 12, 128, 1, // Opcode: LL64
+/* 39 */ MCD::OPC_FilterValue, 56, 10, 0, 0, // Skip to: 54
+/* 44 */ MCD::OPC_CheckPredicate, 73, 5, 0, 0, // Skip to: 54
+/* 49 */ MCD::OPC_Decode, 154, 17, 128, 1, // Opcode: SC64
+/* 54 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32r6_64r632[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 14, 2, 0, // Skip to: 534
+/* 8 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 11 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 33
+/* 16 */ MCD::OPC_CheckPredicate, 74, 111, 9, 0, // Skip to: 2436
+/* 21 */ MCD::OPC_CheckField, 8, 3, 0, 104, 9, 0, // Skip to: 2436
+/* 28 */ MCD::OPC_Decode, 138, 13, 171, 1, // Opcode: LSA_R6
+/* 33 */ MCD::OPC_FilterValue, 9, 17, 0, 0, // Skip to: 55
+/* 38 */ MCD::OPC_CheckPredicate, 74, 89, 9, 0, // Skip to: 2436
+/* 43 */ MCD::OPC_CheckField, 6, 15, 16, 82, 9, 0, // Skip to: 2436
+/* 50 */ MCD::OPC_Decode, 190, 12, 172, 1, // Opcode: JR_HB_R6
+/* 55 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 70
+/* 60 */ MCD::OPC_CheckPredicate, 75, 67, 9, 0, // Skip to: 2436
+/* 65 */ MCD::OPC_Decode, 169, 17, 174, 1, // Opcode: SDBBP_R6
+/* 70 */ MCD::OPC_FilterValue, 16, 23, 0, 0, // Skip to: 98
+/* 75 */ MCD::OPC_CheckPredicate, 74, 52, 9, 0, // Skip to: 2436
+/* 80 */ MCD::OPC_CheckField, 16, 5, 0, 45, 9, 0, // Skip to: 2436
+/* 87 */ MCD::OPC_CheckField, 6, 5, 1, 38, 9, 0, // Skip to: 2436
+/* 94 */ MCD::OPC_Decode, 153, 7, 14, // Opcode: CLZ_R6
+/* 98 */ MCD::OPC_FilterValue, 17, 23, 0, 0, // Skip to: 126
+/* 103 */ MCD::OPC_CheckPredicate, 74, 24, 9, 0, // Skip to: 2436
+/* 108 */ MCD::OPC_CheckField, 16, 5, 0, 17, 9, 0, // Skip to: 2436
+/* 115 */ MCD::OPC_CheckField, 6, 5, 1, 10, 9, 0, // Skip to: 2436
+/* 122 */ MCD::OPC_Decode, 133, 7, 14, // Opcode: CLO_R6
+/* 126 */ MCD::OPC_FilterValue, 18, 23, 0, 0, // Skip to: 154
+/* 131 */ MCD::OPC_CheckPredicate, 76, 252, 8, 0, // Skip to: 2436
+/* 136 */ MCD::OPC_CheckField, 16, 5, 0, 245, 8, 0, // Skip to: 2436
+/* 143 */ MCD::OPC_CheckField, 6, 5, 1, 238, 8, 0, // Skip to: 2436
+/* 150 */ MCD::OPC_Decode, 148, 9, 15, // Opcode: DCLZ_R6
+/* 154 */ MCD::OPC_FilterValue, 19, 23, 0, 0, // Skip to: 182
+/* 159 */ MCD::OPC_CheckPredicate, 76, 224, 8, 0, // Skip to: 2436
+/* 164 */ MCD::OPC_CheckField, 16, 5, 0, 217, 8, 0, // Skip to: 2436
+/* 171 */ MCD::OPC_CheckField, 6, 5, 1, 210, 8, 0, // Skip to: 2436
+/* 178 */ MCD::OPC_Decode, 146, 9, 15, // Opcode: DCLO_R6
+/* 182 */ MCD::OPC_FilterValue, 21, 17, 0, 0, // Skip to: 204
+/* 187 */ MCD::OPC_CheckPredicate, 76, 196, 8, 0, // Skip to: 2436
+/* 192 */ MCD::OPC_CheckField, 8, 3, 0, 189, 8, 0, // Skip to: 2436
+/* 199 */ MCD::OPC_Decode, 177, 9, 180, 1, // Opcode: DLSA_R6
+/* 204 */ MCD::OPC_FilterValue, 24, 31, 0, 0, // Skip to: 240
+/* 209 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 212 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 226
+/* 217 */ MCD::OPC_CheckPredicate, 75, 166, 8, 0, // Skip to: 2436
+/* 222 */ MCD::OPC_Decode, 230, 15, 49, // Opcode: MUL_R6
+/* 226 */ MCD::OPC_FilterValue, 3, 157, 8, 0, // Skip to: 2436
+/* 231 */ MCD::OPC_CheckPredicate, 75, 152, 8, 0, // Skip to: 2436
+/* 236 */ MCD::OPC_Decode, 183, 15, 49, // Opcode: MUH
+/* 240 */ MCD::OPC_FilterValue, 25, 31, 0, 0, // Skip to: 276
+/* 245 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 248 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 262
+/* 253 */ MCD::OPC_CheckPredicate, 75, 130, 8, 0, // Skip to: 2436
+/* 258 */ MCD::OPC_Decode, 218, 15, 49, // Opcode: MULU
+/* 262 */ MCD::OPC_FilterValue, 3, 121, 8, 0, // Skip to: 2436
+/* 267 */ MCD::OPC_CheckPredicate, 75, 116, 8, 0, // Skip to: 2436
+/* 272 */ MCD::OPC_Decode, 184, 15, 49, // Opcode: MUHU
+/* 276 */ MCD::OPC_FilterValue, 26, 31, 0, 0, // Skip to: 312
+/* 281 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 284 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 298
+/* 289 */ MCD::OPC_CheckPredicate, 75, 94, 8, 0, // Skip to: 2436
+/* 294 */ MCD::OPC_Decode, 162, 9, 49, // Opcode: DIV
+/* 298 */ MCD::OPC_FilterValue, 3, 85, 8, 0, // Skip to: 2436
+/* 303 */ MCD::OPC_CheckPredicate, 75, 80, 8, 0, // Skip to: 2436
+/* 308 */ MCD::OPC_Decode, 190, 14, 49, // Opcode: MOD
+/* 312 */ MCD::OPC_FilterValue, 27, 31, 0, 0, // Skip to: 348
+/* 317 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 320 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 334
+/* 325 */ MCD::OPC_CheckPredicate, 75, 58, 8, 0, // Skip to: 2436
+/* 330 */ MCD::OPC_Decode, 163, 9, 49, // Opcode: DIVU
+/* 334 */ MCD::OPC_FilterValue, 3, 49, 8, 0, // Skip to: 2436
+/* 339 */ MCD::OPC_CheckPredicate, 75, 44, 8, 0, // Skip to: 2436
+/* 344 */ MCD::OPC_Decode, 193, 14, 49, // Opcode: MODU
+/* 348 */ MCD::OPC_FilterValue, 28, 31, 0, 0, // Skip to: 384
+/* 353 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 356 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 370
+/* 361 */ MCD::OPC_CheckPredicate, 76, 22, 8, 0, // Skip to: 2436
+/* 366 */ MCD::OPC_Decode, 197, 9, 12, // Opcode: DMUL_R6
+/* 370 */ MCD::OPC_FilterValue, 3, 13, 8, 0, // Skip to: 2436
+/* 375 */ MCD::OPC_CheckPredicate, 76, 8, 8, 0, // Skip to: 2436
+/* 380 */ MCD::OPC_Decode, 191, 9, 12, // Opcode: DMUH
+/* 384 */ MCD::OPC_FilterValue, 29, 31, 0, 0, // Skip to: 420
+/* 389 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 392 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 406
+/* 397 */ MCD::OPC_CheckPredicate, 76, 242, 7, 0, // Skip to: 2436
+/* 402 */ MCD::OPC_Decode, 196, 9, 12, // Opcode: DMULU
+/* 406 */ MCD::OPC_FilterValue, 3, 233, 7, 0, // Skip to: 2436
+/* 411 */ MCD::OPC_CheckPredicate, 76, 228, 7, 0, // Skip to: 2436
+/* 416 */ MCD::OPC_Decode, 192, 9, 12, // Opcode: DMUHU
+/* 420 */ MCD::OPC_FilterValue, 30, 31, 0, 0, // Skip to: 456
+/* 425 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 428 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 442
+/* 433 */ MCD::OPC_CheckPredicate, 76, 206, 7, 0, // Skip to: 2436
+/* 438 */ MCD::OPC_Decode, 149, 9, 12, // Opcode: DDIV
+/* 442 */ MCD::OPC_FilterValue, 3, 197, 7, 0, // Skip to: 2436
+/* 447 */ MCD::OPC_CheckPredicate, 76, 192, 7, 0, // Skip to: 2436
+/* 452 */ MCD::OPC_Decode, 183, 9, 12, // Opcode: DMOD
+/* 456 */ MCD::OPC_FilterValue, 31, 31, 0, 0, // Skip to: 492
+/* 461 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 464 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 478
+/* 469 */ MCD::OPC_CheckPredicate, 76, 170, 7, 0, // Skip to: 2436
+/* 474 */ MCD::OPC_Decode, 150, 9, 12, // Opcode: DDIVU
+/* 478 */ MCD::OPC_FilterValue, 3, 161, 7, 0, // Skip to: 2436
+/* 483 */ MCD::OPC_CheckPredicate, 76, 156, 7, 0, // Skip to: 2436
+/* 488 */ MCD::OPC_Decode, 184, 9, 12, // Opcode: DMODU
+/* 492 */ MCD::OPC_FilterValue, 53, 16, 0, 0, // Skip to: 513
+/* 497 */ MCD::OPC_CheckPredicate, 77, 142, 7, 0, // Skip to: 2436
+/* 502 */ MCD::OPC_CheckField, 6, 5, 0, 135, 7, 0, // Skip to: 2436
+/* 509 */ MCD::OPC_Decode, 190, 17, 49, // Opcode: SELEQZ
+/* 513 */ MCD::OPC_FilterValue, 55, 126, 7, 0, // Skip to: 2436
+/* 518 */ MCD::OPC_CheckPredicate, 77, 121, 7, 0, // Skip to: 2436
+/* 523 */ MCD::OPC_CheckField, 6, 5, 0, 114, 7, 0, // Skip to: 2436
+/* 530 */ MCD::OPC_Decode, 197, 17, 49, // Opcode: SELNEZ
+/* 534 */ MCD::OPC_FilterValue, 1, 55, 0, 0, // Skip to: 594
+/* 539 */ MCD::OPC_ExtractField, 16, 5, // Inst{20-16} ...
+/* 542 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 557
+/* 547 */ MCD::OPC_CheckPredicate, 76, 92, 7, 0, // Skip to: 2436
+/* 552 */ MCD::OPC_Decode, 140, 9, 207, 2, // Opcode: DAHI
+/* 557 */ MCD::OPC_FilterValue, 17, 17, 0, 0, // Skip to: 579
+/* 562 */ MCD::OPC_CheckPredicate, 74, 77, 7, 0, // Skip to: 2436
+/* 567 */ MCD::OPC_CheckField, 21, 5, 0, 70, 7, 0, // Skip to: 2436
+/* 574 */ MCD::OPC_Decode, 138, 5, 184, 1, // Opcode: BAL
+/* 579 */ MCD::OPC_FilterValue, 30, 60, 7, 0, // Skip to: 2436
+/* 584 */ MCD::OPC_CheckPredicate, 76, 55, 7, 0, // Skip to: 2436
+/* 589 */ MCD::OPC_Decode, 142, 9, 207, 2, // Opcode: DATI
+/* 594 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 609
+/* 599 */ MCD::OPC_CheckPredicate, 75, 40, 7, 0, // Skip to: 2436
+/* 604 */ MCD::OPC_Decode, 196, 5, 208, 2, // Opcode: BGEZALC
+/* 609 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 624
+/* 614 */ MCD::OPC_CheckPredicate, 75, 25, 7, 0, // Skip to: 2436
+/* 619 */ MCD::OPC_Decode, 253, 5, 209, 2, // Opcode: BLTZALC
+/* 624 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 639
+/* 629 */ MCD::OPC_CheckPredicate, 75, 10, 7, 0, // Skip to: 2436
+/* 634 */ MCD::OPC_Decode, 174, 5, 210, 2, // Opcode: BEQC
+/* 639 */ MCD::OPC_FilterValue, 15, 10, 0, 0, // Skip to: 654
+/* 644 */ MCD::OPC_CheckPredicate, 74, 251, 6, 0, // Skip to: 2436
+/* 649 */ MCD::OPC_Decode, 235, 4, 189, 1, // Opcode: AUI
+/* 654 */ MCD::OPC_FilterValue, 16, 45, 0, 0, // Skip to: 704
+/* 659 */ MCD::OPC_ExtractField, 0, 16, // Inst{15-0} ...
+/* 662 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 683
+/* 667 */ MCD::OPC_CheckPredicate, 74, 228, 6, 0, // Skip to: 2436
+/* 672 */ MCD::OPC_CheckField, 21, 5, 11, 221, 6, 0, // Skip to: 2436
+/* 679 */ MCD::OPC_Decode, 157, 10, 80, // Opcode: EVP
+/* 683 */ MCD::OPC_FilterValue, 36, 212, 6, 0, // Skip to: 2436
+/* 688 */ MCD::OPC_CheckPredicate, 74, 207, 6, 0, // Skip to: 2436
+/* 693 */ MCD::OPC_CheckField, 21, 5, 11, 200, 6, 0, // Skip to: 2436
+/* 700 */ MCD::OPC_Decode, 140, 10, 80, // Opcode: DVP
+/* 704 */ MCD::OPC_FilterValue, 17, 135, 3, 0, // Skip to: 1612
+/* 709 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 712 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 727
+/* 717 */ MCD::OPC_CheckPredicate, 78, 178, 6, 0, // Skip to: 2436
+/* 722 */ MCD::OPC_Decode, 149, 5, 211, 2, // Opcode: BC1EQZ
+/* 727 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 742
+/* 732 */ MCD::OPC_CheckPredicate, 78, 163, 6, 0, // Skip to: 2436
+/* 737 */ MCD::OPC_Decode, 154, 5, 211, 2, // Opcode: BC1NEZ
+/* 742 */ MCD::OPC_FilterValue, 16, 182, 0, 0, // Skip to: 929
+/* 747 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 750 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 765
+/* 755 */ MCD::OPC_CheckPredicate, 78, 140, 6, 0, // Skip to: 2436
+/* 760 */ MCD::OPC_Decode, 206, 17, 212, 2, // Opcode: SEL_S
+/* 765 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 780
+/* 770 */ MCD::OPC_CheckPredicate, 78, 125, 6, 0, // Skip to: 2436
+/* 775 */ MCD::OPC_Decode, 195, 17, 204, 1, // Opcode: SELEQZ_S
+/* 780 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 795
+/* 785 */ MCD::OPC_CheckPredicate, 78, 110, 6, 0, // Skip to: 2436
+/* 790 */ MCD::OPC_Decode, 202, 17, 204, 1, // Opcode: SELNEZ_S
+/* 795 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 810
+/* 800 */ MCD::OPC_CheckPredicate, 78, 95, 6, 0, // Skip to: 2436
+/* 805 */ MCD::OPC_Decode, 201, 13, 213, 2, // Opcode: MADDF_S
+/* 810 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 825
+/* 815 */ MCD::OPC_CheckPredicate, 78, 80, 6, 0, // Skip to: 2436
+/* 820 */ MCD::OPC_Decode, 252, 14, 213, 2, // Opcode: MSUBF_S
+/* 825 */ MCD::OPC_FilterValue, 26, 17, 0, 0, // Skip to: 847
+/* 830 */ MCD::OPC_CheckPredicate, 78, 65, 6, 0, // Skip to: 2436
+/* 835 */ MCD::OPC_CheckField, 16, 5, 0, 58, 6, 0, // Skip to: 2436
+/* 842 */ MCD::OPC_Decode, 240, 16, 205, 1, // Opcode: RINT_S
+/* 847 */ MCD::OPC_FilterValue, 27, 17, 0, 0, // Skip to: 869
+/* 852 */ MCD::OPC_CheckPredicate, 78, 43, 6, 0, // Skip to: 2436
+/* 857 */ MCD::OPC_CheckField, 16, 5, 0, 36, 6, 0, // Skip to: 2436
+/* 864 */ MCD::OPC_Decode, 240, 6, 205, 1, // Opcode: CLASS_S
+/* 869 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 884
+/* 874 */ MCD::OPC_CheckPredicate, 78, 21, 6, 0, // Skip to: 2436
+/* 879 */ MCD::OPC_Decode, 180, 14, 204, 1, // Opcode: MIN_S
+/* 884 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 899
+/* 889 */ MCD::OPC_CheckPredicate, 78, 6, 6, 0, // Skip to: 2436
+/* 894 */ MCD::OPC_Decode, 249, 13, 204, 1, // Opcode: MAX_S
+/* 899 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 914
+/* 904 */ MCD::OPC_CheckPredicate, 78, 247, 5, 0, // Skip to: 2436
+/* 909 */ MCD::OPC_Decode, 164, 14, 204, 1, // Opcode: MINA_S
+/* 914 */ MCD::OPC_FilterValue, 31, 237, 5, 0, // Skip to: 2436
+/* 919 */ MCD::OPC_CheckPredicate, 78, 232, 5, 0, // Skip to: 2436
+/* 924 */ MCD::OPC_Decode, 233, 13, 204, 1, // Opcode: MAXA_S
+/* 929 */ MCD::OPC_FilterValue, 17, 182, 0, 0, // Skip to: 1116
+/* 934 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 937 */ MCD::OPC_FilterValue, 16, 10, 0, 0, // Skip to: 952
+/* 942 */ MCD::OPC_CheckPredicate, 78, 209, 5, 0, // Skip to: 2436
+/* 947 */ MCD::OPC_Decode, 204, 17, 214, 2, // Opcode: SEL_D
+/* 952 */ MCD::OPC_FilterValue, 20, 10, 0, 0, // Skip to: 967
+/* 957 */ MCD::OPC_CheckPredicate, 78, 194, 5, 0, // Skip to: 2436
+/* 962 */ MCD::OPC_Decode, 192, 17, 215, 2, // Opcode: SELEQZ_D
+/* 967 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 982
+/* 972 */ MCD::OPC_CheckPredicate, 78, 179, 5, 0, // Skip to: 2436
+/* 977 */ MCD::OPC_Decode, 199, 17, 215, 2, // Opcode: SELNEZ_D
+/* 982 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 997
+/* 987 */ MCD::OPC_CheckPredicate, 78, 164, 5, 0, // Skip to: 2436
+/* 992 */ MCD::OPC_Decode, 199, 13, 214, 2, // Opcode: MADDF_D
+/* 997 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 1012
+/* 1002 */ MCD::OPC_CheckPredicate, 78, 149, 5, 0, // Skip to: 2436
+/* 1007 */ MCD::OPC_Decode, 250, 14, 214, 2, // Opcode: MSUBF_D
+/* 1012 */ MCD::OPC_FilterValue, 26, 17, 0, 0, // Skip to: 1034
+/* 1017 */ MCD::OPC_CheckPredicate, 78, 134, 5, 0, // Skip to: 2436
+/* 1022 */ MCD::OPC_CheckField, 16, 5, 0, 127, 5, 0, // Skip to: 2436
+/* 1029 */ MCD::OPC_Decode, 238, 16, 216, 1, // Opcode: RINT_D
+/* 1034 */ MCD::OPC_FilterValue, 27, 17, 0, 0, // Skip to: 1056
+/* 1039 */ MCD::OPC_CheckPredicate, 78, 112, 5, 0, // Skip to: 2436
+/* 1044 */ MCD::OPC_CheckField, 16, 5, 0, 105, 5, 0, // Skip to: 2436
+/* 1051 */ MCD::OPC_Decode, 238, 6, 216, 1, // Opcode: CLASS_D
+/* 1056 */ MCD::OPC_FilterValue, 28, 10, 0, 0, // Skip to: 1071
+/* 1061 */ MCD::OPC_CheckPredicate, 78, 90, 5, 0, // Skip to: 2436
+/* 1066 */ MCD::OPC_Decode, 178, 14, 215, 2, // Opcode: MIN_D
+/* 1071 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 1086
+/* 1076 */ MCD::OPC_CheckPredicate, 78, 75, 5, 0, // Skip to: 2436
+/* 1081 */ MCD::OPC_Decode, 247, 13, 215, 2, // Opcode: MAX_D
+/* 1086 */ MCD::OPC_FilterValue, 30, 10, 0, 0, // Skip to: 1101
+/* 1091 */ MCD::OPC_CheckPredicate, 78, 60, 5, 0, // Skip to: 2436
+/* 1096 */ MCD::OPC_Decode, 162, 14, 215, 2, // Opcode: MINA_D
+/* 1101 */ MCD::OPC_FilterValue, 31, 50, 5, 0, // Skip to: 2436
+/* 1106 */ MCD::OPC_CheckPredicate, 78, 45, 5, 0, // Skip to: 2436
+/* 1111 */ MCD::OPC_Decode, 231, 13, 215, 2, // Opcode: MAXA_D
+/* 1116 */ MCD::OPC_FilterValue, 20, 243, 0, 0, // Skip to: 1364
+/* 1121 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1124 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1139
+/* 1129 */ MCD::OPC_CheckPredicate, 78, 22, 5, 0, // Skip to: 2436
+/* 1134 */ MCD::OPC_Decode, 181, 7, 216, 2, // Opcode: CMP_F_S
+/* 1139 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1154
+/* 1144 */ MCD::OPC_CheckPredicate, 78, 7, 5, 0, // Skip to: 2436
+/* 1149 */ MCD::OPC_Decode, 240, 7, 216, 2, // Opcode: CMP_UN_S
+/* 1154 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1169
+/* 1159 */ MCD::OPC_CheckPredicate, 78, 248, 4, 0, // Skip to: 2436
+/* 1164 */ MCD::OPC_Decode, 178, 7, 216, 2, // Opcode: CMP_EQ_S
+/* 1169 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1184
+/* 1174 */ MCD::OPC_CheckPredicate, 78, 233, 4, 0, // Skip to: 2436
+/* 1179 */ MCD::OPC_Decode, 228, 7, 216, 2, // Opcode: CMP_UEQ_S
+/* 1184 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1199
+/* 1189 */ MCD::OPC_CheckPredicate, 78, 218, 4, 0, // Skip to: 2436
+/* 1194 */ MCD::OPC_Decode, 192, 7, 216, 2, // Opcode: CMP_LT_S
+/* 1199 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1214
+/* 1204 */ MCD::OPC_CheckPredicate, 78, 203, 4, 0, // Skip to: 2436
+/* 1209 */ MCD::OPC_Decode, 236, 7, 216, 2, // Opcode: CMP_ULT_S
+/* 1214 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1229
+/* 1219 */ MCD::OPC_CheckPredicate, 78, 188, 4, 0, // Skip to: 2436
+/* 1224 */ MCD::OPC_Decode, 186, 7, 216, 2, // Opcode: CMP_LE_S
+/* 1229 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1244
+/* 1234 */ MCD::OPC_CheckPredicate, 78, 173, 4, 0, // Skip to: 2436
+/* 1239 */ MCD::OPC_Decode, 232, 7, 216, 2, // Opcode: CMP_ULE_S
+/* 1244 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1259
+/* 1249 */ MCD::OPC_CheckPredicate, 78, 158, 4, 0, // Skip to: 2436
+/* 1254 */ MCD::OPC_Decode, 196, 7, 216, 2, // Opcode: CMP_SAF_S
+/* 1259 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1274
+/* 1264 */ MCD::OPC_CheckPredicate, 78, 143, 4, 0, // Skip to: 2436
+/* 1269 */ MCD::OPC_Decode, 224, 7, 216, 2, // Opcode: CMP_SUN_S
+/* 1274 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1289
+/* 1279 */ MCD::OPC_CheckPredicate, 78, 128, 4, 0, // Skip to: 2436
+/* 1284 */ MCD::OPC_Decode, 200, 7, 216, 2, // Opcode: CMP_SEQ_S
+/* 1289 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1304
+/* 1294 */ MCD::OPC_CheckPredicate, 78, 113, 4, 0, // Skip to: 2436
+/* 1299 */ MCD::OPC_Decode, 212, 7, 216, 2, // Opcode: CMP_SUEQ_S
+/* 1304 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1319
+/* 1309 */ MCD::OPC_CheckPredicate, 78, 98, 4, 0, // Skip to: 2436
+/* 1314 */ MCD::OPC_Decode, 208, 7, 216, 2, // Opcode: CMP_SLT_S
+/* 1319 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1334
+/* 1324 */ MCD::OPC_CheckPredicate, 78, 83, 4, 0, // Skip to: 2436
+/* 1329 */ MCD::OPC_Decode, 220, 7, 216, 2, // Opcode: CMP_SULT_S
+/* 1334 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1349
+/* 1339 */ MCD::OPC_CheckPredicate, 78, 68, 4, 0, // Skip to: 2436
+/* 1344 */ MCD::OPC_Decode, 204, 7, 216, 2, // Opcode: CMP_SLE_S
+/* 1349 */ MCD::OPC_FilterValue, 15, 58, 4, 0, // Skip to: 2436
+/* 1354 */ MCD::OPC_CheckPredicate, 78, 53, 4, 0, // Skip to: 2436
+/* 1359 */ MCD::OPC_Decode, 216, 7, 216, 2, // Opcode: CMP_SULE_S
+/* 1364 */ MCD::OPC_FilterValue, 21, 43, 4, 0, // Skip to: 2436
+/* 1369 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1372 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1387
+/* 1377 */ MCD::OPC_CheckPredicate, 78, 30, 4, 0, // Skip to: 2436
+/* 1382 */ MCD::OPC_Decode, 180, 7, 217, 2, // Opcode: CMP_F_D
+/* 1387 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1402
+/* 1392 */ MCD::OPC_CheckPredicate, 78, 15, 4, 0, // Skip to: 2436
+/* 1397 */ MCD::OPC_Decode, 238, 7, 217, 2, // Opcode: CMP_UN_D
+/* 1402 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1417
+/* 1407 */ MCD::OPC_CheckPredicate, 78, 0, 4, 0, // Skip to: 2436
+/* 1412 */ MCD::OPC_Decode, 174, 7, 217, 2, // Opcode: CMP_EQ_D
+/* 1417 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1432
+/* 1422 */ MCD::OPC_CheckPredicate, 78, 241, 3, 0, // Skip to: 2436
+/* 1427 */ MCD::OPC_Decode, 226, 7, 217, 2, // Opcode: CMP_UEQ_D
+/* 1432 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1447
+/* 1437 */ MCD::OPC_CheckPredicate, 78, 226, 3, 0, // Skip to: 2436
+/* 1442 */ MCD::OPC_Decode, 188, 7, 217, 2, // Opcode: CMP_LT_D
+/* 1447 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1462
+/* 1452 */ MCD::OPC_CheckPredicate, 78, 211, 3, 0, // Skip to: 2436
+/* 1457 */ MCD::OPC_Decode, 234, 7, 217, 2, // Opcode: CMP_ULT_D
+/* 1462 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1477
+/* 1467 */ MCD::OPC_CheckPredicate, 78, 196, 3, 0, // Skip to: 2436
+/* 1472 */ MCD::OPC_Decode, 182, 7, 217, 2, // Opcode: CMP_LE_D
+/* 1477 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1492
+/* 1482 */ MCD::OPC_CheckPredicate, 78, 181, 3, 0, // Skip to: 2436
+/* 1487 */ MCD::OPC_Decode, 230, 7, 217, 2, // Opcode: CMP_ULE_D
+/* 1492 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 1507
+/* 1497 */ MCD::OPC_CheckPredicate, 78, 166, 3, 0, // Skip to: 2436
+/* 1502 */ MCD::OPC_Decode, 194, 7, 217, 2, // Opcode: CMP_SAF_D
+/* 1507 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1522
+/* 1512 */ MCD::OPC_CheckPredicate, 78, 151, 3, 0, // Skip to: 2436
+/* 1517 */ MCD::OPC_Decode, 222, 7, 217, 2, // Opcode: CMP_SUN_D
+/* 1522 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1537
+/* 1527 */ MCD::OPC_CheckPredicate, 78, 136, 3, 0, // Skip to: 2436
+/* 1532 */ MCD::OPC_Decode, 198, 7, 217, 2, // Opcode: CMP_SEQ_D
+/* 1537 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1552
+/* 1542 */ MCD::OPC_CheckPredicate, 78, 121, 3, 0, // Skip to: 2436
+/* 1547 */ MCD::OPC_Decode, 210, 7, 217, 2, // Opcode: CMP_SUEQ_D
+/* 1552 */ MCD::OPC_FilterValue, 12, 10, 0, 0, // Skip to: 1567
+/* 1557 */ MCD::OPC_CheckPredicate, 78, 106, 3, 0, // Skip to: 2436
+/* 1562 */ MCD::OPC_Decode, 206, 7, 217, 2, // Opcode: CMP_SLT_D
+/* 1567 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1582
+/* 1572 */ MCD::OPC_CheckPredicate, 78, 91, 3, 0, // Skip to: 2436
+/* 1577 */ MCD::OPC_Decode, 218, 7, 217, 2, // Opcode: CMP_SULT_D
+/* 1582 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1597
+/* 1587 */ MCD::OPC_CheckPredicate, 78, 76, 3, 0, // Skip to: 2436
+/* 1592 */ MCD::OPC_Decode, 202, 7, 217, 2, // Opcode: CMP_SLE_D
+/* 1597 */ MCD::OPC_FilterValue, 15, 66, 3, 0, // Skip to: 2436
+/* 1602 */ MCD::OPC_CheckPredicate, 78, 61, 3, 0, // Skip to: 2436
+/* 1607 */ MCD::OPC_Decode, 214, 7, 217, 2, // Opcode: CMP_SULE_D
+/* 1612 */ MCD::OPC_FilterValue, 18, 93, 0, 0, // Skip to: 1710
+/* 1617 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 1620 */ MCD::OPC_FilterValue, 9, 10, 0, 0, // Skip to: 1635
+/* 1625 */ MCD::OPC_CheckPredicate, 75, 38, 3, 0, // Skip to: 2436
+/* 1630 */ MCD::OPC_Decode, 159, 5, 218, 2, // Opcode: BC2EQZ
+/* 1635 */ MCD::OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1650
+/* 1640 */ MCD::OPC_CheckPredicate, 75, 23, 3, 0, // Skip to: 2436
+/* 1645 */ MCD::OPC_Decode, 153, 13, 219, 2, // Opcode: LWC2_R6
+/* 1650 */ MCD::OPC_FilterValue, 11, 10, 0, 0, // Skip to: 1665
+/* 1655 */ MCD::OPC_CheckPredicate, 75, 8, 3, 0, // Skip to: 2436
+/* 1660 */ MCD::OPC_Decode, 178, 19, 219, 2, // Opcode: SWC2_R6
+/* 1665 */ MCD::OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1680
+/* 1670 */ MCD::OPC_CheckPredicate, 75, 249, 2, 0, // Skip to: 2436
+/* 1675 */ MCD::OPC_Decode, 161, 5, 218, 2, // Opcode: BC2NEZ
+/* 1680 */ MCD::OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1695
+/* 1685 */ MCD::OPC_CheckPredicate, 75, 234, 2, 0, // Skip to: 2436
+/* 1690 */ MCD::OPC_Decode, 221, 12, 219, 2, // Opcode: LDC2_R6
+/* 1695 */ MCD::OPC_FilterValue, 15, 224, 2, 0, // Skip to: 2436
+/* 1700 */ MCD::OPC_CheckPredicate, 75, 219, 2, 0, // Skip to: 2436
+/* 1705 */ MCD::OPC_Decode, 176, 17, 219, 2, // Opcode: SDC2_R6
+/* 1710 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 1725
+/* 1715 */ MCD::OPC_CheckPredicate, 75, 204, 2, 0, // Skip to: 2436
+/* 1720 */ MCD::OPC_Decode, 201, 5, 220, 2, // Opcode: BGEZC
+/* 1725 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 1740
+/* 1730 */ MCD::OPC_CheckPredicate, 75, 189, 2, 0, // Skip to: 2436
+/* 1735 */ MCD::OPC_Decode, 130, 6, 221, 2, // Opcode: BLTZC
+/* 1740 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 1755
+/* 1745 */ MCD::OPC_CheckPredicate, 75, 174, 2, 0, // Skip to: 2436
+/* 1750 */ MCD::OPC_Decode, 141, 6, 222, 2, // Opcode: BNEC
+/* 1755 */ MCD::OPC_FilterValue, 29, 10, 0, 0, // Skip to: 1770
+/* 1760 */ MCD::OPC_CheckPredicate, 76, 159, 2, 0, // Skip to: 2436
+/* 1765 */ MCD::OPC_Decode, 143, 9, 223, 2, // Opcode: DAUI
+/* 1770 */ MCD::OPC_FilterValue, 31, 135, 1, 0, // Skip to: 2166
+/* 1775 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1778 */ MCD::OPC_FilterValue, 15, 123, 0, 0, // Skip to: 1906
+/* 1783 */ MCD::OPC_ExtractField, 6, 10, // Inst{15-6} ...
+/* 1786 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1801
+/* 1791 */ MCD::OPC_CheckPredicate, 79, 128, 2, 0, // Skip to: 2436
+/* 1796 */ MCD::OPC_Decode, 249, 7, 224, 2, // Opcode: CRC32B
+/* 1801 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1816
+/* 1806 */ MCD::OPC_CheckPredicate, 79, 113, 2, 0, // Skip to: 2436
+/* 1811 */ MCD::OPC_Decode, 255, 7, 224, 2, // Opcode: CRC32H
+/* 1816 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1831
+/* 1821 */ MCD::OPC_CheckPredicate, 79, 98, 2, 0, // Skip to: 2436
+/* 1826 */ MCD::OPC_Decode, 128, 8, 224, 2, // Opcode: CRC32W
+/* 1831 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1846
+/* 1836 */ MCD::OPC_CheckPredicate, 80, 83, 2, 0, // Skip to: 2436
+/* 1841 */ MCD::OPC_Decode, 254, 7, 224, 2, // Opcode: CRC32D
+/* 1846 */ MCD::OPC_FilterValue, 4, 10, 0, 0, // Skip to: 1861
+/* 1851 */ MCD::OPC_CheckPredicate, 79, 68, 2, 0, // Skip to: 2436
+/* 1856 */ MCD::OPC_Decode, 250, 7, 224, 2, // Opcode: CRC32CB
+/* 1861 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1876
+/* 1866 */ MCD::OPC_CheckPredicate, 79, 53, 2, 0, // Skip to: 2436
+/* 1871 */ MCD::OPC_Decode, 252, 7, 224, 2, // Opcode: CRC32CH
+/* 1876 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1891
+/* 1881 */ MCD::OPC_CheckPredicate, 79, 38, 2, 0, // Skip to: 2436
+/* 1886 */ MCD::OPC_Decode, 253, 7, 224, 2, // Opcode: CRC32CW
+/* 1891 */ MCD::OPC_FilterValue, 7, 28, 2, 0, // Skip to: 2436
+/* 1896 */ MCD::OPC_CheckPredicate, 80, 23, 2, 0, // Skip to: 2436
+/* 1901 */ MCD::OPC_Decode, 251, 7, 224, 2, // Opcode: CRC32CD
+/* 1906 */ MCD::OPC_FilterValue, 32, 47, 0, 0, // Skip to: 1958
+/* 1911 */ MCD::OPC_ExtractField, 8, 3, // Inst{10-8} ...
+/* 1914 */ MCD::OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1943
+/* 1919 */ MCD::OPC_CheckPredicate, 74, 0, 2, 0, // Skip to: 2436
+/* 1924 */ MCD::OPC_CheckField, 21, 5, 0, 249, 1, 0, // Skip to: 2436
+/* 1931 */ MCD::OPC_CheckField, 6, 2, 0, 242, 1, 0, // Skip to: 2436
+/* 1938 */ MCD::OPC_Decode, 233, 5, 190, 2, // Opcode: BITSWAP
+/* 1943 */ MCD::OPC_FilterValue, 2, 232, 1, 0, // Skip to: 2436
+/* 1948 */ MCD::OPC_CheckPredicate, 74, 227, 1, 0, // Skip to: 2436
+/* 1953 */ MCD::OPC_Decode, 207, 4, 225, 2, // Opcode: ALIGN
+/* 1958 */ MCD::OPC_FilterValue, 36, 47, 0, 0, // Skip to: 2010
+/* 1963 */ MCD::OPC_ExtractField, 9, 2, // Inst{10-9} ...
+/* 1966 */ MCD::OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1995
+/* 1971 */ MCD::OPC_CheckPredicate, 76, 204, 1, 0, // Skip to: 2436
+/* 1976 */ MCD::OPC_CheckField, 21, 5, 0, 197, 1, 0, // Skip to: 2436
+/* 1983 */ MCD::OPC_CheckField, 6, 3, 0, 190, 1, 0, // Skip to: 2436
+/* 1990 */ MCD::OPC_Decode, 144, 9, 226, 2, // Opcode: DBITSWAP
+/* 1995 */ MCD::OPC_FilterValue, 1, 180, 1, 0, // Skip to: 2436
+/* 2000 */ MCD::OPC_CheckPredicate, 76, 175, 1, 0, // Skip to: 2436
+/* 2005 */ MCD::OPC_Decode, 141, 9, 227, 2, // Opcode: DALIGN
+/* 2010 */ MCD::OPC_FilterValue, 37, 17, 0, 0, // Skip to: 2032
+/* 2015 */ MCD::OPC_CheckPredicate, 75, 160, 1, 0, // Skip to: 2436
+/* 2020 */ MCD::OPC_CheckField, 6, 1, 0, 153, 1, 0, // Skip to: 2436
+/* 2027 */ MCD::OPC_Decode, 210, 6, 195, 2, // Opcode: CACHE_R6
+/* 2032 */ MCD::OPC_FilterValue, 38, 10, 0, 0, // Skip to: 2047
+/* 2037 */ MCD::OPC_CheckPredicate, 81, 138, 1, 0, // Skip to: 2436
+/* 2042 */ MCD::OPC_Decode, 162, 17, 228, 2, // Opcode: SC_R6
+/* 2047 */ MCD::OPC_FilterValue, 39, 10, 0, 0, // Skip to: 2062
+/* 2052 */ MCD::OPC_CheckPredicate, 74, 123, 1, 0, // Skip to: 2436
+/* 2057 */ MCD::OPC_Decode, 157, 17, 228, 2, // Opcode: SCD_R6
+/* 2062 */ MCD::OPC_FilterValue, 53, 17, 0, 0, // Skip to: 2084
+/* 2067 */ MCD::OPC_CheckPredicate, 75, 108, 1, 0, // Skip to: 2436
+/* 2072 */ MCD::OPC_CheckField, 6, 1, 0, 101, 1, 0, // Skip to: 2436
+/* 2079 */ MCD::OPC_Decode, 212, 16, 195, 2, // Opcode: PREF_R6
+/* 2084 */ MCD::OPC_FilterValue, 54, 10, 0, 0, // Skip to: 2099
+/* 2089 */ MCD::OPC_CheckPredicate, 81, 86, 1, 0, // Skip to: 2436
+/* 2094 */ MCD::OPC_Decode, 135, 13, 228, 2, // Opcode: LL_R6
+/* 2099 */ MCD::OPC_FilterValue, 55, 10, 0, 0, // Skip to: 2114
+/* 2104 */ MCD::OPC_CheckPredicate, 76, 71, 1, 0, // Skip to: 2436
+/* 2109 */ MCD::OPC_Decode, 130, 13, 228, 2, // Opcode: LLD_R6
+/* 2114 */ MCD::OPC_FilterValue, 61, 61, 1, 0, // Skip to: 2436
+/* 2119 */ MCD::OPC_ExtractField, 6, 2, // Inst{7-6} ...
+/* 2122 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2144
+/* 2127 */ MCD::OPC_CheckPredicate, 82, 48, 1, 0, // Skip to: 2436
+/* 2132 */ MCD::OPC_CheckField, 10, 11, 0, 41, 1, 0, // Skip to: 2436
+/* 2139 */ MCD::OPC_Decode, 238, 11, 172, 1, // Opcode: GINVI
+/* 2144 */ MCD::OPC_FilterValue, 2, 31, 1, 0, // Skip to: 2436
+/* 2149 */ MCD::OPC_CheckPredicate, 82, 26, 1, 0, // Skip to: 2436
+/* 2154 */ MCD::OPC_CheckField, 10, 11, 0, 19, 1, 0, // Skip to: 2436
+/* 2161 */ MCD::OPC_Decode, 240, 11, 229, 2, // Opcode: GINVT
+/* 2166 */ MCD::OPC_FilterValue, 50, 10, 0, 0, // Skip to: 2181
+/* 2171 */ MCD::OPC_CheckPredicate, 75, 4, 1, 0, // Skip to: 2436
+/* 2176 */ MCD::OPC_Decode, 147, 5, 230, 2, // Opcode: BC
+/* 2181 */ MCD::OPC_FilterValue, 53, 27, 0, 0, // Skip to: 2213
+/* 2186 */ MCD::OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2203
+/* 2191 */ MCD::OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2203
+/* 2198 */ MCD::OPC_Decode, 212, 5, 166, 1, // Opcode: BGTZC_MMR6
+/* 2203 */ MCD::OPC_CheckPredicate, 24, 228, 0, 0, // Skip to: 2436
+/* 2208 */ MCD::OPC_Decode, 132, 6, 166, 1, // Opcode: BLTZC_MMR6
+/* 2213 */ MCD::OPC_FilterValue, 54, 26, 0, 0, // Skip to: 2244
+/* 2218 */ MCD::OPC_CheckPredicate, 74, 11, 0, 0, // Skip to: 2234
+/* 2223 */ MCD::OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 2234
+/* 2230 */ MCD::OPC_Decode, 177, 12, 91, // Opcode: JIC
+/* 2234 */ MCD::OPC_CheckPredicate, 75, 197, 0, 0, // Skip to: 2436
+/* 2239 */ MCD::OPC_Decode, 181, 5, 231, 2, // Opcode: BEQZC
+/* 2244 */ MCD::OPC_FilterValue, 58, 10, 0, 0, // Skip to: 2259
+/* 2249 */ MCD::OPC_CheckPredicate, 74, 182, 0, 0, // Skip to: 2436
+/* 2254 */ MCD::OPC_Decode, 139, 5, 230, 2, // Opcode: BALC
+/* 2259 */ MCD::OPC_FilterValue, 59, 109, 0, 0, // Skip to: 2373
+/* 2264 */ MCD::OPC_ExtractField, 19, 2, // Inst{20-19} ...
+/* 2267 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2282
+/* 2272 */ MCD::OPC_CheckPredicate, 74, 159, 0, 0, // Skip to: 2436
+/* 2277 */ MCD::OPC_Decode, 134, 4, 160, 1, // Opcode: ADDIUPC
+/* 2282 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2297
+/* 2287 */ MCD::OPC_CheckPredicate, 74, 144, 0, 0, // Skip to: 2436
+/* 2292 */ MCD::OPC_Decode, 168, 13, 160, 1, // Opcode: LWPC
+/* 2297 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2312
+/* 2302 */ MCD::OPC_CheckPredicate, 75, 129, 0, 0, // Skip to: 2436
+/* 2307 */ MCD::OPC_Decode, 177, 13, 160, 1, // Opcode: LWUPC
+/* 2312 */ MCD::OPC_FilterValue, 3, 119, 0, 0, // Skip to: 2436
+/* 2317 */ MCD::OPC_ExtractField, 18, 1, // Inst{18} ...
+/* 2320 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2335
+/* 2325 */ MCD::OPC_CheckPredicate, 83, 106, 0, 0, // Skip to: 2436
+/* 2330 */ MCD::OPC_Decode, 228, 12, 232, 2, // Opcode: LDPC
+/* 2335 */ MCD::OPC_FilterValue, 1, 96, 0, 0, // Skip to: 2436
+/* 2340 */ MCD::OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 2343 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2358
+/* 2348 */ MCD::OPC_CheckPredicate, 74, 83, 0, 0, // Skip to: 2436
+/* 2353 */ MCD::OPC_Decode, 236, 4, 161, 1, // Opcode: AUIPC
+/* 2358 */ MCD::OPC_FilterValue, 3, 73, 0, 0, // Skip to: 2436
+/* 2363 */ MCD::OPC_CheckPredicate, 74, 68, 0, 0, // Skip to: 2436
+/* 2368 */ MCD::OPC_Decode, 209, 4, 161, 1, // Opcode: ALUIPC
+/* 2373 */ MCD::OPC_FilterValue, 61, 27, 0, 0, // Skip to: 2405
+/* 2378 */ MCD::OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 2395
+/* 2383 */ MCD::OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 2395
+/* 2390 */ MCD::OPC_Decode, 241, 5, 168, 1, // Opcode: BLEZC_MMR6
+/* 2395 */ MCD::OPC_CheckPredicate, 24, 36, 0, 0, // Skip to: 2436
+/* 2400 */ MCD::OPC_Decode, 203, 5, 168, 1, // Opcode: BGEZC_MMR6
+/* 2405 */ MCD::OPC_FilterValue, 62, 26, 0, 0, // Skip to: 2436
+/* 2410 */ MCD::OPC_CheckPredicate, 74, 11, 0, 0, // Skip to: 2426
+/* 2415 */ MCD::OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 2426
+/* 2422 */ MCD::OPC_Decode, 174, 12, 91, // Opcode: JIALC
+/* 2426 */ MCD::OPC_CheckPredicate, 75, 5, 0, 0, // Skip to: 2436
+/* 2431 */ MCD::OPC_Decode, 156, 6, 231, 2, // Opcode: BNEZC
+/* 2436 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32r6_64r6_Ambiguous32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 6, 27, 0, 0, // Skip to: 35
+/* 8 */ MCD::OPC_CheckPredicate, 75, 12, 0, 0, // Skip to: 25
+/* 13 */ MCD::OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 25
+/* 20 */ MCD::OPC_Decode, 237, 5, 208, 2, // Opcode: BLEZALC
+/* 25 */ MCD::OPC_CheckPredicate, 75, 165, 0, 0, // Skip to: 195
+/* 30 */ MCD::OPC_Decode, 190, 5, 208, 2, // Opcode: BGEUC
+/* 35 */ MCD::OPC_FilterValue, 7, 27, 0, 0, // Skip to: 67
+/* 40 */ MCD::OPC_CheckPredicate, 75, 12, 0, 0, // Skip to: 57
+/* 45 */ MCD::OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 57
+/* 52 */ MCD::OPC_Decode, 208, 5, 209, 2, // Opcode: BGTZALC
+/* 57 */ MCD::OPC_CheckPredicate, 75, 133, 0, 0, // Skip to: 195
+/* 62 */ MCD::OPC_Decode, 247, 5, 209, 2, // Opcode: BLTUC
+/* 67 */ MCD::OPC_FilterValue, 8, 27, 0, 0, // Skip to: 99
+/* 72 */ MCD::OPC_CheckPredicate, 75, 12, 0, 0, // Skip to: 89
+/* 77 */ MCD::OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 89
+/* 84 */ MCD::OPC_Decode, 179, 5, 222, 2, // Opcode: BEQZALC
+/* 89 */ MCD::OPC_CheckPredicate, 75, 101, 0, 0, // Skip to: 195
+/* 94 */ MCD::OPC_Decode, 169, 6, 210, 2, // Opcode: BOVC
+/* 99 */ MCD::OPC_FilterValue, 22, 27, 0, 0, // Skip to: 131
+/* 104 */ MCD::OPC_CheckPredicate, 75, 12, 0, 0, // Skip to: 121
+/* 109 */ MCD::OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 121
+/* 116 */ MCD::OPC_Decode, 239, 5, 220, 2, // Opcode: BLEZC
+/* 121 */ MCD::OPC_CheckPredicate, 75, 69, 0, 0, // Skip to: 195
+/* 126 */ MCD::OPC_Decode, 187, 5, 220, 2, // Opcode: BGEC
+/* 131 */ MCD::OPC_FilterValue, 23, 27, 0, 0, // Skip to: 163
+/* 136 */ MCD::OPC_CheckPredicate, 75, 12, 0, 0, // Skip to: 153
+/* 141 */ MCD::OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 153
+/* 148 */ MCD::OPC_Decode, 210, 5, 221, 2, // Opcode: BGTZC
+/* 153 */ MCD::OPC_CheckPredicate, 75, 37, 0, 0, // Skip to: 195
+/* 158 */ MCD::OPC_Decode, 244, 5, 221, 2, // Opcode: BLTC
+/* 163 */ MCD::OPC_FilterValue, 24, 27, 0, 0, // Skip to: 195
+/* 168 */ MCD::OPC_CheckPredicate, 75, 12, 0, 0, // Skip to: 185
+/* 173 */ MCD::OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 185
+/* 180 */ MCD::OPC_Decode, 154, 6, 222, 2, // Opcode: BNEZALC
+/* 185 */ MCD::OPC_CheckPredicate, 75, 5, 0, 0, // Skip to: 195
+/* 190 */ MCD::OPC_Decode, 162, 6, 222, 2, // Opcode: BNVC
+/* 195 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32r6_64r6_BranchZero32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 22, 10, 0, 0, // Skip to: 18
+/* 8 */ MCD::OPC_CheckPredicate, 84, 20, 0, 0, // Skip to: 33
+/* 13 */ MCD::OPC_Decode, 202, 5, 220, 2, // Opcode: BGEZC64
+/* 18 */ MCD::OPC_FilterValue, 23, 10, 0, 0, // Skip to: 33
+/* 23 */ MCD::OPC_CheckPredicate, 84, 5, 0, 0, // Skip to: 33
+/* 28 */ MCD::OPC_Decode, 131, 6, 221, 2, // Opcode: BLTZC64
+/* 33 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 53, 0, 0, // Skip to: 61
+/* 8 */ MCD::OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 11 */ MCD::OPC_FilterValue, 53, 9, 0, 0, // Skip to: 25
+/* 16 */ MCD::OPC_CheckPredicate, 85, 226, 0, 0, // Skip to: 247
+/* 21 */ MCD::OPC_Decode, 191, 17, 12, // Opcode: SELEQZ64
+/* 25 */ MCD::OPC_FilterValue, 55, 9, 0, 0, // Skip to: 39
+/* 30 */ MCD::OPC_CheckPredicate, 85, 212, 0, 0, // Skip to: 247
+/* 35 */ MCD::OPC_Decode, 198, 17, 12, // Opcode: SELNEZ64
+/* 39 */ MCD::OPC_FilterValue, 137, 8, 202, 0, 0, // Skip to: 247
+/* 45 */ MCD::OPC_CheckPredicate, 74, 197, 0, 0, // Skip to: 247
+/* 50 */ MCD::OPC_CheckField, 11, 10, 0, 190, 0, 0, // Skip to: 247
+/* 57 */ MCD::OPC_Decode, 189, 12, 13, // Opcode: JR_HB64_R6
+/* 61 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76
+/* 66 */ MCD::OPC_CheckPredicate, 84, 176, 0, 0, // Skip to: 247
+/* 71 */ MCD::OPC_Decode, 191, 5, 208, 2, // Opcode: BGEUC64
+/* 76 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 91
+/* 81 */ MCD::OPC_CheckPredicate, 84, 161, 0, 0, // Skip to: 247
+/* 86 */ MCD::OPC_Decode, 248, 5, 209, 2, // Opcode: BLTUC64
+/* 91 */ MCD::OPC_FilterValue, 8, 10, 0, 0, // Skip to: 106
+/* 96 */ MCD::OPC_CheckPredicate, 84, 146, 0, 0, // Skip to: 247
+/* 101 */ MCD::OPC_Decode, 175, 5, 210, 2, // Opcode: BEQC64
+/* 106 */ MCD::OPC_FilterValue, 22, 27, 0, 0, // Skip to: 138
+/* 111 */ MCD::OPC_CheckPredicate, 84, 12, 0, 0, // Skip to: 128
+/* 116 */ MCD::OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 128
+/* 123 */ MCD::OPC_Decode, 240, 5, 220, 2, // Opcode: BLEZC64
+/* 128 */ MCD::OPC_CheckPredicate, 84, 114, 0, 0, // Skip to: 247
+/* 133 */ MCD::OPC_Decode, 188, 5, 220, 2, // Opcode: BGEC64
+/* 138 */ MCD::OPC_FilterValue, 23, 27, 0, 0, // Skip to: 170
+/* 143 */ MCD::OPC_CheckPredicate, 84, 12, 0, 0, // Skip to: 160
+/* 148 */ MCD::OPC_CheckField, 21, 5, 0, 5, 0, 0, // Skip to: 160
+/* 155 */ MCD::OPC_Decode, 211, 5, 221, 2, // Opcode: BGTZC64
+/* 160 */ MCD::OPC_CheckPredicate, 84, 82, 0, 0, // Skip to: 247
+/* 165 */ MCD::OPC_Decode, 245, 5, 221, 2, // Opcode: BLTC64
+/* 170 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 185
+/* 175 */ MCD::OPC_CheckPredicate, 84, 67, 0, 0, // Skip to: 247
+/* 180 */ MCD::OPC_Decode, 142, 6, 222, 2, // Opcode: BNEC64
+/* 185 */ MCD::OPC_FilterValue, 54, 26, 0, 0, // Skip to: 216
+/* 190 */ MCD::OPC_CheckPredicate, 84, 11, 0, 0, // Skip to: 206
+/* 195 */ MCD::OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 206
+/* 202 */ MCD::OPC_Decode, 178, 12, 11, // Opcode: JIC64
+/* 206 */ MCD::OPC_CheckPredicate, 84, 36, 0, 0, // Skip to: 247
+/* 211 */ MCD::OPC_Decode, 183, 5, 233, 2, // Opcode: BEQZC64
+/* 216 */ MCD::OPC_FilterValue, 62, 26, 0, 0, // Skip to: 247
+/* 221 */ MCD::OPC_CheckPredicate, 84, 11, 0, 0, // Skip to: 237
+/* 226 */ MCD::OPC_CheckField, 21, 5, 0, 4, 0, 0, // Skip to: 237
+/* 233 */ MCD::OPC_Decode, 175, 12, 11, // Opcode: JIALC64
+/* 237 */ MCD::OPC_CheckPredicate, 84, 5, 0, 0, // Skip to: 247
+/* 242 */ MCD::OPC_Decode, 158, 6, 233, 2, // Opcode: BNEZC64
+/* 247 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips32r6_64r6_PTR6432[] = {
+/* 0 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 3 */ MCD::OPC_FilterValue, 38, 17, 0, 0, // Skip to: 25
+/* 8 */ MCD::OPC_CheckPredicate, 86, 34, 0, 0, // Skip to: 47
+/* 13 */ MCD::OPC_CheckField, 26, 6, 31, 27, 0, 0, // Skip to: 47
+/* 20 */ MCD::OPC_Decode, 155, 17, 228, 2, // Opcode: SC64_R6
+/* 25 */ MCD::OPC_FilterValue, 54, 17, 0, 0, // Skip to: 47
+/* 30 */ MCD::OPC_CheckPredicate, 86, 12, 0, 0, // Skip to: 47
+/* 35 */ MCD::OPC_CheckField, 26, 6, 31, 5, 0, 0, // Skip to: 47
+/* 42 */ MCD::OPC_Decode, 128, 13, 228, 2, // Opcode: LL64_R6
+/* 47 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMips6432[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 236, 1, 0, // Skip to: 500
+/* 8 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 11 */ MCD::OPC_FilterValue, 8, 16, 0, 0, // Skip to: 32
+/* 16 */ MCD::OPC_CheckPredicate, 67, 214, 4, 0, // Skip to: 1259
+/* 21 */ MCD::OPC_CheckField, 6, 15, 16, 207, 4, 0, // Skip to: 1259
+/* 28 */ MCD::OPC_Decode, 188, 12, 13, // Opcode: JR_HB64
+/* 32 */ MCD::OPC_FilterValue, 9, 45, 0, 0, // Skip to: 82
+/* 37 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 40 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 61
+/* 45 */ MCD::OPC_CheckPredicate, 87, 185, 4, 0, // Skip to: 1259
+/* 50 */ MCD::OPC_CheckField, 16, 5, 0, 178, 4, 0, // Skip to: 1259
+/* 57 */ MCD::OPC_Decode, 161, 12, 15, // Opcode: JALR64
+/* 61 */ MCD::OPC_FilterValue, 16, 169, 4, 0, // Skip to: 1259
+/* 66 */ MCD::OPC_CheckPredicate, 28, 164, 4, 0, // Skip to: 1259
+/* 71 */ MCD::OPC_CheckField, 16, 5, 0, 157, 4, 0, // Skip to: 1259
+/* 78 */ MCD::OPC_Decode, 168, 12, 15, // Opcode: JALR_HB64
+/* 82 */ MCD::OPC_FilterValue, 20, 17, 0, 0, // Skip to: 104
+/* 87 */ MCD::OPC_CheckPredicate, 88, 143, 4, 0, // Skip to: 1259
+/* 92 */ MCD::OPC_CheckField, 6, 5, 0, 136, 4, 0, // Skip to: 1259
+/* 99 */ MCD::OPC_Decode, 130, 10, 234, 2, // Opcode: DSLLV
+/* 104 */ MCD::OPC_FilterValue, 22, 33, 0, 0, // Skip to: 142
+/* 109 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 112 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 127
+/* 117 */ MCD::OPC_CheckPredicate, 88, 113, 4, 0, // Skip to: 1259
+/* 122 */ MCD::OPC_Decode, 136, 10, 234, 2, // Opcode: DSRLV
+/* 127 */ MCD::OPC_FilterValue, 1, 103, 4, 0, // Skip to: 1259
+/* 132 */ MCD::OPC_CheckPredicate, 89, 98, 4, 0, // Skip to: 1259
+/* 137 */ MCD::OPC_Decode, 251, 9, 234, 2, // Opcode: DROTRV
+/* 142 */ MCD::OPC_FilterValue, 23, 17, 0, 0, // Skip to: 164
+/* 147 */ MCD::OPC_CheckPredicate, 88, 83, 4, 0, // Skip to: 1259
+/* 152 */ MCD::OPC_CheckField, 6, 5, 0, 76, 4, 0, // Skip to: 1259
+/* 159 */ MCD::OPC_Decode, 133, 10, 234, 2, // Opcode: DSRAV
+/* 164 */ MCD::OPC_FilterValue, 28, 17, 0, 0, // Skip to: 186
+/* 169 */ MCD::OPC_CheckPredicate, 90, 61, 4, 0, // Skip to: 1259
+/* 174 */ MCD::OPC_CheckField, 6, 10, 0, 54, 4, 0, // Skip to: 1259
+/* 181 */ MCD::OPC_Decode, 194, 9, 235, 2, // Opcode: DMULT
+/* 186 */ MCD::OPC_FilterValue, 29, 17, 0, 0, // Skip to: 208
+/* 191 */ MCD::OPC_CheckPredicate, 90, 39, 4, 0, // Skip to: 1259
+/* 196 */ MCD::OPC_CheckField, 6, 10, 0, 32, 4, 0, // Skip to: 1259
+/* 203 */ MCD::OPC_Decode, 195, 9, 235, 2, // Opcode: DMULTu
+/* 208 */ MCD::OPC_FilterValue, 30, 17, 0, 0, // Skip to: 230
+/* 213 */ MCD::OPC_CheckPredicate, 90, 17, 4, 0, // Skip to: 1259
+/* 218 */ MCD::OPC_CheckField, 6, 10, 0, 10, 4, 0, // Skip to: 1259
+/* 225 */ MCD::OPC_Decode, 253, 9, 235, 2, // Opcode: DSDIV
+/* 230 */ MCD::OPC_FilterValue, 31, 17, 0, 0, // Skip to: 252
+/* 235 */ MCD::OPC_CheckPredicate, 90, 251, 3, 0, // Skip to: 1259
+/* 240 */ MCD::OPC_CheckField, 6, 10, 0, 244, 3, 0, // Skip to: 1259
+/* 247 */ MCD::OPC_Decode, 139, 10, 235, 2, // Opcode: DUDIV
+/* 252 */ MCD::OPC_FilterValue, 44, 16, 0, 0, // Skip to: 273
+/* 257 */ MCD::OPC_CheckPredicate, 88, 229, 3, 0, // Skip to: 1259
+/* 262 */ MCD::OPC_CheckField, 6, 5, 0, 222, 3, 0, // Skip to: 1259
+/* 269 */ MCD::OPC_Decode, 136, 9, 12, // Opcode: DADD
+/* 273 */ MCD::OPC_FilterValue, 45, 16, 0, 0, // Skip to: 294
+/* 278 */ MCD::OPC_CheckPredicate, 88, 208, 3, 0, // Skip to: 1259
+/* 283 */ MCD::OPC_CheckField, 6, 5, 0, 201, 3, 0, // Skip to: 1259
+/* 290 */ MCD::OPC_Decode, 139, 9, 12, // Opcode: DADDu
+/* 294 */ MCD::OPC_FilterValue, 46, 16, 0, 0, // Skip to: 315
+/* 299 */ MCD::OPC_CheckPredicate, 88, 187, 3, 0, // Skip to: 1259
+/* 304 */ MCD::OPC_CheckField, 6, 5, 0, 180, 3, 0, // Skip to: 1259
+/* 311 */ MCD::OPC_Decode, 137, 10, 12, // Opcode: DSUB
+/* 315 */ MCD::OPC_FilterValue, 47, 16, 0, 0, // Skip to: 336
+/* 320 */ MCD::OPC_CheckPredicate, 88, 166, 3, 0, // Skip to: 1259
+/* 325 */ MCD::OPC_CheckField, 6, 5, 0, 159, 3, 0, // Skip to: 1259
+/* 332 */ MCD::OPC_Decode, 138, 10, 12, // Opcode: DSUBu
+/* 336 */ MCD::OPC_FilterValue, 56, 17, 0, 0, // Skip to: 358
+/* 341 */ MCD::OPC_CheckPredicate, 88, 145, 3, 0, // Skip to: 1259
+/* 346 */ MCD::OPC_CheckField, 21, 5, 0, 138, 3, 0, // Skip to: 1259
+/* 353 */ MCD::OPC_Decode, 255, 9, 236, 2, // Opcode: DSLL
+/* 358 */ MCD::OPC_FilterValue, 58, 33, 0, 0, // Skip to: 396
+/* 363 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 366 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 381
+/* 371 */ MCD::OPC_CheckPredicate, 88, 115, 3, 0, // Skip to: 1259
+/* 376 */ MCD::OPC_Decode, 134, 10, 236, 2, // Opcode: DSRL
+/* 381 */ MCD::OPC_FilterValue, 1, 105, 3, 0, // Skip to: 1259
+/* 386 */ MCD::OPC_CheckPredicate, 89, 100, 3, 0, // Skip to: 1259
+/* 391 */ MCD::OPC_Decode, 249, 9, 236, 2, // Opcode: DROTR
+/* 396 */ MCD::OPC_FilterValue, 59, 17, 0, 0, // Skip to: 418
+/* 401 */ MCD::OPC_CheckPredicate, 88, 85, 3, 0, // Skip to: 1259
+/* 406 */ MCD::OPC_CheckField, 21, 5, 0, 78, 3, 0, // Skip to: 1259
+/* 413 */ MCD::OPC_Decode, 131, 10, 236, 2, // Opcode: DSRA
+/* 418 */ MCD::OPC_FilterValue, 60, 17, 0, 0, // Skip to: 440
+/* 423 */ MCD::OPC_CheckPredicate, 88, 63, 3, 0, // Skip to: 1259
+/* 428 */ MCD::OPC_CheckField, 21, 5, 0, 56, 3, 0, // Skip to: 1259
+/* 435 */ MCD::OPC_Decode, 128, 10, 236, 2, // Opcode: DSLL32
+/* 440 */ MCD::OPC_FilterValue, 62, 33, 0, 0, // Skip to: 478
+/* 445 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 448 */ MCD::OPC_FilterValue, 0, 10, 0, 0, // Skip to: 463
+/* 453 */ MCD::OPC_CheckPredicate, 88, 33, 3, 0, // Skip to: 1259
+/* 458 */ MCD::OPC_Decode, 135, 10, 236, 2, // Opcode: DSRL32
+/* 463 */ MCD::OPC_FilterValue, 1, 23, 3, 0, // Skip to: 1259
+/* 468 */ MCD::OPC_CheckPredicate, 89, 18, 3, 0, // Skip to: 1259
+/* 473 */ MCD::OPC_Decode, 250, 9, 236, 2, // Opcode: DROTR32
+/* 478 */ MCD::OPC_FilterValue, 63, 8, 3, 0, // Skip to: 1259
+/* 483 */ MCD::OPC_CheckPredicate, 88, 3, 3, 0, // Skip to: 1259
+/* 488 */ MCD::OPC_CheckField, 21, 5, 0, 252, 2, 0, // Skip to: 1259
+/* 495 */ MCD::OPC_Decode, 132, 10, 236, 2, // Opcode: DSRA32
+/* 500 */ MCD::OPC_FilterValue, 16, 85, 0, 0, // Skip to: 590
+/* 505 */ MCD::OPC_ExtractField, 3, 8, // Inst{10-3} ...
+/* 508 */ MCD::OPC_FilterValue, 0, 33, 0, 0, // Skip to: 546
+/* 513 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 516 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 531
+/* 521 */ MCD::OPC_CheckPredicate, 91, 221, 2, 0, // Skip to: 1259
+/* 526 */ MCD::OPC_Decode, 178, 9, 237, 2, // Opcode: DMFC0
+/* 531 */ MCD::OPC_FilterValue, 5, 211, 2, 0, // Skip to: 1259
+/* 536 */ MCD::OPC_CheckPredicate, 91, 206, 2, 0, // Skip to: 1259
+/* 541 */ MCD::OPC_Decode, 186, 9, 238, 2, // Opcode: DMTC0
+/* 546 */ MCD::OPC_FilterValue, 32, 17, 0, 0, // Skip to: 568
+/* 551 */ MCD::OPC_CheckPredicate, 92, 191, 2, 0, // Skip to: 1259
+/* 556 */ MCD::OPC_CheckField, 21, 5, 3, 184, 2, 0, // Skip to: 1259
+/* 563 */ MCD::OPC_Decode, 182, 9, 237, 2, // Opcode: DMFGC0
+/* 568 */ MCD::OPC_FilterValue, 96, 174, 2, 0, // Skip to: 1259
+/* 573 */ MCD::OPC_CheckPredicate, 92, 169, 2, 0, // Skip to: 1259
+/* 578 */ MCD::OPC_CheckField, 21, 5, 3, 162, 2, 0, // Skip to: 1259
+/* 585 */ MCD::OPC_Decode, 190, 9, 238, 2, // Opcode: DMTGC0
+/* 590 */ MCD::OPC_FilterValue, 18, 47, 0, 0, // Skip to: 642
+/* 595 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 598 */ MCD::OPC_FilterValue, 1, 17, 0, 0, // Skip to: 620
+/* 603 */ MCD::OPC_CheckPredicate, 91, 139, 2, 0, // Skip to: 1259
+/* 608 */ MCD::OPC_CheckField, 3, 8, 0, 132, 2, 0, // Skip to: 1259
+/* 615 */ MCD::OPC_Decode, 180, 9, 239, 2, // Opcode: DMFC2
+/* 620 */ MCD::OPC_FilterValue, 5, 122, 2, 0, // Skip to: 1259
+/* 625 */ MCD::OPC_CheckPredicate, 91, 117, 2, 0, // Skip to: 1259
+/* 630 */ MCD::OPC_CheckField, 3, 8, 0, 110, 2, 0, // Skip to: 1259
+/* 637 */ MCD::OPC_Decode, 188, 9, 240, 2, // Opcode: DMTC2
+/* 642 */ MCD::OPC_FilterValue, 21, 3, 1, 0, // Skip to: 906
+/* 647 */ MCD::OPC_ExtractField, 0, 13, // Inst{12-0} ...
+/* 650 */ MCD::OPC_FilterValue, 188, 8, 10, 0, 0, // Skip to: 666
+/* 656 */ MCD::OPC_CheckPredicate, 14, 86, 2, 0, // Skip to: 1259
+/* 661 */ MCD::OPC_Decode, 174, 8, 241, 2, // Opcode: C_F_D64_MM
+/* 666 */ MCD::OPC_FilterValue, 252, 8, 10, 0, 0, // Skip to: 682
+/* 672 */ MCD::OPC_CheckPredicate, 14, 70, 2, 0, // Skip to: 1259
+/* 677 */ MCD::OPC_Decode, 130, 9, 241, 2, // Opcode: C_UN_D64_MM
+/* 682 */ MCD::OPC_FilterValue, 188, 9, 10, 0, 0, // Skip to: 698
+/* 688 */ MCD::OPC_CheckPredicate, 14, 54, 2, 0, // Skip to: 1259
+/* 693 */ MCD::OPC_Decode, 168, 8, 241, 2, // Opcode: C_EQ_D64_MM
+/* 698 */ MCD::OPC_FilterValue, 252, 9, 10, 0, 0, // Skip to: 714
+/* 704 */ MCD::OPC_CheckPredicate, 14, 38, 2, 0, // Skip to: 1259
+/* 709 */ MCD::OPC_Decode, 240, 8, 241, 2, // Opcode: C_UEQ_D64_MM
+/* 714 */ MCD::OPC_FilterValue, 188, 10, 10, 0, 0, // Skip to: 730
+/* 720 */ MCD::OPC_CheckPredicate, 14, 22, 2, 0, // Skip to: 1259
+/* 725 */ MCD::OPC_Decode, 222, 8, 241, 2, // Opcode: C_OLT_D64_MM
+/* 730 */ MCD::OPC_FilterValue, 252, 10, 10, 0, 0, // Skip to: 746
+/* 736 */ MCD::OPC_CheckPredicate, 14, 6, 2, 0, // Skip to: 1259
+/* 741 */ MCD::OPC_Decode, 252, 8, 241, 2, // Opcode: C_ULT_D64_MM
+/* 746 */ MCD::OPC_FilterValue, 188, 11, 10, 0, 0, // Skip to: 762
+/* 752 */ MCD::OPC_CheckPredicate, 14, 246, 1, 0, // Skip to: 1259
+/* 757 */ MCD::OPC_Decode, 216, 8, 241, 2, // Opcode: C_OLE_D64_MM
+/* 762 */ MCD::OPC_FilterValue, 252, 11, 10, 0, 0, // Skip to: 778
+/* 768 */ MCD::OPC_CheckPredicate, 14, 230, 1, 0, // Skip to: 1259
+/* 773 */ MCD::OPC_Decode, 246, 8, 241, 2, // Opcode: C_ULE_D64_MM
+/* 778 */ MCD::OPC_FilterValue, 188, 12, 10, 0, 0, // Skip to: 794
+/* 784 */ MCD::OPC_CheckPredicate, 14, 214, 1, 0, // Skip to: 1259
+/* 789 */ MCD::OPC_Decode, 234, 8, 241, 2, // Opcode: C_SF_D64_MM
+/* 794 */ MCD::OPC_FilterValue, 252, 12, 10, 0, 0, // Skip to: 810
+/* 800 */ MCD::OPC_CheckPredicate, 14, 198, 1, 0, // Skip to: 1259
+/* 805 */ MCD::OPC_Decode, 198, 8, 241, 2, // Opcode: C_NGLE_D64_MM
+/* 810 */ MCD::OPC_FilterValue, 188, 13, 10, 0, 0, // Skip to: 826
+/* 816 */ MCD::OPC_CheckPredicate, 14, 182, 1, 0, // Skip to: 1259
+/* 821 */ MCD::OPC_Decode, 228, 8, 241, 2, // Opcode: C_SEQ_D64_MM
+/* 826 */ MCD::OPC_FilterValue, 252, 13, 10, 0, 0, // Skip to: 842
+/* 832 */ MCD::OPC_CheckPredicate, 14, 166, 1, 0, // Skip to: 1259
+/* 837 */ MCD::OPC_Decode, 204, 8, 241, 2, // Opcode: C_NGL_D64_MM
+/* 842 */ MCD::OPC_FilterValue, 188, 14, 10, 0, 0, // Skip to: 858
+/* 848 */ MCD::OPC_CheckPredicate, 14, 150, 1, 0, // Skip to: 1259
+/* 853 */ MCD::OPC_Decode, 186, 8, 241, 2, // Opcode: C_LT_D64_MM
+/* 858 */ MCD::OPC_FilterValue, 252, 14, 10, 0, 0, // Skip to: 874
+/* 864 */ MCD::OPC_CheckPredicate, 14, 134, 1, 0, // Skip to: 1259
+/* 869 */ MCD::OPC_Decode, 192, 8, 241, 2, // Opcode: C_NGE_D64_MM
+/* 874 */ MCD::OPC_FilterValue, 188, 15, 10, 0, 0, // Skip to: 890
+/* 880 */ MCD::OPC_CheckPredicate, 14, 118, 1, 0, // Skip to: 1259
+/* 885 */ MCD::OPC_Decode, 180, 8, 241, 2, // Opcode: C_LE_D64_MM
+/* 890 */ MCD::OPC_FilterValue, 252, 15, 107, 1, 0, // Skip to: 1259
+/* 896 */ MCD::OPC_CheckPredicate, 14, 102, 1, 0, // Skip to: 1259
+/* 901 */ MCD::OPC_Decode, 210, 8, 241, 2, // Opcode: C_NGT_D64_MM
+/* 906 */ MCD::OPC_FilterValue, 24, 10, 0, 0, // Skip to: 921
+/* 911 */ MCD::OPC_CheckPredicate, 93, 87, 1, 0, // Skip to: 1259
+/* 916 */ MCD::OPC_Decode, 137, 9, 242, 2, // Opcode: DADDi
+/* 921 */ MCD::OPC_FilterValue, 25, 10, 0, 0, // Skip to: 936
+/* 926 */ MCD::OPC_CheckPredicate, 88, 72, 1, 0, // Skip to: 1259
+/* 931 */ MCD::OPC_Decode, 138, 9, 242, 2, // Opcode: DADDiu
+/* 936 */ MCD::OPC_FilterValue, 26, 10, 0, 0, // Skip to: 951
+/* 941 */ MCD::OPC_CheckPredicate, 93, 57, 1, 0, // Skip to: 1259
+/* 946 */ MCD::OPC_Decode, 227, 12, 128, 1, // Opcode: LDL
+/* 951 */ MCD::OPC_FilterValue, 27, 10, 0, 0, // Skip to: 966
+/* 956 */ MCD::OPC_CheckPredicate, 93, 42, 1, 0, // Skip to: 1259
+/* 961 */ MCD::OPC_Decode, 229, 12, 128, 1, // Opcode: LDR
+/* 966 */ MCD::OPC_FilterValue, 28, 33, 0, 0, // Skip to: 1004
+/* 971 */ MCD::OPC_ExtractField, 0, 11, // Inst{10-0} ...
+/* 974 */ MCD::OPC_FilterValue, 36, 10, 0, 0, // Skip to: 989
+/* 979 */ MCD::OPC_CheckPredicate, 94, 19, 1, 0, // Skip to: 1259
+/* 984 */ MCD::OPC_Decode, 147, 9, 243, 2, // Opcode: DCLZ
+/* 989 */ MCD::OPC_FilterValue, 37, 9, 1, 0, // Skip to: 1259
+/* 994 */ MCD::OPC_CheckPredicate, 94, 4, 1, 0, // Skip to: 1259
+/* 999 */ MCD::OPC_Decode, 145, 9, 243, 2, // Opcode: DCLO
+/* 1004 */ MCD::OPC_FilterValue, 31, 145, 0, 0, // Skip to: 1154
+/* 1009 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1012 */ MCD::OPC_FilterValue, 1, 10, 0, 0, // Skip to: 1027
+/* 1017 */ MCD::OPC_CheckPredicate, 89, 237, 0, 0, // Skip to: 1259
+/* 1022 */ MCD::OPC_Decode, 156, 9, 244, 2, // Opcode: DEXTM
+/* 1027 */ MCD::OPC_FilterValue, 2, 10, 0, 0, // Skip to: 1042
+/* 1032 */ MCD::OPC_CheckPredicate, 89, 222, 0, 0, // Skip to: 1259
+/* 1037 */ MCD::OPC_Decode, 157, 9, 244, 2, // Opcode: DEXTU
+/* 1042 */ MCD::OPC_FilterValue, 3, 10, 0, 0, // Skip to: 1057
+/* 1047 */ MCD::OPC_CheckPredicate, 89, 207, 0, 0, // Skip to: 1259
+/* 1052 */ MCD::OPC_Decode, 154, 9, 244, 2, // Opcode: DEXT
+/* 1057 */ MCD::OPC_FilterValue, 5, 10, 0, 0, // Skip to: 1072
+/* 1062 */ MCD::OPC_CheckPredicate, 89, 192, 0, 0, // Skip to: 1259
+/* 1067 */ MCD::OPC_Decode, 160, 9, 245, 2, // Opcode: DINSM
+/* 1072 */ MCD::OPC_FilterValue, 6, 10, 0, 0, // Skip to: 1087
+/* 1077 */ MCD::OPC_CheckPredicate, 89, 177, 0, 0, // Skip to: 1259
+/* 1082 */ MCD::OPC_Decode, 161, 9, 245, 2, // Opcode: DINSU
+/* 1087 */ MCD::OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1102
+/* 1092 */ MCD::OPC_CheckPredicate, 89, 162, 0, 0, // Skip to: 1259
+/* 1097 */ MCD::OPC_Decode, 159, 9, 245, 2, // Opcode: DINS
+/* 1102 */ MCD::OPC_FilterValue, 36, 152, 0, 0, // Skip to: 1259
+/* 1107 */ MCD::OPC_ExtractField, 6, 5, // Inst{10-6} ...
+/* 1110 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1132
+/* 1115 */ MCD::OPC_CheckPredicate, 89, 139, 0, 0, // Skip to: 1259
+/* 1120 */ MCD::OPC_CheckField, 21, 5, 0, 132, 0, 0, // Skip to: 1259
+/* 1127 */ MCD::OPC_Decode, 252, 9, 226, 2, // Opcode: DSBH
+/* 1132 */ MCD::OPC_FilterValue, 5, 122, 0, 0, // Skip to: 1259
+/* 1137 */ MCD::OPC_CheckPredicate, 89, 117, 0, 0, // Skip to: 1259
+/* 1142 */ MCD::OPC_CheckField, 21, 5, 0, 110, 0, 0, // Skip to: 1259
+/* 1149 */ MCD::OPC_Decode, 254, 9, 226, 2, // Opcode: DSHD
+/* 1154 */ MCD::OPC_FilterValue, 39, 10, 0, 0, // Skip to: 1169
+/* 1159 */ MCD::OPC_CheckPredicate, 88, 95, 0, 0, // Skip to: 1259
+/* 1164 */ MCD::OPC_Decode, 186, 13, 128, 1, // Opcode: LWu
+/* 1169 */ MCD::OPC_FilterValue, 44, 10, 0, 0, // Skip to: 1184
+/* 1174 */ MCD::OPC_CheckPredicate, 93, 80, 0, 0, // Skip to: 1259
+/* 1179 */ MCD::OPC_Decode, 180, 17, 128, 1, // Opcode: SDL
+/* 1184 */ MCD::OPC_FilterValue, 45, 10, 0, 0, // Skip to: 1199
+/* 1189 */ MCD::OPC_CheckPredicate, 93, 65, 0, 0, // Skip to: 1259
+/* 1194 */ MCD::OPC_Decode, 181, 17, 128, 1, // Opcode: SDR
+/* 1199 */ MCD::OPC_FilterValue, 52, 10, 0, 0, // Skip to: 1214
+/* 1204 */ MCD::OPC_CheckPredicate, 90, 50, 0, 0, // Skip to: 1259
+/* 1209 */ MCD::OPC_Decode, 129, 13, 128, 1, // Opcode: LLD
+/* 1214 */ MCD::OPC_FilterValue, 55, 10, 0, 0, // Skip to: 1229
+/* 1219 */ MCD::OPC_CheckPredicate, 88, 35, 0, 0, // Skip to: 1259
+/* 1224 */ MCD::OPC_Decode, 214, 12, 128, 1, // Opcode: LD
+/* 1229 */ MCD::OPC_FilterValue, 60, 10, 0, 0, // Skip to: 1244
+/* 1234 */ MCD::OPC_CheckPredicate, 93, 20, 0, 0, // Skip to: 1259
+/* 1239 */ MCD::OPC_Decode, 156, 17, 128, 1, // Opcode: SCD
+/* 1244 */ MCD::OPC_FilterValue, 63, 10, 0, 0, // Skip to: 1259
+/* 1249 */ MCD::OPC_CheckPredicate, 88, 5, 0, 0, // Skip to: 1259
+/* 1254 */ MCD::OPC_Decode, 163, 17, 128, 1, // Opcode: SD
+/* 1259 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMipsDSP32[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 35, 10, 0, 0, // Skip to: 18
+/* 8 */ MCD::OPC_CheckPredicate, 95, 20, 0, 0, // Skip to: 33
+/* 13 */ MCD::OPC_Decode, 155, 13, 128, 1, // Opcode: LWDSP
+/* 18 */ MCD::OPC_FilterValue, 43, 10, 0, 0, // Skip to: 33
+/* 23 */ MCD::OPC_CheckPredicate, 95, 5, 0, 0, // Skip to: 33
+/* 28 */ MCD::OPC_Decode, 180, 19, 128, 1, // Opcode: SWDSP
+/* 33 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableMipsFP6432[] = {
+/* 0 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 3 */ MCD::OPC_FilterValue, 17, 225, 4, 0, // Skip to: 1257
+/* 8 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 106, 0, 0, // Skip to: 122
+/* 16 */ MCD::OPC_ExtractField, 21, 5, // Inst{25-21} ...
+/* 19 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41
+/* 24 */ MCD::OPC_CheckPredicate, 96, 134, 5, 0, // Skip to: 1443
+/* 29 */ MCD::OPC_CheckField, 6, 5, 0, 127, 5, 0, // Skip to: 1443
+/* 36 */ MCD::OPC_Decode, 134, 14, 246, 2, // Opcode: MFC1_D64
+/* 41 */ MCD::OPC_FilterValue, 3, 17, 0, 0, // Skip to: 63
+/* 46 */ MCD::OPC_CheckPredicate, 97, 112, 5, 0, // Skip to: 1443
+/* 51 */ MCD::OPC_CheckField, 6, 5, 0, 105, 5, 0, // Skip to: 1443
+/* 58 */ MCD::OPC_Decode, 144, 14, 246, 2, // Opcode: MFHC1_D64
+/* 63 */ MCD::OPC_FilterValue, 4, 17, 0, 0, // Skip to: 85
+/* 68 */ MCD::OPC_CheckPredicate, 96, 90, 5, 0, // Skip to: 1443
+/* 73 */ MCD::OPC_CheckField, 6, 5, 0, 83, 5, 0, // Skip to: 1443
+/* 80 */ MCD::OPC_Decode, 149, 15, 247, 2, // Opcode: MTC1_D64
+/* 85 */ MCD::OPC_FilterValue, 7, 17, 0, 0, // Skip to: 107
+/* 90 */ MCD::OPC_CheckPredicate, 97, 68, 5, 0, // Skip to: 1443
+/* 95 */ MCD::OPC_CheckField, 6, 5, 0, 61, 5, 0, // Skip to: 1443
+/* 102 */ MCD::OPC_Decode, 159, 15, 248, 2, // Opcode: MTHC1_D64
+/* 107 */ MCD::OPC_FilterValue, 17, 51, 5, 0, // Skip to: 1443
+/* 112 */ MCD::OPC_CheckPredicate, 96, 46, 5, 0, // Skip to: 1443
+/* 117 */ MCD::OPC_Decode, 198, 10, 215, 2, // Opcode: FADD_D64
+/* 122 */ MCD::OPC_FilterValue, 1, 17, 0, 0, // Skip to: 144
+/* 127 */ MCD::OPC_CheckPredicate, 96, 31, 5, 0, // Skip to: 1443
+/* 132 */ MCD::OPC_CheckField, 21, 5, 17, 24, 5, 0, // Skip to: 1443
+/* 139 */ MCD::OPC_Decode, 212, 11, 215, 2, // Opcode: FSUB_D64
+/* 144 */ MCD::OPC_FilterValue, 2, 17, 0, 0, // Skip to: 166
+/* 149 */ MCD::OPC_CheckPredicate, 96, 9, 5, 0, // Skip to: 1443
+/* 154 */ MCD::OPC_CheckField, 21, 5, 17, 2, 5, 0, // Skip to: 1443
+/* 161 */ MCD::OPC_Decode, 169, 11, 215, 2, // Opcode: FMUL_D64
+/* 166 */ MCD::OPC_FilterValue, 3, 17, 0, 0, // Skip to: 188
+/* 171 */ MCD::OPC_CheckPredicate, 96, 243, 4, 0, // Skip to: 1443
+/* 176 */ MCD::OPC_CheckField, 21, 5, 17, 236, 4, 0, // Skip to: 1443
+/* 183 */ MCD::OPC_Decode, 236, 10, 215, 2, // Opcode: FDIV_D64
+/* 188 */ MCD::OPC_FilterValue, 4, 18, 0, 0, // Skip to: 211
+/* 193 */ MCD::OPC_CheckPredicate, 98, 221, 4, 0, // Skip to: 1443
+/* 198 */ MCD::OPC_CheckField, 16, 10, 160, 4, 213, 4, 0, // Skip to: 1443
+/* 206 */ MCD::OPC_Decode, 204, 11, 216, 1, // Opcode: FSQRT_D64
+/* 211 */ MCD::OPC_FilterValue, 5, 18, 0, 0, // Skip to: 234
+/* 216 */ MCD::OPC_CheckPredicate, 96, 198, 4, 0, // Skip to: 1443
+/* 221 */ MCD::OPC_CheckField, 16, 10, 160, 4, 190, 4, 0, // Skip to: 1443
+/* 229 */ MCD::OPC_Decode, 191, 10, 216, 1, // Opcode: FABS_D64
+/* 234 */ MCD::OPC_FilterValue, 6, 18, 0, 0, // Skip to: 257
+/* 239 */ MCD::OPC_CheckPredicate, 96, 175, 4, 0, // Skip to: 1443
+/* 244 */ MCD::OPC_CheckField, 16, 10, 160, 4, 167, 4, 0, // Skip to: 1443
+/* 252 */ MCD::OPC_Decode, 159, 11, 216, 1, // Opcode: FMOV_D64
+/* 257 */ MCD::OPC_FilterValue, 7, 18, 0, 0, // Skip to: 280
+/* 262 */ MCD::OPC_CheckPredicate, 96, 152, 4, 0, // Skip to: 1443
+/* 267 */ MCD::OPC_CheckField, 16, 10, 160, 4, 144, 4, 0, // Skip to: 1443
+/* 275 */ MCD::OPC_Decode, 177, 11, 216, 1, // Opcode: FNEG_D64
+/* 280 */ MCD::OPC_FilterValue, 8, 35, 0, 0, // Skip to: 320
+/* 285 */ MCD::OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 288 */ MCD::OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 304
+/* 294 */ MCD::OPC_CheckPredicate, 98, 120, 4, 0, // Skip to: 1443
+/* 299 */ MCD::OPC_Decode, 248, 16, 209, 1, // Opcode: ROUND_L_S
+/* 304 */ MCD::OPC_FilterValue, 160, 4, 109, 4, 0, // Skip to: 1443
+/* 310 */ MCD::OPC_CheckPredicate, 99, 104, 4, 0, // Skip to: 1443
+/* 315 */ MCD::OPC_Decode, 246, 16, 216, 1, // Opcode: ROUND_L_D64
+/* 320 */ MCD::OPC_FilterValue, 9, 35, 0, 0, // Skip to: 360
+/* 325 */ MCD::OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 328 */ MCD::OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 344
+/* 334 */ MCD::OPC_CheckPredicate, 98, 80, 4, 0, // Skip to: 1443
+/* 339 */ MCD::OPC_Decode, 154, 20, 209, 1, // Opcode: TRUNC_L_S
+/* 344 */ MCD::OPC_FilterValue, 160, 4, 69, 4, 0, // Skip to: 1443
+/* 350 */ MCD::OPC_CheckPredicate, 99, 64, 4, 0, // Skip to: 1443
+/* 355 */ MCD::OPC_Decode, 152, 20, 216, 1, // Opcode: TRUNC_L_D64
+/* 360 */ MCD::OPC_FilterValue, 10, 35, 0, 0, // Skip to: 400
+/* 365 */ MCD::OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 368 */ MCD::OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 384
+/* 374 */ MCD::OPC_CheckPredicate, 98, 40, 4, 0, // Skip to: 1443
+/* 379 */ MCD::OPC_Decode, 213, 6, 209, 1, // Opcode: CEIL_L_S
+/* 384 */ MCD::OPC_FilterValue, 160, 4, 29, 4, 0, // Skip to: 1443
+/* 390 */ MCD::OPC_CheckPredicate, 99, 24, 4, 0, // Skip to: 1443
+/* 395 */ MCD::OPC_Decode, 211, 6, 216, 1, // Opcode: CEIL_L_D64
+/* 400 */ MCD::OPC_FilterValue, 11, 35, 0, 0, // Skip to: 440
+/* 405 */ MCD::OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 408 */ MCD::OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 424
+/* 414 */ MCD::OPC_CheckPredicate, 98, 0, 4, 0, // Skip to: 1443
+/* 419 */ MCD::OPC_Decode, 138, 11, 209, 1, // Opcode: FLOOR_L_S
+/* 424 */ MCD::OPC_FilterValue, 160, 4, 245, 3, 0, // Skip to: 1443
+/* 430 */ MCD::OPC_CheckPredicate, 99, 240, 3, 0, // Skip to: 1443
+/* 435 */ MCD::OPC_Decode, 136, 11, 216, 1, // Opcode: FLOOR_L_D64
+/* 440 */ MCD::OPC_FilterValue, 12, 18, 0, 0, // Skip to: 463
+/* 445 */ MCD::OPC_CheckPredicate, 98, 225, 3, 0, // Skip to: 1443
+/* 450 */ MCD::OPC_CheckField, 16, 10, 160, 4, 217, 3, 0, // Skip to: 1443
+/* 458 */ MCD::OPC_Decode, 251, 16, 249, 2, // Opcode: ROUND_W_D64
+/* 463 */ MCD::OPC_FilterValue, 13, 18, 0, 0, // Skip to: 486
+/* 468 */ MCD::OPC_CheckPredicate, 98, 202, 3, 0, // Skip to: 1443
+/* 473 */ MCD::OPC_CheckField, 16, 10, 160, 4, 194, 3, 0, // Skip to: 1443
+/* 481 */ MCD::OPC_Decode, 157, 20, 249, 2, // Opcode: TRUNC_W_D64
+/* 486 */ MCD::OPC_FilterValue, 14, 18, 0, 0, // Skip to: 509
+/* 491 */ MCD::OPC_CheckPredicate, 98, 179, 3, 0, // Skip to: 1443
+/* 496 */ MCD::OPC_CheckField, 16, 10, 160, 4, 171, 3, 0, // Skip to: 1443
+/* 504 */ MCD::OPC_Decode, 216, 6, 249, 2, // Opcode: CEIL_W_D64
+/* 509 */ MCD::OPC_FilterValue, 15, 18, 0, 0, // Skip to: 532
+/* 514 */ MCD::OPC_CheckPredicate, 98, 156, 3, 0, // Skip to: 1443
+/* 519 */ MCD::OPC_CheckField, 16, 10, 160, 4, 148, 3, 0, // Skip to: 1443
+/* 527 */ MCD::OPC_Decode, 141, 11, 249, 2, // Opcode: FLOOR_W_D64
+/* 532 */ MCD::OPC_FilterValue, 17, 47, 0, 0, // Skip to: 584
+/* 537 */ MCD::OPC_ExtractField, 16, 2, // Inst{17-16} ...
+/* 540 */ MCD::OPC_FilterValue, 0, 17, 0, 0, // Skip to: 562
+/* 545 */ MCD::OPC_CheckPredicate, 100, 125, 3, 0, // Skip to: 1443
+/* 550 */ MCD::OPC_CheckField, 21, 5, 17, 118, 3, 0, // Skip to: 1443
+/* 557 */ MCD::OPC_Decode, 211, 14, 250, 2, // Opcode: MOVF_D64
+/* 562 */ MCD::OPC_FilterValue, 1, 108, 3, 0, // Skip to: 1443
+/* 567 */ MCD::OPC_CheckPredicate, 100, 103, 3, 0, // Skip to: 1443
+/* 572 */ MCD::OPC_CheckField, 21, 5, 17, 96, 3, 0, // Skip to: 1443
+/* 579 */ MCD::OPC_Decode, 231, 14, 250, 2, // Opcode: MOVT_D64
+/* 584 */ MCD::OPC_FilterValue, 18, 17, 0, 0, // Skip to: 606
+/* 589 */ MCD::OPC_CheckPredicate, 100, 81, 3, 0, // Skip to: 1443
+/* 594 */ MCD::OPC_CheckField, 21, 5, 17, 74, 3, 0, // Skip to: 1443
+/* 601 */ MCD::OPC_Decode, 243, 14, 251, 2, // Opcode: MOVZ_I_D64
+/* 606 */ MCD::OPC_FilterValue, 19, 17, 0, 0, // Skip to: 628
+/* 611 */ MCD::OPC_CheckPredicate, 100, 59, 3, 0, // Skip to: 1443
+/* 616 */ MCD::OPC_CheckField, 21, 5, 17, 52, 3, 0, // Skip to: 1443
+/* 623 */ MCD::OPC_Decode, 223, 14, 251, 2, // Opcode: MOVN_I_D64
+/* 628 */ MCD::OPC_FilterValue, 21, 18, 0, 0, // Skip to: 651
+/* 633 */ MCD::OPC_CheckPredicate, 101, 37, 3, 0, // Skip to: 1443
+/* 638 */ MCD::OPC_CheckField, 16, 10, 160, 4, 29, 3, 0, // Skip to: 1443
+/* 646 */ MCD::OPC_Decode, 226, 16, 216, 1, // Opcode: RECIP_D64
+/* 651 */ MCD::OPC_FilterValue, 22, 18, 0, 0, // Skip to: 674
+/* 656 */ MCD::OPC_CheckPredicate, 101, 14, 3, 0, // Skip to: 1443
+/* 661 */ MCD::OPC_CheckField, 16, 10, 160, 4, 6, 3, 0, // Skip to: 1443
+/* 669 */ MCD::OPC_Decode, 131, 17, 216, 1, // Opcode: RSQRT_D64
+/* 674 */ MCD::OPC_FilterValue, 32, 35, 0, 0, // Skip to: 714
+/* 679 */ MCD::OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 682 */ MCD::OPC_FilterValue, 160, 4, 10, 0, 0, // Skip to: 698
+/* 688 */ MCD::OPC_CheckPredicate, 96, 238, 2, 0, // Skip to: 1443
+/* 693 */ MCD::OPC_Decode, 151, 8, 249, 2, // Opcode: CVT_S_D64
+/* 698 */ MCD::OPC_FilterValue, 160, 5, 227, 2, 0, // Skip to: 1443
+/* 704 */ MCD::OPC_CheckPredicate, 102, 222, 2, 0, // Skip to: 1443
+/* 709 */ MCD::OPC_Decode, 153, 8, 249, 2, // Opcode: CVT_S_L
+/* 714 */ MCD::OPC_FilterValue, 33, 51, 0, 0, // Skip to: 770
+/* 719 */ MCD::OPC_ExtractField, 16, 10, // Inst{25-16} ...
+/* 722 */ MCD::OPC_FilterValue, 128, 4, 10, 0, 0, // Skip to: 738
+/* 728 */ MCD::OPC_CheckPredicate, 96, 198, 2, 0, // Skip to: 1443
+/* 733 */ MCD::OPC_Decode, 138, 8, 209, 1, // Opcode: CVT_D64_S
+/* 738 */ MCD::OPC_FilterValue, 128, 5, 10, 0, 0, // Skip to: 754
+/* 744 */ MCD::OPC_CheckPredicate, 96, 182, 2, 0, // Skip to: 1443
+/* 749 */ MCD::OPC_Decode, 140, 8, 209, 1, // Opcode: CVT_D64_W
+/* 754 */ MCD::OPC_FilterValue, 160, 5, 171, 2, 0, // Skip to: 1443
+/* 760 */ MCD::OPC_CheckPredicate, 102, 166, 2, 0, // Skip to: 1443
+/* 765 */ MCD::OPC_Decode, 137, 8, 216, 1, // Opcode: CVT_D64_L
+/* 770 */ MCD::OPC_FilterValue, 36, 18, 0, 0, // Skip to: 793
+/* 775 */ MCD::OPC_CheckPredicate, 96, 151, 2, 0, // Skip to: 1443
+/* 780 */ MCD::OPC_CheckField, 16, 10, 160, 4, 143, 2, 0, // Skip to: 1443
+/* 788 */ MCD::OPC_Decode, 160, 8, 249, 2, // Opcode: CVT_W_D64
+/* 793 */ MCD::OPC_FilterValue, 48, 24, 0, 0, // Skip to: 822
+/* 798 */ MCD::OPC_CheckPredicate, 103, 128, 2, 0, // Skip to: 1443
+/* 803 */ MCD::OPC_CheckField, 21, 5, 17, 121, 2, 0, // Skip to: 1443
+/* 810 */ MCD::OPC_CheckField, 6, 2, 0, 114, 2, 0, // Skip to: 1443
+/* 817 */ MCD::OPC_Decode, 173, 8, 252, 2, // Opcode: C_F_D64
+/* 822 */ MCD::OPC_FilterValue, 49, 24, 0, 0, // Skip to: 851
+/* 827 */ MCD::OPC_CheckPredicate, 103, 99, 2, 0, // Skip to: 1443
+/* 832 */ MCD::OPC_CheckField, 21, 5, 17, 92, 2, 0, // Skip to: 1443
+/* 839 */ MCD::OPC_CheckField, 6, 2, 0, 85, 2, 0, // Skip to: 1443
+/* 846 */ MCD::OPC_Decode, 129, 9, 252, 2, // Opcode: C_UN_D64
+/* 851 */ MCD::OPC_FilterValue, 50, 24, 0, 0, // Skip to: 880
+/* 856 */ MCD::OPC_CheckPredicate, 103, 70, 2, 0, // Skip to: 1443
+/* 861 */ MCD::OPC_CheckField, 21, 5, 17, 63, 2, 0, // Skip to: 1443
+/* 868 */ MCD::OPC_CheckField, 6, 2, 0, 56, 2, 0, // Skip to: 1443
+/* 875 */ MCD::OPC_Decode, 167, 8, 252, 2, // Opcode: C_EQ_D64
+/* 880 */ MCD::OPC_FilterValue, 51, 24, 0, 0, // Skip to: 909
+/* 885 */ MCD::OPC_CheckPredicate, 103, 41, 2, 0, // Skip to: 1443
+/* 890 */ MCD::OPC_CheckField, 21, 5, 17, 34, 2, 0, // Skip to: 1443
+/* 897 */ MCD::OPC_CheckField, 6, 2, 0, 27, 2, 0, // Skip to: 1443
+/* 904 */ MCD::OPC_Decode, 239, 8, 252, 2, // Opcode: C_UEQ_D64
+/* 909 */ MCD::OPC_FilterValue, 52, 24, 0, 0, // Skip to: 938
+/* 914 */ MCD::OPC_CheckPredicate, 103, 12, 2, 0, // Skip to: 1443
+/* 919 */ MCD::OPC_CheckField, 21, 5, 17, 5, 2, 0, // Skip to: 1443
+/* 926 */ MCD::OPC_CheckField, 6, 2, 0, 254, 1, 0, // Skip to: 1443
+/* 933 */ MCD::OPC_Decode, 221, 8, 252, 2, // Opcode: C_OLT_D64
+/* 938 */ MCD::OPC_FilterValue, 53, 24, 0, 0, // Skip to: 967
+/* 943 */ MCD::OPC_CheckPredicate, 103, 239, 1, 0, // Skip to: 1443
+/* 948 */ MCD::OPC_CheckField, 21, 5, 17, 232, 1, 0, // Skip to: 1443
+/* 955 */ MCD::OPC_CheckField, 6, 2, 0, 225, 1, 0, // Skip to: 1443
+/* 962 */ MCD::OPC_Decode, 251, 8, 252, 2, // Opcode: C_ULT_D64
+/* 967 */ MCD::OPC_FilterValue, 54, 24, 0, 0, // Skip to: 996
+/* 972 */ MCD::OPC_CheckPredicate, 103, 210, 1, 0, // Skip to: 1443
+/* 977 */ MCD::OPC_CheckField, 21, 5, 17, 203, 1, 0, // Skip to: 1443
+/* 984 */ MCD::OPC_CheckField, 6, 2, 0, 196, 1, 0, // Skip to: 1443
+/* 991 */ MCD::OPC_Decode, 215, 8, 252, 2, // Opcode: C_OLE_D64
+/* 996 */ MCD::OPC_FilterValue, 55, 24, 0, 0, // Skip to: 1025
+/* 1001 */ MCD::OPC_CheckPredicate, 103, 181, 1, 0, // Skip to: 1443
+/* 1006 */ MCD::OPC_CheckField, 21, 5, 17, 174, 1, 0, // Skip to: 1443
+/* 1013 */ MCD::OPC_CheckField, 6, 2, 0, 167, 1, 0, // Skip to: 1443
+/* 1020 */ MCD::OPC_Decode, 245, 8, 252, 2, // Opcode: C_ULE_D64
+/* 1025 */ MCD::OPC_FilterValue, 56, 24, 0, 0, // Skip to: 1054
+/* 1030 */ MCD::OPC_CheckPredicate, 103, 152, 1, 0, // Skip to: 1443
+/* 1035 */ MCD::OPC_CheckField, 21, 5, 17, 145, 1, 0, // Skip to: 1443
+/* 1042 */ MCD::OPC_CheckField, 6, 2, 0, 138, 1, 0, // Skip to: 1443
+/* 1049 */ MCD::OPC_Decode, 233, 8, 252, 2, // Opcode: C_SF_D64
+/* 1054 */ MCD::OPC_FilterValue, 57, 24, 0, 0, // Skip to: 1083
+/* 1059 */ MCD::OPC_CheckPredicate, 103, 123, 1, 0, // Skip to: 1443
+/* 1064 */ MCD::OPC_CheckField, 21, 5, 17, 116, 1, 0, // Skip to: 1443
+/* 1071 */ MCD::OPC_CheckField, 6, 2, 0, 109, 1, 0, // Skip to: 1443
+/* 1078 */ MCD::OPC_Decode, 197, 8, 252, 2, // Opcode: C_NGLE_D64
+/* 1083 */ MCD::OPC_FilterValue, 58, 24, 0, 0, // Skip to: 1112
+/* 1088 */ MCD::OPC_CheckPredicate, 103, 94, 1, 0, // Skip to: 1443
+/* 1093 */ MCD::OPC_CheckField, 21, 5, 17, 87, 1, 0, // Skip to: 1443
+/* 1100 */ MCD::OPC_CheckField, 6, 2, 0, 80, 1, 0, // Skip to: 1443
+/* 1107 */ MCD::OPC_Decode, 227, 8, 252, 2, // Opcode: C_SEQ_D64
+/* 1112 */ MCD::OPC_FilterValue, 59, 24, 0, 0, // Skip to: 1141
+/* 1117 */ MCD::OPC_CheckPredicate, 103, 65, 1, 0, // Skip to: 1443
+/* 1122 */ MCD::OPC_CheckField, 21, 5, 17, 58, 1, 0, // Skip to: 1443
+/* 1129 */ MCD::OPC_CheckField, 6, 2, 0, 51, 1, 0, // Skip to: 1443
+/* 1136 */ MCD::OPC_Decode, 203, 8, 252, 2, // Opcode: C_NGL_D64
+/* 1141 */ MCD::OPC_FilterValue, 60, 24, 0, 0, // Skip to: 1170
+/* 1146 */ MCD::OPC_CheckPredicate, 103, 36, 1, 0, // Skip to: 1443
+/* 1151 */ MCD::OPC_CheckField, 21, 5, 17, 29, 1, 0, // Skip to: 1443
+/* 1158 */ MCD::OPC_CheckField, 6, 2, 0, 22, 1, 0, // Skip to: 1443
+/* 1165 */ MCD::OPC_Decode, 185, 8, 252, 2, // Opcode: C_LT_D64
+/* 1170 */ MCD::OPC_FilterValue, 61, 24, 0, 0, // Skip to: 1199
+/* 1175 */ MCD::OPC_CheckPredicate, 103, 7, 1, 0, // Skip to: 1443
+/* 1180 */ MCD::OPC_CheckField, 21, 5, 17, 0, 1, 0, // Skip to: 1443
+/* 1187 */ MCD::OPC_CheckField, 6, 2, 0, 249, 0, 0, // Skip to: 1443
+/* 1194 */ MCD::OPC_Decode, 191, 8, 252, 2, // Opcode: C_NGE_D64
+/* 1199 */ MCD::OPC_FilterValue, 62, 24, 0, 0, // Skip to: 1228
+/* 1204 */ MCD::OPC_CheckPredicate, 103, 234, 0, 0, // Skip to: 1443
+/* 1209 */ MCD::OPC_CheckField, 21, 5, 17, 227, 0, 0, // Skip to: 1443
+/* 1216 */ MCD::OPC_CheckField, 6, 2, 0, 220, 0, 0, // Skip to: 1443
+/* 1223 */ MCD::OPC_Decode, 179, 8, 252, 2, // Opcode: C_LE_D64
+/* 1228 */ MCD::OPC_FilterValue, 63, 210, 0, 0, // Skip to: 1443
+/* 1233 */ MCD::OPC_CheckPredicate, 103, 205, 0, 0, // Skip to: 1443
+/* 1238 */ MCD::OPC_CheckField, 21, 5, 17, 198, 0, 0, // Skip to: 1443
+/* 1245 */ MCD::OPC_CheckField, 6, 2, 0, 191, 0, 0, // Skip to: 1443
+/* 1252 */ MCD::OPC_Decode, 209, 8, 252, 2, // Opcode: C_NGT_D64
+/* 1257 */ MCD::OPC_FilterValue, 19, 151, 0, 0, // Skip to: 1413
+/* 1262 */ MCD::OPC_ExtractField, 0, 6, // Inst{5-0} ...
+/* 1265 */ MCD::OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1287
+/* 1270 */ MCD::OPC_CheckPredicate, 104, 168, 0, 0, // Skip to: 1443
+/* 1275 */ MCD::OPC_CheckField, 11, 5, 0, 161, 0, 0, // Skip to: 1443
+/* 1282 */ MCD::OPC_Decode, 231, 12, 253, 2, // Opcode: LDXC164
+/* 1287 */ MCD::OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1309
+/* 1292 */ MCD::OPC_CheckPredicate, 105, 146, 0, 0, // Skip to: 1443
+/* 1297 */ MCD::OPC_CheckField, 11, 5, 0, 139, 0, 0, // Skip to: 1443
+/* 1304 */ MCD::OPC_Decode, 141, 13, 253, 2, // Opcode: LUXC164
+/* 1309 */ MCD::OPC_FilterValue, 9, 17, 0, 0, // Skip to: 1331
+/* 1314 */ MCD::OPC_CheckPredicate, 104, 124, 0, 0, // Skip to: 1443
+/* 1319 */ MCD::OPC_CheckField, 6, 5, 0, 117, 0, 0, // Skip to: 1443
+/* 1326 */ MCD::OPC_Decode, 183, 17, 254, 2, // Opcode: SDXC164
+/* 1331 */ MCD::OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1353
+/* 1336 */ MCD::OPC_CheckPredicate, 105, 102, 0, 0, // Skip to: 1443
+/* 1341 */ MCD::OPC_CheckField, 6, 5, 0, 95, 0, 0, // Skip to: 1443
+/* 1348 */ MCD::OPC_Decode, 168, 19, 254, 2, // Opcode: SUXC164
+/* 1353 */ MCD::OPC_FilterValue, 33, 10, 0, 0, // Skip to: 1368
+/* 1358 */ MCD::OPC_CheckPredicate, 106, 80, 0, 0, // Skip to: 1443
+/* 1363 */ MCD::OPC_Decode, 215, 13, 255, 2, // Opcode: MADD_D64
+/* 1368 */ MCD::OPC_FilterValue, 41, 10, 0, 0, // Skip to: 1383
+/* 1373 */ MCD::OPC_CheckPredicate, 106, 65, 0, 0, // Skip to: 1443
+/* 1378 */ MCD::OPC_Decode, 138, 15, 255, 2, // Opcode: MSUB_D64
+/* 1383 */ MCD::OPC_FilterValue, 49, 10, 0, 0, // Skip to: 1398
+/* 1388 */ MCD::OPC_CheckPredicate, 107, 50, 0, 0, // Skip to: 1443
+/* 1393 */ MCD::OPC_Decode, 247, 15, 255, 2, // Opcode: NMADD_D64
+/* 1398 */ MCD::OPC_FilterValue, 57, 40, 0, 0, // Skip to: 1443
+/* 1403 */ MCD::OPC_CheckPredicate, 107, 35, 0, 0, // Skip to: 1443
+/* 1408 */ MCD::OPC_Decode, 252, 15, 255, 2, // Opcode: NMSUB_D64
+/* 1413 */ MCD::OPC_FilterValue, 53, 10, 0, 0, // Skip to: 1428
+/* 1418 */ MCD::OPC_CheckPredicate, 98, 20, 0, 0, // Skip to: 1443
+/* 1423 */ MCD::OPC_Decode, 216, 12, 205, 2, // Opcode: LDC164
+/* 1428 */ MCD::OPC_FilterValue, 61, 10, 0, 0, // Skip to: 1443
+/* 1433 */ MCD::OPC_CheckPredicate, 98, 5, 0, 0, // Skip to: 1443
+/* 1438 */ MCD::OPC_Decode, 171, 17, 205, 2, // Opcode: SDC164
+/* 1443 */ MCD::OPC_Fail,
+ 0
+};
+
+static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset& Bits) {
+ switch (Idx) {
+ default: llvm_unreachable("Invalid index!");
+ case 0:
+ return (Bits[Mips::FeatureMips16]);
+ case 1:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureCnMips] && !Bits[Mips::FeatureMicroMips]);
+ case 2:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureCnMips] && !Bits[Mips::FeatureMicroMips]);
+ case 3:
+ return (Bits[Mips::FeatureCnMips]);
+ case 4:
+ return (Bits[Mips::FeatureMips64] && Bits[Mips::FeatureCnMips] && !Bits[Mips::FeatureMicroMips]);
+ case 5:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureMips32r6]);
+ case 6:
+ return (Bits[Mips::FeatureMicroMips]);
+ case 7:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureDSP]);
+ case 8:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureDSPR2]);
+ case 9:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureMips32r5] && Bits[Mips::FeatureVirt]);
+ case 10:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureDSPR3]);
+ case 11:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureMips32r6] && Bits[Mips::FeatureDSP]);
+ case 12:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureSoftFloat]);
+ case 13:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMadd4]);
+ case 14:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureSoftFloat]);
+ case 15:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMadd4]);
+ case 16:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureSoftFloat]);
+ case 17:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureSoftFloat]);
+ case 18:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureSoftFloat]);
+ case 19:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureSoftFloat]);
+ case 20:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureSoftFloat]);
+ case 21:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureEVA]);
+ case 22:
+ return (Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureMips32r6] && Bits[Mips::FeatureEVA]);
+ case 23:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureSoftFloat]);
+ case 24:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureMips32r6]);
+ case 25:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureMips32r6] && Bits[Mips::FeatureGINV]);
+ case 26:
+ return (Bits[Mips::FeatureMicroMips] && Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureSoftFloat]);
+ case 27:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureMicroMips]);
+ case 28:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r2] && !Bits[Mips::FeatureMicroMips]);
+ case 29:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips4_32] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 30:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMSA]);
+ case 31:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 32:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6]);
+ case 33:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureUseIndirectJumpsHazard]);
+ case 34:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32]);
+ case 35:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips4_32] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 36:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureMicroMips]);
+ case 37:
+ return (Bits[Mips::FeatureDSP]);
+ case 38:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMSA] && Bits[Mips::FeatureMips64]);
+ case 39:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 40:
+ return (Bits[Mips::FeatureDSP] && !Bits[Mips::FeatureMicroMips]);
+ case 41:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r5] && Bits[Mips::FeatureVirt] && !Bits[Mips::FeatureMicroMips]);
+ case 42:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMT] && !Bits[Mips::FeatureMicroMips]);
+ case 43:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips3_32] && !Bits[Mips::FeatureMicroMips]);
+ case 44:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r2] && Bits[Mips::FeatureEVA] && !Bits[Mips::FeatureMicroMips]);
+ case 45:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r5] && !Bits[Mips::FeatureMicroMips]);
+ case 46:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32] && !Bits[Mips::FeatureMicroMips]);
+ case 47:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 48:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips3] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 49:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips32r2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 50:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 51:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 52:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 53:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 54:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 55:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips3_32r2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 56:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 57:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 58:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 59:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 60:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat]);
+ case 61:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 62:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips5_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 63:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureMadd4]);
+ case 64:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureMadd4]);
+ case 65:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMadd4] && !Bits[Mips::FeatureMicroMips]);
+ case 66:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMadd4] && !Bits[Mips::FeatureMicroMips]);
+ case 67:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 68:
+ return (Bits[Mips::FeatureDSPR2]);
+ case 69:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && Bits[Mips::FeatureEVA] && !Bits[Mips::FeatureMicroMips]);
+ case 70:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips3_32] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 71:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeaturePTR64Bit] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 72:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeaturePTR64Bit] && !Bits[Mips::FeatureMicroMips]);
+ case 73:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeaturePTR64Bit] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 74:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r6]);
+ case 75:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMicroMips]);
+ case 76:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 77:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeatureGP64Bit] && Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMicroMips]);
+ case 78:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 79:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r6] && Bits[Mips::FeatureCRC] && !Bits[Mips::FeatureMicroMips]);
+ case 80:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips64r6] && Bits[Mips::FeatureCRC] && !Bits[Mips::FeatureMicroMips]);
+ case 81:
+ return (!Bits[Mips::FeatureMips16] && !Bits[Mips::FeaturePTR64Bit] && Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMicroMips]);
+ case 82:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips32r6] && Bits[Mips::FeatureGINV] && !Bits[Mips::FeatureMicroMips]);
+ case 83:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips64r6]);
+ case 84:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureGP64Bit] && Bits[Mips::FeatureMips64r6]);
+ case 85:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureGP64Bit] && Bits[Mips::FeatureMips32r6]);
+ case 86:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeaturePTR64Bit] && Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 87:
+ return (!Bits[Mips::FeatureMips16]);
+ case 88:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips3] && !Bits[Mips::FeatureMicroMips]);
+ case 89:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips64r2] && !Bits[Mips::FeatureMicroMips]);
+ case 90:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips3] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 91:
+ return (Bits[Mips::FeatureMips64]);
+ case 92:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips64r5] && Bits[Mips::FeatureVirt]);
+ case 93:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips3] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6]);
+ case 94:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureMips64] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureMicroMips]);
+ case 95:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureDSP]);
+ case 96:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 97:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips32r2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 98:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 99:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips3_32] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 100:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 101:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 102:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips3_32r2] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 103:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 104:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat]);
+ case 105:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips5_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips]);
+ case 106:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMicroMips] && !Bits[Mips::FeatureMadd4]);
+ case 107:
+ return (!Bits[Mips::FeatureMips16] && Bits[Mips::FeatureFP64Bit] && Bits[Mips::FeatureMips4_32r2] && !Bits[Mips::FeatureMips32r6] && !Bits[Mips::FeatureMips64r6] && !Bits[Mips::FeatureSoftFloat] && !Bits[Mips::FeatureMadd4] && !Bits[Mips::FeatureMicroMips]);
+ }
+}
+
+template<typename InsnType>
+static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
+ uint64_t Address, const void *Decoder, bool &DecodeComplete) {
+ DecodeComplete = true;
+ InsnType tmp;
+ switch (Idx) {
+ default: llvm_unreachable("Invalid index!");
+ case 0:
+ return S;
+ case 1:
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 2:
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 3:
+ tmp = 0;
+ tmp |= fieldFromInstruction(insn, 3, 2) << 3;
+ tmp |= fieldFromInstruction(insn, 5, 3) << 0;
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 4:
+ tmp = fieldFromInstruction(insn, 0, 4);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 5:
+ tmp = fieldFromInstruction(insn, 2, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 6:
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 7:
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 8:
+ tmp = 0;
+ tmp |= fieldFromInstruction(insn, 0, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 16, 5) << 11;
+ tmp |= fieldFromInstruction(insn, 21, 6) << 5;
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 9:
+ tmp = fieldFromInstruction(insn, 5, 3);
+ if (DecodeCPU16RegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 10:
+ if (DecodeFMem3(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 11:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 12:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 13:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 14:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 15:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 16:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 10);
+ if (DecodeSImmWithOffsetAndScale<10>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 17:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 11, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 18:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 19:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 1, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 20:
+ if (DecodeMemMMImm4(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 21:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 22:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 1, 3);
+ if (DecodePOOL16BEncodedField(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 23:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 4);
+ if (DecodeANDI16Imm(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 24:
+ tmp = fieldFromInstruction(insn, 3, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 25:
+ tmp = fieldFromInstruction(insn, 3, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 3, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 26:
+ if (DecodeMemMMReglistImm4Lsl2(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 27:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 28:
+ tmp = fieldFromInstruction(insn, 0, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 29:
+ tmp = fieldFromInstruction(insn, 0, 5);
+ if (DecodeUImmWithOffsetAndScale<5, 0, 4>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 30:
+ if (DecodeMemMMSPImm5Lsl2(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 31:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 1, 4);
+ if (DecodeSImmWithOffsetAndScale<4>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 32:
+ tmp = fieldFromInstruction(insn, 1, 9);
+ if (DecodeSimm9SP(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 33:
+ if (DecodeMemMMGPImm7Lsl2(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 34:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 1, 3);
+ if (DecodeAddiur2Simm7(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 35:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 1, 6);
+ if (DecodeUImmWithOffsetAndScale<6, 0, 4>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 36:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 1, 3);
+ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 37:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 7);
+ if (DecodeBranchTarget7MM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 38:
+ tmp = fieldFromInstruction(insn, 0, 10);
+ if (DecodeBranchTarget10MM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 39:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 7);
+ if (DecodeLi16Imm(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 40:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 41:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 42:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 43:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 44:
+ tmp = fieldFromInstruction(insn, 16, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 6, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 45:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 46:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 47:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 48:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 49:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 50:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 51:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 52:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 53:
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 6);
+ if (DecodeSImmWithOffsetAndScale<6>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 54:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeUImmWithOffset<5, 1>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 55:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 56:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 57:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 58:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 59:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 60:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 61:
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 62:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 13, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 63:
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 64:
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 65:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 14, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 66:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 67:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 68:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 69:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 70:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 71:
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 72:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 73:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 74:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 75:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 76:
+ tmp = fieldFromInstruction(insn, 16, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 77:
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 78:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 79:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 80:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 81:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 13, 8);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 82:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 14, 7);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 83:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 14, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 84:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 10);
+ if (DecodeSImmWithOffsetAndScale<10>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 85:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeSImmWithOffsetAndScale<16>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 86:
+ if (DecodeMemMMImm16(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 87:
+ if (DecodeMemMMImm12(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 88:
+ if (DecodeCacheOpMM(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 89:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 90:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeSImmWithOffsetAndScale<16>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 91:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 92:
+ if (DecodeSyncI_MM(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 93:
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget1SImm16(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 94:
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 95:
+ tmp = fieldFromInstruction(insn, 18, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 96:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 97:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 98:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 99:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 100:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 101:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 13, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 102:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 103:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 13, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 104:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 105:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 106:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 107:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 108:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 109:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 110:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 111:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 13, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 112:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 113:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 114:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 115:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 116:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 117:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 118:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 119:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 120:
+ tmp = fieldFromInstruction(insn, 13, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 121:
+ tmp = fieldFromInstruction(insn, 13, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 122:
+ if (DecodeMemMMImm9(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 123:
+ if (DecodePrefeOpMM(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 124:
+ if (DecodeJumpTargetMM(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 125:
+ tmp = fieldFromInstruction(insn, 23, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 23);
+ if (DecodeSimm23Lsl2(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 126:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 127:
+ if (DecodeFMemMMR2(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 128:
+ if (DecodeMem(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 129:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 130:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 131:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 132:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 133:
+ tmp = fieldFromInstruction(insn, 1, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 134:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 135:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRMM16RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 136:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 137:
+ tmp = fieldFromInstruction(insn, 5, 5);
+ if (DecodeUImmWithOffsetAndScale<5, 0, 4>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 138:
+ tmp = fieldFromInstruction(insn, 6, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 139:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeMovePRegPair(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0;
+ tmp |= fieldFromInstruction(insn, 0, 2) << 0;
+ tmp |= fieldFromInstruction(insn, 3, 1) << 2;
+ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 4, 3);
+ if (DecodeGPRMM16MovePRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 140:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 141:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 9, 2);
+ if (DecodeUImmWithOffset<2, 1>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 142:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 9, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 143:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 9, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 144:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 145:
+ if (DecodeLoadByte15(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 146:
+ if (DecodeFMemCop2MMR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 147:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 148:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTargetMM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 149:
+ if (DecodeSynciR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 150:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 151:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 152:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 153:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 154:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 155:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 156:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 157:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 158:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 159:
+ if (DecodePOP35GroupBranchMMR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 160:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 19);
+ if (DecodeSimm19Lsl2(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 161:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeSImmWithOffsetAndScale<16>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 162:
+ if (DecodePOP37GroupBranchMMR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 163:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 21);
+ if (DecodeBranchTarget21MM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 164:
+ tmp = fieldFromInstruction(insn, 0, 26);
+ if (DecodeBranchTarget26MM(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 165:
+ if (DecodeBlezGroupBranchMMR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 166:
+ if (DecodePOP65GroupBranchMMR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 167:
+ if (DecodeBgtzGroupBranchMMR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 168:
+ if (DecodePOP75GroupBranchMMR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 169:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 170:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 18, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 171:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 2);
+ if (DecodeUImmWithOffset<2, 1>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 172:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 173:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 174:
+ tmp = fieldFromInstruction(insn, 6, 20);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 175:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 176:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 177:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 178:
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeHI32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 179:
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeLO32DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 180:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 2);
+ if (DecodeUImmWithOffset<2, 1>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 181:
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 182:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 183:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 184:
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 185:
+ if (DecodeSyncI(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 186:
+ if (DecodeJumpTarget(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 187:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 188:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeSImmWithOffsetAndScale<16>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 189:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 190:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 191:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 192:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 5, 1);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 4, 1);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 193:
+ tmp = fieldFromInstruction(insn, 11, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 194:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 195:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 196:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 197:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 198:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 199:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 200:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCCRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 201:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 202:
+ tmp = fieldFromInstruction(insn, 18, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 203:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 204:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 205:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 206:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 18, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 207:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 208:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 209:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 210:
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 211:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 212:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 213:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 214:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 18, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 215:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 216:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 217:
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 218:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 219:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 220:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 221:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 222:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 223:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 224:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 225:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 226:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 227:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 228:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeAFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 229:
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 230:
+ tmp = 0;
+ tmp |= fieldFromInstruction(insn, 11, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 16, 5) << 0;
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 231:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 8);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 232:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 8);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 233:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 8);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 234:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 8);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 235:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 236:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 237:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 238:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 239:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 240:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 241:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 242:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 243:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 6);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 244:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 245:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 246:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 6);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 247:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 248:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 249:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 250:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 251:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 252:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 253:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 254:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 255:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 256:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 257:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 258:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 259:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 260:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 261:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 262:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 263:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 264:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 265:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 266:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 267:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 268:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 269:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 270:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 271:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 272:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 273:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 274:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 275:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 1);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 276:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 277:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 278:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 279:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 280:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 1);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 281:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSACtrlRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 282:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 283:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 284:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 285:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 1);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 286:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 287:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 4);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 288:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 289:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 290:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 1);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 291:
+ if (DecodeINSVE_DF(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 292:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 293:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 294:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128BRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 295:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 296:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 297:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 298:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 299:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 300:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 301:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128HRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 302:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeMSA128DRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeMSA128WRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 303:
+ if (DecodeMSA128Mem(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 304:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeUImmWithOffset<5, 1>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 305:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeInsSize(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 306:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 307:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 308:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 309:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 310:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 311:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 312:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 313:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 314:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 315:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 316:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 317:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 318:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 319:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 320:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeDSPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 321:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 322:
+ if (DecodeMemEVA(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 323:
+ if (DecodeCacheeOp_CacheOpR6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 324:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 325:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 326:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 327:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 328:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 10);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 329:
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 6);
+ if (DecodeSImmWithOffsetAndScale<6>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 330:
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 2);
+ if (DecodeACC64DSPRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 331:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeHWRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 332:
+ if (DecodeCacheOp(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 333:
+ if (DecodeFMem(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 334:
+ if (DecodeFMem2(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 335:
+ if (DecodeDAHIDATI(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 336:
+ if (DecodeBlezGroupBranch(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 337:
+ if (DecodeBgtzGroupBranch(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 338:
+ if (DecodeAddiGroupBranch(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 339:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 340:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 341:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 342:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 343:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 344:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 345:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGRCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 346:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeBranchTarget(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 347:
+ if (DecodeFMemCop2R6(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 348:
+ if (DecodeBlezlGroupBranch(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 349:
+ if (DecodeBgtzlGroupBranch(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 350:
+ if (DecodeDaddiGroupBranch(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 351:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 352:
+ if (DecodeCRC(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 353:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 354:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 355:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 356:
+ if (DecodeSpecial3LlSc(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 357:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 8, 2);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 358:
+ tmp = fieldFromInstruction(insn, 0, 26);
+ if (DecodeBranchTarget26(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 359:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 21);
+ if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 360:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 18);
+ if (DecodeSimm18Lsl3(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 361:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 21);
+ if (DecodeBranchTarget21(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 362:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 363:
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 364:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 365:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 366:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCOP0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 367:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 368:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeCOP2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 3);
+ MI.addOperand(MCOperand::createImm(tmp));
+ return S;
+ case 369:
+ tmp = fieldFromInstruction(insn, 13, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 370:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 0, 16);
+ if (DecodeSImmWithOffsetAndScale<16>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 371:
+ tmp = 0;
+ tmp |= fieldFromInstruction(insn, 11, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 16, 5) << 0;
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeGPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 372:
+ if (DecodeDEXT(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 373:
+ if (DecodeDINS(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 374:
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 375:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 376:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 377:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 378:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 18, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 379:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeGPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 380:
+ tmp = fieldFromInstruction(insn, 8, 3);
+ if (DecodeFCCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 381:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 382:
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodePtrRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 383:
+ tmp = fieldFromInstruction(insn, 6, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 21, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 11, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 16, 5);
+ if (DecodeFGR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ }
+}
+
+template<typename InsnType>
+static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
+ InsnType insn, uint64_t Address,
+ const void *DisAsm,
+ const MCSubtargetInfo &STI) {
+ const FeatureBitset& Bits = STI.getFeatureBits();
+
+ const uint8_t *Ptr = DecodeTable;
+ uint32_t CurFieldValue = 0;
+ DecodeStatus S = MCDisassembler::Success;
+ while (true) {
+ ptrdiff_t Loc = Ptr - DecodeTable;
+ switch (*Ptr) {
+ default:
+ errs() << Loc << ": Unexpected decode table opcode!\n";
+ return MCDisassembler::Fail;
+ case MCD::OPC_ExtractField: {
+ unsigned Start = *++Ptr;
+ unsigned Len = *++Ptr;
+ ++Ptr;
+ CurFieldValue = fieldFromInstruction(insn, Start, Len);
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_ExtractField(" << Start << ", "
+ << Len << "): " << CurFieldValue << "\n");
+ break;
+ }
+ case MCD::OPC_FilterValue: {
+ // Decode the field value.
+ unsigned Len;
+ InsnType Val = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // Perform the filter operation.
+ if (Val != CurFieldValue)
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_FilterValue(" << Val << ", " << NumToSkip
+ << "): " << ((Val != CurFieldValue) ? "FAIL:" : "PASS:")
+ << " continuing at " << (Ptr - DecodeTable) << "\n");
+
+ break;
+ }
+ case MCD::OPC_CheckField: {
+ unsigned Start = *++Ptr;
+ unsigned Len = *++Ptr;
+ InsnType FieldValue = fieldFromInstruction(insn, Start, Len);
+ // Decode the field value.
+ uint32_t ExpectedValue = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // If the actual and expected values don't match, skip.
+ if (ExpectedValue != FieldValue)
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", "
+ << Len << ", " << ExpectedValue << ", " << NumToSkip
+ << "): FieldValue = " << FieldValue << ", ExpectedValue = "
+ << ExpectedValue << ": "
+ << ((ExpectedValue == FieldValue) ? "PASS\n" : "FAIL\n"));
+ break;
+ }
+ case MCD::OPC_CheckPredicate: {
+ unsigned Len;
+ // Decode the Predicate Index value.
+ unsigned PIdx = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+ // Check the predicate.
+ bool Pred;
+ if (!(Pred = checkDecoderPredicate(PIdx, Bits)))
+ Ptr += NumToSkip;
+ (void)Pred;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate(" << PIdx << "): "
+ << (Pred ? "PASS\n" : "FAIL\n"));
+
+ break;
+ }
+ case MCD::OPC_Decode: {
+ unsigned Len;
+ // Decode the Opcode value.
+ unsigned Opc = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+
+ MI.clear();
+ MI.setOpcode(Opc);
+ bool DecodeComplete;
+ S = decodeToMCInst(S, DecodeIdx, insn, MI, Address, DisAsm, DecodeComplete);
+ assert(DecodeComplete);
+
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
+ << ", using decoder " << DecodeIdx << ": "
+ << (S != MCDisassembler::Fail ? "PASS" : "FAIL") << "\n");
+ return S;
+ }
+ case MCD::OPC_TryDecode: {
+ unsigned Len;
+ // Decode the Opcode value.
+ unsigned Opc = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // Perform the decode operation.
+ MCInst TmpMI;
+ TmpMI.setOpcode(Opc);
+ bool DecodeComplete;
+ S = decodeToMCInst(S, DecodeIdx, insn, TmpMI, Address, DisAsm, DecodeComplete);
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_TryDecode: opcode " << Opc
+ << ", using decoder " << DecodeIdx << ": ");
+
+ if (DecodeComplete) {
+ // Decoding complete.
+ LLVM_DEBUG(dbgs() << (S != MCDisassembler::Fail ? "PASS" : "FAIL") << "\n");
+ MI = TmpMI;
+ return S;
+ } else {
+ assert(S == MCDisassembler::Fail);
+ // If the decoding was incomplete, skip.
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << "FAIL: continuing at " << (Ptr - DecodeTable) << "\n");
+ // Reset decode status. This also drops a SoftFail status that could be
+ // set before the decode attempt.
+ S = MCDisassembler::Success;
+ }
+ break;
+ }
+ case MCD::OPC_SoftFail: {
+ // Decode the mask values.
+ unsigned Len;
+ InsnType PositiveMask = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ InsnType NegativeMask = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ bool Fail = (insn & PositiveMask) || (~insn & NegativeMask);
+ if (Fail)
+ S = MCDisassembler::SoftFail;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_SoftFail: " << (Fail ? "FAIL\n":"PASS\n"));
+ break;
+ }
+ case MCD::OPC_Fail: {
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_Fail\n");
+ return MCDisassembler::Fail;
+ }
+ }
+ }
+ llvm_unreachable("bogosity detected in disassembler state machine!");
+}
+
+
+} // End llvm namespace
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenFastISel.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenFastISel.inc
new file mode 100644
index 0000000..57d88bb
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenFastISel.inc
@@ -0,0 +1,4017 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* "Fast" Instruction Selector for the Mips target *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+// FastEmit Immediate Predicate functions.
+static bool Predicate_immZExt5(int64_t Imm) {
+return Imm == (Imm & 0x1f);
+}
+static bool Predicate_immZExt6(int64_t Imm) {
+return Imm == (Imm & 0x3f);
+}
+static bool Predicate_immSExt6(int64_t Imm) {
+return isInt<6>(Imm);
+}
+static bool Predicate_immZExt4Ptr(int64_t Imm) {
+return isUInt<4>(Imm);
+}
+static bool Predicate_immZExt3Ptr(int64_t Imm) {
+return isUInt<3>(Imm);
+}
+static bool Predicate_immZExt2Ptr(int64_t Imm) {
+return isUInt<2>(Imm);
+}
+static bool Predicate_immZExt1Ptr(int64_t Imm) {
+return isUInt<1>(Imm);
+}
+static bool Predicate_immZExt4(int64_t Imm) {
+return isUInt<4>(Imm);
+}
+static bool Predicate_immZExt3(int64_t Imm) {
+return isUInt<3>(Imm);
+}
+static bool Predicate_immZExt2(int64_t Imm) {
+return isUInt<2>(Imm);
+}
+static bool Predicate_immZExt1(int64_t Imm) {
+return isUInt<1>(Imm);
+}
+static bool Predicate_immZExt8(int64_t Imm) {
+return isUInt<8>(Imm);
+}
+static bool Predicate_immSExtAddiur2(int64_t Imm) {
+return Imm == 1 || Imm == -1 ||
+ ((Imm % 4 == 0) &&
+ Imm < 28 && Imm > 0);
+}
+static bool Predicate_immSExtAddius5(int64_t Imm) {
+return Imm >= -8 && Imm <= 7;
+}
+static bool Predicate_immZExtAndi16(int64_t Imm) {
+return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
+ Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
+ Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
+}
+static bool Predicate_immZExt2Shift(int64_t Imm) {
+return Imm >= 1 && Imm <= 8;
+}
+
+
+// FastEmit functions for ISD::BITCAST.
+
+unsigned fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::MTC1_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::MTC1_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::MTC1, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::DMTC1, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::MFC1_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::MFC1_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::MFC1, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::DMFC1, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0, Op0IsKill);
+ case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::BRIND.
+
+unsigned fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_r(Mips::JrcRx16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::PseudoIndirectBranch_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_r(Mips::PseudoIndirectBranch_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::PseudoIndrectHazardBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_r(Mips::PseudoIndirectBranchR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::PseudoIndirectHazardBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::PseudoIndirectBranch, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::PseudoIndrectHazardBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_r(Mips::PseudoIndirectBranch64R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::PseudoIndirectHazardBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::PseudoIndirectBranch64, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::CTLZ.
+
+unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::CLZ_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::CLZ_R6, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::CLZ, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::DCLZ_R6, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::DCLZ, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::NLZC_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::NLZC_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::NLZC_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::NLZC_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0, Op0IsKill);
+ case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
+ case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
+ case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::CTPOP.
+
+unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasCnMips())) {
+ return fastEmitInst_r(Mips::POP, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasCnMips())) {
+ return fastEmitInst_r(Mips::DPOP, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::PCNT_B, &Mips::MSA128BRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::PCNT_H, &Mips::MSA128HRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::PCNT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::PCNT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0, Op0IsKill);
+ case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
+ case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
+ case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FABS.
+
+unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::FABS_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::FABS_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::FABS_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::FABS_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::FABS_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::FABS_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FABS_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FABS_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0, Op0IsKill);
+ case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FEXP2.
+
+unsigned fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FEXP2_W_1_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FEXP2_D_1_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FLOG2.
+
+unsigned fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FLOG2_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FLOG2_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FNEG.
+
+unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::FNEG_S_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::FNEG_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::FNEG_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::FNEG_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::FNEG_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::FNEG_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::FNEG_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FP_EXTEND.
+
+unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasMSA())) {
+ return fastEmitInst_r(Mips::MSA_FP_EXTEND_W_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasMSA())) {
+ return fastEmitInst_r(Mips::MSA_FP_EXTEND_D_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+switch (RetVT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0, Op0IsKill);
+ default: return 0;
+}
+}
+
+unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::CVT_D32_S_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::CVT_D64_S_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::CVT_D64_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::CVT_D32_S, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0, Op0IsKill);
+ case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FP_ROUND.
+
+unsigned fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f16)
+ return 0;
+ if ((Subtarget->hasMSA())) {
+ return fastEmitInst_r(Mips::MSA_FP_ROUND_W_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasMSA())) {
+ return fastEmitInst_r(Mips::MSA_FP_ROUND_D_PSEUDO, &Mips::MSA128F16RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::CVT_S_D32_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::CVT_S_D64_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::CVT_S_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::CVT_S_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+switch (RetVT.SimpleTy) {
+ case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0, Op0IsKill);
+ case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
+ default: return 0;
+}
+}
+
+unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FP_TO_SINT.
+
+unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FTRUNC_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FTRUNC_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FP_TO_UINT.
+
+unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FTRUNC_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FTRUNC_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FRINT.
+
+unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FRINT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FRINT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FSQRT.
+
+unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::FSQRT_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::FSQRT_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_r(Mips::FSQRT_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::FSQRT_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::FSQRT_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::FSQRT_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FSQRT_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FSQRT_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0, Op0IsKill);
+ case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SIGN_EXTEND.
+
+unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
+ return fastEmitInst_r(Mips::SLL64_32, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SINT_TO_FP.
+
+unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
+ return fastEmitInst_r(Mips::PseudoCVT_S_W, &Mips::FGR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::PseudoCVT_D64_W, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ if ((!Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::PseudoCVT_D32_W, &Mips::AFGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+switch (RetVT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0, Op0IsKill);
+ default: return 0;
+}
+}
+
+unsigned fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::PseudoCVT_D64_L, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FFINT_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FFINT_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0, Op0IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::UINT_TO_FP.
+
+unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FFINT_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::FFINT_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::JmpLink.
+
+unsigned fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_r(Mips::JALR16_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_r(Mips::JumpLinkReg16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill);
+ }
+ if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::JALRHBPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::JALRPseudo, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::JALRHB64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ if ((!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_r(Mips::JALR64Pseudo, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::MFHI.
+
+unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::MFHI_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_r(Mips::MFHI_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::PseudoMFHI, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::PseudoMFHI64, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+switch (RetVT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
+ default: return 0;
+}
+}
+
+unsigned fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::MFLO.
+
+unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::MFLO_DSP_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_r(Mips::MFLO_DSP, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::PseudoMFLO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::PseudoMFLO64, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+switch (RetVT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0, Op0IsKill);
+ default: return 0;
+}
+}
+
+unsigned fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::MTC1_D64.
+
+unsigned fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::MTC1_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::TailCall.
+
+unsigned fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::TAILCALLREG_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_r(Mips::TAILCALLREG_MM, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::TAILCALLHBR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_r(Mips::TAILCALLR6REG, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::TAILCALLREGHB, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::TAILCALLREG, &Mips::GPR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::TAILCALLHB64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_r(Mips::TAILCALL64R6REG, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
+ return fastEmitInst_r(Mips::TAILCALLREGHB64, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_r(Mips::TAILCALLREG64, &Mips::GPR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::TruncIntFP.
+
+unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_r(Mips::TRUNC_W_S, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::TRUNC_L_S, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+switch (RetVT.SimpleTy) {
+ case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0, Op0IsKill);
+ default: return 0;
+}
+}
+
+unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::TRUNC_W_D_MMR6, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_r(Mips::TRUNC_W_MM, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::TRUNC_W_D64, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_r(Mips::TRUNC_W_D32, &Mips::FGR32RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(unsigned Op0, bool Op0IsKill) {
+ if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
+ return fastEmitInst_r(Mips::TRUNC_L_D64, &Mips::FGR64RegClass, Op0, Op0IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+switch (RetVT.SimpleTy) {
+ case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0, Op0IsKill);
+ default: return 0;
+}
+}
+
+unsigned fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0, Op0IsKill);
+ case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::VALL_NONZERO.
+
+unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SNZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SNZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SNZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SNZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::VALL_ZERO.
+
+unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SZ_B_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SZ_H_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SZ_W_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SZ_D_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0, Op0IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0, Op0IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::VANY_NONZERO.
+
+unsigned fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SNZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::VANY_ZERO.
+
+unsigned fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ return fastEmitInst_r(Mips::SZ_V_PSEUDO, &Mips::GPR32RegClass, Op0, Op0IsKill);
+}
+
+unsigned fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill) override {
+ switch (Opcode) {
+ case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
+ case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0, Op0IsKill);
+ case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0, Op0IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADD.
+
+unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::ADDU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::AdduRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_rr(Mips::ADDu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i8)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::ADDU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ADDV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i16)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::ADDQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ADDV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ADDV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ADDV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADDC.
+
+unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::ADDSC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::ADDu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DADDu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADDE.
+
+unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::ADDWC, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::AND.
+
+unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::AndRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::AND_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_rr(Mips::AND_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::AND, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::AND64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::AND_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::AND_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::AND_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::AND_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FADD.
+
+unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_rr(Mips::FADD_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FADD_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_rr(Mips::FADD_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_rr(Mips::FADD_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FADD_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FADD_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::FADD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::FADD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FDIV.
+
+unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_rr(Mips::FDIV_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FDIV_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_rr(Mips::FDIV_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_rr(Mips::FDIV_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FDIV_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FDIV_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::FDIV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::FDIV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FMUL.
+
+unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_rr(Mips::FMUL_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FMUL_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_rr(Mips::FMUL_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_rr(Mips::FMUL_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FMUL_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FMUL_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::FMUL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::FMUL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::FSUB.
+
+unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_rr(Mips::FSUB_S_MM, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FSUB_S, &Mips::FGR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
+ return fastEmitInst_rr(Mips::FSUB_D64_MM, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
+ return fastEmitInst_rr(Mips::FSUB_D32_MM, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FSUB_D64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::FSUB_D32, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::FSUB_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::FSUB_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::MUL.
+
+unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::MultRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MUL_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_rr(Mips::MUL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MUL_R6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::MUL, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DMUL_R6, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasCnMips())) {
+ return fastEmitInst_rr(Mips::DMUL, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MULV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i16)
+ return 0;
+ if ((Subtarget->hasDSPR2())) {
+ return fastEmitInst_rr(Mips::MUL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MULV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MULV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MULV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::MULHS.
+
+unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MUH_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MUH, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DMUH, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::MULHU.
+
+unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MUHU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DMUHU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::OR.
+
+unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::OrRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::OR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_rr(Mips::OR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::OR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::OR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::OR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::OR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::OR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::OR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ROTR.
+
+unsigned fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::ROTRV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::ROTRV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SDIV.
+
+unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DIV_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DIV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DDIV, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::DIV_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::DIV_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::DIV_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::DIV_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SHL.
+
+unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SLLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::SllvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SLLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SLL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SLL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SLL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SLL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SMAX.
+
+unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MAX_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MAX_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MAX_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MAX_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SMIN.
+
+unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MIN_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MIN_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MIN_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MIN_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRA.
+
+unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SRAV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::SravRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SRAV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SRA_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SRA_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SRA_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SRA_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SREM.
+
+unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MOD_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MOD, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DMOD, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MOD_S_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MOD_S_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MOD_S_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MOD_S_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRL.
+
+unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SRLV_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::SrlvRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SRLV, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SRL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SRL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SRL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SRL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SUB.
+
+unsigned fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SUBU16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::SubuRxRyRz16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i8)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::SUBU_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SUBV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i16)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::SUBQ_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SUBV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SUBV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::SUBV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SUBC.
+
+unsigned fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SUBU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SUBu_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::SUBu, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DSUBu, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::UDIV.
+
+unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DIVU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DIVU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DDIVU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::DIV_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::DIV_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::DIV_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::DIV_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::UMAX.
+
+unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MAX_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MAX_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MAX_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MAX_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::UMIN.
+
+unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MIN_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MIN_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MIN_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MIN_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::UREM.
+
+unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MODU_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MODU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::DMODU, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MOD_U_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MOD_U_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MOD_U_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::MOD_U_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::XOR.
+
+unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::XorRxRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::XOR_MMR6, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
+ return fastEmitInst_rr(Mips::XOR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::XOR, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::XOR64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::XOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::XOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::XOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::XOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::BuildPairF64.
+
+unsigned fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::BuildPairF64_64, &Mips::FGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::BuildPairF64, &Mips::AFGR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::DivRem.
+
+unsigned fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::SDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoSDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoDSDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::DivRem16.
+
+unsigned fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::DivRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::DivRemU.
+
+unsigned fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::UDIV_MM_Pseudo, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoUDIV, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoDUDIV, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::DivRemU16.
+
+unsigned fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::DivuRxRy16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::EH_RETURN.
+
+unsigned fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return fastEmitInst_rr(Mips::MIPSeh_return32, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+}
+
+unsigned fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::isVoid)
+ return 0;
+ return fastEmitInst_rr(Mips::MIPSeh_return64, &Mips::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+}
+
+unsigned fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::ILVEV.
+
+unsigned fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::ILVL.
+
+unsigned fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVL_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVL_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVL_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVL_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::ILVOD.
+
+unsigned fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::ILVR.
+
+unsigned fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVR_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVR_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVR_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::ILVR_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::MTLOHI.
+
+unsigned fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((!Subtarget->inMips16Mode())) {
+ return fastEmitInst_rr(Mips::PseudoMTLOHI_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoMTLOHI, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoMTLOHI64, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::Mult.
+
+unsigned fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MULT_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::MULT_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoMULT, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoDMULT, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::Multu.
+
+unsigned fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_rr(Mips::MULTU_DSP_MM, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_rr(Mips::MULTU_DSP, &Mips::ACC64DSPRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoMULTu, &Mips::ACC64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::Untyped)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
+ return fastEmitInst_rr(Mips::PseudoDMULTu, &Mips::ACC128RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::PCKEV.
+
+unsigned fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::PCKEV_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::PCKEV_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::PCKEV_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::PCKEV_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::PCKOD.
+
+unsigned fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::PCKOD_B, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::PCKOD_H, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::PCKOD_W, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::PCKOD_D, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::VNOR.
+
+unsigned fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v16i8)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::NOR_V, &Mips::MSA128BRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v8i16)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::NOR_V_H_PSEUDO, &Mips::MSA128HRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v4i32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::NOR_V_W_PSEUDO, &Mips::MSA128WRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ if (RetVT.SimpleTy != MVT::v2i64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_rr(Mips::NOR_V_D_PSEUDO, &Mips::MSA128DRegClass, Op0, Op0IsKill, Op1, Op1IsKill);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) {
+ switch (VT.SimpleTy) {
+ case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) override {
+ switch (Opcode) {
+ case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::ExtractElementF64.
+
+unsigned fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_ri(Mips::ExtractElementF64_64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
+ return fastEmitInst_ri(Mips::ExtractElementF64, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::SHLL_DSP.
+
+unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::v4i8)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_ri(Mips::SHLL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::v2i16)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_ri(Mips::SHLL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
+ case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::SHRA_DSP.
+
+unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::v4i8)
+ return 0;
+ if ((Subtarget->hasDSPR2())) {
+ return fastEmitInst_ri(Mips::SHRA_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::v2i16)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_ri(Mips::SHRA_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
+ case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for MipsISD::SHRL_DSP.
+
+unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::v4i8)
+ return 0;
+ if ((Subtarget->hasDSP())) {
+ return fastEmitInst_ri(Mips::SHRL_QB, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::v2i16)
+ return 0;
+ if ((Subtarget->hasDSPR2())) {
+ return fastEmitInst_ri(Mips::SHRL_PH, &Mips::DSPRRegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, Op0IsKill, imm1);
+ case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) override {
+ if (VT == MVT::i32 && Predicate_immZExt5(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ if (VT == MVT::i32 && Predicate_immZExt6(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ if (VT == MVT::iPTR && Predicate_immZExt2Ptr(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ if (VT == MVT::iPTR && Predicate_immZExt1Ptr(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ if (VT == MVT::i32 && Predicate_immZExt4(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ if (VT == MVT::i32 && Predicate_immSExtAddiur2(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ if (VT == MVT::i32 && Predicate_immSExtAddius5(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ if (VT == MVT::i32 && Predicate_immZExtAndi16(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ if (VT == MVT::i32 && Predicate_immZExt2Shift(imm1))
+ if (unsigned Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, Op0IsKill, imm1))
+ return Reg;
+
+ switch (Opcode) {
+ case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, Op0IsKill, imm1);
+ case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
+ case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
+ case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ROTR.
+
+unsigned fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::ROTR_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::ROTR, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SHL.
+
+unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::SLL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_ri(Mips::SllX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::SLL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRA.
+
+unsigned fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::SRA_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_ri(Mips::SraX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::SRA, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRL.
+
+unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::SRL_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_ri(Mips::SrlX16, &Mips::CPU16RegsRegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::SRL, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
+ case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
+ case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
+ case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ROTR.
+
+unsigned fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::DROTR, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SHL.
+
+unsigned fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::DSLL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRA.
+
+unsigned fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::DSRA, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRL.
+
+unsigned fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i64)
+ return 0;
+ if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::DSRL, &Mips::GPR64RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
+ case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
+ case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
+ case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
+
+unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::f32)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_ri(Mips::COPY_FW_PSEUDO, &Mips::FGR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
+
+unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::f64)
+ return 0;
+ if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
+ return fastEmitInst_ri(Mips::COPY_FD_PSEUDO, &Mips::FGR64RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
+
+unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMSA())) {
+ return fastEmitInst_ri(Mips::COPY_S_W, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADD.
+
+unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::ADDIUR2_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::ADD.
+
+unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::ADDIUS5_MM, &Mips::GPR32RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::AND.
+
+unsigned fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::ANDI16_MMR6, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
+ }
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::ANDI16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SHL.
+
+unsigned fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::SLL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::SRL.
+
+unsigned fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMicroMipsMode())) {
+ return fastEmitInst_ri(Mips::SRL16_MM, &Mips::GPRMM16RegClass, Op0, Op0IsKill, imm1);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
+ switch (Opcode) {
+ case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
+ case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, Op0IsKill, imm1);
+ default: return 0;
+ }
+}
+
+// FastEmit functions for ISD::Constant.
+
+unsigned fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
+ if (RetVT.SimpleTy != MVT::i32)
+ return 0;
+ if ((Subtarget->inMips16Mode())) {
+ return fastEmitInst_i(Mips::LwConstant32, &Mips::CPU16RegsRegClass, imm0);
+ }
+ return 0;
+}
+
+unsigned fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
+ switch (VT.SimpleTy) {
+ case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
+ default: return 0;
+ }
+}
+
+// Top-level FastEmit function.
+
+unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
+ switch (Opcode) {
+ case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
+ default: return 0;
+ }
+}
+
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenGlobalISel.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenGlobalISel.inc
new file mode 100644
index 0000000..a360f30
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenGlobalISel.inc
@@ -0,0 +1,15608 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Global Instruction Selector for the Mips target *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_GLOBALISEL_PREDICATE_BITSET
+const unsigned MAX_SUBTARGET_PREDICATES = 41;
+using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
+#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
+
+#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
+ mutable MatcherState State;
+ typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
+ typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&) const;
+ const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
+ static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
+ static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
+ bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
+ bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
+ bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
+ const int64_t *getMatchTable() const override;
+ bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
+#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
+
+#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
+, State(0),
+ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
+#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
+
+#ifdef GET_GLOBALISEL_IMPL
+// Bits for subtarget features that participate in instruction matching.
+enum SubtargetFeatureBits : uint8_t {
+ Feature_HasMips2Bit = 7,
+ Feature_HasMips3Bit = 16,
+ Feature_HasMips4_32Bit = 26,
+ Feature_NotMips4_32Bit = 27,
+ Feature_HasMips4_32r2Bit = 17,
+ Feature_HasMips32Bit = 3,
+ Feature_HasMips32r2Bit = 6,
+ Feature_HasMips32r6Bit = 28,
+ Feature_NotMips32r6Bit = 4,
+ Feature_IsGP64bitBit = 21,
+ Feature_IsPTR64bitBit = 23,
+ Feature_HasMips64Bit = 24,
+ Feature_HasMips64r2Bit = 22,
+ Feature_HasMips64r6Bit = 29,
+ Feature_NotMips64r6Bit = 5,
+ Feature_InMips16ModeBit = 30,
+ Feature_NotInMips16ModeBit = 0,
+ Feature_HasCnMipsBit = 25,
+ Feature_NotCnMipsBit = 8,
+ Feature_IsN64Bit = 37,
+ Feature_RelocNotPICBit = 9,
+ Feature_RelocPICBit = 36,
+ Feature_NoNaNsFPMathBit = 20,
+ Feature_HasStdEncBit = 1,
+ Feature_NotDSPBit = 11,
+ Feature_InMicroMipsBit = 34,
+ Feature_NotInMicroMipsBit = 2,
+ Feature_IsLEBit = 39,
+ Feature_IsBEBit = 40,
+ Feature_IsNotNaClBit = 18,
+ Feature_HasEVABit = 35,
+ Feature_HasMSABit = 33,
+ Feature_HasMadd4Bit = 19,
+ Feature_UseIndirectJumpsHazardBit = 12,
+ Feature_NoIndirectJumpGuardsBit = 10,
+ Feature_AllowFPOpFusionBit = 38,
+ Feature_IsFP64bitBit = 15,
+ Feature_NotFP64bitBit = 14,
+ Feature_IsNotSoftFloatBit = 13,
+ Feature_HasDSPBit = 31,
+ Feature_HasDSPR2Bit = 32,
+};
+
+PredicateBitset MipsInstructionSelector::
+computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
+ PredicateBitset Features;
+ if (Subtarget->hasMips2())
+ Features[Feature_HasMips2Bit] = 1;
+ if (Subtarget->hasMips3())
+ Features[Feature_HasMips3Bit] = 1;
+ if (Subtarget->hasMips4_32())
+ Features[Feature_HasMips4_32Bit] = 1;
+ if (!Subtarget->hasMips4_32())
+ Features[Feature_NotMips4_32Bit] = 1;
+ if (Subtarget->hasMips4_32r2())
+ Features[Feature_HasMips4_32r2Bit] = 1;
+ if (Subtarget->hasMips32())
+ Features[Feature_HasMips32Bit] = 1;
+ if (Subtarget->hasMips32r2())
+ Features[Feature_HasMips32r2Bit] = 1;
+ if (Subtarget->hasMips32r6())
+ Features[Feature_HasMips32r6Bit] = 1;
+ if (!Subtarget->hasMips32r6())
+ Features[Feature_NotMips32r6Bit] = 1;
+ if (Subtarget->isGP64bit())
+ Features[Feature_IsGP64bitBit] = 1;
+ if (Subtarget->isABI_N64())
+ Features[Feature_IsPTR64bitBit] = 1;
+ if (Subtarget->hasMips64())
+ Features[Feature_HasMips64Bit] = 1;
+ if (Subtarget->hasMips64r2())
+ Features[Feature_HasMips64r2Bit] = 1;
+ if (Subtarget->hasMips64r6())
+ Features[Feature_HasMips64r6Bit] = 1;
+ if (!Subtarget->hasMips64r6())
+ Features[Feature_NotMips64r6Bit] = 1;
+ if (Subtarget->inMips16Mode())
+ Features[Feature_InMips16ModeBit] = 1;
+ if (!Subtarget->inMips16Mode())
+ Features[Feature_NotInMips16ModeBit] = 1;
+ if (Subtarget->hasCnMips())
+ Features[Feature_HasCnMipsBit] = 1;
+ if (!Subtarget->hasCnMips())
+ Features[Feature_NotCnMipsBit] = 1;
+ if (Subtarget->isABI_N64())
+ Features[Feature_IsN64Bit] = 1;
+ if (!TM.isPositionIndependent())
+ Features[Feature_RelocNotPICBit] = 1;
+ if (TM.isPositionIndependent())
+ Features[Feature_RelocPICBit] = 1;
+ if (TM.Options.NoNaNsFPMath)
+ Features[Feature_NoNaNsFPMathBit] = 1;
+ if (Subtarget->hasStandardEncoding())
+ Features[Feature_HasStdEncBit] = 1;
+ if (!Subtarget->hasDSP())
+ Features[Feature_NotDSPBit] = 1;
+ if (Subtarget->inMicroMipsMode())
+ Features[Feature_InMicroMipsBit] = 1;
+ if (!Subtarget->inMicroMipsMode())
+ Features[Feature_NotInMicroMipsBit] = 1;
+ if (Subtarget->isLittle())
+ Features[Feature_IsLEBit] = 1;
+ if (!Subtarget->isLittle())
+ Features[Feature_IsBEBit] = 1;
+ if (!Subtarget->isTargetNaCl())
+ Features[Feature_IsNotNaClBit] = 1;
+ if (Subtarget->hasEVA())
+ Features[Feature_HasEVABit] = 1;
+ if (Subtarget->hasMSA())
+ Features[Feature_HasMSABit] = 1;
+ if (!Subtarget->disableMadd4())
+ Features[Feature_HasMadd4Bit] = 1;
+ if (Subtarget->useIndirectJumpsHazard())
+ Features[Feature_UseIndirectJumpsHazardBit] = 1;
+ if (!Subtarget->useIndirectJumpsHazard())
+ Features[Feature_NoIndirectJumpGuardsBit] = 1;
+ if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
+ Features[Feature_AllowFPOpFusionBit] = 1;
+ if (Subtarget->isFP64bit())
+ Features[Feature_IsFP64bitBit] = 1;
+ if (!Subtarget->isFP64bit())
+ Features[Feature_NotFP64bitBit] = 1;
+ if (!Subtarget->useSoftFloat())
+ Features[Feature_IsNotSoftFloatBit] = 1;
+ if (Subtarget->hasDSP())
+ Features[Feature_HasDSPBit] = 1;
+ if (Subtarget->hasDSPR2())
+ Features[Feature_HasDSPR2Bit] = 1;
+ return Features;
+}
+
+PredicateBitset MipsInstructionSelector::
+computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
+ PredicateBitset Features;
+ return Features;
+}
+
+// LLT Objects.
+enum {
+ GILLT_s16,
+ GILLT_s32,
+ GILLT_s64,
+ GILLT_v2s16,
+ GILLT_v2s64,
+ GILLT_v4s8,
+ GILLT_v4s32,
+ GILLT_v8s16,
+ GILLT_v16s8,
+};
+const static size_t NumTypeObjects = 9;
+const static LLT TypeObjects[] = {
+ LLT::scalar(16),
+ LLT::scalar(32),
+ LLT::scalar(64),
+ LLT::vector(2, 16),
+ LLT::vector(2, 64),
+ LLT::vector(4, 8),
+ LLT::vector(4, 32),
+ LLT::vector(8, 16),
+ LLT::vector(16, 8),
+};
+
+// Feature bitsets.
+enum {
+ GIFBS_Invalid,
+ GIFBS_HasCnMips,
+ GIFBS_HasDSP,
+ GIFBS_HasDSPR2,
+ GIFBS_HasMSA,
+ GIFBS_InMicroMips,
+ GIFBS_InMips16Mode,
+ GIFBS_IsFP64bit,
+ GIFBS_NotFP64bit,
+ GIFBS_HasDSP_InMicroMips,
+ GIFBS_HasDSP_NotInMicroMips,
+ GIFBS_HasDSPR2_InMicroMips,
+ GIFBS_HasMSA_HasStdEnc,
+ GIFBS_HasMSA_IsBE,
+ GIFBS_HasMSA_IsLE,
+ GIFBS_HasMips32r6_InMicroMips,
+ GIFBS_HasMips64r2_HasStdEnc,
+ GIFBS_HasMips64r6_HasStdEnc,
+ GIFBS_HasStdEnc_IsNotSoftFloat,
+ GIFBS_HasStdEnc_NotInMicroMips,
+ GIFBS_HasStdEnc_NotMips4_32,
+ GIFBS_InMicroMips_IsFP64bit,
+ GIFBS_InMicroMips_IsNotSoftFloat,
+ GIFBS_InMicroMips_NotFP64bit,
+ GIFBS_InMicroMips_NotMips32r6,
+ GIFBS_IsGP64bit_NotInMips16Mode,
+ GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
+ GIFBS_HasMSA_HasMips64_HasStdEnc,
+ GIFBS_HasMips3_HasStdEnc_IsGP64bit,
+ GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
+ GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
+ GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
+ GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
+ GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
+ GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
+ GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
+ GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
+ GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
+ GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
+ GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
+ GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
+ GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
+ GIFBS_InMicroMips_NotMips32r6_RelocPIC,
+ GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
+ GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
+ GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
+ GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
+ GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
+ GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
+ GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+};
+const static PredicateBitset FeatureBitsets[] {
+ {}, // GIFBS_Invalid
+ {Feature_HasCnMipsBit, },
+ {Feature_HasDSPBit, },
+ {Feature_HasDSPR2Bit, },
+ {Feature_HasMSABit, },
+ {Feature_InMicroMipsBit, },
+ {Feature_InMips16ModeBit, },
+ {Feature_IsFP64bitBit, },
+ {Feature_NotFP64bitBit, },
+ {Feature_HasDSPBit, Feature_InMicroMipsBit, },
+ {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
+ {Feature_HasMSABit, Feature_HasStdEncBit, },
+ {Feature_HasMSABit, Feature_IsBEBit, },
+ {Feature_HasMSABit, Feature_IsLEBit, },
+ {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
+ {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
+ {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
+ {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
+ {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
+ {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
+ {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
+ {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
+ {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
+ {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
+ {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
+ {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
+ {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
+ {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
+ {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
+ {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
+ {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
+ {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
+ {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
+ {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
+ {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
+ {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
+ {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
+ {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
+ {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
+ {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+ {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
+};
+
+// ComplexPattern predicates.
+enum {
+ GICP_Invalid,
+};
+// See constructor for table contents
+
+// PatFrag predicates.
+enum {
+ GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
+ GIPFP_I64_Predicate_immSExt10,
+ GIPFP_I64_Predicate_immSExt6,
+ GIPFP_I64_Predicate_immSExtAddiur2,
+ GIPFP_I64_Predicate_immSExtAddius5,
+ GIPFP_I64_Predicate_immZExt1,
+ GIPFP_I64_Predicate_immZExt10,
+ GIPFP_I64_Predicate_immZExt1Ptr,
+ GIPFP_I64_Predicate_immZExt2,
+ GIPFP_I64_Predicate_immZExt2Lsa,
+ GIPFP_I64_Predicate_immZExt2Ptr,
+ GIPFP_I64_Predicate_immZExt2Shift,
+ GIPFP_I64_Predicate_immZExt3,
+ GIPFP_I64_Predicate_immZExt3Ptr,
+ GIPFP_I64_Predicate_immZExt4,
+ GIPFP_I64_Predicate_immZExt4Ptr,
+ GIPFP_I64_Predicate_immZExt5,
+ GIPFP_I64_Predicate_immZExt5_64,
+ GIPFP_I64_Predicate_immZExt6,
+ GIPFP_I64_Predicate_immZExt8,
+ GIPFP_I64_Predicate_immZExtAndi16,
+ GIPFP_I64_Predicate_immi32Cst15,
+ GIPFP_I64_Predicate_immi32Cst31,
+ GIPFP_I64_Predicate_immi32Cst7,
+};
+bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
+ switch (PredicateID) {
+ case GIPFP_I64_Predicate_immLi16: {
+ return Imm >= -1 && Imm <= 126;
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immSExt10: {
+ return isInt<10>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immSExt6: {
+ return isInt<6>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immSExtAddiur2: {
+ return Imm == 1 || Imm == -1 ||
+ ((Imm % 4 == 0) &&
+ Imm < 28 && Imm > 0);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immSExtAddius5: {
+ return Imm >= -8 && Imm <= 7;
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt1: {
+ return isUInt<1>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt10: {
+ return isUInt<10>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt1Ptr: {
+ return isUInt<1>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt2: {
+ return isUInt<2>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt2Lsa: {
+ return isUInt<2>(Imm - 1);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt2Ptr: {
+ return isUInt<2>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt2Shift: {
+ return Imm >= 1 && Imm <= 8;
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt3: {
+ return isUInt<3>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt3Ptr: {
+ return isUInt<3>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt4: {
+ return isUInt<4>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt4Ptr: {
+ return isUInt<4>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt5: {
+ return Imm == (Imm & 0x1f);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt5_64: {
+ return Imm == (Imm & 0x1f);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt6: {
+ return Imm == (Imm & 0x3f);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExt8: {
+ return isUInt<8>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immZExtAndi16: {
+ return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
+ Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
+ Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immi32Cst15: {
+ return isUInt<32>(Imm) && Imm == 15;
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immi32Cst31: {
+ return isUInt<32>(Imm) && Imm == 31;
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immi32Cst7: {
+ return isUInt<32>(Imm) && Imm == 7;
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ }
+ llvm_unreachable("Unknown predicate");
+ return false;
+}
+bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
+ llvm_unreachable("Unknown predicate");
+ return false;
+}
+bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
+ llvm_unreachable("Unknown predicate");
+ return false;
+}
+bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
+ const MachineFunction &MF = *MI.getParent()->getParent();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+ (void)MRI;
+ llvm_unreachable("Unknown predicate");
+ return false;
+}
+
+MipsInstructionSelector::ComplexMatcherMemFn
+MipsInstructionSelector::ComplexPredicateFns[] = {
+ nullptr, // GICP_Invalid
+};
+
+// Custom renderers.
+enum {
+ GICR_Invalid,
+};
+MipsInstructionSelector::CustomRendererFn
+MipsInstructionSelector::CustomRenderers[] = {
+ nullptr, // GICP_Invalid
+};
+
+bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
+ MachineFunction &MF = *I.getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ // FIXME: This should be computed on a per-function basis rather than per-insn.
+ AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);
+ const PredicateBitset AvailableFeatures = getAvailableFeatures();
+ NewMIVector OutMIs;
+ State.MIs.clear();
+ State.MIs.push_back(&I);
+
+ if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
+ return true;
+ }
+
+ return false;
+}
+
+const int64_t *MipsInstructionSelector::getMatchTable() const {
+ constexpr static int64_t MatchTable0[] = {
+ GIM_SwitchOpcode, /*MI*/0, /*[*/34, 124, /*)*//*default:*//*Label 40*/ 37669,
+ /*TargetOpcode::G_ADD*//*Label 0*/ 95,
+ /*TargetOpcode::G_SUB*//*Label 1*/ 1272,
+ /*TargetOpcode::G_MUL*//*Label 2*/ 1884,
+ /*TargetOpcode::G_SDIV*//*Label 3*/ 2260,
+ /*TargetOpcode::G_UDIV*//*Label 4*/ 2481,
+ /*TargetOpcode::G_SREM*//*Label 5*/ 2702,
+ /*TargetOpcode::G_UREM*//*Label 6*/ 2923,
+ /*TargetOpcode::G_AND*//*Label 7*/ 3144,
+ /*TargetOpcode::G_OR*//*Label 8*/ 3588,
+ /*TargetOpcode::G_XOR*//*Label 9*/ 3890, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_BITCAST*//*Label 10*/ 4684,
+ /*TargetOpcode::G_LOAD*//*Label 11*/ 8337,
+ /*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 8403,
+ /*TargetOpcode::G_ZEXTLOAD*//*Label 13*/ 8469, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_INTRINSIC*//*Label 14*/ 8535,
+ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 25046, 0,
+ /*TargetOpcode::G_TRUNC*//*Label 16*/ 29970,
+ /*TargetOpcode::G_CONSTANT*//*Label 17*/ 30027, 0, 0, 0,
+ /*TargetOpcode::G_SEXT*//*Label 18*/ 30087,
+ /*TargetOpcode::G_ZEXT*//*Label 19*/ 30115,
+ /*TargetOpcode::G_SHL*//*Label 20*/ 30200,
+ /*TargetOpcode::G_LSHR*//*Label 21*/ 30724,
+ /*TargetOpcode::G_ASHR*//*Label 22*/ 31248, 0, 0,
+ /*TargetOpcode::G_SELECT*//*Label 23*/ 31729, 0, 0, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_FADD*//*Label 24*/ 33183,
+ /*TargetOpcode::G_FSUB*//*Label 25*/ 34062,
+ /*TargetOpcode::G_FMUL*//*Label 26*/ 34638,
+ /*TargetOpcode::G_FMA*//*Label 27*/ 35075,
+ /*TargetOpcode::G_FDIV*//*Label 28*/ 35165, 0, 0, 0,
+ /*TargetOpcode::G_FEXP2*//*Label 29*/ 35416, 0,
+ /*TargetOpcode::G_FLOG2*//*Label 30*/ 35474,
+ /*TargetOpcode::G_FNEG*//*Label 31*/ 35532,
+ /*TargetOpcode::G_FPEXT*//*Label 32*/ 36828,
+ /*TargetOpcode::G_FPTRUNC*//*Label 33*/ 36977,
+ /*TargetOpcode::G_FPTOSI*//*Label 34*/ 37105,
+ /*TargetOpcode::G_FPTOUI*//*Label 35*/ 37163,
+ /*TargetOpcode::G_SITOFP*//*Label 36*/ 37221,
+ /*TargetOpcode::G_UITOFP*//*Label 37*/ 37374, 0, 0, 0,
+ /*TargetOpcode::G_BR*//*Label 38*/ 37432, 0, 0, 0,
+ /*TargetOpcode::G_BSWAP*//*Label 39*/ 37517,
+ // Label 0: @95
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 49*/ 1271,
+ /*GILLT_s32*//*Label 41*/ 109,
+ /*GILLT_s64*//*Label 42*/ 458,
+ /*GILLT_v2s16*//*Label 43*/ 621,
+ /*GILLT_v2s64*//*Label 44*/ 648,
+ /*GILLT_v4s8*//*Label 45*/ 797,
+ /*GILLT_v4s32*//*Label 46*/ 824,
+ /*GILLT_v8s16*//*Label 47*/ 973,
+ /*GILLT_v16s8*//*Label 48*/ 1122,
+ // Label 41: @109
+ GIM_Try, /*On fail goto*//*Label 50*/ 457,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 51*/ 187, // Rule ID 2290 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2290,
+ GIR_Done,
+ // Label 51: @187
+ GIM_Try, /*On fail goto*//*Label 52*/ 255, // Rule ID 802 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 802,
+ GIR_Done,
+ // Label 52: @255
+ GIM_Try, /*On fail goto*//*Label 53*/ 298, // Rule ID 2066 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2066,
+ GIR_Done,
+ // Label 53: @298
+ GIM_Try, /*On fail goto*//*Label 54*/ 341, // Rule ID 2067 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2067,
+ GIR_Done,
+ // Label 54: @341
+ GIM_Try, /*On fail goto*//*Label 55*/ 364, // Rule ID 1165 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
+ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1165,
+ GIR_Done,
+ // Label 55: @364
+ GIM_Try, /*On fail goto*//*Label 56*/ 387, // Rule ID 34 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 34,
+ GIR_Done,
+ // Label 56: @387
+ GIM_Try, /*On fail goto*//*Label 57*/ 410, // Rule ID 1028 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
+ // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1028,
+ GIR_Done,
+ // Label 57: @410
+ GIM_Try, /*On fail goto*//*Label 58*/ 433, // Rule ID 1040 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1040,
+ GIR_Done,
+ // Label 58: @433
+ GIM_Try, /*On fail goto*//*Label 59*/ 456, // Rule ID 1735 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1735,
+ GIR_Done,
+ // Label 59: @456
+ GIM_Reject,
+ // Label 50: @457
+ GIM_Reject,
+ // Label 42: @458
+ GIM_Try, /*On fail goto*//*Label 60*/ 620,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 61*/ 536, // Rule ID 2291 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2291,
+ GIR_Done,
+ // Label 61: @536
+ GIM_Try, /*On fail goto*//*Label 62*/ 600, // Rule ID 803 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 803,
+ GIR_Done,
+ // Label 62: @600
+ GIM_Try, /*On fail goto*//*Label 63*/ 619, // Rule ID 180 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 180,
+ GIR_Done,
+ // Label 63: @619
+ GIM_Reject,
+ // Label 60: @620
+ GIM_Reject,
+ // Label 43: @621
+ GIM_Try, /*On fail goto*//*Label 64*/ 647, // Rule ID 1834 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1834,
+ GIR_Done,
+ // Label 64: @647
+ GIM_Reject,
+ // Label 44: @648
+ GIM_Try, /*On fail goto*//*Label 65*/ 796,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_Try, /*On fail goto*//*Label 66*/ 719, // Rule ID 2295 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2295,
+ GIR_Done,
+ // Label 66: @719
+ GIM_Try, /*On fail goto*//*Label 67*/ 776, // Rule ID 811 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 811,
+ GIR_Done,
+ // Label 67: @776
+ GIM_Try, /*On fail goto*//*Label 68*/ 795, // Rule ID 478 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 478,
+ GIR_Done,
+ // Label 68: @795
+ GIM_Reject,
+ // Label 65: @796
+ GIM_Reject,
+ // Label 45: @797
+ GIM_Try, /*On fail goto*//*Label 69*/ 823, // Rule ID 1840 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1840,
+ GIR_Done,
+ // Label 69: @823
+ GIM_Reject,
+ // Label 46: @824
+ GIM_Try, /*On fail goto*//*Label 70*/ 972,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_Try, /*On fail goto*//*Label 71*/ 895, // Rule ID 2294 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2294,
+ GIR_Done,
+ // Label 71: @895
+ GIM_Try, /*On fail goto*//*Label 72*/ 952, // Rule ID 810 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 810,
+ GIR_Done,
+ // Label 72: @952
+ GIM_Try, /*On fail goto*//*Label 73*/ 971, // Rule ID 477 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 477,
+ GIR_Done,
+ // Label 73: @971
+ GIM_Reject,
+ // Label 70: @972
+ GIM_Reject,
+ // Label 47: @973
+ GIM_Try, /*On fail goto*//*Label 74*/ 1121,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_Try, /*On fail goto*//*Label 75*/ 1044, // Rule ID 2293 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2293,
+ GIR_Done,
+ // Label 75: @1044
+ GIM_Try, /*On fail goto*//*Label 76*/ 1101, // Rule ID 809 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 809,
+ GIR_Done,
+ // Label 76: @1101
+ GIM_Try, /*On fail goto*//*Label 77*/ 1120, // Rule ID 476 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 476,
+ GIR_Done,
+ // Label 77: @1120
+ GIM_Reject,
+ // Label 74: @1121
+ GIM_Reject,
+ // Label 48: @1122
+ GIM_Try, /*On fail goto*//*Label 78*/ 1270,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_Try, /*On fail goto*//*Label 79*/ 1193, // Rule ID 2292 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2292,
+ GIR_Done,
+ // Label 79: @1193
+ GIM_Try, /*On fail goto*//*Label 80*/ 1250, // Rule ID 808 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 808,
+ GIR_Done,
+ // Label 80: @1250
+ GIM_Try, /*On fail goto*//*Label 81*/ 1269, // Rule ID 475 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 475,
+ GIR_Done,
+ // Label 81: @1269
+ GIM_Reject,
+ // Label 78: @1270
+ GIM_Reject,
+ // Label 49: @1271
+ GIM_Reject,
+ // Label 1: @1272
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 90*/ 1883,
+ /*GILLT_s32*//*Label 82*/ 1286,
+ /*GILLT_s64*//*Label 83*/ 1445,
+ /*GILLT_v2s16*//*Label 84*/ 1477,
+ /*GILLT_v2s64*//*Label 85*/ 1504,
+ /*GILLT_v4s8*//*Label 86*/ 1592,
+ /*GILLT_v4s32*//*Label 87*/ 1619,
+ /*GILLT_v8s16*//*Label 88*/ 1707,
+ /*GILLT_v16s8*//*Label 89*/ 1795,
+ // Label 82: @1286
+ GIM_Try, /*On fail goto*//*Label 91*/ 1444,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 92*/ 1328, // Rule ID 1734 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1734,
+ GIR_Done,
+ // Label 92: @1328
+ GIM_Try, /*On fail goto*//*Label 93*/ 1351, // Rule ID 1167 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
+ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1167,
+ GIR_Done,
+ // Label 93: @1351
+ GIM_Try, /*On fail goto*//*Label 94*/ 1374, // Rule ID 35 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 35,
+ GIR_Done,
+ // Label 94: @1374
+ GIM_Try, /*On fail goto*//*Label 95*/ 1397, // Rule ID 1032 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
+ // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1032,
+ GIR_Done,
+ // Label 95: @1397
+ GIM_Try, /*On fail goto*//*Label 96*/ 1420, // Rule ID 1041 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1041,
+ GIR_Done,
+ // Label 96: @1420
+ GIM_Try, /*On fail goto*//*Label 97*/ 1443, // Rule ID 1739 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1739,
+ GIR_Done,
+ // Label 97: @1443
+ GIM_Reject,
+ // Label 91: @1444
+ GIM_Reject,
+ // Label 83: @1445
+ GIM_Try, /*On fail goto*//*Label 98*/ 1476, // Rule ID 181 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 181,
+ GIR_Done,
+ // Label 98: @1476
+ GIM_Reject,
+ // Label 84: @1477
+ GIM_Try, /*On fail goto*//*Label 99*/ 1503, // Rule ID 1836 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1836,
+ GIR_Done,
+ // Label 99: @1503
+ GIM_Reject,
+ // Label 85: @1504
+ GIM_Try, /*On fail goto*//*Label 100*/ 1591,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_Try, /*On fail goto*//*Label 101*/ 1575, // Rule ID 867 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 867,
+ GIR_Done,
+ // Label 101: @1575
+ GIM_Try, /*On fail goto*//*Label 102*/ 1590, // Rule ID 996 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 996,
+ GIR_Done,
+ // Label 102: @1590
+ GIM_Reject,
+ // Label 100: @1591
+ GIM_Reject,
+ // Label 86: @1592
+ GIM_Try, /*On fail goto*//*Label 103*/ 1618, // Rule ID 1842 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1842,
+ GIR_Done,
+ // Label 103: @1618
+ GIM_Reject,
+ // Label 87: @1619
+ GIM_Try, /*On fail goto*//*Label 104*/ 1706,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_Try, /*On fail goto*//*Label 105*/ 1690, // Rule ID 866 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 866,
+ GIR_Done,
+ // Label 105: @1690
+ GIM_Try, /*On fail goto*//*Label 106*/ 1705, // Rule ID 995 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 995,
+ GIR_Done,
+ // Label 106: @1705
+ GIM_Reject,
+ // Label 104: @1706
+ GIM_Reject,
+ // Label 88: @1707
+ GIM_Try, /*On fail goto*//*Label 107*/ 1794,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_Try, /*On fail goto*//*Label 108*/ 1778, // Rule ID 865 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 865,
+ GIR_Done,
+ // Label 108: @1778
+ GIM_Try, /*On fail goto*//*Label 109*/ 1793, // Rule ID 994 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 994,
+ GIR_Done,
+ // Label 109: @1793
+ GIM_Reject,
+ // Label 107: @1794
+ GIM_Reject,
+ // Label 89: @1795
+ GIM_Try, /*On fail goto*//*Label 110*/ 1882,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_Try, /*On fail goto*//*Label 111*/ 1866, // Rule ID 864 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 864,
+ GIR_Done,
+ // Label 111: @1866
+ GIM_Try, /*On fail goto*//*Label 112*/ 1881, // Rule ID 993 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 993,
+ GIR_Done,
+ // Label 112: @1881
+ GIM_Reject,
+ // Label 110: @1882
+ GIM_Reject,
+ // Label 90: @1883
+ GIM_Reject,
+ // Label 2: @1884
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 120*/ 2259,
+ /*GILLT_s32*//*Label 113*/ 1898,
+ /*GILLT_s64*//*Label 114*/ 2043,
+ /*GILLT_v2s16*//*Label 115*/ 2104,
+ /*GILLT_v2s64*//*Label 116*/ 2131, 0,
+ /*GILLT_v4s32*//*Label 117*/ 2163,
+ /*GILLT_v8s16*//*Label 118*/ 2195,
+ /*GILLT_v16s8*//*Label 119*/ 2227,
+ // Label 113: @1898
+ GIM_Try, /*On fail goto*//*Label 121*/ 2042,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 122*/ 1937, // Rule ID 36 //
+ GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 36,
+ GIR_Done,
+ // Label 122: @1937
+ GIM_Try, /*On fail goto*//*Label 123*/ 1960, // Rule ID 304 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 304,
+ GIR_Done,
+ // Label 123: @1960
+ GIM_Try, /*On fail goto*//*Label 124*/ 1989, // Rule ID 1042 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1042,
+ GIR_Done,
+ // Label 124: @1989
+ GIM_Try, /*On fail goto*//*Label 125*/ 2012, // Rule ID 1136 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1136,
+ GIR_Done,
+ // Label 125: @2012
+ GIM_Try, /*On fail goto*//*Label 126*/ 2041, // Rule ID 1737 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1737,
+ GIR_Done,
+ // Label 126: @2041
+ GIM_Reject,
+ // Label 121: @2042
+ GIM_Reject,
+ // Label 114: @2043
+ GIM_Try, /*On fail goto*//*Label 127*/ 2103,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 128*/ 2091, // Rule ID 246 //
+ GIM_CheckFeatures, GIFBS_HasCnMips,
+ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 246,
+ GIR_Done,
+ // Label 128: @2091
+ GIM_Try, /*On fail goto*//*Label 129*/ 2102, // Rule ID 319 //
+ GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
+ // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 319,
+ GIR_Done,
+ // Label 129: @2102
+ GIM_Reject,
+ // Label 127: @2103
+ GIM_Reject,
+ // Label 115: @2104
+ GIM_Try, /*On fail goto*//*Label 130*/ 2130, // Rule ID 1838 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1838,
+ GIR_Done,
+ // Label 130: @2130
+ GIM_Reject,
+ // Label 116: @2131
+ GIM_Try, /*On fail goto*//*Label 131*/ 2162, // Rule ID 875 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 875,
+ GIR_Done,
+ // Label 131: @2162
+ GIM_Reject,
+ // Label 117: @2163
+ GIM_Try, /*On fail goto*//*Label 132*/ 2194, // Rule ID 874 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 874,
+ GIR_Done,
+ // Label 132: @2194
+ GIM_Reject,
+ // Label 118: @2195
+ GIM_Try, /*On fail goto*//*Label 133*/ 2226, // Rule ID 873 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 873,
+ GIR_Done,
+ // Label 133: @2226
+ GIM_Reject,
+ // Label 119: @2227
+ GIM_Try, /*On fail goto*//*Label 134*/ 2258, // Rule ID 872 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 872,
+ GIR_Done,
+ // Label 134: @2258
+ GIM_Reject,
+ // Label 120: @2259
+ GIM_Reject,
+ // Label 3: @2260
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 141*/ 2480,
+ /*GILLT_s32*//*Label 135*/ 2274,
+ /*GILLT_s64*//*Label 136*/ 2320, 0,
+ /*GILLT_v2s64*//*Label 137*/ 2352, 0,
+ /*GILLT_v4s32*//*Label 138*/ 2384,
+ /*GILLT_v8s16*//*Label 139*/ 2416,
+ /*GILLT_v16s8*//*Label 140*/ 2448,
+ // Label 135: @2274
+ GIM_Try, /*On fail goto*//*Label 142*/ 2319,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 143*/ 2307, // Rule ID 298 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
+ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 298,
+ GIR_Done,
+ // Label 143: @2307
+ GIM_Try, /*On fail goto*//*Label 144*/ 2318, // Rule ID 1129 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1129,
+ GIR_Done,
+ // Label 144: @2318
+ GIM_Reject,
+ // Label 142: @2319
+ GIM_Reject,
+ // Label 136: @2320
+ GIM_Try, /*On fail goto*//*Label 145*/ 2351, // Rule ID 313 //
+ GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 313,
+ GIR_Done,
+ // Label 145: @2351
+ GIM_Reject,
+ // Label 137: @2352
+ GIM_Try, /*On fail goto*//*Label 146*/ 2383, // Rule ID 615 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 615,
+ GIR_Done,
+ // Label 146: @2383
+ GIM_Reject,
+ // Label 138: @2384
+ GIM_Try, /*On fail goto*//*Label 147*/ 2415, // Rule ID 614 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 614,
+ GIR_Done,
+ // Label 147: @2415
+ GIM_Reject,
+ // Label 139: @2416
+ GIM_Try, /*On fail goto*//*Label 148*/ 2447, // Rule ID 613 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 613,
+ GIR_Done,
+ // Label 148: @2447
+ GIM_Reject,
+ // Label 140: @2448
+ GIM_Try, /*On fail goto*//*Label 149*/ 2479, // Rule ID 612 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 612,
+ GIR_Done,
+ // Label 149: @2479
+ GIM_Reject,
+ // Label 141: @2480
+ GIM_Reject,
+ // Label 4: @2481
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 156*/ 2701,
+ /*GILLT_s32*//*Label 150*/ 2495,
+ /*GILLT_s64*//*Label 151*/ 2541, 0,
+ /*GILLT_v2s64*//*Label 152*/ 2573, 0,
+ /*GILLT_v4s32*//*Label 153*/ 2605,
+ /*GILLT_v8s16*//*Label 154*/ 2637,
+ /*GILLT_v16s8*//*Label 155*/ 2669,
+ // Label 150: @2495
+ GIM_Try, /*On fail goto*//*Label 157*/ 2540,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 158*/ 2528, // Rule ID 299 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
+ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 299,
+ GIR_Done,
+ // Label 158: @2528
+ GIM_Try, /*On fail goto*//*Label 159*/ 2539, // Rule ID 1130 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1130,
+ GIR_Done,
+ // Label 159: @2539
+ GIM_Reject,
+ // Label 157: @2540
+ GIM_Reject,
+ // Label 151: @2541
+ GIM_Try, /*On fail goto*//*Label 160*/ 2572, // Rule ID 314 //
+ GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 314,
+ GIR_Done,
+ // Label 160: @2572
+ GIM_Reject,
+ // Label 152: @2573
+ GIM_Try, /*On fail goto*//*Label 161*/ 2604, // Rule ID 619 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 619,
+ GIR_Done,
+ // Label 161: @2604
+ GIM_Reject,
+ // Label 153: @2605
+ GIM_Try, /*On fail goto*//*Label 162*/ 2636, // Rule ID 618 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 618,
+ GIR_Done,
+ // Label 162: @2636
+ GIM_Reject,
+ // Label 154: @2637
+ GIM_Try, /*On fail goto*//*Label 163*/ 2668, // Rule ID 617 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 617,
+ GIR_Done,
+ // Label 163: @2668
+ GIM_Reject,
+ // Label 155: @2669
+ GIM_Try, /*On fail goto*//*Label 164*/ 2700, // Rule ID 616 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 616,
+ GIR_Done,
+ // Label 164: @2700
+ GIM_Reject,
+ // Label 156: @2701
+ GIM_Reject,
+ // Label 5: @2702
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 171*/ 2922,
+ /*GILLT_s32*//*Label 165*/ 2716,
+ /*GILLT_s64*//*Label 166*/ 2762, 0,
+ /*GILLT_v2s64*//*Label 167*/ 2794, 0,
+ /*GILLT_v4s32*//*Label 168*/ 2826,
+ /*GILLT_v8s16*//*Label 169*/ 2858,
+ /*GILLT_v16s8*//*Label 170*/ 2890,
+ // Label 165: @2716
+ GIM_Try, /*On fail goto*//*Label 172*/ 2761,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 173*/ 2749, // Rule ID 300 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
+ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 300,
+ GIR_Done,
+ // Label 173: @2749
+ GIM_Try, /*On fail goto*//*Label 174*/ 2760, // Rule ID 1134 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1134,
+ GIR_Done,
+ // Label 174: @2760
+ GIM_Reject,
+ // Label 172: @2761
+ GIM_Reject,
+ // Label 166: @2762
+ GIM_Try, /*On fail goto*//*Label 175*/ 2793, // Rule ID 315 //
+ GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 315,
+ GIR_Done,
+ // Label 175: @2793
+ GIM_Reject,
+ // Label 167: @2794
+ GIM_Try, /*On fail goto*//*Label 176*/ 2825, // Rule ID 855 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 855,
+ GIR_Done,
+ // Label 176: @2825
+ GIM_Reject,
+ // Label 168: @2826
+ GIM_Try, /*On fail goto*//*Label 177*/ 2857, // Rule ID 854 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 854,
+ GIR_Done,
+ // Label 177: @2857
+ GIM_Reject,
+ // Label 169: @2858
+ GIM_Try, /*On fail goto*//*Label 178*/ 2889, // Rule ID 853 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 853,
+ GIR_Done,
+ // Label 178: @2889
+ GIM_Reject,
+ // Label 170: @2890
+ GIM_Try, /*On fail goto*//*Label 179*/ 2921, // Rule ID 852 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 852,
+ GIR_Done,
+ // Label 179: @2921
+ GIM_Reject,
+ // Label 171: @2922
+ GIM_Reject,
+ // Label 6: @2923
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 186*/ 3143,
+ /*GILLT_s32*//*Label 180*/ 2937,
+ /*GILLT_s64*//*Label 181*/ 2983, 0,
+ /*GILLT_v2s64*//*Label 182*/ 3015, 0,
+ /*GILLT_v4s32*//*Label 183*/ 3047,
+ /*GILLT_v8s16*//*Label 184*/ 3079,
+ /*GILLT_v16s8*//*Label 185*/ 3111,
+ // Label 180: @2937
+ GIM_Try, /*On fail goto*//*Label 187*/ 2982,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 188*/ 2970, // Rule ID 301 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
+ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 301,
+ GIR_Done,
+ // Label 188: @2970
+ GIM_Try, /*On fail goto*//*Label 189*/ 2981, // Rule ID 1135 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1135,
+ GIR_Done,
+ // Label 189: @2981
+ GIM_Reject,
+ // Label 187: @2982
+ GIM_Reject,
+ // Label 181: @2983
+ GIM_Try, /*On fail goto*//*Label 190*/ 3014, // Rule ID 316 //
+ GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 316,
+ GIR_Done,
+ // Label 190: @3014
+ GIM_Reject,
+ // Label 182: @3015
+ GIM_Try, /*On fail goto*//*Label 191*/ 3046, // Rule ID 859 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 859,
+ GIR_Done,
+ // Label 191: @3046
+ GIM_Reject,
+ // Label 183: @3047
+ GIM_Try, /*On fail goto*//*Label 192*/ 3078, // Rule ID 858 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 858,
+ GIR_Done,
+ // Label 192: @3078
+ GIM_Reject,
+ // Label 184: @3079
+ GIM_Try, /*On fail goto*//*Label 193*/ 3110, // Rule ID 857 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 857,
+ GIR_Done,
+ // Label 193: @3110
+ GIM_Reject,
+ // Label 185: @3111
+ GIM_Try, /*On fail goto*//*Label 194*/ 3142, // Rule ID 856 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 856,
+ GIR_Done,
+ // Label 194: @3142
+ GIM_Reject,
+ // Label 186: @3143
+ GIM_Reject,
+ // Label 7: @3144
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 201*/ 3587,
+ /*GILLT_s32*//*Label 195*/ 3158,
+ /*GILLT_s64*//*Label 196*/ 3371, 0,
+ /*GILLT_v2s64*//*Label 197*/ 3459, 0,
+ /*GILLT_v4s32*//*Label 198*/ 3491,
+ /*GILLT_v8s16*//*Label 199*/ 3523,
+ /*GILLT_v16s8*//*Label 200*/ 3555,
+ // Label 195: @3158
+ GIM_Try, /*On fail goto*//*Label 202*/ 3370,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 203*/ 3211, // Rule ID 2069 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2069,
+ GIR_Done,
+ // Label 203: @3211
+ GIM_Try, /*On fail goto*//*Label 204*/ 3254, // Rule ID 2221 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2221,
+ GIR_Done,
+ // Label 204: @3254
+ GIM_Try, /*On fail goto*//*Label 205*/ 3277, // Rule ID 39 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 39,
+ GIR_Done,
+ // Label 205: @3277
+ GIM_Try, /*On fail goto*//*Label 206*/ 3300, // Rule ID 1029 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
+ // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1029,
+ GIR_Done,
+ // Label 206: @3300
+ GIM_Try, /*On fail goto*//*Label 207*/ 3323, // Rule ID 1045 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1045,
+ GIR_Done,
+ // Label 207: @3323
+ GIM_Try, /*On fail goto*//*Label 208*/ 3346, // Rule ID 1127 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1127,
+ GIR_Done,
+ // Label 208: @3346
+ GIM_Try, /*On fail goto*//*Label 209*/ 3369, // Rule ID 1736 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1736,
+ GIR_Done,
+ // Label 209: @3369
+ GIM_Reject,
+ // Label 202: @3370
+ GIM_Reject,
+ // Label 196: @3371
+ GIM_Try, /*On fail goto*//*Label 210*/ 3458,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 211*/ 3438, // Rule ID 241 //
+ GIM_CheckFeatures, GIFBS_HasCnMips,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 241,
+ GIR_Done,
+ // Label 211: @3438
+ GIM_Try, /*On fail goto*//*Label 212*/ 3457, // Rule ID 184 //
+ GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 184,
+ GIR_Done,
+ // Label 212: @3457
+ GIM_Reject,
+ // Label 210: @3458
+ GIM_Reject,
+ // Label 197: @3459
+ GIM_Try, /*On fail goto*//*Label 213*/ 3490, // Rule ID 486 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 486,
+ GIR_Done,
+ // Label 213: @3490
+ GIM_Reject,
+ // Label 198: @3491
+ GIM_Try, /*On fail goto*//*Label 214*/ 3522, // Rule ID 485 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 485,
+ GIR_Done,
+ // Label 214: @3522
+ GIM_Reject,
+ // Label 199: @3523
+ GIM_Try, /*On fail goto*//*Label 215*/ 3554, // Rule ID 484 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_H_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 484,
+ GIR_Done,
+ // Label 215: @3554
+ GIM_Reject,
+ // Label 200: @3555
+ GIM_Try, /*On fail goto*//*Label 216*/ 3586, // Rule ID 483 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 483,
+ GIR_Done,
+ // Label 216: @3586
+ GIM_Reject,
+ // Label 201: @3587
+ GIM_Reject,
+ // Label 8: @3588
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 223*/ 3889,
+ /*GILLT_s32*//*Label 217*/ 3602,
+ /*GILLT_s64*//*Label 218*/ 3729, 0,
+ /*GILLT_v2s64*//*Label 219*/ 3761, 0,
+ /*GILLT_v4s32*//*Label 220*/ 3793,
+ /*GILLT_v8s16*//*Label 221*/ 3825,
+ /*GILLT_v16s8*//*Label 222*/ 3857,
+ // Label 217: @3602
+ GIM_Try, /*On fail goto*//*Label 224*/ 3728,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 225*/ 3635, // Rule ID 40 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 40,
+ GIR_Done,
+ // Label 225: @3635
+ GIM_Try, /*On fail goto*//*Label 226*/ 3658, // Rule ID 1031 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
+ // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR16_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1031,
+ GIR_Done,
+ // Label 226: @3658
+ GIM_Try, /*On fail goto*//*Label 227*/ 3681, // Rule ID 1046 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1046,
+ GIR_Done,
+ // Label 227: @3681
+ GIM_Try, /*On fail goto*//*Label 228*/ 3704, // Rule ID 1140 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1140,
+ GIR_Done,
+ // Label 228: @3704
+ GIM_Try, /*On fail goto*//*Label 229*/ 3727, // Rule ID 1738 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OrRxRxRy16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1738,
+ GIR_Done,
+ // Label 229: @3727
+ GIM_Reject,
+ // Label 224: @3728
+ GIM_Reject,
+ // Label 218: @3729
+ GIM_Try, /*On fail goto*//*Label 230*/ 3760, // Rule ID 185 //
+ GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 185,
+ GIR_Done,
+ // Label 230: @3760
+ GIM_Reject,
+ // Label 219: @3761
+ GIM_Try, /*On fail goto*//*Label 231*/ 3792, // Rule ID 892 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_D_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 892,
+ GIR_Done,
+ // Label 231: @3792
+ GIM_Reject,
+ // Label 220: @3793
+ GIM_Try, /*On fail goto*//*Label 232*/ 3824, // Rule ID 891 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_W_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 891,
+ GIR_Done,
+ // Label 232: @3824
+ GIM_Reject,
+ // Label 221: @3825
+ GIM_Try, /*On fail goto*//*Label 233*/ 3856, // Rule ID 890 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V_H_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 890,
+ GIR_Done,
+ // Label 233: @3856
+ GIM_Reject,
+ // Label 222: @3857
+ GIM_Try, /*On fail goto*//*Label 234*/ 3888, // Rule ID 889 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::OR_V,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 889,
+ GIR_Done,
+ // Label 234: @3888
+ GIM_Reject,
+ // Label 223: @3889
+ GIM_Reject,
+ // Label 9: @3890
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 241*/ 4683,
+ /*GILLT_s32*//*Label 235*/ 3904,
+ /*GILLT_s64*//*Label 236*/ 4467, 0,
+ /*GILLT_v2s64*//*Label 237*/ 4555, 0,
+ /*GILLT_v4s32*//*Label 238*/ 4587,
+ /*GILLT_v8s16*//*Label 239*/ 4619,
+ /*GILLT_v16s8*//*Label 240*/ 4651,
+ // Label 235: @3904
+ GIM_Try, /*On fail goto*//*Label 242*/ 4466,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 243*/ 3971, // Rule ID 42 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 42,
+ GIR_Done,
+ // Label 243: @3971
+ GIM_Try, /*On fail goto*//*Label 244*/ 4028, // Rule ID 1048 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1048,
+ GIR_Done,
+ // Label 244: @4028
+ GIM_Try, /*On fail goto*//*Label 245*/ 4085, // Rule ID 1139 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1139,
+ GIR_Done,
+ // Label 245: @4085
+ GIM_Try, /*On fail goto*//*Label 246*/ 4117, // Rule ID 1166 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1166,
+ GIR_Done,
+ // Label 246: @4117
+ GIM_Try, /*On fail goto*//*Label 247*/ 4149, // Rule ID 1030 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1030,
+ GIR_Done,
+ // Label 247: @4149
+ GIM_Try, /*On fail goto*//*Label 248*/ 4184, // Rule ID 1353 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
+ GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1353,
+ GIR_Done,
+ // Label 248: @4184
+ GIM_Try, /*On fail goto*//*Label 249*/ 4216, // Rule ID 1733 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] }) => (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NotRxRy16,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // r
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1733,
+ GIR_Done,
+ // Label 249: @4216
+ GIM_Try, /*On fail goto*//*Label 250*/ 4248, // Rule ID 2064 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2064,
+ GIR_Done,
+ // Label 250: @4248
+ GIM_Try, /*On fail goto*//*Label 251*/ 4283, // Rule ID 2065 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
+ GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2065,
+ GIR_Done,
+ // Label 251: @4283
+ GIM_Try, /*On fail goto*//*Label 252*/ 4315, // Rule ID 2224 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOT16_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2224,
+ GIR_Done,
+ // Label 252: @4315
+ GIM_Try, /*On fail goto*//*Label 253*/ 4350, // Rule ID 2225 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] }) => (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
+ GIR_AddRegister, /*InsnID*/0, Mips::ZERO,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2225,
+ GIR_Done,
+ // Label 253: @4350
+ GIM_Try, /*On fail goto*//*Label 254*/ 4373, // Rule ID 41 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 41,
+ GIR_Done,
+ // Label 254: @4373
+ GIM_Try, /*On fail goto*//*Label 255*/ 4396, // Rule ID 1033 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
+ // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR16_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1033,
+ GIR_Done,
+ // Label 255: @4396
+ GIM_Try, /*On fail goto*//*Label 256*/ 4419, // Rule ID 1047 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1047,
+ GIR_Done,
+ // Label 256: @4419
+ GIM_Try, /*On fail goto*//*Label 257*/ 4442, // Rule ID 1143 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1143,
+ GIR_Done,
+ // Label 257: @4442
+ GIM_Try, /*On fail goto*//*Label 258*/ 4465, // Rule ID 1740 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XorRxRxRy16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1740,
+ GIR_Done,
+ // Label 258: @4465
+ GIM_Reject,
+ // Label 242: @4466
+ GIM_Reject,
+ // Label 236: @4467
+ GIM_Try, /*On fail goto*//*Label 259*/ 4554,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 260*/ 4534, // Rule ID 187 //
+ GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_OR,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, -1,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] }) => (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NOR64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 187,
+ GIR_Done,
+ // Label 260: @4534
+ GIM_Try, /*On fail goto*//*Label 261*/ 4553, // Rule ID 186 //
+ GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 186,
+ GIR_Done,
+ // Label 261: @4553
+ GIM_Reject,
+ // Label 259: @4554
+ GIM_Reject,
+ // Label 237: @4555
+ GIM_Try, /*On fail goto*//*Label 262*/ 4586, // Rule ID 1008 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_D_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1008,
+ GIR_Done,
+ // Label 262: @4586
+ GIM_Reject,
+ // Label 238: @4587
+ GIM_Try, /*On fail goto*//*Label 263*/ 4618, // Rule ID 1007 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_W_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1007,
+ GIR_Done,
+ // Label 263: @4618
+ GIM_Reject,
+ // Label 239: @4619
+ GIM_Try, /*On fail goto*//*Label 264*/ 4650, // Rule ID 1006 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V_H_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1006,
+ GIR_Done,
+ // Label 264: @4650
+ GIM_Reject,
+ // Label 240: @4651
+ GIM_Try, /*On fail goto*//*Label 265*/ 4682, // Rule ID 1005 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::XOR_V,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1005,
+ GIR_Done,
+ // Label 265: @4682
+ GIM_Reject,
+ // Label 241: @4683
+ GIM_Reject,
+ // Label 10: @4684
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 274*/ 8336,
+ /*GILLT_s32*//*Label 266*/ 4698,
+ /*GILLT_s64*//*Label 267*/ 4937,
+ /*GILLT_v2s16*//*Label 268*/ 4983,
+ /*GILLT_v2s64*//*Label 269*/ 5029,
+ /*GILLT_v4s8*//*Label 270*/ 6002,
+ /*GILLT_v4s32*//*Label 271*/ 6048,
+ /*GILLT_v8s16*//*Label 272*/ 6951,
+ /*GILLT_v16s8*//*Label 273*/ 7749,
+ // Label 266: @4698
+ GIM_Try, /*On fail goto*//*Label 275*/ 4721, // Rule ID 117 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 117,
+ GIR_Done,
+ // Label 275: @4721
+ GIM_Try, /*On fail goto*//*Label 276*/ 4744, // Rule ID 118 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 118,
+ GIR_Done,
+ // Label 276: @4744
+ GIM_Try, /*On fail goto*//*Label 277*/ 4767, // Rule ID 1119 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1119,
+ GIR_Done,
+ // Label 277: @4767
+ GIM_Try, /*On fail goto*//*Label 278*/ 4790, // Rule ID 1120 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1120,
+ GIR_Done,
+ // Label 278: @4790
+ GIM_Try, /*On fail goto*//*Label 279*/ 4813, // Rule ID 1132 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt) => (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MTC1_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1132,
+ GIR_Done,
+ // Label 279: @4813
+ GIM_Try, /*On fail goto*//*Label 280*/ 4836, // Rule ID 1133 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs) => (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MFC1_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1133,
+ GIR_Done,
+ // Label 280: @4836
+ GIM_Try, /*On fail goto*//*Label 281*/ 4861, // Rule ID 1821 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
+ // GIR_Coverage, 1821,
+ GIR_Done,
+ // Label 281: @4861
+ GIM_Try, /*On fail goto*//*Label 282*/ 4886, // Rule ID 1822 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/11,
+ // GIR_Coverage, 1822,
+ GIR_Done,
+ // Label 282: @4886
+ GIM_Try, /*On fail goto*//*Label 283*/ 4911, // Rule ID 1825 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
+ // GIR_Coverage, 1825,
+ GIR_Done,
+ // Label 283: @4911
+ GIM_Try, /*On fail goto*//*Label 284*/ 4936, // Rule ID 1826 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC FGR32*/8,
+ // GIR_Coverage, 1826,
+ GIR_Done,
+ // Label 284: @4936
+ GIM_Reject,
+ // Label 267: @4937
+ GIM_Try, /*On fail goto*//*Label 285*/ 4982,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 286*/ 4962, // Rule ID 119 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt) => (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMTC1,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 119,
+ GIR_Done,
+ // Label 286: @4962
+ GIM_Try, /*On fail goto*//*Label 287*/ 4981, // Rule ID 120 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs) => (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMFC1,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 120,
+ GIR_Done,
+ // Label 287: @4981
+ GIM_Reject,
+ // Label 285: @4982
+ GIM_Reject,
+ // Label 268: @4983
+ GIM_Try, /*On fail goto*//*Label 288*/ 5028,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 289*/ 5010, // Rule ID 1823 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
+ // GIR_Coverage, 1823,
+ GIR_Done,
+ // Label 289: @5010
+ GIM_Try, /*On fail goto*//*Label 290*/ 5027, // Rule ID 1827 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
+ // GIR_Coverage, 1827,
+ GIR_Done,
+ // Label 290: @5027
+ GIM_Reject,
+ // Label 288: @5028
+ GIM_Reject,
+ // Label 269: @5029
+ GIM_Try, /*On fail goto*//*Label 291*/ 5050, // Rule ID 1908 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1908,
+ GIR_Done,
+ // Label 291: @5050
+ GIM_Try, /*On fail goto*//*Label 292*/ 5071, // Rule ID 1911 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1911,
+ GIR_Done,
+ // Label 292: @5071
+ GIM_Try, /*On fail goto*//*Label 293*/ 5092, // Rule ID 1928 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1928,
+ GIR_Done,
+ // Label 293: @5092
+ GIM_Try, /*On fail goto*//*Label 294*/ 5113, // Rule ID 1929 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1929,
+ GIR_Done,
+ // Label 294: @5113
+ GIM_Try, /*On fail goto*//*Label 295*/ 5134, // Rule ID 1930 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1930,
+ GIR_Done,
+ // Label 295: @5134
+ GIM_Try, /*On fail goto*//*Label 296*/ 5155, // Rule ID 1931 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1931,
+ GIR_Done,
+ // Label 296: @5155
+ GIM_Try, /*On fail goto*//*Label 297*/ 5176, // Rule ID 1932 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1932,
+ GIR_Done,
+ // Label 297: @5176
+ GIM_Try, /*On fail goto*//*Label 298*/ 5197, // Rule ID 1938 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1938,
+ GIR_Done,
+ // Label 298: @5197
+ GIM_Try, /*On fail goto*//*Label 299*/ 5218, // Rule ID 1939 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1939,
+ GIR_Done,
+ // Label 299: @5218
+ GIM_Try, /*On fail goto*//*Label 300*/ 5239, // Rule ID 1940 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1940,
+ GIR_Done,
+ // Label 300: @5239
+ GIM_Try, /*On fail goto*//*Label 301*/ 5260, // Rule ID 1941 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1941,
+ GIR_Done,
+ // Label 301: @5260
+ GIM_Try, /*On fail goto*//*Label 302*/ 5281, // Rule ID 1942 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1942,
+ GIR_Done,
+ // Label 302: @5281
+ GIM_Try, /*On fail goto*//*Label 303*/ 5381, // Rule ID 1947 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/3, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1947,
+ GIR_Done,
+ // Label 303: @5381
+ GIM_Try, /*On fail goto*//*Label 304*/ 5481, // Rule ID 1948 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/3, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1948,
+ GIR_Done,
+ // Label 304: @5481
+ GIM_Try, /*On fail goto*//*Label 305*/ 5546, // Rule ID 1952 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1952,
+ GIR_Done,
+ // Label 305: @5546
+ GIM_Try, /*On fail goto*//*Label 306*/ 5611, // Rule ID 1953 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1953,
+ GIR_Done,
+ // Label 306: @5611
+ GIM_Try, /*On fail goto*//*Label 307*/ 5676, // Rule ID 1957 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1957,
+ GIR_Done,
+ // Label 307: @5676
+ GIM_Try, /*On fail goto*//*Label 308*/ 5741, // Rule ID 1958 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1958,
+ GIR_Done,
+ // Label 308: @5741
+ GIM_Try, /*On fail goto*//*Label 309*/ 5806, // Rule ID 1962 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1962,
+ GIR_Done,
+ // Label 309: @5806
+ GIM_Try, /*On fail goto*//*Label 310*/ 5871, // Rule ID 1963 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1963,
+ GIR_Done,
+ // Label 310: @5871
+ GIM_Try, /*On fail goto*//*Label 311*/ 5936, // Rule ID 1967 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1967,
+ GIR_Done,
+ // Label 311: @5936
+ GIM_Try, /*On fail goto*//*Label 312*/ 6001, // Rule ID 1968 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128D*/67,
+ // GIR_Coverage, 1968,
+ GIR_Done,
+ // Label 312: @6001
+ GIM_Reject,
+ // Label 270: @6002
+ GIM_Try, /*On fail goto*//*Label 313*/ 6047,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 314*/ 6029, // Rule ID 1824 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
+ // GIR_Coverage, 1824,
+ GIR_Done,
+ // Label 314: @6029
+ GIM_Try, /*On fail goto*//*Label 315*/ 6046, // Rule ID 1828 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC DSPR*/7,
+ // GIR_Coverage, 1828,
+ GIR_Done,
+ // Label 315: @6046
+ GIM_Reject,
+ // Label 313: @6047
+ GIM_Reject,
+ // Label 271: @6048
+ GIM_Try, /*On fail goto*//*Label 316*/ 6069, // Rule ID 1907 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1907,
+ GIR_Done,
+ // Label 316: @6069
+ GIM_Try, /*On fail goto*//*Label 317*/ 6090, // Rule ID 1910 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1910,
+ GIR_Done,
+ // Label 317: @6090
+ GIM_Try, /*On fail goto*//*Label 318*/ 6111, // Rule ID 1923 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1923,
+ GIR_Done,
+ // Label 318: @6111
+ GIM_Try, /*On fail goto*//*Label 319*/ 6132, // Rule ID 1924 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1924,
+ GIR_Done,
+ // Label 319: @6132
+ GIM_Try, /*On fail goto*//*Label 320*/ 6153, // Rule ID 1925 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1925,
+ GIR_Done,
+ // Label 320: @6153
+ GIM_Try, /*On fail goto*//*Label 321*/ 6174, // Rule ID 1926 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1926,
+ GIR_Done,
+ // Label 321: @6174
+ GIM_Try, /*On fail goto*//*Label 322*/ 6195, // Rule ID 1927 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1927,
+ GIR_Done,
+ // Label 322: @6195
+ GIM_Try, /*On fail goto*//*Label 323*/ 6216, // Rule ID 1933 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1933,
+ GIR_Done,
+ // Label 323: @6216
+ GIM_Try, /*On fail goto*//*Label 324*/ 6237, // Rule ID 1934 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1934,
+ GIR_Done,
+ // Label 324: @6237
+ GIM_Try, /*On fail goto*//*Label 325*/ 6258, // Rule ID 1935 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1935,
+ GIR_Done,
+ // Label 325: @6258
+ GIM_Try, /*On fail goto*//*Label 326*/ 6279, // Rule ID 1936 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1936,
+ GIR_Done,
+ // Label 326: @6279
+ GIM_Try, /*On fail goto*//*Label 327*/ 6300, // Rule ID 1937 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1937,
+ GIR_Done,
+ // Label 327: @6300
+ GIM_Try, /*On fail goto*//*Label 328*/ 6365, // Rule ID 1945 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1945,
+ GIR_Done,
+ // Label 328: @6365
+ GIM_Try, /*On fail goto*//*Label 329*/ 6430, // Rule ID 1946 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1946,
+ GIR_Done,
+ // Label 329: @6430
+ GIM_Try, /*On fail goto*//*Label 330*/ 6495, // Rule ID 1950 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1950,
+ GIR_Done,
+ // Label 330: @6495
+ GIM_Try, /*On fail goto*//*Label 331*/ 6560, // Rule ID 1951 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1951,
+ GIR_Done,
+ // Label 331: @6560
+ GIM_Try, /*On fail goto*//*Label 332*/ 6625, // Rule ID 1955 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1955,
+ GIR_Done,
+ // Label 332: @6625
+ GIM_Try, /*On fail goto*//*Label 333*/ 6690, // Rule ID 1956 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1956,
+ GIR_Done,
+ // Label 333: @6690
+ GIM_Try, /*On fail goto*//*Label 334*/ 6755, // Rule ID 1972 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1972,
+ GIR_Done,
+ // Label 334: @6755
+ GIM_Try, /*On fail goto*//*Label 335*/ 6820, // Rule ID 1973 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1973,
+ GIR_Done,
+ // Label 335: @6820
+ GIM_Try, /*On fail goto*//*Label 336*/ 6885, // Rule ID 1977 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1977,
+ GIR_Done,
+ // Label 336: @6885
+ GIM_Try, /*On fail goto*//*Label 337*/ 6950, // Rule ID 1978 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128W*/69,
+ // GIR_Coverage, 1978,
+ GIR_Done,
+ // Label 337: @6950
+ GIM_Reject,
+ // Label 272: @6951
+ GIM_Try, /*On fail goto*//*Label 338*/ 6972, // Rule ID 1906 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1906,
+ GIR_Done,
+ // Label 338: @6972
+ GIM_Try, /*On fail goto*//*Label 339*/ 6993, // Rule ID 1909 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1909,
+ GIR_Done,
+ // Label 339: @6993
+ GIM_Try, /*On fail goto*//*Label 340*/ 7014, // Rule ID 1918 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1918,
+ GIR_Done,
+ // Label 340: @7014
+ GIM_Try, /*On fail goto*//*Label 341*/ 7035, // Rule ID 1919 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1919,
+ GIR_Done,
+ // Label 341: @7035
+ GIM_Try, /*On fail goto*//*Label 342*/ 7056, // Rule ID 1920 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1920,
+ GIR_Done,
+ // Label 342: @7056
+ GIM_Try, /*On fail goto*//*Label 343*/ 7077, // Rule ID 1921 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1921,
+ GIR_Done,
+ // Label 343: @7077
+ GIM_Try, /*On fail goto*//*Label 344*/ 7098, // Rule ID 1922 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1922,
+ GIR_Done,
+ // Label 344: @7098
+ GIM_Try, /*On fail goto*//*Label 345*/ 7163, // Rule ID 1943 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1943,
+ GIR_Done,
+ // Label 345: @7163
+ GIM_Try, /*On fail goto*//*Label 346*/ 7228, // Rule ID 1944 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1944,
+ GIR_Done,
+ // Label 346: @7228
+ GIM_Try, /*On fail goto*//*Label 347*/ 7293, // Rule ID 1960 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1960,
+ GIR_Done,
+ // Label 347: @7293
+ GIM_Try, /*On fail goto*//*Label 348*/ 7358, // Rule ID 1961 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1961,
+ GIR_Done,
+ // Label 348: @7358
+ GIM_Try, /*On fail goto*//*Label 349*/ 7423, // Rule ID 1965 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1965,
+ GIR_Done,
+ // Label 349: @7423
+ GIM_Try, /*On fail goto*//*Label 350*/ 7488, // Rule ID 1966 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1966,
+ GIR_Done,
+ // Label 350: @7488
+ GIM_Try, /*On fail goto*//*Label 351*/ 7553, // Rule ID 1970 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1970,
+ GIR_Done,
+ // Label 351: @7553
+ GIM_Try, /*On fail goto*//*Label 352*/ 7618, // Rule ID 1971 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1971,
+ GIR_Done,
+ // Label 352: @7618
+ GIM_Try, /*On fail goto*//*Label 353*/ 7683, // Rule ID 1975 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1975,
+ GIR_Done,
+ // Label 353: @7683
+ GIM_Try, /*On fail goto*//*Label 354*/ 7748, // Rule ID 1976 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_H,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128H*/68,
+ // GIR_Coverage, 1976,
+ GIR_Done,
+ // Label 354: @7748
+ GIM_Reject,
+ // Label 273: @7749
+ GIM_Try, /*On fail goto*//*Label 355*/ 7770, // Rule ID 1912 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1912,
+ GIR_Done,
+ // Label 355: @7770
+ GIM_Try, /*On fail goto*//*Label 356*/ 7791, // Rule ID 1913 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1913,
+ GIR_Done,
+ // Label 356: @7791
+ GIM_Try, /*On fail goto*//*Label 357*/ 7812, // Rule ID 1914 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1914,
+ GIR_Done,
+ // Label 357: @7812
+ GIM_Try, /*On fail goto*//*Label 358*/ 7833, // Rule ID 1915 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1915,
+ GIR_Done,
+ // Label 358: @7833
+ GIM_Try, /*On fail goto*//*Label 359*/ 7854, // Rule ID 1916 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1916,
+ GIR_Done,
+ // Label 359: @7854
+ GIM_Try, /*On fail goto*//*Label 360*/ 7875, // Rule ID 1917 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsLE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1917,
+ GIR_Done,
+ // Label 360: @7875
+ GIM_Try, /*On fail goto*//*Label 361*/ 7940, // Rule ID 1949 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1949,
+ GIR_Done,
+ // Label 361: @7940
+ GIM_Try, /*On fail goto*//*Label 362*/ 8005, // Rule ID 1954 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1954,
+ GIR_Done,
+ // Label 362: @8005
+ GIM_Try, /*On fail goto*//*Label 363*/ 8070, // Rule ID 1959 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1959,
+ GIR_Done,
+ // Label 363: @8070
+ GIM_Try, /*On fail goto*//*Label 364*/ 8135, // Rule ID 1964 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1964,
+ GIR_Done,
+ // Label 364: @8135
+ GIM_Try, /*On fail goto*//*Label 365*/ 8235, // Rule ID 1969 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/3, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1969,
+ GIR_Done,
+ // Label 365: @8235
+ GIM_Try, /*On fail goto*//*Label 366*/ 8335, // Rule ID 1974 //
+ GIM_CheckFeatures, GIFBS_HasMSA_IsBE,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
+ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
+ GIR_BuildMI, /*InsnID*/4, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SHF_B,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/3, /*Imm*/27,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SHF_W,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/1, /*Imm*/177,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/TargetOpcode::COPY,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC MSA128B*/66,
+ // GIR_Coverage, 1974,
+ GIR_Done,
+ // Label 366: @8335
+ GIM_Reject,
+ // Label 274: @8336
+ GIM_Reject,
+ // Label 11: @8337
+ GIM_Try, /*On fail goto*//*Label 367*/ 8402, // Rule ID 1897 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LWX,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1897,
+ GIR_Done,
+ // Label 367: @8402
+ GIM_Reject,
+ // Label 12: @8403
+ GIM_Try, /*On fail goto*//*Label 368*/ 8468, // Rule ID 1896 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LHX,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1896,
+ GIR_Done,
+ // Label 368: @8468
+ GIM_Reject,
+ // Label 13: @8469
+ GIM_Try, /*On fail goto*//*Label 369*/ 8534, // Rule ID 1895 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LBUX,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1895,
+ GIR_Done,
+ // Label 369: @8534
+ GIM_Reject,
+ // Label 14: @8535
+ GIM_Try, /*On fail goto*//*Label 370*/ 10729,
+ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
+ GIM_Try, /*On fail goto*//*Label 371*/ 8587, // Rule ID 400 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 400,
+ GIR_Done,
+ // Label 371: @8587
+ GIM_Try, /*On fail goto*//*Label 372*/ 8634, // Rule ID 401 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 401,
+ GIR_Done,
+ // Label 372: @8634
+ GIM_Try, /*On fail goto*//*Label 373*/ 8681, // Rule ID 1245 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExt10,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm) => (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1245,
+ GIR_Done,
+ // Label 373: @8681
+ GIM_Try, /*On fail goto*//*Label 374*/ 8728, // Rule ID 1246 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt8,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm) => (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPL_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1246,
+ GIR_Done,
+ // Label 374: @8728
+ GIM_Try, /*On fail goto*//*Label 375*/ 8768, // Rule ID 334 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3468:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 334,
+ GIR_Done,
+ // Label 375: @8768
+ GIM_Try, /*On fail goto*//*Label 376*/ 8808, // Rule ID 341 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3450:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 341,
+ GIR_Done,
+ // Label 376: @8808
+ GIM_Try, /*On fail goto*//*Label 377*/ 8848, // Rule ID 342 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 342,
+ GIR_Done,
+ // Label 377: @8848
+ GIM_Try, /*On fail goto*//*Label 378*/ 8888, // Rule ID 343 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 343,
+ GIR_Done,
+ // Label 378: @8888
+ GIM_Try, /*On fail goto*//*Label 379*/ 8928, // Rule ID 344 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3454:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 344,
+ GIR_Done,
+ // Label 379: @8928
+ GIM_Try, /*On fail goto*//*Label 380*/ 8968, // Rule ID 345 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3453:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 345,
+ GIR_Done,
+ // Label 380: @8968
+ GIM_Try, /*On fail goto*//*Label 381*/ 9008, // Rule ID 346 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3455:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 346,
+ GIR_Done,
+ // Label 381: @9008
+ GIM_Try, /*On fail goto*//*Label 382*/ 9048, // Rule ID 347 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3456:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 347,
+ GIR_Done,
+ // Label 382: @9048
+ GIM_Try, /*On fail goto*//*Label 383*/ 9088, // Rule ID 348 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3458:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 348,
+ GIR_Done,
+ // Label 383: @9088
+ GIM_Try, /*On fail goto*//*Label 384*/ 9128, // Rule ID 349 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3457:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 349,
+ GIR_Done,
+ // Label 384: @9128
+ GIM_Try, /*On fail goto*//*Label 385*/ 9168, // Rule ID 350 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3459:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 350,
+ GIR_Done,
+ // Label 385: @9168
+ GIM_Try, /*On fail goto*//*Label 386*/ 9208, // Rule ID 398 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3026:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 398,
+ GIR_Done,
+ // Label 386: @9208
+ GIM_Try, /*On fail goto*//*Label 387*/ 9248, // Rule ID 402 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 402,
+ GIR_Done,
+ // Label 387: @9248
+ GIM_Try, /*On fail goto*//*Label 388*/ 9288, // Rule ID 403 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 403,
+ GIR_Done,
+ // Label 388: @9288
+ GIM_Try, /*On fail goto*//*Label 389*/ 9328, // Rule ID 648 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3178:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 648,
+ GIR_Done,
+ // Label 389: @9328
+ GIM_Try, /*On fail goto*//*Label 390*/ 9368, // Rule ID 649 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fclass_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3177:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCLASS_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 649,
+ GIR_Done,
+ // Label 390: @9368
+ GIM_Try, /*On fail goto*//*Label 391*/ 9408, // Rule ID 672 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3204:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 672,
+ GIR_Done,
+ // Label 391: @9408
+ GIM_Try, /*On fail goto*//*Label 392*/ 9448, // Rule ID 673 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupl_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3203:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPL_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 673,
+ GIR_Done,
+ // Label 392: @9448
+ GIM_Try, /*On fail goto*//*Label 393*/ 9488, // Rule ID 674 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3206:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws) => (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 674,
+ GIR_Done,
+ // Label 393: @9488
+ GIM_Try, /*On fail goto*//*Label 394*/ 9528, // Rule ID 675 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexupr_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3205:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXUPR_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 675,
+ GIR_Done,
+ // Label 394: @9528
+ GIM_Try, /*On fail goto*//*Label 395*/ 9568, // Rule ID 680 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3212:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 680,
+ GIR_Done,
+ // Label 395: @9568
+ GIM_Try, /*On fail goto*//*Label 396*/ 9608, // Rule ID 681 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffql_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3211:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQL_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 681,
+ GIR_Done,
+ // Label 396: @9608
+ GIM_Try, /*On fail goto*//*Label 397*/ 9648, // Rule ID 682 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3214:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 682,
+ GIR_Done,
+ // Label 397: @9648
+ GIM_Try, /*On fail goto*//*Label 398*/ 9688, // Rule ID 683 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ffqr_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3213:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FFQR_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 683,
+ GIR_Done,
+ // Label 398: @9688
+ GIM_Try, /*On fail goto*//*Label 399*/ 9728, // Rule ID 708 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3236:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 708,
+ GIR_Done,
+ // Label 399: @9728
+ GIM_Try, /*On fail goto*//*Label 400*/ 9768, // Rule ID 709 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frcp_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3235:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRCP_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 709,
+ GIR_Done,
+ // Label 400: @9768
+ GIM_Try, /*On fail goto*//*Label 401*/ 9808, // Rule ID 710 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3240:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 710,
+ GIR_Done,
+ // Label 401: @9808
+ GIM_Try, /*On fail goto*//*Label 402*/ 9848, // Rule ID 711 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_frsqrt_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3239:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FRSQRT_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 711,
+ GIR_Done,
+ // Label 402: @9848
+ GIM_Try, /*On fail goto*//*Label 403*/ 9888, // Rule ID 738 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3268:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 738,
+ GIR_Done,
+ // Label 403: @9888
+ GIM_Try, /*On fail goto*//*Label 404*/ 9928, // Rule ID 739 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3267:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 739,
+ GIR_Done,
+ // Label 404: @9928
+ GIM_Try, /*On fail goto*//*Label 405*/ 9968, // Rule ID 740 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3270:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 740,
+ GIR_Done,
+ // Label 405: @9968
+ GIM_Try, /*On fail goto*//*Label 406*/ 10008, // Rule ID 741 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftint_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3269:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTINT_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 741,
+ GIR_Done,
+ // Label 406: @10008
+ GIM_Try, /*On fail goto*//*Label 407*/ 10048, // Rule ID 876 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3423:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws) => (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 876,
+ GIR_Done,
+ // Label 407: @10048
+ GIM_Try, /*On fail goto*//*Label 408*/ 10088, // Rule ID 877 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3425:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws) => (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 877,
+ GIR_Done,
+ // Label 408: @10088
+ GIM_Try, /*On fail goto*//*Label 409*/ 10128, // Rule ID 878 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3426:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws) => (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 878,
+ GIR_Done,
+ // Label 409: @10128
+ GIM_Try, /*On fail goto*//*Label 410*/ 10168, // Rule ID 879 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_nloc_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3424:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws) => (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NLOC_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 879,
+ GIR_Done,
+ // Label 410: @10168
+ GIM_Try, /*On fail goto*//*Label 411*/ 10208, // Rule ID 1208 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3450:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHL_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1208,
+ GIR_Done,
+ // Label 411: @10208
+ GIM_Try, /*On fail goto*//*Label 412*/ 10248, // Rule ID 1209 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceq_w_phr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3451:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQ_W_PHR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1209,
+ GIR_Done,
+ // Label 412: @10248
+ GIM_Try, /*On fail goto*//*Label 413*/ 10288, // Rule ID 1210 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBL_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1210,
+ GIR_Done,
+ // Label 413: @10288
+ GIM_Try, /*On fail goto*//*Label 414*/ 10328, // Rule ID 1211 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbla,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3453:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBLA_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1211,
+ GIR_Done,
+ // Label 414: @10328
+ GIM_Try, /*On fail goto*//*Label 415*/ 10368, // Rule ID 1212 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3454:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1212,
+ GIR_Done,
+ // Label 415: @10368
+ GIM_Try, /*On fail goto*//*Label 416*/ 10408, // Rule ID 1213 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precequ_ph_qbra,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3455:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEQU_PH_QBRA_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1213,
+ GIR_Done,
+ // Label 416: @10408
+ GIM_Try, /*On fail goto*//*Label 417*/ 10448, // Rule ID 1214 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3456:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBL_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1214,
+ GIR_Done,
+ // Label 417: @10448
+ GIM_Try, /*On fail goto*//*Label 418*/ 10488, // Rule ID 1215 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbla,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3457:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBLA_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1215,
+ GIR_Done,
+ // Label 418: @10488
+ GIM_Try, /*On fail goto*//*Label 419*/ 10528, // Rule ID 1216 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3458:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1216,
+ GIR_Done,
+ // Label 419: @10528
+ GIM_Try, /*On fail goto*//*Label 420*/ 10568, // Rule ID 1217 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_preceu_ph_qbra,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3459:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECEU_PH_QBRA_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1217,
+ GIR_Done,
+ // Label 420: @10568
+ GIM_Try, /*On fail goto*//*Label 421*/ 10608, // Rule ID 1243 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_raddu_w_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3468:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RADDU_W_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1243,
+ GIR_Done,
+ // Label 421: @10608
+ GIM_Try, /*On fail goto*//*Label 422*/ 10648, // Rule ID 1247 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3470:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1247,
+ GIR_Done,
+ // Label 422: @10648
+ GIM_Try, /*On fail goto*//*Label 423*/ 10688, // Rule ID 1248 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_repl_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3471:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::REPLV_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1248,
+ GIR_Done,
+ // Label 423: @10688
+ GIM_Try, /*On fail goto*//*Label 424*/ 10728, // Rule ID 1258 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bitrev,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3026:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BITREV_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1258,
+ GIR_Done,
+ // Label 424: @10728
+ GIM_Reject,
+ // Label 370: @10729
+ GIM_Try, /*On fail goto*//*Label 425*/ 21997,
+ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
+ GIM_Try, /*On fail goto*//*Label 426*/ 10793, // Rule ID 357 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 357,
+ GIR_Done,
+ // Label 426: @10793
+ GIM_Try, /*On fail goto*//*Label 427*/ 10852, // Rule ID 361 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 361,
+ GIR_Done,
+ // Label 427: @10852
+ GIM_Try, /*On fail goto*//*Label 428*/ 10911, // Rule ID 452 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa) => (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 452,
+ GIR_Done,
+ // Label 428: @10911
+ GIM_Try, /*On fail goto*//*Label 429*/ 10970, // Rule ID 906 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3472:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 906,
+ GIR_Done,
+ // Label 429: @10970
+ GIM_Try, /*On fail goto*//*Label 430*/ 11029, // Rule ID 907 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3474:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 907,
+ GIR_Done,
+ // Label 430: @11029
+ GIM_Try, /*On fail goto*//*Label 431*/ 11088, // Rule ID 908 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3475:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 908,
+ GIR_Done,
+ // Label 431: @11088
+ GIM_Try, /*On fail goto*//*Label 432*/ 11147, // Rule ID 909 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3473:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 909,
+ GIR_Done,
+ // Label 432: @11147
+ GIM_Try, /*On fail goto*//*Label 433*/ 11206, // Rule ID 910 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3476:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 910,
+ GIR_Done,
+ // Label 433: @11206
+ GIM_Try, /*On fail goto*//*Label 434*/ 11265, // Rule ID 911 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3478:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 911,
+ GIR_Done,
+ // Label 434: @11265
+ GIM_Try, /*On fail goto*//*Label 435*/ 11324, // Rule ID 912 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3479:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 912,
+ GIR_Done,
+ // Label 435: @11324
+ GIM_Try, /*On fail goto*//*Label 436*/ 11383, // Rule ID 913 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sat_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3477:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SAT_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 913,
+ GIR_Done,
+ // Label 436: @11383
+ GIM_Try, /*On fail goto*//*Label 437*/ 11442, // Rule ID 953 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3531:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 953,
+ GIR_Done,
+ // Label 437: @11442
+ GIM_Try, /*On fail goto*//*Label 438*/ 11501, // Rule ID 954 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3533:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 954,
+ GIR_Done,
+ // Label 438: @11501
+ GIM_Try, /*On fail goto*//*Label 439*/ 11560, // Rule ID 955 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3534:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 955,
+ GIR_Done,
+ // Label 439: @11560
+ GIM_Try, /*On fail goto*//*Label 440*/ 11619, // Rule ID 956 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srari_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3532:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRARI_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 956,
+ GIR_Done,
+ // Label 440: @11619
+ GIM_Try, /*On fail goto*//*Label 441*/ 11678, // Rule ID 969 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3547:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$m) => (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 969,
+ GIR_Done,
+ // Label 441: @11678
+ GIM_Try, /*On fail goto*//*Label 442*/ 11737, // Rule ID 970 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3549:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$m) => (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 970,
+ GIR_Done,
+ // Label 442: @11737
+ GIM_Try, /*On fail goto*//*Label 443*/ 11796, // Rule ID 971 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3550:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$m) => (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 971,
+ GIR_Done,
+ // Label 443: @11796
+ GIM_Try, /*On fail goto*//*Label 444*/ 11855, // Rule ID 972 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlri_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3548:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$m) => (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$m)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLRI_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // m
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 972,
+ GIR_Done,
+ // Label 444: @11855
+ GIM_Try, /*On fail goto*//*Label 445*/ 11914, // Rule ID 1202 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1202,
+ GIR_Done,
+ // Label 445: @11914
+ GIM_Try, /*On fail goto*//*Label 446*/ 11973, // Rule ID 1206 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1206,
+ GIR_Done,
+ // Label 446: @11973
+ GIM_Try, /*On fail goto*//*Label 447*/ 12032, // Rule ID 1281 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa) => (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_R_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1281,
+ GIR_Done,
+ // Label 447: @12032
+ GIM_Try, /*On fail goto*//*Label 448*/ 12087, // Rule ID 1851 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1851,
+ GIR_Done,
+ // Label 448: @12087
+ GIM_Try, /*On fail goto*//*Label 449*/ 12142, // Rule ID 1852 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1852,
+ GIR_Done,
+ // Label 449: @12142
+ GIM_Try, /*On fail goto*//*Label 450*/ 12197, // Rule ID 1857 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRA_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1857,
+ GIR_Done,
+ // Label 450: @12197
+ GIM_Try, /*On fail goto*//*Label 451*/ 12252, // Rule ID 1858 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRL_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1858,
+ GIR_Done,
+ // Label 451: @12252
+ GIM_Try, /*On fail goto*//*Label 452*/ 12304, // Rule ID 327 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 2962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 327,
+ GIR_Done,
+ // Label 452: @12304
+ GIM_Try, /*On fail goto*//*Label 453*/ 12356, // Rule ID 328 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3581:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 328,
+ GIR_Done,
+ // Label 453: @12356
+ GIM_Try, /*On fail goto*//*Label 454*/ 12408, // Rule ID 329 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 2940:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 329,
+ GIR_Done,
+ // Label 454: @12408
+ GIM_Try, /*On fail goto*//*Label 455*/ 12460, // Rule ID 330 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3556:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 330,
+ GIR_Done,
+ // Label 455: @12460
+ GIM_Try, /*On fail goto*//*Label 456*/ 12512, // Rule ID 333 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3388:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 333,
+ GIR_Done,
+ // Label 456: @12512
+ GIM_Try, /*On fail goto*//*Label 457*/ 12564, // Rule ID 337 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3464:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 337,
+ GIR_Done,
+ // Label 457: @12564
+ GIM_Try, /*On fail goto*//*Label 458*/ 12616, // Rule ID 338 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 338,
+ GIR_Done,
+ // Label 458: @12616
+ GIM_Try, /*On fail goto*//*Label 459*/ 12668, // Rule ID 352 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 352,
+ GIR_Done,
+ // Label 459: @12668
+ GIM_Try, /*On fail goto*//*Label 460*/ 12720, // Rule ID 356 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 356,
+ GIR_Done,
+ // Label 460: @12720
+ GIM_Try, /*On fail goto*//*Label 461*/ 12772, // Rule ID 358 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 358,
+ GIR_Done,
+ // Label 461: @12772
+ GIM_Try, /*On fail goto*//*Label 462*/ 12824, // Rule ID 362 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 362,
+ GIR_Done,
+ // Label 462: @12824
+ GIM_Try, /*On fail goto*//*Label 463*/ 12876, // Rule ID 399 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 399,
+ GIR_Done,
+ // Label 463: @12876
+ GIM_Try, /*On fail goto*//*Label 464*/ 12928, // Rule ID 423 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 2963:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 423,
+ GIR_Done,
+ // Label 464: @12928
+ GIM_Try, /*On fail goto*//*Label 465*/ 12980, // Rule ID 424 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 2964:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 424,
+ GIR_Done,
+ // Label 465: @12980
+ GIM_Try, /*On fail goto*//*Label 466*/ 13032, // Rule ID 425 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3582:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 425,
+ GIR_Done,
+ // Label 466: @13032
+ GIM_Try, /*On fail goto*//*Label 467*/ 13084, // Rule ID 426 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3583:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 426,
+ GIR_Done,
+ // Label 467: @13084
+ GIM_Try, /*On fail goto*//*Label 468*/ 13136, // Rule ID 427 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 2942:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 427,
+ GIR_Done,
+ // Label 468: @13136
+ GIM_Try, /*On fail goto*//*Label 469*/ 13188, // Rule ID 428 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 2943:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 428,
+ GIR_Done,
+ // Label 469: @13188
+ GIM_Try, /*On fail goto*//*Label 470*/ 13240, // Rule ID 429 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3558:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 429,
+ GIR_Done,
+ // Label 470: @13240
+ GIM_Try, /*On fail goto*//*Label 471*/ 13292, // Rule ID 430 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3559:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 430,
+ GIR_Done,
+ // Label 471: @13292
+ GIM_Try, /*On fail goto*//*Label 472*/ 13344, // Rule ID 431 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 2945:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 431,
+ GIR_Done,
+ // Label 472: @13344
+ GIM_Try, /*On fail goto*//*Label 473*/ 13396, // Rule ID 432 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 2944:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 432,
+ GIR_Done,
+ // Label 473: @13396
+ GIM_Try, /*On fail goto*//*Label 474*/ 13448, // Rule ID 433 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 433,
+ GIR_Done,
+ // Label 474: @13448
+ GIM_Try, /*On fail goto*//*Label 475*/ 13500, // Rule ID 434 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3560:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 434,
+ GIR_Done,
+ // Label 475: @13500
+ GIM_Try, /*On fail goto*//*Label 476*/ 13552, // Rule ID 451 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 451,
+ GIR_Done,
+ // Label 476: @13552
+ GIM_Try, /*On fail goto*//*Label 477*/ 13604, // Rule ID 453 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 453,
+ GIR_Done,
+ // Label 477: @13604
+ GIM_Try, /*On fail goto*//*Label 478*/ 13656, // Rule ID 454 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 454,
+ GIR_Done,
+ // Label 478: @13656
+ GIM_Try, /*On fail goto*//*Label 479*/ 13708, // Rule ID 459 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2935:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 459,
+ GIR_Done,
+ // Label 479: @13708
+ GIM_Try, /*On fail goto*//*Label 480*/ 13760, // Rule ID 460 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2937:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 460,
+ GIR_Done,
+ // Label 480: @13760
+ GIM_Try, /*On fail goto*//*Label 481*/ 13812, // Rule ID 461 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2938:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 461,
+ GIR_Done,
+ // Label 481: @13812
+ GIM_Try, /*On fail goto*//*Label 482*/ 13864, // Rule ID 462 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_add_a_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2936:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADD_A_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 462,
+ GIR_Done,
+ // Label 482: @13864
+ GIM_Try, /*On fail goto*//*Label 483*/ 13916, // Rule ID 463 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2946:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 463,
+ GIR_Done,
+ // Label 483: @13916
+ GIM_Try, /*On fail goto*//*Label 484*/ 13968, // Rule ID 464 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2948:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 464,
+ GIR_Done,
+ // Label 484: @13968
+ GIM_Try, /*On fail goto*//*Label 485*/ 14020, // Rule ID 465 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2949:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 465,
+ GIR_Done,
+ // Label 485: @14020
+ GIM_Try, /*On fail goto*//*Label 486*/ 14072, // Rule ID 466 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_a_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2947:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_A_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 466,
+ GIR_Done,
+ // Label 486: @14072
+ GIM_Try, /*On fail goto*//*Label 487*/ 14124, // Rule ID 467 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2950:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 467,
+ GIR_Done,
+ // Label 487: @14124
+ GIM_Try, /*On fail goto*//*Label 488*/ 14176, // Rule ID 468 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2952:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 468,
+ GIR_Done,
+ // Label 488: @14176
+ GIM_Try, /*On fail goto*//*Label 489*/ 14228, // Rule ID 469 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2953:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 469,
+ GIR_Done,
+ // Label 489: @14228
+ GIM_Try, /*On fail goto*//*Label 490*/ 14280, // Rule ID 470 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2951:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 470,
+ GIR_Done,
+ // Label 490: @14280
+ GIM_Try, /*On fail goto*//*Label 491*/ 14332, // Rule ID 471 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2954:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 471,
+ GIR_Done,
+ // Label 491: @14332
+ GIM_Try, /*On fail goto*//*Label 492*/ 14384, // Rule ID 472 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2956:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 472,
+ GIR_Done,
+ // Label 492: @14384
+ GIM_Try, /*On fail goto*//*Label 493*/ 14436, // Rule ID 473 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2957:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 473,
+ GIR_Done,
+ // Label 493: @14436
+ GIM_Try, /*On fail goto*//*Label 494*/ 14488, // Rule ID 474 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adds_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2955:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDS_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 474,
+ GIR_Done,
+ // Label 494: @14488
+ GIM_Try, /*On fail goto*//*Label 495*/ 14540, // Rule ID 488 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2977:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 488,
+ GIR_Done,
+ // Label 495: @14540
+ GIM_Try, /*On fail goto*//*Label 496*/ 14592, // Rule ID 489 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2979:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 489,
+ GIR_Done,
+ // Label 496: @14592
+ GIM_Try, /*On fail goto*//*Label 497*/ 14644, // Rule ID 490 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2980:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 490,
+ GIR_Done,
+ // Label 497: @14644
+ GIM_Try, /*On fail goto*//*Label 498*/ 14696, // Rule ID 491 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2978:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 491,
+ GIR_Done,
+ // Label 498: @14696
+ GIM_Try, /*On fail goto*//*Label 499*/ 14748, // Rule ID 492 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2981:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 492,
+ GIR_Done,
+ // Label 499: @14748
+ GIM_Try, /*On fail goto*//*Label 500*/ 14800, // Rule ID 493 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2983:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 493,
+ GIR_Done,
+ // Label 500: @14800
+ GIM_Try, /*On fail goto*//*Label 501*/ 14852, // Rule ID 494 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2984:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 494,
+ GIR_Done,
+ // Label 501: @14852
+ GIM_Try, /*On fail goto*//*Label 502*/ 14904, // Rule ID 495 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_asub_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2982:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ASUB_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 495,
+ GIR_Done,
+ // Label 502: @14904
+ GIM_Try, /*On fail goto*//*Label 503*/ 14956, // Rule ID 496 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2985:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 496,
+ GIR_Done,
+ // Label 503: @14956
+ GIM_Try, /*On fail goto*//*Label 504*/ 15008, // Rule ID 497 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2987:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 497,
+ GIR_Done,
+ // Label 504: @15008
+ GIM_Try, /*On fail goto*//*Label 505*/ 15060, // Rule ID 498 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2988:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 498,
+ GIR_Done,
+ // Label 505: @15060
+ GIM_Try, /*On fail goto*//*Label 506*/ 15112, // Rule ID 499 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2986:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 499,
+ GIR_Done,
+ // Label 506: @15112
+ GIM_Try, /*On fail goto*//*Label 507*/ 15164, // Rule ID 500 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2989:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 500,
+ GIR_Done,
+ // Label 507: @15164
+ GIM_Try, /*On fail goto*//*Label 508*/ 15216, // Rule ID 501 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2991:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 501,
+ GIR_Done,
+ // Label 508: @15216
+ GIM_Try, /*On fail goto*//*Label 509*/ 15268, // Rule ID 502 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2992:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 502,
+ GIR_Done,
+ // Label 509: @15268
+ GIM_Try, /*On fail goto*//*Label 510*/ 15320, // Rule ID 503 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ave_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2990:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVE_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 503,
+ GIR_Done,
+ // Label 510: @15320
+ GIM_Try, /*On fail goto*//*Label 511*/ 15372, // Rule ID 504 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2993:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 504,
+ GIR_Done,
+ // Label 511: @15372
+ GIM_Try, /*On fail goto*//*Label 512*/ 15424, // Rule ID 505 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2995:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 505,
+ GIR_Done,
+ // Label 512: @15424
+ GIM_Try, /*On fail goto*//*Label 513*/ 15476, // Rule ID 506 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 2996:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 506,
+ GIR_Done,
+ // Label 513: @15476
+ GIM_Try, /*On fail goto*//*Label 514*/ 15528, // Rule ID 507 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2994:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 507,
+ GIR_Done,
+ // Label 514: @15528
+ GIM_Try, /*On fail goto*//*Label 515*/ 15580, // Rule ID 508 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 2997:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 508,
+ GIR_Done,
+ // Label 515: @15580
+ GIM_Try, /*On fail goto*//*Label 516*/ 15632, // Rule ID 509 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 2999:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 509,
+ GIR_Done,
+ // Label 516: @15632
+ GIM_Try, /*On fail goto*//*Label 517*/ 15684, // Rule ID 510 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3000:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 510,
+ GIR_Done,
+ // Label 517: @15684
+ GIM_Try, /*On fail goto*//*Label 518*/ 15736, // Rule ID 511 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_aver_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 2998:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::AVER_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 511,
+ GIR_Done,
+ // Label 518: @15736
+ GIM_Try, /*On fail goto*//*Label 519*/ 15788, // Rule ID 620 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3132:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 620,
+ GIR_Done,
+ // Label 519: @15788
+ GIM_Try, /*On fail goto*//*Label 520*/ 15840, // Rule ID 621 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3133:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 621,
+ GIR_Done,
+ // Label 520: @15840
+ GIM_Try, /*On fail goto*//*Label 521*/ 15892, // Rule ID 622 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3131:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 622,
+ GIR_Done,
+ // Label 521: @15892
+ GIM_Try, /*On fail goto*//*Label 522*/ 15944, // Rule ID 623 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3135:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 623,
+ GIR_Done,
+ // Label 522: @15944
+ GIM_Try, /*On fail goto*//*Label 523*/ 15996, // Rule ID 624 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3136:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 624,
+ GIR_Done,
+ // Label 523: @15996
+ GIM_Try, /*On fail goto*//*Label 524*/ 16048, // Rule ID 625 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dotp_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3134:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DOTP_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 625,
+ GIR_Done,
+ // Label 524: @16048
+ GIM_Try, /*On fail goto*//*Label 525*/ 16100, // Rule ID 640 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3174:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 640,
+ GIR_Done,
+ // Label 525: @16100
+ GIM_Try, /*On fail goto*//*Label 526*/ 16152, // Rule ID 641 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fcaf_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3173:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FCAF_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 641,
+ GIR_Done,
+ // Label 526: @16152
+ GIM_Try, /*On fail goto*//*Label 527*/ 16204, // Rule ID 666 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8f16] } 3199:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 666,
+ GIR_Done,
+ // Label 527: @16204
+ GIM_Try, /*On fail goto*//*Label 528*/ 16256, // Rule ID 667 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fexdo_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3200:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXDO_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 667,
+ GIR_Done,
+ // Label 528: @16256
+ GIM_Try, /*On fail goto*//*Label 529*/ 16308, // Rule ID 694 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3226:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 694,
+ GIR_Done,
+ // Label 529: @16308
+ GIM_Try, /*On fail goto*//*Label 530*/ 16360, // Rule ID 695 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3225:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 695,
+ GIR_Done,
+ // Label 530: @16360
+ GIM_Try, /*On fail goto*//*Label 531*/ 16412, // Rule ID 696 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3224:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 696,
+ GIR_Done,
+ // Label 531: @16412
+ GIM_Try, /*On fail goto*//*Label 532*/ 16464, // Rule ID 697 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmax_a_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3223:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMAX_A_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 697,
+ GIR_Done,
+ // Label 532: @16464
+ GIM_Try, /*On fail goto*//*Label 533*/ 16516, // Rule ID 698 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3230:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 698,
+ GIR_Done,
+ // Label 533: @16516
+ GIM_Try, /*On fail goto*//*Label 534*/ 16568, // Rule ID 699 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3229:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 699,
+ GIR_Done,
+ // Label 534: @16568
+ GIM_Try, /*On fail goto*//*Label 535*/ 16620, // Rule ID 700 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4f32] } 3228:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 700,
+ GIR_Done,
+ // Label 535: @16620
+ GIM_Try, /*On fail goto*//*Label 536*/ 16672, // Rule ID 701 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fmin_a_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2f64] } 3227:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMIN_A_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 701,
+ GIR_Done,
+ // Label 536: @16672
+ GIM_Try, /*On fail goto*//*Label 537*/ 16724, // Rule ID 712 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3242:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 712,
+ GIR_Done,
+ // Label 537: @16724
+ GIM_Try, /*On fail goto*//*Label 538*/ 16776, // Rule ID 713 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsaf_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3241:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSAF_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 713,
+ GIR_Done,
+ // Label 538: @16776
+ GIM_Try, /*On fail goto*//*Label 539*/ 16828, // Rule ID 714 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3244:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 714,
+ GIR_Done,
+ // Label 539: @16828
+ GIM_Try, /*On fail goto*//*Label 540*/ 16880, // Rule ID 715 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fseq_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3243:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSEQ_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 715,
+ GIR_Done,
+ // Label 540: @16880
+ GIM_Try, /*On fail goto*//*Label 541*/ 16932, // Rule ID 716 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3246:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 716,
+ GIR_Done,
+ // Label 541: @16932
+ GIM_Try, /*On fail goto*//*Label 542*/ 16984, // Rule ID 717 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsle_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3245:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLE_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 717,
+ GIR_Done,
+ // Label 542: @16984
+ GIM_Try, /*On fail goto*//*Label 543*/ 17036, // Rule ID 718 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3248:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 718,
+ GIR_Done,
+ // Label 543: @17036
+ GIM_Try, /*On fail goto*//*Label 544*/ 17088, // Rule ID 719 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fslt_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3247:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSLT_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 719,
+ GIR_Done,
+ // Label 544: @17088
+ GIM_Try, /*On fail goto*//*Label 545*/ 17140, // Rule ID 720 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3250:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 720,
+ GIR_Done,
+ // Label 545: @17140
+ GIM_Try, /*On fail goto*//*Label 546*/ 17192, // Rule ID 721 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsne_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3249:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSNE_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 721,
+ GIR_Done,
+ // Label 546: @17192
+ GIM_Try, /*On fail goto*//*Label 547*/ 17244, // Rule ID 722 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3252:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 722,
+ GIR_Done,
+ // Label 547: @17244
+ GIM_Try, /*On fail goto*//*Label 548*/ 17296, // Rule ID 723 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsor_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3251:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSOR_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 723,
+ GIR_Done,
+ // Label 548: @17296
+ GIM_Try, /*On fail goto*//*Label 549*/ 17348, // Rule ID 728 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3258:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 728,
+ GIR_Done,
+ // Label 549: @17348
+ GIM_Try, /*On fail goto*//*Label 550*/ 17400, // Rule ID 729 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsueq_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3257:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUEQ_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 729,
+ GIR_Done,
+ // Label 550: @17400
+ GIM_Try, /*On fail goto*//*Label 551*/ 17452, // Rule ID 730 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3260:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 730,
+ GIR_Done,
+ // Label 551: @17452
+ GIM_Try, /*On fail goto*//*Label 552*/ 17504, // Rule ID 731 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsule_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3259:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULE_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 731,
+ GIR_Done,
+ // Label 552: @17504
+ GIM_Try, /*On fail goto*//*Label 553*/ 17556, // Rule ID 732 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3262:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 732,
+ GIR_Done,
+ // Label 553: @17556
+ GIM_Try, /*On fail goto*//*Label 554*/ 17608, // Rule ID 733 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsult_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3261:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSULT_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 733,
+ GIR_Done,
+ // Label 554: @17608
+ GIM_Try, /*On fail goto*//*Label 555*/ 17660, // Rule ID 734 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3264:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 734,
+ GIR_Done,
+ // Label 555: @17660
+ GIM_Try, /*On fail goto*//*Label 556*/ 17712, // Rule ID 735 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsun_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3263:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUN_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 735,
+ GIR_Done,
+ // Label 556: @17712
+ GIM_Try, /*On fail goto*//*Label 557*/ 17764, // Rule ID 736 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3266:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 736,
+ GIR_Done,
+ // Label 557: @17764
+ GIM_Try, /*On fail goto*//*Label 558*/ 17816, // Rule ID 737 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_fsune_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3265:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUNE_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 737,
+ GIR_Done,
+ // Label 558: @17816
+ GIM_Try, /*On fail goto*//*Label 559*/ 17868, // Rule ID 742 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3271:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 742,
+ GIR_Done,
+ // Label 559: @17868
+ GIM_Try, /*On fail goto*//*Label 560*/ 17920, // Rule ID 743 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_ftq_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3272:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FTQ_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 743,
+ GIR_Done,
+ // Label 560: @17920
+ GIM_Try, /*On fail goto*//*Label 561*/ 17972, // Rule ID 748 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3278:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 748,
+ GIR_Done,
+ // Label 561: @17972
+ GIM_Try, /*On fail goto*//*Label 562*/ 18024, // Rule ID 749 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3279:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 749,
+ GIR_Done,
+ // Label 562: @18024
+ GIM_Try, /*On fail goto*//*Label 563*/ 18076, // Rule ID 750 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3277:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 750,
+ GIR_Done,
+ // Label 563: @18076
+ GIM_Try, /*On fail goto*//*Label 564*/ 18128, // Rule ID 751 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3281:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 751,
+ GIR_Done,
+ // Label 564: @18128
+ GIM_Try, /*On fail goto*//*Label 565*/ 18180, // Rule ID 752 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3282:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 752,
+ GIR_Done,
+ // Label 565: @18180
+ GIM_Try, /*On fail goto*//*Label 566*/ 18232, // Rule ID 753 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hadd_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3280:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HADD_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 753,
+ GIR_Done,
+ // Label 566: @18232
+ GIM_Try, /*On fail goto*//*Label 567*/ 18284, // Rule ID 754 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3284:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 754,
+ GIR_Done,
+ // Label 567: @18284
+ GIM_Try, /*On fail goto*//*Label 568*/ 18336, // Rule ID 755 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3285:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 755,
+ GIR_Done,
+ // Label 568: @18336
+ GIM_Try, /*On fail goto*//*Label 569*/ 18388, // Rule ID 756 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3283:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 756,
+ GIR_Done,
+ // Label 569: @18388
+ GIM_Try, /*On fail goto*//*Label 570*/ 18440, // Rule ID 757 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3287:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 757,
+ GIR_Done,
+ // Label 570: @18440
+ GIM_Try, /*On fail goto*//*Label 571*/ 18492, // Rule ID 758 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3288:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 758,
+ GIR_Done,
+ // Label 571: @18492
+ GIM_Try, /*On fail goto*//*Label 572*/ 18544, // Rule ID 759 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_hsub_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3286:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::HSUB_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 759,
+ GIR_Done,
+ // Label 572: @18544
+ GIM_Try, /*On fail goto*//*Label 573*/ 18596, // Rule ID 812 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3340:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 812,
+ GIR_Done,
+ // Label 573: @18596
+ GIM_Try, /*On fail goto*//*Label 574*/ 18648, // Rule ID 813 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3342:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 813,
+ GIR_Done,
+ // Label 574: @18648
+ GIM_Try, /*On fail goto*//*Label 575*/ 18700, // Rule ID 814 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3343:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 814,
+ GIR_Done,
+ // Label 575: @18700
+ GIM_Try, /*On fail goto*//*Label 576*/ 18752, // Rule ID 815 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_max_a_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3341:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MAX_A_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 815,
+ GIR_Done,
+ // Label 576: @18752
+ GIM_Try, /*On fail goto*//*Label 577*/ 18804, // Rule ID 832 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3360:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 832,
+ GIR_Done,
+ // Label 577: @18804
+ GIM_Try, /*On fail goto*//*Label 578*/ 18856, // Rule ID 833 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3362:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 833,
+ GIR_Done,
+ // Label 578: @18856
+ GIM_Try, /*On fail goto*//*Label 579*/ 18908, // Rule ID 834 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3363:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 834,
+ GIR_Done,
+ // Label 579: @18908
+ GIM_Try, /*On fail goto*//*Label 580*/ 18960, // Rule ID 835 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_min_a_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3361:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MIN_A_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 835,
+ GIR_Done,
+ // Label 580: @18960
+ GIM_Try, /*On fail goto*//*Label 581*/ 19012, // Rule ID 868 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3402:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 868,
+ GIR_Done,
+ // Label 581: @19012
+ GIM_Try, /*On fail goto*//*Label 582*/ 19064, // Rule ID 869 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_q_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3403:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_Q_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 869,
+ GIR_Done,
+ // Label 582: @19064
+ GIM_Try, /*On fail goto*//*Label 583*/ 19116, // Rule ID 870 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3413:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 870,
+ GIR_Done,
+ // Label 583: @19116
+ GIM_Try, /*On fail goto*//*Label 584*/ 19168, // Rule ID 871 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulr_q_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3414:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULR_Q_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 871,
+ GIR_Done,
+ // Label 584: @19168
+ GIM_Try, /*On fail goto*//*Label 585*/ 19220, // Rule ID 949 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3527:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 949,
+ GIR_Done,
+ // Label 585: @19220
+ GIM_Try, /*On fail goto*//*Label 586*/ 19272, // Rule ID 950 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3529:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 950,
+ GIR_Done,
+ // Label 586: @19272
+ GIM_Try, /*On fail goto*//*Label 587*/ 19324, // Rule ID 951 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3530:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 951,
+ GIR_Done,
+ // Label 587: @19324
+ GIM_Try, /*On fail goto*//*Label 588*/ 19376, // Rule ID 952 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srar_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3528:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRAR_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 952,
+ GIR_Done,
+ // Label 588: @19376
+ GIM_Try, /*On fail goto*//*Label 589*/ 19428, // Rule ID 965 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3543:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 965,
+ GIR_Done,
+ // Label 589: @19428
+ GIM_Try, /*On fail goto*//*Label 590*/ 19480, // Rule ID 966 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3545:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 966,
+ GIR_Done,
+ // Label 590: @19480
+ GIM_Try, /*On fail goto*//*Label 591*/ 19532, // Rule ID 967 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3546:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 967,
+ GIR_Done,
+ // Label 591: @19532
+ GIM_Try, /*On fail goto*//*Label 592*/ 19584, // Rule ID 968 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_srlr_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3544:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRLR_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 968,
+ GIR_Done,
+ // Label 592: @19584
+ GIM_Try, /*On fail goto*//*Label 593*/ 19636, // Rule ID 977 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3562:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 977,
+ GIR_Done,
+ // Label 593: @19636
+ GIM_Try, /*On fail goto*//*Label 594*/ 19688, // Rule ID 978 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3564:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 978,
+ GIR_Done,
+ // Label 594: @19688
+ GIM_Try, /*On fail goto*//*Label 595*/ 19740, // Rule ID 979 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3565:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 979,
+ GIR_Done,
+ // Label 595: @19740
+ GIM_Try, /*On fail goto*//*Label 596*/ 19792, // Rule ID 980 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3563:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 980,
+ GIR_Done,
+ // Label 596: @19792
+ GIM_Try, /*On fail goto*//*Label 597*/ 19844, // Rule ID 981 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3566:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 981,
+ GIR_Done,
+ // Label 597: @19844
+ GIM_Try, /*On fail goto*//*Label 598*/ 19896, // Rule ID 982 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3568:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 982,
+ GIR_Done,
+ // Label 598: @19896
+ GIM_Try, /*On fail goto*//*Label 599*/ 19948, // Rule ID 983 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3569:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 983,
+ GIR_Done,
+ // Label 599: @19948
+ GIM_Try, /*On fail goto*//*Label 600*/ 20000, // Rule ID 984 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subs_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3567:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBS_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 984,
+ GIR_Done,
+ // Label 600: @20000
+ GIM_Try, /*On fail goto*//*Label 601*/ 20052, // Rule ID 985 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3570:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 985,
+ GIR_Done,
+ // Label 601: @20052
+ GIM_Try, /*On fail goto*//*Label 602*/ 20104, // Rule ID 986 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3572:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 986,
+ GIR_Done,
+ // Label 602: @20104
+ GIM_Try, /*On fail goto*//*Label 603*/ 20156, // Rule ID 987 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3573:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 987,
+ GIR_Done,
+ // Label 603: @20156
+ GIM_Try, /*On fail goto*//*Label 604*/ 20208, // Rule ID 988 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsus_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3571:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUS_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 988,
+ GIR_Done,
+ // Label 604: @20208
+ GIM_Try, /*On fail goto*//*Label 605*/ 20260, // Rule ID 989 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3574:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 989,
+ GIR_Done,
+ // Label 605: @20260
+ GIM_Try, /*On fail goto*//*Label 606*/ 20312, // Rule ID 990 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3576:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 990,
+ GIR_Done,
+ // Label 606: @20312
+ GIM_Try, /*On fail goto*//*Label 607*/ 20364, // Rule ID 991 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3577:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 991,
+ GIR_Done,
+ // Label 607: @20364
+ GIM_Try, /*On fail goto*//*Label 608*/ 20416, // Rule ID 992 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subsuu_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3575:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBSUU_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 992,
+ GIR_Done,
+ // Label 608: @20416
+ GIM_Try, /*On fail goto*//*Label 609*/ 20468, // Rule ID 1180 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 2940:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1180,
+ GIR_Done,
+ // Label 609: @20468
+ GIM_Try, /*On fail goto*//*Label 610*/ 20520, // Rule ID 1182 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 2962:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1182,
+ GIR_Done,
+ // Label 610: @20520
+ GIM_Try, /*On fail goto*//*Label 611*/ 20572, // Rule ID 1203 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3488:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1203,
+ GIR_Done,
+ // Label 611: @20572
+ GIM_Try, /*On fail goto*//*Label 612*/ 20624, // Rule ID 1204 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3490:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1204,
+ GIR_Done,
+ // Label 612: @20624
+ GIM_Try, /*On fail goto*//*Label 613*/ 20676, // Rule ID 1205 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3492:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1205,
+ GIR_Done,
+ // Label 613: @20676
+ GIM_Try, /*On fail goto*//*Label 614*/ 20728, // Rule ID 1207 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3494:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1207,
+ GIR_Done,
+ // Label 614: @20728
+ GIM_Try, /*On fail goto*//*Label 615*/ 20780, // Rule ID 1218 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3556:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1218,
+ GIR_Done,
+ // Label 615: @20780
+ GIM_Try, /*On fail goto*//*Label 616*/ 20832, // Rule ID 1220 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3581:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1220,
+ GIR_Done,
+ // Label 616: @20832
+ GIM_Try, /*On fail goto*//*Label 617*/ 20884, // Rule ID 1230 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_ph_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_PH_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1230,
+ GIR_Done,
+ // Label 617: @20884
+ GIM_Try, /*On fail goto*//*Label 618*/ 20936, // Rule ID 1231 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_qb_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3464:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_QB_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1231,
+ GIR_Done,
+ // Label 618: @20936
+ GIM_Try, /*On fail goto*//*Label 619*/ 20988, // Rule ID 1250 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_packrl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3435:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PACKRL_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1250,
+ GIR_Done,
+ // Label 619: @20988
+ GIM_Try, /*On fail goto*//*Label 620*/ 21040, // Rule ID 1256 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_modsub,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3388:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MODSUB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1256,
+ GIR_Done,
+ // Label 620: @21040
+ GIM_Try, /*On fail goto*//*Label 621*/ 21092, // Rule ID 1269 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 2942:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1269,
+ GIR_Done,
+ // Label 621: @21092
+ GIM_Try, /*On fail goto*//*Label 622*/ 21144, // Rule ID 1270 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 2943:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1270,
+ GIR_Done,
+ // Label 622: @21144
+ GIM_Try, /*On fail goto*//*Label 623*/ 21196, // Rule ID 1271 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 2945:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_W_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1271,
+ GIR_Done,
+ // Label 623: @21196
+ GIM_Try, /*On fail goto*//*Label 624*/ 21248, // Rule ID 1272 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addqh_r_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 2944:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQH_R_W_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1272,
+ GIR_Done,
+ // Label 624: @21248
+ GIM_Try, /*On fail goto*//*Label 625*/ 21300, // Rule ID 1275 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 2963:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1275,
+ GIR_Done,
+ // Label 625: @21300
+ GIM_Try, /*On fail goto*//*Label 626*/ 21352, // Rule ID 1276 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_adduh_r_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 2964:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDUH_R_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1276,
+ GIR_Done,
+ // Label 626: @21352
+ GIM_Try, /*On fail goto*//*Label 627*/ 21404, // Rule ID 1282 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3489:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1282,
+ GIR_Done,
+ // Label 627: @21404
+ GIM_Try, /*On fail goto*//*Label 628*/ 21456, // Rule ID 1283 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shra_r_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3491:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRAV_R_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1283,
+ GIR_Done,
+ // Label 628: @21456
+ GIM_Try, /*On fail goto*//*Label 629*/ 21508, // Rule ID 1288 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shrl_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3493:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHRLV_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1288,
+ GIR_Done,
+ // Label 629: @21508
+ GIM_Try, /*On fail goto*//*Label 630*/ 21560, // Rule ID 1289 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3558:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1289,
+ GIR_Done,
+ // Label 630: @21560
+ GIM_Try, /*On fail goto*//*Label 631*/ 21612, // Rule ID 1290 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3559:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1290,
+ GIR_Done,
+ // Label 631: @21612
+ GIM_Try, /*On fail goto*//*Label 632*/ 21664, // Rule ID 1291 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3561:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_W_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1291,
+ GIR_Done,
+ // Label 632: @21664
+ GIM_Try, /*On fail goto*//*Label 633*/ 21716, // Rule ID 1292 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subqh_r_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[i32] } 3560:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQH_R_W_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1292,
+ GIR_Done,
+ // Label 633: @21716
+ GIM_Try, /*On fail goto*//*Label 634*/ 21768, // Rule ID 1295 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3582:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1295,
+ GIR_Done,
+ // Label 634: @21768
+ GIM_Try, /*On fail goto*//*Label 635*/ 21820, // Rule ID 1296 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subuh_r_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3583:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBUH_R_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1296,
+ GIR_Done,
+ // Label 635: @21820
+ GIM_Try, /*On fail goto*//*Label 636*/ 21864, // Rule ID 1833 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 2939:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1833,
+ GIR_Done,
+ // Label 636: @21864
+ GIM_Try, /*On fail goto*//*Label 637*/ 21908, // Rule ID 1835 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3555:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1835,
+ GIR_Done,
+ // Label 637: @21908
+ GIM_Try, /*On fail goto*//*Label 638*/ 21952, // Rule ID 1839 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 2960:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1839,
+ GIR_Done,
+ // Label 638: @21952
+ GIM_Try, /*On fail goto*//*Label 639*/ 21996, // Rule ID 1841 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i8] } 3579:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1841,
+ GIR_Done,
+ // Label 639: @21996
+ GIM_Reject,
+ // Label 425: @21997
+ GIM_Try, /*On fail goto*//*Label 640*/ 25045,
+ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
+ GIM_Try, /*On fail goto*//*Label 641*/ 22073, // Rule ID 449 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3461:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 449,
+ GIR_Done,
+ // Label 641: @22073
+ GIM_Try, /*On fail goto*//*Label 642*/ 22144, // Rule ID 450 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3462:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 450,
+ GIR_Done,
+ // Label 642: @22144
+ GIM_Try, /*On fail goto*//*Label 643*/ 22215, // Rule ID 455 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[i32] } 2976:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 455,
+ GIR_Done,
+ // Label 643: @22215
+ GIM_Try, /*On fail goto*//*Label 644*/ 22286, // Rule ID 456 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[i32] } 3001:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$sa) => (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 456,
+ GIR_Done,
+ // Label 644: @22286
+ GIM_Try, /*On fail goto*//*Label 645*/ 22357, // Rule ID 457 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[i32] } 3467:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 457,
+ GIR_Done,
+ // Label 645: @22357
+ GIM_Try, /*On fail goto*//*Label 646*/ 22428, // Rule ID 921 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3499:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$n) => (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (imm:{ *:[i32] }):$n)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 921,
+ GIR_Done,
+ // Label 646: @22428
+ GIM_Try, /*On fail goto*//*Label 647*/ 22499, // Rule ID 922 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3501:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$n) => (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (imm:{ *:[i32] }):$n)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 922,
+ GIR_Done,
+ // Label 647: @22499
+ GIM_Try, /*On fail goto*//*Label 648*/ 22570, // Rule ID 923 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3502:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$n) => (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (imm:{ *:[i32] }):$n)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 923,
+ GIR_Done,
+ // Label 648: @22570
+ GIM_Try, /*On fail goto*//*Label 649*/ 22641, // Rule ID 924 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sldi_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt1,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3500:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt1>>:$n) => (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (imm:{ *:[i32] }):$n)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLDI_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // n
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 924,
+ GIR_Done,
+ // Label 649: @22641
+ GIM_Try, /*On fail goto*//*Label 650*/ 22712, // Rule ID 1284 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_balign,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[i32] } 3001:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp) => (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BALIGN_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1284,
+ GIR_Done,
+ // Label 650: @22712
+ GIM_Try, /*On fail goto*//*Label 651*/ 22783, // Rule ID 1306 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_ph_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3461:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_PH_W_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1306,
+ GIR_Done,
+ // Label 651: @22783
+ GIM_Try, /*On fail goto*//*Label 652*/ 22854, // Rule ID 1307 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_sra_r_ph_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[v2i16] } 3462:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_SRA_R_PH_W_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1307,
+ GIR_Done,
+ // Label 652: @22854
+ GIM_Try, /*On fail goto*//*Label 653*/ 22925, // Rule ID 1308 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_prepend,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[i32] } 3467:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PREPEND_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1308,
+ GIR_Done,
+ // Label 653: @22925
+ GIM_Try, /*On fail goto*//*Label 654*/ 22996, // Rule ID 1309 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_append,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_wo_chain:{ *:[i32] } 2976:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::APPEND_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1309,
+ GIR_Done,
+ // Label 654: @22996
+ GIM_Try, /*On fail goto*//*Label 655*/ 23060, // Rule ID 520 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3010:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 520,
+ GIR_Done,
+ // Label 655: @23060
+ GIM_Try, /*On fail goto*//*Label 656*/ 23124, // Rule ID 521 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3012:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 521,
+ GIR_Done,
+ // Label 656: @23124
+ GIM_Try, /*On fail goto*//*Label 657*/ 23188, // Rule ID 522 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3013:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 522,
+ GIR_Done,
+ // Label 657: @23188
+ GIM_Try, /*On fail goto*//*Label 658*/ 23252, // Rule ID 523 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsl_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3011:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSL_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 523,
+ GIR_Done,
+ // Label 658: @23252
+ GIM_Try, /*On fail goto*//*Label 659*/ 23316, // Rule ID 528 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3018:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 528,
+ GIR_Done,
+ // Label 659: @23316
+ GIM_Try, /*On fail goto*//*Label 660*/ 23380, // Rule ID 529 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3020:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 529,
+ GIR_Done,
+ // Label 660: @23380
+ GIM_Try, /*On fail goto*//*Label 661*/ 23444, // Rule ID 530 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3021:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 530,
+ GIR_Done,
+ // Label 661: @23444
+ GIM_Try, /*On fail goto*//*Label 662*/ 23508, // Rule ID 531 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_binsr_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128DRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3019:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BINSR_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 531,
+ GIR_Done,
+ // Label 662: @23508
+ GIM_Try, /*On fail goto*//*Label 663*/ 23572, // Rule ID 626 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3139:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 626,
+ GIR_Done,
+ // Label 663: @23572
+ GIM_Try, /*On fail goto*//*Label 664*/ 23636, // Rule ID 627 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3140:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 627,
+ GIR_Done,
+ // Label 664: @23636
+ GIM_Try, /*On fail goto*//*Label 665*/ 23700, // Rule ID 628 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3138:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 628,
+ GIR_Done,
+ // Label 665: @23700
+ GIM_Try, /*On fail goto*//*Label 666*/ 23764, // Rule ID 629 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3142:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 629,
+ GIR_Done,
+ // Label 666: @23764
+ GIM_Try, /*On fail goto*//*Label 667*/ 23828, // Rule ID 630 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3143:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 630,
+ GIR_Done,
+ // Label 667: @23828
+ GIM_Try, /*On fail goto*//*Label 668*/ 23892, // Rule ID 631 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpadd_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3141:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPADD_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 631,
+ GIR_Done,
+ // Label 668: @23892
+ GIM_Try, /*On fail goto*//*Label 669*/ 23956, // Rule ID 632 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3159:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 632,
+ GIR_Done,
+ // Label 669: @23956
+ GIM_Try, /*On fail goto*//*Label 670*/ 24020, // Rule ID 633 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3160:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 633,
+ GIR_Done,
+ // Label 670: @24020
+ GIM_Try, /*On fail goto*//*Label 671*/ 24084, // Rule ID 634 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_s_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3158:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 634,
+ GIR_Done,
+ // Label 671: @24084
+ GIM_Try, /*On fail goto*//*Label 672*/ 24148, // Rule ID 635 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128BRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3162:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 635,
+ GIR_Done,
+ // Label 672: @24148
+ GIM_Try, /*On fail goto*//*Label 673*/ 24212, // Rule ID 636 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3163:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 636,
+ GIR_Done,
+ // Label 673: @24212
+ GIM_Try, /*On fail goto*//*Label 674*/ 24276, // Rule ID 637 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_dpsub_u_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3161:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DPSUB_U_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 637,
+ GIR_Done,
+ // Label 674: @24276
+ GIM_Try, /*On fail goto*//*Label 675*/ 24340, // Rule ID 804 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3327:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 804,
+ GIR_Done,
+ // Label 675: @24340
+ GIM_Try, /*On fail goto*//*Label 676*/ 24404, // Rule ID 805 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_madd_q_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3328:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_Q_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 805,
+ GIR_Done,
+ // Label 676: @24404
+ GIM_Try, /*On fail goto*//*Label 677*/ 24468, // Rule ID 806 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3329:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 806,
+ GIR_Done,
+ // Label 677: @24468
+ GIM_Try, /*On fail goto*//*Label 678*/ 24532, // Rule ID 807 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_maddr_q_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3330:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDR_Q_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 807,
+ GIR_Done,
+ // Label 678: @24532
+ GIM_Try, /*On fail goto*//*Label 679*/ 24596, // Rule ID 860 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3391:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 860,
+ GIR_Done,
+ // Label 679: @24596
+ GIM_Try, /*On fail goto*//*Label 680*/ 24660, // Rule ID 861 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msub_q_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3392:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_Q_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 861,
+ GIR_Done,
+ // Label 680: @24660
+ GIM_Try, /*On fail goto*//*Label 681*/ 24724, // Rule ID 862 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128HRegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3393:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 862,
+ GIR_Done,
+ // Label 681: @24724
+ GIM_Try, /*On fail goto*//*Label 682*/ 24788, // Rule ID 863 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_msubr_q_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::MSA128WRegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3394:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBR_Q_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 863,
+ GIR_Done,
+ // Label 682: @24788
+ GIM_Try, /*On fail goto*//*Label 683*/ 24852, // Rule ID 917 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_b,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v16i8] } 3495:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_B,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 917,
+ GIR_Done,
+ // Label 683: @24852
+ GIM_Try, /*On fail goto*//*Label 684*/ 24916, // Rule ID 918 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_h,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v8i16] } 3497:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_H,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 918,
+ GIR_Done,
+ // Label 684: @24916
+ GIM_Try, /*On fail goto*//*Label 685*/ 24980, // Rule ID 919 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v4i32] } 3498:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 919,
+ GIR_Done,
+ // Label 685: @24980
+ GIM_Try, /*On fail goto*//*Label 686*/ 25044, // Rule ID 920 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_sld_d,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_wo_chain:{ *:[v2i64] } 3496:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt) => (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // rt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 920,
+ GIR_Done,
+ // Label 686: @25044
+ GIM_Reject,
+ // Label 640: @25045
+ GIM_Reject,
+ // Label 15: @25046
+ GIM_Try, /*On fail goto*//*Label 687*/ 25079, // Rule ID 326 //
+ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_bposge32,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3044:{ *:[iPTR] }) => (BPOSGE32_PSEUDO:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BPOSGE32_PSEUDO,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 326,
+ GIR_Done,
+ // Label 687: @25079
+ GIM_Try, /*On fail goto*//*Label 688*/ 25981,
+ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
+ GIM_Try, /*On fail goto*//*Label 689*/ 25136, // Rule ID 413 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_rddsp,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt10,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_w_chain:{ *:[i32] } 3469:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt10>>:$mask) => (RDDSP:{ *:[i32] } (imm:{ *:[i32] }):$mask)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::RDDSP,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // mask
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 413,
+ GIR_Done,
+ // Label 689: @25136
+ GIM_Try, /*On fail goto*//*Label 690*/ 25188, // Rule ID 414 //
+ GIM_CheckFeatures, GIFBS_HasDSP_NotInMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_wrdsp,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt10,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_void 3596:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt10>>:$mask) => (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$mask)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::WRDSP,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // mask
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 414,
+ GIR_Done,
+ // Label 690: @25188
+ GIM_Try, /*On fail goto*//*Label 691*/ 25232, // Rule ID 335 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 2932:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt) => (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 335,
+ GIR_Done,
+ // Label 691: @25232
+ GIM_Try, /*On fail goto*//*Label 692*/ 25276, // Rule ID 336 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 2934:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt) => (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 336,
+ GIR_Done,
+ // Label 692: @25276
+ GIM_Try, /*On fail goto*//*Label 693*/ 25320, // Rule ID 422 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 2933:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt) => (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 422,
+ GIR_Done,
+ // Label 693: @25320
+ GIM_Try, /*On fail goto*//*Label 694*/ 25364, // Rule ID 1187 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 2932:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs) => (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1187,
+ GIR_Done,
+ // Label 694: @25364
+ GIM_Try, /*On fail goto*//*Label 695*/ 25408, // Rule ID 1188 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 2934:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs) => (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1188,
+ GIR_Done,
+ // Label 695: @25408
+ GIM_Try, /*On fail goto*//*Label 696*/ 25452, // Rule ID 1268 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_absq_s_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 2933:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs) => (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ABSQ_S_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1268,
+ GIR_Done,
+ // Label 696: @25452
+ GIM_Try, /*On fail goto*//*Label 697*/ 25496, // Rule ID 389 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3110:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 389,
+ GIR_Done,
+ // Label 697: @25496
+ GIM_Try, /*On fail goto*//*Label 698*/ 25540, // Rule ID 390 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3112:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 390,
+ GIR_Done,
+ // Label 698: @25540
+ GIM_Try, /*On fail goto*//*Label 699*/ 25584, // Rule ID 391 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 391,
+ GIR_Done,
+ // Label 699: @25584
+ GIM_Try, /*On fail goto*//*Label 700*/ 25628, // Rule ID 395 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3101:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 395,
+ GIR_Done,
+ // Label 700: @25628
+ GIM_Try, /*On fail goto*//*Label 701*/ 25672, // Rule ID 396 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3103:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 396,
+ GIR_Done,
+ // Label 701: @25672
+ GIM_Try, /*On fail goto*//*Label 702*/ 25716, // Rule ID 397 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3102:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 397,
+ GIR_Done,
+ // Label 702: @25716
+ GIM_Try, /*On fail goto*//*Label 703*/ 25760, // Rule ID 1259 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_eq_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3101:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_EQ_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1259,
+ GIR_Done,
+ // Label 703: @25760
+ GIM_Try, /*On fail goto*//*Label 704*/ 25804, // Rule ID 1260 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_lt_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3103:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LT_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1260,
+ GIR_Done,
+ // Label 704: @25804
+ GIM_Try, /*On fail goto*//*Label 705*/ 25848, // Rule ID 1261 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmp_le_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3102:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMP_LE_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1261,
+ GIR_Done,
+ // Label 705: @25848
+ GIM_Try, /*On fail goto*//*Label 706*/ 25892, // Rule ID 1265 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_eq_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3110:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_EQ_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1265,
+ GIR_Done,
+ // Label 706: @25892
+ GIM_Try, /*On fail goto*//*Label 707*/ 25936, // Rule ID 1266 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_lt_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3112:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LT_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1266,
+ GIR_Done,
+ // Label 707: @25936
+ GIM_Try, /*On fail goto*//*Label 708*/ 25980, // Rule ID 1267 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mips_cmpu_le_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_void 3111:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPU_LE_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1267,
+ GIR_Done,
+ // Label 708: @25980
+ GIM_Reject,
+ // Label 688: @25981
+ GIM_Try, /*On fail goto*//*Label 709*/ 29969,
+ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
+ GIM_Try, /*On fail goto*//*Label 710*/ 26050, // Rule ID 354 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa) => (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 354,
+ GIR_Done,
+ // Label 710: @26050
+ GIM_Try, /*On fail goto*//*Label 711*/ 26114, // Rule ID 359 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa) => (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 359,
+ GIR_Done,
+ // Label 711: @26114
+ GIM_Try, /*On fail goto*//*Label 712*/ 26178, // Rule ID 1196 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa) => (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1196,
+ GIR_Done,
+ // Label 712: @26178
+ GIM_Try, /*On fail goto*//*Label 713*/ 26242, // Rule ID 1201 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa) => (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_S_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1201,
+ GIR_Done,
+ // Label 713: @26242
+ GIM_Try, /*On fail goto*//*Label 714*/ 26297, // Rule ID 1850 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt4,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt) => (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1850,
+ GIR_Done,
+ // Label 714: @26297
+ GIM_Try, /*On fail goto*//*Label 715*/ 26352, // Rule ID 1856 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt3,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt) => (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLL_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1856,
+ GIR_Done,
+ // Label 715: @26352
+ GIM_Try, /*On fail goto*//*Label 716*/ 26408, // Rule ID 331 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 2941:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 331,
+ GIR_Done,
+ // Label 716: @26408
+ GIM_Try, /*On fail goto*//*Label 717*/ 26464, // Rule ID 332 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3557:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 332,
+ GIR_Done,
+ // Label 717: @26464
+ GIM_Try, /*On fail goto*//*Label 718*/ 26520, // Rule ID 339 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3465:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 339,
+ GIR_Done,
+ // Label 718: @26520
+ GIM_Try, /*On fail goto*//*Label 719*/ 26576, // Rule ID 340 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 340,
+ GIR_Done,
+ // Label 719: @26576
+ GIM_Try, /*On fail goto*//*Label 720*/ 26632, // Rule ID 351 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 351,
+ GIR_Done,
+ // Label 720: @26632
+ GIM_Try, /*On fail goto*//*Label 721*/ 26688, // Rule ID 353 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 353,
+ GIR_Done,
+ // Label 721: @26688
+ GIM_Try, /*On fail goto*//*Label 722*/ 26744, // Rule ID 355 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 355,
+ GIR_Done,
+ // Label 722: @26744
+ GIM_Try, /*On fail goto*//*Label 723*/ 26800, // Rule ID 360 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa) => (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs_sa
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 360,
+ GIR_Done,
+ // Label 723: @26800
+ GIM_Try, /*On fail goto*//*Label 724*/ 26856, // Rule ID 363 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 363,
+ GIR_Done,
+ // Label 724: @26856
+ GIM_Try, /*On fail goto*//*Label 725*/ 26912, // Rule ID 364 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 364,
+ GIR_Done,
+ // Label 725: @26912
+ GIM_Try, /*On fail goto*//*Label 726*/ 26968, // Rule ID 365 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3405:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 365,
+ GIR_Done,
+ // Label 726: @26968
+ GIM_Try, /*On fail goto*//*Label 727*/ 27024, // Rule ID 366 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3406:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 366,
+ GIR_Done,
+ // Label 727: @27024
+ GIM_Try, /*On fail goto*//*Label 728*/ 27080, // Rule ID 367 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3409:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 367,
+ GIR_Done,
+ // Label 728: @27080
+ GIM_Try, /*On fail goto*//*Label 729*/ 27136, // Rule ID 392 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3107:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 392,
+ GIR_Done,
+ // Label 729: @27136
+ GIM_Try, /*On fail goto*//*Label 730*/ 27192, // Rule ID 393 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3109:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 393,
+ GIR_Done,
+ // Label 730: @27192
+ GIM_Try, /*On fail goto*//*Label 731*/ 27248, // Rule ID 394 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3108:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 394,
+ GIR_Done,
+ // Label 731: @27248
+ GIM_Try, /*On fail goto*//*Label 732*/ 27304, // Rule ID 404 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 404,
+ GIR_Done,
+ // Label 732: @27304
+ GIM_Try, /*On fail goto*//*Label 733*/ 27360, // Rule ID 405 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3448:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 405,
+ GIR_Done,
+ // Label 733: @27360
+ GIM_Try, /*On fail goto*//*Label 734*/ 27416, // Rule ID 409 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3309:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 409,
+ GIR_Done,
+ // Label 734: @27416
+ GIM_Try, /*On fail goto*//*Label 735*/ 27472, // Rule ID 415 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 2959:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 415,
+ GIR_Done,
+ // Label 735: @27472
+ GIM_Try, /*On fail goto*//*Label 736*/ 27528, // Rule ID 416 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 2961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 416,
+ GIR_Done,
+ // Label 736: @27528
+ GIM_Try, /*On fail goto*//*Label 737*/ 27584, // Rule ID 417 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3578:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 417,
+ GIR_Done,
+ // Label 737: @27584
+ GIM_Try, /*On fail goto*//*Label 738*/ 27640, // Rule ID 418 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3580:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 418,
+ GIR_Done,
+ // Label 738: @27640
+ GIM_Try, /*On fail goto*//*Label 739*/ 27696, // Rule ID 419 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3104:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 419,
+ GIR_Done,
+ // Label 739: @27696
+ GIM_Try, /*On fail goto*//*Label 740*/ 27752, // Rule ID 420 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3106:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 420,
+ GIR_Done,
+ // Label 740: @27752
+ GIM_Try, /*On fail goto*//*Label 741*/ 27808, // Rule ID 421 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3105:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 421,
+ GIR_Done,
+ // Label 741: @27808
+ GIM_Try, /*On fail goto*//*Label 742*/ 27864, // Rule ID 435 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3404:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 435,
+ GIR_Done,
+ // Label 742: @27864
+ GIM_Try, /*On fail goto*//*Label 743*/ 27920, // Rule ID 436 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3412:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 436,
+ GIR_Done,
+ // Label 743: @27920
+ GIM_Try, /*On fail goto*//*Label 744*/ 27976, // Rule ID 437 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3410:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 437,
+ GIR_Done,
+ // Label 744: @27976
+ GIM_Try, /*On fail goto*//*Label 745*/ 28032, // Rule ID 438 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3411:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 438,
+ GIR_Done,
+ // Label 745: @28032
+ GIM_Try, /*On fail goto*//*Label 746*/ 28088, // Rule ID 448 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3460:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 448,
+ GIR_Done,
+ // Label 746: @28088
+ GIM_Try, /*On fail goto*//*Label 747*/ 28144, // Rule ID 1181 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addq_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 2941:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDQ_S_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1181,
+ GIR_Done,
+ // Label 747: @28144
+ GIM_Try, /*On fail goto*//*Label 748*/ 28200, // Rule ID 1189 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_insv,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3309:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs) => (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::INSV_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1189,
+ GIR_Done,
+ // Label 748: @28200
+ GIM_Try, /*On fail goto*//*Label 749*/ 28256, // Rule ID 1197 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3484:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1197,
+ GIR_Done,
+ // Label 749: @28256
+ GIM_Try, /*On fail goto*//*Label 750*/ 28312, // Rule ID 1198 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1198,
+ GIR_Done,
+ // Label 750: @28312
+ GIM_Try, /*On fail goto*//*Label 751*/ 28368, // Rule ID 1199 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3485:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1199,
+ GIR_Done,
+ // Label 751: @28368
+ GIM_Try, /*On fail goto*//*Label 752*/ 28424, // Rule ID 1200 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_shll_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3487:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SHLLV_S_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1200,
+ GIR_Done,
+ // Label 752: @28424
+ GIM_Try, /*On fail goto*//*Label 753*/ 28480, // Rule ID 1219 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subq_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3557:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBQ_S_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1219,
+ GIR_Done,
+ // Label 753: @28480
+ GIM_Try, /*On fail goto*//*Label 754*/ 28536, // Rule ID 1225 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3405:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHL_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1225,
+ GIR_Done,
+ // Label 754: @28536
+ GIM_Try, /*On fail goto*//*Label 755*/ 28592, // Rule ID 1226 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleq_s_w_phr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3406:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEQ_S_W_PHR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1226,
+ GIR_Done,
+ // Label 755: @28592
+ GIM_Try, /*On fail goto*//*Label 756*/ 28648, // Rule ID 1227 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbl,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3407:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBL_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1227,
+ GIR_Done,
+ // Label 756: @28648
+ GIM_Try, /*On fail goto*//*Label 757*/ 28704, // Rule ID 1228 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_muleu_s_ph_qbr,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3408:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULEU_S_PH_QBR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1228,
+ GIR_Done,
+ // Label 757: @28704
+ GIM_Try, /*On fail goto*//*Label 758*/ 28760, // Rule ID 1229 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3409:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1229,
+ GIR_Done,
+ // Label 758: @28760
+ GIM_Try, /*On fail goto*//*Label 759*/ 28816, // Rule ID 1232 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrqu_s_qb_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3466:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQU_S_QB_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1232,
+ GIR_Done,
+ // Label 759: @28816
+ GIM_Try, /*On fail goto*//*Label 760*/ 28872, // Rule ID 1233 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precrq_rs_ph_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3465:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECRQ_RS_PH_W_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1233,
+ GIR_Done,
+ // Label 760: @28872
+ GIM_Try, /*On fail goto*//*Label 761*/ 28928, // Rule ID 1251 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3448:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_PH_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1251,
+ GIR_Done,
+ // Label 761: @28928
+ GIM_Try, /*On fail goto*//*Label 762*/ 28984, // Rule ID 1252 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_pick_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PICK_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1252,
+ GIR_Done,
+ // Label 762: @28984
+ GIM_Try, /*On fail goto*//*Label 763*/ 29040, // Rule ID 1262 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_eq_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3107:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_EQ_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1262,
+ GIR_Done,
+ // Label 763: @29040
+ GIM_Try, /*On fail goto*//*Label 764*/ 29096, // Rule ID 1263 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_lt_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3109:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LT_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1263,
+ GIR_Done,
+ // Label 764: @29096
+ GIM_Try, /*On fail goto*//*Label 765*/ 29152, // Rule ID 1264 //
+ GIM_CheckFeatures, GIFBS_HasDSP_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgu_le_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3108:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGU_LE_QB_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1264,
+ GIR_Done,
+ // Label 765: @29152
+ GIM_Try, /*On fail goto*//*Label 766*/ 29208, // Rule ID 1273 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 2959:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1273,
+ GIR_Done,
+ // Label 766: @29208
+ GIM_Try, /*On fail goto*//*Label 767*/ 29264, // Rule ID 1274 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addu_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 2961:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDU_S_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1274,
+ GIR_Done,
+ // Label 767: @29264
+ GIM_Try, /*On fail goto*//*Label 768*/ 29320, // Rule ID 1285 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_eq_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3104:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_EQ_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1285,
+ GIR_Done,
+ // Label 768: @29320
+ GIM_Try, /*On fail goto*//*Label 769*/ 29376, // Rule ID 1286 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_lt_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3106:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LT_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1286,
+ GIR_Done,
+ // Label 769: @29376
+ GIM_Try, /*On fail goto*//*Label 770*/ 29432, // Rule ID 1287 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_cmpgdu_le_qb,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3105:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt) => (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::CMPGDU_LE_QB_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1287,
+ GIR_Done,
+ // Label 770: @29432
+ GIM_Try, /*On fail goto*//*Label 771*/ 29488, // Rule ID 1293 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3578:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1293,
+ GIR_Done,
+ // Label 771: @29488
+ GIM_Try, /*On fail goto*//*Label 772*/ 29544, // Rule ID 1294 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_subu_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3580:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SUBU_S_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1294,
+ GIR_Done,
+ // Label 772: @29544
+ GIM_Try, /*On fail goto*//*Label 773*/ 29600, // Rule ID 1301 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3404:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_S_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1301,
+ GIR_Done,
+ // Label 773: @29600
+ GIM_Try, /*On fail goto*//*Label 774*/ 29656, // Rule ID 1302 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_rs_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3410:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_RS_W_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1302,
+ GIR_Done,
+ // Label 774: @29656
+ GIM_Try, /*On fail goto*//*Label 775*/ 29712, // Rule ID 1303 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3411:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1303,
+ GIR_Done,
+ // Label 775: @29712
+ GIM_Try, /*On fail goto*//*Label 776*/ 29768, // Rule ID 1304 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mulq_s_w,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 3412:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MULQ_S_W_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1304,
+ GIR_Done,
+ // Label 776: @29768
+ GIM_Try, /*On fail goto*//*Label 777*/ 29824, // Rule ID 1305 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2_InMicroMips,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_precr_qb_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::DSPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v4i8] } 3460:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt) => (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::PRECR_QB_PH_MMR2,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rt
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1305,
+ GIR_Done,
+ // Label 777: @29824
+ GIM_Try, /*On fail goto*//*Label 778*/ 29872, // Rule ID 1837 //
+ GIM_CheckFeatures, GIFBS_HasDSPR2,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_mul_ph,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
+ // (intrinsic_w_chain:{ *:[v2i16] } 3401:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MUL_PH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1837,
+ GIR_Done,
+ // Label 778: @29872
+ GIM_Try, /*On fail goto*//*Label 779*/ 29920, // Rule ID 1843 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addsc,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 2958:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDSC,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1843,
+ GIR_Done,
+ // Label 779: @29920
+ GIM_Try, /*On fail goto*//*Label 780*/ 29968, // Rule ID 1845 //
+ GIM_CheckFeatures, GIFBS_HasDSP,
+ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mips_addwc,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ // (intrinsic_w_chain:{ *:[i32] } 2973:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b) => (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDWC,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // a
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // b
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1845,
+ GIR_Done,
+ // Label 780: @29968
+ GIM_Reject,
+ // Label 709: @29969
+ GIM_Reject,
+ // Label 16: @29970
+ GIM_Try, /*On fail goto*//*Label 781*/ 30026, // Rule ID 1514 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src) => (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1514,
+ GIR_Done,
+ // Label 781: @30026
+ GIM_Reject,
+ // Label 17: @30027
+ GIM_Try, /*On fail goto*//*Label 782*/ 30086,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 783*/ 30059, // Rule ID 2059 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_immLi16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ // MIs[0] Operand 1
+ // No operand predicates
+ // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm => (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LI16_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2059,
+ GIR_Done,
+ // Label 783: @30059
+ GIM_Try, /*On fail goto*//*Label 784*/ 30085, // Rule ID 1761 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ // MIs[0] Operand 1
+ // No operand predicates
+ // (imm:{ *:[i32] }):$imm => (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LwConstant32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
+ GIR_AddImm, /*InsnID*/0, /*Imm*/-1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1761,
+ GIR_Done,
+ // Label 784: @30085
+ GIM_Reject,
+ // Label 782: @30086
+ GIM_Reject,
+ // Label 18: @30087
+ GIM_Try, /*On fail goto*//*Label 785*/ 30114, // Rule ID 1521 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL64_32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1521,
+ GIR_Done,
+ // Label 785: @30114
+ GIM_Reject,
+ // Label 19: @30115
+ GIM_Try, /*On fail goto*//*Label 786*/ 30199,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 787*/ 30172, // Rule ID 1520 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
+ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSLL64_32,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/32,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1520,
+ GIR_Done,
+ // Label 787: @30172
+ GIM_Try, /*On fail goto*//*Label 788*/ 30198, // Rule ID 1522 //
+ GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
+ // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src) => (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DEXT64_32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/32,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1522,
+ GIR_Done,
+ // Label 788: @30198
+ GIM_Reject,
+ // Label 786: @30199
+ GIM_Reject,
+ // Label 20: @30200
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 795*/ 30723,
+ /*GILLT_s32*//*Label 789*/ 30214,
+ /*GILLT_s64*//*Label 790*/ 30467, 0,
+ /*GILLT_v2s64*//*Label 791*/ 30595, 0,
+ /*GILLT_v4s32*//*Label 792*/ 30627,
+ /*GILLT_v8s16*//*Label 793*/ 30659,
+ /*GILLT_v16s8*//*Label 794*/ 30691,
+ // Label 789: @30214
+ GIM_Try, /*On fail goto*//*Label 796*/ 30466,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 797*/ 30267, // Rule ID 43 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 43,
+ GIR_Done,
+ // Label 797: @30267
+ GIM_Try, /*On fail goto*//*Label 798*/ 30310, // Rule ID 1743 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SllX16,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1743,
+ GIR_Done,
+ // Label 798: @30310
+ GIM_Try, /*On fail goto*//*Label 799*/ 30353, // Rule ID 2071 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL16_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2071,
+ GIR_Done,
+ // Label 799: @30353
+ GIM_Try, /*On fail goto*//*Label 800*/ 30396, // Rule ID 2072 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SLL_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2072,
+ GIR_Done,
+ // Label 800: @30396
+ GIM_Try, /*On fail goto*//*Label 801*/ 30419, // Rule ID 46 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 46,
+ GIR_Done,
+ // Label 801: @30419
+ GIM_Try, /*On fail goto*//*Label 802*/ 30442, // Rule ID 1746 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SllvRxRy16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1746,
+ GIR_Done,
+ // Label 802: @30442
+ GIM_Try, /*On fail goto*//*Label 803*/ 30465, // Rule ID 2073 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLLV_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2073,
+ GIR_Done,
+ // Label 803: @30465
+ GIM_Reject,
+ // Label 796: @30466
+ GIM_Reject,
+ // Label 790: @30467
+ GIM_Try, /*On fail goto*//*Label 804*/ 30594,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 805*/ 30520, // Rule ID 188 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 188,
+ GIR_Done,
+ // Label 805: @30520
+ GIM_Try, /*On fail goto*//*Label 806*/ 30578, // Rule ID 1515 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSLLV,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1515,
+ GIR_Done,
+ // Label 806: @30578
+ GIM_Try, /*On fail goto*//*Label 807*/ 30593, // Rule ID 191 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSLLV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 191,
+ GIR_Done,
+ // Label 807: @30593
+ GIM_Reject,
+ // Label 804: @30594
+ GIM_Reject,
+ // Label 791: @30595
+ GIM_Try, /*On fail goto*//*Label 808*/ 30626, // Rule ID 928 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 928,
+ GIR_Done,
+ // Label 808: @30626
+ GIM_Reject,
+ // Label 792: @30627
+ GIM_Try, /*On fail goto*//*Label 809*/ 30658, // Rule ID 927 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 927,
+ GIR_Done,
+ // Label 809: @30658
+ GIM_Reject,
+ // Label 793: @30659
+ GIM_Try, /*On fail goto*//*Label 810*/ 30690, // Rule ID 926 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 926,
+ GIR_Done,
+ // Label 810: @30690
+ GIM_Reject,
+ // Label 794: @30691
+ GIM_Try, /*On fail goto*//*Label 811*/ 30722, // Rule ID 925 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SLL_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 925,
+ GIR_Done,
+ // Label 811: @30722
+ GIM_Reject,
+ // Label 795: @30723
+ GIM_Reject,
+ // Label 21: @30724
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 818*/ 31247,
+ /*GILLT_s32*//*Label 812*/ 30738,
+ /*GILLT_s64*//*Label 813*/ 30991, 0,
+ /*GILLT_v2s64*//*Label 814*/ 31119, 0,
+ /*GILLT_v4s32*//*Label 815*/ 31151,
+ /*GILLT_v8s16*//*Label 816*/ 31183,
+ /*GILLT_v16s8*//*Label 817*/ 31215,
+ // Label 812: @30738
+ GIM_Try, /*On fail goto*//*Label 819*/ 30990,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 820*/ 30791, // Rule ID 44 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 44,
+ GIR_Done,
+ // Label 820: @30791
+ GIM_Try, /*On fail goto*//*Label 821*/ 30834, // Rule ID 1744 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SrlX16,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1744,
+ GIR_Done,
+ // Label 821: @30834
+ GIM_Try, /*On fail goto*//*Label 822*/ 30877, // Rule ID 2074 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt2Shift,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm) => (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL16_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2074,
+ GIR_Done,
+ // Label 822: @30877
+ GIM_Try, /*On fail goto*//*Label 823*/ 30920, // Rule ID 2075 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRL_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2075,
+ GIR_Done,
+ // Label 823: @30920
+ GIM_Try, /*On fail goto*//*Label 824*/ 30943, // Rule ID 47 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 47,
+ GIR_Done,
+ // Label 824: @30943
+ GIM_Try, /*On fail goto*//*Label 825*/ 30966, // Rule ID 1748 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SrlvRxRy16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1748,
+ GIR_Done,
+ // Label 825: @30966
+ GIM_Try, /*On fail goto*//*Label 826*/ 30989, // Rule ID 2076 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRLV_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2076,
+ GIR_Done,
+ // Label 826: @30989
+ GIM_Reject,
+ // Label 819: @30990
+ GIM_Reject,
+ // Label 813: @30991
+ GIM_Try, /*On fail goto*//*Label 827*/ 31118,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 828*/ 31044, // Rule ID 189 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 189,
+ GIR_Done,
+ // Label 828: @31044
+ GIM_Try, /*On fail goto*//*Label 829*/ 31102, // Rule ID 1516 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRLV,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1516,
+ GIR_Done,
+ // Label 829: @31102
+ GIM_Try, /*On fail goto*//*Label 830*/ 31117, // Rule ID 193 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRLV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 193,
+ GIR_Done,
+ // Label 830: @31117
+ GIM_Reject,
+ // Label 827: @31118
+ GIM_Reject,
+ // Label 814: @31119
+ GIM_Try, /*On fail goto*//*Label 831*/ 31150, // Rule ID 960 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 960,
+ GIR_Done,
+ // Label 831: @31150
+ GIM_Reject,
+ // Label 815: @31151
+ GIM_Try, /*On fail goto*//*Label 832*/ 31182, // Rule ID 959 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 959,
+ GIR_Done,
+ // Label 832: @31182
+ GIM_Reject,
+ // Label 816: @31183
+ GIM_Try, /*On fail goto*//*Label 833*/ 31214, // Rule ID 958 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 958,
+ GIR_Done,
+ // Label 833: @31214
+ GIM_Reject,
+ // Label 817: @31215
+ GIM_Try, /*On fail goto*//*Label 834*/ 31246, // Rule ID 957 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRL_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 957,
+ GIR_Done,
+ // Label 834: @31246
+ GIM_Reject,
+ // Label 818: @31247
+ GIM_Reject,
+ // Label 22: @31248
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 841*/ 31728,
+ /*GILLT_s32*//*Label 835*/ 31262,
+ /*GILLT_s64*//*Label 836*/ 31472, 0,
+ /*GILLT_v2s64*//*Label 837*/ 31600, 0,
+ /*GILLT_v4s32*//*Label 838*/ 31632,
+ /*GILLT_v8s16*//*Label 839*/ 31664,
+ /*GILLT_v16s8*//*Label 840*/ 31696,
+ // Label 835: @31262
+ GIM_Try, /*On fail goto*//*Label 842*/ 31471,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 843*/ 31315, // Rule ID 45 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt) => (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 45,
+ GIR_Done,
+ // Label 843: @31315
+ GIM_Try, /*On fail goto*//*Label 844*/ 31358, // Rule ID 1745 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SraX16,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // in
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1745,
+ GIR_Done,
+ // Label 844: @31358
+ GIM_Try, /*On fail goto*//*Label 845*/ 31401, // Rule ID 2077 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt5,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm) => (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SRA_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2077,
+ GIR_Done,
+ // Label 845: @31401
+ GIM_Try, /*On fail goto*//*Label 846*/ 31424, // Rule ID 48 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 48,
+ GIR_Done,
+ // Label 846: @31424
+ GIM_Try, /*On fail goto*//*Label 847*/ 31447, // Rule ID 1747 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra) => (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SravRxRy16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1747,
+ GIR_Done,
+ // Label 847: @31447
+ GIM_Try, /*On fail goto*//*Label 848*/ 31470, // Rule ID 2078 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs) => (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRAV_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2078,
+ GIR_Done,
+ // Label 848: @31470
+ GIM_Reject,
+ // Label 842: @31471
+ GIM_Reject,
+ // Label 836: @31472
+ GIM_Try, /*On fail goto*//*Label 849*/ 31599,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 850*/ 31525, // Rule ID 190 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExt6,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt) => (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 190,
+ GIR_Done,
+ // Label 850: @31525
+ GIM_Try, /*On fail goto*//*Label 851*/ 31583, // Rule ID 1517 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_IsGP64bit,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_TRUNC,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs)) => (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/TargetOpcode::COPY,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/1, // rs
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSRAV,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1517,
+ GIR_Done,
+ // Label 851: @31583
+ GIM_Try, /*On fail goto*//*Label 852*/ 31598, // Rule ID 192 //
+ GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs) => (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSRAV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 192,
+ GIR_Done,
+ // Label 852: @31598
+ GIM_Reject,
+ // Label 849: @31599
+ GIM_Reject,
+ // Label 837: @31600
+ GIM_Try, /*On fail goto*//*Label 853*/ 31631, // Rule ID 944 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 944,
+ GIR_Done,
+ // Label 853: @31631
+ GIM_Reject,
+ // Label 838: @31632
+ GIM_Try, /*On fail goto*//*Label 854*/ 31663, // Rule ID 943 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 943,
+ GIR_Done,
+ // Label 854: @31663
+ GIM_Reject,
+ // Label 839: @31664
+ GIM_Try, /*On fail goto*//*Label 855*/ 31695, // Rule ID 942 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
+ // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_H,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 942,
+ GIR_Done,
+ // Label 855: @31695
+ GIM_Reject,
+ // Label 840: @31696
+ GIM_Try, /*On fail goto*//*Label 856*/ 31727, // Rule ID 941 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
+ // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SRA_B,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 941,
+ GIR_Done,
+ // Label 856: @31727
+ GIM_Reject,
+ // Label 841: @31728
+ GIM_Reject,
+ // Label 23: @31729
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 859*/ 33182,
+ /*GILLT_s32*//*Label 857*/ 31737,
+ /*GILLT_s64*//*Label 858*/ 32536,
+ // Label 857: @31737
+ GIM_Try, /*On fail goto*//*Label 860*/ 31776, // Rule ID 267 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F) => (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 267,
+ GIR_Done,
+ // Label 860: @31776
+ GIM_Try, /*On fail goto*//*Label 861*/ 31815, // Rule ID 269 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
+ // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F) => (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 269,
+ GIR_Done,
+ // Label 861: @31815
+ GIM_Try, /*On fail goto*//*Label 862*/ 31871, // Rule ID 306 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
+ // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 306,
+ GIR_Done,
+ // Label 862: @31871
+ GIM_Try, /*On fail goto*//*Label 863*/ 31927, // Rule ID 1170 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGRCCRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
+ // (select:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs) => (SEL_S_MMR6:{ *:[f32] } FGRCCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SEL_S_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fd_in
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1170,
+ GIR_Done,
+ // Label 863: @31927
+ GIM_Try, /*On fail goto*//*Label 864*/ 31983, // Rule ID 1567 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1567,
+ GIR_Done,
+ // Label 864: @31983
+ GIM_Try, /*On fail goto*//*Label 865*/ 32039, // Rule ID 1606 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1606,
+ GIR_Done,
+ // Label 865: @32039
+ GIM_Try, /*On fail goto*//*Label 866*/ 32095, // Rule ID 1622 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
+ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1622,
+ GIR_Done,
+ // Label 866: @32095
+ GIM_Try, /*On fail goto*//*Label 867*/ 32151, // Rule ID 1635 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
+ // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1635,
+ GIR_Done,
+ // Label 867: @32151
+ GIM_Try, /*On fail goto*//*Label 868*/ 32207, // Rule ID 1792 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::CPU16RegsRegClassID,
+ // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y) => (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::SelBneZ,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd_
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // x
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // y
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1792,
+ GIR_Done,
+ // Label 868: @32207
+ GIM_Try, /*On fail goto*//*Label 869*/ 32263, // Rule ID 2128 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2128,
+ GIR_Done,
+ // Label 869: @32263
+ GIM_Try, /*On fail goto*//*Label 870*/ 32319, // Rule ID 2142 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR32RegClassID,
+ // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F) => (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2142,
+ GIR_Done,
+ // Label 870: @32319
+ GIM_Try, /*On fail goto*//*Label 871*/ 32375, // Rule ID 2170 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR32RegClassID,
+ // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F) => (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_S_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2170,
+ GIR_Done,
+ // Label 871: @32375
+ GIM_Try, /*On fail goto*//*Label 872*/ 32455, // Rule ID 1704 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1704,
+ GIR_Done,
+ // Label 872: @32455
+ GIM_Try, /*On fail goto*//*Label 873*/ 32535, // Rule ID 2187 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f) => (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ_MMR6,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ_MMR6,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2187,
+ GIR_Done,
+ // Label 873: @32535
+ GIM_Reject,
+ // Label 858: @32536
+ GIM_Try, /*On fail goto*//*Label 874*/ 32575, // Rule ID 268 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotMips4_32,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
+ // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F) => (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_I64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 268,
+ GIR_Done,
+ // Label 874: @32575
+ GIM_Try, /*On fail goto*//*Label 875*/ 32614, // Rule ID 270 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
+ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 270,
+ GIR_Done,
+ // Label 875: @32614
+ GIM_Try, /*On fail goto*//*Label 876*/ 32653, // Rule ID 271 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
+ // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F) => (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoSELECT_D64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 271,
+ GIR_Done,
+ // Label 876: @32653
+ GIM_Try, /*On fail goto*//*Label 877*/ 32709, // Rule ID 1603 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
+ // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_I64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1603,
+ GIR_Done,
+ // Label 877: @32709
+ GIM_Try, /*On fail goto*//*Label 878*/ 32765, // Rule ID 1609 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::GPR64RegClassID,
+ // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F) => (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_I64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1609,
+ GIR_Done,
+ // Label 878: @32765
+ GIM_Try, /*On fail goto*//*Label 879*/ 32821, // Rule ID 1648 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
+ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1648,
+ GIR_Done,
+ // Label 879: @32821
+ GIM_Try, /*On fail goto*//*Label 880*/ 32877, // Rule ID 1671 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
+ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1671,
+ GIR_Done,
+ // Label 880: @32877
+ GIM_Try, /*On fail goto*//*Label 881*/ 32933, // Rule ID 1674 //
+ GIM_CheckFeatures, GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::FGR64RegClassID,
+ // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F) => (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I64_D64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1674,
+ GIR_Done,
+ // Label 881: @32933
+ GIM_Try, /*On fail goto*//*Label 882*/ 32989, // Rule ID 2183 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::AFGR64RegClassID,
+ // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F) => (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MOVN_I_D32_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // T
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // F
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2183,
+ GIR_Done,
+ // Label 882: @32989
+ GIM_Try, /*On fail goto*//*Label 883*/ 33069, // Rule ID 1707 //
+ GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SELEQZ64,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1707,
+ GIR_Done,
+ // Label 883: @33069
+ GIM_Try, /*On fail goto*//*Label 884*/ 33181, // Rule ID 1718 //
+ GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f) => (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/4, /*Opcode*/Mips::SLL64_32,
+ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/Mips::SELEQZ64,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/Mips::SLL64_32,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::SELNEZ64,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::OR64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1718,
+ GIR_Done,
+ // Label 884: @33181
+ GIM_Reject,
+ // Label 859: @33182
+ GIM_Reject,
+ // Label 24: @33183
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 889*/ 34061,
+ /*GILLT_s32*//*Label 885*/ 33195,
+ /*GILLT_s64*//*Label 886*/ 33395, 0,
+ /*GILLT_v2s64*//*Label 887*/ 33743, 0,
+ /*GILLT_v4s32*//*Label 888*/ 33902,
+ // Label 885: @33195
+ GIM_Try, /*On fail goto*//*Label 890*/ 33394,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 891*/ 33266, // Rule ID 145 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 145,
+ GIR_Done,
+ // Label 891: @33266
+ GIM_Try, /*On fail goto*//*Label 892*/ 33323, // Rule ID 2241 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)) => (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2241,
+ GIR_Done,
+ // Label 892: @33323
+ GIM_Try, /*On fail goto*//*Label 893*/ 33342, // Rule ID 133 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 133,
+ GIR_Done,
+ // Label 893: @33342
+ GIM_Try, /*On fail goto*//*Label 894*/ 33361, // Rule ID 1089 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_S_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1089,
+ GIR_Done,
+ // Label 894: @33361
+ GIM_Try, /*On fail goto*//*Label 895*/ 33393, // Rule ID 1145 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FADD_S_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1145,
+ GIR_Done,
+ // Label 895: @33393
+ GIM_Reject,
+ // Label 890: @33394
+ GIM_Reject,
+ // Label 886: @33395
+ GIM_Try, /*On fail goto*//*Label 896*/ 33742,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 897*/ 33466, // Rule ID 147 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 147,
+ GIR_Done,
+ // Label 897: @33466
+ GIM_Try, /*On fail goto*//*Label 898*/ 33527, // Rule ID 149 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 149,
+ GIR_Done,
+ // Label 898: @33527
+ GIM_Try, /*On fail goto*//*Label 899*/ 33588, // Rule ID 2242 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2242,
+ GIR_Done,
+ // Label 899: @33588
+ GIM_Try, /*On fail goto*//*Label 900*/ 33649, // Rule ID 2243 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)) => (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADD_D64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2243,
+ GIR_Done,
+ // Label 900: @33649
+ GIM_Try, /*On fail goto*//*Label 901*/ 33672, // Rule ID 134 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 134,
+ GIR_Done,
+ // Label 901: @33672
+ GIM_Try, /*On fail goto*//*Label 902*/ 33695, // Rule ID 135 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 135,
+ GIR_Done,
+ // Label 902: @33695
+ GIM_Try, /*On fail goto*//*Label 903*/ 33718, // Rule ID 1093 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D32_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1093,
+ GIR_Done,
+ // Label 903: @33718
+ GIM_Try, /*On fail goto*//*Label 904*/ 33741, // Rule ID 1094 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D64_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1094,
+ GIR_Done,
+ // Label 904: @33741
+ GIM_Reject,
+ // Label 896: @33742
+ GIM_Reject,
+ // Label 887: @33743
+ GIM_Try, /*On fail goto*//*Label 905*/ 33901,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_Try, /*On fail goto*//*Label 906*/ 33815, // Rule ID 2348 //
+ GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
+ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2348,
+ GIR_Done,
+ // Label 906: @33815
+ GIM_Try, /*On fail goto*//*Label 907*/ 33877, // Rule ID 1901 //
+ GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
+ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1901,
+ GIR_Done,
+ // Label 907: @33877
+ GIM_Try, /*On fail goto*//*Label 908*/ 33900, // Rule ID 639 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 639,
+ GIR_Done,
+ // Label 908: @33900
+ GIM_Reject,
+ // Label 905: @33901
+ GIM_Reject,
+ // Label 888: @33902
+ GIM_Try, /*On fail goto*//*Label 909*/ 34060,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_Try, /*On fail goto*//*Label 910*/ 33974, // Rule ID 2347 //
+ GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
+ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/2,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2347,
+ GIR_Done,
+ // Label 910: @33974
+ GIM_Try, /*On fail goto*//*Label 911*/ 34036, // Rule ID 1900 //
+ GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
+ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMADD_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1900,
+ GIR_Done,
+ // Label 911: @34036
+ GIM_Try, /*On fail goto*//*Label 912*/ 34059, // Rule ID 638 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FADD_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 638,
+ GIR_Done,
+ // Label 912: @34059
+ GIM_Reject,
+ // Label 909: @34060
+ GIM_Reject,
+ // Label 889: @34061
+ GIM_Reject,
+ // Label 25: @34062
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 917*/ 34637,
+ /*GILLT_s32*//*Label 913*/ 34074,
+ /*GILLT_s64*//*Label 914*/ 34217, 0,
+ /*GILLT_v2s64*//*Label 915*/ 34443, 0,
+ /*GILLT_v4s32*//*Label 916*/ 34540,
+ // Label 913: @34074
+ GIM_Try, /*On fail goto*//*Label 918*/ 34216,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 919*/ 34145, // Rule ID 146 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr) => (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 146,
+ GIR_Done,
+ // Label 919: @34145
+ GIM_Try, /*On fail goto*//*Label 920*/ 34164, // Rule ID 142 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 142,
+ GIR_Done,
+ // Label 920: @34164
+ GIM_Try, /*On fail goto*//*Label 921*/ 34183, // Rule ID 1092 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_S_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1092,
+ GIR_Done,
+ // Label 921: @34183
+ GIM_Try, /*On fail goto*//*Label 922*/ 34215, // Rule ID 1146 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FSUB_S_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1146,
+ GIR_Done,
+ // Label 922: @34215
+ GIM_Reject,
+ // Label 918: @34216
+ GIM_Reject,
+ // Label 914: @34217
+ GIM_Try, /*On fail goto*//*Label 923*/ 34442,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 924*/ 34288, // Rule ID 148 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 148,
+ GIR_Done,
+ // Label 924: @34288
+ GIM_Try, /*On fail goto*//*Label 925*/ 34349, // Rule ID 150 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr) => (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUB_D64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 150,
+ GIR_Done,
+ // Label 925: @34349
+ GIM_Try, /*On fail goto*//*Label 926*/ 34372, // Rule ID 143 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 143,
+ GIR_Done,
+ // Label 926: @34372
+ GIM_Try, /*On fail goto*//*Label 927*/ 34395, // Rule ID 144 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 144,
+ GIR_Done,
+ // Label 927: @34395
+ GIM_Try, /*On fail goto*//*Label 928*/ 34418, // Rule ID 1099 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D32_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1099,
+ GIR_Done,
+ // Label 928: @34418
+ GIM_Try, /*On fail goto*//*Label 929*/ 34441, // Rule ID 1100 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D64_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1100,
+ GIR_Done,
+ // Label 929: @34441
+ GIM_Reject,
+ // Label 923: @34442
+ GIM_Reject,
+ // Label 915: @34443
+ GIM_Try, /*On fail goto*//*Label 930*/ 34539,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_Try, /*On fail goto*//*Label 931*/ 34515, // Rule ID 1899 //
+ GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
+ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1899,
+ GIR_Done,
+ // Label 931: @34515
+ GIM_Try, /*On fail goto*//*Label 932*/ 34538, // Rule ID 727 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 727,
+ GIR_Done,
+ // Label 932: @34538
+ GIM_Reject,
+ // Label 930: @34539
+ GIM_Reject,
+ // Label 916: @34540
+ GIM_Try, /*On fail goto*//*Label 933*/ 34636,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_Try, /*On fail goto*//*Label 934*/ 34612, // Rule ID 1898 //
+ GIM_CheckFeatures, GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
+ GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/0, /*OtherMI*/0, /*OtherOpIdx*/1,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMSUB_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1898,
+ GIR_Done,
+ // Label 934: @34612
+ GIM_Try, /*On fail goto*//*Label 935*/ 34635, // Rule ID 726 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FSUB_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 726,
+ GIR_Done,
+ // Label 935: @34635
+ GIM_Reject,
+ // Label 933: @34636
+ GIM_Reject,
+ // Label 917: @34637
+ GIM_Reject,
+ // Label 26: @34638
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 940*/ 35074,
+ /*GILLT_s32*//*Label 936*/ 34650,
+ /*GILLT_s64*//*Label 937*/ 34720, 0,
+ /*GILLT_v2s64*//*Label 938*/ 34824, 0,
+ /*GILLT_v4s32*//*Label 939*/ 34949,
+ // Label 936: @34650
+ GIM_Try, /*On fail goto*//*Label 941*/ 34719,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 942*/ 34683, // Rule ID 139 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 139,
+ GIR_Done,
+ // Label 942: @34683
+ GIM_Try, /*On fail goto*//*Label 943*/ 34694, // Rule ID 1091 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
+ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_S_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1091,
+ GIR_Done,
+ // Label 943: @34694
+ GIM_Try, /*On fail goto*//*Label 944*/ 34718, // Rule ID 1147 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
+ // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FMUL_S_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1147,
+ GIR_Done,
+ // Label 944: @34718
+ GIM_Reject,
+ // Label 941: @34719
+ GIM_Reject,
+ // Label 937: @34720
+ GIM_Try, /*On fail goto*//*Label 945*/ 34823,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 946*/ 34753, // Rule ID 140 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 140,
+ GIR_Done,
+ // Label 946: @34753
+ GIM_Try, /*On fail goto*//*Label 947*/ 34776, // Rule ID 141 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 141,
+ GIR_Done,
+ // Label 947: @34776
+ GIM_Try, /*On fail goto*//*Label 948*/ 34799, // Rule ID 1097 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D32_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1097,
+ GIR_Done,
+ // Label 948: @34799
+ GIM_Try, /*On fail goto*//*Label 949*/ 34822, // Rule ID 1098 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D64_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1098,
+ GIR_Done,
+ // Label 949: @34822
+ GIM_Reject,
+ // Label 945: @34823
+ GIM_Reject,
+ // Label 938: @34824
+ GIM_Try, /*On fail goto*//*Label 950*/ 34948,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_Try, /*On fail goto*//*Label 951*/ 34883, // Rule ID 2289 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2289,
+ GIR_Done,
+ // Label 951: @34883
+ GIM_Try, /*On fail goto*//*Label 952*/ 34928, // Rule ID 669 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt)) => (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 669,
+ GIR_Done,
+ // Label 952: @34928
+ GIM_Try, /*On fail goto*//*Label 953*/ 34947, // Rule ID 705 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 705,
+ GIR_Done,
+ // Label 953: @34947
+ GIM_Reject,
+ // Label 950: @34948
+ GIM_Reject,
+ // Label 939: @34949
+ GIM_Try, /*On fail goto*//*Label 954*/ 35073,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_Try, /*On fail goto*//*Label 955*/ 35008, // Rule ID 2288 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2288,
+ GIR_Done,
+ // Label 955: @35008
+ GIM_Try, /*On fail goto*//*Label 956*/ 35053, // Rule ID 668 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FEXP2,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt)) => (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FEXP2_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ws
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 668,
+ GIR_Done,
+ // Label 956: @35053
+ GIM_Try, /*On fail goto*//*Label 957*/ 35072, // Rule ID 704 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMUL_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 704,
+ GIR_Done,
+ // Label 957: @35072
+ GIM_Reject,
+ // Label 954: @35073
+ GIM_Reject,
+ // Label 940: @35074
+ GIM_Reject,
+ // Label 27: @35075
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 960*/ 35164,
+ /*GILLT_v2s64*//*Label 958*/ 35084, 0,
+ /*GILLT_v4s32*//*Label 959*/ 35124,
+ // Label 958: @35084
+ GIM_Try, /*On fail goto*//*Label 961*/ 35123, // Rule ID 693 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128DRegClassID,
+ // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 693,
+ GIR_Done,
+ // Label 961: @35123
+ GIM_Reject,
+ // Label 959: @35124
+ GIM_Try, /*On fail goto*//*Label 962*/ 35163, // Rule ID 692 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/Mips::MSA128WRegClassID,
+ // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FMADD_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 692,
+ GIR_Done,
+ // Label 962: @35163
+ GIM_Reject,
+ // Label 960: @35164
+ GIM_Reject,
+ // Label 28: @35165
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 967*/ 35415,
+ /*GILLT_s32*//*Label 963*/ 35177,
+ /*GILLT_s64*//*Label 964*/ 35247, 0,
+ /*GILLT_v2s64*//*Label 965*/ 35351, 0,
+ /*GILLT_v4s32*//*Label 966*/ 35383,
+ // Label 963: @35177
+ GIM_Try, /*On fail goto*//*Label 968*/ 35246,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 969*/ 35210, // Rule ID 136 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
+ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 136,
+ GIR_Done,
+ // Label 969: @35210
+ GIM_Try, /*On fail goto*//*Label 970*/ 35221, // Rule ID 1090 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
+ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_S_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1090,
+ GIR_Done,
+ // Label 970: @35221
+ GIM_Try, /*On fail goto*//*Label 971*/ 35245, // Rule ID 1148 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
+ // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft) => (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::FDIV_S_MMR6,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ft
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // fs
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1148,
+ GIR_Done,
+ // Label 971: @35245
+ GIM_Reject,
+ // Label 968: @35246
+ GIM_Reject,
+ // Label 964: @35247
+ GIM_Try, /*On fail goto*//*Label 972*/ 35350,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 973*/ 35280, // Rule ID 137 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 137,
+ GIR_Done,
+ // Label 973: @35280
+ GIM_Try, /*On fail goto*//*Label 974*/ 35303, // Rule ID 138 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 138,
+ GIR_Done,
+ // Label 974: @35303
+ GIM_Try, /*On fail goto*//*Label 975*/ 35326, // Rule ID 1095 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D32_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1095,
+ GIR_Done,
+ // Label 975: @35326
+ GIM_Try, /*On fail goto*//*Label 976*/ 35349, // Rule ID 1096 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft) => (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D64_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1096,
+ GIR_Done,
+ // Label 976: @35349
+ GIM_Reject,
+ // Label 972: @35350
+ GIM_Reject,
+ // Label 965: @35351
+ GIM_Try, /*On fail goto*//*Label 977*/ 35382, // Rule ID 665 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
+ // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt) => (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 665,
+ GIR_Done,
+ // Label 977: @35382
+ GIM_Reject,
+ // Label 966: @35383
+ GIM_Try, /*On fail goto*//*Label 978*/ 35414, // Rule ID 664 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
+ // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) => (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FDIV_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 664,
+ GIR_Done,
+ // Label 978: @35414
+ GIM_Reject,
+ // Label 967: @35415
+ GIM_Reject,
+ // Label 29: @35416
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 981*/ 35473,
+ /*GILLT_v2s64*//*Label 979*/ 35425, 0,
+ /*GILLT_v4s32*//*Label 980*/ 35449,
+ // Label 979: @35425
+ GIM_Try, /*On fail goto*//*Label 982*/ 35448, // Rule ID 671 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws) => (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_D_1_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 671,
+ GIR_Done,
+ // Label 982: @35448
+ GIM_Reject,
+ // Label 980: @35449
+ GIM_Try, /*On fail goto*//*Label 983*/ 35472, // Rule ID 670 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws) => (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FEXP2_W_1_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 670,
+ GIR_Done,
+ // Label 983: @35472
+ GIM_Reject,
+ // Label 981: @35473
+ GIM_Reject,
+ // Label 30: @35474
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 986*/ 35531,
+ /*GILLT_v2s64*//*Label 984*/ 35483, 0,
+ /*GILLT_v4s32*//*Label 985*/ 35507,
+ // Label 984: @35483
+ GIM_Try, /*On fail goto*//*Label 987*/ 35506, // Rule ID 691 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 691,
+ GIR_Done,
+ // Label 987: @35506
+ GIM_Reject,
+ // Label 985: @35507
+ GIM_Try, /*On fail goto*//*Label 988*/ 35530, // Rule ID 690 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FLOG2_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 690,
+ GIR_Done,
+ // Label 988: @35530
+ GIM_Reject,
+ // Label 986: @35531
+ GIM_Reject,
+ // Label 31: @35532
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 991*/ 36827,
+ /*GILLT_s32*//*Label 989*/ 35540,
+ /*GILLT_s64*//*Label 990*/ 36041,
+ // Label 989: @35540
+ GIM_Try, /*On fail goto*//*Label 992*/ 36040,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 993*/ 35624, // Rule ID 1414 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1414,
+ GIR_Done,
+ // Label 993: @35624
+ GIM_Try, /*On fail goto*//*Label 994*/ 35698, // Rule ID 2144 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2144,
+ GIR_Done,
+ // Label 994: @35698
+ GIM_Try, /*On fail goto*//*Label 995*/ 35772, // Rule ID 2323 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2323,
+ GIR_Done,
+ // Label 995: @35772
+ GIM_Try, /*On fail goto*//*Label 996*/ 35846, // Rule ID 2420 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))) => (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_S_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2420,
+ GIR_Done,
+ // Label 996: @35846
+ GIM_Try, /*On fail goto*//*Label 997*/ 35920, // Rule ID 1415 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1415,
+ GIR_Done,
+ // Label 997: @35920
+ GIM_Try, /*On fail goto*//*Label 998*/ 35994, // Rule ID 2145 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)) => (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_S_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2145,
+ GIR_Done,
+ // Label 998: @35994
+ GIM_Try, /*On fail goto*//*Label 999*/ 36009, // Rule ID 111 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 111,
+ GIR_Done,
+ // Label 999: @36009
+ GIM_Try, /*On fail goto*//*Label 1000*/ 36024, // Rule ID 1112 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1112,
+ GIR_Done,
+ // Label 1000: @36024
+ GIM_Try, /*On fail goto*//*Label 1001*/ 36039, // Rule ID 1149 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs) => (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_S_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1149,
+ GIR_Done,
+ // Label 1001: @36039
+ GIM_Reject,
+ // Label 992: @36040
+ GIM_Reject,
+ // Label 990: @36041
+ GIM_Try, /*On fail goto*//*Label 1002*/ 36826,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 1003*/ 36125, // Rule ID 1416 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1416,
+ GIR_Done,
+ // Label 1003: @36125
+ GIM_Try, /*On fail goto*//*Label 1004*/ 36203, // Rule ID 1418 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1418,
+ GIR_Done,
+ // Label 1004: @36203
+ GIM_Try, /*On fail goto*//*Label 1005*/ 36281, // Rule ID 2146 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2146,
+ GIR_Done,
+ // Label 1005: @36281
+ GIM_Try, /*On fail goto*//*Label 1006*/ 36359, // Rule ID 2324 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2324,
+ GIR_Done,
+ // Label 1006: @36359
+ GIM_Try, /*On fail goto*//*Label 1007*/ 36437, // Rule ID 2325 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2325,
+ GIR_Done,
+ // Label 1007: @36437
+ GIM_Try, /*On fail goto*//*Label 1008*/ 36515, // Rule ID 2421 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))) => (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMADD_D32_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2421,
+ GIR_Done,
+ // Label 1008: @36515
+ GIM_Try, /*On fail goto*//*Label 1009*/ 36593, // Rule ID 1417 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1417,
+ GIR_Done,
+ // Label 1009: @36593
+ GIM_Try, /*On fail goto*//*Label 1010*/ 36671, // Rule ID 1419 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D64,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1419,
+ GIR_Done,
+ // Label 1010: @36671
+ GIM_Try, /*On fail goto*//*Label 1011*/ 36749, // Rule ID 2147 //
+ GIM_CheckFeatures, GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FSUB,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FMUL,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)) => (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NMSUB_D32_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // fd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2147,
+ GIR_Done,
+ // Label 1011: @36749
+ GIM_Try, /*On fail goto*//*Label 1012*/ 36768, // Rule ID 112 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 112,
+ GIR_Done,
+ // Label 1012: @36768
+ GIM_Try, /*On fail goto*//*Label 1013*/ 36787, // Rule ID 113 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 113,
+ GIR_Done,
+ // Label 1013: @36787
+ GIM_Try, /*On fail goto*//*Label 1014*/ 36806, // Rule ID 1113 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D32_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1113,
+ GIR_Done,
+ // Label 1014: @36806
+ GIM_Try, /*On fail goto*//*Label 1015*/ 36825, // Rule ID 1114 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs) => (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FNEG_D64_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1114,
+ GIR_Done,
+ // Label 1015: @36825
+ GIM_Reject,
+ // Label 1002: @36826
+ GIM_Reject,
+ // Label 991: @36827
+ GIM_Reject,
+ // Label 32: @36828
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1018*/ 36976,
+ /*GILLT_s32*//*Label 1016*/ 36836,
+ /*GILLT_s64*//*Label 1017*/ 36860,
+ // Label 1016: @36836
+ GIM_Try, /*On fail goto*//*Label 1019*/ 36859, // Rule ID 1024 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID,
+ // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_W_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1024,
+ GIR_Done,
+ // Label 1019: @36859
+ GIM_Reject,
+ // Label 1017: @36860
+ GIM_Try, /*On fail goto*//*Label 1020*/ 36883, // Rule ID 1026 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128F16RegClassID,
+ // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws) => (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_EXTEND_D_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1026,
+ GIR_Done,
+ // Label 1020: @36883
+ GIM_Try, /*On fail goto*//*Label 1021*/ 36906, // Rule ID 1403 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1403,
+ GIR_Done,
+ // Label 1021: @36906
+ GIM_Try, /*On fail goto*//*Label 1022*/ 36929, // Rule ID 1413 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1413,
+ GIR_Done,
+ // Label 1022: @36929
+ GIM_Try, /*On fail goto*//*Label 1023*/ 36952, // Rule ID 2155 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D64_S_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2155,
+ GIR_Done,
+ // Label 1023: @36952
+ GIM_Try, /*On fail goto*//*Label 1024*/ 36975, // Rule ID 2157 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src) => (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_D32_S_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2157,
+ GIR_Done,
+ // Label 1024: @36975
+ GIM_Reject,
+ // Label 1018: @36976
+ GIM_Reject,
+ // Label 33: @36977
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 1027*/ 37104,
+ /*GILLT_s16*//*Label 1025*/ 36985,
+ /*GILLT_s32*//*Label 1026*/ 37032,
+ // Label 1025: @36985
+ GIM_Try, /*On fail goto*//*Label 1028*/ 37008, // Rule ID 1025 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR32RegClassID,
+ // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_W_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1025,
+ GIR_Done,
+ // Label 1028: @37008
+ GIM_Try, /*On fail goto*//*Label 1029*/ 37031, // Rule ID 1027 //
+ GIM_CheckFeatures, GIFBS_HasMSA,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128F16RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MSA_FP_ROUND_D_PSEUDO,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1027,
+ GIR_Done,
+ // Label 1029: @37031
+ GIM_Reject,
+ // Label 1026: @37032
+ GIM_Try, /*On fail goto*//*Label 1030*/ 37103,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 1031*/ 37057, // Rule ID 1402 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1402,
+ GIR_Done,
+ // Label 1031: @37057
+ GIM_Try, /*On fail goto*//*Label 1032*/ 37072, // Rule ID 1412 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1412,
+ GIR_Done,
+ // Label 1032: @37072
+ GIM_Try, /*On fail goto*//*Label 1033*/ 37087, // Rule ID 2154 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_IsFP64bit,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::FGR64RegClassID,
+ // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D64_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2154,
+ GIR_Done,
+ // Label 1033: @37087
+ GIM_Try, /*On fail goto*//*Label 1034*/ 37102, // Rule ID 2156 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotFP64bit,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::AFGR64RegClassID,
+ // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::CVT_S_D32_MM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2156,
+ GIR_Done,
+ // Label 1034: @37102
+ GIM_Reject,
+ // Label 1030: @37103
+ GIM_Reject,
+ // Label 1027: @37104
+ GIM_Reject,
+ // Label 34: @37105
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1037*/ 37162,
+ /*GILLT_v2s64*//*Label 1035*/ 37114, 0,
+ /*GILLT_v4s32*//*Label 1036*/ 37138,
+ // Label 1035: @37114
+ GIM_Try, /*On fail goto*//*Label 1038*/ 37137, // Rule ID 745 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 745,
+ GIR_Done,
+ // Label 1038: @37137
+ GIM_Reject,
+ // Label 1036: @37138
+ GIM_Try, /*On fail goto*//*Label 1039*/ 37161, // Rule ID 744 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_S_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 744,
+ GIR_Done,
+ // Label 1039: @37161
+ GIM_Reject,
+ // Label 1037: @37162
+ GIM_Reject,
+ // Label 35: @37163
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1042*/ 37220,
+ /*GILLT_v2s64*//*Label 1040*/ 37172, 0,
+ /*GILLT_v4s32*//*Label 1041*/ 37196,
+ // Label 1040: @37172
+ GIM_Try, /*On fail goto*//*Label 1043*/ 37195, // Rule ID 747 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws) => (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 747,
+ GIR_Done,
+ // Label 1043: @37195
+ GIM_Reject,
+ // Label 1041: @37196
+ GIM_Try, /*On fail goto*//*Label 1044*/ 37219, // Rule ID 746 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws) => (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FTRUNC_U_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 746,
+ GIR_Done,
+ // Label 1044: @37219
+ GIM_Reject,
+ // Label 1042: @37220
+ GIM_Reject,
+ // Label 36: @37221
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 7, /*)*//*default:*//*Label 1049*/ 37373,
+ /*GILLT_s32*//*Label 1045*/ 37233,
+ /*GILLT_s64*//*Label 1046*/ 37255, 0,
+ /*GILLT_v2s64*//*Label 1047*/ 37325, 0,
+ /*GILLT_v4s32*//*Label 1048*/ 37349,
+ // Label 1045: @37233
+ GIM_Try, /*On fail goto*//*Label 1050*/ 37254, // Rule ID 1397 //
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_S_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1397,
+ GIR_Done,
+ // Label 1050: @37254
+ GIM_Reject,
+ // Label 1046: @37255
+ GIM_Try, /*On fail goto*//*Label 1051*/ 37278, // Rule ID 1400 //
+ GIM_CheckFeatures, GIFBS_NotFP64bit,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::AFGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D32_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1400,
+ GIR_Done,
+ // Label 1051: @37278
+ GIM_Try, /*On fail goto*//*Label 1052*/ 37301, // Rule ID 1406 //
+ GIM_CheckFeatures, GIFBS_IsFP64bit,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src) => (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1406,
+ GIR_Done,
+ // Label 1052: @37301
+ GIM_Try, /*On fail goto*//*Label 1053*/ 37324, // Rule ID 1408 //
+ GIM_CheckFeatures, GIFBS_IsFP64bit,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::FGR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src) => (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::PseudoCVT_D64_L,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1408,
+ GIR_Done,
+ // Label 1053: @37324
+ GIM_Reject,
+ // Label 1047: @37325
+ GIM_Try, /*On fail goto*//*Label 1054*/ 37348, // Rule ID 677 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 677,
+ GIR_Done,
+ // Label 1054: @37348
+ GIM_Reject,
+ // Label 1048: @37349
+ GIM_Try, /*On fail goto*//*Label 1055*/ 37372, // Rule ID 676 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_S_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 676,
+ GIR_Done,
+ // Label 1055: @37372
+ GIM_Reject,
+ // Label 1049: @37373
+ GIM_Reject,
+ // Label 37: @37374
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/4, 7, /*)*//*default:*//*Label 1058*/ 37431,
+ /*GILLT_v2s64*//*Label 1056*/ 37383, 0,
+ /*GILLT_v4s32*//*Label 1057*/ 37407,
+ // Label 1056: @37383
+ GIM_Try, /*On fail goto*//*Label 1059*/ 37406, // Rule ID 679 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
+ // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws) => (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 679,
+ GIR_Done,
+ // Label 1059: @37406
+ GIM_Reject,
+ // Label 1057: @37407
+ GIM_Try, /*On fail goto*//*Label 1060*/ 37430, // Rule ID 678 //
+ GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
+ // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws) => (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::FFINT_U_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 678,
+ GIR_Done,
+ // Label 1060: @37430
+ GIM_Reject,
+ // Label 1058: @37431
+ GIM_Reject,
+ // Label 38: @37432
+ GIM_Try, /*On fail goto*//*Label 1061*/ 37516,
+ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
+ GIM_Try, /*On fail goto*//*Label 1062*/ 37451, // Rule ID 73 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
+ // (br (bb:{ *:[Other] }):$target) => (J (bb:{ *:[Other] }):$target)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 73,
+ GIR_Done,
+ // Label 1062: @37451
+ GIM_Try, /*On fail goto*//*Label 1063*/ 37465, // Rule ID 80 //
+ GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
+ // (br (bb:{ *:[Other] }):$offset) => (B (bb:{ *:[Other] }):$offset)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 80,
+ GIR_Done,
+ // Label 1063: @37465
+ GIM_Try, /*On fail goto*//*Label 1064*/ 37479, // Rule ID 1072 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
+ // (br (bb:{ *:[Other] }):$target) => (J_MM (bb:{ *:[Other] }):$target)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::J_MM,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1072,
+ GIR_Done,
+ // Label 1064: @37479
+ GIM_Try, /*On fail goto*//*Label 1065*/ 37493, // Rule ID 1081 //
+ GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6_RelocPIC,
+ // (br (bb:{ *:[Other] }):$offset) => (B_MM (bb:{ *:[Other] }):$offset)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::B_MM,
+ GIR_AddImplicitDef, /*InsnID*/0, Mips::AT,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1081,
+ GIR_Done,
+ // Label 1065: @37493
+ GIM_Try, /*On fail goto*//*Label 1066*/ 37504, // Rule ID 1128 //
+ GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
+ // (br (bb:{ *:[Other] }):$offset) => (BC_MMR6 (bb:{ *:[Other] }):$offset)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::BC_MMR6,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1128,
+ GIR_Done,
+ // Label 1066: @37504
+ GIM_Try, /*On fail goto*//*Label 1067*/ 37515, // Rule ID 1775 //
+ GIM_CheckFeatures, GIFBS_InMips16Mode,
+ // (br (bb:{ *:[Other] }):$imm16) => (Bimm16 (bb:{ *:[Other] }):$imm16)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::Bimm16,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1775,
+ GIR_Done,
+ // Label 1067: @37515
+ GIM_Reject,
+ // Label 1061: @37516
+ GIM_Reject,
+ // Label 39: @37517
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 3, /*)*//*default:*//*Label 1070*/ 37668,
+ /*GILLT_s32*//*Label 1068*/ 37525,
+ /*GILLT_s64*//*Label 1069*/ 37619,
+ // Label 1068: @37525
+ GIM_Try, /*On fail goto*//*Label 1071*/ 37618,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 1072*/ 37578, // Rule ID 1383 //
+ GIM_CheckFeatures, GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
+ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/16,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1383,
+ GIR_Done,
+ // Label 1072: @37578
+ GIM_Try, /*On fail goto*//*Label 1073*/ 37617, // Rule ID 2088 //
+ GIM_CheckFeatures, GIFBS_InMicroMips,
+ // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt) => (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::WSBH_MM,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ROTR_MM,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/16,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 2088,
+ GIR_Done,
+ // Label 1073: @37617
+ GIM_Reject,
+ // Label 1071: @37618
+ GIM_Reject,
+ // Label 1069: @37619
+ GIM_Try, /*On fail goto*//*Label 1074*/ 37667, // Rule ID 1525 //
+ GIM_CheckFeatures, GIFBS_HasMips64r2_HasStdEnc,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
+ // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt) => (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/Mips::DSBH,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DSHD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1525,
+ GIR_Done,
+ // Label 1074: @37667
+ GIM_Reject,
+ // Label 1070: @37668
+ GIM_Reject,
+ // Label 40: @37669
+ GIM_Reject,
+ };
+ return MatchTable0;
+}
+#endif // ifdef GET_GLOBALISEL_IMPL
+#ifdef GET_GLOBALISEL_PREDICATES_DECL
+PredicateBitset AvailableModuleFeatures;
+mutable PredicateBitset AvailableFunctionFeatures;
+PredicateBitset getAvailableFeatures() const {
+ return AvailableModuleFeatures | AvailableFunctionFeatures;
+}
+PredicateBitset
+computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
+PredicateBitset
+computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
+ const MachineFunction *MF) const;
+#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
+#ifdef GET_GLOBALISEL_PREDICATES_INIT
+AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
+AvailableFunctionFeatures()
+#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenInstrInfo.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenInstrInfo.inc
new file mode 100644
index 0000000..777c047
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenInstrInfo.inc
@@ -0,0 +1,10389 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Instruction Enum Values and Descriptors *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+namespace llvm {
+
+namespace Mips {
+ enum {
+ PHI = 0,
+ INLINEASM = 1,
+ CFI_INSTRUCTION = 2,
+ EH_LABEL = 3,
+ GC_LABEL = 4,
+ ANNOTATION_LABEL = 5,
+ KILL = 6,
+ EXTRACT_SUBREG = 7,
+ INSERT_SUBREG = 8,
+ IMPLICIT_DEF = 9,
+ SUBREG_TO_REG = 10,
+ COPY_TO_REGCLASS = 11,
+ DBG_VALUE = 12,
+ DBG_LABEL = 13,
+ REG_SEQUENCE = 14,
+ COPY = 15,
+ BUNDLE = 16,
+ LIFETIME_START = 17,
+ LIFETIME_END = 18,
+ STACKMAP = 19,
+ FENTRY_CALL = 20,
+ PATCHPOINT = 21,
+ LOAD_STACK_GUARD = 22,
+ STATEPOINT = 23,
+ LOCAL_ESCAPE = 24,
+ FAULTING_OP = 25,
+ PATCHABLE_OP = 26,
+ PATCHABLE_FUNCTION_ENTER = 27,
+ PATCHABLE_RET = 28,
+ PATCHABLE_FUNCTION_EXIT = 29,
+ PATCHABLE_TAIL_CALL = 30,
+ PATCHABLE_EVENT_CALL = 31,
+ PATCHABLE_TYPED_EVENT_CALL = 32,
+ ICALL_BRANCH_FUNNEL = 33,
+ G_ADD = 34,
+ G_SUB = 35,
+ G_MUL = 36,
+ G_SDIV = 37,
+ G_UDIV = 38,
+ G_SREM = 39,
+ G_UREM = 40,
+ G_AND = 41,
+ G_OR = 42,
+ G_XOR = 43,
+ G_IMPLICIT_DEF = 44,
+ G_PHI = 45,
+ G_FRAME_INDEX = 46,
+ G_GLOBAL_VALUE = 47,
+ G_EXTRACT = 48,
+ G_UNMERGE_VALUES = 49,
+ G_INSERT = 50,
+ G_MERGE_VALUES = 51,
+ G_PTRTOINT = 52,
+ G_INTTOPTR = 53,
+ G_BITCAST = 54,
+ G_LOAD = 55,
+ G_SEXTLOAD = 56,
+ G_ZEXTLOAD = 57,
+ G_STORE = 58,
+ G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59,
+ G_ATOMIC_CMPXCHG = 60,
+ G_ATOMICRMW_XCHG = 61,
+ G_ATOMICRMW_ADD = 62,
+ G_ATOMICRMW_SUB = 63,
+ G_ATOMICRMW_AND = 64,
+ G_ATOMICRMW_NAND = 65,
+ G_ATOMICRMW_OR = 66,
+ G_ATOMICRMW_XOR = 67,
+ G_ATOMICRMW_MAX = 68,
+ G_ATOMICRMW_MIN = 69,
+ G_ATOMICRMW_UMAX = 70,
+ G_ATOMICRMW_UMIN = 71,
+ G_BRCOND = 72,
+ G_BRINDIRECT = 73,
+ G_INTRINSIC = 74,
+ G_INTRINSIC_W_SIDE_EFFECTS = 75,
+ G_ANYEXT = 76,
+ G_TRUNC = 77,
+ G_CONSTANT = 78,
+ G_FCONSTANT = 79,
+ G_VASTART = 80,
+ G_VAARG = 81,
+ G_SEXT = 82,
+ G_ZEXT = 83,
+ G_SHL = 84,
+ G_LSHR = 85,
+ G_ASHR = 86,
+ G_ICMP = 87,
+ G_FCMP = 88,
+ G_SELECT = 89,
+ G_UADDE = 90,
+ G_USUBE = 91,
+ G_SADDO = 92,
+ G_SSUBO = 93,
+ G_UMULO = 94,
+ G_SMULO = 95,
+ G_UMULH = 96,
+ G_SMULH = 97,
+ G_FADD = 98,
+ G_FSUB = 99,
+ G_FMUL = 100,
+ G_FMA = 101,
+ G_FDIV = 102,
+ G_FREM = 103,
+ G_FPOW = 104,
+ G_FEXP = 105,
+ G_FEXP2 = 106,
+ G_FLOG = 107,
+ G_FLOG2 = 108,
+ G_FNEG = 109,
+ G_FPEXT = 110,
+ G_FPTRUNC = 111,
+ G_FPTOSI = 112,
+ G_FPTOUI = 113,
+ G_SITOFP = 114,
+ G_UITOFP = 115,
+ G_FABS = 116,
+ G_GEP = 117,
+ G_PTR_MASK = 118,
+ G_BR = 119,
+ G_INSERT_VECTOR_ELT = 120,
+ G_EXTRACT_VECTOR_ELT = 121,
+ G_SHUFFLE_VECTOR = 122,
+ G_BSWAP = 123,
+ G_ADDRSPACE_CAST = 124,
+ G_BLOCK_ADDR = 125,
+ ABSMacro = 126,
+ ADJCALLSTACKDOWN = 127,
+ ADJCALLSTACKUP = 128,
+ AND_V_D_PSEUDO = 129,
+ AND_V_H_PSEUDO = 130,
+ AND_V_W_PSEUDO = 131,
+ ATOMIC_CMP_SWAP_I16 = 132,
+ ATOMIC_CMP_SWAP_I16_POSTRA = 133,
+ ATOMIC_CMP_SWAP_I32 = 134,
+ ATOMIC_CMP_SWAP_I32_POSTRA = 135,
+ ATOMIC_CMP_SWAP_I64 = 136,
+ ATOMIC_CMP_SWAP_I64_POSTRA = 137,
+ ATOMIC_CMP_SWAP_I8 = 138,
+ ATOMIC_CMP_SWAP_I8_POSTRA = 139,
+ ATOMIC_LOAD_ADD_I16 = 140,
+ ATOMIC_LOAD_ADD_I16_POSTRA = 141,
+ ATOMIC_LOAD_ADD_I32 = 142,
+ ATOMIC_LOAD_ADD_I32_POSTRA = 143,
+ ATOMIC_LOAD_ADD_I64 = 144,
+ ATOMIC_LOAD_ADD_I64_POSTRA = 145,
+ ATOMIC_LOAD_ADD_I8 = 146,
+ ATOMIC_LOAD_ADD_I8_POSTRA = 147,
+ ATOMIC_LOAD_AND_I16 = 148,
+ ATOMIC_LOAD_AND_I16_POSTRA = 149,
+ ATOMIC_LOAD_AND_I32 = 150,
+ ATOMIC_LOAD_AND_I32_POSTRA = 151,
+ ATOMIC_LOAD_AND_I64 = 152,
+ ATOMIC_LOAD_AND_I64_POSTRA = 153,
+ ATOMIC_LOAD_AND_I8 = 154,
+ ATOMIC_LOAD_AND_I8_POSTRA = 155,
+ ATOMIC_LOAD_NAND_I16 = 156,
+ ATOMIC_LOAD_NAND_I16_POSTRA = 157,
+ ATOMIC_LOAD_NAND_I32 = 158,
+ ATOMIC_LOAD_NAND_I32_POSTRA = 159,
+ ATOMIC_LOAD_NAND_I64 = 160,
+ ATOMIC_LOAD_NAND_I64_POSTRA = 161,
+ ATOMIC_LOAD_NAND_I8 = 162,
+ ATOMIC_LOAD_NAND_I8_POSTRA = 163,
+ ATOMIC_LOAD_OR_I16 = 164,
+ ATOMIC_LOAD_OR_I16_POSTRA = 165,
+ ATOMIC_LOAD_OR_I32 = 166,
+ ATOMIC_LOAD_OR_I32_POSTRA = 167,
+ ATOMIC_LOAD_OR_I64 = 168,
+ ATOMIC_LOAD_OR_I64_POSTRA = 169,
+ ATOMIC_LOAD_OR_I8 = 170,
+ ATOMIC_LOAD_OR_I8_POSTRA = 171,
+ ATOMIC_LOAD_SUB_I16 = 172,
+ ATOMIC_LOAD_SUB_I16_POSTRA = 173,
+ ATOMIC_LOAD_SUB_I32 = 174,
+ ATOMIC_LOAD_SUB_I32_POSTRA = 175,
+ ATOMIC_LOAD_SUB_I64 = 176,
+ ATOMIC_LOAD_SUB_I64_POSTRA = 177,
+ ATOMIC_LOAD_SUB_I8 = 178,
+ ATOMIC_LOAD_SUB_I8_POSTRA = 179,
+ ATOMIC_LOAD_XOR_I16 = 180,
+ ATOMIC_LOAD_XOR_I16_POSTRA = 181,
+ ATOMIC_LOAD_XOR_I32 = 182,
+ ATOMIC_LOAD_XOR_I32_POSTRA = 183,
+ ATOMIC_LOAD_XOR_I64 = 184,
+ ATOMIC_LOAD_XOR_I64_POSTRA = 185,
+ ATOMIC_LOAD_XOR_I8 = 186,
+ ATOMIC_LOAD_XOR_I8_POSTRA = 187,
+ ATOMIC_SWAP_I16 = 188,
+ ATOMIC_SWAP_I16_POSTRA = 189,
+ ATOMIC_SWAP_I32 = 190,
+ ATOMIC_SWAP_I32_POSTRA = 191,
+ ATOMIC_SWAP_I64 = 192,
+ ATOMIC_SWAP_I64_POSTRA = 193,
+ ATOMIC_SWAP_I8 = 194,
+ ATOMIC_SWAP_I8_POSTRA = 195,
+ B = 196,
+ BAL_BR = 197,
+ BAL_BR_MM = 198,
+ BEQLImmMacro = 199,
+ BGE = 200,
+ BGEImmMacro = 201,
+ BGEL = 202,
+ BGELImmMacro = 203,
+ BGEU = 204,
+ BGEUImmMacro = 205,
+ BGEUL = 206,
+ BGEULImmMacro = 207,
+ BGT = 208,
+ BGTImmMacro = 209,
+ BGTL = 210,
+ BGTLImmMacro = 211,
+ BGTU = 212,
+ BGTUImmMacro = 213,
+ BGTUL = 214,
+ BGTULImmMacro = 215,
+ BLE = 216,
+ BLEImmMacro = 217,
+ BLEL = 218,
+ BLELImmMacro = 219,
+ BLEU = 220,
+ BLEUImmMacro = 221,
+ BLEUL = 222,
+ BLEULImmMacro = 223,
+ BLT = 224,
+ BLTImmMacro = 225,
+ BLTL = 226,
+ BLTLImmMacro = 227,
+ BLTU = 228,
+ BLTUImmMacro = 229,
+ BLTUL = 230,
+ BLTULImmMacro = 231,
+ BNELImmMacro = 232,
+ BPOSGE32_PSEUDO = 233,
+ BSEL_D_PSEUDO = 234,
+ BSEL_FD_PSEUDO = 235,
+ BSEL_FW_PSEUDO = 236,
+ BSEL_H_PSEUDO = 237,
+ BSEL_W_PSEUDO = 238,
+ B_MM = 239,
+ B_MMR6_Pseudo = 240,
+ B_MM_Pseudo = 241,
+ BeqImm = 242,
+ BneImm = 243,
+ BteqzT8CmpX16 = 244,
+ BteqzT8CmpiX16 = 245,
+ BteqzT8SltX16 = 246,
+ BteqzT8SltiX16 = 247,
+ BteqzT8SltiuX16 = 248,
+ BteqzT8SltuX16 = 249,
+ BtnezT8CmpX16 = 250,
+ BtnezT8CmpiX16 = 251,
+ BtnezT8SltX16 = 252,
+ BtnezT8SltiX16 = 253,
+ BtnezT8SltiuX16 = 254,
+ BtnezT8SltuX16 = 255,
+ BuildPairF64 = 256,
+ BuildPairF64_64 = 257,
+ CFTC1 = 258,
+ CONSTPOOL_ENTRY = 259,
+ COPY_FD_PSEUDO = 260,
+ COPY_FW_PSEUDO = 261,
+ CTTC1 = 262,
+ Constant32 = 263,
+ DMULImmMacro = 264,
+ DMULMacro = 265,
+ DMULOMacro = 266,
+ DMULOUMacro = 267,
+ DROL = 268,
+ DROLImm = 269,
+ DROR = 270,
+ DRORImm = 271,
+ DSDivIMacro = 272,
+ DSDivMacro = 273,
+ DSRemIMacro = 274,
+ DSRemMacro = 275,
+ DUDivIMacro = 276,
+ DUDivMacro = 277,
+ DURemIMacro = 278,
+ DURemMacro = 279,
+ ERet = 280,
+ ExtractElementF64 = 281,
+ ExtractElementF64_64 = 282,
+ FABS_D = 283,
+ FABS_W = 284,
+ FEXP2_D_1_PSEUDO = 285,
+ FEXP2_W_1_PSEUDO = 286,
+ FILL_FD_PSEUDO = 287,
+ FILL_FW_PSEUDO = 288,
+ GotPrologue16 = 289,
+ INSERT_B_VIDX64_PSEUDO = 290,
+ INSERT_B_VIDX_PSEUDO = 291,
+ INSERT_D_VIDX64_PSEUDO = 292,
+ INSERT_D_VIDX_PSEUDO = 293,
+ INSERT_FD_PSEUDO = 294,
+ INSERT_FD_VIDX64_PSEUDO = 295,
+ INSERT_FD_VIDX_PSEUDO = 296,
+ INSERT_FW_PSEUDO = 297,
+ INSERT_FW_VIDX64_PSEUDO = 298,
+ INSERT_FW_VIDX_PSEUDO = 299,
+ INSERT_H_VIDX64_PSEUDO = 300,
+ INSERT_H_VIDX_PSEUDO = 301,
+ INSERT_W_VIDX64_PSEUDO = 302,
+ INSERT_W_VIDX_PSEUDO = 303,
+ JALR64Pseudo = 304,
+ JALRHB64Pseudo = 305,
+ JALRHBPseudo = 306,
+ JALRPseudo = 307,
+ JalOneReg = 308,
+ JalTwoReg = 309,
+ LDMacro = 310,
+ LD_F16 = 311,
+ LOAD_ACC128 = 312,
+ LOAD_ACC64 = 313,
+ LOAD_ACC64DSP = 314,
+ LOAD_CCOND_DSP = 315,
+ LONG_BRANCH_ADDiu = 316,
+ LONG_BRANCH_DADDiu = 317,
+ LONG_BRANCH_LUi = 318,
+ LWM_MM = 319,
+ LoadAddrImm32 = 320,
+ LoadAddrImm64 = 321,
+ LoadAddrReg32 = 322,
+ LoadAddrReg64 = 323,
+ LoadImm32 = 324,
+ LoadImm64 = 325,
+ LoadImmDoubleFGR = 326,
+ LoadImmDoubleFGR_32 = 327,
+ LoadImmDoubleGPR = 328,
+ LoadImmSingleFGR = 329,
+ LoadImmSingleGPR = 330,
+ LwConstant32 = 331,
+ MFTACX = 332,
+ MFTC0 = 333,
+ MFTC1 = 334,
+ MFTDSP = 335,
+ MFTGPR = 336,
+ MFTHC1 = 337,
+ MFTHI = 338,
+ MFTLO = 339,
+ MIPSeh_return32 = 340,
+ MIPSeh_return64 = 341,
+ MSA_FP_EXTEND_D_PSEUDO = 342,
+ MSA_FP_EXTEND_W_PSEUDO = 343,
+ MSA_FP_ROUND_D_PSEUDO = 344,
+ MSA_FP_ROUND_W_PSEUDO = 345,
+ MTTACX = 346,
+ MTTC0 = 347,
+ MTTC1 = 348,
+ MTTDSP = 349,
+ MTTGPR = 350,
+ MTTHC1 = 351,
+ MTTHI = 352,
+ MTTLO = 353,
+ MULImmMacro = 354,
+ MULOMacro = 355,
+ MULOUMacro = 356,
+ MultRxRy16 = 357,
+ MultRxRyRz16 = 358,
+ MultuRxRy16 = 359,
+ MultuRxRyRz16 = 360,
+ NOP = 361,
+ NORImm = 362,
+ NORImm64 = 363,
+ NOR_V_D_PSEUDO = 364,
+ NOR_V_H_PSEUDO = 365,
+ NOR_V_W_PSEUDO = 366,
+ OR_V_D_PSEUDO = 367,
+ OR_V_H_PSEUDO = 368,
+ OR_V_W_PSEUDO = 369,
+ PseudoCMPU_EQ_QB = 370,
+ PseudoCMPU_LE_QB = 371,
+ PseudoCMPU_LT_QB = 372,
+ PseudoCMP_EQ_PH = 373,
+ PseudoCMP_LE_PH = 374,
+ PseudoCMP_LT_PH = 375,
+ PseudoCVT_D32_W = 376,
+ PseudoCVT_D64_L = 377,
+ PseudoCVT_D64_W = 378,
+ PseudoCVT_S_L = 379,
+ PseudoCVT_S_W = 380,
+ PseudoDMULT = 381,
+ PseudoDMULTu = 382,
+ PseudoDSDIV = 383,
+ PseudoDUDIV = 384,
+ PseudoIndirectBranch = 385,
+ PseudoIndirectBranch64 = 386,
+ PseudoIndirectBranch64R6 = 387,
+ PseudoIndirectBranchR6 = 388,
+ PseudoIndirectBranch_MM = 389,
+ PseudoIndirectBranch_MMR6 = 390,
+ PseudoIndirectHazardBranch = 391,
+ PseudoIndirectHazardBranch64 = 392,
+ PseudoIndrectHazardBranch64R6 = 393,
+ PseudoIndrectHazardBranchR6 = 394,
+ PseudoMADD = 395,
+ PseudoMADDU = 396,
+ PseudoMFHI = 397,
+ PseudoMFHI64 = 398,
+ PseudoMFLO = 399,
+ PseudoMFLO64 = 400,
+ PseudoMSUB = 401,
+ PseudoMSUBU = 402,
+ PseudoMTLOHI = 403,
+ PseudoMTLOHI64 = 404,
+ PseudoMTLOHI_DSP = 405,
+ PseudoMULT = 406,
+ PseudoMULTu = 407,
+ PseudoPICK_PH = 408,
+ PseudoPICK_QB = 409,
+ PseudoReturn = 410,
+ PseudoReturn64 = 411,
+ PseudoSDIV = 412,
+ PseudoSELECTFP_F_D32 = 413,
+ PseudoSELECTFP_F_D64 = 414,
+ PseudoSELECTFP_F_I = 415,
+ PseudoSELECTFP_F_I64 = 416,
+ PseudoSELECTFP_F_S = 417,
+ PseudoSELECTFP_T_D32 = 418,
+ PseudoSELECTFP_T_D64 = 419,
+ PseudoSELECTFP_T_I = 420,
+ PseudoSELECTFP_T_I64 = 421,
+ PseudoSELECTFP_T_S = 422,
+ PseudoSELECT_D32 = 423,
+ PseudoSELECT_D64 = 424,
+ PseudoSELECT_I = 425,
+ PseudoSELECT_I64 = 426,
+ PseudoSELECT_S = 427,
+ PseudoTRUNC_W_D = 428,
+ PseudoTRUNC_W_D32 = 429,
+ PseudoTRUNC_W_S = 430,
+ PseudoUDIV = 431,
+ ROL = 432,
+ ROLImm = 433,
+ ROR = 434,
+ RORImm = 435,
+ RetRA = 436,
+ RetRA16 = 437,
+ SDIV_MM_Pseudo = 438,
+ SDMacro = 439,
+ SDivIMacro = 440,
+ SDivMacro = 441,
+ SEQIMacro = 442,
+ SEQMacro = 443,
+ SLTImm64 = 444,
+ SLTUImm64 = 445,
+ SNZ_B_PSEUDO = 446,
+ SNZ_D_PSEUDO = 447,
+ SNZ_H_PSEUDO = 448,
+ SNZ_V_PSEUDO = 449,
+ SNZ_W_PSEUDO = 450,
+ SRemIMacro = 451,
+ SRemMacro = 452,
+ STORE_ACC128 = 453,
+ STORE_ACC64 = 454,
+ STORE_ACC64DSP = 455,
+ STORE_CCOND_DSP = 456,
+ ST_F16 = 457,
+ SWM_MM = 458,
+ SZ_B_PSEUDO = 459,
+ SZ_D_PSEUDO = 460,
+ SZ_H_PSEUDO = 461,
+ SZ_V_PSEUDO = 462,
+ SZ_W_PSEUDO = 463,
+ SelBeqZ = 464,
+ SelBneZ = 465,
+ SelTBteqZCmp = 466,
+ SelTBteqZCmpi = 467,
+ SelTBteqZSlt = 468,
+ SelTBteqZSlti = 469,
+ SelTBteqZSltiu = 470,
+ SelTBteqZSltu = 471,
+ SelTBtneZCmp = 472,
+ SelTBtneZCmpi = 473,
+ SelTBtneZSlt = 474,
+ SelTBtneZSlti = 475,
+ SelTBtneZSltiu = 476,
+ SelTBtneZSltu = 477,
+ SltCCRxRy16 = 478,
+ SltiCCRxImmX16 = 479,
+ SltiuCCRxImmX16 = 480,
+ SltuCCRxRy16 = 481,
+ SltuRxRyRz16 = 482,
+ TAILCALL = 483,
+ TAILCALL64R6REG = 484,
+ TAILCALLHB64R6REG = 485,
+ TAILCALLHBR6REG = 486,
+ TAILCALLR6REG = 487,
+ TAILCALLREG = 488,
+ TAILCALLREG64 = 489,
+ TAILCALLREGHB = 490,
+ TAILCALLREGHB64 = 491,
+ TAILCALLREG_MM = 492,
+ TAILCALLREG_MMR6 = 493,
+ TAILCALL_MM = 494,
+ TAILCALL_MMR6 = 495,
+ TRAP = 496,
+ TRAP_MM = 497,
+ UDIV_MM_Pseudo = 498,
+ UDivIMacro = 499,
+ UDivMacro = 500,
+ URemIMacro = 501,
+ URemMacro = 502,
+ Ulh = 503,
+ Ulhu = 504,
+ Ulw = 505,
+ Ush = 506,
+ Usw = 507,
+ XOR_V_D_PSEUDO = 508,
+ XOR_V_H_PSEUDO = 509,
+ XOR_V_W_PSEUDO = 510,
+ ABSQ_S_PH = 511,
+ ABSQ_S_PH_MM = 512,
+ ABSQ_S_QB = 513,
+ ABSQ_S_QB_MMR2 = 514,
+ ABSQ_S_W = 515,
+ ABSQ_S_W_MM = 516,
+ ADD = 517,
+ ADDIUPC = 518,
+ ADDIUPC_MM = 519,
+ ADDIUPC_MMR6 = 520,
+ ADDIUR1SP_MM = 521,
+ ADDIUR2_MM = 522,
+ ADDIUS5_MM = 523,
+ ADDIUSP_MM = 524,
+ ADDIU_MMR6 = 525,
+ ADDQH_PH = 526,
+ ADDQH_PH_MMR2 = 527,
+ ADDQH_R_PH = 528,
+ ADDQH_R_PH_MMR2 = 529,
+ ADDQH_R_W = 530,
+ ADDQH_R_W_MMR2 = 531,
+ ADDQH_W = 532,
+ ADDQH_W_MMR2 = 533,
+ ADDQ_PH = 534,
+ ADDQ_PH_MM = 535,
+ ADDQ_S_PH = 536,
+ ADDQ_S_PH_MM = 537,
+ ADDQ_S_W = 538,
+ ADDQ_S_W_MM = 539,
+ ADDSC = 540,
+ ADDSC_MM = 541,
+ ADDS_A_B = 542,
+ ADDS_A_D = 543,
+ ADDS_A_H = 544,
+ ADDS_A_W = 545,
+ ADDS_S_B = 546,
+ ADDS_S_D = 547,
+ ADDS_S_H = 548,
+ ADDS_S_W = 549,
+ ADDS_U_B = 550,
+ ADDS_U_D = 551,
+ ADDS_U_H = 552,
+ ADDS_U_W = 553,
+ ADDU16_MM = 554,
+ ADDU16_MMR6 = 555,
+ ADDUH_QB = 556,
+ ADDUH_QB_MMR2 = 557,
+ ADDUH_R_QB = 558,
+ ADDUH_R_QB_MMR2 = 559,
+ ADDU_MMR6 = 560,
+ ADDU_PH = 561,
+ ADDU_PH_MMR2 = 562,
+ ADDU_QB = 563,
+ ADDU_QB_MM = 564,
+ ADDU_S_PH = 565,
+ ADDU_S_PH_MMR2 = 566,
+ ADDU_S_QB = 567,
+ ADDU_S_QB_MM = 568,
+ ADDVI_B = 569,
+ ADDVI_D = 570,
+ ADDVI_H = 571,
+ ADDVI_W = 572,
+ ADDV_B = 573,
+ ADDV_D = 574,
+ ADDV_H = 575,
+ ADDV_W = 576,
+ ADDWC = 577,
+ ADDWC_MM = 578,
+ ADD_A_B = 579,
+ ADD_A_D = 580,
+ ADD_A_H = 581,
+ ADD_A_W = 582,
+ ADD_MM = 583,
+ ADD_MMR6 = 584,
+ ADDi = 585,
+ ADDi_MM = 586,
+ ADDiu = 587,
+ ADDiu_MM = 588,
+ ADDu = 589,
+ ADDu_MM = 590,
+ ALIGN = 591,
+ ALIGN_MMR6 = 592,
+ ALUIPC = 593,
+ ALUIPC_MMR6 = 594,
+ AND = 595,
+ AND16_MM = 596,
+ AND16_MMR6 = 597,
+ AND64 = 598,
+ ANDI16_MM = 599,
+ ANDI16_MMR6 = 600,
+ ANDI_B = 601,
+ ANDI_MMR6 = 602,
+ AND_MM = 603,
+ AND_MMR6 = 604,
+ AND_V = 605,
+ ANDi = 606,
+ ANDi64 = 607,
+ ANDi_MM = 608,
+ APPEND = 609,
+ APPEND_MMR2 = 610,
+ ASUB_S_B = 611,
+ ASUB_S_D = 612,
+ ASUB_S_H = 613,
+ ASUB_S_W = 614,
+ ASUB_U_B = 615,
+ ASUB_U_D = 616,
+ ASUB_U_H = 617,
+ ASUB_U_W = 618,
+ AUI = 619,
+ AUIPC = 620,
+ AUIPC_MMR6 = 621,
+ AUI_MMR6 = 622,
+ AVER_S_B = 623,
+ AVER_S_D = 624,
+ AVER_S_H = 625,
+ AVER_S_W = 626,
+ AVER_U_B = 627,
+ AVER_U_D = 628,
+ AVER_U_H = 629,
+ AVER_U_W = 630,
+ AVE_S_B = 631,
+ AVE_S_D = 632,
+ AVE_S_H = 633,
+ AVE_S_W = 634,
+ AVE_U_B = 635,
+ AVE_U_D = 636,
+ AVE_U_H = 637,
+ AVE_U_W = 638,
+ AddiuRxImmX16 = 639,
+ AddiuRxPcImmX16 = 640,
+ AddiuRxRxImm16 = 641,
+ AddiuRxRxImmX16 = 642,
+ AddiuRxRyOffMemX16 = 643,
+ AddiuSpImm16 = 644,
+ AddiuSpImmX16 = 645,
+ AdduRxRyRz16 = 646,
+ AndRxRxRy16 = 647,
+ B16_MM = 648,
+ BADDu = 649,
+ BAL = 650,
+ BALC = 651,
+ BALC_MMR6 = 652,
+ BALIGN = 653,
+ BALIGN_MMR2 = 654,
+ BBIT0 = 655,
+ BBIT032 = 656,
+ BBIT1 = 657,
+ BBIT132 = 658,
+ BC = 659,
+ BC16_MMR6 = 660,
+ BC1EQZ = 661,
+ BC1EQZC_MMR6 = 662,
+ BC1F = 663,
+ BC1FL = 664,
+ BC1F_MM = 665,
+ BC1NEZ = 666,
+ BC1NEZC_MMR6 = 667,
+ BC1T = 668,
+ BC1TL = 669,
+ BC1T_MM = 670,
+ BC2EQZ = 671,
+ BC2EQZC_MMR6 = 672,
+ BC2NEZ = 673,
+ BC2NEZC_MMR6 = 674,
+ BCLRI_B = 675,
+ BCLRI_D = 676,
+ BCLRI_H = 677,
+ BCLRI_W = 678,
+ BCLR_B = 679,
+ BCLR_D = 680,
+ BCLR_H = 681,
+ BCLR_W = 682,
+ BC_MMR6 = 683,
+ BEQ = 684,
+ BEQ64 = 685,
+ BEQC = 686,
+ BEQC64 = 687,
+ BEQC_MMR6 = 688,
+ BEQL = 689,
+ BEQZ16_MM = 690,
+ BEQZALC = 691,
+ BEQZALC_MMR6 = 692,
+ BEQZC = 693,
+ BEQZC16_MMR6 = 694,
+ BEQZC64 = 695,
+ BEQZC_MM = 696,
+ BEQZC_MMR6 = 697,
+ BEQ_MM = 698,
+ BGEC = 699,
+ BGEC64 = 700,
+ BGEC_MMR6 = 701,
+ BGEUC = 702,
+ BGEUC64 = 703,
+ BGEUC_MMR6 = 704,
+ BGEZ = 705,
+ BGEZ64 = 706,
+ BGEZAL = 707,
+ BGEZALC = 708,
+ BGEZALC_MMR6 = 709,
+ BGEZALL = 710,
+ BGEZALS_MM = 711,
+ BGEZAL_MM = 712,
+ BGEZC = 713,
+ BGEZC64 = 714,
+ BGEZC_MMR6 = 715,
+ BGEZL = 716,
+ BGEZ_MM = 717,
+ BGTZ = 718,
+ BGTZ64 = 719,
+ BGTZALC = 720,
+ BGTZALC_MMR6 = 721,
+ BGTZC = 722,
+ BGTZC64 = 723,
+ BGTZC_MMR6 = 724,
+ BGTZL = 725,
+ BGTZ_MM = 726,
+ BINSLI_B = 727,
+ BINSLI_D = 728,
+ BINSLI_H = 729,
+ BINSLI_W = 730,
+ BINSL_B = 731,
+ BINSL_D = 732,
+ BINSL_H = 733,
+ BINSL_W = 734,
+ BINSRI_B = 735,
+ BINSRI_D = 736,
+ BINSRI_H = 737,
+ BINSRI_W = 738,
+ BINSR_B = 739,
+ BINSR_D = 740,
+ BINSR_H = 741,
+ BINSR_W = 742,
+ BITREV = 743,
+ BITREV_MM = 744,
+ BITSWAP = 745,
+ BITSWAP_MMR6 = 746,
+ BLEZ = 747,
+ BLEZ64 = 748,
+ BLEZALC = 749,
+ BLEZALC_MMR6 = 750,
+ BLEZC = 751,
+ BLEZC64 = 752,
+ BLEZC_MMR6 = 753,
+ BLEZL = 754,
+ BLEZ_MM = 755,
+ BLTC = 756,
+ BLTC64 = 757,
+ BLTC_MMR6 = 758,
+ BLTUC = 759,
+ BLTUC64 = 760,
+ BLTUC_MMR6 = 761,
+ BLTZ = 762,
+ BLTZ64 = 763,
+ BLTZAL = 764,
+ BLTZALC = 765,
+ BLTZALC_MMR6 = 766,
+ BLTZALL = 767,
+ BLTZALS_MM = 768,
+ BLTZAL_MM = 769,
+ BLTZC = 770,
+ BLTZC64 = 771,
+ BLTZC_MMR6 = 772,
+ BLTZL = 773,
+ BLTZ_MM = 774,
+ BMNZI_B = 775,
+ BMNZ_V = 776,
+ BMZI_B = 777,
+ BMZ_V = 778,
+ BNE = 779,
+ BNE64 = 780,
+ BNEC = 781,
+ BNEC64 = 782,
+ BNEC_MMR6 = 783,
+ BNEGI_B = 784,
+ BNEGI_D = 785,
+ BNEGI_H = 786,
+ BNEGI_W = 787,
+ BNEG_B = 788,
+ BNEG_D = 789,
+ BNEG_H = 790,
+ BNEG_W = 791,
+ BNEL = 792,
+ BNEZ16_MM = 793,
+ BNEZALC = 794,
+ BNEZALC_MMR6 = 795,
+ BNEZC = 796,
+ BNEZC16_MMR6 = 797,
+ BNEZC64 = 798,
+ BNEZC_MM = 799,
+ BNEZC_MMR6 = 800,
+ BNE_MM = 801,
+ BNVC = 802,
+ BNVC_MMR6 = 803,
+ BNZ_B = 804,
+ BNZ_D = 805,
+ BNZ_H = 806,
+ BNZ_V = 807,
+ BNZ_W = 808,
+ BOVC = 809,
+ BOVC_MMR6 = 810,
+ BPOSGE32 = 811,
+ BPOSGE32C_MMR3 = 812,
+ BPOSGE32_MM = 813,
+ BREAK = 814,
+ BREAK16_MM = 815,
+ BREAK16_MMR6 = 816,
+ BREAK_MM = 817,
+ BREAK_MMR6 = 818,
+ BSELI_B = 819,
+ BSEL_V = 820,
+ BSETI_B = 821,
+ BSETI_D = 822,
+ BSETI_H = 823,
+ BSETI_W = 824,
+ BSET_B = 825,
+ BSET_D = 826,
+ BSET_H = 827,
+ BSET_W = 828,
+ BZ_B = 829,
+ BZ_D = 830,
+ BZ_H = 831,
+ BZ_V = 832,
+ BZ_W = 833,
+ BeqzRxImm16 = 834,
+ BeqzRxImmX16 = 835,
+ Bimm16 = 836,
+ BimmX16 = 837,
+ BnezRxImm16 = 838,
+ BnezRxImmX16 = 839,
+ Break16 = 840,
+ Bteqz16 = 841,
+ BteqzX16 = 842,
+ Btnez16 = 843,
+ BtnezX16 = 844,
+ CACHE = 845,
+ CACHEE = 846,
+ CACHEE_MM = 847,
+ CACHE_MM = 848,
+ CACHE_MMR6 = 849,
+ CACHE_R6 = 850,
+ CEIL_L_D64 = 851,
+ CEIL_L_D_MMR6 = 852,
+ CEIL_L_S = 853,
+ CEIL_L_S_MMR6 = 854,
+ CEIL_W_D32 = 855,
+ CEIL_W_D64 = 856,
+ CEIL_W_D_MMR6 = 857,
+ CEIL_W_MM = 858,
+ CEIL_W_S = 859,
+ CEIL_W_S_MM = 860,
+ CEIL_W_S_MMR6 = 861,
+ CEQI_B = 862,
+ CEQI_D = 863,
+ CEQI_H = 864,
+ CEQI_W = 865,
+ CEQ_B = 866,
+ CEQ_D = 867,
+ CEQ_H = 868,
+ CEQ_W = 869,
+ CFC1 = 870,
+ CFC1_MM = 871,
+ CFC2_MM = 872,
+ CFCMSA = 873,
+ CINS = 874,
+ CINS32 = 875,
+ CINS64_32 = 876,
+ CINS_i32 = 877,
+ CLASS_D = 878,
+ CLASS_D_MMR6 = 879,
+ CLASS_S = 880,
+ CLASS_S_MMR6 = 881,
+ CLEI_S_B = 882,
+ CLEI_S_D = 883,
+ CLEI_S_H = 884,
+ CLEI_S_W = 885,
+ CLEI_U_B = 886,
+ CLEI_U_D = 887,
+ CLEI_U_H = 888,
+ CLEI_U_W = 889,
+ CLE_S_B = 890,
+ CLE_S_D = 891,
+ CLE_S_H = 892,
+ CLE_S_W = 893,
+ CLE_U_B = 894,
+ CLE_U_D = 895,
+ CLE_U_H = 896,
+ CLE_U_W = 897,
+ CLO = 898,
+ CLO_MM = 899,
+ CLO_MMR6 = 900,
+ CLO_R6 = 901,
+ CLTI_S_B = 902,
+ CLTI_S_D = 903,
+ CLTI_S_H = 904,
+ CLTI_S_W = 905,
+ CLTI_U_B = 906,
+ CLTI_U_D = 907,
+ CLTI_U_H = 908,
+ CLTI_U_W = 909,
+ CLT_S_B = 910,
+ CLT_S_D = 911,
+ CLT_S_H = 912,
+ CLT_S_W = 913,
+ CLT_U_B = 914,
+ CLT_U_D = 915,
+ CLT_U_H = 916,
+ CLT_U_W = 917,
+ CLZ = 918,
+ CLZ_MM = 919,
+ CLZ_MMR6 = 920,
+ CLZ_R6 = 921,
+ CMPGDU_EQ_QB = 922,
+ CMPGDU_EQ_QB_MMR2 = 923,
+ CMPGDU_LE_QB = 924,
+ CMPGDU_LE_QB_MMR2 = 925,
+ CMPGDU_LT_QB = 926,
+ CMPGDU_LT_QB_MMR2 = 927,
+ CMPGU_EQ_QB = 928,
+ CMPGU_EQ_QB_MM = 929,
+ CMPGU_LE_QB = 930,
+ CMPGU_LE_QB_MM = 931,
+ CMPGU_LT_QB = 932,
+ CMPGU_LT_QB_MM = 933,
+ CMPU_EQ_QB = 934,
+ CMPU_EQ_QB_MM = 935,
+ CMPU_LE_QB = 936,
+ CMPU_LE_QB_MM = 937,
+ CMPU_LT_QB = 938,
+ CMPU_LT_QB_MM = 939,
+ CMP_AF_D_MMR6 = 940,
+ CMP_AF_S_MMR6 = 941,
+ CMP_EQ_D = 942,
+ CMP_EQ_D_MMR6 = 943,
+ CMP_EQ_PH = 944,
+ CMP_EQ_PH_MM = 945,
+ CMP_EQ_S = 946,
+ CMP_EQ_S_MMR6 = 947,
+ CMP_F_D = 948,
+ CMP_F_S = 949,
+ CMP_LE_D = 950,
+ CMP_LE_D_MMR6 = 951,
+ CMP_LE_PH = 952,
+ CMP_LE_PH_MM = 953,
+ CMP_LE_S = 954,
+ CMP_LE_S_MMR6 = 955,
+ CMP_LT_D = 956,
+ CMP_LT_D_MMR6 = 957,
+ CMP_LT_PH = 958,
+ CMP_LT_PH_MM = 959,
+ CMP_LT_S = 960,
+ CMP_LT_S_MMR6 = 961,
+ CMP_SAF_D = 962,
+ CMP_SAF_D_MMR6 = 963,
+ CMP_SAF_S = 964,
+ CMP_SAF_S_MMR6 = 965,
+ CMP_SEQ_D = 966,
+ CMP_SEQ_D_MMR6 = 967,
+ CMP_SEQ_S = 968,
+ CMP_SEQ_S_MMR6 = 969,
+ CMP_SLE_D = 970,
+ CMP_SLE_D_MMR6 = 971,
+ CMP_SLE_S = 972,
+ CMP_SLE_S_MMR6 = 973,
+ CMP_SLT_D = 974,
+ CMP_SLT_D_MMR6 = 975,
+ CMP_SLT_S = 976,
+ CMP_SLT_S_MMR6 = 977,
+ CMP_SUEQ_D = 978,
+ CMP_SUEQ_D_MMR6 = 979,
+ CMP_SUEQ_S = 980,
+ CMP_SUEQ_S_MMR6 = 981,
+ CMP_SULE_D = 982,
+ CMP_SULE_D_MMR6 = 983,
+ CMP_SULE_S = 984,
+ CMP_SULE_S_MMR6 = 985,
+ CMP_SULT_D = 986,
+ CMP_SULT_D_MMR6 = 987,
+ CMP_SULT_S = 988,
+ CMP_SULT_S_MMR6 = 989,
+ CMP_SUN_D = 990,
+ CMP_SUN_D_MMR6 = 991,
+ CMP_SUN_S = 992,
+ CMP_SUN_S_MMR6 = 993,
+ CMP_UEQ_D = 994,
+ CMP_UEQ_D_MMR6 = 995,
+ CMP_UEQ_S = 996,
+ CMP_UEQ_S_MMR6 = 997,
+ CMP_ULE_D = 998,
+ CMP_ULE_D_MMR6 = 999,
+ CMP_ULE_S = 1000,
+ CMP_ULE_S_MMR6 = 1001,
+ CMP_ULT_D = 1002,
+ CMP_ULT_D_MMR6 = 1003,
+ CMP_ULT_S = 1004,
+ CMP_ULT_S_MMR6 = 1005,
+ CMP_UN_D = 1006,
+ CMP_UN_D_MMR6 = 1007,
+ CMP_UN_S = 1008,
+ CMP_UN_S_MMR6 = 1009,
+ COPY_S_B = 1010,
+ COPY_S_D = 1011,
+ COPY_S_H = 1012,
+ COPY_S_W = 1013,
+ COPY_U_B = 1014,
+ COPY_U_H = 1015,
+ COPY_U_W = 1016,
+ CRC32B = 1017,
+ CRC32CB = 1018,
+ CRC32CD = 1019,
+ CRC32CH = 1020,
+ CRC32CW = 1021,
+ CRC32D = 1022,
+ CRC32H = 1023,
+ CRC32W = 1024,
+ CTC1 = 1025,
+ CTC1_MM = 1026,
+ CTC2_MM = 1027,
+ CTCMSA = 1028,
+ CVT_D32_S = 1029,
+ CVT_D32_S_MM = 1030,
+ CVT_D32_W = 1031,
+ CVT_D32_W_MM = 1032,
+ CVT_D64_L = 1033,
+ CVT_D64_S = 1034,
+ CVT_D64_S_MM = 1035,
+ CVT_D64_W = 1036,
+ CVT_D64_W_MM = 1037,
+ CVT_D_L_MMR6 = 1038,
+ CVT_L_D64 = 1039,
+ CVT_L_D64_MM = 1040,
+ CVT_L_D_MMR6 = 1041,
+ CVT_L_S = 1042,
+ CVT_L_S_MM = 1043,
+ CVT_L_S_MMR6 = 1044,
+ CVT_S_D32 = 1045,
+ CVT_S_D32_MM = 1046,
+ CVT_S_D64 = 1047,
+ CVT_S_D64_MM = 1048,
+ CVT_S_L = 1049,
+ CVT_S_L_MMR6 = 1050,
+ CVT_S_W = 1051,
+ CVT_S_W_MM = 1052,
+ CVT_S_W_MMR6 = 1053,
+ CVT_W_D32 = 1054,
+ CVT_W_D32_MM = 1055,
+ CVT_W_D64 = 1056,
+ CVT_W_D64_MM = 1057,
+ CVT_W_S = 1058,
+ CVT_W_S_MM = 1059,
+ CVT_W_S_MMR6 = 1060,
+ C_EQ_D32 = 1061,
+ C_EQ_D32_MM = 1062,
+ C_EQ_D64 = 1063,
+ C_EQ_D64_MM = 1064,
+ C_EQ_S = 1065,
+ C_EQ_S_MM = 1066,
+ C_F_D32 = 1067,
+ C_F_D32_MM = 1068,
+ C_F_D64 = 1069,
+ C_F_D64_MM = 1070,
+ C_F_S = 1071,
+ C_F_S_MM = 1072,
+ C_LE_D32 = 1073,
+ C_LE_D32_MM = 1074,
+ C_LE_D64 = 1075,
+ C_LE_D64_MM = 1076,
+ C_LE_S = 1077,
+ C_LE_S_MM = 1078,
+ C_LT_D32 = 1079,
+ C_LT_D32_MM = 1080,
+ C_LT_D64 = 1081,
+ C_LT_D64_MM = 1082,
+ C_LT_S = 1083,
+ C_LT_S_MM = 1084,
+ C_NGE_D32 = 1085,
+ C_NGE_D32_MM = 1086,
+ C_NGE_D64 = 1087,
+ C_NGE_D64_MM = 1088,
+ C_NGE_S = 1089,
+ C_NGE_S_MM = 1090,
+ C_NGLE_D32 = 1091,
+ C_NGLE_D32_MM = 1092,
+ C_NGLE_D64 = 1093,
+ C_NGLE_D64_MM = 1094,
+ C_NGLE_S = 1095,
+ C_NGLE_S_MM = 1096,
+ C_NGL_D32 = 1097,
+ C_NGL_D32_MM = 1098,
+ C_NGL_D64 = 1099,
+ C_NGL_D64_MM = 1100,
+ C_NGL_S = 1101,
+ C_NGL_S_MM = 1102,
+ C_NGT_D32 = 1103,
+ C_NGT_D32_MM = 1104,
+ C_NGT_D64 = 1105,
+ C_NGT_D64_MM = 1106,
+ C_NGT_S = 1107,
+ C_NGT_S_MM = 1108,
+ C_OLE_D32 = 1109,
+ C_OLE_D32_MM = 1110,
+ C_OLE_D64 = 1111,
+ C_OLE_D64_MM = 1112,
+ C_OLE_S = 1113,
+ C_OLE_S_MM = 1114,
+ C_OLT_D32 = 1115,
+ C_OLT_D32_MM = 1116,
+ C_OLT_D64 = 1117,
+ C_OLT_D64_MM = 1118,
+ C_OLT_S = 1119,
+ C_OLT_S_MM = 1120,
+ C_SEQ_D32 = 1121,
+ C_SEQ_D32_MM = 1122,
+ C_SEQ_D64 = 1123,
+ C_SEQ_D64_MM = 1124,
+ C_SEQ_S = 1125,
+ C_SEQ_S_MM = 1126,
+ C_SF_D32 = 1127,
+ C_SF_D32_MM = 1128,
+ C_SF_D64 = 1129,
+ C_SF_D64_MM = 1130,
+ C_SF_S = 1131,
+ C_SF_S_MM = 1132,
+ C_UEQ_D32 = 1133,
+ C_UEQ_D32_MM = 1134,
+ C_UEQ_D64 = 1135,
+ C_UEQ_D64_MM = 1136,
+ C_UEQ_S = 1137,
+ C_UEQ_S_MM = 1138,
+ C_ULE_D32 = 1139,
+ C_ULE_D32_MM = 1140,
+ C_ULE_D64 = 1141,
+ C_ULE_D64_MM = 1142,
+ C_ULE_S = 1143,
+ C_ULE_S_MM = 1144,
+ C_ULT_D32 = 1145,
+ C_ULT_D32_MM = 1146,
+ C_ULT_D64 = 1147,
+ C_ULT_D64_MM = 1148,
+ C_ULT_S = 1149,
+ C_ULT_S_MM = 1150,
+ C_UN_D32 = 1151,
+ C_UN_D32_MM = 1152,
+ C_UN_D64 = 1153,
+ C_UN_D64_MM = 1154,
+ C_UN_S = 1155,
+ C_UN_S_MM = 1156,
+ CmpRxRy16 = 1157,
+ CmpiRxImm16 = 1158,
+ CmpiRxImmX16 = 1159,
+ DADD = 1160,
+ DADDi = 1161,
+ DADDiu = 1162,
+ DADDu = 1163,
+ DAHI = 1164,
+ DALIGN = 1165,
+ DATI = 1166,
+ DAUI = 1167,
+ DBITSWAP = 1168,
+ DCLO = 1169,
+ DCLO_R6 = 1170,
+ DCLZ = 1171,
+ DCLZ_R6 = 1172,
+ DDIV = 1173,
+ DDIVU = 1174,
+ DERET = 1175,
+ DERET_MM = 1176,
+ DERET_MMR6 = 1177,
+ DEXT = 1178,
+ DEXT64_32 = 1179,
+ DEXTM = 1180,
+ DEXTU = 1181,
+ DI = 1182,
+ DINS = 1183,
+ DINSM = 1184,
+ DINSU = 1185,
+ DIV = 1186,
+ DIVU = 1187,
+ DIVU_MMR6 = 1188,
+ DIV_MMR6 = 1189,
+ DIV_S_B = 1190,
+ DIV_S_D = 1191,
+ DIV_S_H = 1192,
+ DIV_S_W = 1193,
+ DIV_U_B = 1194,
+ DIV_U_D = 1195,
+ DIV_U_H = 1196,
+ DIV_U_W = 1197,
+ DI_MM = 1198,
+ DI_MMR6 = 1199,
+ DLSA = 1200,
+ DLSA_R6 = 1201,
+ DMFC0 = 1202,
+ DMFC1 = 1203,
+ DMFC2 = 1204,
+ DMFC2_OCTEON = 1205,
+ DMFGC0 = 1206,
+ DMOD = 1207,
+ DMODU = 1208,
+ DMT = 1209,
+ DMTC0 = 1210,
+ DMTC1 = 1211,
+ DMTC2 = 1212,
+ DMTC2_OCTEON = 1213,
+ DMTGC0 = 1214,
+ DMUH = 1215,
+ DMUHU = 1216,
+ DMUL = 1217,
+ DMULT = 1218,
+ DMULTu = 1219,
+ DMULU = 1220,
+ DMUL_R6 = 1221,
+ DOTP_S_D = 1222,
+ DOTP_S_H = 1223,
+ DOTP_S_W = 1224,
+ DOTP_U_D = 1225,
+ DOTP_U_H = 1226,
+ DOTP_U_W = 1227,
+ DPADD_S_D = 1228,
+ DPADD_S_H = 1229,
+ DPADD_S_W = 1230,
+ DPADD_U_D = 1231,
+ DPADD_U_H = 1232,
+ DPADD_U_W = 1233,
+ DPAQX_SA_W_PH = 1234,
+ DPAQX_SA_W_PH_MMR2 = 1235,
+ DPAQX_S_W_PH = 1236,
+ DPAQX_S_W_PH_MMR2 = 1237,
+ DPAQ_SA_L_W = 1238,
+ DPAQ_SA_L_W_MM = 1239,
+ DPAQ_S_W_PH = 1240,
+ DPAQ_S_W_PH_MM = 1241,
+ DPAU_H_QBL = 1242,
+ DPAU_H_QBL_MM = 1243,
+ DPAU_H_QBR = 1244,
+ DPAU_H_QBR_MM = 1245,
+ DPAX_W_PH = 1246,
+ DPAX_W_PH_MMR2 = 1247,
+ DPA_W_PH = 1248,
+ DPA_W_PH_MMR2 = 1249,
+ DPOP = 1250,
+ DPSQX_SA_W_PH = 1251,
+ DPSQX_SA_W_PH_MMR2 = 1252,
+ DPSQX_S_W_PH = 1253,
+ DPSQX_S_W_PH_MMR2 = 1254,
+ DPSQ_SA_L_W = 1255,
+ DPSQ_SA_L_W_MM = 1256,
+ DPSQ_S_W_PH = 1257,
+ DPSQ_S_W_PH_MM = 1258,
+ DPSUB_S_D = 1259,
+ DPSUB_S_H = 1260,
+ DPSUB_S_W = 1261,
+ DPSUB_U_D = 1262,
+ DPSUB_U_H = 1263,
+ DPSUB_U_W = 1264,
+ DPSU_H_QBL = 1265,
+ DPSU_H_QBL_MM = 1266,
+ DPSU_H_QBR = 1267,
+ DPSU_H_QBR_MM = 1268,
+ DPSX_W_PH = 1269,
+ DPSX_W_PH_MMR2 = 1270,
+ DPS_W_PH = 1271,
+ DPS_W_PH_MMR2 = 1272,
+ DROTR = 1273,
+ DROTR32 = 1274,
+ DROTRV = 1275,
+ DSBH = 1276,
+ DSDIV = 1277,
+ DSHD = 1278,
+ DSLL = 1279,
+ DSLL32 = 1280,
+ DSLL64_32 = 1281,
+ DSLLV = 1282,
+ DSRA = 1283,
+ DSRA32 = 1284,
+ DSRAV = 1285,
+ DSRL = 1286,
+ DSRL32 = 1287,
+ DSRLV = 1288,
+ DSUB = 1289,
+ DSUBu = 1290,
+ DUDIV = 1291,
+ DVP = 1292,
+ DVPE = 1293,
+ DVP_MMR6 = 1294,
+ DivRxRy16 = 1295,
+ DivuRxRy16 = 1296,
+ EHB = 1297,
+ EHB_MM = 1298,
+ EHB_MMR6 = 1299,
+ EI = 1300,
+ EI_MM = 1301,
+ EI_MMR6 = 1302,
+ EMT = 1303,
+ ERET = 1304,
+ ERETNC = 1305,
+ ERETNC_MMR6 = 1306,
+ ERET_MM = 1307,
+ ERET_MMR6 = 1308,
+ EVP = 1309,
+ EVPE = 1310,
+ EVP_MMR6 = 1311,
+ EXT = 1312,
+ EXTP = 1313,
+ EXTPDP = 1314,
+ EXTPDPV = 1315,
+ EXTPDPV_MM = 1316,
+ EXTPDP_MM = 1317,
+ EXTPV = 1318,
+ EXTPV_MM = 1319,
+ EXTP_MM = 1320,
+ EXTRV_RS_W = 1321,
+ EXTRV_RS_W_MM = 1322,
+ EXTRV_R_W = 1323,
+ EXTRV_R_W_MM = 1324,
+ EXTRV_S_H = 1325,
+ EXTRV_S_H_MM = 1326,
+ EXTRV_W = 1327,
+ EXTRV_W_MM = 1328,
+ EXTR_RS_W = 1329,
+ EXTR_RS_W_MM = 1330,
+ EXTR_R_W = 1331,
+ EXTR_R_W_MM = 1332,
+ EXTR_S_H = 1333,
+ EXTR_S_H_MM = 1334,
+ EXTR_W = 1335,
+ EXTR_W_MM = 1336,
+ EXTS = 1337,
+ EXTS32 = 1338,
+ EXT_MM = 1339,
+ EXT_MMR6 = 1340,
+ FABS_D32 = 1341,
+ FABS_D32_MM = 1342,
+ FABS_D64 = 1343,
+ FABS_D64_MM = 1344,
+ FABS_S = 1345,
+ FABS_S_MM = 1346,
+ FADD_D = 1347,
+ FADD_D32 = 1348,
+ FADD_D32_MM = 1349,
+ FADD_D64 = 1350,
+ FADD_D64_MM = 1351,
+ FADD_S = 1352,
+ FADD_S_MM = 1353,
+ FADD_S_MMR6 = 1354,
+ FADD_W = 1355,
+ FCAF_D = 1356,
+ FCAF_W = 1357,
+ FCEQ_D = 1358,
+ FCEQ_W = 1359,
+ FCLASS_D = 1360,
+ FCLASS_W = 1361,
+ FCLE_D = 1362,
+ FCLE_W = 1363,
+ FCLT_D = 1364,
+ FCLT_W = 1365,
+ FCMP_D32 = 1366,
+ FCMP_D32_MM = 1367,
+ FCMP_D64 = 1368,
+ FCMP_S32 = 1369,
+ FCMP_S32_MM = 1370,
+ FCNE_D = 1371,
+ FCNE_W = 1372,
+ FCOR_D = 1373,
+ FCOR_W = 1374,
+ FCUEQ_D = 1375,
+ FCUEQ_W = 1376,
+ FCULE_D = 1377,
+ FCULE_W = 1378,
+ FCULT_D = 1379,
+ FCULT_W = 1380,
+ FCUNE_D = 1381,
+ FCUNE_W = 1382,
+ FCUN_D = 1383,
+ FCUN_W = 1384,
+ FDIV_D = 1385,
+ FDIV_D32 = 1386,
+ FDIV_D32_MM = 1387,
+ FDIV_D64 = 1388,
+ FDIV_D64_MM = 1389,
+ FDIV_S = 1390,
+ FDIV_S_MM = 1391,
+ FDIV_S_MMR6 = 1392,
+ FDIV_W = 1393,
+ FEXDO_H = 1394,
+ FEXDO_W = 1395,
+ FEXP2_D = 1396,
+ FEXP2_W = 1397,
+ FEXUPL_D = 1398,
+ FEXUPL_W = 1399,
+ FEXUPR_D = 1400,
+ FEXUPR_W = 1401,
+ FFINT_S_D = 1402,
+ FFINT_S_W = 1403,
+ FFINT_U_D = 1404,
+ FFINT_U_W = 1405,
+ FFQL_D = 1406,
+ FFQL_W = 1407,
+ FFQR_D = 1408,
+ FFQR_W = 1409,
+ FILL_B = 1410,
+ FILL_D = 1411,
+ FILL_H = 1412,
+ FILL_W = 1413,
+ FLOG2_D = 1414,
+ FLOG2_W = 1415,
+ FLOOR_L_D64 = 1416,
+ FLOOR_L_D_MMR6 = 1417,
+ FLOOR_L_S = 1418,
+ FLOOR_L_S_MMR6 = 1419,
+ FLOOR_W_D32 = 1420,
+ FLOOR_W_D64 = 1421,
+ FLOOR_W_D_MMR6 = 1422,
+ FLOOR_W_MM = 1423,
+ FLOOR_W_S = 1424,
+ FLOOR_W_S_MM = 1425,
+ FLOOR_W_S_MMR6 = 1426,
+ FMADD_D = 1427,
+ FMADD_W = 1428,
+ FMAX_A_D = 1429,
+ FMAX_A_W = 1430,
+ FMAX_D = 1431,
+ FMAX_W = 1432,
+ FMIN_A_D = 1433,
+ FMIN_A_W = 1434,
+ FMIN_D = 1435,
+ FMIN_W = 1436,
+ FMOV_D32 = 1437,
+ FMOV_D32_MM = 1438,
+ FMOV_D64 = 1439,
+ FMOV_D64_MM = 1440,
+ FMOV_S = 1441,
+ FMOV_S_MM = 1442,
+ FMOV_S_MMR6 = 1443,
+ FMSUB_D = 1444,
+ FMSUB_W = 1445,
+ FMUL_D = 1446,
+ FMUL_D32 = 1447,
+ FMUL_D32_MM = 1448,
+ FMUL_D64 = 1449,
+ FMUL_D64_MM = 1450,
+ FMUL_S = 1451,
+ FMUL_S_MM = 1452,
+ FMUL_S_MMR6 = 1453,
+ FMUL_W = 1454,
+ FNEG_D32 = 1455,
+ FNEG_D32_MM = 1456,
+ FNEG_D64 = 1457,
+ FNEG_D64_MM = 1458,
+ FNEG_S = 1459,
+ FNEG_S_MM = 1460,
+ FNEG_S_MMR6 = 1461,
+ FORK = 1462,
+ FRCP_D = 1463,
+ FRCP_W = 1464,
+ FRINT_D = 1465,
+ FRINT_W = 1466,
+ FRSQRT_D = 1467,
+ FRSQRT_W = 1468,
+ FSAF_D = 1469,
+ FSAF_W = 1470,
+ FSEQ_D = 1471,
+ FSEQ_W = 1472,
+ FSLE_D = 1473,
+ FSLE_W = 1474,
+ FSLT_D = 1475,
+ FSLT_W = 1476,
+ FSNE_D = 1477,
+ FSNE_W = 1478,
+ FSOR_D = 1479,
+ FSOR_W = 1480,
+ FSQRT_D = 1481,
+ FSQRT_D32 = 1482,
+ FSQRT_D32_MM = 1483,
+ FSQRT_D64 = 1484,
+ FSQRT_D64_MM = 1485,
+ FSQRT_S = 1486,
+ FSQRT_S_MM = 1487,
+ FSQRT_W = 1488,
+ FSUB_D = 1489,
+ FSUB_D32 = 1490,
+ FSUB_D32_MM = 1491,
+ FSUB_D64 = 1492,
+ FSUB_D64_MM = 1493,
+ FSUB_S = 1494,
+ FSUB_S_MM = 1495,
+ FSUB_S_MMR6 = 1496,
+ FSUB_W = 1497,
+ FSUEQ_D = 1498,
+ FSUEQ_W = 1499,
+ FSULE_D = 1500,
+ FSULE_W = 1501,
+ FSULT_D = 1502,
+ FSULT_W = 1503,
+ FSUNE_D = 1504,
+ FSUNE_W = 1505,
+ FSUN_D = 1506,
+ FSUN_W = 1507,
+ FTINT_S_D = 1508,
+ FTINT_S_W = 1509,
+ FTINT_U_D = 1510,
+ FTINT_U_W = 1511,
+ FTQ_H = 1512,
+ FTQ_W = 1513,
+ FTRUNC_S_D = 1514,
+ FTRUNC_S_W = 1515,
+ FTRUNC_U_D = 1516,
+ FTRUNC_U_W = 1517,
+ GINVI = 1518,
+ GINVI_MMR6 = 1519,
+ GINVT = 1520,
+ GINVT_MMR6 = 1521,
+ HADD_S_D = 1522,
+ HADD_S_H = 1523,
+ HADD_S_W = 1524,
+ HADD_U_D = 1525,
+ HADD_U_H = 1526,
+ HADD_U_W = 1527,
+ HSUB_S_D = 1528,
+ HSUB_S_H = 1529,
+ HSUB_S_W = 1530,
+ HSUB_U_D = 1531,
+ HSUB_U_H = 1532,
+ HSUB_U_W = 1533,
+ HYPCALL = 1534,
+ HYPCALL_MM = 1535,
+ ILVEV_B = 1536,
+ ILVEV_D = 1537,
+ ILVEV_H = 1538,
+ ILVEV_W = 1539,
+ ILVL_B = 1540,
+ ILVL_D = 1541,
+ ILVL_H = 1542,
+ ILVL_W = 1543,
+ ILVOD_B = 1544,
+ ILVOD_D = 1545,
+ ILVOD_H = 1546,
+ ILVOD_W = 1547,
+ ILVR_B = 1548,
+ ILVR_D = 1549,
+ ILVR_H = 1550,
+ ILVR_W = 1551,
+ INS = 1552,
+ INSERT_B = 1553,
+ INSERT_D = 1554,
+ INSERT_H = 1555,
+ INSERT_W = 1556,
+ INSV = 1557,
+ INSVE_B = 1558,
+ INSVE_D = 1559,
+ INSVE_H = 1560,
+ INSVE_W = 1561,
+ INSV_MM = 1562,
+ INS_MM = 1563,
+ INS_MMR6 = 1564,
+ J = 1565,
+ JAL = 1566,
+ JALR = 1567,
+ JALR16_MM = 1568,
+ JALR64 = 1569,
+ JALRC16_MMR6 = 1570,
+ JALRC_HB_MMR6 = 1571,
+ JALRC_MMR6 = 1572,
+ JALRS16_MM = 1573,
+ JALRS_MM = 1574,
+ JALR_HB = 1575,
+ JALR_HB64 = 1576,
+ JALR_MM = 1577,
+ JALS_MM = 1578,
+ JALX = 1579,
+ JALX_MM = 1580,
+ JAL_MM = 1581,
+ JIALC = 1582,
+ JIALC64 = 1583,
+ JIALC_MMR6 = 1584,
+ JIC = 1585,
+ JIC64 = 1586,
+ JIC_MMR6 = 1587,
+ JR = 1588,
+ JR16_MM = 1589,
+ JR64 = 1590,
+ JRADDIUSP = 1591,
+ JRC16_MM = 1592,
+ JRC16_MMR6 = 1593,
+ JRCADDIUSP_MMR6 = 1594,
+ JR_HB = 1595,
+ JR_HB64 = 1596,
+ JR_HB64_R6 = 1597,
+ JR_HB_R6 = 1598,
+ JR_MM = 1599,
+ J_MM = 1600,
+ Jal16 = 1601,
+ JalB16 = 1602,
+ JrRa16 = 1603,
+ JrcRa16 = 1604,
+ JrcRx16 = 1605,
+ JumpLinkReg16 = 1606,
+ LB = 1607,
+ LB64 = 1608,
+ LBE = 1609,
+ LBE_MM = 1610,
+ LBU16_MM = 1611,
+ LBUX = 1612,
+ LBUX_MM = 1613,
+ LBU_MMR6 = 1614,
+ LB_MM = 1615,
+ LB_MMR6 = 1616,
+ LBu = 1617,
+ LBu64 = 1618,
+ LBuE = 1619,
+ LBuE_MM = 1620,
+ LBu_MM = 1621,
+ LD = 1622,
+ LDC1 = 1623,
+ LDC164 = 1624,
+ LDC1_D64_MMR6 = 1625,
+ LDC1_MM = 1626,
+ LDC2 = 1627,
+ LDC2_MMR6 = 1628,
+ LDC2_R6 = 1629,
+ LDC3 = 1630,
+ LDI_B = 1631,
+ LDI_D = 1632,
+ LDI_H = 1633,
+ LDI_W = 1634,
+ LDL = 1635,
+ LDPC = 1636,
+ LDR = 1637,
+ LDXC1 = 1638,
+ LDXC164 = 1639,
+ LD_B = 1640,
+ LD_D = 1641,
+ LD_H = 1642,
+ LD_W = 1643,
+ LEA_ADDiu = 1644,
+ LEA_ADDiu64 = 1645,
+ LEA_ADDiu_MM = 1646,
+ LH = 1647,
+ LH64 = 1648,
+ LHE = 1649,
+ LHE_MM = 1650,
+ LHU16_MM = 1651,
+ LHX = 1652,
+ LHX_MM = 1653,
+ LH_MM = 1654,
+ LHu = 1655,
+ LHu64 = 1656,
+ LHuE = 1657,
+ LHuE_MM = 1658,
+ LHu_MM = 1659,
+ LI16_MM = 1660,
+ LI16_MMR6 = 1661,
+ LL = 1662,
+ LL64 = 1663,
+ LL64_R6 = 1664,
+ LLD = 1665,
+ LLD_R6 = 1666,
+ LLE = 1667,
+ LLE_MM = 1668,
+ LL_MM = 1669,
+ LL_MMR6 = 1670,
+ LL_R6 = 1671,
+ LSA = 1672,
+ LSA_MMR6 = 1673,
+ LSA_R6 = 1674,
+ LUI_MMR6 = 1675,
+ LUXC1 = 1676,
+ LUXC164 = 1677,
+ LUXC1_MM = 1678,
+ LUi = 1679,
+ LUi64 = 1680,
+ LUi_MM = 1681,
+ LW = 1682,
+ LW16_MM = 1683,
+ LW64 = 1684,
+ LWC1 = 1685,
+ LWC1_MM = 1686,
+ LWC2 = 1687,
+ LWC2_MMR6 = 1688,
+ LWC2_R6 = 1689,
+ LWC3 = 1690,
+ LWDSP = 1691,
+ LWDSP_MM = 1692,
+ LWE = 1693,
+ LWE_MM = 1694,
+ LWGP_MM = 1695,
+ LWL = 1696,
+ LWL64 = 1697,
+ LWLE = 1698,
+ LWLE_MM = 1699,
+ LWL_MM = 1700,
+ LWM16_MM = 1701,
+ LWM16_MMR6 = 1702,
+ LWM32_MM = 1703,
+ LWPC = 1704,
+ LWPC_MMR6 = 1705,
+ LWP_MM = 1706,
+ LWR = 1707,
+ LWR64 = 1708,
+ LWRE = 1709,
+ LWRE_MM = 1710,
+ LWR_MM = 1711,
+ LWSP_MM = 1712,
+ LWUPC = 1713,
+ LWU_MM = 1714,
+ LWX = 1715,
+ LWXC1 = 1716,
+ LWXC1_MM = 1717,
+ LWXS_MM = 1718,
+ LWX_MM = 1719,
+ LW_MM = 1720,
+ LW_MMR6 = 1721,
+ LWu = 1722,
+ LbRxRyOffMemX16 = 1723,
+ LbuRxRyOffMemX16 = 1724,
+ LhRxRyOffMemX16 = 1725,
+ LhuRxRyOffMemX16 = 1726,
+ LiRxImm16 = 1727,
+ LiRxImmAlignX16 = 1728,
+ LiRxImmX16 = 1729,
+ LwRxPcTcp16 = 1730,
+ LwRxPcTcpX16 = 1731,
+ LwRxRyOffMemX16 = 1732,
+ LwRxSpImmX16 = 1733,
+ MADD = 1734,
+ MADDF_D = 1735,
+ MADDF_D_MMR6 = 1736,
+ MADDF_S = 1737,
+ MADDF_S_MMR6 = 1738,
+ MADDR_Q_H = 1739,
+ MADDR_Q_W = 1740,
+ MADDU = 1741,
+ MADDU_DSP = 1742,
+ MADDU_DSP_MM = 1743,
+ MADDU_MM = 1744,
+ MADDV_B = 1745,
+ MADDV_D = 1746,
+ MADDV_H = 1747,
+ MADDV_W = 1748,
+ MADD_D32 = 1749,
+ MADD_D32_MM = 1750,
+ MADD_D64 = 1751,
+ MADD_DSP = 1752,
+ MADD_DSP_MM = 1753,
+ MADD_MM = 1754,
+ MADD_Q_H = 1755,
+ MADD_Q_W = 1756,
+ MADD_S = 1757,
+ MADD_S_MM = 1758,
+ MAQ_SA_W_PHL = 1759,
+ MAQ_SA_W_PHL_MM = 1760,
+ MAQ_SA_W_PHR = 1761,
+ MAQ_SA_W_PHR_MM = 1762,
+ MAQ_S_W_PHL = 1763,
+ MAQ_S_W_PHL_MM = 1764,
+ MAQ_S_W_PHR = 1765,
+ MAQ_S_W_PHR_MM = 1766,
+ MAXA_D = 1767,
+ MAXA_D_MMR6 = 1768,
+ MAXA_S = 1769,
+ MAXA_S_MMR6 = 1770,
+ MAXI_S_B = 1771,
+ MAXI_S_D = 1772,
+ MAXI_S_H = 1773,
+ MAXI_S_W = 1774,
+ MAXI_U_B = 1775,
+ MAXI_U_D = 1776,
+ MAXI_U_H = 1777,
+ MAXI_U_W = 1778,
+ MAX_A_B = 1779,
+ MAX_A_D = 1780,
+ MAX_A_H = 1781,
+ MAX_A_W = 1782,
+ MAX_D = 1783,
+ MAX_D_MMR6 = 1784,
+ MAX_S = 1785,
+ MAX_S_B = 1786,
+ MAX_S_D = 1787,
+ MAX_S_H = 1788,
+ MAX_S_MMR6 = 1789,
+ MAX_S_W = 1790,
+ MAX_U_B = 1791,
+ MAX_U_D = 1792,
+ MAX_U_H = 1793,
+ MAX_U_W = 1794,
+ MFC0 = 1795,
+ MFC0_MMR6 = 1796,
+ MFC1 = 1797,
+ MFC1_D64 = 1798,
+ MFC1_MM = 1799,
+ MFC1_MMR6 = 1800,
+ MFC2 = 1801,
+ MFC2_MMR6 = 1802,
+ MFGC0 = 1803,
+ MFGC0_MM = 1804,
+ MFHC0_MMR6 = 1805,
+ MFHC1_D32 = 1806,
+ MFHC1_D32_MM = 1807,
+ MFHC1_D64 = 1808,
+ MFHC1_D64_MM = 1809,
+ MFHC2_MMR6 = 1810,
+ MFHGC0 = 1811,
+ MFHGC0_MM = 1812,
+ MFHI = 1813,
+ MFHI16_MM = 1814,
+ MFHI64 = 1815,
+ MFHI_DSP = 1816,
+ MFHI_DSP_MM = 1817,
+ MFHI_MM = 1818,
+ MFLO = 1819,
+ MFLO16_MM = 1820,
+ MFLO64 = 1821,
+ MFLO_DSP = 1822,
+ MFLO_DSP_MM = 1823,
+ MFLO_MM = 1824,
+ MFTR = 1825,
+ MINA_D = 1826,
+ MINA_D_MMR6 = 1827,
+ MINA_S = 1828,
+ MINA_S_MMR6 = 1829,
+ MINI_S_B = 1830,
+ MINI_S_D = 1831,
+ MINI_S_H = 1832,
+ MINI_S_W = 1833,
+ MINI_U_B = 1834,
+ MINI_U_D = 1835,
+ MINI_U_H = 1836,
+ MINI_U_W = 1837,
+ MIN_A_B = 1838,
+ MIN_A_D = 1839,
+ MIN_A_H = 1840,
+ MIN_A_W = 1841,
+ MIN_D = 1842,
+ MIN_D_MMR6 = 1843,
+ MIN_S = 1844,
+ MIN_S_B = 1845,
+ MIN_S_D = 1846,
+ MIN_S_H = 1847,
+ MIN_S_MMR6 = 1848,
+ MIN_S_W = 1849,
+ MIN_U_B = 1850,
+ MIN_U_D = 1851,
+ MIN_U_H = 1852,
+ MIN_U_W = 1853,
+ MOD = 1854,
+ MODSUB = 1855,
+ MODSUB_MM = 1856,
+ MODU = 1857,
+ MODU_MMR6 = 1858,
+ MOD_MMR6 = 1859,
+ MOD_S_B = 1860,
+ MOD_S_D = 1861,
+ MOD_S_H = 1862,
+ MOD_S_W = 1863,
+ MOD_U_B = 1864,
+ MOD_U_D = 1865,
+ MOD_U_H = 1866,
+ MOD_U_W = 1867,
+ MOVE16_MM = 1868,
+ MOVE16_MMR6 = 1869,
+ MOVEP_MM = 1870,
+ MOVEP_MMR6 = 1871,
+ MOVE_V = 1872,
+ MOVF_D32 = 1873,
+ MOVF_D32_MM = 1874,
+ MOVF_D64 = 1875,
+ MOVF_I = 1876,
+ MOVF_I64 = 1877,
+ MOVF_I_MM = 1878,
+ MOVF_S = 1879,
+ MOVF_S_MM = 1880,
+ MOVN_I64_D64 = 1881,
+ MOVN_I64_I = 1882,
+ MOVN_I64_I64 = 1883,
+ MOVN_I64_S = 1884,
+ MOVN_I_D32 = 1885,
+ MOVN_I_D32_MM = 1886,
+ MOVN_I_D64 = 1887,
+ MOVN_I_I = 1888,
+ MOVN_I_I64 = 1889,
+ MOVN_I_MM = 1890,
+ MOVN_I_S = 1891,
+ MOVN_I_S_MM = 1892,
+ MOVT_D32 = 1893,
+ MOVT_D32_MM = 1894,
+ MOVT_D64 = 1895,
+ MOVT_I = 1896,
+ MOVT_I64 = 1897,
+ MOVT_I_MM = 1898,
+ MOVT_S = 1899,
+ MOVT_S_MM = 1900,
+ MOVZ_I64_D64 = 1901,
+ MOVZ_I64_I = 1902,
+ MOVZ_I64_I64 = 1903,
+ MOVZ_I64_S = 1904,
+ MOVZ_I_D32 = 1905,
+ MOVZ_I_D32_MM = 1906,
+ MOVZ_I_D64 = 1907,
+ MOVZ_I_I = 1908,
+ MOVZ_I_I64 = 1909,
+ MOVZ_I_MM = 1910,
+ MOVZ_I_S = 1911,
+ MOVZ_I_S_MM = 1912,
+ MSUB = 1913,
+ MSUBF_D = 1914,
+ MSUBF_D_MMR6 = 1915,
+ MSUBF_S = 1916,
+ MSUBF_S_MMR6 = 1917,
+ MSUBR_Q_H = 1918,
+ MSUBR_Q_W = 1919,
+ MSUBU = 1920,
+ MSUBU_DSP = 1921,
+ MSUBU_DSP_MM = 1922,
+ MSUBU_MM = 1923,
+ MSUBV_B = 1924,
+ MSUBV_D = 1925,
+ MSUBV_H = 1926,
+ MSUBV_W = 1927,
+ MSUB_D32 = 1928,
+ MSUB_D32_MM = 1929,
+ MSUB_D64 = 1930,
+ MSUB_DSP = 1931,
+ MSUB_DSP_MM = 1932,
+ MSUB_MM = 1933,
+ MSUB_Q_H = 1934,
+ MSUB_Q_W = 1935,
+ MSUB_S = 1936,
+ MSUB_S_MM = 1937,
+ MTC0 = 1938,
+ MTC0_MMR6 = 1939,
+ MTC1 = 1940,
+ MTC1_D64 = 1941,
+ MTC1_MM = 1942,
+ MTC1_MMR6 = 1943,
+ MTC2 = 1944,
+ MTC2_MMR6 = 1945,
+ MTGC0 = 1946,
+ MTGC0_MM = 1947,
+ MTHC0_MMR6 = 1948,
+ MTHC1_D32 = 1949,
+ MTHC1_D32_MM = 1950,
+ MTHC1_D64 = 1951,
+ MTHC1_D64_MM = 1952,
+ MTHC2_MMR6 = 1953,
+ MTHGC0 = 1954,
+ MTHGC0_MM = 1955,
+ MTHI = 1956,
+ MTHI64 = 1957,
+ MTHI_DSP = 1958,
+ MTHI_DSP_MM = 1959,
+ MTHI_MM = 1960,
+ MTHLIP = 1961,
+ MTHLIP_MM = 1962,
+ MTLO = 1963,
+ MTLO64 = 1964,
+ MTLO_DSP = 1965,
+ MTLO_DSP_MM = 1966,
+ MTLO_MM = 1967,
+ MTM0 = 1968,
+ MTM1 = 1969,
+ MTM2 = 1970,
+ MTP0 = 1971,
+ MTP1 = 1972,
+ MTP2 = 1973,
+ MTTR = 1974,
+ MUH = 1975,
+ MUHU = 1976,
+ MUHU_MMR6 = 1977,
+ MUH_MMR6 = 1978,
+ MUL = 1979,
+ MULEQ_S_W_PHL = 1980,
+ MULEQ_S_W_PHL_MM = 1981,
+ MULEQ_S_W_PHR = 1982,
+ MULEQ_S_W_PHR_MM = 1983,
+ MULEU_S_PH_QBL = 1984,
+ MULEU_S_PH_QBL_MM = 1985,
+ MULEU_S_PH_QBR = 1986,
+ MULEU_S_PH_QBR_MM = 1987,
+ MULQ_RS_PH = 1988,
+ MULQ_RS_PH_MM = 1989,
+ MULQ_RS_W = 1990,
+ MULQ_RS_W_MMR2 = 1991,
+ MULQ_S_PH = 1992,
+ MULQ_S_PH_MMR2 = 1993,
+ MULQ_S_W = 1994,
+ MULQ_S_W_MMR2 = 1995,
+ MULR_Q_H = 1996,
+ MULR_Q_W = 1997,
+ MULSAQ_S_W_PH = 1998,
+ MULSAQ_S_W_PH_MM = 1999,
+ MULSA_W_PH = 2000,
+ MULSA_W_PH_MMR2 = 2001,
+ MULT = 2002,
+ MULTU_DSP = 2003,
+ MULTU_DSP_MM = 2004,
+ MULT_DSP = 2005,
+ MULT_DSP_MM = 2006,
+ MULT_MM = 2007,
+ MULTu = 2008,
+ MULTu_MM = 2009,
+ MULU = 2010,
+ MULU_MMR6 = 2011,
+ MULV_B = 2012,
+ MULV_D = 2013,
+ MULV_H = 2014,
+ MULV_W = 2015,
+ MUL_MM = 2016,
+ MUL_MMR6 = 2017,
+ MUL_PH = 2018,
+ MUL_PH_MMR2 = 2019,
+ MUL_Q_H = 2020,
+ MUL_Q_W = 2021,
+ MUL_R6 = 2022,
+ MUL_S_PH = 2023,
+ MUL_S_PH_MMR2 = 2024,
+ Mfhi16 = 2025,
+ Mflo16 = 2026,
+ Move32R16 = 2027,
+ MoveR3216 = 2028,
+ NLOC_B = 2029,
+ NLOC_D = 2030,
+ NLOC_H = 2031,
+ NLOC_W = 2032,
+ NLZC_B = 2033,
+ NLZC_D = 2034,
+ NLZC_H = 2035,
+ NLZC_W = 2036,
+ NMADD_D32 = 2037,
+ NMADD_D32_MM = 2038,
+ NMADD_D64 = 2039,
+ NMADD_S = 2040,
+ NMADD_S_MM = 2041,
+ NMSUB_D32 = 2042,
+ NMSUB_D32_MM = 2043,
+ NMSUB_D64 = 2044,
+ NMSUB_S = 2045,
+ NMSUB_S_MM = 2046,
+ NOR = 2047,
+ NOR64 = 2048,
+ NORI_B = 2049,
+ NOR_MM = 2050,
+ NOR_MMR6 = 2051,
+ NOR_V = 2052,
+ NOT16_MM = 2053,
+ NOT16_MMR6 = 2054,
+ NegRxRy16 = 2055,
+ NotRxRy16 = 2056,
+ OR = 2057,
+ OR16_MM = 2058,
+ OR16_MMR6 = 2059,
+ OR64 = 2060,
+ ORI_B = 2061,
+ ORI_MMR6 = 2062,
+ OR_MM = 2063,
+ OR_MMR6 = 2064,
+ OR_V = 2065,
+ ORi = 2066,
+ ORi64 = 2067,
+ ORi_MM = 2068,
+ OrRxRxRy16 = 2069,
+ PACKRL_PH = 2070,
+ PACKRL_PH_MM = 2071,
+ PAUSE = 2072,
+ PAUSE_MM = 2073,
+ PAUSE_MMR6 = 2074,
+ PCKEV_B = 2075,
+ PCKEV_D = 2076,
+ PCKEV_H = 2077,
+ PCKEV_W = 2078,
+ PCKOD_B = 2079,
+ PCKOD_D = 2080,
+ PCKOD_H = 2081,
+ PCKOD_W = 2082,
+ PCNT_B = 2083,
+ PCNT_D = 2084,
+ PCNT_H = 2085,
+ PCNT_W = 2086,
+ PICK_PH = 2087,
+ PICK_PH_MM = 2088,
+ PICK_QB = 2089,
+ PICK_QB_MM = 2090,
+ POP = 2091,
+ PRECEQU_PH_QBL = 2092,
+ PRECEQU_PH_QBLA = 2093,
+ PRECEQU_PH_QBLA_MM = 2094,
+ PRECEQU_PH_QBL_MM = 2095,
+ PRECEQU_PH_QBR = 2096,
+ PRECEQU_PH_QBRA = 2097,
+ PRECEQU_PH_QBRA_MM = 2098,
+ PRECEQU_PH_QBR_MM = 2099,
+ PRECEQ_W_PHL = 2100,
+ PRECEQ_W_PHL_MM = 2101,
+ PRECEQ_W_PHR = 2102,
+ PRECEQ_W_PHR_MM = 2103,
+ PRECEU_PH_QBL = 2104,
+ PRECEU_PH_QBLA = 2105,
+ PRECEU_PH_QBLA_MM = 2106,
+ PRECEU_PH_QBL_MM = 2107,
+ PRECEU_PH_QBR = 2108,
+ PRECEU_PH_QBRA = 2109,
+ PRECEU_PH_QBRA_MM = 2110,
+ PRECEU_PH_QBR_MM = 2111,
+ PRECRQU_S_QB_PH = 2112,
+ PRECRQU_S_QB_PH_MM = 2113,
+ PRECRQ_PH_W = 2114,
+ PRECRQ_PH_W_MM = 2115,
+ PRECRQ_QB_PH = 2116,
+ PRECRQ_QB_PH_MM = 2117,
+ PRECRQ_RS_PH_W = 2118,
+ PRECRQ_RS_PH_W_MM = 2119,
+ PRECR_QB_PH = 2120,
+ PRECR_QB_PH_MMR2 = 2121,
+ PRECR_SRA_PH_W = 2122,
+ PRECR_SRA_PH_W_MMR2 = 2123,
+ PRECR_SRA_R_PH_W = 2124,
+ PRECR_SRA_R_PH_W_MMR2 = 2125,
+ PREF = 2126,
+ PREFE = 2127,
+ PREFE_MM = 2128,
+ PREFX_MM = 2129,
+ PREF_MM = 2130,
+ PREF_MMR6 = 2131,
+ PREF_R6 = 2132,
+ PREPEND = 2133,
+ PREPEND_MMR2 = 2134,
+ RADDU_W_QB = 2135,
+ RADDU_W_QB_MM = 2136,
+ RDDSP = 2137,
+ RDDSP_MM = 2138,
+ RDHWR = 2139,
+ RDHWR64 = 2140,
+ RDHWR_MM = 2141,
+ RDHWR_MMR6 = 2142,
+ RDPGPR_MMR6 = 2143,
+ RECIP_D32 = 2144,
+ RECIP_D32_MM = 2145,
+ RECIP_D64 = 2146,
+ RECIP_D64_MM = 2147,
+ RECIP_S = 2148,
+ RECIP_S_MM = 2149,
+ REPLV_PH = 2150,
+ REPLV_PH_MM = 2151,
+ REPLV_QB = 2152,
+ REPLV_QB_MM = 2153,
+ REPL_PH = 2154,
+ REPL_PH_MM = 2155,
+ REPL_QB = 2156,
+ REPL_QB_MM = 2157,
+ RINT_D = 2158,
+ RINT_D_MMR6 = 2159,
+ RINT_S = 2160,
+ RINT_S_MMR6 = 2161,
+ ROTR = 2162,
+ ROTRV = 2163,
+ ROTRV_MM = 2164,
+ ROTR_MM = 2165,
+ ROUND_L_D64 = 2166,
+ ROUND_L_D_MMR6 = 2167,
+ ROUND_L_S = 2168,
+ ROUND_L_S_MMR6 = 2169,
+ ROUND_W_D32 = 2170,
+ ROUND_W_D64 = 2171,
+ ROUND_W_D_MMR6 = 2172,
+ ROUND_W_MM = 2173,
+ ROUND_W_S = 2174,
+ ROUND_W_S_MM = 2175,
+ ROUND_W_S_MMR6 = 2176,
+ RSQRT_D32 = 2177,
+ RSQRT_D32_MM = 2178,
+ RSQRT_D64 = 2179,
+ RSQRT_D64_MM = 2180,
+ RSQRT_S = 2181,
+ RSQRT_S_MM = 2182,
+ Restore16 = 2183,
+ RestoreX16 = 2184,
+ SAT_S_B = 2185,
+ SAT_S_D = 2186,
+ SAT_S_H = 2187,
+ SAT_S_W = 2188,
+ SAT_U_B = 2189,
+ SAT_U_D = 2190,
+ SAT_U_H = 2191,
+ SAT_U_W = 2192,
+ SB = 2193,
+ SB16_MM = 2194,
+ SB16_MMR6 = 2195,
+ SB64 = 2196,
+ SBE = 2197,
+ SBE_MM = 2198,
+ SB_MM = 2199,
+ SB_MMR6 = 2200,
+ SC = 2201,
+ SC64 = 2202,
+ SC64_R6 = 2203,
+ SCD = 2204,
+ SCD_R6 = 2205,
+ SCE = 2206,
+ SCE_MM = 2207,
+ SC_MM = 2208,
+ SC_MMR6 = 2209,
+ SC_R6 = 2210,
+ SD = 2211,
+ SDBBP = 2212,
+ SDBBP16_MM = 2213,
+ SDBBP16_MMR6 = 2214,
+ SDBBP_MM = 2215,
+ SDBBP_MMR6 = 2216,
+ SDBBP_R6 = 2217,
+ SDC1 = 2218,
+ SDC164 = 2219,
+ SDC1_D64_MMR6 = 2220,
+ SDC1_MM = 2221,
+ SDC2 = 2222,
+ SDC2_MMR6 = 2223,
+ SDC2_R6 = 2224,
+ SDC3 = 2225,
+ SDIV = 2226,
+ SDIV_MM = 2227,
+ SDL = 2228,
+ SDR = 2229,
+ SDXC1 = 2230,
+ SDXC164 = 2231,
+ SEB = 2232,
+ SEB64 = 2233,
+ SEB_MM = 2234,
+ SEH = 2235,
+ SEH64 = 2236,
+ SEH_MM = 2237,
+ SELEQZ = 2238,
+ SELEQZ64 = 2239,
+ SELEQZ_D = 2240,
+ SELEQZ_D_MMR6 = 2241,
+ SELEQZ_MMR6 = 2242,
+ SELEQZ_S = 2243,
+ SELEQZ_S_MMR6 = 2244,
+ SELNEZ = 2245,
+ SELNEZ64 = 2246,
+ SELNEZ_D = 2247,
+ SELNEZ_D_MMR6 = 2248,
+ SELNEZ_MMR6 = 2249,
+ SELNEZ_S = 2250,
+ SELNEZ_S_MMR6 = 2251,
+ SEL_D = 2252,
+ SEL_D_MMR6 = 2253,
+ SEL_S = 2254,
+ SEL_S_MMR6 = 2255,
+ SEQ = 2256,
+ SEQi = 2257,
+ SH = 2258,
+ SH16_MM = 2259,
+ SH16_MMR6 = 2260,
+ SH64 = 2261,
+ SHE = 2262,
+ SHE_MM = 2263,
+ SHF_B = 2264,
+ SHF_H = 2265,
+ SHF_W = 2266,
+ SHILO = 2267,
+ SHILOV = 2268,
+ SHILOV_MM = 2269,
+ SHILO_MM = 2270,
+ SHLLV_PH = 2271,
+ SHLLV_PH_MM = 2272,
+ SHLLV_QB = 2273,
+ SHLLV_QB_MM = 2274,
+ SHLLV_S_PH = 2275,
+ SHLLV_S_PH_MM = 2276,
+ SHLLV_S_W = 2277,
+ SHLLV_S_W_MM = 2278,
+ SHLL_PH = 2279,
+ SHLL_PH_MM = 2280,
+ SHLL_QB = 2281,
+ SHLL_QB_MM = 2282,
+ SHLL_S_PH = 2283,
+ SHLL_S_PH_MM = 2284,
+ SHLL_S_W = 2285,
+ SHLL_S_W_MM = 2286,
+ SHRAV_PH = 2287,
+ SHRAV_PH_MM = 2288,
+ SHRAV_QB = 2289,
+ SHRAV_QB_MMR2 = 2290,
+ SHRAV_R_PH = 2291,
+ SHRAV_R_PH_MM = 2292,
+ SHRAV_R_QB = 2293,
+ SHRAV_R_QB_MMR2 = 2294,
+ SHRAV_R_W = 2295,
+ SHRAV_R_W_MM = 2296,
+ SHRA_PH = 2297,
+ SHRA_PH_MM = 2298,
+ SHRA_QB = 2299,
+ SHRA_QB_MMR2 = 2300,
+ SHRA_R_PH = 2301,
+ SHRA_R_PH_MM = 2302,
+ SHRA_R_QB = 2303,
+ SHRA_R_QB_MMR2 = 2304,
+ SHRA_R_W = 2305,
+ SHRA_R_W_MM = 2306,
+ SHRLV_PH = 2307,
+ SHRLV_PH_MMR2 = 2308,
+ SHRLV_QB = 2309,
+ SHRLV_QB_MM = 2310,
+ SHRL_PH = 2311,
+ SHRL_PH_MMR2 = 2312,
+ SHRL_QB = 2313,
+ SHRL_QB_MM = 2314,
+ SH_MM = 2315,
+ SH_MMR6 = 2316,
+ SLDI_B = 2317,
+ SLDI_D = 2318,
+ SLDI_H = 2319,
+ SLDI_W = 2320,
+ SLD_B = 2321,
+ SLD_D = 2322,
+ SLD_H = 2323,
+ SLD_W = 2324,
+ SLL = 2325,
+ SLL16_MM = 2326,
+ SLL16_MMR6 = 2327,
+ SLL64_32 = 2328,
+ SLL64_64 = 2329,
+ SLLI_B = 2330,
+ SLLI_D = 2331,
+ SLLI_H = 2332,
+ SLLI_W = 2333,
+ SLLV = 2334,
+ SLLV_MM = 2335,
+ SLL_B = 2336,
+ SLL_D = 2337,
+ SLL_H = 2338,
+ SLL_MM = 2339,
+ SLL_MMR6 = 2340,
+ SLL_W = 2341,
+ SLT = 2342,
+ SLT64 = 2343,
+ SLT_MM = 2344,
+ SLTi = 2345,
+ SLTi64 = 2346,
+ SLTi_MM = 2347,
+ SLTiu = 2348,
+ SLTiu64 = 2349,
+ SLTiu_MM = 2350,
+ SLTu = 2351,
+ SLTu64 = 2352,
+ SLTu_MM = 2353,
+ SNE = 2354,
+ SNEi = 2355,
+ SPLATI_B = 2356,
+ SPLATI_D = 2357,
+ SPLATI_H = 2358,
+ SPLATI_W = 2359,
+ SPLAT_B = 2360,
+ SPLAT_D = 2361,
+ SPLAT_H = 2362,
+ SPLAT_W = 2363,
+ SRA = 2364,
+ SRAI_B = 2365,
+ SRAI_D = 2366,
+ SRAI_H = 2367,
+ SRAI_W = 2368,
+ SRARI_B = 2369,
+ SRARI_D = 2370,
+ SRARI_H = 2371,
+ SRARI_W = 2372,
+ SRAR_B = 2373,
+ SRAR_D = 2374,
+ SRAR_H = 2375,
+ SRAR_W = 2376,
+ SRAV = 2377,
+ SRAV_MM = 2378,
+ SRA_B = 2379,
+ SRA_D = 2380,
+ SRA_H = 2381,
+ SRA_MM = 2382,
+ SRA_W = 2383,
+ SRL = 2384,
+ SRL16_MM = 2385,
+ SRL16_MMR6 = 2386,
+ SRLI_B = 2387,
+ SRLI_D = 2388,
+ SRLI_H = 2389,
+ SRLI_W = 2390,
+ SRLRI_B = 2391,
+ SRLRI_D = 2392,
+ SRLRI_H = 2393,
+ SRLRI_W = 2394,
+ SRLR_B = 2395,
+ SRLR_D = 2396,
+ SRLR_H = 2397,
+ SRLR_W = 2398,
+ SRLV = 2399,
+ SRLV_MM = 2400,
+ SRL_B = 2401,
+ SRL_D = 2402,
+ SRL_H = 2403,
+ SRL_MM = 2404,
+ SRL_W = 2405,
+ SSNOP = 2406,
+ SSNOP_MM = 2407,
+ SSNOP_MMR6 = 2408,
+ ST_B = 2409,
+ ST_D = 2410,
+ ST_H = 2411,
+ ST_W = 2412,
+ SUB = 2413,
+ SUBQH_PH = 2414,
+ SUBQH_PH_MMR2 = 2415,
+ SUBQH_R_PH = 2416,
+ SUBQH_R_PH_MMR2 = 2417,
+ SUBQH_R_W = 2418,
+ SUBQH_R_W_MMR2 = 2419,
+ SUBQH_W = 2420,
+ SUBQH_W_MMR2 = 2421,
+ SUBQ_PH = 2422,
+ SUBQ_PH_MM = 2423,
+ SUBQ_S_PH = 2424,
+ SUBQ_S_PH_MM = 2425,
+ SUBQ_S_W = 2426,
+ SUBQ_S_W_MM = 2427,
+ SUBSUS_U_B = 2428,
+ SUBSUS_U_D = 2429,
+ SUBSUS_U_H = 2430,
+ SUBSUS_U_W = 2431,
+ SUBSUU_S_B = 2432,
+ SUBSUU_S_D = 2433,
+ SUBSUU_S_H = 2434,
+ SUBSUU_S_W = 2435,
+ SUBS_S_B = 2436,
+ SUBS_S_D = 2437,
+ SUBS_S_H = 2438,
+ SUBS_S_W = 2439,
+ SUBS_U_B = 2440,
+ SUBS_U_D = 2441,
+ SUBS_U_H = 2442,
+ SUBS_U_W = 2443,
+ SUBU16_MM = 2444,
+ SUBU16_MMR6 = 2445,
+ SUBUH_QB = 2446,
+ SUBUH_QB_MMR2 = 2447,
+ SUBUH_R_QB = 2448,
+ SUBUH_R_QB_MMR2 = 2449,
+ SUBU_MMR6 = 2450,
+ SUBU_PH = 2451,
+ SUBU_PH_MMR2 = 2452,
+ SUBU_QB = 2453,
+ SUBU_QB_MM = 2454,
+ SUBU_S_PH = 2455,
+ SUBU_S_PH_MMR2 = 2456,
+ SUBU_S_QB = 2457,
+ SUBU_S_QB_MM = 2458,
+ SUBVI_B = 2459,
+ SUBVI_D = 2460,
+ SUBVI_H = 2461,
+ SUBVI_W = 2462,
+ SUBV_B = 2463,
+ SUBV_D = 2464,
+ SUBV_H = 2465,
+ SUBV_W = 2466,
+ SUB_MM = 2467,
+ SUB_MMR6 = 2468,
+ SUBu = 2469,
+ SUBu_MM = 2470,
+ SUXC1 = 2471,
+ SUXC164 = 2472,
+ SUXC1_MM = 2473,
+ SW = 2474,
+ SW16_MM = 2475,
+ SW16_MMR6 = 2476,
+ SW64 = 2477,
+ SWC1 = 2478,
+ SWC1_MM = 2479,
+ SWC2 = 2480,
+ SWC2_MMR6 = 2481,
+ SWC2_R6 = 2482,
+ SWC3 = 2483,
+ SWDSP = 2484,
+ SWDSP_MM = 2485,
+ SWE = 2486,
+ SWE_MM = 2487,
+ SWL = 2488,
+ SWL64 = 2489,
+ SWLE = 2490,
+ SWLE_MM = 2491,
+ SWL_MM = 2492,
+ SWM16_MM = 2493,
+ SWM16_MMR6 = 2494,
+ SWM32_MM = 2495,
+ SWP_MM = 2496,
+ SWR = 2497,
+ SWR64 = 2498,
+ SWRE = 2499,
+ SWRE_MM = 2500,
+ SWR_MM = 2501,
+ SWSP_MM = 2502,
+ SWSP_MMR6 = 2503,
+ SWXC1 = 2504,
+ SWXC1_MM = 2505,
+ SW_MM = 2506,
+ SW_MMR6 = 2507,
+ SYNC = 2508,
+ SYNCI = 2509,
+ SYNCI_MM = 2510,
+ SYNCI_MMR6 = 2511,
+ SYNC_MM = 2512,
+ SYNC_MMR6 = 2513,
+ SYSCALL = 2514,
+ SYSCALL_MM = 2515,
+ Save16 = 2516,
+ SaveX16 = 2517,
+ SbRxRyOffMemX16 = 2518,
+ SebRx16 = 2519,
+ SehRx16 = 2520,
+ ShRxRyOffMemX16 = 2521,
+ SllX16 = 2522,
+ SllvRxRy16 = 2523,
+ SltRxRy16 = 2524,
+ SltiRxImm16 = 2525,
+ SltiRxImmX16 = 2526,
+ SltiuRxImm16 = 2527,
+ SltiuRxImmX16 = 2528,
+ SltuRxRy16 = 2529,
+ SraX16 = 2530,
+ SravRxRy16 = 2531,
+ SrlX16 = 2532,
+ SrlvRxRy16 = 2533,
+ SubuRxRyRz16 = 2534,
+ SwRxRyOffMemX16 = 2535,
+ SwRxSpImmX16 = 2536,
+ TEQ = 2537,
+ TEQI = 2538,
+ TEQI_MM = 2539,
+ TEQ_MM = 2540,
+ TGE = 2541,
+ TGEI = 2542,
+ TGEIU = 2543,
+ TGEIU_MM = 2544,
+ TGEI_MM = 2545,
+ TGEU = 2546,
+ TGEU_MM = 2547,
+ TGE_MM = 2548,
+ TLBGINV = 2549,
+ TLBGINVF = 2550,
+ TLBGINVF_MM = 2551,
+ TLBGINV_MM = 2552,
+ TLBGP = 2553,
+ TLBGP_MM = 2554,
+ TLBGR = 2555,
+ TLBGR_MM = 2556,
+ TLBGWI = 2557,
+ TLBGWI_MM = 2558,
+ TLBGWR = 2559,
+ TLBGWR_MM = 2560,
+ TLBINV = 2561,
+ TLBINVF = 2562,
+ TLBINVF_MMR6 = 2563,
+ TLBINV_MMR6 = 2564,
+ TLBP = 2565,
+ TLBP_MM = 2566,
+ TLBR = 2567,
+ TLBR_MM = 2568,
+ TLBWI = 2569,
+ TLBWI_MM = 2570,
+ TLBWR = 2571,
+ TLBWR_MM = 2572,
+ TLT = 2573,
+ TLTI = 2574,
+ TLTIU_MM = 2575,
+ TLTI_MM = 2576,
+ TLTU = 2577,
+ TLTU_MM = 2578,
+ TLT_MM = 2579,
+ TNE = 2580,
+ TNEI = 2581,
+ TNEI_MM = 2582,
+ TNE_MM = 2583,
+ TRUNC_L_D64 = 2584,
+ TRUNC_L_D_MMR6 = 2585,
+ TRUNC_L_S = 2586,
+ TRUNC_L_S_MMR6 = 2587,
+ TRUNC_W_D32 = 2588,
+ TRUNC_W_D64 = 2589,
+ TRUNC_W_D_MMR6 = 2590,
+ TRUNC_W_MM = 2591,
+ TRUNC_W_S = 2592,
+ TRUNC_W_S_MM = 2593,
+ TRUNC_W_S_MMR6 = 2594,
+ TTLTIU = 2595,
+ UDIV = 2596,
+ UDIV_MM = 2597,
+ V3MULU = 2598,
+ VMM0 = 2599,
+ VMULU = 2600,
+ VSHF_B = 2601,
+ VSHF_D = 2602,
+ VSHF_H = 2603,
+ VSHF_W = 2604,
+ WAIT = 2605,
+ WAIT_MM = 2606,
+ WAIT_MMR6 = 2607,
+ WRDSP = 2608,
+ WRDSP_MM = 2609,
+ WRPGPR_MMR6 = 2610,
+ WSBH = 2611,
+ WSBH_MM = 2612,
+ WSBH_MMR6 = 2613,
+ XOR = 2614,
+ XOR16_MM = 2615,
+ XOR16_MMR6 = 2616,
+ XOR64 = 2617,
+ XORI_B = 2618,
+ XORI_MMR6 = 2619,
+ XOR_MM = 2620,
+ XOR_MMR6 = 2621,
+ XOR_V = 2622,
+ XORi = 2623,
+ XORi64 = 2624,
+ XORi_MM = 2625,
+ XorRxRxRy16 = 2626,
+ YIELD = 2627,
+ INSTRUCTION_LIST_END = 2628
+ };
+
+} // end Mips namespace
+} // end llvm namespace
+#endif // GET_INSTRINFO_ENUM
+
+#ifdef GET_INSTRINFO_SCHED_ENUM
+#undef GET_INSTRINFO_SCHED_ENUM
+namespace llvm {
+
+namespace Mips {
+namespace Sched {
+ enum {
+ NoInstrModel = 0,
+ IIPseudo = 1,
+ II_B = 2,
+ II_BCCZAL = 3,
+ II_MTC1 = 4,
+ II_MFC1 = 5,
+ II_JALR = 6,
+ II_CVT = 7,
+ II_DMULT = 8,
+ II_DMULTU = 9,
+ II_DDIV = 10,
+ II_DDIVU = 11,
+ II_IndirectBranchPseudo = 12,
+ II_MADD = 13,
+ II_MADDU = 14,
+ II_MFHI_MFLO = 15,
+ II_MSUB = 16,
+ II_MSUBU = 17,
+ II_MTHI_MTLO = 18,
+ II_MULT = 19,
+ II_MULTU = 20,
+ II_ReturnPseudo = 21,
+ II_DIV = 22,
+ II_DIVU = 23,
+ II_J = 24,
+ II_JR = 25,
+ II_TRAP = 26,
+ II_ADD = 27,
+ II_ADDIUPC = 28,
+ II_ADDIU = 29,
+ II_ADDU = 30,
+ II_ADDI = 31,
+ II_ALIGN = 32,
+ II_ALUIPC = 33,
+ II_AND = 34,
+ II_ANDI = 35,
+ II_AUI = 36,
+ II_AUIPC = 37,
+ IIM16Alu = 38,
+ II_BADDU = 39,
+ II_BC = 40,
+ II_BALC = 41,
+ II_BBIT = 42,
+ II_BC1CCZ = 43,
+ II_BC1F = 44,
+ II_BC1FL = 45,
+ II_BC1T = 46,
+ II_BC1TL = 47,
+ II_BC2CCZ = 48,
+ II_BCC = 49,
+ II_BCCC = 50,
+ II_BCCZ = 51,
+ II_BCCZC = 52,
+ II_BCCZALS = 53,
+ II_BITSWAP = 54,
+ II_BREAK = 55,
+ II_CACHE = 56,
+ II_CACHEE = 57,
+ II_CEIL = 58,
+ II_CFC1 = 59,
+ II_CFC2 = 60,
+ II_INS = 61,
+ II_CLASS_D = 62,
+ II_CLASS_S = 63,
+ II_CLO = 64,
+ II_CLZ = 65,
+ II_CMP_CC_D = 66,
+ II_CMP_CC_S = 67,
+ II_CRC32B = 68,
+ II_CRC32CB = 69,
+ II_CRC32CD = 70,
+ II_CRC32CH = 71,
+ II_CRC32CW = 72,
+ II_CRC32D = 73,
+ II_CRC32H = 74,
+ II_CRC32W = 75,
+ II_CTC1 = 76,
+ II_CTC2 = 77,
+ II_C_CC_D = 78,
+ II_C_CC_S = 79,
+ II_DADD = 80,
+ II_DADDI = 81,
+ II_DADDIU = 82,
+ II_DADDU = 83,
+ II_DAHI = 84,
+ II_DALIGN = 85,
+ II_DATI = 86,
+ II_DAUI = 87,
+ II_DBITSWAP = 88,
+ II_DCLO = 89,
+ II_DCLZ = 90,
+ II_DERET = 91,
+ II_EXT = 92,
+ II_DI = 93,
+ II_DLSA = 94,
+ II_DMFC0 = 95,
+ II_DMFC1 = 96,
+ II_DMFC2 = 97,
+ II_DMFGC0 = 98,
+ II_DMOD = 99,
+ II_DMODU = 100,
+ II_DMT = 101,
+ II_DMTC0 = 102,
+ II_DMTC1 = 103,
+ II_DMTC2 = 104,
+ II_DMTGC0 = 105,
+ II_DMUH = 106,
+ II_DMUHU = 107,
+ II_DMUL = 108,
+ II_POP = 109,
+ II_DROTR = 110,
+ II_DROTR32 = 111,
+ II_DROTRV = 112,
+ II_DSBH = 113,
+ II_DSHD = 114,
+ II_DSLL = 115,
+ II_DSLL32 = 116,
+ II_DSLLV = 117,
+ II_DSRA = 118,
+ II_DSRA32 = 119,
+ II_DSRAV = 120,
+ II_DSRL = 121,
+ II_DSRL32 = 122,
+ II_DSRLV = 123,
+ II_DSUB = 124,
+ II_DSUBU = 125,
+ II_DVP = 126,
+ II_DVPE = 127,
+ II_EHB = 128,
+ II_EI = 129,
+ II_EMT = 130,
+ II_ERET = 131,
+ II_ERETNC = 132,
+ II_EVP = 133,
+ II_EVPE = 134,
+ II_ABS = 135,
+ II_SQRT_D = 136,
+ II_ADD_D = 137,
+ II_ADD_S = 138,
+ II_DIV_D = 139,
+ II_DIV_S = 140,
+ II_FLOOR = 141,
+ II_MOV_D = 142,
+ II_MOV_S = 143,
+ II_MUL_D = 144,
+ II_MUL_S = 145,
+ II_NEG = 146,
+ II_FORK = 147,
+ II_SQRT_S = 148,
+ II_SUB_D = 149,
+ II_SUB_S = 150,
+ II_GINVI = 151,
+ II_GINVT = 152,
+ II_HYPCALL = 153,
+ II_JAL = 154,
+ II_JALR_HB = 155,
+ II_JALRC = 156,
+ II_JALRS = 157,
+ II_JALS = 158,
+ II_JIALC = 159,
+ II_JIC = 160,
+ II_JRADDIUSP = 161,
+ II_JRC = 162,
+ II_JR_HB = 163,
+ II_LB = 164,
+ II_LBE = 165,
+ II_LBU = 166,
+ II_LBUE = 167,
+ II_LD = 168,
+ II_LDC1 = 169,
+ II_LDC2 = 170,
+ II_LDC3 = 171,
+ II_LDL = 172,
+ II_LDPC = 173,
+ II_LDR = 174,
+ II_LDXC1 = 175,
+ II_LH = 176,
+ II_LHE = 177,
+ II_LHU = 178,
+ II_LHUE = 179,
+ II_LI = 180,
+ II_LL = 181,
+ II_LLD = 182,
+ II_LLE = 183,
+ II_LSA = 184,
+ II_LUI = 185,
+ II_LUXC1 = 186,
+ II_LW = 187,
+ II_LWC1 = 188,
+ II_LWC2 = 189,
+ II_LWC3 = 190,
+ II_LWE = 191,
+ II_LWL = 192,
+ II_LWLE = 193,
+ II_LWM = 194,
+ II_LWPC = 195,
+ II_LWP = 196,
+ II_LWR = 197,
+ II_LWRE = 198,
+ II_LWUPC = 199,
+ II_LWU = 200,
+ II_LWXC1 = 201,
+ II_LWXS = 202,
+ II_MADDF_D = 203,
+ II_MADDF_S = 204,
+ II_MADD_D = 205,
+ II_MADD_S = 206,
+ II_MAX_D = 207,
+ II_MAXA_D = 208,
+ II_MAX_S = 209,
+ II_MAXA_S = 210,
+ II_MFC0 = 211,
+ II_MFC2 = 212,
+ II_MFGC0 = 213,
+ II_MFHC0 = 214,
+ II_MFHC1 = 215,
+ II_MFHGC0 = 216,
+ II_MFTR = 217,
+ II_MIN_S = 218,
+ II_MINA_D = 219,
+ II_MIN_D = 220,
+ II_MINA_S = 221,
+ II_MOD = 222,
+ II_MODU = 223,
+ II_MOVE = 224,
+ II_MOVF_D = 225,
+ II_MOVF = 226,
+ II_MOVF_S = 227,
+ II_MOVN_D = 228,
+ II_MOVN = 229,
+ II_MOVN_S = 230,
+ II_MOVT_D = 231,
+ II_MOVT = 232,
+ II_MOVT_S = 233,
+ II_MOVZ_D = 234,
+ II_MOVZ = 235,
+ II_MOVZ_S = 236,
+ II_MSUBF_D = 237,
+ II_MSUBF_S = 238,
+ II_MSUB_D = 239,
+ II_MSUB_S = 240,
+ II_MTC0 = 241,
+ II_MTC2 = 242,
+ II_MTGC0 = 243,
+ II_MTHC0 = 244,
+ II_MTHC1 = 245,
+ II_MTHGC0 = 246,
+ II_MTTR = 247,
+ II_MUH = 248,
+ II_MUHU = 249,
+ II_MUL = 250,
+ II_MULU = 251,
+ II_NMADD_D = 252,
+ II_NMADD_S = 253,
+ II_NMSUB_D = 254,
+ II_NMSUB_S = 255,
+ II_NOR = 256,
+ II_NOT = 257,
+ II_OR = 258,
+ II_ORI = 259,
+ II_PAUSE = 260,
+ II_PREF = 261,
+ II_PREFE = 262,
+ II_RDHWR = 263,
+ II_RDPGPR = 264,
+ II_RECIP_D = 265,
+ II_RECIP_S = 266,
+ II_RINT_D = 267,
+ II_RINT_S = 268,
+ II_ROTR = 269,
+ II_ROTRV = 270,
+ II_ROUND = 271,
+ II_RSQRT_D = 272,
+ II_RSQRT_S = 273,
+ II_RESTORE = 274,
+ II_SB = 275,
+ II_SBE = 276,
+ II_SC = 277,
+ II_SCD = 278,
+ II_SCE = 279,
+ II_SD = 280,
+ II_SDBBP = 281,
+ II_SDC1 = 282,
+ II_SDC2 = 283,
+ II_SDC3 = 284,
+ II_SDL = 285,
+ II_SDR = 286,
+ II_SDXC1 = 287,
+ II_SEB = 288,
+ II_SEH = 289,
+ II_SELCCZ = 290,
+ II_SELCCZ_D = 291,
+ II_SELCCZ_S = 292,
+ II_SEL_D = 293,
+ II_SEL_S = 294,
+ II_SEQ_SNE = 295,
+ II_SEQI_SNEI = 296,
+ II_SH = 297,
+ II_SHE = 298,
+ II_SLL = 299,
+ II_SLLV = 300,
+ II_SLT_SLTU = 301,
+ II_SLTI_SLTIU = 302,
+ II_SRA = 303,
+ II_SRAV = 304,
+ II_SRL = 305,
+ II_SRLV = 306,
+ II_SSNOP = 307,
+ II_SUB = 308,
+ II_SUBU = 309,
+ II_SUXC1 = 310,
+ II_SW = 311,
+ II_SWC1 = 312,
+ II_SWC2 = 313,
+ II_SWC3 = 314,
+ II_SWE = 315,
+ II_SWL = 316,
+ II_SWLE = 317,
+ II_SWM = 318,
+ II_SWP = 319,
+ II_SWR = 320,
+ II_SWRE = 321,
+ II_SWXC1 = 322,
+ II_SYNC = 323,
+ II_SYNCI = 324,
+ II_SYSCALL = 325,
+ II_SAVE = 326,
+ II_TEQ = 327,
+ II_TEQI = 328,
+ II_TGE = 329,
+ II_TGEI = 330,
+ II_TGEIU = 331,
+ II_TGEU = 332,
+ II_TLBGINV = 333,
+ II_TLBGINVF = 334,
+ II_TLBGP = 335,
+ II_TLBGR = 336,
+ II_TLBGWI = 337,
+ II_TLBGWR = 338,
+ II_TLBINV = 339,
+ II_TLBINVF = 340,
+ II_TLBP = 341,
+ II_TLBR = 342,
+ II_TLBWI = 343,
+ II_TLBWR = 344,
+ II_TLT = 345,
+ II_TLTI = 346,
+ II_TTLTIU = 347,
+ II_TLTU = 348,
+ II_TNE = 349,
+ II_TNEI = 350,
+ II_TRUNC = 351,
+ II_WAIT = 352,
+ II_WRPGPR = 353,
+ II_WSBH = 354,
+ II_XOR = 355,
+ II_XORI = 356,
+ II_YIELD = 357,
+ AND = 358,
+ LUi = 359,
+ NOR = 360,
+ OR = 361,
+ SLTi_SLTiu = 362,
+ SUB = 363,
+ SUBu = 364,
+ XOR = 365,
+ B = 366,
+ BAL = 367,
+ BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 368,
+ BEQ_BEQL_BNE_BNEL = 369,
+ BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 370,
+ BREAK = 371,
+ DERET = 372,
+ ERET = 373,
+ ERETNC = 374,
+ J_TAILCALL = 375,
+ JR_TAILCALLREG_TAILCALLREGHB = 376,
+ JR_HB = 377,
+ PseudoIndirectBranch_PseudoIndirectHazardBranch = 378,
+ PseudoReturn = 379,
+ SDBBP = 380,
+ SSNOP = 381,
+ SYSCALL = 382,
+ TEQ = 383,
+ TEQI = 384,
+ TGE = 385,
+ TGEI = 386,
+ TGEIU = 387,
+ TGEU = 388,
+ TLT = 389,
+ TLTI = 390,
+ TLTU = 391,
+ TNE = 392,
+ TNEI = 393,
+ TRAP = 394,
+ TTLTIU = 395,
+ WAIT = 396,
+ PAUSE = 397,
+ JAL = 398,
+ JALR_JALRHBPseudo_JALRPseudo = 399,
+ JALR_HB = 400,
+ JALX = 401,
+ TLBINV = 402,
+ TLBINVF = 403,
+ TLBP = 404,
+ TLBR = 405,
+ TLBWI = 406,
+ TLBWR = 407,
+ MFC0 = 408,
+ MTC0 = 409,
+ MFC2 = 410,
+ MTC2 = 411,
+ LB = 412,
+ LBu = 413,
+ LH = 414,
+ LHu = 415,
+ LW = 416,
+ LL = 417,
+ LWC2 = 418,
+ LWC3 = 419,
+ LDC2 = 420,
+ LDC3 = 421,
+ LBE = 422,
+ LBuE = 423,
+ LHE = 424,
+ LHuE = 425,
+ LWE = 426,
+ LLE = 427,
+ LWPC = 428,
+ LWL = 429,
+ LWR = 430,
+ LWLE = 431,
+ LWRE = 432,
+ SB = 433,
+ SH = 434,
+ SW = 435,
+ SWC2 = 436,
+ SWC3 = 437,
+ SDC2 = 438,
+ SDC3 = 439,
+ SC = 440,
+ SBE = 441,
+ SHE = 442,
+ SWE = 443,
+ SCE = 444,
+ SWL = 445,
+ SWR = 446,
+ SWLE = 447,
+ SWRE = 448,
+ PREF = 449,
+ PREFE = 450,
+ CACHE = 451,
+ CACHEE = 452,
+ SYNC = 453,
+ SYNCI = 454,
+ CLO = 455,
+ CLZ = 456,
+ DI = 457,
+ EI = 458,
+ MFHI_MFLO_PseudoMFHI_PseudoMFLO = 459,
+ EHB = 460,
+ RDHWR = 461,
+ WSBH = 462,
+ MOVN_I_I = 463,
+ MOVZ_I_I = 464,
+ DIV_PseudoSDIV_SDIV = 465,
+ DIVU_PseudoUDIV_UDIV = 466,
+ MUL = 467,
+ MULT_PseudoMULT = 468,
+ MULTu_PseudoMULTu = 469,
+ MADD_PseudoMADD = 470,
+ MADDU_PseudoMADDU = 471,
+ MSUB_PseudoMSUB = 472,
+ MSUBU_PseudoMSUBU = 473,
+ MTHI_MTLO_PseudoMTLOHI = 474,
+ EXT = 475,
+ INS = 476,
+ ADD = 477,
+ ADDi = 478,
+ ADDiu = 479,
+ ANDi = 480,
+ ORi = 481,
+ ROTR = 482,
+ SEB = 483,
+ SEH = 484,
+ SLT_SLTu = 485,
+ SLL = 486,
+ SRA = 487,
+ SRL = 488,
+ XORi = 489,
+ ADDu = 490,
+ SLLV = 491,
+ SRAV = 492,
+ SRLV = 493,
+ LSA = 494,
+ COPY = 495,
+ VSHF_B_VSHF_D_VSHF_H_VSHF_W = 496,
+ BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 497,
+ BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 498,
+ INSERT_B_INSERT_D_INSERT_H_INSERT_W = 499,
+ SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 500,
+ BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 501,
+ BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 502,
+ BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 503,
+ BSELI_B_BSEL_V = 504,
+ BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 505,
+ PCNT_B_PCNT_D_PCNT_H_PCNT_W = 506,
+ SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 507,
+ BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 508,
+ CFCMSA_CTCMSA = 509,
+ FABS_S_FABS_D32_FABS_D64 = 510,
+ MOVF_D32_MOVF_D64 = 511,
+ MOVF_S = 512,
+ MOVT_D32_MOVT_D64 = 513,
+ MOVT_S = 514,
+ FMOV_D32_FMOV_D64 = 515,
+ FMOV_S = 516,
+ FNEG_S_FNEG_D32_FNEG_D64 = 517,
+ ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 518,
+ ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 519,
+ ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 520,
+ ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 521,
+ AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 522,
+ SHF_B_SHF_H_SHF_W = 523,
+ FILL_B_FILL_D_FILL_H_FILL_W = 524,
+ SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 525,
+ MOVE_V = 526,
+ LDI_B_LDI_D_LDI_H_LDI_W = 527,
+ AND_V_NOR_V_OR_V_XOR_V = 528,
+ ANDI_B_NORI_B_ORI_B_XORI_B = 529,
+ FEXP2_D_FEXP2_W = 530,
+ CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 531,
+ CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 532,
+ CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 533,
+ CMP_UN_D = 534,
+ CMP_UN_S = 535,
+ CMP_UEQ_D = 536,
+ CMP_UEQ_S = 537,
+ CMP_EQ_D = 538,
+ CMP_EQ_S = 539,
+ CMP_LT_D = 540,
+ CMP_LT_S = 541,
+ CMP_ULT_D = 542,
+ CMP_ULT_S = 543,
+ CMP_LE_D = 544,
+ CMP_LE_S = 545,
+ CMP_ULE_D = 546,
+ CMP_ULE_S = 547,
+ FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 548,
+ FSUEQ_D_FSUEQ_W = 549,
+ FSULE_D_FSULE_W = 550,
+ FSULT_D_FSULT_W = 551,
+ FSUNE_D_FSUNE_W = 552,
+ FSUN_D_FSUN_W = 553,
+ FCAF_D_FCAF_W = 554,
+ FCEQ_D_FCEQ_W = 555,
+ FCLE_D_FCLE_W = 556,
+ FCLT_D_FCLT_W = 557,
+ FCNE_D_FCNE_W = 558,
+ FCOR_D_FCOR_W = 559,
+ FCUEQ_D_FCUEQ_W = 560,
+ FCULE_D_FCULE_W = 561,
+ FCULT_D_FCULT_W = 562,
+ FCUNE_D_FCUNE_W = 563,
+ FCUN_D_FCUN_W = 564,
+ FABS_D_FABS_W = 565,
+ FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 566,
+ FFQL_D_FFQL_W = 567,
+ FFQR_D_FFQR_W = 568,
+ FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 569,
+ FRINT_D_FRINT_W = 570,
+ FTQ_H_FTQ_W = 571,
+ FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 572,
+ FEXDO_H_FEXDO_W = 573,
+ FEXUPL_D_FEXUPL_W = 574,
+ FEXUPR_D_FEXUPR_W = 575,
+ FCLASS_D_FCLASS_W = 576,
+ FMAX_A_D_FMAX_A_W = 577,
+ FMAX_D_FMAX_W = 578,
+ FMIN_A_D_FMIN_A_W = 579,
+ FMIN_D_FMIN_W = 580,
+ FLOG2_D_FLOG2_W = 581,
+ ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 582,
+ ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 583,
+ INSVE_B_INSVE_D_INSVE_H_INSVE_W = 584,
+ SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 585,
+ SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 586,
+ SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 587,
+ SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 588,
+ SUBV_B_SUBV_D_SUBV_H_SUBV_W = 589,
+ MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 590,
+ DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 591,
+ HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 592,
+ HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 593,
+ MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 594,
+ MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 595,
+ MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 596,
+ MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 597,
+ SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 598,
+ SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 599,
+ SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 600,
+ SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 601,
+ SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 602,
+ PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 603,
+ NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 604,
+ FADD_D32_FADD_D64 = 605,
+ FADD_S = 606,
+ FMUL_D32_FMUL_D64 = 607,
+ FMUL_S = 608,
+ FSUB_D32_FSUB_D64 = 609,
+ FSUB_S = 610,
+ TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 611,
+ CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 612,
+ C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 613,
+ C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 614,
+ FCMP_D32_FCMP_D64 = 615,
+ FCMP_S32 = 616,
+ PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 617,
+ FDIV_S = 618,
+ FDIV_D32_FDIV_D64 = 619,
+ FSQRT_S = 620,
+ FSQRT_D32_FSQRT_D64 = 621,
+ FRCP_D_FRCP_W = 622,
+ FRSQRT_D_FRSQRT_W = 623,
+ RECIP_D32_RECIP_D64 = 624,
+ RSQRT_D32_RSQRT_D64 = 625,
+ RECIP_S = 626,
+ RSQRT_S = 627,
+ FMADD_D_FMADD_W = 628,
+ FMSUB_D_FMSUB_W = 629,
+ FDIV_W = 630,
+ FDIV_D = 631,
+ FSQRT_W = 632,
+ FSQRT_D = 633,
+ FMUL_D_FMUL_W = 634,
+ FADD_D_FADD_W = 635,
+ FSUB_D_FSUB_W = 636,
+ DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 637,
+ DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 638,
+ DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 639,
+ MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 640,
+ MADDV_B_MADDV_D_MADDV_H_MADDV_W = 641,
+ MULV_B_MULV_D_MULV_H_MULV_W = 642,
+ MADDR_Q_H_MADDR_Q_W = 643,
+ MADD_Q_H_MADD_Q_W = 644,
+ MSUBR_Q_H_MSUBR_Q_W = 645,
+ MSUB_Q_H_MSUB_Q_W = 646,
+ MULR_Q_H_MULR_Q_W = 647,
+ MUL_Q_H_MUL_Q_W = 648,
+ MADD_D32_MADD_D64 = 649,
+ MADD_S = 650,
+ MSUB_D32_MSUB_D64 = 651,
+ MSUB_S = 652,
+ NMADD_D32_NMADD_D64 = 653,
+ NMADD_S = 654,
+ NMSUB_D32_NMSUB_D64 = 655,
+ NMSUB_S = 656,
+ CTC1 = 657,
+ MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 658,
+ MTHC1_D32_MTHC1_D64 = 659,
+ COPY_U_B_COPY_U_H_COPY_U_W = 660,
+ COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 661,
+ BC1F = 662,
+ BC1FL = 663,
+ BC1T = 664,
+ BC1TL = 665,
+ CFC1 = 666,
+ MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 667,
+ MFHC1_D32_MFHC1_D64 = 668,
+ MOVF_I = 669,
+ MOVT_I = 670,
+ SDC1 = 671,
+ SDXC1 = 672,
+ SUXC1 = 673,
+ SWC1 = 674,
+ SWXC1 = 675,
+ ST_B_ST_D_ST_H_ST_W = 676,
+ MOVN_I_D32_MOVN_I_D64 = 677,
+ MOVN_I_S = 678,
+ MOVZ_I_D32_MOVZ_I_D64 = 679,
+ MOVZ_I_S = 680,
+ LDC1 = 681,
+ LDXC1 = 682,
+ LWC1 = 683,
+ LWXC1 = 684,
+ LUXC1 = 685,
+ LD_B_LD_D_LD_H_LD_W = 686,
+ CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 687,
+ FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 688,
+ ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 689,
+ ROTRV = 690,
+ EXTRV_RS_W = 691,
+ EXTRV_R_W = 692,
+ EXTRV_S_H = 693,
+ EXTRV_W = 694,
+ EXTR_RS_W = 695,
+ EXTR_R_W = 696,
+ EXTR_S_H = 697,
+ EXTR_W = 698,
+ INSV = 699,
+ MTHLIP = 700,
+ MTHI_DSP = 701,
+ MTLO_DSP = 702,
+ ABSQ_S_PH = 703,
+ ABSQ_S_W = 704,
+ ADDQ_PH = 705,
+ ADDQ_S_PH = 706,
+ ADDQ_S_W = 707,
+ ADDSC = 708,
+ ADDU_QB = 709,
+ ADDU_S_QB = 710,
+ ADDWC = 711,
+ BITREV = 712,
+ BPOSGE32 = 713,
+ CMPGU_EQ_QB = 714,
+ CMPGU_LE_QB = 715,
+ CMPGU_LT_QB = 716,
+ CMPU_EQ_QB = 717,
+ CMPU_LE_QB = 718,
+ CMPU_LT_QB = 719,
+ CMP_EQ_PH = 720,
+ CMP_LE_PH = 721,
+ CMP_LT_PH = 722,
+ DPAQ_SA_L_W = 723,
+ DPAQ_S_W_PH = 724,
+ DPAU_H_QBL = 725,
+ DPAU_H_QBR = 726,
+ DPSQ_SA_L_W = 727,
+ DPSQ_S_W_PH = 728,
+ DPSU_H_QBL = 729,
+ DPSU_H_QBR = 730,
+ EXTPDPV = 731,
+ EXTPDP = 732,
+ EXTPV = 733,
+ EXTP = 734,
+ LBUX = 735,
+ LHX = 736,
+ LWX = 737,
+ MADDU_DSP = 738,
+ MADD_DSP = 739,
+ MAQ_SA_W_PHL = 740,
+ MAQ_SA_W_PHR = 741,
+ MAQ_S_W_PHL = 742,
+ MAQ_S_W_PHR = 743,
+ MFHI_DSP = 744,
+ MFLO_DSP = 745,
+ MODSUB = 746,
+ MSUBU_DSP = 747,
+ MSUB_DSP = 748,
+ MULEQ_S_W_PHL = 749,
+ MULEQ_S_W_PHR = 750,
+ MULEU_S_PH_QBL = 751,
+ MULEU_S_PH_QBR = 752,
+ MULQ_RS_PH = 753,
+ MULSAQ_S_W_PH = 754,
+ MULTU_DSP = 755,
+ MULT_DSP = 756,
+ PACKRL_PH = 757,
+ PICK_PH = 758,
+ PICK_QB = 759,
+ PRECEQU_PH_QBLA = 760,
+ PRECEQU_PH_QBL = 761,
+ PRECEQU_PH_QBRA = 762,
+ PRECEQU_PH_QBR = 763,
+ PRECEQ_W_PHL = 764,
+ PRECEQ_W_PHR = 765,
+ PRECEU_PH_QBLA = 766,
+ PRECEU_PH_QBL = 767,
+ PRECEU_PH_QBRA = 768,
+ PRECEU_PH_QBR = 769,
+ PRECRQU_S_QB_PH = 770,
+ PRECRQ_PH_W = 771,
+ PRECRQ_QB_PH = 772,
+ PRECRQ_RS_PH_W = 773,
+ RADDU_W_QB = 774,
+ RDDSP = 775,
+ REPLV_PH = 776,
+ REPLV_QB = 777,
+ REPL_PH = 778,
+ REPL_QB = 779,
+ SHILOV = 780,
+ SHILO = 781,
+ SHLLV_PH = 782,
+ SHLLV_QB = 783,
+ SHLLV_S_PH = 784,
+ SHLLV_S_W = 785,
+ SHLL_PH = 786,
+ SHLL_QB = 787,
+ SHLL_S_PH = 788,
+ SHLL_S_W = 789,
+ SHRAV_PH = 790,
+ SHRAV_R_PH = 791,
+ SHRAV_R_W = 792,
+ SHRA_PH = 793,
+ SHRA_R_PH = 794,
+ SHRA_R_W = 795,
+ SHRLV_QB = 796,
+ SHRL_QB = 797,
+ SUBQ_PH = 798,
+ SUBQ_S_PH = 799,
+ SUBQ_S_W = 800,
+ SUBU_QB = 801,
+ SUBU_S_QB = 802,
+ WRDSP = 803,
+ ABSQ_S_QB = 804,
+ ADDQH_PH = 805,
+ ADDQH_R_PH = 806,
+ ADDQH_R_W = 807,
+ ADDQH_W = 808,
+ ADDUH_QB = 809,
+ ADDUH_R_QB = 810,
+ ADDU_PH = 811,
+ ADDU_S_PH = 812,
+ APPEND = 813,
+ BALIGN = 814,
+ CMPGDU_EQ_QB = 815,
+ CMPGDU_LE_QB = 816,
+ CMPGDU_LT_QB = 817,
+ DPA_W_PH = 818,
+ DPAQX_SA_W_PH = 819,
+ DPAQX_S_W_PH = 820,
+ DPAX_W_PH = 821,
+ DPS_W_PH = 822,
+ DPSQX_S_W_PH = 823,
+ DPSQX_SA_W_PH = 824,
+ DPSX_W_PH = 825,
+ MUL_PH = 826,
+ MUL_S_PH = 827,
+ MULQ_RS_W = 828,
+ MULQ_S_PH = 829,
+ MULQ_S_W = 830,
+ MULSA_W_PH = 831,
+ PRECR_QB_PH = 832,
+ PRECR_SRA_PH_W = 833,
+ PRECR_SRA_R_PH_W = 834,
+ PREPEND = 835,
+ SHRA_QB = 836,
+ SHRA_R_QB = 837,
+ SHRAV_QB = 838,
+ SHRAV_R_QB = 839,
+ SHRL_PH = 840,
+ SHRLV_PH = 841,
+ SUBQH_PH = 842,
+ SUBQH_R_PH = 843,
+ SUBQH_W = 844,
+ SUBQH_R_W = 845,
+ SUBU_PH = 846,
+ SUBU_S_PH = 847,
+ SUBUH_QB = 848,
+ SUBUH_R_QB = 849,
+ ABSQ_S_PH_MM = 850,
+ ABSQ_S_W_MM = 851,
+ ADDQ_PH_MM = 852,
+ ADDQ_S_PH_MM = 853,
+ ADDQ_S_W_MM = 854,
+ ADDSC_MM = 855,
+ ADDU_QB_MM = 856,
+ ADDU_S_QB_MM = 857,
+ ADDWC_MM = 858,
+ BITREV_MM = 859,
+ BPOSGE32_MM = 860,
+ CMPGU_EQ_QB_MM = 861,
+ CMPGU_LE_QB_MM = 862,
+ CMPGU_LT_QB_MM = 863,
+ CMPU_EQ_QB_MM = 864,
+ CMPU_LE_QB_MM = 865,
+ CMPU_LT_QB_MM = 866,
+ CMP_EQ_PH_MM = 867,
+ CMP_LE_PH_MM = 868,
+ CMP_LT_PH_MM = 869,
+ DPAQ_SA_L_W_MM = 870,
+ DPAQ_S_W_PH_MM = 871,
+ DPAU_H_QBL_MM = 872,
+ DPAU_H_QBR_MM = 873,
+ DPSQ_SA_L_W_MM = 874,
+ DPSQ_S_W_PH_MM = 875,
+ DPSU_H_QBL_MM = 876,
+ DPSU_H_QBR_MM = 877,
+ EXTPDPV_MM = 878,
+ EXTPDP_MM = 879,
+ EXTPV_MM = 880,
+ EXTP_MM = 881,
+ EXTRV_RS_W_MM = 882,
+ EXTRV_R_W_MM = 883,
+ EXTRV_S_H_MM = 884,
+ EXTRV_W_MM = 885,
+ EXTR_RS_W_MM = 886,
+ EXTR_R_W_MM = 887,
+ EXTR_S_H_MM = 888,
+ EXTR_W_MM = 889,
+ INSV_MM = 890,
+ LBUX_MM = 891,
+ LHX_MM = 892,
+ LWX_MM = 893,
+ MADDU_DSP_MM = 894,
+ MADD_DSP_MM = 895,
+ MAQ_SA_W_PHL_MM = 896,
+ MAQ_SA_W_PHR_MM = 897,
+ MAQ_S_W_PHL_MM = 898,
+ MAQ_S_W_PHR_MM = 899,
+ MFHI_DSP_MM = 900,
+ MFLO_DSP_MM = 901,
+ MODSUB_MM = 902,
+ MOVEP_MM = 903,
+ MOVEP_MMR6 = 904,
+ MOVN_I_MM = 905,
+ MOVZ_I_MM = 906,
+ MSUBU_DSP_MM = 907,
+ MSUB_DSP_MM = 908,
+ MTHI_DSP_MM = 909,
+ MTHLIP_MM = 910,
+ MTLO_DSP_MM = 911,
+ MULEQ_S_W_PHL_MM = 912,
+ MULEQ_S_W_PHR_MM = 913,
+ MULEU_S_PH_QBL_MM = 914,
+ MULEU_S_PH_QBR_MM = 915,
+ MULQ_RS_PH_MM = 916,
+ MULSAQ_S_W_PH_MM = 917,
+ MULTU_DSP_MM = 918,
+ MULT_DSP_MM = 919,
+ PACKRL_PH_MM = 920,
+ PICK_PH_MM = 921,
+ PICK_QB_MM = 922,
+ PRECEQU_PH_QBLA_MM = 923,
+ PRECEQU_PH_QBL_MM = 924,
+ PRECEQU_PH_QBRA_MM = 925,
+ PRECEQU_PH_QBR_MM = 926,
+ PRECEQ_W_PHL_MM = 927,
+ PRECEQ_W_PHR_MM = 928,
+ PRECEU_PH_QBLA_MM = 929,
+ PRECEU_PH_QBL_MM = 930,
+ PRECEU_PH_QBRA_MM = 931,
+ PRECEU_PH_QBR_MM = 932,
+ PRECRQU_S_QB_PH_MM = 933,
+ PRECRQ_PH_W_MM = 934,
+ PRECRQ_QB_PH_MM = 935,
+ PRECRQ_RS_PH_W_MM = 936,
+ RADDU_W_QB_MM = 937,
+ RDDSP_MM = 938,
+ REPLV_PH_MM = 939,
+ REPLV_QB_MM = 940,
+ REPL_PH_MM = 941,
+ REPL_QB_MM = 942,
+ SHILOV_MM = 943,
+ SHILO_MM = 944,
+ SHLLV_PH_MM = 945,
+ SHLLV_QB_MM = 946,
+ SHLLV_S_PH_MM = 947,
+ SHLLV_S_W_MM = 948,
+ SHLL_PH_MM = 949,
+ SHLL_QB_MM = 950,
+ SHLL_S_PH_MM = 951,
+ SHLL_S_W_MM = 952,
+ SHRAV_PH_MM = 953,
+ SHRAV_R_PH_MM = 954,
+ SHRAV_R_W_MM = 955,
+ SHRA_PH_MM = 956,
+ SHRA_R_PH_MM = 957,
+ SHRA_R_W_MM = 958,
+ SHRLV_QB_MM = 959,
+ SHRL_QB_MM = 960,
+ SUBQ_PH_MM = 961,
+ SUBQ_S_PH_MM = 962,
+ SUBQ_S_W_MM = 963,
+ SUBU_QB_MM = 964,
+ SUBU_S_QB_MM = 965,
+ WRDSP_MM = 966,
+ ABSQ_S_QB_MMR2 = 967,
+ ADDQH_PH_MMR2 = 968,
+ ADDQH_R_PH_MMR2 = 969,
+ ADDQH_R_W_MMR2 = 970,
+ ADDQH_W_MMR2 = 971,
+ ADDUH_QB_MMR2 = 972,
+ ADDUH_R_QB_MMR2 = 973,
+ ADDU_PH_MMR2 = 974,
+ ADDU_S_PH_MMR2 = 975,
+ APPEND_MMR2 = 976,
+ BALIGN_MMR2 = 977,
+ CMPGDU_EQ_QB_MMR2 = 978,
+ CMPGDU_LE_QB_MMR2 = 979,
+ CMPGDU_LT_QB_MMR2 = 980,
+ DPA_W_PH_MMR2 = 981,
+ DPAQX_SA_W_PH_MMR2 = 982,
+ DPAQX_S_W_PH_MMR2 = 983,
+ DPAX_W_PH_MMR2 = 984,
+ DPS_W_PH_MMR2 = 985,
+ DPSQX_S_W_PH_MMR2 = 986,
+ DPSQX_SA_W_PH_MMR2 = 987,
+ DPSX_W_PH_MMR2 = 988,
+ MUL_PH_MMR2 = 989,
+ MUL_S_PH_MMR2 = 990,
+ MULQ_RS_W_MMR2 = 991,
+ MULQ_S_PH_MMR2 = 992,
+ MULQ_S_W_MMR2 = 993,
+ MULSA_W_PH_MMR2 = 994,
+ PRECR_QB_PH_MMR2 = 995,
+ PRECR_SRA_PH_W_MMR2 = 996,
+ PRECR_SRA_R_PH_W_MMR2 = 997,
+ PREPEND_MMR2 = 998,
+ SHRA_QB_MMR2 = 999,
+ SHRA_R_QB_MMR2 = 1000,
+ SHRAV_QB_MMR2 = 1001,
+ SHRAV_R_QB_MMR2 = 1002,
+ SHRL_PH_MMR2 = 1003,
+ SHRLV_PH_MMR2 = 1004,
+ SUBQH_PH_MMR2 = 1005,
+ SUBQH_R_PH_MMR2 = 1006,
+ SUBQH_W_MMR2 = 1007,
+ SUBQH_R_W_MMR2 = 1008,
+ SUBU_PH_MMR2 = 1009,
+ SUBU_S_PH_MMR2 = 1010,
+ SUBUH_QB_MMR2 = 1011,
+ SUBUH_R_QB_MMR2 = 1012,
+ BPOSGE32C_MMR3 = 1013,
+ SCHED_LIST_END = 1014
+ };
+} // end Sched namespace
+} // end Mips namespace
+} // end llvm namespace
+#endif // GET_INSTRINFO_SCHED_ENUM
+
+#ifdef GET_INSTRINFO_MC_DESC
+#undef GET_INSTRINFO_MC_DESC
+namespace llvm {
+
+static const MCPhysReg ImplicitList1[] = { Mips::SP, 0 };
+static const MCPhysReg ImplicitList2[] = { Mips::AT, 0 };
+static const MCPhysReg ImplicitList3[] = { Mips::RA, 0 };
+static const MCPhysReg ImplicitList4[] = { Mips::DSPPos, 0 };
+static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1, 0 };
+static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0, 0 };
+static const MCPhysReg ImplicitList7[] = { Mips::T8, 0 };
+static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20, 0 };
+static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry, 0 };
+static const MCPhysReg ImplicitList10[] = { Mips::DSPCCond, 0 };
+static const MCPhysReg ImplicitList11[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, 0 };
+static const MCPhysReg ImplicitList12[] = { Mips::HI0_64, Mips::LO0_64, 0 };
+static const MCPhysReg ImplicitList13[] = { Mips::DSPOutFlag16_19, 0 };
+static const MCPhysReg ImplicitList14[] = { Mips::DSPEFI, 0 };
+static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI, 0 };
+static const MCPhysReg ImplicitList16[] = { Mips::DSPOutFlag23, 0 };
+static const MCPhysReg ImplicitList17[] = { Mips::FCC0, 0 };
+static const MCPhysReg ImplicitList18[] = { Mips::DSPPos, Mips::DSPSCount, 0 };
+static const MCPhysReg ImplicitList19[] = { Mips::AC0, 0 };
+static const MCPhysReg ImplicitList20[] = { Mips::AC0_64, 0 };
+static const MCPhysReg ImplicitList21[] = { Mips::HI0, 0 };
+static const MCPhysReg ImplicitList22[] = { Mips::HI0_64, 0 };
+static const MCPhysReg ImplicitList23[] = { Mips::LO0, 0 };
+static const MCPhysReg ImplicitList24[] = { Mips::LO0_64, 0 };
+static const MCPhysReg ImplicitList25[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, 0 };
+static const MCPhysReg ImplicitList26[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, 0 };
+static const MCPhysReg ImplicitList27[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
+static const MCPhysReg ImplicitList28[] = { Mips::P0, 0 };
+static const MCPhysReg ImplicitList29[] = { Mips::P1, 0 };
+static const MCPhysReg ImplicitList30[] = { Mips::P2, 0 };
+static const MCPhysReg ImplicitList31[] = { Mips::DSPOutFlag21, 0 };
+static const MCPhysReg ImplicitList32[] = { Mips::DSPOutFlag22, 0 };
+static const MCPhysReg ImplicitList33[] = { Mips::P0, Mips::P1, Mips::P2, 0 };
+static const MCPhysReg ImplicitList34[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 };
+
+static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo31[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo32[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo33[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo34[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo35[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo36[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo37[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo38[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo39[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo40[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo42[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo43[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo44[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo45[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo46[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo47[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo48[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo49[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo50[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo51[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo52[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo53[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo54[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo55[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo56[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo57[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo58[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo59[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo60[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo61[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo62[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo63[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo64[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo65[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo66[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo67[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo68[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo69[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo70[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo71[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo72[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo73[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo74[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo75[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo80[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo81[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo82[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo84[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo85[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo86[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo87[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo88[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo89[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo90[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo92[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo93[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo94[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo95[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo96[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo97[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo98[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo99[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo100[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo101[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo102[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo103[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo104[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo105[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo106[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo107[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo108[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo109[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo110[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo111[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo112[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo113[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo114[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo115[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo116[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo117[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo118[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo119[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo120[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo121[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo122[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo123[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo124[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo125[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo126[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo127[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo128[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo129[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo130[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo131[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo132[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo133[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo134[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo135[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo136[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo137[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo138[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo139[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo140[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo141[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo142[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo143[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo144[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo145[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo146[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo147[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo148[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo149[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo150[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo151[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo152[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo153[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo154[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo155[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo156[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo157[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo158[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo159[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo160[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo161[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo162[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo163[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo164[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo165[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo166[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo167[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo168[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo169[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo170[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo171[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo172[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo173[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo174[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo175[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo176[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo177[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo178[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo179[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo180[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo181[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo182[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo183[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo184[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo185[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo186[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo187[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo188[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo189[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo190[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo191[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo192[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo193[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo194[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo195[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo196[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo197[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo198[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo199[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo200[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo201[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo202[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo203[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo204[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo205[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo206[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo207[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo208[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo209[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo210[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo211[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo212[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo213[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo214[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo215[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo216[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo217[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo218[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo219[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo220[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo221[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo222[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo223[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo224[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo225[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo226[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo227[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo228[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo229[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo230[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo231[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo232[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo233[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo234[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo235[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo236[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo237[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo238[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo239[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo240[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo241[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo242[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo243[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo244[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo245[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo246[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo247[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo248[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo249[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo250[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo251[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo252[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo253[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo254[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo255[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo256[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo257[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo258[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo259[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo260[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo261[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo262[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo263[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo264[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo265[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo266[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo267[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo268[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo269[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo271[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo272[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo273[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo274[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo275[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo276[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo277[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo278[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo279[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo280[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo281[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo282[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo283[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo284[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo285[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo286[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo287[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo288[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo289[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo290[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo291[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo292[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo293[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo294[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo295[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo296[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo297[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo298[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo299[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo300[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo301[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo302[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo303[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo304[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo305[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo306[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo307[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo308[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo309[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo310[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo311[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo312[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo313[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo314[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo315[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo316[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo317[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo318[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo319[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo320[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo321[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo322[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo323[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo324[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo325[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo326[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo327[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo328[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo329[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo330[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo331[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo332[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo333[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo334[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo335[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo336[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo337[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo338[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo339[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo340[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo341[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo342[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+
+extern const MCInstrDesc MipsInsts[] = {
+ { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
+ { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
+ { 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2 = CFI_INSTRUCTION
+ { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = EH_LABEL
+ { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = GC_LABEL
+ { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = ANNOTATION_LABEL
+ { 6, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #6 = KILL
+ { 7, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #7 = EXTRACT_SUBREG
+ { 8, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #8 = INSERT_SUBREG
+ { 9, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #9 = IMPLICIT_DEF
+ { 10, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #10 = SUBREG_TO_REG
+ { 11, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #11 = COPY_TO_REGCLASS
+ { 12, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #12 = DBG_VALUE
+ { 13, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #13 = DBG_LABEL
+ { 14, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #14 = REG_SEQUENCE
+ { 15, 2, 1, 0, 495, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = COPY
+ { 16, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #16 = BUNDLE
+ { 17, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #17 = LIFETIME_START
+ { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_END
+ { 19, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #19 = STACKMAP
+ { 20, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #20 = FENTRY_CALL
+ { 21, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #21 = PATCHPOINT
+ { 22, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #22 = LOAD_STACK_GUARD
+ { 23, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #23 = STATEPOINT
+ { 24, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #24 = LOCAL_ESCAPE
+ { 25, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #25 = FAULTING_OP
+ { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = PATCHABLE_OP
+ { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_FUNCTION_ENTER
+ { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_RET
+ { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_FUNCTION_EXIT
+ { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_TAIL_CALL
+ { 31, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #31 = PATCHABLE_EVENT_CALL
+ { 32, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #32 = PATCHABLE_TYPED_EVENT_CALL
+ { 33, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #33 = ICALL_BRANCH_FUNNEL
+ { 34, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #34 = G_ADD
+ { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #35 = G_SUB
+ { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #36 = G_MUL
+ { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #37 = G_SDIV
+ { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #38 = G_UDIV
+ { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #39 = G_SREM
+ { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #40 = G_UREM
+ { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #41 = G_AND
+ { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #42 = G_OR
+ { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #43 = G_XOR
+ { 44, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = G_IMPLICIT_DEF
+ { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #45 = G_PHI
+ { 46, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #46 = G_FRAME_INDEX
+ { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #47 = G_GLOBAL_VALUE
+ { 48, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #48 = G_EXTRACT
+ { 49, 2, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #49 = G_UNMERGE_VALUES
+ { 50, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #50 = G_INSERT
+ { 51, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #51 = G_MERGE_VALUES
+ { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #52 = G_PTRTOINT
+ { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #53 = G_INTTOPTR
+ { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #54 = G_BITCAST
+ { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #55 = G_LOAD
+ { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #56 = G_SEXTLOAD
+ { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #57 = G_ZEXTLOAD
+ { 58, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #58 = G_STORE
+ { 59, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #59 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ { 60, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #60 = G_ATOMIC_CMPXCHG
+ { 61, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #61 = G_ATOMICRMW_XCHG
+ { 62, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #62 = G_ATOMICRMW_ADD
+ { 63, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #63 = G_ATOMICRMW_SUB
+ { 64, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #64 = G_ATOMICRMW_AND
+ { 65, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #65 = G_ATOMICRMW_NAND
+ { 66, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #66 = G_ATOMICRMW_OR
+ { 67, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #67 = G_ATOMICRMW_XOR
+ { 68, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #68 = G_ATOMICRMW_MAX
+ { 69, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #69 = G_ATOMICRMW_MIN
+ { 70, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #70 = G_ATOMICRMW_UMAX
+ { 71, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #71 = G_ATOMICRMW_UMIN
+ { 72, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #72 = G_BRCOND
+ { 73, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #73 = G_BRINDIRECT
+ { 74, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #74 = G_INTRINSIC
+ { 75, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #75 = G_INTRINSIC_W_SIDE_EFFECTS
+ { 76, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #76 = G_ANYEXT
+ { 77, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #77 = G_TRUNC
+ { 78, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #78 = G_CONSTANT
+ { 79, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #79 = G_FCONSTANT
+ { 80, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #80 = G_VASTART
+ { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #81 = G_VAARG
+ { 82, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #82 = G_SEXT
+ { 83, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #83 = G_ZEXT
+ { 84, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #84 = G_SHL
+ { 85, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #85 = G_LSHR
+ { 86, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #86 = G_ASHR
+ { 87, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #87 = G_ICMP
+ { 88, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #88 = G_FCMP
+ { 89, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #89 = G_SELECT
+ { 90, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #90 = G_UADDE
+ { 91, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #91 = G_USUBE
+ { 92, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #92 = G_SADDO
+ { 93, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #93 = G_SSUBO
+ { 94, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #94 = G_UMULO
+ { 95, 4, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #95 = G_SMULO
+ { 96, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #96 = G_UMULH
+ { 97, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #97 = G_SMULH
+ { 98, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #98 = G_FADD
+ { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #99 = G_FSUB
+ { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #100 = G_FMUL
+ { 101, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #101 = G_FMA
+ { 102, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #102 = G_FDIV
+ { 103, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #103 = G_FREM
+ { 104, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #104 = G_FPOW
+ { 105, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #105 = G_FEXP
+ { 106, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #106 = G_FEXP2
+ { 107, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #107 = G_FLOG
+ { 108, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #108 = G_FLOG2
+ { 109, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #109 = G_FNEG
+ { 110, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #110 = G_FPEXT
+ { 111, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #111 = G_FPTRUNC
+ { 112, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #112 = G_FPTOSI
+ { 113, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #113 = G_FPTOUI
+ { 114, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #114 = G_SITOFP
+ { 115, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #115 = G_UITOFP
+ { 116, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #116 = G_FABS
+ { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #117 = G_GEP
+ { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #118 = G_PTR_MASK
+ { 119, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #119 = G_BR
+ { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #120 = G_INSERT_VECTOR_ELT
+ { 121, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #121 = G_EXTRACT_VECTOR_ELT
+ { 122, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #122 = G_SHUFFLE_VECTOR
+ { 123, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #123 = G_BSWAP
+ { 124, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #124 = G_ADDRSPACE_CAST
+ { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #125 = G_BLOCK_ADDR
+ { 126, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #126 = ABSMacro
+ { 127, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #127 = ADJCALLSTACKDOWN
+ { 128, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #128 = ADJCALLSTACKUP
+ { 129, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #129 = AND_V_D_PSEUDO
+ { 130, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #130 = AND_V_H_PSEUDO
+ { 131, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #131 = AND_V_W_PSEUDO
+ { 132, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #132 = ATOMIC_CMP_SWAP_I16
+ { 133, 7, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #133 = ATOMIC_CMP_SWAP_I16_POSTRA
+ { 134, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #134 = ATOMIC_CMP_SWAP_I32
+ { 135, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #135 = ATOMIC_CMP_SWAP_I32_POSTRA
+ { 136, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #136 = ATOMIC_CMP_SWAP_I64
+ { 137, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #137 = ATOMIC_CMP_SWAP_I64_POSTRA
+ { 138, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #138 = ATOMIC_CMP_SWAP_I8
+ { 139, 7, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #139 = ATOMIC_CMP_SWAP_I8_POSTRA
+ { 140, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #140 = ATOMIC_LOAD_ADD_I16
+ { 141, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #141 = ATOMIC_LOAD_ADD_I16_POSTRA
+ { 142, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #142 = ATOMIC_LOAD_ADD_I32
+ { 143, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #143 = ATOMIC_LOAD_ADD_I32_POSTRA
+ { 144, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #144 = ATOMIC_LOAD_ADD_I64
+ { 145, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #145 = ATOMIC_LOAD_ADD_I64_POSTRA
+ { 146, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #146 = ATOMIC_LOAD_ADD_I8
+ { 147, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #147 = ATOMIC_LOAD_ADD_I8_POSTRA
+ { 148, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #148 = ATOMIC_LOAD_AND_I16
+ { 149, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #149 = ATOMIC_LOAD_AND_I16_POSTRA
+ { 150, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #150 = ATOMIC_LOAD_AND_I32
+ { 151, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #151 = ATOMIC_LOAD_AND_I32_POSTRA
+ { 152, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #152 = ATOMIC_LOAD_AND_I64
+ { 153, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #153 = ATOMIC_LOAD_AND_I64_POSTRA
+ { 154, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #154 = ATOMIC_LOAD_AND_I8
+ { 155, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #155 = ATOMIC_LOAD_AND_I8_POSTRA
+ { 156, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #156 = ATOMIC_LOAD_NAND_I16
+ { 157, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #157 = ATOMIC_LOAD_NAND_I16_POSTRA
+ { 158, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #158 = ATOMIC_LOAD_NAND_I32
+ { 159, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #159 = ATOMIC_LOAD_NAND_I32_POSTRA
+ { 160, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #160 = ATOMIC_LOAD_NAND_I64
+ { 161, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #161 = ATOMIC_LOAD_NAND_I64_POSTRA
+ { 162, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #162 = ATOMIC_LOAD_NAND_I8
+ { 163, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #163 = ATOMIC_LOAD_NAND_I8_POSTRA
+ { 164, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #164 = ATOMIC_LOAD_OR_I16
+ { 165, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #165 = ATOMIC_LOAD_OR_I16_POSTRA
+ { 166, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #166 = ATOMIC_LOAD_OR_I32
+ { 167, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #167 = ATOMIC_LOAD_OR_I32_POSTRA
+ { 168, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #168 = ATOMIC_LOAD_OR_I64
+ { 169, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #169 = ATOMIC_LOAD_OR_I64_POSTRA
+ { 170, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #170 = ATOMIC_LOAD_OR_I8
+ { 171, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #171 = ATOMIC_LOAD_OR_I8_POSTRA
+ { 172, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #172 = ATOMIC_LOAD_SUB_I16
+ { 173, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #173 = ATOMIC_LOAD_SUB_I16_POSTRA
+ { 174, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #174 = ATOMIC_LOAD_SUB_I32
+ { 175, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #175 = ATOMIC_LOAD_SUB_I32_POSTRA
+ { 176, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #176 = ATOMIC_LOAD_SUB_I64
+ { 177, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #177 = ATOMIC_LOAD_SUB_I64_POSTRA
+ { 178, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #178 = ATOMIC_LOAD_SUB_I8
+ { 179, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #179 = ATOMIC_LOAD_SUB_I8_POSTRA
+ { 180, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #180 = ATOMIC_LOAD_XOR_I16
+ { 181, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #181 = ATOMIC_LOAD_XOR_I16_POSTRA
+ { 182, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #182 = ATOMIC_LOAD_XOR_I32
+ { 183, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #183 = ATOMIC_LOAD_XOR_I32_POSTRA
+ { 184, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #184 = ATOMIC_LOAD_XOR_I64
+ { 185, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #185 = ATOMIC_LOAD_XOR_I64_POSTRA
+ { 186, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #186 = ATOMIC_LOAD_XOR_I8
+ { 187, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #187 = ATOMIC_LOAD_XOR_I8_POSTRA
+ { 188, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #188 = ATOMIC_SWAP_I16
+ { 189, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #189 = ATOMIC_SWAP_I16_POSTRA
+ { 190, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #190 = ATOMIC_SWAP_I32
+ { 191, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #191 = ATOMIC_SWAP_I32_POSTRA
+ { 192, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #192 = ATOMIC_SWAP_I64
+ { 193, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #193 = ATOMIC_SWAP_I64_POSTRA
+ { 194, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #194 = ATOMIC_SWAP_I8
+ { 195, 6, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #195 = ATOMIC_SWAP_I8_POSTRA
+ { 196, 1, 0, 4, 366, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #196 = B
+ { 197, 1, 0, 4, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #197 = BAL_BR
+ { 198, 1, 0, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #198 = BAL_BR_MM
+ { 199, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #199 = BEQLImmMacro
+ { 200, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #200 = BGE
+ { 201, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #201 = BGEImmMacro
+ { 202, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #202 = BGEL
+ { 203, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #203 = BGELImmMacro
+ { 204, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #204 = BGEU
+ { 205, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #205 = BGEUImmMacro
+ { 206, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #206 = BGEUL
+ { 207, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #207 = BGEULImmMacro
+ { 208, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #208 = BGT
+ { 209, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #209 = BGTImmMacro
+ { 210, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #210 = BGTL
+ { 211, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #211 = BGTLImmMacro
+ { 212, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #212 = BGTU
+ { 213, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #213 = BGTUImmMacro
+ { 214, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #214 = BGTUL
+ { 215, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #215 = BGTULImmMacro
+ { 216, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #216 = BLE
+ { 217, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #217 = BLEImmMacro
+ { 218, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #218 = BLEL
+ { 219, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #219 = BLELImmMacro
+ { 220, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #220 = BLEU
+ { 221, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #221 = BLEUImmMacro
+ { 222, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #222 = BLEUL
+ { 223, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #223 = BLEULImmMacro
+ { 224, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #224 = BLT
+ { 225, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #225 = BLTImmMacro
+ { 226, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #226 = BLTL
+ { 227, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #227 = BLTLImmMacro
+ { 228, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #228 = BLTU
+ { 229, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #229 = BLTUImmMacro
+ { 230, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #230 = BLTUL
+ { 231, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #231 = BLTULImmMacro
+ { 232, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #232 = BNELImmMacro
+ { 233, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #233 = BPOSGE32_PSEUDO
+ { 234, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #234 = BSEL_D_PSEUDO
+ { 235, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #235 = BSEL_FD_PSEUDO
+ { 236, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #236 = BSEL_FW_PSEUDO
+ { 237, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #237 = BSEL_H_PSEUDO
+ { 238, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #238 = BSEL_W_PSEUDO
+ { 239, 1, 0, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #239 = B_MM
+ { 240, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #240 = B_MMR6_Pseudo
+ { 241, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #241 = B_MM_Pseudo
+ { 242, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #242 = BeqImm
+ { 243, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #243 = BneImm
+ { 244, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #244 = BteqzT8CmpX16
+ { 245, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #245 = BteqzT8CmpiX16
+ { 246, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #246 = BteqzT8SltX16
+ { 247, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #247 = BteqzT8SltiX16
+ { 248, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #248 = BteqzT8SltiuX16
+ { 249, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #249 = BteqzT8SltuX16
+ { 250, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #250 = BtnezT8CmpX16
+ { 251, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #251 = BtnezT8CmpiX16
+ { 252, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #252 = BtnezT8SltX16
+ { 253, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #253 = BtnezT8SltiX16
+ { 254, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #254 = BtnezT8SltiuX16
+ { 255, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #255 = BtnezT8SltuX16
+ { 256, 3, 1, 4, 658, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #256 = BuildPairF64
+ { 257, 3, 1, 4, 658, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #257 = BuildPairF64_64
+ { 258, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #258 = CFTC1
+ { 259, 3, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #259 = CONSTPOOL_ENTRY
+ { 260, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #260 = COPY_FD_PSEUDO
+ { 261, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #261 = COPY_FW_PSEUDO
+ { 262, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #262 = CTTC1
+ { 263, 1, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #263 = Constant32
+ { 264, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #264 = DMULImmMacro
+ { 265, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #265 = DMULMacro
+ { 266, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #266 = DMULOMacro
+ { 267, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #267 = DMULOUMacro
+ { 268, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #268 = DROL
+ { 269, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #269 = DROLImm
+ { 270, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #270 = DROR
+ { 271, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #271 = DRORImm
+ { 272, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #272 = DSDivIMacro
+ { 273, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #273 = DSDivMacro
+ { 274, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #274 = DSRemIMacro
+ { 275, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #275 = DSRemMacro
+ { 276, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #276 = DUDivIMacro
+ { 277, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #277 = DUDivMacro
+ { 278, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #278 = DURemIMacro
+ { 279, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #279 = DURemMacro
+ { 280, 0, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #280 = ERet
+ { 281, 3, 1, 4, 667, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #281 = ExtractElementF64
+ { 282, 3, 1, 4, 667, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #282 = ExtractElementF64_64
+ { 283, 2, 1, 4, 565, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #283 = FABS_D
+ { 284, 2, 1, 4, 565, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #284 = FABS_W
+ { 285, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #285 = FEXP2_D_1_PSEUDO
+ { 286, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #286 = FEXP2_W_1_PSEUDO
+ { 287, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #287 = FILL_FD_PSEUDO
+ { 288, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #288 = FILL_FW_PSEUDO
+ { 289, 4, 2, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #289 = GotPrologue16
+ { 290, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #290 = INSERT_B_VIDX64_PSEUDO
+ { 291, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #291 = INSERT_B_VIDX_PSEUDO
+ { 292, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #292 = INSERT_D_VIDX64_PSEUDO
+ { 293, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #293 = INSERT_D_VIDX_PSEUDO
+ { 294, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #294 = INSERT_FD_PSEUDO
+ { 295, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #295 = INSERT_FD_VIDX64_PSEUDO
+ { 296, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #296 = INSERT_FD_VIDX_PSEUDO
+ { 297, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #297 = INSERT_FW_PSEUDO
+ { 298, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #298 = INSERT_FW_VIDX64_PSEUDO
+ { 299, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #299 = INSERT_FW_VIDX_PSEUDO
+ { 300, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #300 = INSERT_H_VIDX64_PSEUDO
+ { 301, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #301 = INSERT_H_VIDX_PSEUDO
+ { 302, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #302 = INSERT_W_VIDX64_PSEUDO
+ { 303, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #303 = INSERT_W_VIDX_PSEUDO
+ { 304, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo81, -1 ,nullptr }, // Inst #304 = JALR64Pseudo
+ { 305, 1, 0, 4, 6, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo81, -1 ,nullptr }, // Inst #305 = JALRHB64Pseudo
+ { 306, 1, 0, 4, 399, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #306 = JALRHBPseudo
+ { 307, 1, 0, 4, 399, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #307 = JALRPseudo
+ { 308, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #308 = JalOneReg
+ { 309, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #309 = JalTwoReg
+ { 310, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #310 = LDMacro
+ { 311, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #311 = LD_F16
+ { 312, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #312 = LOAD_ACC128
+ { 313, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #313 = LOAD_ACC64
+ { 314, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #314 = LOAD_ACC64DSP
+ { 315, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #315 = LOAD_CCOND_DSP
+ { 316, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #316 = LONG_BRANCH_ADDiu
+ { 317, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #317 = LONG_BRANCH_DADDiu
+ { 318, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #318 = LONG_BRANCH_LUi
+ { 319, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #319 = LWM_MM
+ { 320, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #320 = LoadAddrImm32
+ { 321, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #321 = LoadAddrImm64
+ { 322, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #322 = LoadAddrReg32
+ { 323, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #323 = LoadAddrReg64
+ { 324, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #324 = LoadImm32
+ { 325, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #325 = LoadImm64
+ { 326, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #326 = LoadImmDoubleFGR
+ { 327, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #327 = LoadImmDoubleFGR_32
+ { 328, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #328 = LoadImmDoubleGPR
+ { 329, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #329 = LoadImmSingleFGR
+ { 330, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #330 = LoadImmSingleGPR
+ { 331, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #331 = LwConstant32
+ { 332, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #332 = MFTACX
+ { 333, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #333 = MFTC0
+ { 334, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #334 = MFTC1
+ { 335, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #335 = MFTDSP
+ { 336, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #336 = MFTGPR
+ { 337, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #337 = MFTHC1
+ { 338, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #338 = MFTHI
+ { 339, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #339 = MFTLO
+ { 340, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #340 = MIPSeh_return32
+ { 341, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #341 = MIPSeh_return64
+ { 342, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #342 = MSA_FP_EXTEND_D_PSEUDO
+ { 343, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #343 = MSA_FP_EXTEND_W_PSEUDO
+ { 344, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #344 = MSA_FP_ROUND_D_PSEUDO
+ { 345, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #345 = MSA_FP_ROUND_W_PSEUDO
+ { 346, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #346 = MTTACX
+ { 347, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #347 = MTTC0
+ { 348, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #348 = MTTC1
+ { 349, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #349 = MTTDSP
+ { 350, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #350 = MTTGPR
+ { 351, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #351 = MTTHC1
+ { 352, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #352 = MTTHI
+ { 353, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #353 = MTTLO
+ { 354, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #354 = MULImmMacro
+ { 355, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #355 = MULOMacro
+ { 356, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #356 = MULOUMacro
+ { 357, 2, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr }, // Inst #357 = MultRxRy16
+ { 358, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo112, -1 ,nullptr }, // Inst #358 = MultRxRyRz16
+ { 359, 2, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr }, // Inst #359 = MultuRxRy16
+ { 360, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo112, -1 ,nullptr }, // Inst #360 = MultuRxRyRz16
+ { 361, 0, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #361 = NOP
+ { 362, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #362 = NORImm
+ { 363, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #363 = NORImm64
+ { 364, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #364 = NOR_V_D_PSEUDO
+ { 365, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #365 = NOR_V_H_PSEUDO
+ { 366, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #366 = NOR_V_W_PSEUDO
+ { 367, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #367 = OR_V_D_PSEUDO
+ { 368, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #368 = OR_V_H_PSEUDO
+ { 369, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #369 = OR_V_W_PSEUDO
+ { 370, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #370 = PseudoCMPU_EQ_QB
+ { 371, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #371 = PseudoCMPU_LE_QB
+ { 372, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #372 = PseudoCMPU_LT_QB
+ { 373, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #373 = PseudoCMP_EQ_PH
+ { 374, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #374 = PseudoCMP_LE_PH
+ { 375, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #375 = PseudoCMP_LT_PH
+ { 376, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #376 = PseudoCVT_D32_W
+ { 377, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #377 = PseudoCVT_D64_L
+ { 378, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #378 = PseudoCVT_D64_W
+ { 379, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #379 = PseudoCVT_S_L
+ { 380, 2, 1, 4, 617, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #380 = PseudoCVT_S_W
+ { 381, 3, 1, 4, 8, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #381 = PseudoDMULT
+ { 382, 3, 1, 4, 9, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #382 = PseudoDMULTu
+ { 383, 3, 1, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #383 = PseudoDSDIV
+ { 384, 3, 1, 4, 11, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #384 = PseudoDUDIV
+ { 385, 1, 0, 4, 378, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #385 = PseudoIndirectBranch
+ { 386, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #386 = PseudoIndirectBranch64
+ { 387, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #387 = PseudoIndirectBranch64R6
+ { 388, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #388 = PseudoIndirectBranchR6
+ { 389, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #389 = PseudoIndirectBranch_MM
+ { 390, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #390 = PseudoIndirectBranch_MMR6
+ { 391, 1, 0, 4, 378, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #391 = PseudoIndirectHazardBranch
+ { 392, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #392 = PseudoIndirectHazardBranch64
+ { 393, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #393 = PseudoIndrectHazardBranch64R6
+ { 394, 1, 0, 4, 12, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #394 = PseudoIndrectHazardBranchR6
+ { 395, 4, 1, 4, 470, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #395 = PseudoMADD
+ { 396, 4, 1, 4, 471, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #396 = PseudoMADDU
+ { 397, 2, 1, 4, 459, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #397 = PseudoMFHI
+ { 398, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #398 = PseudoMFHI64
+ { 399, 2, 1, 4, 459, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #399 = PseudoMFLO
+ { 400, 2, 1, 4, 15, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #400 = PseudoMFLO64
+ { 401, 4, 1, 4, 472, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #401 = PseudoMSUB
+ { 402, 4, 1, 4, 473, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #402 = PseudoMSUBU
+ { 403, 3, 1, 4, 474, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #403 = PseudoMTLOHI
+ { 404, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #404 = PseudoMTLOHI64
+ { 405, 3, 1, 4, 18, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #405 = PseudoMTLOHI_DSP
+ { 406, 3, 1, 4, 468, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #406 = PseudoMULT
+ { 407, 3, 1, 4, 469, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #407 = PseudoMULTu
+ { 408, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #408 = PseudoPICK_PH
+ { 409, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #409 = PseudoPICK_QB
+ { 410, 1, 0, 4, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #410 = PseudoReturn
+ { 411, 1, 0, 4, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #411 = PseudoReturn64
+ { 412, 3, 1, 4, 465, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #412 = PseudoSDIV
+ { 413, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #413 = PseudoSELECTFP_F_D32
+ { 414, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #414 = PseudoSELECTFP_F_D64
+ { 415, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #415 = PseudoSELECTFP_F_I
+ { 416, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #416 = PseudoSELECTFP_F_I64
+ { 417, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #417 = PseudoSELECTFP_F_S
+ { 418, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #418 = PseudoSELECTFP_T_D32
+ { 419, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #419 = PseudoSELECTFP_T_D64
+ { 420, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #420 = PseudoSELECTFP_T_I
+ { 421, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #421 = PseudoSELECTFP_T_I64
+ { 422, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #422 = PseudoSELECTFP_T_S
+ { 423, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #423 = PseudoSELECT_D32
+ { 424, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #424 = PseudoSELECT_D64
+ { 425, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #425 = PseudoSELECT_I
+ { 426, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #426 = PseudoSELECT_I64
+ { 427, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #427 = PseudoSELECT_S
+ { 428, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #428 = PseudoTRUNC_W_D
+ { 429, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #429 = PseudoTRUNC_W_D32
+ { 430, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #430 = PseudoTRUNC_W_S
+ { 431, 3, 1, 4, 466, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #431 = PseudoUDIV
+ { 432, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #432 = ROL
+ { 433, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #433 = ROLImm
+ { 434, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #434 = ROR
+ { 435, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #435 = RORImm
+ { 436, 0, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #436 = RetRA
+ { 437, 0, 0, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #437 = RetRA16
+ { 438, 3, 1, 4, 22, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #438 = SDIV_MM_Pseudo
+ { 439, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #439 = SDMacro
+ { 440, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #440 = SDivIMacro
+ { 441, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #441 = SDivMacro
+ { 442, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #442 = SEQIMacro
+ { 443, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #443 = SEQMacro
+ { 444, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #444 = SLTImm64
+ { 445, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #445 = SLTUImm64
+ { 446, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #446 = SNZ_B_PSEUDO
+ { 447, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #447 = SNZ_D_PSEUDO
+ { 448, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #448 = SNZ_H_PSEUDO
+ { 449, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #449 = SNZ_V_PSEUDO
+ { 450, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #450 = SNZ_W_PSEUDO
+ { 451, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #451 = SRemIMacro
+ { 452, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #452 = SRemMacro
+ { 453, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #453 = STORE_ACC128
+ { 454, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #454 = STORE_ACC64
+ { 455, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #455 = STORE_ACC64DSP
+ { 456, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #456 = STORE_CCOND_DSP
+ { 457, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #457 = ST_F16
+ { 458, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #458 = SWM_MM
+ { 459, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #459 = SZ_B_PSEUDO
+ { 460, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #460 = SZ_D_PSEUDO
+ { 461, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #461 = SZ_H_PSEUDO
+ { 462, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #462 = SZ_V_PSEUDO
+ { 463, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #463 = SZ_W_PSEUDO
+ { 464, 4, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #464 = SelBeqZ
+ { 465, 4, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #465 = SelBneZ
+ { 466, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #466 = SelTBteqZCmp
+ { 467, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #467 = SelTBteqZCmpi
+ { 468, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #468 = SelTBteqZSlt
+ { 469, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #469 = SelTBteqZSlti
+ { 470, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #470 = SelTBteqZSltiu
+ { 471, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #471 = SelTBteqZSltu
+ { 472, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #472 = SelTBtneZCmp
+ { 473, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #473 = SelTBtneZCmpi
+ { 474, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #474 = SelTBtneZSlt
+ { 475, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #475 = SelTBtneZSlti
+ { 476, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #476 = SelTBtneZSltiu
+ { 477, 5, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #477 = SelTBtneZSltu
+ { 478, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #478 = SltCCRxRy16
+ { 479, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #479 = SltiCCRxImmX16
+ { 480, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #480 = SltiuCCRxImmX16
+ { 481, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #481 = SltuCCRxRy16
+ { 482, 3, 1, 2, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo112, -1 ,nullptr }, // Inst #482 = SltuRxRyRz16
+ { 483, 1, 0, 4, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #483 = TAILCALL
+ { 484, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr }, // Inst #484 = TAILCALL64R6REG
+ { 485, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr }, // Inst #485 = TAILCALLHB64R6REG
+ { 486, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #486 = TAILCALLHBR6REG
+ { 487, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #487 = TAILCALLR6REG
+ { 488, 1, 0, 4, 376, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #488 = TAILCALLREG
+ { 489, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr }, // Inst #489 = TAILCALLREG64
+ { 490, 1, 0, 4, 376, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #490 = TAILCALLREGHB
+ { 491, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo81, -1 ,nullptr }, // Inst #491 = TAILCALLREGHB64
+ { 492, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #492 = TAILCALLREG_MM
+ { 493, 1, 0, 4, 25, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo44, -1 ,nullptr }, // Inst #493 = TAILCALLREG_MMR6
+ { 494, 1, 0, 4, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #494 = TAILCALL_MM
+ { 495, 1, 0, 4, 24, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #495 = TAILCALL_MMR6
+ { 496, 0, 0, 4, 394, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #496 = TRAP
+ { 497, 0, 0, 4, 26, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #497 = TRAP_MM
+ { 498, 3, 1, 4, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #498 = UDIV_MM_Pseudo
+ { 499, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #499 = UDivIMacro
+ { 500, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #500 = UDivMacro
+ { 501, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #501 = URemIMacro
+ { 502, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #502 = URemMacro
+ { 503, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #503 = Ulh
+ { 504, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #504 = Ulhu
+ { 505, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #505 = Ulw
+ { 506, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #506 = Ush
+ { 507, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #507 = Usw
+ { 508, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #508 = XOR_V_D_PSEUDO
+ { 509, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #509 = XOR_V_H_PSEUDO
+ { 510, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #510 = XOR_V_W_PSEUDO
+ { 511, 2, 1, 4, 703, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr }, // Inst #511 = ABSQ_S_PH
+ { 512, 2, 1, 4, 850, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr }, // Inst #512 = ABSQ_S_PH_MM
+ { 513, 2, 1, 4, 804, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr }, // Inst #513 = ABSQ_S_QB
+ { 514, 2, 1, 4, 967, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo146, -1 ,nullptr }, // Inst #514 = ABSQ_S_QB_MMR2
+ { 515, 2, 1, 4, 704, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo31, -1 ,nullptr }, // Inst #515 = ABSQ_S_W
+ { 516, 2, 1, 4, 851, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo31, -1 ,nullptr }, // Inst #516 = ABSQ_S_W_MM
+ { 517, 3, 1, 4, 477, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #517 = ADD
+ { 518, 2, 1, 4, 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #518 = ADDIUPC
+ { 519, 2, 1, 4, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #519 = ADDIUPC_MM
+ { 520, 2, 1, 4, 28, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #520 = ADDIUPC_MMR6
+ { 521, 2, 1, 2, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #521 = ADDIUR1SP_MM
+ { 522, 3, 1, 2, 29, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #522 = ADDIUR2_MM
+ { 523, 3, 1, 2, 29, 0, 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #523 = ADDIUS5_MM
+ { 524, 1, 0, 2, 29, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #524 = ADDIUSP_MM
+ { 525, 3, 1, 4, 29, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #525 = ADDIU_MMR6
+ { 526, 3, 1, 4, 805, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #526 = ADDQH_PH
+ { 527, 3, 1, 4, 968, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #527 = ADDQH_PH_MMR2
+ { 528, 3, 1, 4, 806, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #528 = ADDQH_R_PH
+ { 529, 3, 1, 4, 969, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #529 = ADDQH_R_PH_MMR2
+ { 530, 3, 1, 4, 807, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #530 = ADDQH_R_W
+ { 531, 3, 1, 4, 970, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #531 = ADDQH_R_W_MMR2
+ { 532, 3, 1, 4, 808, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #532 = ADDQH_W
+ { 533, 3, 1, 4, 971, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #533 = ADDQH_W_MMR2
+ { 534, 3, 1, 4, 705, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #534 = ADDQ_PH
+ { 535, 3, 1, 4, 852, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #535 = ADDQ_PH_MM
+ { 536, 3, 1, 4, 706, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #536 = ADDQ_S_PH
+ { 537, 3, 1, 4, 853, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #537 = ADDQ_S_PH_MM
+ { 538, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #538 = ADDQ_S_W
+ { 539, 3, 1, 4, 854, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #539 = ADDQ_S_W_MM
+ { 540, 3, 1, 4, 708, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo58, -1 ,nullptr }, // Inst #540 = ADDSC
+ { 541, 3, 1, 4, 855, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo58, -1 ,nullptr }, // Inst #541 = ADDSC_MM
+ { 542, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #542 = ADDS_A_B
+ { 543, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #543 = ADDS_A_D
+ { 544, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #544 = ADDS_A_H
+ { 545, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #545 = ADDS_A_W
+ { 546, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #546 = ADDS_S_B
+ { 547, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #547 = ADDS_S_D
+ { 548, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #548 = ADDS_S_H
+ { 549, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #549 = ADDS_S_W
+ { 550, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #550 = ADDS_U_B
+ { 551, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #551 = ADDS_U_D
+ { 552, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #552 = ADDS_U_H
+ { 553, 3, 1, 4, 519, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #553 = ADDS_U_W
+ { 554, 3, 1, 2, 30, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #554 = ADDU16_MM
+ { 555, 3, 1, 2, 30, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #555 = ADDU16_MMR6
+ { 556, 3, 1, 4, 809, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #556 = ADDUH_QB
+ { 557, 3, 1, 4, 972, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #557 = ADDUH_QB_MMR2
+ { 558, 3, 1, 4, 810, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #558 = ADDUH_R_QB
+ { 559, 3, 1, 4, 973, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #559 = ADDUH_R_QB_MMR2
+ { 560, 3, 1, 4, 30, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #560 = ADDU_MMR6
+ { 561, 3, 1, 4, 811, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #561 = ADDU_PH
+ { 562, 3, 1, 4, 974, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #562 = ADDU_PH_MMR2
+ { 563, 3, 1, 4, 709, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #563 = ADDU_QB
+ { 564, 3, 1, 4, 856, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #564 = ADDU_QB_MM
+ { 565, 3, 1, 4, 812, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #565 = ADDU_S_PH
+ { 566, 3, 1, 4, 975, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #566 = ADDU_S_PH_MMR2
+ { 567, 3, 1, 4, 710, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #567 = ADDU_S_QB
+ { 568, 3, 1, 4, 857, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #568 = ADDU_S_QB_MM
+ { 569, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #569 = ADDVI_B
+ { 570, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #570 = ADDVI_D
+ { 571, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #571 = ADDVI_H
+ { 572, 3, 1, 4, 520, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #572 = ADDVI_W
+ { 573, 3, 1, 4, 520, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #573 = ADDV_B
+ { 574, 3, 1, 4, 520, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #574 = ADDV_D
+ { 575, 3, 1, 4, 520, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #575 = ADDV_H
+ { 576, 3, 1, 4, 520, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #576 = ADDV_W
+ { 577, 3, 1, 4, 711, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #577 = ADDWC
+ { 578, 3, 1, 4, 858, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #578 = ADDWC_MM
+ { 579, 3, 1, 4, 518, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #579 = ADD_A_B
+ { 580, 3, 1, 4, 518, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #580 = ADD_A_D
+ { 581, 3, 1, 4, 518, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #581 = ADD_A_H
+ { 582, 3, 1, 4, 518, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #582 = ADD_A_W
+ { 583, 3, 1, 4, 27, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #583 = ADD_MM
+ { 584, 3, 1, 4, 27, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #584 = ADD_MMR6
+ { 585, 3, 1, 4, 478, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #585 = ADDi
+ { 586, 3, 1, 4, 31, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #586 = ADDi_MM
+ { 587, 3, 1, 4, 479, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #587 = ADDiu
+ { 588, 3, 1, 4, 29, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #588 = ADDiu_MM
+ { 589, 3, 1, 4, 490, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #589 = ADDu
+ { 590, 3, 1, 4, 30, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #590 = ADDu_MM
+ { 591, 4, 1, 4, 32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #591 = ALIGN
+ { 592, 4, 1, 4, 32, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #592 = ALIGN_MMR6
+ { 593, 2, 1, 4, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #593 = ALUIPC
+ { 594, 2, 1, 4, 33, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #594 = ALUIPC_MMR6
+ { 595, 3, 1, 4, 358, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #595 = AND
+ { 596, 3, 1, 2, 34, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #596 = AND16_MM
+ { 597, 3, 1, 2, 34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #597 = AND16_MMR6
+ { 598, 3, 1, 4, 34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #598 = AND64
+ { 599, 3, 1, 2, 34, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #599 = ANDI16_MM
+ { 600, 3, 1, 2, 34, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #600 = ANDI16_MMR6
+ { 601, 3, 1, 4, 529, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #601 = ANDI_B
+ { 602, 3, 1, 4, 35, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #602 = ANDI_MMR6
+ { 603, 3, 1, 4, 34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #603 = AND_MM
+ { 604, 3, 1, 4, 34, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #604 = AND_MMR6
+ { 605, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #605 = AND_V
+ { 606, 3, 1, 4, 480, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #606 = ANDi
+ { 607, 3, 1, 4, 34, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #607 = ANDi64
+ { 608, 3, 1, 4, 35, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #608 = ANDi_MM
+ { 609, 4, 1, 4, 813, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #609 = APPEND
+ { 610, 4, 1, 4, 976, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #610 = APPEND_MMR2
+ { 611, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #611 = ASUB_S_B
+ { 612, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #612 = ASUB_S_D
+ { 613, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #613 = ASUB_S_H
+ { 614, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #614 = ASUB_S_W
+ { 615, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #615 = ASUB_U_B
+ { 616, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #616 = ASUB_U_D
+ { 617, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #617 = ASUB_U_H
+ { 618, 3, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #618 = ASUB_U_W
+ { 619, 3, 1, 4, 36, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #619 = AUI
+ { 620, 2, 1, 4, 37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #620 = AUIPC
+ { 621, 2, 1, 4, 37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #621 = AUIPC_MMR6
+ { 622, 3, 1, 4, 36, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #622 = AUI_MMR6
+ { 623, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #623 = AVER_S_B
+ { 624, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #624 = AVER_S_D
+ { 625, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #625 = AVER_S_H
+ { 626, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #626 = AVER_S_W
+ { 627, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #627 = AVER_U_B
+ { 628, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #628 = AVER_U_D
+ { 629, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #629 = AVER_U_H
+ { 630, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #630 = AVER_U_W
+ { 631, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #631 = AVE_S_B
+ { 632, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #632 = AVE_S_D
+ { 633, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #633 = AVE_S_H
+ { 634, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #634 = AVE_S_W
+ { 635, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #635 = AVE_U_B
+ { 636, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #636 = AVE_U_D
+ { 637, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #637 = AVE_U_H
+ { 638, 3, 1, 4, 522, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #638 = AVE_U_W
+ { 639, 2, 1, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #639 = AddiuRxImmX16
+ { 640, 2, 1, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #640 = AddiuRxPcImmX16
+ { 641, 3, 1, 2, 38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #641 = AddiuRxRxImm16
+ { 642, 3, 1, 4, 38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #642 = AddiuRxRxImmX16
+ { 643, 3, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #643 = AddiuRxRyOffMemX16
+ { 644, 1, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr }, // Inst #644 = AddiuSpImm16
+ { 645, 1, 0, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr }, // Inst #645 = AddiuSpImmX16
+ { 646, 3, 1, 2, 38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #646 = AdduRxRyRz16
+ { 647, 3, 1, 2, 38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #647 = AndRxRxRy16
+ { 648, 1, 0, 2, 2, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #648 = B16_MM
+ { 649, 3, 1, 4, 39, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #649 = BADDu
+ { 650, 1, 0, 4, 367, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #650 = BAL
+ { 651, 1, 0, 4, 41, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #651 = BALC
+ { 652, 1, 0, 4, 41, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo41, -1 ,nullptr }, // Inst #652 = BALC_MMR6
+ { 653, 4, 1, 4, 814, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #653 = BALIGN
+ { 654, 4, 1, 4, 977, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #654 = BALIGN_MMR2
+ { 655, 3, 0, 4, 42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr }, // Inst #655 = BBIT0
+ { 656, 3, 0, 4, 42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr }, // Inst #656 = BBIT032
+ { 657, 3, 0, 4, 42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr }, // Inst #657 = BBIT1
+ { 658, 3, 0, 4, 42, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo164, -1 ,nullptr }, // Inst #658 = BBIT132
+ { 659, 1, 0, 4, 40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #659 = BC
+ { 660, 1, 0, 2, 40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo41, -1 ,nullptr }, // Inst #660 = BC16_MMR6
+ { 661, 2, 0, 4, 43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #661 = BC1EQZ
+ { 662, 2, 0, 4, 43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo165, -1 ,nullptr }, // Inst #662 = BC1EQZC_MMR6
+ { 663, 2, 0, 4, 662, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #663 = BC1F
+ { 664, 2, 0, 4, 663, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #664 = BC1FL
+ { 665, 2, 0, 4, 44, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #665 = BC1F_MM
+ { 666, 2, 0, 4, 43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #666 = BC1NEZ
+ { 667, 2, 0, 4, 43, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo165, -1 ,nullptr }, // Inst #667 = BC1NEZC_MMR6
+ { 668, 2, 0, 4, 664, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #668 = BC1T
+ { 669, 2, 0, 4, 665, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #669 = BC1TL
+ { 670, 2, 0, 4, 46, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x85ULL, nullptr, ImplicitList2, OperandInfo166, -1 ,nullptr }, // Inst #670 = BC1T_MM
+ { 671, 2, 0, 4, 48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #671 = BC2EQZ
+ { 672, 2, 0, 4, 48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo167, -1 ,nullptr }, // Inst #672 = BC2EQZC_MMR6
+ { 673, 2, 0, 4, 48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #673 = BC2NEZ
+ { 674, 2, 0, 4, 48, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo167, -1 ,nullptr }, // Inst #674 = BC2NEZC_MMR6
+ { 675, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #675 = BCLRI_B
+ { 676, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #676 = BCLRI_D
+ { 677, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #677 = BCLRI_H
+ { 678, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #678 = BCLRI_W
+ { 679, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #679 = BCLR_B
+ { 680, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #680 = BCLR_D
+ { 681, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #681 = BCLR_H
+ { 682, 3, 1, 4, 502, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #682 = BCLR_W
+ { 683, 1, 0, 4, 40, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #683 = BC_MMR6
+ { 684, 3, 0, 4, 369, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #684 = BEQ
+ { 685, 3, 0, 4, 49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #685 = BEQ64
+ { 686, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #686 = BEQC
+ { 687, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #687 = BEQC64
+ { 688, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #688 = BEQC_MMR6
+ { 689, 3, 0, 4, 369, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #689 = BEQL
+ { 690, 2, 0, 2, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr }, // Inst #690 = BEQZ16_MM
+ { 691, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #691 = BEQZALC
+ { 692, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #692 = BEQZALC_MMR6
+ { 693, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #693 = BEQZC
+ { 694, 2, 0, 2, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr }, // Inst #694 = BEQZC16_MMR6
+ { 695, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #695 = BEQZC64
+ { 696, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #696 = BEQZC_MM
+ { 697, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #697 = BEQZC_MMR6
+ { 698, 3, 0, 4, 49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #698 = BEQ_MM
+ { 699, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #699 = BGEC
+ { 700, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #700 = BGEC64
+ { 701, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #701 = BGEC_MMR6
+ { 702, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #702 = BGEUC
+ { 703, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #703 = BGEUC64
+ { 704, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #704 = BGEUC_MMR6
+ { 705, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #705 = BGEZ
+ { 706, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #706 = BGEZ64
+ { 707, 2, 0, 4, 368, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #707 = BGEZAL
+ { 708, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #708 = BGEZALC
+ { 709, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #709 = BGEZALC_MMR6
+ { 710, 2, 0, 4, 368, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #710 = BGEZALL
+ { 711, 2, 0, 4, 53, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #711 = BGEZALS_MM
+ { 712, 2, 0, 4, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #712 = BGEZAL_MM
+ { 713, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #713 = BGEZC
+ { 714, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #714 = BGEZC64
+ { 715, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #715 = BGEZC_MMR6
+ { 716, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #716 = BGEZL
+ { 717, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #717 = BGEZ_MM
+ { 718, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #718 = BGTZ
+ { 719, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #719 = BGTZ64
+ { 720, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #720 = BGTZALC
+ { 721, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #721 = BGTZALC_MMR6
+ { 722, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #722 = BGTZC
+ { 723, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #723 = BGTZC64
+ { 724, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #724 = BGTZC_MMR6
+ { 725, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #725 = BGTZL
+ { 726, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #726 = BGTZ_MM
+ { 727, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #727 = BINSLI_B
+ { 728, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #728 = BINSLI_D
+ { 729, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #729 = BINSLI_H
+ { 730, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #730 = BINSLI_W
+ { 731, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #731 = BINSL_B
+ { 732, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #732 = BINSL_D
+ { 733, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #733 = BINSL_H
+ { 734, 4, 1, 4, 497, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #734 = BINSL_W
+ { 735, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #735 = BINSRI_B
+ { 736, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #736 = BINSRI_D
+ { 737, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #737 = BINSRI_H
+ { 738, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #738 = BINSRI_W
+ { 739, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #739 = BINSR_B
+ { 740, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #740 = BINSR_D
+ { 741, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #741 = BINSR_H
+ { 742, 4, 1, 4, 498, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #742 = BINSR_W
+ { 743, 2, 1, 4, 712, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #743 = BITREV
+ { 744, 2, 1, 4, 859, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #744 = BITREV_MM
+ { 745, 2, 1, 4, 54, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #745 = BITSWAP
+ { 746, 2, 1, 4, 54, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #746 = BITSWAP_MMR6
+ { 747, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #747 = BLEZ
+ { 748, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #748 = BLEZ64
+ { 749, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #749 = BLEZALC
+ { 750, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #750 = BLEZALC_MMR6
+ { 751, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #751 = BLEZC
+ { 752, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #752 = BLEZC64
+ { 753, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #753 = BLEZC_MMR6
+ { 754, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #754 = BLEZL
+ { 755, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #755 = BLEZ_MM
+ { 756, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #756 = BLTC
+ { 757, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #757 = BLTC64
+ { 758, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #758 = BLTC_MMR6
+ { 759, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #759 = BLTUC
+ { 760, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #760 = BLTUC64
+ { 761, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #761 = BLTUC_MMR6
+ { 762, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #762 = BLTZ
+ { 763, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #763 = BLTZ64
+ { 764, 2, 0, 4, 368, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #764 = BLTZAL
+ { 765, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #765 = BLTZALC
+ { 766, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #766 = BLTZALC_MMR6
+ { 767, 2, 0, 4, 368, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #767 = BLTZALL
+ { 768, 2, 0, 4, 53, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #768 = BLTZALS_MM
+ { 769, 2, 0, 4, 3, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #769 = BLTZAL_MM
+ { 770, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #770 = BLTZC
+ { 771, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #771 = BLTZC64
+ { 772, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #772 = BLTZC_MMR6
+ { 773, 2, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #773 = BLTZL
+ { 774, 2, 0, 4, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #774 = BLTZ_MM
+ { 775, 4, 1, 4, 505, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #775 = BMNZI_B
+ { 776, 4, 1, 4, 505, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #776 = BMNZ_V
+ { 777, 4, 1, 4, 505, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #777 = BMZI_B
+ { 778, 4, 1, 4, 505, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #778 = BMZ_V
+ { 779, 3, 0, 4, 369, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #779 = BNE
+ { 780, 3, 0, 4, 49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #780 = BNE64
+ { 781, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #781 = BNEC
+ { 782, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo168, -1 ,nullptr }, // Inst #782 = BNEC64
+ { 783, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #783 = BNEC_MMR6
+ { 784, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #784 = BNEGI_B
+ { 785, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #785 = BNEGI_D
+ { 786, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #786 = BNEGI_H
+ { 787, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #787 = BNEGI_W
+ { 788, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #788 = BNEG_B
+ { 789, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #789 = BNEG_D
+ { 790, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #790 = BNEG_H
+ { 791, 3, 1, 4, 503, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #791 = BNEG_W
+ { 792, 3, 0, 4, 369, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #792 = BNEL
+ { 793, 2, 0, 2, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr }, // Inst #793 = BNEZ16_MM
+ { 794, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #794 = BNEZALC
+ { 795, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr }, // Inst #795 = BNEZALC_MMR6
+ { 796, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #796 = BNEZC
+ { 797, 2, 0, 2, 51, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo169, -1 ,nullptr }, // Inst #797 = BNEZC16_MMR6
+ { 798, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo171, -1 ,nullptr }, // Inst #798 = BNEZC64
+ { 799, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #799 = BNEZC_MM
+ { 800, 2, 0, 4, 52, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr }, // Inst #800 = BNEZC_MMR6
+ { 801, 3, 0, 4, 49, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #801 = BNE_MM
+ { 802, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #802 = BNVC
+ { 803, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #803 = BNVC_MMR6
+ { 804, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #804 = BNZ_B
+ { 805, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #805 = BNZ_D
+ { 806, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #806 = BNZ_H
+ { 807, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #807 = BNZ_V
+ { 808, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo180, -1 ,nullptr }, // Inst #808 = BNZ_W
+ { 809, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #809 = BOVC
+ { 810, 3, 0, 4, 50, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #810 = BOVC_MMR6
+ { 811, 1, 0, 4, 713, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #811 = BPOSGE32
+ { 812, 1, 0, 4, 1013, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #812 = BPOSGE32C_MMR3
+ { 813, 1, 0, 4, 860, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #813 = BPOSGE32_MM
+ { 814, 2, 0, 4, 371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #814 = BREAK
+ { 815, 1, 0, 2, 55, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #815 = BREAK16_MM
+ { 816, 1, 0, 2, 55, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #816 = BREAK16_MMR6
+ { 817, 2, 0, 4, 55, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #817 = BREAK_MM
+ { 818, 2, 0, 4, 55, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #818 = BREAK_MMR6
+ { 819, 4, 1, 4, 504, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #819 = BSELI_B
+ { 820, 4, 1, 4, 504, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #820 = BSEL_V
+ { 821, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #821 = BSETI_B
+ { 822, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #822 = BSETI_D
+ { 823, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #823 = BSETI_H
+ { 824, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #824 = BSETI_W
+ { 825, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #825 = BSET_B
+ { 826, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #826 = BSET_D
+ { 827, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #827 = BSET_H
+ { 828, 3, 1, 4, 501, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #828 = BSET_W
+ { 829, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #829 = BZ_B
+ { 830, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #830 = BZ_D
+ { 831, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #831 = BZ_H
+ { 832, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #832 = BZ_V
+ { 833, 2, 0, 4, 508, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo180, -1 ,nullptr }, // Inst #833 = BZ_W
+ { 834, 2, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #834 = BeqzRxImm16
+ { 835, 2, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #835 = BeqzRxImmX16
+ { 836, 1, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #836 = Bimm16
+ { 837, 1, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #837 = BimmX16
+ { 838, 2, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #838 = BnezRxImm16
+ { 839, 2, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #839 = BnezRxImmX16
+ { 840, 0, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #840 = Break16
+ { 841, 1, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #841 = Bteqz16
+ { 842, 1, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #842 = BteqzX16
+ { 843, 1, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #843 = Btnez16
+ { 844, 1, 0, 4, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #844 = BtnezX16
+ { 845, 3, 0, 4, 451, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #845 = CACHE
+ { 846, 3, 0, 4, 452, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #846 = CACHEE
+ { 847, 3, 0, 4, 57, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #847 = CACHEE_MM
+ { 848, 3, 0, 4, 56, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #848 = CACHE_MM
+ { 849, 3, 0, 4, 56, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #849 = CACHE_MMR6
+ { 850, 3, 0, 4, 56, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #850 = CACHE_R6
+ { 851, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #851 = CEIL_L_D64
+ { 852, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #852 = CEIL_L_D_MMR6
+ { 853, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #853 = CEIL_L_S
+ { 854, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #854 = CEIL_L_S_MMR6
+ { 855, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #855 = CEIL_W_D32
+ { 856, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #856 = CEIL_W_D64
+ { 857, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #857 = CEIL_W_D_MMR6
+ { 858, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #858 = CEIL_W_MM
+ { 859, 2, 1, 4, 687, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #859 = CEIL_W_S
+ { 860, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #860 = CEIL_W_S_MM
+ { 861, 2, 1, 4, 58, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #861 = CEIL_W_S_MMR6
+ { 862, 3, 1, 4, 533, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #862 = CEQI_B
+ { 863, 3, 1, 4, 533, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #863 = CEQI_D
+ { 864, 3, 1, 4, 533, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #864 = CEQI_H
+ { 865, 3, 1, 4, 533, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #865 = CEQI_W
+ { 866, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #866 = CEQ_B
+ { 867, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #867 = CEQ_D
+ { 868, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #868 = CEQ_H
+ { 869, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #869 = CEQ_W
+ { 870, 2, 1, 4, 666, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #870 = CFC1
+ { 871, 2, 1, 4, 59, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #871 = CFC1_MM
+ { 872, 2, 1, 4, 60, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #872 = CFC2_MM
+ { 873, 2, 1, 4, 509, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #873 = CFCMSA
+ { 874, 4, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #874 = CINS
+ { 875, 4, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #875 = CINS32
+ { 876, 4, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #876 = CINS64_32
+ { 877, 4, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #877 = CINS_i32
+ { 878, 2, 1, 4, 62, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #878 = CLASS_D
+ { 879, 2, 1, 4, 63, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #879 = CLASS_D_MMR6
+ { 880, 2, 1, 4, 63, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #880 = CLASS_S
+ { 881, 2, 1, 4, 63, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #881 = CLASS_S_MMR6
+ { 882, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #882 = CLEI_S_B
+ { 883, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #883 = CLEI_S_D
+ { 884, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #884 = CLEI_S_H
+ { 885, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #885 = CLEI_S_W
+ { 886, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #886 = CLEI_U_B
+ { 887, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #887 = CLEI_U_D
+ { 888, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #888 = CLEI_U_H
+ { 889, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #889 = CLEI_U_W
+ { 890, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #890 = CLE_S_B
+ { 891, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #891 = CLE_S_D
+ { 892, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #892 = CLE_S_H
+ { 893, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #893 = CLE_S_W
+ { 894, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #894 = CLE_U_B
+ { 895, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #895 = CLE_U_D
+ { 896, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #896 = CLE_U_H
+ { 897, 3, 1, 4, 532, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #897 = CLE_U_W
+ { 898, 2, 1, 4, 455, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #898 = CLO
+ { 899, 2, 1, 4, 64, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #899 = CLO_MM
+ { 900, 2, 1, 4, 64, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #900 = CLO_MMR6
+ { 901, 2, 1, 4, 64, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #901 = CLO_R6
+ { 902, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #902 = CLTI_S_B
+ { 903, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #903 = CLTI_S_D
+ { 904, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #904 = CLTI_S_H
+ { 905, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #905 = CLTI_S_W
+ { 906, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #906 = CLTI_U_B
+ { 907, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #907 = CLTI_U_D
+ { 908, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #908 = CLTI_U_H
+ { 909, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #909 = CLTI_U_W
+ { 910, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #910 = CLT_S_B
+ { 911, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #911 = CLT_S_D
+ { 912, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #912 = CLT_S_H
+ { 913, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #913 = CLT_S_W
+ { 914, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #914 = CLT_U_B
+ { 915, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #915 = CLT_U_D
+ { 916, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #916 = CLT_U_H
+ { 917, 3, 1, 4, 531, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #917 = CLT_U_W
+ { 918, 2, 1, 4, 456, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #918 = CLZ
+ { 919, 2, 1, 4, 65, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #919 = CLZ_MM
+ { 920, 2, 1, 4, 65, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #920 = CLZ_MMR6
+ { 921, 2, 1, 4, 65, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #921 = CLZ_R6
+ { 922, 3, 1, 4, 815, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #922 = CMPGDU_EQ_QB
+ { 923, 3, 1, 4, 978, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #923 = CMPGDU_EQ_QB_MMR2
+ { 924, 3, 1, 4, 816, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #924 = CMPGDU_LE_QB
+ { 925, 3, 1, 4, 979, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #925 = CMPGDU_LE_QB_MMR2
+ { 926, 3, 1, 4, 817, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #926 = CMPGDU_LT_QB
+ { 927, 3, 1, 4, 980, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo194, -1 ,nullptr }, // Inst #927 = CMPGDU_LT_QB_MMR2
+ { 928, 3, 1, 4, 714, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #928 = CMPGU_EQ_QB
+ { 929, 3, 1, 4, 861, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #929 = CMPGU_EQ_QB_MM
+ { 930, 3, 1, 4, 715, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #930 = CMPGU_LE_QB
+ { 931, 3, 1, 4, 862, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #931 = CMPGU_LE_QB_MM
+ { 932, 3, 1, 4, 716, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #932 = CMPGU_LT_QB
+ { 933, 3, 1, 4, 863, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #933 = CMPGU_LT_QB_MM
+ { 934, 2, 0, 4, 717, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #934 = CMPU_EQ_QB
+ { 935, 2, 0, 4, 864, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #935 = CMPU_EQ_QB_MM
+ { 936, 2, 0, 4, 718, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #936 = CMPU_LE_QB
+ { 937, 2, 0, 4, 865, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #937 = CMPU_LE_QB_MM
+ { 938, 2, 0, 4, 719, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #938 = CMPU_LT_QB
+ { 939, 2, 0, 4, 866, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #939 = CMPU_LT_QB_MM
+ { 940, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #940 = CMP_AF_D_MMR6
+ { 941, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #941 = CMP_AF_S_MMR6
+ { 942, 3, 1, 4, 538, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #942 = CMP_EQ_D
+ { 943, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #943 = CMP_EQ_D_MMR6
+ { 944, 2, 0, 4, 720, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #944 = CMP_EQ_PH
+ { 945, 2, 0, 4, 867, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #945 = CMP_EQ_PH_MM
+ { 946, 3, 1, 4, 539, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #946 = CMP_EQ_S
+ { 947, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #947 = CMP_EQ_S_MMR6
+ { 948, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #948 = CMP_F_D
+ { 949, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #949 = CMP_F_S
+ { 950, 3, 1, 4, 544, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #950 = CMP_LE_D
+ { 951, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #951 = CMP_LE_D_MMR6
+ { 952, 2, 0, 4, 721, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #952 = CMP_LE_PH
+ { 953, 2, 0, 4, 868, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #953 = CMP_LE_PH_MM
+ { 954, 3, 1, 4, 545, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #954 = CMP_LE_S
+ { 955, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #955 = CMP_LE_S_MMR6
+ { 956, 3, 1, 4, 540, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #956 = CMP_LT_D
+ { 957, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #957 = CMP_LT_D_MMR6
+ { 958, 2, 0, 4, 722, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #958 = CMP_LT_PH
+ { 959, 2, 0, 4, 869, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo146, -1 ,nullptr }, // Inst #959 = CMP_LT_PH_MM
+ { 960, 3, 1, 4, 541, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #960 = CMP_LT_S
+ { 961, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #961 = CMP_LT_S_MMR6
+ { 962, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #962 = CMP_SAF_D
+ { 963, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #963 = CMP_SAF_D_MMR6
+ { 964, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #964 = CMP_SAF_S
+ { 965, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #965 = CMP_SAF_S_MMR6
+ { 966, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #966 = CMP_SEQ_D
+ { 967, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #967 = CMP_SEQ_D_MMR6
+ { 968, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #968 = CMP_SEQ_S
+ { 969, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #969 = CMP_SEQ_S_MMR6
+ { 970, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #970 = CMP_SLE_D
+ { 971, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #971 = CMP_SLE_D_MMR6
+ { 972, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #972 = CMP_SLE_S
+ { 973, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #973 = CMP_SLE_S_MMR6
+ { 974, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #974 = CMP_SLT_D
+ { 975, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #975 = CMP_SLT_D_MMR6
+ { 976, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #976 = CMP_SLT_S
+ { 977, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #977 = CMP_SLT_S_MMR6
+ { 978, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #978 = CMP_SUEQ_D
+ { 979, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #979 = CMP_SUEQ_D_MMR6
+ { 980, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #980 = CMP_SUEQ_S
+ { 981, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #981 = CMP_SUEQ_S_MMR6
+ { 982, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #982 = CMP_SULE_D
+ { 983, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #983 = CMP_SULE_D_MMR6
+ { 984, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #984 = CMP_SULE_S
+ { 985, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #985 = CMP_SULE_S_MMR6
+ { 986, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #986 = CMP_SULT_D
+ { 987, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #987 = CMP_SULT_D_MMR6
+ { 988, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #988 = CMP_SULT_S
+ { 989, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #989 = CMP_SULT_S_MMR6
+ { 990, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #990 = CMP_SUN_D
+ { 991, 3, 1, 4, 66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #991 = CMP_SUN_D_MMR6
+ { 992, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #992 = CMP_SUN_S
+ { 993, 3, 1, 4, 67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #993 = CMP_SUN_S_MMR6
+ { 994, 3, 1, 4, 536, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #994 = CMP_UEQ_D
+ { 995, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #995 = CMP_UEQ_D_MMR6
+ { 996, 3, 1, 4, 537, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #996 = CMP_UEQ_S
+ { 997, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #997 = CMP_UEQ_S_MMR6
+ { 998, 3, 1, 4, 546, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #998 = CMP_ULE_D
+ { 999, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #999 = CMP_ULE_D_MMR6
+ { 1000, 3, 1, 4, 547, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1000 = CMP_ULE_S
+ { 1001, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1001 = CMP_ULE_S_MMR6
+ { 1002, 3, 1, 4, 542, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1002 = CMP_ULT_D
+ { 1003, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1003 = CMP_ULT_D_MMR6
+ { 1004, 3, 1, 4, 543, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1004 = CMP_ULT_S
+ { 1005, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1005 = CMP_ULT_S_MMR6
+ { 1006, 3, 1, 4, 534, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1006 = CMP_UN_D
+ { 1007, 3, 1, 4, 66, 0, 0x16ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1007 = CMP_UN_D_MMR6
+ { 1008, 3, 1, 4, 535, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1008 = CMP_UN_S
+ { 1009, 3, 1, 4, 67, 0, 0x16ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1009 = CMP_UN_S_MMR6
+ { 1010, 3, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1010 = COPY_S_B
+ { 1011, 3, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1011 = COPY_S_D
+ { 1012, 3, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1012 = COPY_S_H
+ { 1013, 3, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1013 = COPY_S_W
+ { 1014, 3, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1014 = COPY_U_B
+ { 1015, 3, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1015 = COPY_U_H
+ { 1016, 3, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1016 = COPY_U_W
+ { 1017, 3, 1, 4, 68, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1017 = CRC32B
+ { 1018, 3, 1, 4, 69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1018 = CRC32CB
+ { 1019, 3, 1, 4, 70, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1019 = CRC32CD
+ { 1020, 3, 1, 4, 71, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1020 = CRC32CH
+ { 1021, 3, 1, 4, 72, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1021 = CRC32CW
+ { 1022, 3, 1, 4, 73, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1022 = CRC32D
+ { 1023, 3, 1, 4, 74, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1023 = CRC32H
+ { 1024, 3, 1, 4, 75, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1024 = CRC32W
+ { 1025, 2, 1, 4, 657, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1025 = CTC1
+ { 1026, 2, 1, 4, 76, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1026 = CTC1_MM
+ { 1027, 2, 1, 4, 77, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1027 = CTC2_MM
+ { 1028, 2, 0, 4, 509, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1028 = CTCMSA
+ { 1029, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1029 = CVT_D32_S
+ { 1030, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1030 = CVT_D32_S_MM
+ { 1031, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1031 = CVT_D32_W
+ { 1032, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1032 = CVT_D32_W_MM
+ { 1033, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1033 = CVT_D64_L
+ { 1034, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1034 = CVT_D64_S
+ { 1035, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1035 = CVT_D64_S_MM
+ { 1036, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1036 = CVT_D64_W
+ { 1037, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1037 = CVT_D64_W_MM
+ { 1038, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1038 = CVT_D_L_MMR6
+ { 1039, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1039 = CVT_L_D64
+ { 1040, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1040 = CVT_L_D64_MM
+ { 1041, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1041 = CVT_L_D_MMR6
+ { 1042, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1042 = CVT_L_S
+ { 1043, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1043 = CVT_L_S_MM
+ { 1044, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1044 = CVT_L_S_MMR6
+ { 1045, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1045 = CVT_S_D32
+ { 1046, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1046 = CVT_S_D32_MM
+ { 1047, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1047 = CVT_S_D64
+ { 1048, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1048 = CVT_S_D64_MM
+ { 1049, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1049 = CVT_S_L
+ { 1050, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1050 = CVT_S_L_MMR6
+ { 1051, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1051 = CVT_S_W
+ { 1052, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1052 = CVT_S_W_MM
+ { 1053, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1053 = CVT_S_W_MMR6
+ { 1054, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1054 = CVT_W_D32
+ { 1055, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1055 = CVT_W_D32_MM
+ { 1056, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1056 = CVT_W_D64
+ { 1057, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1057 = CVT_W_D64_MM
+ { 1058, 2, 1, 4, 612, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1058 = CVT_W_S
+ { 1059, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1059 = CVT_W_S_MM
+ { 1060, 2, 1, 4, 7, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1060 = CVT_W_S_MMR6
+ { 1061, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1061 = C_EQ_D32
+ { 1062, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1062 = C_EQ_D32_MM
+ { 1063, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1063 = C_EQ_D64
+ { 1064, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1064 = C_EQ_D64_MM
+ { 1065, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1065 = C_EQ_S
+ { 1066, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1066 = C_EQ_S_MM
+ { 1067, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1067 = C_F_D32
+ { 1068, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1068 = C_F_D32_MM
+ { 1069, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1069 = C_F_D64
+ { 1070, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1070 = C_F_D64_MM
+ { 1071, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1071 = C_F_S
+ { 1072, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1072 = C_F_S_MM
+ { 1073, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1073 = C_LE_D32
+ { 1074, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1074 = C_LE_D32_MM
+ { 1075, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1075 = C_LE_D64
+ { 1076, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1076 = C_LE_D64_MM
+ { 1077, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1077 = C_LE_S
+ { 1078, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1078 = C_LE_S_MM
+ { 1079, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1079 = C_LT_D32
+ { 1080, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1080 = C_LT_D32_MM
+ { 1081, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1081 = C_LT_D64
+ { 1082, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1082 = C_LT_D64_MM
+ { 1083, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1083 = C_LT_S
+ { 1084, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1084 = C_LT_S_MM
+ { 1085, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1085 = C_NGE_D32
+ { 1086, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1086 = C_NGE_D32_MM
+ { 1087, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1087 = C_NGE_D64
+ { 1088, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1088 = C_NGE_D64_MM
+ { 1089, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1089 = C_NGE_S
+ { 1090, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1090 = C_NGE_S_MM
+ { 1091, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1091 = C_NGLE_D32
+ { 1092, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1092 = C_NGLE_D32_MM
+ { 1093, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1093 = C_NGLE_D64
+ { 1094, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1094 = C_NGLE_D64_MM
+ { 1095, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1095 = C_NGLE_S
+ { 1096, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1096 = C_NGLE_S_MM
+ { 1097, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1097 = C_NGL_D32
+ { 1098, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1098 = C_NGL_D32_MM
+ { 1099, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1099 = C_NGL_D64
+ { 1100, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1100 = C_NGL_D64_MM
+ { 1101, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1101 = C_NGL_S
+ { 1102, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1102 = C_NGL_S_MM
+ { 1103, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1103 = C_NGT_D32
+ { 1104, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1104 = C_NGT_D32_MM
+ { 1105, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1105 = C_NGT_D64
+ { 1106, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1106 = C_NGT_D64_MM
+ { 1107, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1107 = C_NGT_S
+ { 1108, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1108 = C_NGT_S_MM
+ { 1109, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1109 = C_OLE_D32
+ { 1110, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1110 = C_OLE_D32_MM
+ { 1111, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1111 = C_OLE_D64
+ { 1112, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1112 = C_OLE_D64_MM
+ { 1113, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1113 = C_OLE_S
+ { 1114, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1114 = C_OLE_S_MM
+ { 1115, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1115 = C_OLT_D32
+ { 1116, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1116 = C_OLT_D32_MM
+ { 1117, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1117 = C_OLT_D64
+ { 1118, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1118 = C_OLT_D64_MM
+ { 1119, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1119 = C_OLT_S
+ { 1120, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1120 = C_OLT_S_MM
+ { 1121, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1121 = C_SEQ_D32
+ { 1122, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1122 = C_SEQ_D32_MM
+ { 1123, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1123 = C_SEQ_D64
+ { 1124, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1124 = C_SEQ_D64_MM
+ { 1125, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1125 = C_SEQ_S
+ { 1126, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1126 = C_SEQ_S_MM
+ { 1127, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1127 = C_SF_D32
+ { 1128, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1128 = C_SF_D32_MM
+ { 1129, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1129 = C_SF_D64
+ { 1130, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1130 = C_SF_D64_MM
+ { 1131, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1131 = C_SF_S
+ { 1132, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1132 = C_SF_S_MM
+ { 1133, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1133 = C_UEQ_D32
+ { 1134, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1134 = C_UEQ_D32_MM
+ { 1135, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1135 = C_UEQ_D64
+ { 1136, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1136 = C_UEQ_D64_MM
+ { 1137, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1137 = C_UEQ_S
+ { 1138, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1138 = C_UEQ_S_MM
+ { 1139, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1139 = C_ULE_D32
+ { 1140, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1140 = C_ULE_D32_MM
+ { 1141, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1141 = C_ULE_D64
+ { 1142, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1142 = C_ULE_D64_MM
+ { 1143, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1143 = C_ULE_S
+ { 1144, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1144 = C_ULE_S_MM
+ { 1145, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1145 = C_ULT_D32
+ { 1146, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1146 = C_ULT_D32_MM
+ { 1147, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1147 = C_ULT_D64
+ { 1148, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1148 = C_ULT_D64_MM
+ { 1149, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1149 = C_ULT_S
+ { 1150, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1150 = C_ULT_S_MM
+ { 1151, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1151 = C_UN_D32
+ { 1152, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1152 = C_UN_D32_MM
+ { 1153, 3, 1, 4, 613, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1153 = C_UN_D64
+ { 1154, 3, 1, 4, 78, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1154 = C_UN_D64_MM
+ { 1155, 3, 1, 4, 614, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1155 = C_UN_S
+ { 1156, 3, 1, 4, 79, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1156 = C_UN_S_MM
+ { 1157, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo111, -1 ,nullptr }, // Inst #1157 = CmpRxRy16
+ { 1158, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #1158 = CmpiRxImm16
+ { 1159, 2, 0, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #1159 = CmpiRxImmX16
+ { 1160, 3, 1, 4, 80, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1160 = DADD
+ { 1161, 3, 1, 4, 81, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1161 = DADDi
+ { 1162, 3, 1, 4, 82, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1162 = DADDiu
+ { 1163, 3, 1, 4, 83, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1163 = DADDu
+ { 1164, 3, 1, 4, 84, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1164 = DAHI
+ { 1165, 4, 1, 4, 85, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1165 = DALIGN
+ { 1166, 3, 1, 4, 86, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1166 = DATI
+ { 1167, 3, 1, 4, 87, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1167 = DAUI
+ { 1168, 2, 1, 4, 88, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1168 = DBITSWAP
+ { 1169, 2, 1, 4, 89, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1169 = DCLO
+ { 1170, 2, 1, 4, 89, 0, 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1170 = DCLO_R6
+ { 1171, 2, 1, 4, 90, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1171 = DCLZ
+ { 1172, 2, 1, 4, 90, 0, 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1172 = DCLZ_R6
+ { 1173, 3, 1, 4, 10, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1173 = DDIV
+ { 1174, 3, 1, 4, 11, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1174 = DDIVU
+ { 1175, 0, 0, 4, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1175 = DERET
+ { 1176, 0, 0, 4, 91, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1176 = DERET_MM
+ { 1177, 0, 0, 4, 91, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1177 = DERET_MMR6
+ { 1178, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1178 = DEXT
+ { 1179, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1179 = DEXT64_32
+ { 1180, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1180 = DEXTM
+ { 1181, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1181 = DEXTU
+ { 1182, 1, 1, 4, 457, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1182 = DI
+ { 1183, 5, 1, 4, 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1183 = DINS
+ { 1184, 5, 1, 4, 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1184 = DINSM
+ { 1185, 5, 1, 4, 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1185 = DINSU
+ { 1186, 3, 1, 4, 465, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1186 = DIV
+ { 1187, 3, 1, 4, 466, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1187 = DIVU
+ { 1188, 3, 1, 4, 23, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1188 = DIVU_MMR6
+ { 1189, 3, 1, 4, 22, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1189 = DIV_MMR6
+ { 1190, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1190 = DIV_S_B
+ { 1191, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1191 = DIV_S_D
+ { 1192, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1192 = DIV_S_H
+ { 1193, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1193 = DIV_S_W
+ { 1194, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1194 = DIV_U_B
+ { 1195, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1195 = DIV_U_D
+ { 1196, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1196 = DIV_U_H
+ { 1197, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1197 = DIV_U_W
+ { 1198, 1, 1, 4, 93, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1198 = DI_MM
+ { 1199, 1, 1, 4, 93, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1199 = DI_MMR6
+ { 1200, 4, 1, 4, 94, 0, 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1200 = DLSA
+ { 1201, 4, 1, 4, 94, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1201 = DLSA_R6
+ { 1202, 3, 1, 4, 95, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1202 = DMFC0
+ { 1203, 2, 1, 4, 96, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1203 = DMFC1
+ { 1204, 3, 1, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1204 = DMFC2
+ { 1205, 2, 2, 4, 97, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1205 = DMFC2_OCTEON
+ { 1206, 3, 1, 4, 98, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1206 = DMFGC0
+ { 1207, 3, 1, 4, 99, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1207 = DMOD
+ { 1208, 3, 1, 4, 100, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1208 = DMODU
+ { 1209, 1, 1, 4, 101, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1209 = DMT
+ { 1210, 3, 1, 4, 102, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1210 = DMTC0
+ { 1211, 2, 1, 4, 103, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1211 = DMTC1
+ { 1212, 3, 1, 4, 104, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1212 = DMTC2
+ { 1213, 2, 2, 4, 104, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1213 = DMTC2_OCTEON
+ { 1214, 3, 1, 4, 105, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1214 = DMTGC0
+ { 1215, 3, 1, 4, 106, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1215 = DMUH
+ { 1216, 3, 1, 4, 107, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1216 = DMUHU
+ { 1217, 3, 1, 4, 108, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList11, OperandInfo57, -1 ,nullptr }, // Inst #1217 = DMUL
+ { 1218, 2, 0, 4, 8, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1218 = DMULT
+ { 1219, 2, 0, 4, 9, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1219 = DMULTu
+ { 1220, 3, 1, 4, 108, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1220 = DMULU
+ { 1221, 3, 1, 4, 108, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1221 = DMUL_R6
+ { 1222, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1222 = DOTP_S_D
+ { 1223, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1223 = DOTP_S_H
+ { 1224, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1224 = DOTP_S_W
+ { 1225, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1225 = DOTP_U_D
+ { 1226, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1226 = DOTP_U_H
+ { 1227, 3, 1, 4, 639, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1227 = DOTP_U_W
+ { 1228, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1228 = DPADD_S_D
+ { 1229, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1229 = DPADD_S_H
+ { 1230, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1230 = DPADD_S_W
+ { 1231, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1231 = DPADD_U_D
+ { 1232, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1232 = DPADD_U_H
+ { 1233, 4, 1, 4, 637, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1233 = DPADD_U_W
+ { 1234, 4, 1, 4, 819, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1234 = DPAQX_SA_W_PH
+ { 1235, 4, 1, 4, 982, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1235 = DPAQX_SA_W_PH_MMR2
+ { 1236, 4, 1, 4, 820, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1236 = DPAQX_S_W_PH
+ { 1237, 4, 1, 4, 983, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1237 = DPAQX_S_W_PH_MMR2
+ { 1238, 4, 1, 4, 723, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1238 = DPAQ_SA_L_W
+ { 1239, 4, 1, 4, 870, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1239 = DPAQ_SA_L_W_MM
+ { 1240, 4, 1, 4, 724, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1240 = DPAQ_S_W_PH
+ { 1241, 4, 1, 4, 871, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1241 = DPAQ_S_W_PH_MM
+ { 1242, 4, 1, 4, 725, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1242 = DPAU_H_QBL
+ { 1243, 4, 1, 4, 872, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1243 = DPAU_H_QBL_MM
+ { 1244, 4, 1, 4, 726, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1244 = DPAU_H_QBR
+ { 1245, 4, 1, 4, 873, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1245 = DPAU_H_QBR_MM
+ { 1246, 4, 1, 4, 821, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1246 = DPAX_W_PH
+ { 1247, 4, 1, 4, 984, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1247 = DPAX_W_PH_MMR2
+ { 1248, 4, 1, 4, 818, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1248 = DPA_W_PH
+ { 1249, 4, 1, 4, 981, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1249 = DPA_W_PH_MMR2
+ { 1250, 2, 1, 4, 109, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1250 = DPOP
+ { 1251, 4, 1, 4, 824, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1251 = DPSQX_SA_W_PH
+ { 1252, 4, 1, 4, 987, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1252 = DPSQX_SA_W_PH_MMR2
+ { 1253, 4, 1, 4, 823, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1253 = DPSQX_S_W_PH
+ { 1254, 4, 1, 4, 986, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1254 = DPSQX_S_W_PH_MMR2
+ { 1255, 4, 1, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1255 = DPSQ_SA_L_W
+ { 1256, 4, 1, 4, 874, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1256 = DPSQ_SA_L_W_MM
+ { 1257, 4, 1, 4, 728, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1257 = DPSQ_S_W_PH
+ { 1258, 4, 1, 4, 875, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1258 = DPSQ_S_W_PH_MM
+ { 1259, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1259 = DPSUB_S_D
+ { 1260, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1260 = DPSUB_S_H
+ { 1261, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1261 = DPSUB_S_W
+ { 1262, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1262 = DPSUB_U_D
+ { 1263, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1263 = DPSUB_U_H
+ { 1264, 4, 1, 4, 638, 0, 0x6ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1264 = DPSUB_U_W
+ { 1265, 4, 1, 4, 729, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1265 = DPSU_H_QBL
+ { 1266, 4, 1, 4, 876, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1266 = DPSU_H_QBL_MM
+ { 1267, 4, 1, 4, 730, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1267 = DPSU_H_QBR
+ { 1268, 4, 1, 4, 877, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1268 = DPSU_H_QBR_MM
+ { 1269, 4, 1, 4, 825, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1269 = DPSX_W_PH
+ { 1270, 4, 1, 4, 988, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1270 = DPSX_W_PH_MMR2
+ { 1271, 4, 1, 4, 822, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1271 = DPS_W_PH
+ { 1272, 4, 1, 4, 985, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1272 = DPS_W_PH_MMR2
+ { 1273, 3, 1, 4, 110, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1273 = DROTR
+ { 1274, 3, 1, 4, 111, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1274 = DROTR32
+ { 1275, 3, 1, 4, 112, 0, 0x1ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1275 = DROTRV
+ { 1276, 2, 1, 4, 113, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1276 = DSBH
+ { 1277, 2, 0, 4, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1277 = DSDIV
+ { 1278, 2, 1, 4, 114, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1278 = DSHD
+ { 1279, 3, 1, 4, 115, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1279 = DSLL
+ { 1280, 3, 1, 4, 116, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1280 = DSLL32
+ { 1281, 2, 1, 4, 115, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1281 = DSLL64_32
+ { 1282, 3, 1, 4, 117, 0, 0x1ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1282 = DSLLV
+ { 1283, 3, 1, 4, 118, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1283 = DSRA
+ { 1284, 3, 1, 4, 119, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1284 = DSRA32
+ { 1285, 3, 1, 4, 120, 0, 0x1ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1285 = DSRAV
+ { 1286, 3, 1, 4, 121, 0, 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1286 = DSRL
+ { 1287, 3, 1, 4, 122, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #1287 = DSRL32
+ { 1288, 3, 1, 4, 123, 0, 0x1ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1288 = DSRLV
+ { 1289, 3, 1, 4, 124, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1289 = DSUB
+ { 1290, 3, 1, 4, 125, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #1290 = DSUBu
+ { 1291, 2, 0, 4, 11, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo103, -1 ,nullptr }, // Inst #1291 = DUDIV
+ { 1292, 1, 1, 4, 126, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1292 = DVP
+ { 1293, 1, 1, 4, 127, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1293 = DVPE
+ { 1294, 1, 1, 4, 126, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1294 = DVP_MMR6
+ { 1295, 2, 0, 2, 38, 0, 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr }, // Inst #1295 = DivRxRy16
+ { 1296, 2, 0, 2, 38, 0, 0x0ULL, nullptr, ImplicitList6, OperandInfo111, -1 ,nullptr }, // Inst #1296 = DivuRxRy16
+ { 1297, 0, 0, 4, 460, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1297 = EHB
+ { 1298, 0, 0, 4, 128, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1298 = EHB_MM
+ { 1299, 0, 0, 4, 128, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1299 = EHB_MMR6
+ { 1300, 1, 1, 4, 458, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1300 = EI
+ { 1301, 1, 1, 4, 129, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1301 = EI_MM
+ { 1302, 1, 1, 4, 129, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1302 = EI_MMR6
+ { 1303, 1, 1, 4, 130, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1303 = EMT
+ { 1304, 0, 0, 4, 373, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1304 = ERET
+ { 1305, 0, 0, 4, 374, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1305 = ERETNC
+ { 1306, 0, 0, 4, 132, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1306 = ERETNC_MMR6
+ { 1307, 0, 0, 4, 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1307 = ERET_MM
+ { 1308, 0, 0, 4, 131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1308 = ERET_MMR6
+ { 1309, 1, 1, 4, 133, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1309 = EVP
+ { 1310, 1, 1, 4, 134, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1310 = EVPE
+ { 1311, 1, 1, 4, 133, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1311 = EVP_MMR6
+ { 1312, 4, 1, 4, 475, 0, 0x1ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1312 = EXT
+ { 1313, 3, 1, 4, 734, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo225, -1 ,nullptr }, // Inst #1313 = EXTP
+ { 1314, 3, 1, 4, 732, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo225, -1 ,nullptr }, // Inst #1314 = EXTPDP
+ { 1315, 3, 1, 4, 731, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo226, -1 ,nullptr }, // Inst #1315 = EXTPDPV
+ { 1316, 3, 1, 4, 878, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo226, -1 ,nullptr }, // Inst #1316 = EXTPDPV_MM
+ { 1317, 3, 1, 4, 879, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo225, -1 ,nullptr }, // Inst #1317 = EXTPDP_MM
+ { 1318, 3, 1, 4, 733, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo226, -1 ,nullptr }, // Inst #1318 = EXTPV
+ { 1319, 3, 1, 4, 880, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo226, -1 ,nullptr }, // Inst #1319 = EXTPV_MM
+ { 1320, 3, 1, 4, 881, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo225, -1 ,nullptr }, // Inst #1320 = EXTP_MM
+ { 1321, 3, 1, 4, 691, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1321 = EXTRV_RS_W
+ { 1322, 3, 1, 4, 882, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1322 = EXTRV_RS_W_MM
+ { 1323, 3, 1, 4, 692, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1323 = EXTRV_R_W
+ { 1324, 3, 1, 4, 883, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1324 = EXTRV_R_W_MM
+ { 1325, 3, 1, 4, 693, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1325 = EXTRV_S_H
+ { 1326, 3, 1, 4, 884, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1326 = EXTRV_S_H_MM
+ { 1327, 3, 1, 4, 694, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1327 = EXTRV_W
+ { 1328, 3, 1, 4, 885, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo226, -1 ,nullptr }, // Inst #1328 = EXTRV_W_MM
+ { 1329, 3, 1, 4, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1329 = EXTR_RS_W
+ { 1330, 3, 1, 4, 886, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1330 = EXTR_RS_W_MM
+ { 1331, 3, 1, 4, 696, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1331 = EXTR_R_W
+ { 1332, 3, 1, 4, 887, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1332 = EXTR_R_W_MM
+ { 1333, 3, 1, 4, 697, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1333 = EXTR_S_H
+ { 1334, 3, 1, 4, 888, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1334 = EXTR_S_H_MM
+ { 1335, 3, 1, 4, 698, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1335 = EXTR_W
+ { 1336, 3, 1, 4, 889, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo225, -1 ,nullptr }, // Inst #1336 = EXTR_W_MM
+ { 1337, 4, 1, 4, 92, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1337 = EXTS
+ { 1338, 4, 1, 4, 92, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1338 = EXTS32
+ { 1339, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1339 = EXT_MM
+ { 1340, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1340 = EXT_MMR6
+ { 1341, 2, 1, 4, 510, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1341 = FABS_D32
+ { 1342, 2, 1, 4, 136, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1342 = FABS_D32_MM
+ { 1343, 2, 1, 4, 510, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1343 = FABS_D64
+ { 1344, 2, 1, 4, 136, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1344 = FABS_D64_MM
+ { 1345, 2, 1, 4, 510, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1345 = FABS_S
+ { 1346, 2, 1, 4, 135, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1346 = FABS_S_MM
+ { 1347, 3, 1, 4, 635, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1347 = FADD_D
+ { 1348, 3, 1, 4, 605, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1348 = FADD_D32
+ { 1349, 3, 1, 4, 137, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1349 = FADD_D32_MM
+ { 1350, 3, 1, 4, 605, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1350 = FADD_D64
+ { 1351, 3, 1, 4, 137, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1351 = FADD_D64_MM
+ { 1352, 3, 1, 4, 606, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1352 = FADD_S
+ { 1353, 3, 1, 4, 138, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1353 = FADD_S_MM
+ { 1354, 3, 1, 4, 138, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1354 = FADD_S_MMR6
+ { 1355, 3, 1, 4, 635, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1355 = FADD_W
+ { 1356, 3, 1, 4, 554, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1356 = FCAF_D
+ { 1357, 3, 1, 4, 554, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1357 = FCAF_W
+ { 1358, 3, 1, 4, 555, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1358 = FCEQ_D
+ { 1359, 3, 1, 4, 555, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1359 = FCEQ_W
+ { 1360, 2, 1, 4, 576, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1360 = FCLASS_D
+ { 1361, 2, 1, 4, 576, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1361 = FCLASS_W
+ { 1362, 3, 1, 4, 556, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1362 = FCLE_D
+ { 1363, 3, 1, 4, 556, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1363 = FCLE_W
+ { 1364, 3, 1, 4, 557, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1364 = FCLT_D
+ { 1365, 3, 1, 4, 557, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1365 = FCLT_W
+ { 1366, 3, 0, 4, 615, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo231, -1 ,nullptr }, // Inst #1366 = FCMP_D32
+ { 1367, 3, 0, 4, 78, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo231, -1 ,nullptr }, // Inst #1367 = FCMP_D32_MM
+ { 1368, 3, 0, 4, 615, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo232, -1 ,nullptr }, // Inst #1368 = FCMP_D64
+ { 1369, 3, 0, 4, 616, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo233, -1 ,nullptr }, // Inst #1369 = FCMP_S32
+ { 1370, 3, 0, 4, 79, 0, 0x84ULL, nullptr, ImplicitList17, OperandInfo233, -1 ,nullptr }, // Inst #1370 = FCMP_S32_MM
+ { 1371, 3, 1, 4, 558, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1371 = FCNE_D
+ { 1372, 3, 1, 4, 558, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1372 = FCNE_W
+ { 1373, 3, 1, 4, 559, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1373 = FCOR_D
+ { 1374, 3, 1, 4, 559, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1374 = FCOR_W
+ { 1375, 3, 1, 4, 560, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1375 = FCUEQ_D
+ { 1376, 3, 1, 4, 560, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1376 = FCUEQ_W
+ { 1377, 3, 1, 4, 561, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1377 = FCULE_D
+ { 1378, 3, 1, 4, 561, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1378 = FCULE_W
+ { 1379, 3, 1, 4, 562, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1379 = FCULT_D
+ { 1380, 3, 1, 4, 562, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1380 = FCULT_W
+ { 1381, 3, 1, 4, 563, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1381 = FCUNE_D
+ { 1382, 3, 1, 4, 563, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1382 = FCUNE_W
+ { 1383, 3, 1, 4, 564, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1383 = FCUN_D
+ { 1384, 3, 1, 4, 564, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1384 = FCUN_W
+ { 1385, 3, 1, 4, 631, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1385 = FDIV_D
+ { 1386, 3, 1, 4, 619, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1386 = FDIV_D32
+ { 1387, 3, 1, 4, 139, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1387 = FDIV_D32_MM
+ { 1388, 3, 1, 4, 619, 0, 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1388 = FDIV_D64
+ { 1389, 3, 1, 4, 139, 0, 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1389 = FDIV_D64_MM
+ { 1390, 3, 1, 4, 618, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1390 = FDIV_S
+ { 1391, 3, 1, 4, 140, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1391 = FDIV_S_MM
+ { 1392, 3, 1, 4, 140, 0, 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1392 = FDIV_S_MMR6
+ { 1393, 3, 1, 4, 630, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1393 = FDIV_W
+ { 1394, 3, 1, 4, 573, 0, 0x6ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1394 = FEXDO_H
+ { 1395, 3, 1, 4, 573, 0, 0x6ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1395 = FEXDO_W
+ { 1396, 3, 1, 4, 530, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1396 = FEXP2_D
+ { 1397, 3, 1, 4, 530, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1397 = FEXP2_W
+ { 1398, 2, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1398 = FEXUPL_D
+ { 1399, 2, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1399 = FEXUPL_W
+ { 1400, 2, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1400 = FEXUPR_D
+ { 1401, 2, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1401 = FEXUPR_W
+ { 1402, 2, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1402 = FFINT_S_D
+ { 1403, 2, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1403 = FFINT_S_W
+ { 1404, 2, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1404 = FFINT_U_D
+ { 1405, 2, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1405 = FFINT_U_W
+ { 1406, 2, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1406 = FFQL_D
+ { 1407, 2, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1407 = FFQL_W
+ { 1408, 2, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #1408 = FFQR_D
+ { 1409, 2, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #1409 = FFQR_W
+ { 1410, 2, 1, 4, 524, 0, 0x6ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1410 = FILL_B
+ { 1411, 2, 1, 4, 524, 0, 0x6ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1411 = FILL_D
+ { 1412, 2, 1, 4, 524, 0, 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1412 = FILL_H
+ { 1413, 2, 1, 4, 524, 0, 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1413 = FILL_W
+ { 1414, 2, 1, 4, 581, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1414 = FLOG2_D
+ { 1415, 2, 1, 4, 581, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1415 = FLOG2_W
+ { 1416, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1416 = FLOOR_L_D64
+ { 1417, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1417 = FLOOR_L_D_MMR6
+ { 1418, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1418 = FLOOR_L_S
+ { 1419, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1419 = FLOOR_L_S_MMR6
+ { 1420, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1420 = FLOOR_W_D32
+ { 1421, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1421 = FLOOR_W_D64
+ { 1422, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1422 = FLOOR_W_D_MMR6
+ { 1423, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1423 = FLOOR_W_MM
+ { 1424, 2, 1, 4, 688, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1424 = FLOOR_W_S
+ { 1425, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1425 = FLOOR_W_S_MM
+ { 1426, 2, 1, 4, 141, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1426 = FLOOR_W_S_MMR6
+ { 1427, 4, 1, 4, 628, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #1427 = FMADD_D
+ { 1428, 4, 1, 4, 628, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1428 = FMADD_W
+ { 1429, 3, 1, 4, 577, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1429 = FMAX_A_D
+ { 1430, 3, 1, 4, 577, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1430 = FMAX_A_W
+ { 1431, 3, 1, 4, 578, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1431 = FMAX_D
+ { 1432, 3, 1, 4, 578, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1432 = FMAX_W
+ { 1433, 3, 1, 4, 579, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1433 = FMIN_A_D
+ { 1434, 3, 1, 4, 579, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1434 = FMIN_A_W
+ { 1435, 3, 1, 4, 580, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1435 = FMIN_D
+ { 1436, 3, 1, 4, 580, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1436 = FMIN_W
+ { 1437, 2, 1, 4, 515, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1437 = FMOV_D32
+ { 1438, 2, 1, 4, 142, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1438 = FMOV_D32_MM
+ { 1439, 2, 1, 4, 515, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1439 = FMOV_D64
+ { 1440, 2, 1, 4, 142, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1440 = FMOV_D64_MM
+ { 1441, 2, 1, 4, 516, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1441 = FMOV_S
+ { 1442, 2, 1, 4, 143, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1442 = FMOV_S_MM
+ { 1443, 2, 1, 4, 143, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1443 = FMOV_S_MMR6
+ { 1444, 4, 1, 4, 629, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #1444 = FMSUB_D
+ { 1445, 4, 1, 4, 629, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1445 = FMSUB_W
+ { 1446, 3, 1, 4, 634, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1446 = FMUL_D
+ { 1447, 3, 1, 4, 607, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1447 = FMUL_D32
+ { 1448, 3, 1, 4, 144, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1448 = FMUL_D32_MM
+ { 1449, 3, 1, 4, 607, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1449 = FMUL_D64
+ { 1450, 3, 1, 4, 144, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1450 = FMUL_D64_MM
+ { 1451, 3, 1, 4, 608, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1451 = FMUL_S
+ { 1452, 3, 1, 4, 145, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1452 = FMUL_S_MM
+ { 1453, 3, 1, 4, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1453 = FMUL_S_MMR6
+ { 1454, 3, 1, 4, 634, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1454 = FMUL_W
+ { 1455, 2, 1, 4, 517, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1455 = FNEG_D32
+ { 1456, 2, 1, 4, 146, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1456 = FNEG_D32_MM
+ { 1457, 2, 1, 4, 517, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1457 = FNEG_D64
+ { 1458, 2, 1, 4, 146, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1458 = FNEG_D64_MM
+ { 1459, 2, 1, 4, 517, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1459 = FNEG_S
+ { 1460, 2, 1, 4, 146, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1460 = FNEG_S_MM
+ { 1461, 2, 1, 4, 146, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1461 = FNEG_S_MMR6
+ { 1462, 3, 2, 4, 147, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1462 = FORK
+ { 1463, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1463 = FRCP_D
+ { 1464, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1464 = FRCP_W
+ { 1465, 2, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1465 = FRINT_D
+ { 1466, 2, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1466 = FRINT_W
+ { 1467, 2, 1, 4, 623, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1467 = FRSQRT_D
+ { 1468, 2, 1, 4, 623, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1468 = FRSQRT_W
+ { 1469, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1469 = FSAF_D
+ { 1470, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1470 = FSAF_W
+ { 1471, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1471 = FSEQ_D
+ { 1472, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1472 = FSEQ_W
+ { 1473, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1473 = FSLE_D
+ { 1474, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1474 = FSLE_W
+ { 1475, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1475 = FSLT_D
+ { 1476, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1476 = FSLT_W
+ { 1477, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1477 = FSNE_D
+ { 1478, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1478 = FSNE_W
+ { 1479, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1479 = FSOR_D
+ { 1480, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1480 = FSOR_W
+ { 1481, 2, 1, 4, 633, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1481 = FSQRT_D
+ { 1482, 2, 1, 4, 621, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1482 = FSQRT_D32
+ { 1483, 2, 1, 4, 136, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1483 = FSQRT_D32_MM
+ { 1484, 2, 1, 4, 621, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1484 = FSQRT_D64
+ { 1485, 2, 1, 4, 136, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1485 = FSQRT_D64_MM
+ { 1486, 2, 1, 4, 620, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1486 = FSQRT_S
+ { 1487, 2, 1, 4, 148, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1487 = FSQRT_S_MM
+ { 1488, 2, 1, 4, 632, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1488 = FSQRT_W
+ { 1489, 3, 1, 4, 636, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1489 = FSUB_D
+ { 1490, 3, 1, 4, 609, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1490 = FSUB_D32
+ { 1491, 3, 1, 4, 149, 0, 0x4ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1491 = FSUB_D32_MM
+ { 1492, 3, 1, 4, 609, 0, 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1492 = FSUB_D64
+ { 1493, 3, 1, 4, 149, 0, 0x4ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1493 = FSUB_D64_MM
+ { 1494, 3, 1, 4, 610, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1494 = FSUB_S
+ { 1495, 3, 1, 4, 150, 0, 0x4ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1495 = FSUB_S_MM
+ { 1496, 3, 1, 4, 150, 0, 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1496 = FSUB_S_MMR6
+ { 1497, 3, 1, 4, 636, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1497 = FSUB_W
+ { 1498, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1498 = FSUEQ_D
+ { 1499, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1499 = FSUEQ_W
+ { 1500, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1500 = FSULE_D
+ { 1501, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1501 = FSULE_W
+ { 1502, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1502 = FSULT_D
+ { 1503, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1503 = FSULT_W
+ { 1504, 3, 1, 4, 552, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1504 = FSUNE_D
+ { 1505, 3, 1, 4, 552, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1505 = FSUNE_W
+ { 1506, 3, 1, 4, 553, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1506 = FSUN_D
+ { 1507, 3, 1, 4, 553, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1507 = FSUN_W
+ { 1508, 2, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1508 = FTINT_S_D
+ { 1509, 2, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1509 = FTINT_S_W
+ { 1510, 2, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1510 = FTINT_U_D
+ { 1511, 2, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1511 = FTINT_U_W
+ { 1512, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1512 = FTQ_H
+ { 1513, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1513 = FTQ_W
+ { 1514, 2, 1, 4, 572, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1514 = FTRUNC_S_D
+ { 1515, 2, 1, 4, 572, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1515 = FTRUNC_S_W
+ { 1516, 2, 1, 4, 572, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #1516 = FTRUNC_U_D
+ { 1517, 2, 1, 4, 572, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1517 = FTRUNC_U_W
+ { 1518, 1, 0, 4, 151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1518 = GINVI
+ { 1519, 1, 0, 4, 151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1519 = GINVI_MMR6
+ { 1520, 2, 0, 4, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1520 = GINVT
+ { 1521, 2, 0, 4, 152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1521 = GINVT_MMR6
+ { 1522, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1522 = HADD_S_D
+ { 1523, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1523 = HADD_S_H
+ { 1524, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1524 = HADD_S_W
+ { 1525, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1525 = HADD_U_D
+ { 1526, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1526 = HADD_U_H
+ { 1527, 3, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1527 = HADD_U_W
+ { 1528, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1528 = HSUB_S_D
+ { 1529, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1529 = HSUB_S_H
+ { 1530, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1530 = HSUB_S_W
+ { 1531, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1531 = HSUB_U_D
+ { 1532, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1532 = HSUB_U_H
+ { 1533, 3, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1533 = HSUB_U_W
+ { 1534, 1, 0, 4, 153, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1534 = HYPCALL
+ { 1535, 1, 0, 4, 153, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1535 = HYPCALL_MM
+ { 1536, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1536 = ILVEV_B
+ { 1537, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1537 = ILVEV_D
+ { 1538, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1538 = ILVEV_H
+ { 1539, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1539 = ILVEV_W
+ { 1540, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1540 = ILVL_B
+ { 1541, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1541 = ILVL_D
+ { 1542, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1542 = ILVL_H
+ { 1543, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1543 = ILVL_W
+ { 1544, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1544 = ILVOD_B
+ { 1545, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1545 = ILVOD_D
+ { 1546, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1546 = ILVOD_H
+ { 1547, 3, 1, 4, 583, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1547 = ILVOD_W
+ { 1548, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1548 = ILVR_B
+ { 1549, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1549 = ILVR_D
+ { 1550, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1550 = ILVR_H
+ { 1551, 3, 1, 4, 582, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1551 = ILVR_W
+ { 1552, 5, 1, 4, 476, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #1552 = INS
+ { 1553, 4, 1, 4, 499, 0, 0x6ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #1553 = INSERT_B
+ { 1554, 4, 1, 4, 499, 0, 0x6ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #1554 = INSERT_D
+ { 1555, 4, 1, 4, 499, 0, 0x6ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1555 = INSERT_H
+ { 1556, 4, 1, 4, 499, 0, 0x6ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1556 = INSERT_W
+ { 1557, 3, 1, 4, 699, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList18, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1557 = INSV
+ { 1558, 5, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1558 = INSVE_B
+ { 1559, 5, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #1559 = INSVE_D
+ { 1560, 5, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1560 = INSVE_H
+ { 1561, 5, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1561 = INSVE_W
+ { 1562, 3, 1, 4, 890, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList18, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1562 = INSV_MM
+ { 1563, 5, 1, 4, 61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #1563 = INS_MM
+ { 1564, 5, 1, 4, 61, 0, 0x1ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #1564 = INS_MMR6
+ { 1565, 1, 0, 4, 375, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1565 = J
+ { 1566, 1, 0, 4, 398, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1566 = JAL
+ { 1567, 2, 1, 4, 399, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #1567 = JALR
+ { 1568, 1, 0, 2, 6, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #1568 = JALR16_MM
+ { 1569, 2, 1, 4, 6, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo103, -1 ,nullptr }, // Inst #1569 = JALR64
+ { 1570, 1, 0, 2, 6, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #1570 = JALRC16_MMR6
+ { 1571, 2, 1, 4, 155, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #1571 = JALRC_HB_MMR6
+ { 1572, 2, 1, 4, 156, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #1572 = JALRC_MMR6
+ { 1573, 1, 0, 2, 157, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo44, -1 ,nullptr }, // Inst #1573 = JALRS16_MM
+ { 1574, 2, 1, 4, 157, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #1574 = JALRS_MM
+ { 1575, 2, 1, 4, 400, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #1575 = JALR_HB
+ { 1576, 2, 1, 4, 155, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1576 = JALR_HB64
+ { 1577, 2, 1, 4, 6, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr }, // Inst #1577 = JALR_MM
+ { 1578, 1, 0, 4, 158, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1578 = JALS_MM
+ { 1579, 1, 0, 4, 401, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1579 = JALX
+ { 1580, 1, 0, 4, 154, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1580 = JALX_MM
+ { 1581, 1, 0, 4, 154, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1581 = JAL_MM
+ { 1582, 2, 0, 4, 159, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo95, -1 ,nullptr }, // Inst #1582 = JIALC
+ { 1583, 2, 0, 4, 159, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo93, -1 ,nullptr }, // Inst #1583 = JIALC64
+ { 1584, 2, 0, 4, 159, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo95, -1 ,nullptr }, // Inst #1584 = JIALC_MMR6
+ { 1585, 2, 0, 4, 159, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #1585 = JIC
+ { 1586, 2, 0, 4, 160, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo93, -1 ,nullptr }, // Inst #1586 = JIC64
+ { 1587, 2, 0, 4, 160, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo95, -1 ,nullptr }, // Inst #1587 = JIC_MMR6
+ { 1588, 1, 0, 4, 376, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1588 = JR
+ { 1589, 1, 0, 2, 25, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1589 = JR16_MM
+ { 1590, 1, 0, 4, 25, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1590 = JR64
+ { 1591, 1, 0, 2, 161, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1591 = JRADDIUSP
+ { 1592, 1, 0, 2, 162, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1592 = JRC16_MM
+ { 1593, 1, 0, 2, 25, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1593 = JRC16_MMR6
+ { 1594, 1, 0, 2, 161, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1594 = JRCADDIUSP_MMR6
+ { 1595, 1, 0, 4, 377, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1595 = JR_HB
+ { 1596, 1, 0, 4, 163, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1596 = JR_HB64
+ { 1597, 1, 0, 4, 163, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1597 = JR_HB64_R6
+ { 1598, 1, 0, 4, 163, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1598 = JR_HB_R6
+ { 1599, 1, 0, 4, 25, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1599 = JR_MM
+ { 1600, 1, 0, 4, 24, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1600 = J_MM
+ { 1601, 1, 0, 6, 38, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1601 = Jal16
+ { 1602, 1, 0, 6, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1602 = JalB16
+ { 1603, 0, 0, 2, 38, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1603 = JrRa16
+ { 1604, 0, 0, 2, 38, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1604 = JrcRa16
+ { 1605, 1, 0, 2, 38, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1605 = JrcRx16
+ { 1606, 1, 0, 2, 156, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo252, -1 ,nullptr }, // Inst #1606 = JumpLinkReg16
+ { 1607, 3, 1, 4, 412, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1607 = LB
+ { 1608, 3, 1, 4, 164, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1608 = LB64
+ { 1609, 3, 1, 4, 422, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1609 = LBE
+ { 1610, 3, 1, 4, 165, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1610 = LBE_MM
+ { 1611, 3, 1, 2, 166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1611 = LBU16_MM
+ { 1612, 3, 1, 4, 735, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1612 = LBUX
+ { 1613, 3, 1, 4, 891, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1613 = LBUX_MM
+ { 1614, 3, 1, 4, 166, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1614 = LBU_MMR6
+ { 1615, 3, 1, 4, 164, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1615 = LB_MM
+ { 1616, 3, 1, 4, 164, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1616 = LB_MMR6
+ { 1617, 3, 1, 4, 413, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1617 = LBu
+ { 1618, 3, 1, 4, 166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1618 = LBu64
+ { 1619, 3, 1, 4, 423, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1619 = LBuE
+ { 1620, 3, 1, 4, 167, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1620 = LBuE_MM
+ { 1621, 3, 1, 4, 166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1621 = LBu_MM
+ { 1622, 3, 1, 4, 168, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1622 = LD
+ { 1623, 3, 1, 4, 681, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1623 = LDC1
+ { 1624, 3, 1, 4, 169, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #1624 = LDC164
+ { 1625, 3, 1, 4, 169, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #1625 = LDC1_D64_MMR6
+ { 1626, 3, 1, 4, 169, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1626 = LDC1_MM
+ { 1627, 3, 1, 4, 420, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1627 = LDC2
+ { 1628, 3, 1, 4, 170, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1628 = LDC2_MMR6
+ { 1629, 3, 1, 4, 170, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1629 = LDC2_R6
+ { 1630, 3, 1, 4, 421, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1630 = LDC3
+ { 1631, 2, 1, 4, 527, 0, 0x6ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1631 = LDI_B
+ { 1632, 2, 1, 4, 527, 0, 0x6ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1632 = LDI_D
+ { 1633, 2, 1, 4, 527, 0, 0x6ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1633 = LDI_H
+ { 1634, 2, 1, 4, 527, 0, 0x6ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1634 = LDI_W
+ { 1635, 4, 1, 4, 172, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1635 = LDL
+ { 1636, 2, 1, 4, 173, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1636 = LDPC
+ { 1637, 4, 1, 4, 174, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1637 = LDR
+ { 1638, 3, 1, 4, 682, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1638 = LDXC1
+ { 1639, 3, 1, 4, 175, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1639 = LDXC164
+ { 1640, 3, 1, 4, 686, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1640 = LD_B
+ { 1641, 3, 1, 4, 686, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1641 = LD_D
+ { 1642, 3, 1, 4, 686, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #1642 = LD_H
+ { 1643, 3, 1, 4, 686, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #1643 = LD_W
+ { 1644, 3, 1, 4, 29, 0, 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1644 = LEA_ADDiu
+ { 1645, 3, 1, 4, 29, 0, 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1645 = LEA_ADDiu64
+ { 1646, 3, 1, 4, 29, 0, 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1646 = LEA_ADDiu_MM
+ { 1647, 3, 1, 4, 414, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1647 = LH
+ { 1648, 3, 1, 4, 176, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1648 = LH64
+ { 1649, 3, 1, 4, 424, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1649 = LHE
+ { 1650, 3, 1, 4, 177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1650 = LHE_MM
+ { 1651, 3, 1, 2, 178, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1651 = LHU16_MM
+ { 1652, 3, 1, 4, 736, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1652 = LHX
+ { 1653, 3, 1, 4, 892, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1653 = LHX_MM
+ { 1654, 3, 1, 4, 176, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1654 = LH_MM
+ { 1655, 3, 1, 4, 415, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1655 = LHu
+ { 1656, 3, 1, 4, 178, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1656 = LHu64
+ { 1657, 3, 1, 4, 425, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1657 = LHuE
+ { 1658, 3, 1, 4, 179, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1658 = LHuE_MM
+ { 1659, 3, 1, 4, 178, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1659 = LHu_MM
+ { 1660, 2, 1, 2, 180, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1660 = LI16_MM
+ { 1661, 2, 1, 2, 180, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1661 = LI16_MMR6
+ { 1662, 3, 1, 4, 417, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1662 = LL
+ { 1663, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1663 = LL64
+ { 1664, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1664 = LL64_R6
+ { 1665, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1665 = LLD
+ { 1666, 3, 1, 4, 182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1666 = LLD_R6
+ { 1667, 3, 1, 4, 427, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1667 = LLE
+ { 1668, 3, 1, 4, 183, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1668 = LLE_MM
+ { 1669, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1669 = LL_MM
+ { 1670, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1670 = LL_MMR6
+ { 1671, 3, 1, 4, 181, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1671 = LL_R6
+ { 1672, 4, 1, 4, 494, 0, 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #1672 = LSA
+ { 1673, 4, 1, 4, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #1673 = LSA_MMR6
+ { 1674, 4, 1, 4, 184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #1674 = LSA_R6
+ { 1675, 2, 1, 4, 185, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1675 = LUI_MMR6
+ { 1676, 3, 1, 4, 685, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1676 = LUXC1
+ { 1677, 3, 1, 4, 186, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1677 = LUXC164
+ { 1678, 3, 1, 4, 186, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1678 = LUXC1_MM
+ { 1679, 2, 1, 4, 359, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1679 = LUi
+ { 1680, 2, 1, 4, 185, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #1680 = LUi64
+ { 1681, 2, 1, 4, 185, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1681 = LUi_MM
+ { 1682, 3, 1, 4, 416, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1682 = LW
+ { 1683, 3, 1, 2, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1683 = LW16_MM
+ { 1684, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1684 = LW64
+ { 1685, 3, 1, 4, 683, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #1685 = LWC1
+ { 1686, 3, 1, 4, 188, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #1686 = LWC1_MM
+ { 1687, 3, 1, 4, 418, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1687 = LWC2
+ { 1688, 3, 1, 4, 189, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1688 = LWC2_MMR6
+ { 1689, 3, 1, 4, 189, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1689 = LWC2_R6
+ { 1690, 3, 1, 4, 419, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1690 = LWC3
+ { 1691, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1691 = LWDSP
+ { 1692, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1692 = LWDSP_MM
+ { 1693, 3, 1, 4, 426, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1693 = LWE
+ { 1694, 3, 1, 4, 191, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1694 = LWE_MM
+ { 1695, 3, 1, 2, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #1695 = LWGP_MM
+ { 1696, 4, 1, 4, 429, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1696 = LWL
+ { 1697, 4, 1, 4, 192, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1697 = LWL64
+ { 1698, 4, 1, 4, 431, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1698 = LWLE
+ { 1699, 4, 1, 4, 193, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1699 = LWLE_MM
+ { 1700, 4, 1, 4, 192, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1700 = LWL_MM
+ { 1701, 3, 1, 2, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1701 = LWM16_MM
+ { 1702, 3, 1, 2, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1702 = LWM16_MMR6
+ { 1703, 3, 1, 4, 194, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #1703 = LWM32_MM
+ { 1704, 2, 1, 4, 428, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1704 = LWPC
+ { 1705, 2, 1, 4, 195, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1705 = LWPC_MMR6
+ { 1706, 4, 2, 4, 196, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1706 = LWP_MM
+ { 1707, 4, 1, 4, 430, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1707 = LWR
+ { 1708, 4, 1, 4, 197, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1708 = LWR64
+ { 1709, 4, 1, 4, 432, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1709 = LWRE
+ { 1710, 4, 1, 4, 198, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1710 = LWRE_MM
+ { 1711, 4, 1, 4, 197, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1711 = LWR_MM
+ { 1712, 3, 1, 2, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #1712 = LWSP_MM
+ { 1713, 2, 1, 4, 199, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1713 = LWUPC
+ { 1714, 3, 1, 4, 200, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1714 = LWU_MM
+ { 1715, 3, 1, 4, 737, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1715 = LWX
+ { 1716, 3, 1, 4, 684, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #1716 = LWXC1
+ { 1717, 3, 1, 4, 201, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #1717 = LWXC1_MM
+ { 1718, 3, 1, 4, 202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1718 = LWXS_MM
+ { 1719, 3, 1, 4, 893, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1719 = LWX_MM
+ { 1720, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1720 = LW_MM
+ { 1721, 3, 1, 4, 187, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #1721 = LW_MMR6
+ { 1722, 3, 1, 4, 200, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #1722 = LWu
+ { 1723, 3, 1, 4, 164, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1723 = LbRxRyOffMemX16
+ { 1724, 3, 1, 4, 166, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1724 = LbuRxRyOffMemX16
+ { 1725, 3, 1, 4, 176, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1725 = LhRxRyOffMemX16
+ { 1726, 3, 1, 4, 178, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1726 = LhuRxRyOffMemX16
+ { 1727, 2, 1, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1727 = LiRxImm16
+ { 1728, 2, 1, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1728 = LiRxImmAlignX16
+ { 1729, 2, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1729 = LiRxImmX16
+ { 1730, 3, 1, 2, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1730 = LwRxPcTcp16
+ { 1731, 3, 1, 4, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1731 = LwRxPcTcpX16
+ { 1732, 3, 1, 4, 187, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1732 = LwRxRyOffMemX16
+ { 1733, 3, 1, 4, 187, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1733 = LwRxSpImmX16
+ { 1734, 2, 0, 4, 470, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1734 = MADD
+ { 1735, 4, 1, 4, 203, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1735 = MADDF_D
+ { 1736, 4, 1, 4, 203, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1736 = MADDF_D_MMR6
+ { 1737, 4, 1, 4, 204, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1737 = MADDF_S
+ { 1738, 4, 1, 4, 204, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1738 = MADDF_S_MMR6
+ { 1739, 4, 1, 4, 643, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1739 = MADDR_Q_H
+ { 1740, 4, 1, 4, 643, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1740 = MADDR_Q_W
+ { 1741, 2, 0, 4, 471, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1741 = MADDU
+ { 1742, 4, 1, 4, 738, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1742 = MADDU_DSP
+ { 1743, 4, 1, 4, 894, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1743 = MADDU_DSP_MM
+ { 1744, 2, 0, 4, 14, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1744 = MADDU_MM
+ { 1745, 4, 1, 4, 641, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1745 = MADDV_B
+ { 1746, 4, 1, 4, 641, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #1746 = MADDV_D
+ { 1747, 4, 1, 4, 641, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1747 = MADDV_H
+ { 1748, 4, 1, 4, 641, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1748 = MADDV_W
+ { 1749, 4, 1, 4, 649, 0, 0x4ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1749 = MADD_D32
+ { 1750, 4, 1, 4, 205, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1750 = MADD_D32_MM
+ { 1751, 4, 1, 4, 649, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1751 = MADD_D64
+ { 1752, 4, 1, 4, 739, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1752 = MADD_DSP
+ { 1753, 4, 1, 4, 895, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1753 = MADD_DSP_MM
+ { 1754, 2, 0, 4, 13, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1754 = MADD_MM
+ { 1755, 4, 1, 4, 644, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1755 = MADD_Q_H
+ { 1756, 4, 1, 4, 644, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1756 = MADD_Q_W
+ { 1757, 4, 1, 4, 650, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1757 = MADD_S
+ { 1758, 4, 1, 4, 206, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1758 = MADD_S_MM
+ { 1759, 4, 1, 4, 740, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1759 = MAQ_SA_W_PHL
+ { 1760, 4, 1, 4, 896, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1760 = MAQ_SA_W_PHL_MM
+ { 1761, 4, 1, 4, 741, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1761 = MAQ_SA_W_PHR
+ { 1762, 4, 1, 4, 897, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1762 = MAQ_SA_W_PHR_MM
+ { 1763, 4, 1, 4, 742, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1763 = MAQ_S_W_PHL
+ { 1764, 4, 1, 4, 898, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1764 = MAQ_S_W_PHL_MM
+ { 1765, 4, 1, 4, 743, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1765 = MAQ_S_W_PHR
+ { 1766, 4, 1, 4, 899, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1766 = MAQ_S_W_PHR_MM
+ { 1767, 3, 1, 4, 207, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1767 = MAXA_D
+ { 1768, 3, 1, 4, 208, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1768 = MAXA_D_MMR6
+ { 1769, 3, 1, 4, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1769 = MAXA_S
+ { 1770, 3, 1, 4, 210, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1770 = MAXA_S_MMR6
+ { 1771, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1771 = MAXI_S_B
+ { 1772, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1772 = MAXI_S_D
+ { 1773, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1773 = MAXI_S_H
+ { 1774, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1774 = MAXI_S_W
+ { 1775, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1775 = MAXI_U_B
+ { 1776, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1776 = MAXI_U_D
+ { 1777, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1777 = MAXI_U_H
+ { 1778, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1778 = MAXI_U_W
+ { 1779, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1779 = MAX_A_B
+ { 1780, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1780 = MAX_A_D
+ { 1781, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1781 = MAX_A_H
+ { 1782, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1782 = MAX_A_W
+ { 1783, 3, 1, 4, 207, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1783 = MAX_D
+ { 1784, 3, 1, 4, 207, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1784 = MAX_D_MMR6
+ { 1785, 3, 1, 4, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1785 = MAX_S
+ { 1786, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1786 = MAX_S_B
+ { 1787, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1787 = MAX_S_D
+ { 1788, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1788 = MAX_S_H
+ { 1789, 3, 1, 4, 209, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1789 = MAX_S_MMR6
+ { 1790, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1790 = MAX_S_W
+ { 1791, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1791 = MAX_U_B
+ { 1792, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1792 = MAX_U_D
+ { 1793, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1793 = MAX_U_H
+ { 1794, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1794 = MAX_U_W
+ { 1795, 3, 1, 4, 408, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1795 = MFC0
+ { 1796, 3, 1, 4, 211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1796 = MFC0_MMR6
+ { 1797, 2, 1, 4, 667, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1797 = MFC1
+ { 1798, 2, 1, 4, 667, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1798 = MFC1_D64
+ { 1799, 2, 1, 4, 5, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1799 = MFC1_MM
+ { 1800, 2, 1, 4, 5, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1800 = MFC1_MMR6
+ { 1801, 3, 1, 4, 410, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1801 = MFC2
+ { 1802, 2, 1, 4, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1802 = MFC2_MMR6
+ { 1803, 3, 1, 4, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1803 = MFGC0
+ { 1804, 3, 1, 4, 213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1804 = MFGC0_MM
+ { 1805, 3, 1, 4, 214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1805 = MFHC0_MMR6
+ { 1806, 2, 1, 4, 668, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #1806 = MFHC1_D32
+ { 1807, 2, 1, 4, 215, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #1807 = MFHC1_D32_MM
+ { 1808, 2, 1, 4, 668, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1808 = MFHC1_D64
+ { 1809, 2, 1, 4, 215, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1809 = MFHC1_D64_MM
+ { 1810, 2, 1, 4, 212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1810 = MFHC2_MMR6
+ { 1811, 3, 1, 4, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1811 = MFHGC0
+ { 1812, 3, 1, 4, 216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1812 = MFHGC0_MM
+ { 1813, 1, 1, 4, 459, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1813 = MFHI
+ { 1814, 1, 1, 2, 15, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1814 = MFHI16_MM
+ { 1815, 1, 1, 4, 15, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1815 = MFHI64
+ { 1816, 2, 1, 4, 744, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1816 = MFHI_DSP
+ { 1817, 2, 1, 4, 900, 0, 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1817 = MFHI_DSP_MM
+ { 1818, 1, 1, 4, 15, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1818 = MFHI_MM
+ { 1819, 1, 1, 4, 459, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1819 = MFLO
+ { 1820, 1, 1, 2, 15, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1820 = MFLO16_MM
+ { 1821, 1, 1, 4, 15, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #1821 = MFLO64
+ { 1822, 2, 1, 4, 745, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1822 = MFLO_DSP
+ { 1823, 2, 1, 4, 901, 0, 0x6ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1823 = MFLO_DSP_MM
+ { 1824, 1, 1, 4, 15, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #1824 = MFLO_MM
+ { 1825, 5, 1, 4, 217, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #1825 = MFTR
+ { 1826, 3, 1, 4, 218, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1826 = MINA_D
+ { 1827, 3, 1, 4, 219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1827 = MINA_D_MMR6
+ { 1828, 3, 1, 4, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1828 = MINA_S
+ { 1829, 3, 1, 4, 221, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1829 = MINA_S_MMR6
+ { 1830, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1830 = MINI_S_B
+ { 1831, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1831 = MINI_S_D
+ { 1832, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1832 = MINI_S_H
+ { 1833, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1833 = MINI_S_W
+ { 1834, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1834 = MINI_U_B
+ { 1835, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1835 = MINI_U_D
+ { 1836, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1836 = MINI_U_H
+ { 1837, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #1837 = MINI_U_W
+ { 1838, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1838 = MIN_A_B
+ { 1839, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1839 = MIN_A_D
+ { 1840, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1840 = MIN_A_H
+ { 1841, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1841 = MIN_A_W
+ { 1842, 3, 1, 4, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1842 = MIN_D
+ { 1843, 3, 1, 4, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1843 = MIN_D_MMR6
+ { 1844, 3, 1, 4, 218, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1844 = MIN_S
+ { 1845, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1845 = MIN_S_B
+ { 1846, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1846 = MIN_S_D
+ { 1847, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1847 = MIN_S_H
+ { 1848, 3, 1, 4, 218, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1848 = MIN_S_MMR6
+ { 1849, 3, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1849 = MIN_S_W
+ { 1850, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1850 = MIN_U_B
+ { 1851, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1851 = MIN_U_D
+ { 1852, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1852 = MIN_U_H
+ { 1853, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1853 = MIN_U_W
+ { 1854, 3, 1, 4, 222, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1854 = MOD
+ { 1855, 3, 1, 4, 746, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1855 = MODSUB
+ { 1856, 3, 1, 4, 902, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1856 = MODSUB_MM
+ { 1857, 3, 1, 4, 223, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1857 = MODU
+ { 1858, 3, 1, 4, 223, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1858 = MODU_MMR6
+ { 1859, 3, 1, 4, 222, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1859 = MOD_MMR6
+ { 1860, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1860 = MOD_S_B
+ { 1861, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1861 = MOD_S_D
+ { 1862, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1862 = MOD_S_H
+ { 1863, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1863 = MOD_S_W
+ { 1864, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #1864 = MOD_U_B
+ { 1865, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #1865 = MOD_U_D
+ { 1866, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1866 = MOD_U_H
+ { 1867, 3, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1867 = MOD_U_W
+ { 1868, 2, 1, 2, 224, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #1868 = MOVE16_MM
+ { 1869, 2, 1, 2, 224, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #1869 = MOVE16_MMR6
+ { 1870, 4, 1, 2, 903, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #1870 = MOVEP_MM
+ { 1871, 4, 1, 2, 904, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #1871 = MOVEP_MMR6
+ { 1872, 2, 1, 4, 526, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1872 = MOVE_V
+ { 1873, 4, 1, 4, 511, 0, 0x4ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1873 = MOVF_D32
+ { 1874, 4, 1, 4, 225, 0, 0x4ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1874 = MOVF_D32_MM
+ { 1875, 4, 1, 4, 511, 0, 0x4ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1875 = MOVF_D64
+ { 1876, 4, 1, 4, 669, 0, 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1876 = MOVF_I
+ { 1877, 4, 1, 4, 226, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1877 = MOVF_I64
+ { 1878, 4, 1, 4, 226, 0, 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1878 = MOVF_I_MM
+ { 1879, 4, 1, 4, 512, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1879 = MOVF_S
+ { 1880, 4, 1, 4, 227, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1880 = MOVF_S_MM
+ { 1881, 4, 1, 4, 228, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1881 = MOVN_I64_D64
+ { 1882, 4, 1, 4, 229, 0, 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1882 = MOVN_I64_I
+ { 1883, 4, 1, 4, 229, 0, 0x4ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #1883 = MOVN_I64_I64
+ { 1884, 4, 1, 4, 230, 0, 0x4ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #1884 = MOVN_I64_S
+ { 1885, 4, 1, 4, 677, 0, 0x4ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #1885 = MOVN_I_D32
+ { 1886, 4, 1, 4, 228, 0, 0x4ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #1886 = MOVN_I_D32_MM
+ { 1887, 4, 1, 4, 677, 0, 0x4ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1887 = MOVN_I_D64
+ { 1888, 4, 1, 4, 463, 0, 0x4ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #1888 = MOVN_I_I
+ { 1889, 4, 1, 4, 229, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1889 = MOVN_I_I64
+ { 1890, 4, 1, 4, 905, 0, 0x4ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #1890 = MOVN_I_MM
+ { 1891, 4, 1, 4, 678, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #1891 = MOVN_I_S
+ { 1892, 4, 1, 4, 230, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #1892 = MOVN_I_S_MM
+ { 1893, 4, 1, 4, 513, 0, 0x4ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1893 = MOVT_D32
+ { 1894, 4, 1, 4, 231, 0, 0x4ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1894 = MOVT_D32_MM
+ { 1895, 4, 1, 4, 513, 0, 0x4ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1895 = MOVT_D64
+ { 1896, 4, 1, 4, 670, 0, 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1896 = MOVT_I
+ { 1897, 4, 1, 4, 232, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1897 = MOVT_I64
+ { 1898, 4, 1, 4, 232, 0, 0x4ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1898 = MOVT_I_MM
+ { 1899, 4, 1, 4, 514, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1899 = MOVT_S
+ { 1900, 4, 1, 4, 233, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1900 = MOVT_S_MM
+ { 1901, 4, 1, 4, 234, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1901 = MOVZ_I64_D64
+ { 1902, 4, 1, 4, 235, 0, 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1902 = MOVZ_I64_I
+ { 1903, 4, 1, 4, 235, 0, 0x4ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #1903 = MOVZ_I64_I64
+ { 1904, 4, 1, 4, 236, 0, 0x4ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #1904 = MOVZ_I64_S
+ { 1905, 4, 1, 4, 679, 0, 0x4ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #1905 = MOVZ_I_D32
+ { 1906, 4, 1, 4, 234, 0, 0x4ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #1906 = MOVZ_I_D32_MM
+ { 1907, 4, 1, 4, 679, 0, 0x4ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1907 = MOVZ_I_D64
+ { 1908, 4, 1, 4, 464, 0, 0x4ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #1908 = MOVZ_I_I
+ { 1909, 4, 1, 4, 235, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1909 = MOVZ_I_I64
+ { 1910, 4, 1, 4, 906, 0, 0x4ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #1910 = MOVZ_I_MM
+ { 1911, 4, 1, 4, 680, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #1911 = MOVZ_I_S
+ { 1912, 4, 1, 4, 236, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #1912 = MOVZ_I_S_MM
+ { 1913, 2, 0, 4, 472, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1913 = MSUB
+ { 1914, 4, 1, 4, 237, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1914 = MSUBF_D
+ { 1915, 4, 1, 4, 237, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1915 = MSUBF_D_MMR6
+ { 1916, 4, 1, 4, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1916 = MSUBF_S
+ { 1917, 4, 1, 4, 238, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1917 = MSUBF_S_MMR6
+ { 1918, 4, 1, 4, 645, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1918 = MSUBR_Q_H
+ { 1919, 4, 1, 4, 645, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1919 = MSUBR_Q_W
+ { 1920, 2, 0, 4, 473, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1920 = MSUBU
+ { 1921, 4, 1, 4, 747, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1921 = MSUBU_DSP
+ { 1922, 4, 1, 4, 907, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1922 = MSUBU_DSP_MM
+ { 1923, 2, 0, 4, 17, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1923 = MSUBU_MM
+ { 1924, 4, 1, 4, 640, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1924 = MSUBV_B
+ { 1925, 4, 1, 4, 640, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #1925 = MSUBV_D
+ { 1926, 4, 1, 4, 640, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1926 = MSUBV_H
+ { 1927, 4, 1, 4, 640, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1927 = MSUBV_W
+ { 1928, 4, 1, 4, 651, 0, 0x4ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1928 = MSUB_D32
+ { 1929, 4, 1, 4, 239, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1929 = MSUB_D32_MM
+ { 1930, 4, 1, 4, 651, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1930 = MSUB_D64
+ { 1931, 4, 1, 4, 748, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1931 = MSUB_DSP
+ { 1932, 4, 1, 4, 908, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1932 = MSUB_DSP_MM
+ { 1933, 2, 0, 4, 16, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #1933 = MSUB_MM
+ { 1934, 4, 1, 4, 646, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #1934 = MSUB_Q_H
+ { 1935, 4, 1, 4, 646, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #1935 = MSUB_Q_W
+ { 1936, 4, 1, 4, 652, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1936 = MSUB_S
+ { 1937, 4, 1, 4, 240, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1937 = MSUB_S_MM
+ { 1938, 3, 1, 4, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1938 = MTC0
+ { 1939, 3, 1, 4, 241, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1939 = MTC0_MMR6
+ { 1940, 2, 1, 4, 658, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1940 = MTC1
+ { 1941, 2, 1, 4, 658, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #1941 = MTC1_D64
+ { 1942, 2, 1, 4, 4, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1942 = MTC1_MM
+ { 1943, 2, 1, 4, 4, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1943 = MTC1_MMR6
+ { 1944, 3, 1, 4, 411, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1944 = MTC2
+ { 1945, 2, 1, 4, 242, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1945 = MTC2_MMR6
+ { 1946, 3, 1, 4, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1946 = MTGC0
+ { 1947, 3, 1, 4, 243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1947 = MTGC0_MM
+ { 1948, 3, 1, 4, 244, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1948 = MTHC0_MMR6
+ { 1949, 3, 1, 4, 659, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #1949 = MTHC1_D32
+ { 1950, 3, 1, 4, 245, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #1950 = MTHC1_D32_MM
+ { 1951, 3, 1, 4, 659, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #1951 = MTHC1_D64
+ { 1952, 3, 1, 4, 245, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #1952 = MTHC1_D64_MM
+ { 1953, 2, 1, 4, 242, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1953 = MTHC2_MMR6
+ { 1954, 3, 1, 4, 246, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1954 = MTHGC0
+ { 1955, 3, 1, 4, 246, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #1955 = MTHGC0_MM
+ { 1956, 1, 0, 4, 474, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo44, -1 ,nullptr }, // Inst #1956 = MTHI
+ { 1957, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList22, OperandInfo81, -1 ,nullptr }, // Inst #1957 = MTHI64
+ { 1958, 2, 1, 4, 701, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #1958 = MTHI_DSP
+ { 1959, 2, 1, 4, 909, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #1959 = MTHI_DSP_MM
+ { 1960, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo44, -1 ,nullptr }, // Inst #1960 = MTHI_MM
+ { 1961, 3, 1, 4, 700, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo310, -1 ,nullptr }, // Inst #1961 = MTHLIP
+ { 1962, 3, 1, 4, 910, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo310, -1 ,nullptr }, // Inst #1962 = MTHLIP_MM
+ { 1963, 1, 0, 4, 474, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo44, -1 ,nullptr }, // Inst #1963 = MTLO
+ { 1964, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList24, OperandInfo81, -1 ,nullptr }, // Inst #1964 = MTLO64
+ { 1965, 2, 1, 4, 702, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #1965 = MTLO_DSP
+ { 1966, 2, 1, 4, 911, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #1966 = MTLO_DSP_MM
+ { 1967, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo44, -1 ,nullptr }, // Inst #1967 = MTLO_MM
+ { 1968, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList25, OperandInfo81, -1 ,nullptr }, // Inst #1968 = MTM0
+ { 1969, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList26, OperandInfo81, -1 ,nullptr }, // Inst #1969 = MTM1
+ { 1970, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList27, OperandInfo81, -1 ,nullptr }, // Inst #1970 = MTM2
+ { 1971, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList28, OperandInfo81, -1 ,nullptr }, // Inst #1971 = MTP0
+ { 1972, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList29, OperandInfo81, -1 ,nullptr }, // Inst #1972 = MTP1
+ { 1973, 1, 0, 4, 18, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList30, OperandInfo81, -1 ,nullptr }, // Inst #1973 = MTP2
+ { 1974, 5, 1, 4, 247, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #1974 = MTTR
+ { 1975, 3, 1, 4, 248, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1975 = MUH
+ { 1976, 3, 1, 4, 249, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1976 = MUHU
+ { 1977, 3, 1, 4, 249, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1977 = MUHU_MMR6
+ { 1978, 3, 1, 4, 248, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #1978 = MUH_MMR6
+ { 1979, 3, 1, 4, 467, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo58, -1 ,nullptr }, // Inst #1979 = MUL
+ { 1980, 3, 1, 4, 749, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo194, -1 ,nullptr }, // Inst #1980 = MULEQ_S_W_PHL
+ { 1981, 3, 1, 4, 912, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo194, -1 ,nullptr }, // Inst #1981 = MULEQ_S_W_PHL_MM
+ { 1982, 3, 1, 4, 750, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo194, -1 ,nullptr }, // Inst #1982 = MULEQ_S_W_PHR
+ { 1983, 3, 1, 4, 913, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo194, -1 ,nullptr }, // Inst #1983 = MULEQ_S_W_PHR_MM
+ { 1984, 3, 1, 4, 751, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #1984 = MULEU_S_PH_QBL
+ { 1985, 3, 1, 4, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #1985 = MULEU_S_PH_QBL_MM
+ { 1986, 3, 1, 4, 752, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #1986 = MULEU_S_PH_QBR
+ { 1987, 3, 1, 4, 915, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #1987 = MULEU_S_PH_QBR_MM
+ { 1988, 3, 1, 4, 753, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #1988 = MULQ_RS_PH
+ { 1989, 3, 1, 4, 916, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #1989 = MULQ_RS_PH_MM
+ { 1990, 3, 1, 4, 828, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo58, -1 ,nullptr }, // Inst #1990 = MULQ_RS_W
+ { 1991, 3, 1, 4, 991, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo58, -1 ,nullptr }, // Inst #1991 = MULQ_RS_W_MMR2
+ { 1992, 3, 1, 4, 829, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #1992 = MULQ_S_PH
+ { 1993, 3, 1, 4, 992, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #1993 = MULQ_S_PH_MMR2
+ { 1994, 3, 1, 4, 830, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo58, -1 ,nullptr }, // Inst #1994 = MULQ_S_W
+ { 1995, 3, 1, 4, 993, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo58, -1 ,nullptr }, // Inst #1995 = MULQ_S_W_MMR2
+ { 1996, 3, 1, 4, 647, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #1996 = MULR_Q_H
+ { 1997, 3, 1, 4, 647, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #1997 = MULR_Q_W
+ { 1998, 4, 1, 4, 754, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1998 = MULSAQ_S_W_PH
+ { 1999, 4, 1, 4, 917, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo222, -1 ,nullptr }, // Inst #1999 = MULSAQ_S_W_PH_MM
+ { 2000, 4, 1, 4, 831, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #2000 = MULSA_W_PH
+ { 2001, 4, 1, 4, 994, 0, 0x6ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #2001 = MULSA_W_PH_MMR2
+ { 2002, 2, 0, 4, 468, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2002 = MULT
+ { 2003, 3, 1, 4, 755, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2003 = MULTU_DSP
+ { 2004, 3, 1, 4, 918, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2004 = MULTU_DSP_MM
+ { 2005, 3, 1, 4, 756, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2005 = MULT_DSP
+ { 2006, 3, 1, 4, 919, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2006 = MULT_DSP_MM
+ { 2007, 2, 0, 4, 19, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2007 = MULT_MM
+ { 2008, 2, 0, 4, 469, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2008 = MULTu
+ { 2009, 2, 0, 4, 20, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2009 = MULTu_MM
+ { 2010, 3, 1, 4, 251, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2010 = MULU
+ { 2011, 3, 1, 4, 251, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2011 = MULU_MMR6
+ { 2012, 3, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2012 = MULV_B
+ { 2013, 3, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2013 = MULV_D
+ { 2014, 3, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2014 = MULV_H
+ { 2015, 3, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2015 = MULV_W
+ { 2016, 3, 1, 4, 250, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo58, -1 ,nullptr }, // Inst #2016 = MUL_MM
+ { 2017, 3, 1, 4, 250, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2017 = MUL_MMR6
+ { 2018, 3, 1, 4, 826, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2018 = MUL_PH
+ { 2019, 3, 1, 4, 989, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2019 = MUL_PH_MMR2
+ { 2020, 3, 1, 4, 648, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2020 = MUL_Q_H
+ { 2021, 3, 1, 4, 648, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2021 = MUL_Q_W
+ { 2022, 3, 1, 4, 250, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2022 = MUL_R6
+ { 2023, 3, 1, 4, 827, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2023 = MUL_S_PH
+ { 2024, 3, 1, 4, 990, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo150, -1 ,nullptr }, // Inst #2024 = MUL_S_PH_MMR2
+ { 2025, 1, 1, 2, 38, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2025 = Mfhi16
+ { 2026, 1, 1, 2, 38, 0, 0x0ULL, ImplicitList23, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2026 = Mflo16
+ { 2027, 2, 1, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2027 = Move32R16
+ { 2028, 2, 1, 2, 38, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2028 = MoveR3216
+ { 2029, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2029 = NLOC_B
+ { 2030, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2030 = NLOC_D
+ { 2031, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2031 = NLOC_H
+ { 2032, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2032 = NLOC_W
+ { 2033, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2033 = NLZC_B
+ { 2034, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2034 = NLZC_D
+ { 2035, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2035 = NLZC_H
+ { 2036, 2, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2036 = NLZC_W
+ { 2037, 4, 1, 4, 653, 0, 0x4ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2037 = NMADD_D32
+ { 2038, 4, 1, 4, 252, 0, 0x4ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2038 = NMADD_D32_MM
+ { 2039, 4, 1, 4, 653, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2039 = NMADD_D64
+ { 2040, 4, 1, 4, 654, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2040 = NMADD_S
+ { 2041, 4, 1, 4, 253, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2041 = NMADD_S_MM
+ { 2042, 4, 1, 4, 655, 0, 0x4ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2042 = NMSUB_D32
+ { 2043, 4, 1, 4, 254, 0, 0x4ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2043 = NMSUB_D32_MM
+ { 2044, 4, 1, 4, 655, 0, 0x4ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2044 = NMSUB_D64
+ { 2045, 4, 1, 4, 656, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2045 = NMSUB_S
+ { 2046, 4, 1, 4, 255, 0, 0x4ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2046 = NMSUB_S_MM
+ { 2047, 3, 1, 4, 360, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2047 = NOR
+ { 2048, 3, 1, 4, 256, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2048 = NOR64
+ { 2049, 3, 1, 4, 529, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2049 = NORI_B
+ { 2050, 3, 1, 4, 256, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2050 = NOR_MM
+ { 2051, 3, 1, 4, 256, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2051 = NOR_MMR6
+ { 2052, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2052 = NOR_V
+ { 2053, 2, 1, 2, 257, 0, 0x0ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2053 = NOT16_MM
+ { 2054, 2, 1, 2, 257, 0, 0x0ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2054 = NOT16_MMR6
+ { 2055, 2, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #2055 = NegRxRy16
+ { 2056, 2, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #2056 = NotRxRy16
+ { 2057, 3, 1, 4, 361, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2057 = OR
+ { 2058, 3, 1, 2, 258, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2058 = OR16_MM
+ { 2059, 3, 1, 2, 258, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2059 = OR16_MMR6
+ { 2060, 3, 1, 4, 258, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2060 = OR64
+ { 2061, 3, 1, 4, 529, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2061 = ORI_B
+ { 2062, 3, 1, 4, 259, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2062 = ORI_MMR6
+ { 2063, 3, 1, 4, 258, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2063 = OR_MM
+ { 2064, 3, 1, 4, 258, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2064 = OR_MMR6
+ { 2065, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2065 = OR_V
+ { 2066, 3, 1, 4, 481, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2066 = ORi
+ { 2067, 3, 1, 4, 258, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2067 = ORi64
+ { 2068, 3, 1, 4, 259, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2068 = ORi_MM
+ { 2069, 3, 1, 2, 38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2069 = OrRxRxRy16
+ { 2070, 3, 1, 4, 757, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2070 = PACKRL_PH
+ { 2071, 3, 1, 4, 920, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2071 = PACKRL_PH_MM
+ { 2072, 0, 0, 4, 397, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2072 = PAUSE
+ { 2073, 0, 0, 4, 260, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2073 = PAUSE_MM
+ { 2074, 0, 0, 4, 260, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2074 = PAUSE_MMR6
+ { 2075, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2075 = PCKEV_B
+ { 2076, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2076 = PCKEV_D
+ { 2077, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2077 = PCKEV_H
+ { 2078, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2078 = PCKEV_W
+ { 2079, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2079 = PCKOD_B
+ { 2080, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2080 = PCKOD_D
+ { 2081, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2081 = PCKOD_H
+ { 2082, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2082 = PCKOD_W
+ { 2083, 2, 1, 4, 506, 0, 0x6ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2083 = PCNT_B
+ { 2084, 2, 1, 4, 506, 0, 0x6ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2084 = PCNT_D
+ { 2085, 2, 1, 4, 506, 0, 0x6ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2085 = PCNT_H
+ { 2086, 2, 1, 4, 506, 0, 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2086 = PCNT_W
+ { 2087, 3, 1, 4, 758, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2087 = PICK_PH
+ { 2088, 3, 1, 4, 921, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2088 = PICK_PH_MM
+ { 2089, 3, 1, 4, 759, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2089 = PICK_QB
+ { 2090, 3, 1, 4, 922, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2090 = PICK_QB_MM
+ { 2091, 2, 1, 4, 109, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2091 = POP
+ { 2092, 2, 1, 4, 761, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2092 = PRECEQU_PH_QBL
+ { 2093, 2, 1, 4, 760, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2093 = PRECEQU_PH_QBLA
+ { 2094, 2, 1, 4, 923, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2094 = PRECEQU_PH_QBLA_MM
+ { 2095, 2, 1, 4, 924, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2095 = PRECEQU_PH_QBL_MM
+ { 2096, 2, 1, 4, 763, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2096 = PRECEQU_PH_QBR
+ { 2097, 2, 1, 4, 762, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2097 = PRECEQU_PH_QBRA
+ { 2098, 2, 1, 4, 925, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2098 = PRECEQU_PH_QBRA_MM
+ { 2099, 2, 1, 4, 926, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2099 = PRECEQU_PH_QBR_MM
+ { 2100, 2, 1, 4, 764, 0, 0x6ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2100 = PRECEQ_W_PHL
+ { 2101, 2, 1, 4, 927, 0, 0x6ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2101 = PRECEQ_W_PHL_MM
+ { 2102, 2, 1, 4, 765, 0, 0x6ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2102 = PRECEQ_W_PHR
+ { 2103, 2, 1, 4, 928, 0, 0x6ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2103 = PRECEQ_W_PHR_MM
+ { 2104, 2, 1, 4, 767, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2104 = PRECEU_PH_QBL
+ { 2105, 2, 1, 4, 766, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2105 = PRECEU_PH_QBLA
+ { 2106, 2, 1, 4, 929, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2106 = PRECEU_PH_QBLA_MM
+ { 2107, 2, 1, 4, 930, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2107 = PRECEU_PH_QBL_MM
+ { 2108, 2, 1, 4, 769, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2108 = PRECEU_PH_QBR
+ { 2109, 2, 1, 4, 768, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2109 = PRECEU_PH_QBRA
+ { 2110, 2, 1, 4, 931, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2110 = PRECEU_PH_QBRA_MM
+ { 2111, 2, 1, 4, 932, 0, 0x6ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #2111 = PRECEU_PH_QBR_MM
+ { 2112, 3, 1, 4, 770, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo150, -1 ,nullptr }, // Inst #2112 = PRECRQU_S_QB_PH
+ { 2113, 3, 1, 4, 933, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo150, -1 ,nullptr }, // Inst #2113 = PRECRQU_S_QB_PH_MM
+ { 2114, 3, 1, 4, 771, 0, 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2114 = PRECRQ_PH_W
+ { 2115, 3, 1, 4, 934, 0, 0x6ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2115 = PRECRQ_PH_W_MM
+ { 2116, 3, 1, 4, 772, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2116 = PRECRQ_QB_PH
+ { 2117, 3, 1, 4, 935, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2117 = PRECRQ_QB_PH_MM
+ { 2118, 3, 1, 4, 773, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo317, -1 ,nullptr }, // Inst #2118 = PRECRQ_RS_PH_W
+ { 2119, 3, 1, 4, 936, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo317, -1 ,nullptr }, // Inst #2119 = PRECRQ_RS_PH_W_MM
+ { 2120, 3, 1, 4, 832, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2120 = PRECR_QB_PH
+ { 2121, 3, 1, 4, 995, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2121 = PRECR_QB_PH_MMR2
+ { 2122, 4, 1, 4, 833, 0, 0x6ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2122 = PRECR_SRA_PH_W
+ { 2123, 4, 1, 4, 996, 0, 0x6ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2123 = PRECR_SRA_PH_W_MMR2
+ { 2124, 4, 1, 4, 834, 0, 0x6ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2124 = PRECR_SRA_R_PH_W
+ { 2125, 4, 1, 4, 997, 0, 0x6ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2125 = PRECR_SRA_R_PH_W_MMR2
+ { 2126, 3, 0, 4, 449, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2126 = PREF
+ { 2127, 3, 0, 4, 450, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2127 = PREFE
+ { 2128, 3, 0, 4, 262, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2128 = PREFE_MM
+ { 2129, 3, 0, 4, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2129 = PREFX_MM
+ { 2130, 3, 0, 4, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2130 = PREF_MM
+ { 2131, 3, 0, 4, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2131 = PREF_MMR6
+ { 2132, 3, 0, 4, 261, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2132 = PREF_R6
+ { 2133, 4, 1, 4, 835, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2133 = PREPEND
+ { 2134, 4, 1, 4, 998, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2134 = PREPEND_MMR2
+ { 2135, 2, 1, 4, 774, 0, 0x6ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2135 = RADDU_W_QB
+ { 2136, 2, 1, 4, 937, 0, 0x6ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2136 = RADDU_W_QB_MM
+ { 2137, 2, 1, 4, 775, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2137 = RDDSP
+ { 2138, 2, 1, 4, 938, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2138 = RDDSP_MM
+ { 2139, 3, 1, 4, 461, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2139 = RDHWR
+ { 2140, 3, 1, 4, 263, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2140 = RDHWR64
+ { 2141, 3, 1, 4, 263, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2141 = RDHWR_MM
+ { 2142, 3, 1, 4, 263, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2142 = RDHWR_MMR6
+ { 2143, 2, 1, 4, 264, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2143 = RDPGPR_MMR6
+ { 2144, 2, 1, 4, 624, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #2144 = RECIP_D32
+ { 2145, 2, 1, 4, 265, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #2145 = RECIP_D32_MM
+ { 2146, 2, 1, 4, 624, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2146 = RECIP_D64
+ { 2147, 2, 1, 4, 265, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2147 = RECIP_D64_MM
+ { 2148, 2, 1, 4, 626, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2148 = RECIP_S
+ { 2149, 2, 1, 4, 266, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2149 = RECIP_S_MM
+ { 2150, 2, 1, 4, 776, 0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2150 = REPLV_PH
+ { 2151, 2, 1, 4, 939, 0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2151 = REPLV_PH_MM
+ { 2152, 2, 1, 4, 777, 0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2152 = REPLV_QB
+ { 2153, 2, 1, 4, 940, 0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2153 = REPLV_QB_MM
+ { 2154, 2, 1, 4, 778, 0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2154 = REPL_PH
+ { 2155, 2, 1, 4, 941, 0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2155 = REPL_PH_MM
+ { 2156, 2, 1, 4, 779, 0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2156 = REPL_QB
+ { 2157, 2, 1, 4, 942, 0, 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2157 = REPL_QB_MM
+ { 2158, 2, 1, 4, 267, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2158 = RINT_D
+ { 2159, 2, 1, 4, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2159 = RINT_D_MMR6
+ { 2160, 2, 1, 4, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2160 = RINT_S
+ { 2161, 2, 1, 4, 268, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2161 = RINT_S_MMR6
+ { 2162, 3, 1, 4, 482, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2162 = ROTR
+ { 2163, 3, 1, 4, 690, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2163 = ROTRV
+ { 2164, 3, 1, 4, 270, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2164 = ROTRV_MM
+ { 2165, 3, 1, 4, 269, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2165 = ROTR_MM
+ { 2166, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2166 = ROUND_L_D64
+ { 2167, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2167 = ROUND_L_D_MMR6
+ { 2168, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2168 = ROUND_L_S
+ { 2169, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2169 = ROUND_L_S_MMR6
+ { 2170, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2170 = ROUND_W_D32
+ { 2171, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #2171 = ROUND_W_D64
+ { 2172, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2172 = ROUND_W_D_MMR6
+ { 2173, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2173 = ROUND_W_MM
+ { 2174, 2, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2174 = ROUND_W_S
+ { 2175, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2175 = ROUND_W_S_MM
+ { 2176, 2, 1, 4, 271, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2176 = ROUND_W_S_MMR6
+ { 2177, 2, 1, 4, 625, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #2177 = RSQRT_D32
+ { 2178, 2, 1, 4, 265, 0, 0x4ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #2178 = RSQRT_D32_MM
+ { 2179, 2, 1, 4, 625, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2179 = RSQRT_D64
+ { 2180, 2, 1, 4, 265, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2180 = RSQRT_D64_MM
+ { 2181, 2, 1, 4, 627, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2181 = RSQRT_S
+ { 2182, 2, 1, 4, 266, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2182 = RSQRT_S_MM
+ { 2183, 0, 0, 2, 274, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2183 = Restore16
+ { 2184, 0, 0, 2, 274, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2184 = RestoreX16
+ { 2185, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2185 = SAT_S_B
+ { 2186, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2186 = SAT_S_D
+ { 2187, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2187 = SAT_S_H
+ { 2188, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2188 = SAT_S_W
+ { 2189, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2189 = SAT_U_B
+ { 2190, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2190 = SAT_U_D
+ { 2191, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2191 = SAT_U_H
+ { 2192, 3, 1, 4, 507, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2192 = SAT_U_W
+ { 2193, 3, 0, 4, 433, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2193 = SB
+ { 2194, 3, 0, 2, 275, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2194 = SB16_MM
+ { 2195, 3, 0, 2, 275, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2195 = SB16_MMR6
+ { 2196, 3, 0, 4, 275, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2196 = SB64
+ { 2197, 3, 0, 4, 441, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2197 = SBE
+ { 2198, 3, 0, 4, 276, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2198 = SBE_MM
+ { 2199, 3, 0, 4, 275, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2199 = SB_MM
+ { 2200, 3, 0, 4, 275, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2200 = SB_MMR6
+ { 2201, 4, 1, 4, 440, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2201 = SC
+ { 2202, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2202 = SC64
+ { 2203, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2203 = SC64_R6
+ { 2204, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2204 = SCD
+ { 2205, 4, 1, 4, 278, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2205 = SCD_R6
+ { 2206, 4, 1, 4, 444, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2206 = SCE
+ { 2207, 4, 1, 4, 279, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2207 = SCE_MM
+ { 2208, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2208 = SC_MM
+ { 2209, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2209 = SC_MMR6
+ { 2210, 4, 1, 4, 277, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2210 = SC_R6
+ { 2211, 3, 0, 4, 280, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2211 = SD
+ { 2212, 1, 0, 4, 380, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2212 = SDBBP
+ { 2213, 1, 0, 2, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2213 = SDBBP16_MM
+ { 2214, 1, 0, 2, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2214 = SDBBP16_MMR6
+ { 2215, 1, 0, 4, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2215 = SDBBP_MM
+ { 2216, 1, 0, 4, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2216 = SDBBP_MMR6
+ { 2217, 1, 0, 4, 281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2217 = SDBBP_R6
+ { 2218, 3, 0, 4, 671, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2218 = SDC1
+ { 2219, 3, 0, 4, 282, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2219 = SDC164
+ { 2220, 3, 0, 4, 282, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2220 = SDC1_D64_MMR6
+ { 2221, 3, 0, 4, 282, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2221 = SDC1_MM
+ { 2222, 3, 0, 4, 438, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2222 = SDC2
+ { 2223, 3, 0, 4, 283, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2223 = SDC2_MMR6
+ { 2224, 3, 0, 4, 283, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2224 = SDC2_R6
+ { 2225, 3, 0, 4, 439, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2225 = SDC3
+ { 2226, 2, 0, 4, 465, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2226 = SDIV
+ { 2227, 2, 0, 4, 22, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2227 = SDIV_MM
+ { 2228, 3, 0, 4, 285, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2228 = SDL
+ { 2229, 3, 0, 4, 286, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2229 = SDR
+ { 2230, 3, 0, 4, 672, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2230 = SDXC1
+ { 2231, 3, 0, 4, 287, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2231 = SDXC164
+ { 2232, 2, 1, 4, 483, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2232 = SEB
+ { 2233, 2, 1, 4, 288, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2233 = SEB64
+ { 2234, 2, 1, 4, 288, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2234 = SEB_MM
+ { 2235, 2, 1, 4, 484, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2235 = SEH
+ { 2236, 2, 1, 4, 289, 0, 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2236 = SEH64
+ { 2237, 2, 1, 4, 289, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2237 = SEH_MM
+ { 2238, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2238 = SELEQZ
+ { 2239, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2239 = SELEQZ64
+ { 2240, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #2240 = SELEQZ_D
+ { 2241, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #2241 = SELEQZ_D_MMR6
+ { 2242, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2242 = SELEQZ_MMR6
+ { 2243, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2243 = SELEQZ_S
+ { 2244, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2244 = SELEQZ_S_MMR6
+ { 2245, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2245 = SELNEZ
+ { 2246, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2246 = SELNEZ64
+ { 2247, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #2247 = SELNEZ_D
+ { 2248, 3, 1, 4, 291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #2248 = SELNEZ_D_MMR6
+ { 2249, 3, 1, 4, 290, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2249 = SELNEZ_MMR6
+ { 2250, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2250 = SELNEZ_S
+ { 2251, 3, 1, 4, 292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2251 = SELNEZ_S_MMR6
+ { 2252, 4, 1, 4, 293, 0, 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2252 = SEL_D
+ { 2253, 4, 1, 4, 293, 0, 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2253 = SEL_D_MMR6
+ { 2254, 4, 1, 4, 294, 0, 0x6ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2254 = SEL_S
+ { 2255, 4, 1, 4, 294, 0, 0x6ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2255 = SEL_S_MMR6
+ { 2256, 3, 1, 4, 295, 0, 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2256 = SEQ
+ { 2257, 3, 1, 4, 296, 0, 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2257 = SEQi
+ { 2258, 3, 0, 4, 434, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2258 = SH
+ { 2259, 3, 0, 2, 297, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2259 = SH16_MM
+ { 2260, 3, 0, 2, 297, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2260 = SH16_MMR6
+ { 2261, 3, 0, 4, 297, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2261 = SH64
+ { 2262, 3, 0, 4, 442, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2262 = SHE
+ { 2263, 3, 0, 4, 298, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2263 = SHE_MM
+ { 2264, 3, 1, 4, 523, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2264 = SHF_B
+ { 2265, 3, 1, 4, 523, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2265 = SHF_H
+ { 2266, 3, 1, 4, 523, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2266 = SHF_W
+ { 2267, 3, 1, 4, 781, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2267 = SHILO
+ { 2268, 3, 1, 4, 780, 0, 0x6ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #2268 = SHILOV
+ { 2269, 3, 1, 4, 943, 0, 0x6ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #2269 = SHILOV_MM
+ { 2270, 3, 1, 4, 944, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2270 = SHILO_MM
+ { 2271, 3, 1, 4, 782, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2271 = SHLLV_PH
+ { 2272, 3, 1, 4, 945, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2272 = SHLLV_PH_MM
+ { 2273, 3, 1, 4, 783, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2273 = SHLLV_QB
+ { 2274, 3, 1, 4, 946, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2274 = SHLLV_QB_MM
+ { 2275, 3, 1, 4, 784, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2275 = SHLLV_S_PH
+ { 2276, 3, 1, 4, 947, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2276 = SHLLV_S_PH_MM
+ { 2277, 3, 1, 4, 785, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo58, -1 ,nullptr }, // Inst #2277 = SHLLV_S_W
+ { 2278, 3, 1, 4, 948, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo58, -1 ,nullptr }, // Inst #2278 = SHLLV_S_W_MM
+ { 2279, 3, 1, 4, 786, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2279 = SHLL_PH
+ { 2280, 3, 1, 4, 949, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2280 = SHLL_PH_MM
+ { 2281, 3, 1, 4, 787, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2281 = SHLL_QB
+ { 2282, 3, 1, 4, 950, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2282 = SHLL_QB_MM
+ { 2283, 3, 1, 4, 788, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2283 = SHLL_S_PH
+ { 2284, 3, 1, 4, 951, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo330, -1 ,nullptr }, // Inst #2284 = SHLL_S_PH_MM
+ { 2285, 3, 1, 4, 789, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo59, -1 ,nullptr }, // Inst #2285 = SHLL_S_W
+ { 2286, 3, 1, 4, 952, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo59, -1 ,nullptr }, // Inst #2286 = SHLL_S_W_MM
+ { 2287, 3, 1, 4, 790, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2287 = SHRAV_PH
+ { 2288, 3, 1, 4, 953, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2288 = SHRAV_PH_MM
+ { 2289, 3, 1, 4, 838, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2289 = SHRAV_QB
+ { 2290, 3, 1, 4, 1001, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2290 = SHRAV_QB_MMR2
+ { 2291, 3, 1, 4, 791, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2291 = SHRAV_R_PH
+ { 2292, 3, 1, 4, 954, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2292 = SHRAV_R_PH_MM
+ { 2293, 3, 1, 4, 839, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2293 = SHRAV_R_QB
+ { 2294, 3, 1, 4, 1002, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2294 = SHRAV_R_QB_MMR2
+ { 2295, 3, 1, 4, 792, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2295 = SHRAV_R_W
+ { 2296, 3, 1, 4, 955, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2296 = SHRAV_R_W_MM
+ { 2297, 3, 1, 4, 793, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2297 = SHRA_PH
+ { 2298, 3, 1, 4, 956, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2298 = SHRA_PH_MM
+ { 2299, 3, 1, 4, 836, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2299 = SHRA_QB
+ { 2300, 3, 1, 4, 999, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2300 = SHRA_QB_MMR2
+ { 2301, 3, 1, 4, 794, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2301 = SHRA_R_PH
+ { 2302, 3, 1, 4, 957, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2302 = SHRA_R_PH_MM
+ { 2303, 3, 1, 4, 837, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2303 = SHRA_R_QB
+ { 2304, 3, 1, 4, 1000, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2304 = SHRA_R_QB_MMR2
+ { 2305, 3, 1, 4, 795, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2305 = SHRA_R_W
+ { 2306, 3, 1, 4, 958, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2306 = SHRA_R_W_MM
+ { 2307, 3, 1, 4, 841, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2307 = SHRLV_PH
+ { 2308, 3, 1, 4, 1004, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2308 = SHRLV_PH_MMR2
+ { 2309, 3, 1, 4, 796, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2309 = SHRLV_QB
+ { 2310, 3, 1, 4, 959, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2310 = SHRLV_QB_MM
+ { 2311, 3, 1, 4, 840, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2311 = SHRL_PH
+ { 2312, 3, 1, 4, 1003, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2312 = SHRL_PH_MMR2
+ { 2313, 3, 1, 4, 797, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2313 = SHRL_QB
+ { 2314, 3, 1, 4, 960, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2314 = SHRL_QB_MM
+ { 2315, 3, 0, 4, 297, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2315 = SH_MM
+ { 2316, 3, 0, 4, 297, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2316 = SH_MMR6
+ { 2317, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2317 = SLDI_B
+ { 2318, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #2318 = SLDI_D
+ { 2319, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #2319 = SLDI_H
+ { 2320, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #2320 = SLDI_W
+ { 2321, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2321 = SLD_B
+ { 2322, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2322 = SLD_D
+ { 2323, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr }, // Inst #2323 = SLD_H
+ { 2324, 4, 1, 4, 500, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2324 = SLD_W
+ { 2325, 3, 1, 4, 486, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2325 = SLL
+ { 2326, 3, 1, 2, 299, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #2326 = SLL16_MM
+ { 2327, 3, 1, 2, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #2327 = SLL16_MMR6
+ { 2328, 2, 1, 4, 299, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #2328 = SLL64_32
+ { 2329, 2, 1, 4, 299, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #2329 = SLL64_64
+ { 2330, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2330 = SLLI_B
+ { 2331, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2331 = SLLI_D
+ { 2332, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2332 = SLLI_H
+ { 2333, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2333 = SLLI_W
+ { 2334, 3, 1, 4, 491, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2334 = SLLV
+ { 2335, 3, 1, 4, 300, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2335 = SLLV_MM
+ { 2336, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2336 = SLL_B
+ { 2337, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2337 = SLL_D
+ { 2338, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2338 = SLL_H
+ { 2339, 3, 1, 4, 299, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2339 = SLL_MM
+ { 2340, 3, 1, 4, 299, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2340 = SLL_MMR6
+ { 2341, 3, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2341 = SLL_W
+ { 2342, 3, 1, 4, 485, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2342 = SLT
+ { 2343, 3, 1, 4, 301, 0, 0x1ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2343 = SLT64
+ { 2344, 3, 1, 4, 301, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2344 = SLT_MM
+ { 2345, 3, 1, 4, 362, 0, 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2345 = SLTi
+ { 2346, 3, 1, 4, 302, 0, 0x2ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2346 = SLTi64
+ { 2347, 3, 1, 4, 302, 0, 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2347 = SLTi_MM
+ { 2348, 3, 1, 4, 362, 0, 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2348 = SLTiu
+ { 2349, 3, 1, 4, 302, 0, 0x2ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2349 = SLTiu64
+ { 2350, 3, 1, 4, 302, 0, 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2350 = SLTiu_MM
+ { 2351, 3, 1, 4, 485, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2351 = SLTu
+ { 2352, 3, 1, 4, 301, 0, 0x1ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2352 = SLTu64
+ { 2353, 3, 1, 4, 301, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2353 = SLTu_MM
+ { 2354, 3, 1, 4, 295, 0, 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2354 = SNE
+ { 2355, 3, 1, 4, 296, 0, 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2355 = SNEi
+ { 2356, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2356 = SPLATI_B
+ { 2357, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2357 = SPLATI_D
+ { 2358, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2358 = SPLATI_H
+ { 2359, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2359 = SPLATI_W
+ { 2360, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2360 = SPLAT_B
+ { 2361, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2361 = SPLAT_D
+ { 2362, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2362 = SPLAT_H
+ { 2363, 3, 1, 4, 525, 0, 0x6ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2363 = SPLAT_W
+ { 2364, 3, 1, 4, 487, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2364 = SRA
+ { 2365, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2365 = SRAI_B
+ { 2366, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2366 = SRAI_D
+ { 2367, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2367 = SRAI_H
+ { 2368, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2368 = SRAI_W
+ { 2369, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2369 = SRARI_B
+ { 2370, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2370 = SRARI_D
+ { 2371, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2371 = SRARI_H
+ { 2372, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2372 = SRARI_W
+ { 2373, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2373 = SRAR_B
+ { 2374, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2374 = SRAR_D
+ { 2375, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2375 = SRAR_H
+ { 2376, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2376 = SRAR_W
+ { 2377, 3, 1, 4, 492, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2377 = SRAV
+ { 2378, 3, 1, 4, 304, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2378 = SRAV_MM
+ { 2379, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2379 = SRA_B
+ { 2380, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2380 = SRA_D
+ { 2381, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2381 = SRA_H
+ { 2382, 3, 1, 4, 303, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2382 = SRA_MM
+ { 2383, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2383 = SRA_W
+ { 2384, 3, 1, 4, 488, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2384 = SRL
+ { 2385, 3, 1, 2, 305, 0, 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #2385 = SRL16_MM
+ { 2386, 3, 1, 2, 305, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #2386 = SRL16_MMR6
+ { 2387, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2387 = SRLI_B
+ { 2388, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2388 = SRLI_D
+ { 2389, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2389 = SRLI_H
+ { 2390, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2390 = SRLI_W
+ { 2391, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2391 = SRLRI_B
+ { 2392, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2392 = SRLRI_D
+ { 2393, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2393 = SRLRI_H
+ { 2394, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2394 = SRLRI_W
+ { 2395, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2395 = SRLR_B
+ { 2396, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2396 = SRLR_D
+ { 2397, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2397 = SRLR_H
+ { 2398, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2398 = SRLR_W
+ { 2399, 3, 1, 4, 493, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2399 = SRLV
+ { 2400, 3, 1, 4, 306, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2400 = SRLV_MM
+ { 2401, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2401 = SRL_B
+ { 2402, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2402 = SRL_D
+ { 2403, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2403 = SRL_H
+ { 2404, 3, 1, 4, 305, 0, 0x1ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2404 = SRL_MM
+ { 2405, 3, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2405 = SRL_W
+ { 2406, 0, 0, 4, 381, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2406 = SSNOP
+ { 2407, 0, 0, 4, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2407 = SSNOP_MM
+ { 2408, 0, 0, 4, 307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2408 = SSNOP_MMR6
+ { 2409, 3, 0, 4, 676, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2409 = ST_B
+ { 2410, 3, 0, 4, 676, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2410 = ST_D
+ { 2411, 3, 0, 4, 676, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2411 = ST_H
+ { 2412, 3, 0, 4, 676, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2412 = ST_W
+ { 2413, 3, 1, 4, 363, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2413 = SUB
+ { 2414, 3, 1, 4, 842, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2414 = SUBQH_PH
+ { 2415, 3, 1, 4, 1005, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2415 = SUBQH_PH_MMR2
+ { 2416, 3, 1, 4, 843, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2416 = SUBQH_R_PH
+ { 2417, 3, 1, 4, 1006, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2417 = SUBQH_R_PH_MMR2
+ { 2418, 3, 1, 4, 845, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2418 = SUBQH_R_W
+ { 2419, 3, 1, 4, 1008, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2419 = SUBQH_R_W_MMR2
+ { 2420, 3, 1, 4, 844, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2420 = SUBQH_W
+ { 2421, 3, 1, 4, 1007, 0, 0x6ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2421 = SUBQH_W_MMR2
+ { 2422, 3, 1, 4, 798, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2422 = SUBQ_PH
+ { 2423, 3, 1, 4, 961, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2423 = SUBQ_PH_MM
+ { 2424, 3, 1, 4, 799, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2424 = SUBQ_S_PH
+ { 2425, 3, 1, 4, 962, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2425 = SUBQ_S_PH_MM
+ { 2426, 3, 1, 4, 800, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #2426 = SUBQ_S_W
+ { 2427, 3, 1, 4, 963, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo58, -1 ,nullptr }, // Inst #2427 = SUBQ_S_W_MM
+ { 2428, 3, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2428 = SUBSUS_U_B
+ { 2429, 3, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2429 = SUBSUS_U_D
+ { 2430, 3, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2430 = SUBSUS_U_H
+ { 2431, 3, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2431 = SUBSUS_U_W
+ { 2432, 3, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2432 = SUBSUU_S_B
+ { 2433, 3, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2433 = SUBSUU_S_D
+ { 2434, 3, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2434 = SUBSUU_S_H
+ { 2435, 3, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2435 = SUBSUU_S_W
+ { 2436, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2436 = SUBS_S_B
+ { 2437, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2437 = SUBS_S_D
+ { 2438, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2438 = SUBS_S_H
+ { 2439, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2439 = SUBS_S_W
+ { 2440, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2440 = SUBS_U_B
+ { 2441, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2441 = SUBS_U_D
+ { 2442, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2442 = SUBS_U_H
+ { 2443, 3, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2443 = SUBS_U_W
+ { 2444, 3, 1, 2, 309, 0, 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #2444 = SUBU16_MM
+ { 2445, 3, 1, 2, 309, 0, 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #2445 = SUBU16_MMR6
+ { 2446, 3, 1, 4, 848, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2446 = SUBUH_QB
+ { 2447, 3, 1, 4, 1011, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2447 = SUBUH_QB_MMR2
+ { 2448, 3, 1, 4, 849, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2448 = SUBUH_R_QB
+ { 2449, 3, 1, 4, 1012, 0, 0x6ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2449 = SUBUH_R_QB_MMR2
+ { 2450, 3, 1, 4, 309, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2450 = SUBU_MMR6
+ { 2451, 3, 1, 4, 846, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2451 = SUBU_PH
+ { 2452, 3, 1, 4, 1009, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2452 = SUBU_PH_MMR2
+ { 2453, 3, 1, 4, 801, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2453 = SUBU_QB
+ { 2454, 3, 1, 4, 964, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2454 = SUBU_QB_MM
+ { 2455, 3, 1, 4, 847, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2455 = SUBU_S_PH
+ { 2456, 3, 1, 4, 1010, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2456 = SUBU_S_PH_MMR2
+ { 2457, 3, 1, 4, 802, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2457 = SUBU_S_QB
+ { 2458, 3, 1, 4, 965, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo150, -1 ,nullptr }, // Inst #2458 = SUBU_S_QB_MM
+ { 2459, 3, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2459 = SUBVI_B
+ { 2460, 3, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2460 = SUBVI_D
+ { 2461, 3, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #2461 = SUBVI_H
+ { 2462, 3, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #2462 = SUBVI_W
+ { 2463, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2463 = SUBV_B
+ { 2464, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #2464 = SUBV_D
+ { 2465, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #2465 = SUBV_H
+ { 2466, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #2466 = SUBV_W
+ { 2467, 3, 1, 4, 308, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2467 = SUB_MM
+ { 2468, 3, 1, 4, 308, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2468 = SUB_MMR6
+ { 2469, 3, 1, 4, 364, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2469 = SUBu
+ { 2470, 3, 1, 4, 309, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2470 = SUBu_MM
+ { 2471, 3, 0, 4, 673, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2471 = SUXC1
+ { 2472, 3, 0, 4, 310, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2472 = SUXC164
+ { 2473, 3, 0, 4, 310, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2473 = SUXC1_MM
+ { 2474, 3, 0, 4, 435, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2474 = SW
+ { 2475, 3, 0, 2, 311, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2475 = SW16_MM
+ { 2476, 3, 0, 2, 311, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2476 = SW16_MMR6
+ { 2477, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2477 = SW64
+ { 2478, 3, 0, 4, 674, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2478 = SWC1
+ { 2479, 3, 0, 4, 312, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2479 = SWC1_MM
+ { 2480, 3, 0, 4, 436, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2480 = SWC2
+ { 2481, 3, 0, 4, 313, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2481 = SWC2_MMR6
+ { 2482, 3, 0, 4, 313, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2482 = SWC2_R6
+ { 2483, 3, 0, 4, 437, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2483 = SWC3
+ { 2484, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2484 = SWDSP
+ { 2485, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2485 = SWDSP_MM
+ { 2486, 3, 0, 4, 443, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2486 = SWE
+ { 2487, 3, 0, 4, 315, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2487 = SWE_MM
+ { 2488, 3, 0, 4, 445, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2488 = SWL
+ { 2489, 3, 0, 4, 316, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2489 = SWL64
+ { 2490, 3, 0, 4, 447, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2490 = SWLE
+ { 2491, 3, 0, 4, 317, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2491 = SWLE_MM
+ { 2492, 3, 0, 4, 316, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2492 = SWL_MM
+ { 2493, 3, 0, 2, 318, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2493 = SWM16_MM
+ { 2494, 3, 0, 2, 318, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2494 = SWM16_MMR6
+ { 2495, 3, 0, 4, 318, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #2495 = SWM32_MM
+ { 2496, 4, 0, 4, 319, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2496 = SWP_MM
+ { 2497, 3, 0, 4, 446, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2497 = SWR
+ { 2498, 3, 0, 4, 320, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #2498 = SWR64
+ { 2499, 3, 0, 4, 448, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2499 = SWRE
+ { 2500, 3, 0, 4, 321, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2500 = SWRE_MM
+ { 2501, 3, 0, 4, 320, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2501 = SWR_MM
+ { 2502, 3, 0, 2, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2502 = SWSP_MM
+ { 2503, 3, 0, 2, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2503 = SWSP_MMR6
+ { 2504, 3, 0, 4, 675, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2504 = SWXC1
+ { 2505, 3, 0, 4, 322, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2505 = SWXC1_MM
+ { 2506, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2506 = SW_MM
+ { 2507, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #2507 = SW_MMR6
+ { 2508, 1, 0, 4, 453, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2508 = SYNC
+ { 2509, 2, 0, 4, 454, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2509 = SYNCI
+ { 2510, 2, 0, 4, 324, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2510 = SYNCI_MM
+ { 2511, 2, 0, 4, 324, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2511 = SYNCI_MMR6
+ { 2512, 1, 0, 4, 323, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2512 = SYNC_MM
+ { 2513, 1, 0, 4, 323, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2513 = SYNC_MMR6
+ { 2514, 1, 0, 4, 382, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2514 = SYSCALL
+ { 2515, 1, 0, 4, 325, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2515 = SYSCALL_MM
+ { 2516, 0, 0, 2, 326, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2516 = Save16
+ { 2517, 0, 0, 2, 326, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2517 = SaveX16
+ { 2518, 3, 0, 4, 275, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2518 = SbRxRyOffMemX16
+ { 2519, 2, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2519 = SebRx16
+ { 2520, 2, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2520 = SehRx16
+ { 2521, 3, 0, 4, 297, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2521 = ShRxRyOffMemX16
+ { 2522, 3, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #2522 = SllX16
+ { 2523, 3, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2523 = SllvRxRy16
+ { 2524, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo111, -1 ,nullptr }, // Inst #2524 = SltRxRy16
+ { 2525, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #2525 = SltiRxImm16
+ { 2526, 2, 0, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #2526 = SltiRxImmX16
+ { 2527, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #2527 = SltiuRxImm16
+ { 2528, 2, 0, 4, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo160, -1 ,nullptr }, // Inst #2528 = SltiuRxImmX16
+ { 2529, 2, 0, 2, 38, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo111, -1 ,nullptr }, // Inst #2529 = SltuRxRy16
+ { 2530, 3, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #2530 = SraX16
+ { 2531, 3, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2531 = SravRxRy16
+ { 2532, 3, 1, 4, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #2532 = SrlX16
+ { 2533, 3, 1, 2, 38, 0, 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2533 = SrlvRxRy16
+ { 2534, 3, 1, 2, 38, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #2534 = SubuRxRyRz16
+ { 2535, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2535 = SwRxRyOffMemX16
+ { 2536, 3, 0, 4, 311, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #2536 = SwRxSpImmX16
+ { 2537, 3, 0, 4, 383, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2537 = TEQ
+ { 2538, 2, 0, 4, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2538 = TEQI
+ { 2539, 2, 0, 4, 328, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2539 = TEQI_MM
+ { 2540, 3, 0, 4, 327, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2540 = TEQ_MM
+ { 2541, 3, 0, 4, 385, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2541 = TGE
+ { 2542, 2, 0, 4, 386, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2542 = TGEI
+ { 2543, 2, 0, 4, 387, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2543 = TGEIU
+ { 2544, 2, 0, 4, 331, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2544 = TGEIU_MM
+ { 2545, 2, 0, 4, 330, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2545 = TGEI_MM
+ { 2546, 3, 0, 4, 388, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2546 = TGEU
+ { 2547, 3, 0, 4, 332, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2547 = TGEU_MM
+ { 2548, 3, 0, 4, 329, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2548 = TGE_MM
+ { 2549, 0, 0, 4, 333, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2549 = TLBGINV
+ { 2550, 0, 0, 4, 334, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2550 = TLBGINVF
+ { 2551, 0, 0, 4, 334, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2551 = TLBGINVF_MM
+ { 2552, 0, 0, 4, 333, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2552 = TLBGINV_MM
+ { 2553, 0, 0, 4, 335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2553 = TLBGP
+ { 2554, 0, 0, 4, 335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2554 = TLBGP_MM
+ { 2555, 0, 0, 4, 336, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2555 = TLBGR
+ { 2556, 0, 0, 4, 336, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2556 = TLBGR_MM
+ { 2557, 0, 0, 4, 337, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2557 = TLBGWI
+ { 2558, 0, 0, 4, 337, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2558 = TLBGWI_MM
+ { 2559, 0, 0, 4, 338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2559 = TLBGWR
+ { 2560, 0, 0, 4, 338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2560 = TLBGWR_MM
+ { 2561, 0, 0, 4, 402, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2561 = TLBINV
+ { 2562, 0, 0, 4, 403, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2562 = TLBINVF
+ { 2563, 0, 0, 4, 340, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2563 = TLBINVF_MMR6
+ { 2564, 0, 0, 4, 339, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2564 = TLBINV_MMR6
+ { 2565, 0, 0, 4, 404, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2565 = TLBP
+ { 2566, 0, 0, 4, 341, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2566 = TLBP_MM
+ { 2567, 0, 0, 4, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2567 = TLBR
+ { 2568, 0, 0, 4, 342, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2568 = TLBR_MM
+ { 2569, 0, 0, 4, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2569 = TLBWI
+ { 2570, 0, 0, 4, 343, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2570 = TLBWI_MM
+ { 2571, 0, 0, 4, 407, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2571 = TLBWR
+ { 2572, 0, 0, 4, 344, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2572 = TLBWR_MM
+ { 2573, 3, 0, 4, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2573 = TLT
+ { 2574, 2, 0, 4, 390, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2574 = TLTI
+ { 2575, 2, 0, 4, 347, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2575 = TLTIU_MM
+ { 2576, 2, 0, 4, 346, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2576 = TLTI_MM
+ { 2577, 3, 0, 4, 391, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2577 = TLTU
+ { 2578, 3, 0, 4, 348, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2578 = TLTU_MM
+ { 2579, 3, 0, 4, 345, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2579 = TLT_MM
+ { 2580, 3, 0, 4, 392, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2580 = TNE
+ { 2581, 2, 0, 4, 393, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2581 = TNEI
+ { 2582, 2, 0, 4, 350, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2582 = TNEI_MM
+ { 2583, 3, 0, 4, 349, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2583 = TNE_MM
+ { 2584, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2584 = TRUNC_L_D64
+ { 2585, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2585 = TRUNC_L_D_MMR6
+ { 2586, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2586 = TRUNC_L_S
+ { 2587, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2587 = TRUNC_L_S_MMR6
+ { 2588, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2588 = TRUNC_W_D32
+ { 2589, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #2589 = TRUNC_W_D64
+ { 2590, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2590 = TRUNC_W_D_MMR6
+ { 2591, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2591 = TRUNC_W_MM
+ { 2592, 2, 1, 4, 611, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2592 = TRUNC_W_S
+ { 2593, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2593 = TRUNC_W_S_MM
+ { 2594, 2, 1, 4, 351, 0, 0x4ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #2594 = TRUNC_W_S_MMR6
+ { 2595, 2, 0, 4, 395, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2595 = TTLTIU
+ { 2596, 2, 0, 4, 466, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2596 = UDIV
+ { 2597, 2, 0, 4, 23, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo31, -1 ,nullptr }, // Inst #2597 = UDIV_MM
+ { 2598, 3, 1, 4, 108, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList33, OperandInfo57, -1 ,nullptr }, // Inst #2598 = V3MULU
+ { 2599, 3, 1, 4, 108, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList25, OperandInfo57, -1 ,nullptr }, // Inst #2599 = VMM0
+ { 2600, 3, 1, 4, 108, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList34, OperandInfo57, -1 ,nullptr }, // Inst #2600 = VMULU
+ { 2601, 4, 1, 4, 496, 0, 0x6ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2601 = VSHF_B
+ { 2602, 4, 1, 4, 496, 0, 0x6ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #2602 = VSHF_D
+ { 2603, 4, 1, 4, 496, 0, 0x6ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #2603 = VSHF_H
+ { 2604, 4, 1, 4, 496, 0, 0x6ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #2604 = VSHF_W
+ { 2605, 0, 0, 4, 396, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2605 = WAIT
+ { 2606, 1, 0, 4, 352, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2606 = WAIT_MM
+ { 2607, 1, 0, 4, 352, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2607 = WAIT_MMR6
+ { 2608, 2, 0, 4, 803, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2608 = WRDSP
+ { 2609, 2, 0, 4, 966, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2609 = WRDSP_MM
+ { 2610, 2, 1, 4, 353, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2610 = WRPGPR_MMR6
+ { 2611, 2, 1, 4, 462, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2611 = WSBH
+ { 2612, 2, 1, 4, 354, 0, 0x1ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2612 = WSBH_MM
+ { 2613, 2, 1, 4, 354, 0, 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2613 = WSBH_MMR6
+ { 2614, 3, 1, 4, 365, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2614 = XOR
+ { 2615, 3, 1, 2, 355, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2615 = XOR16_MM
+ { 2616, 3, 1, 2, 355, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2616 = XOR16_MMR6
+ { 2617, 3, 1, 4, 355, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #2617 = XOR64
+ { 2618, 3, 1, 4, 529, 0, 0x6ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2618 = XORI_B
+ { 2619, 3, 1, 4, 356, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2619 = XORI_MMR6
+ { 2620, 3, 1, 4, 355, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2620 = XOR_MM
+ { 2621, 3, 1, 4, 355, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2621 = XOR_MMR6
+ { 2622, 3, 1, 4, 528, 0, 0x6ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2622 = XOR_V
+ { 2623, 3, 1, 4, 489, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2623 = XORi
+ { 2624, 3, 1, 4, 355, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #2624 = XORi64
+ { 2625, 3, 1, 4, 356, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2625 = XORi_MM
+ { 2626, 3, 1, 2, 38, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2626 = XorRxRxRy16
+ { 2627, 2, 1, 4, 357, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #2627 = YIELD
+};
+
+extern const char MipsInstrNameData[] = {
+ /* 0 */ 'D', 'M', 'F', 'C', '0', 0,
+ /* 6 */ 'D', 'M', 'F', 'G', 'C', '0', 0,
+ /* 13 */ 'M', 'F', 'H', 'G', 'C', '0', 0,
+ /* 20 */ 'M', 'T', 'H', 'G', 'C', '0', 0,
+ /* 27 */ 'D', 'M', 'T', 'G', 'C', '0', 0,
+ /* 34 */ 'M', 'F', 'T', 'C', '0', 0,
+ /* 40 */ 'D', 'M', 'T', 'C', '0', 0,
+ /* 46 */ 'M', 'T', 'T', 'C', '0', 0,
+ /* 52 */ 'V', 'M', 'M', '0', 0,
+ /* 57 */ 'M', 'T', 'M', '0', 0,
+ /* 62 */ 'M', 'T', 'P', '0', 0,
+ /* 67 */ 'B', 'B', 'I', 'T', '0', 0,
+ /* 73 */ 'L', 'D', 'C', '1', 0,
+ /* 78 */ 'S', 'D', 'C', '1', 0,
+ /* 83 */ 'C', 'F', 'C', '1', 0,
+ /* 88 */ 'D', 'M', 'F', 'C', '1', 0,
+ /* 94 */ 'M', 'F', 'T', 'H', 'C', '1', 0,
+ /* 101 */ 'M', 'T', 'T', 'H', 'C', '1', 0,
+ /* 108 */ 'C', 'T', 'C', '1', 0,
+ /* 113 */ 'C', 'F', 'T', 'C', '1', 0,
+ /* 119 */ 'M', 'F', 'T', 'C', '1', 0,
+ /* 125 */ 'D', 'M', 'T', 'C', '1', 0,
+ /* 131 */ 'C', 'T', 'T', 'C', '1', 0,
+ /* 137 */ 'M', 'T', 'T', 'C', '1', 0,
+ /* 143 */ 'L', 'W', 'C', '1', 0,
+ /* 148 */ 'S', 'W', 'C', '1', 0,
+ /* 153 */ 'L', 'D', 'X', 'C', '1', 0,
+ /* 159 */ 'S', 'D', 'X', 'C', '1', 0,
+ /* 165 */ 'L', 'U', 'X', 'C', '1', 0,
+ /* 171 */ 'S', 'U', 'X', 'C', '1', 0,
+ /* 177 */ 'L', 'W', 'X', 'C', '1', 0,
+ /* 183 */ 'S', 'W', 'X', 'C', '1', 0,
+ /* 189 */ 'M', 'T', 'M', '1', 0,
+ /* 194 */ 'M', 'T', 'P', '1', 0,
+ /* 199 */ 'B', 'B', 'I', 'T', '1', 0,
+ /* 205 */ 'B', 'B', 'I', 'T', '0', '3', '2', 0,
+ /* 213 */ 'B', 'B', 'I', 'T', '1', '3', '2', 0,
+ /* 221 */ 'D', 'S', 'R', 'A', '3', '2', 0,
+ /* 228 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', 0,
+ /* 238 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', 0,
+ /* 248 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', 0,
+ /* 257 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', 0,
+ /* 267 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', 0,
+ /* 276 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', 0,
+ /* 286 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', 0,
+ /* 296 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', 0,
+ /* 307 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', 0,
+ /* 317 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', 0,
+ /* 327 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', 0,
+ /* 336 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', 0,
+ /* 345 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', 0,
+ /* 354 */ 'C', '_', 'F', '_', 'D', '3', '2', 0,
+ /* 362 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '3', '2', 0,
+ /* 383 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', 0,
+ /* 392 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', 0,
+ /* 403 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', 0,
+ /* 414 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', 0,
+ /* 424 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', 0,
+ /* 433 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', 0,
+ /* 442 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', 0,
+ /* 452 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', 0,
+ /* 461 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', 0,
+ /* 471 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', 0,
+ /* 481 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', 0,
+ /* 490 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', 0,
+ /* 499 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', 0,
+ /* 509 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '3', '2', 0,
+ /* 526 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', 0,
+ /* 536 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', 0,
+ /* 546 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', 0,
+ /* 556 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', 0,
+ /* 565 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0,
+ /* 575 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0,
+ /* 585 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', 0,
+ /* 594 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '3', '2', 0,
+ /* 615 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', 0,
+ /* 624 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', 0,
+ /* 633 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '3', '2', 0,
+ /* 651 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '3', '2', 0,
+ /* 663 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '3', '2', 0,
+ /* 674 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '3', '2', 0,
+ /* 686 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', 0,
+ /* 696 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 0,
+ /* 705 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0,
+ /* 725 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0,
+ /* 745 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
+ /* 766 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0,
+ /* 786 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0,
+ /* 802 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0,
+ /* 822 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0,
+ /* 842 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0,
+ /* 861 */ 'D', 'S', 'L', 'L', '3', '2', 0,
+ /* 868 */ 'D', 'S', 'R', 'L', '3', '2', 0,
+ /* 875 */ 'D', 'R', 'O', 'T', 'R', '3', '2', 0,
+ /* 883 */ 'C', 'I', 'N', 'S', '3', '2', 0,
+ /* 890 */ 'E', 'X', 'T', 'S', '3', '2', 0,
+ /* 897 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', 0,
+ /* 906 */ 'D', 'S', 'L', 'L', '6', '4', '_', '3', '2', 0,
+ /* 916 */ 'C', 'I', 'N', 'S', '6', '4', '_', '3', '2', 0,
+ /* 926 */ 'D', 'E', 'X', 'T', '6', '4', '_', '3', '2', 0,
+ /* 936 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', '_', '3', '2', 0,
+ /* 956 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '3', '2', 0,
+ /* 970 */ 'C', 'I', 'N', 'S', '_', 'i', '3', '2', 0,
+ /* 979 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '3', '2', 0,
+ /* 989 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '3', '2', 0,
+ /* 1003 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '3', '2', 0,
+ /* 1019 */ 'L', 'w', 'C', 'o', 'n', 's', 't', 'a', 'n', 't', '3', '2', 0,
+ /* 1032 */ 'L', 'D', 'C', '2', 0,
+ /* 1037 */ 'S', 'D', 'C', '2', 0,
+ /* 1042 */ 'D', 'M', 'F', 'C', '2', 0,
+ /* 1048 */ 'D', 'M', 'T', 'C', '2', 0,
+ /* 1054 */ 'L', 'W', 'C', '2', 0,
+ /* 1059 */ 'S', 'W', 'C', '2', 0,
+ /* 1064 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
+ /* 1072 */ 'M', 'T', 'M', '2', 0,
+ /* 1077 */ 'M', 'T', 'P', '2', 0,
+ /* 1082 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
+ /* 1090 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1103 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1121 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1135 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1149 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1167 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1182 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1198 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1214 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1230 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1245 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1263 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0,
+ /* 1277 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0,
+ /* 1290 */ 'A', 'P', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0,
+ /* 1302 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1319 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1333 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1347 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1360 */ 'M', 'U', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1372 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1388 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1404 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1418 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1433 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1448 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1463 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1476 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1489 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1503 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1517 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1533 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1552 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1571 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1585 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1603 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1621 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1636 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0,
+ /* 1651 */ 'B', 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '2', 0,
+ /* 1663 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
+ /* 1683 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
+ /* 1705 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
+ /* 1718 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
+ /* 1731 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
+ /* 1746 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
+ /* 1761 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
+ /* 1776 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0,
+ /* 1790 */ 'L', 'D', 'C', '3', 0,
+ /* 1795 */ 'S', 'D', 'C', '3', 0,
+ /* 1800 */ 'L', 'W', 'C', '3', 0,
+ /* 1805 */ 'S', 'W', 'C', '3', 0,
+ /* 1810 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 'C', '_', 'M', 'M', 'R', '3', 0,
+ /* 1825 */ 'L', 'D', 'C', '1', '6', '4', 0,
+ /* 1832 */ 'S', 'D', 'C', '1', '6', '4', 0,
+ /* 1839 */ 'L', 'D', 'X', 'C', '1', '6', '4', 0,
+ /* 1847 */ 'S', 'D', 'X', 'C', '1', '6', '4', 0,
+ /* 1855 */ 'L', 'U', 'X', 'C', '1', '6', '4', 0,
+ /* 1863 */ 'S', 'U', 'X', 'C', '1', '6', '4', 0,
+ /* 1871 */ 'S', 'E', 'B', '6', '4', 0,
+ /* 1877 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', '6', '4', 0,
+ /* 1893 */ 'J', 'R', '_', 'H', 'B', '6', '4', 0,
+ /* 1901 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', '6', '4', 0,
+ /* 1911 */ 'L', 'B', '6', '4', 0,
+ /* 1916 */ 'S', 'B', '6', '4', 0,
+ /* 1921 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 0,
+ /* 1932 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 0,
+ /* 1944 */ 'B', 'G', 'E', 'C', '6', '4', 0,
+ /* 1951 */ 'B', 'N', 'E', 'C', '6', '4', 0,
+ /* 1958 */ 'J', 'I', 'C', '6', '4', 0,
+ /* 1964 */ 'J', 'I', 'A', 'L', 'C', '6', '4', 0,
+ /* 1972 */ 'B', 'E', 'Q', 'C', '6', '4', 0,
+ /* 1979 */ 'S', 'C', '6', '4', 0,
+ /* 1984 */ 'B', 'L', 'T', 'C', '6', '4', 0,
+ /* 1991 */ 'B', 'G', 'E', 'U', 'C', '6', '4', 0,
+ /* 1999 */ 'B', 'L', 'T', 'U', 'C', '6', '4', 0,
+ /* 2007 */ 'B', 'G', 'E', 'Z', 'C', '6', '4', 0,
+ /* 2015 */ 'B', 'L', 'E', 'Z', 'C', '6', '4', 0,
+ /* 2023 */ 'B', 'N', 'E', 'Z', 'C', '6', '4', 0,
+ /* 2031 */ 'B', 'E', 'Q', 'Z', 'C', '6', '4', 0,
+ /* 2039 */ 'B', 'G', 'T', 'Z', 'C', '6', '4', 0,
+ /* 2047 */ 'B', 'L', 'T', 'Z', 'C', '6', '4', 0,
+ /* 2055 */ 'A', 'N', 'D', '6', '4', 0,
+ /* 2061 */ 'M', 'F', 'C', '1', '_', 'D', '6', '4', 0,
+ /* 2070 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '6', '4', 0,
+ /* 2080 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '6', '4', 0,
+ /* 2090 */ 'M', 'T', 'C', '1', '_', 'D', '6', '4', 0,
+ /* 2099 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'D', '6', '4', 0,
+ /* 2112 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'D', '6', '4', 0,
+ /* 2125 */ 'F', 'S', 'U', 'B', '_', 'D', '6', '4', 0,
+ /* 2134 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '6', '4', 0,
+ /* 2144 */ 'F', 'A', 'D', 'D', '_', 'D', '6', '4', 0,
+ /* 2153 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '6', '4', 0,
+ /* 2163 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '6', '4', 0,
+ /* 2173 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '6', '4', 0,
+ /* 2184 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '6', '4', 0,
+ /* 2194 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '6', '4', 0,
+ /* 2204 */ 'C', '_', 'L', 'E', '_', 'D', '6', '4', 0,
+ /* 2213 */ 'C', '_', 'S', 'F', '_', 'D', '6', '4', 0,
+ /* 2222 */ 'M', 'O', 'V', 'F', '_', 'D', '6', '4', 0,
+ /* 2231 */ 'C', '_', 'F', '_', 'D', '6', '4', 0,
+ /* 2239 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '6', '4', 0,
+ /* 2260 */ 'F', 'N', 'E', 'G', '_', 'D', '6', '4', 0,
+ /* 2269 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '6', '4', 0,
+ /* 2280 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '6', '4', 0,
+ /* 2291 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '6', '4', 0,
+ /* 2301 */ 'F', 'M', 'U', 'L', '_', 'D', '6', '4', 0,
+ /* 2310 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '6', '4', 0,
+ /* 2322 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '6', '4', 0,
+ /* 2334 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '6', '4', 0,
+ /* 2345 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '6', '4', 0,
+ /* 2357 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '6', '4', 0,
+ /* 2367 */ 'C', '_', 'U', 'N', '_', 'D', '6', '4', 0,
+ /* 2376 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '6', '4', 0,
+ /* 2386 */ 'F', 'C', 'M', 'P', '_', 'D', '6', '4', 0,
+ /* 2395 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '6', '4', 0,
+ /* 2405 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '6', '4', 0,
+ /* 2415 */ 'C', '_', 'E', 'Q', '_', 'D', '6', '4', 0,
+ /* 2424 */ 'F', 'A', 'B', 'S', '_', 'D', '6', '4', 0,
+ /* 2433 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '6', '4', 0,
+ /* 2443 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '6', '4', 0,
+ /* 2460 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '6', '4', 0,
+ /* 2470 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '6', '4', 0,
+ /* 2480 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '6', '4', 0,
+ /* 2490 */ 'C', '_', 'L', 'T', '_', 'D', '6', '4', 0,
+ /* 2499 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0,
+ /* 2509 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0,
+ /* 2519 */ 'M', 'O', 'V', 'T', '_', 'D', '6', '4', 0,
+ /* 2528 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '6', '4', 0,
+ /* 2549 */ 'F', 'D', 'I', 'V', '_', 'D', '6', '4', 0,
+ /* 2558 */ 'F', 'M', 'O', 'V', '_', 'D', '6', '4', 0,
+ /* 2567 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '6', '4', 0,
+ /* 2579 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '6', '4', 0,
+ /* 2591 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '6', '4', 0,
+ /* 2602 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '6', '4', 0,
+ /* 2614 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '6', '4', 0,
+ /* 2624 */ 'B', 'N', 'E', '6', '4', 0,
+ /* 2630 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', 0,
+ /* 2643 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', 0,
+ /* 2661 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '6', '4', 0,
+ /* 2675 */ 'S', 'E', 'H', '6', '4', 0,
+ /* 2681 */ 'L', 'H', '6', '4', 0,
+ /* 2686 */ 'S', 'H', '6', '4', 0,
+ /* 2691 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', '6', '4', 0,
+ /* 2704 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '6', '4', 0,
+ /* 2719 */ 'M', 'T', 'H', 'I', '6', '4', 0,
+ /* 2726 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'I', '6', '4', 0,
+ /* 2739 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'I', '6', '4', 0,
+ /* 2752 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0,
+ /* 2772 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0,
+ /* 2792 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
+ /* 2813 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0,
+ /* 2833 */ 'M', 'O', 'V', 'F', '_', 'I', '6', '4', 0,
+ /* 2842 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'I', '6', '4', 0,
+ /* 2863 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'I', '6', '4', 0,
+ /* 2874 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'I', '6', '4', 0,
+ /* 2885 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0,
+ /* 2901 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0,
+ /* 2921 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0,
+ /* 2941 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', 0,
+ /* 2960 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', 0,
+ /* 2977 */ 'M', 'O', 'V', 'T', '_', 'I', '6', '4', 0,
+ /* 2986 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'I', '6', '4', 0,
+ /* 3007 */ 'L', 'L', '6', '4', 0,
+ /* 3012 */ 'L', 'W', 'L', '6', '4', 0,
+ /* 3018 */ 'S', 'W', 'L', '6', '4', 0,
+ /* 3024 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', '6', '4', 0,
+ /* 3037 */ 'M', 'T', 'L', 'O', '6', '4', 0,
+ /* 3044 */ 'B', 'E', 'Q', '6', '4', 0,
+ /* 3050 */ 'J', 'R', '6', '4', 0,
+ /* 3055 */ 'J', 'A', 'L', 'R', '6', '4', 0,
+ /* 3062 */ 'N', 'O', 'R', '6', '4', 0,
+ /* 3068 */ 'X', 'O', 'R', '6', '4', 0,
+ /* 3074 */ 'R', 'D', 'H', 'W', 'R', '6', '4', 0,
+ /* 3082 */ 'L', 'W', 'R', '6', '4', 0,
+ /* 3088 */ 'S', 'W', 'R', '6', '4', 0,
+ /* 3094 */ 'S', 'L', 'T', '6', '4', 0,
+ /* 3100 */ 'L', 'W', '6', '4', 0,
+ /* 3105 */ 'S', 'W', '6', '4', 0,
+ /* 3110 */ 'B', 'G', 'E', 'Z', '6', '4', 0,
+ /* 3117 */ 'B', 'L', 'E', 'Z', '6', '4', 0,
+ /* 3124 */ 'S', 'E', 'L', 'N', 'E', 'Z', '6', '4', 0,
+ /* 3133 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '6', '4', 0,
+ /* 3142 */ 'B', 'G', 'T', 'Z', '6', '4', 0,
+ /* 3149 */ 'B', 'L', 'T', 'Z', '6', '4', 0,
+ /* 3156 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', '_', '6', '4', 0,
+ /* 3172 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', '_', '6', '4', 0,
+ /* 3193 */ 'S', 'L', 'L', '6', '4', '_', '6', '4', 0,
+ /* 3202 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '6', '4', 0,
+ /* 3216 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0,
+ /* 3245 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0,
+ /* 3268 */ 'A', 'N', 'D', 'i', '6', '4', 0,
+ /* 3275 */ 'X', 'O', 'R', 'i', '6', '4', 0,
+ /* 3282 */ 'S', 'L', 'T', 'i', '6', '4', 0,
+ /* 3289 */ 'L', 'U', 'i', '6', '4', 0,
+ /* 3295 */ 'N', 'O', 'R', 'I', 'm', 'm', '6', '4', 0,
+ /* 3304 */ 'S', 'L', 'T', 'I', 'm', 'm', '6', '4', 0,
+ /* 3313 */ 'S', 'L', 'T', 'U', 'I', 'm', 'm', '6', '4', 0,
+ /* 3323 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '6', '4', 0,
+ /* 3333 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '6', '4', 0,
+ /* 3347 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', '6', '4', 0,
+ /* 3362 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '6', '4', 0,
+ /* 3378 */ 'L', 'B', 'u', '6', '4', 0,
+ /* 3384 */ 'L', 'H', 'u', '6', '4', 0,
+ /* 3390 */ 'S', 'L', 'T', 'u', '6', '4', 0,
+ /* 3397 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', '6', '4', 0,
+ /* 3409 */ 'S', 'L', 'T', 'i', 'u', '6', '4', 0,
+ /* 3417 */ 'M', 'o', 'v', 'e', 'R', '3', '2', '1', '6', 0,
+ /* 3427 */ 'R', 'e', 't', 'R', 'A', '1', '6', 0,
+ /* 3435 */ 'J', 'a', 'l', 'B', '1', '6', 0,
+ /* 3442 */ 'L', 'D', '_', 'F', '1', '6', 0,
+ /* 3449 */ 'S', 'T', '_', 'F', '1', '6', 0,
+ /* 3456 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', 0,
+ /* 3476 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', 0,
+ /* 3496 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', 0,
+ /* 3517 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', 0,
+ /* 3537 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0,
+ /* 3553 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0,
+ /* 3573 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', 0,
+ /* 3593 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', 0,
+ /* 3612 */ 'M', 'o', 'v', 'e', '3', '2', 'R', '1', '6', 0,
+ /* 3622 */ 'S', 'r', 'a', 'X', '1', '6', 0,
+ /* 3629 */ 'R', 'e', 's', 't', 'o', 'r', 'e', 'X', '1', '6', 0,
+ /* 3640 */ 'S', 'a', 'v', 'e', 'X', '1', '6', 0,
+ /* 3648 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0,
+ /* 3663 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0,
+ /* 3678 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0,
+ /* 3693 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0,
+ /* 3708 */ 'S', 'l', 'l', 'X', '1', '6', 0,
+ /* 3715 */ 'S', 'r', 'l', 'X', '1', '6', 0,
+ /* 3722 */ 'L', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3738 */ 'S', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3754 */ 'L', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3770 */ 'S', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3786 */ 'L', 'b', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3803 */ 'L', 'h', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3820 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3839 */ 'L', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3855 */ 'S', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0,
+ /* 3871 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'P', 'c', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3887 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3901 */ 'L', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3914 */ 'S', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3927 */ 'S', 'l', 't', 'i', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3942 */ 'S', 'l', 't', 'i', 'u', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3958 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3969 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3982 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 3995 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 4009 */ 'S', 'l', 't', 'i', 'u', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 4023 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 4039 */ 'B', 'n', 'e', 'z', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 4052 */ 'B', 'e', 'q', 'z', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0,
+ /* 4065 */ 'B', 'i', 'm', 'm', 'X', '1', '6', 0,
+ /* 4073 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'A', 'l', 'i', 'g', 'n', 'X', '1', '6', 0,
+ /* 4089 */ 'L', 'w', 'R', 'x', 'P', 'c', 'T', 'c', 'p', 'X', '1', '6', 0,
+ /* 4102 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'X', '1', '6', 0,
+ /* 4116 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'X', '1', '6', 0,
+ /* 4130 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'X', '1', '6', 0,
+ /* 4144 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'X', '1', '6', 0,
+ /* 4158 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'u', 'X', '1', '6', 0,
+ /* 4174 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'u', 'X', '1', '6', 0,
+ /* 4190 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'u', 'X', '1', '6', 0,
+ /* 4205 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'u', 'X', '1', '6', 0,
+ /* 4220 */ 'B', 't', 'n', 'e', 'z', 'X', '1', '6', 0,
+ /* 4229 */ 'B', 't', 'e', 'q', 'z', 'X', '1', '6', 0,
+ /* 4238 */ 'J', 'r', 'c', 'R', 'a', '1', '6', 0,
+ /* 4246 */ 'J', 'r', 'R', 'a', '1', '6', 0,
+ /* 4253 */ 'R', 'e', 's', 't', 'o', 'r', 'e', '1', '6', 0,
+ /* 4263 */ 'G', 'o', 't', 'P', 'r', 'o', 'l', 'o', 'g', 'u', 'e', '1', '6', 0,
+ /* 4277 */ 'S', 'a', 'v', 'e', '1', '6', 0,
+ /* 4284 */ 'J', 'u', 'm', 'p', 'L', 'i', 'n', 'k', 'R', 'e', 'g', '1', '6', 0,
+ /* 4298 */ 'M', 'f', 'h', 'i', '1', '6', 0,
+ /* 4305 */ 'B', 'r', 'e', 'a', 'k', '1', '6', 0,
+ /* 4313 */ 'J', 'a', 'l', '1', '6', 0,
+ /* 4319 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', '1', '6', 0,
+ /* 4332 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
+ /* 4342 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
+ /* 4354 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
+ /* 4366 */ 'S', 'l', 't', 'i', 'u', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
+ /* 4379 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
+ /* 4394 */ 'B', 'n', 'e', 'z', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
+ /* 4406 */ 'B', 'e', 'q', 'z', 'R', 'x', 'I', 'm', 'm', '1', '6', 0,
+ /* 4418 */ 'B', 'i', 'm', 'm', '1', '6', 0,
+ /* 4425 */ 'M', 'f', 'l', 'o', '1', '6', 0,
+ /* 4432 */ 'L', 'w', 'R', 'x', 'P', 'c', 'T', 'c', 'p', '1', '6', 0,
+ /* 4444 */ 'S', 'e', 'b', 'R', 'x', '1', '6', 0,
+ /* 4452 */ 'J', 'r', 'c', 'R', 'x', '1', '6', 0,
+ /* 4460 */ 'S', 'e', 'h', 'R', 'x', '1', '6', 0,
+ /* 4468 */ 'S', 'l', 't', 'C', 'C', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4480 */ 'S', 'l', 't', 'u', 'C', 'C', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4493 */ 'N', 'e', 'g', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4503 */ 'C', 'm', 'p', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4513 */ 'S', 'l', 't', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4523 */ 'M', 'u', 'l', 't', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4534 */ 'N', 'o', 't', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4544 */ 'S', 'l', 't', 'u', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4555 */ 'M', 'u', 'l', 't', 'u', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4567 */ 'D', 'i', 'v', 'u', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4578 */ 'S', 'r', 'a', 'v', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4589 */ 'D', 'i', 'v', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4599 */ 'S', 'l', 'l', 'v', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4610 */ 'S', 'r', 'l', 'v', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4621 */ 'A', 'n', 'd', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4633 */ 'O', 'r', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4644 */ 'X', 'o', 'r', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0,
+ /* 4656 */ 'M', 'u', 'l', 't', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
+ /* 4669 */ 'S', 'u', 'b', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
+ /* 4682 */ 'A', 'd', 'd', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
+ /* 4695 */ 'S', 'l', 't', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
+ /* 4708 */ 'M', 'u', 'l', 't', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0,
+ /* 4722 */ 'B', 't', 'n', 'e', 'z', '1', '6', 0,
+ /* 4730 */ 'B', 't', 'e', 'q', 'z', '1', '6', 0,
+ /* 4738 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 'R', '6', 0,
+ /* 4768 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 'R', '6', 0,
+ /* 4793 */ 'M', 'F', 'C', '0', '_', 'M', 'M', 'R', '6', 0,
+ /* 4803 */ 'M', 'F', 'H', 'C', '0', '_', 'M', 'M', 'R', '6', 0,
+ /* 4814 */ 'M', 'T', 'H', 'C', '0', '_', 'M', 'M', 'R', '6', 0,
+ /* 4825 */ 'M', 'T', 'C', '0', '_', 'M', 'M', 'R', '6', 0,
+ /* 4835 */ 'M', 'F', 'C', '1', '_', 'M', 'M', 'R', '6', 0,
+ /* 4845 */ 'M', 'T', 'C', '1', '_', 'M', 'M', 'R', '6', 0,
+ /* 4855 */ 'L', 'D', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
+ /* 4865 */ 'S', 'D', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
+ /* 4875 */ 'M', 'F', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
+ /* 4885 */ 'M', 'F', 'H', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
+ /* 4896 */ 'M', 'T', 'H', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
+ /* 4907 */ 'M', 'T', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
+ /* 4917 */ 'L', 'W', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
+ /* 4927 */ 'S', 'W', 'C', '2', '_', 'M', 'M', 'R', '6', 0,
+ /* 4937 */ 'L', 'D', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 'R', '6', 0,
+ /* 4951 */ 'S', 'D', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 'R', '6', 0,
+ /* 4965 */ 'S', 'B', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 4975 */ 'B', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 4985 */ 'J', 'R', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 4996 */ 'J', 'A', 'L', 'R', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5009 */ 'B', 'N', 'E', 'Z', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5022 */ 'B', 'E', 'Q', 'Z', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5035 */ 'A', 'N', 'D', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5046 */ 'M', 'O', 'V', 'E', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5058 */ 'S', 'H', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5068 */ 'A', 'N', 'D', 'I', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5080 */ 'L', 'I', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5090 */ 'B', 'R', 'E', 'A', 'K', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5103 */ 'S', 'L', 'L', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5114 */ 'S', 'R', 'L', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5125 */ 'L', 'W', 'M', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5136 */ 'S', 'W', 'M', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5147 */ 'S', 'D', 'B', 'B', 'P', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5160 */ 'X', 'O', 'R', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5171 */ 'N', 'O', 'T', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5182 */ 'S', 'U', 'B', 'U', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5194 */ 'A', 'D', 'D', 'U', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5206 */ 'S', 'W', '1', '6', '_', 'M', 'M', 'R', '6', 0,
+ /* 5216 */ 'L', 'S', 'A', '_', 'M', 'M', 'R', '6', 0,
+ /* 5225 */ 'E', 'H', 'B', '_', 'M', 'M', 'R', '6', 0,
+ /* 5234 */ 'J', 'A', 'L', 'R', 'C', '_', 'H', 'B', '_', 'M', 'M', 'R', '6', 0,
+ /* 5248 */ 'L', 'B', '_', 'M', 'M', 'R', '6', 0,
+ /* 5256 */ 'S', 'B', '_', 'M', 'M', 'R', '6', 0,
+ /* 5264 */ 'S', 'U', 'B', '_', 'M', 'M', 'R', '6', 0,
+ /* 5273 */ 'B', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5281 */ 'B', 'G', 'E', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5291 */ 'B', 'N', 'E', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5301 */ 'J', 'I', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5310 */ 'B', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5320 */ 'J', 'I', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5331 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5344 */ 'B', 'L', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5357 */ 'B', 'N', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5370 */ 'B', 'E', 'Q', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5383 */ 'B', 'G', 'T', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5396 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5409 */ 'E', 'R', 'E', 'T', 'N', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5421 */ 'S', 'Y', 'N', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5431 */ 'A', 'U', 'I', 'P', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5442 */ 'A', 'L', 'U', 'I', 'P', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5454 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5467 */ 'L', 'W', 'P', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5477 */ 'B', 'E', 'Q', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5487 */ 'J', 'A', 'L', 'R', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5498 */ 'S', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5506 */ 'B', 'L', 'T', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5516 */ 'B', 'G', 'E', 'U', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5527 */ 'B', 'L', 'T', 'U', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5538 */ 'B', 'N', 'V', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5548 */ 'B', 'O', 'V', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5558 */ 'B', 'G', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5569 */ 'B', 'L', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5580 */ 'B', 'C', '1', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5593 */ 'B', 'C', '2', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5606 */ 'B', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5617 */ 'B', 'C', '1', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5630 */ 'B', 'C', '2', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5643 */ 'B', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5654 */ 'B', 'G', 'T', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5665 */ 'B', 'L', 'T', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0,
+ /* 5676 */ 'A', 'D', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5685 */ 'A', 'N', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5694 */ 'M', 'O', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5703 */ 'M', 'I', 'N', 'A', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5715 */ 'M', 'A', 'X', 'A', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5727 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5742 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5758 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5773 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5787 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5802 */ 'C', 'M', 'P', '_', 'A', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5816 */ 'M', 'S', 'U', 'B', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5829 */ 'M', 'A', 'D', 'D', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5842 */ 'S', 'E', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5853 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5868 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5883 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5897 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5912 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5925 */ 'M', 'I', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5936 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5951 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5965 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5980 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 5996 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6011 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6025 */ 'C', 'L', 'A', 'S', 'S', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6038 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6053 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6069 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6084 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6098 */ 'R', 'I', 'N', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6110 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6125 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6140 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6154 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6169 */ 'M', 'A', 'X', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6180 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6194 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'D', '_', 'M', 'M', 'R', '6', 0,
+ /* 6208 */ 'C', 'A', 'C', 'H', 'E', '_', 'M', 'M', 'R', '6', 0,
+ /* 6219 */ 'P', 'A', 'U', 'S', 'E', '_', 'M', 'M', 'R', '6', 0,
+ /* 6230 */ 'P', 'R', 'E', 'F', '_', 'M', 'M', 'R', '6', 0,
+ /* 6240 */ 'T', 'L', 'B', 'I', 'N', 'V', 'F', '_', 'M', 'M', 'R', '6', 0,
+ /* 6253 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '_', 'M', 'M', 'R', '6', 0,
+ /* 6270 */ 'W', 'S', 'B', 'H', '_', 'M', 'M', 'R', '6', 0,
+ /* 6280 */ 'S', 'H', '_', 'M', 'M', 'R', '6', 0,
+ /* 6288 */ 'M', 'U', 'H', '_', 'M', 'M', 'R', '6', 0,
+ /* 6297 */ 'S', 'Y', 'N', 'C', 'I', '_', 'M', 'M', 'R', '6', 0,
+ /* 6308 */ 'A', 'N', 'D', 'I', '_', 'M', 'M', 'R', '6', 0,
+ /* 6318 */ 'E', 'I', '_', 'M', 'M', 'R', '6', 0,
+ /* 6326 */ 'X', 'O', 'R', 'I', '_', 'M', 'M', 'R', '6', 0,
+ /* 6336 */ 'A', 'U', 'I', '_', 'M', 'M', 'R', '6', 0,
+ /* 6345 */ 'L', 'U', 'I', '_', 'M', 'M', 'R', '6', 0,
+ /* 6354 */ 'G', 'I', 'N', 'V', 'I', '_', 'M', 'M', 'R', '6', 0,
+ /* 6365 */ 'B', 'R', 'E', 'A', 'K', '_', 'M', 'M', 'R', '6', 0,
+ /* 6376 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '_', 'M', 'M', 'R', '6', 0,
+ /* 6390 */ 'S', 'L', 'L', '_', 'M', 'M', 'R', '6', 0,
+ /* 6399 */ 'M', 'U', 'L', '_', 'M', 'M', 'R', '6', 0,
+ /* 6408 */ 'C', 'V', 'T', '_', 'D', '_', 'L', '_', 'M', 'M', 'R', '6', 0,
+ /* 6421 */ 'C', 'V', 'T', '_', 'S', '_', 'L', '_', 'M', 'M', 'R', '6', 0,
+ /* 6434 */ 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '6', 0,
+ /* 6445 */ 'C', 'L', 'O', '_', 'M', 'M', 'R', '6', 0,
+ /* 6454 */ 'B', 'I', 'T', 'S', 'W', 'A', 'P', '_', 'M', 'M', 'R', '6', 0,
+ /* 6467 */ 'S', 'D', 'B', 'B', 'P', '_', 'M', 'M', 'R', '6', 0,
+ /* 6478 */ 'M', 'O', 'V', 'E', 'P', '_', 'M', 'M', 'R', '6', 0,
+ /* 6489 */ 'S', 'S', 'N', 'O', 'P', '_', 'M', 'M', 'R', '6', 0,
+ /* 6500 */ 'J', 'R', 'C', 'A', 'D', 'D', 'I', 'U', 'S', 'P', '_', 'M', 'M', 'R', '6', 0,
+ /* 6516 */ 'S', 'W', 'S', 'P', '_', 'M', 'M', 'R', '6', 0,
+ /* 6526 */ 'D', 'V', 'P', '_', 'M', 'M', 'R', '6', 0,
+ /* 6535 */ 'E', 'V', 'P', '_', 'M', 'M', 'R', '6', 0,
+ /* 6544 */ 'N', 'O', 'R', '_', 'M', 'M', 'R', '6', 0,
+ /* 6553 */ 'X', 'O', 'R', '_', 'M', 'M', 'R', '6', 0,
+ /* 6562 */ 'R', 'D', 'P', 'G', 'P', 'R', '_', 'M', 'M', 'R', '6', 0,
+ /* 6574 */ 'W', 'R', 'P', 'G', 'P', 'R', '_', 'M', 'M', 'R', '6', 0,
+ /* 6586 */ 'R', 'D', 'H', 'W', 'R', '_', 'M', 'M', 'R', '6', 0,
+ /* 6597 */ 'I', 'N', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6606 */ 'M', 'I', 'N', 'A', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6618 */ 'M', 'A', 'X', 'A', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6630 */ 'F', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6642 */ 'F', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6654 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6669 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6685 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6700 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6714 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6729 */ 'C', 'M', 'P', '_', 'A', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6743 */ 'M', 'S', 'U', 'B', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6756 */ 'M', 'A', 'D', 'D', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6769 */ 'F', 'N', 'E', 'G', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6781 */ 'S', 'E', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6792 */ 'F', 'M', 'U', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6804 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6819 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6834 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6848 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6863 */ 'C', 'V', 'T', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6876 */ 'M', 'I', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6887 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6902 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6916 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6931 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6947 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6962 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6976 */ 'C', 'L', 'A', 'S', 'S', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 6989 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7004 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7020 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7035 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7049 */ 'R', 'I', 'N', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7061 */ 'F', 'D', 'I', 'V', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7073 */ 'F', 'M', 'O', 'V', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7085 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7100 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7115 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7129 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7144 */ 'C', 'V', 'T', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7157 */ 'M', 'A', 'X', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7168 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7182 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'S', '_', 'M', 'M', 'R', '6', 0,
+ /* 7196 */ 'D', 'E', 'R', 'E', 'T', '_', 'M', 'M', 'R', '6', 0,
+ /* 7207 */ 'W', 'A', 'I', 'T', '_', 'M', 'M', 'R', '6', 0,
+ /* 7217 */ 'G', 'I', 'N', 'V', 'T', '_', 'M', 'M', 'R', '6', 0,
+ /* 7228 */ 'E', 'X', 'T', '_', 'M', 'M', 'R', '6', 0,
+ /* 7237 */ 'L', 'B', 'U', '_', 'M', 'M', 'R', '6', 0,
+ /* 7246 */ 'S', 'U', 'B', 'U', '_', 'M', 'M', 'R', '6', 0,
+ /* 7256 */ 'A', 'D', 'D', 'U', '_', 'M', 'M', 'R', '6', 0,
+ /* 7266 */ 'M', 'O', 'D', 'U', '_', 'M', 'M', 'R', '6', 0,
+ /* 7276 */ 'M', 'U', 'H', 'U', '_', 'M', 'M', 'R', '6', 0,
+ /* 7286 */ 'A', 'D', 'D', 'I', 'U', '_', 'M', 'M', 'R', '6', 0,
+ /* 7297 */ 'M', 'U', 'L', 'U', '_', 'M', 'M', 'R', '6', 0,
+ /* 7307 */ 'D', 'I', 'V', 'U', '_', 'M', 'M', 'R', '6', 0,
+ /* 7317 */ 'D', 'I', 'V', '_', 'M', 'M', 'R', '6', 0,
+ /* 7326 */ 'T', 'L', 'B', 'I', 'N', 'V', '_', 'M', 'M', 'R', '6', 0,
+ /* 7338 */ 'L', 'W', '_', 'M', 'M', 'R', '6', 0,
+ /* 7346 */ 'S', 'W', '_', 'M', 'M', 'R', '6', 0,
+ /* 7354 */ 'C', 'V', 'T', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '6', 0,
+ /* 7367 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'M', 'M', 'R', '6', 0,
+ /* 7379 */ 'C', 'L', 'Z', '_', 'M', 'M', 'R', '6', 0,
+ /* 7388 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'M', 'M', 'R', '6', 0,
+ /* 7400 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '_', 'M', 'M', 'R', '6', 0,
+ /* 7426 */ 'L', 'D', 'C', '2', '_', 'R', '6', 0,
+ /* 7434 */ 'S', 'D', 'C', '2', '_', 'R', '6', 0,
+ /* 7442 */ 'L', 'W', 'C', '2', '_', 'R', '6', 0,
+ /* 7450 */ 'S', 'W', 'C', '2', '_', 'R', '6', 0,
+ /* 7458 */ 'J', 'R', '_', 'H', 'B', '6', '4', '_', 'R', '6', 0,
+ /* 7469 */ 'S', 'C', '6', '4', '_', 'R', '6', 0,
+ /* 7477 */ 'L', 'L', '6', '4', '_', 'R', '6', 0,
+ /* 7485 */ 'D', 'L', 'S', 'A', '_', 'R', '6', 0,
+ /* 7493 */ 'J', 'R', '_', 'H', 'B', '_', 'R', '6', 0,
+ /* 7502 */ 'S', 'C', '_', 'R', '6', 0,
+ /* 7508 */ 'S', 'C', 'D', '_', 'R', '6', 0,
+ /* 7515 */ 'L', 'L', 'D', '_', 'R', '6', 0,
+ /* 7522 */ 'C', 'A', 'C', 'H', 'E', '_', 'R', '6', 0,
+ /* 7531 */ 'P', 'R', 'E', 'F', '_', 'R', '6', 0,
+ /* 7539 */ 'L', 'L', '_', 'R', '6', 0,
+ /* 7545 */ 'D', 'M', 'U', 'L', '_', 'R', '6', 0,
+ /* 7553 */ 'D', 'C', 'L', 'O', '_', 'R', '6', 0,
+ /* 7561 */ 'S', 'D', 'B', 'B', 'P', '_', 'R', '6', 0,
+ /* 7570 */ 'D', 'C', 'L', 'Z', '_', 'R', '6', 0,
+ /* 7578 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', 'R', '6', 0,
+ /* 7606 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', 'R', '6', 0,
+ /* 7629 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '1', '2', '8', 0,
+ /* 7641 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '1', '2', '8', 0,
+ /* 7654 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', 0,
+ /* 7673 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', 0,
+ /* 7692 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', 0,
+ /* 7712 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', 0,
+ /* 7731 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0,
+ /* 7746 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0,
+ /* 7765 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0,
+ /* 7784 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0,
+ /* 7802 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', 0,
+ /* 7817 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', 0,
+ /* 7833 */ 'G', '_', 'F', 'M', 'A', 0,
+ /* 7839 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', 0,
+ /* 7854 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', 0,
+ /* 7870 */ 'D', 'S', 'R', 'A', 0,
+ /* 7875 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 7902 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 7929 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 7957 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 7984 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8007 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8034 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8061 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8087 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8114 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8141 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8169 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8196 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8219 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8246 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8273 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8299 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8326 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8353 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8381 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8408 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8431 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8458 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8485 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8511 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8537 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8563 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8590 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8616 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8638 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8664 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8690 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0,
+ /* 8715 */ 'R', 'e', 't', 'R', 'A', 0,
+ /* 8721 */ 'D', 'L', 'S', 'A', 0,
+ /* 8726 */ 'C', 'F', 'C', 'M', 'S', 'A', 0,
+ /* 8733 */ 'C', 'T', 'C', 'M', 'S', 'A', 0,
+ /* 8740 */ 'C', 'R', 'C', '3', '2', 'B', 0,
+ /* 8747 */ 'C', 'R', 'C', '3', '2', 'C', 'B', 0,
+ /* 8755 */ 'S', 'E', 'B', 0,
+ /* 8759 */ 'E', 'H', 'B', 0,
+ /* 8763 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', 0,
+ /* 8777 */ 'J', 'R', '_', 'H', 'B', 0,
+ /* 8783 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', 0,
+ /* 8791 */ 'L', 'B', 0,
+ /* 8794 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', 0,
+ /* 8802 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0,
+ /* 8815 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0,
+ /* 8827 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0,
+ /* 8844 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', 0,
+ /* 8853 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', 0,
+ /* 8862 */ 'P', 's', 'e', 'u', 'd', 'o', 'P', 'I', 'C', 'K', '_', 'Q', 'B', 0,
+ /* 8876 */ 'S', 'H', 'L', 'L', '_', 'Q', 'B', 0,
+ /* 8884 */ 'R', 'E', 'P', 'L', '_', 'Q', 'B', 0,
+ /* 8892 */ 'S', 'H', 'R', 'L', '_', 'Q', 'B', 0,
+ /* 8900 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0,
+ /* 8913 */ 'C', 'M', 'P', 'G', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0,
+ /* 8925 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0,
+ /* 8942 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', 0,
+ /* 8952 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', 0,
+ /* 8963 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', 0,
+ /* 8974 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', 0,
+ /* 8985 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', 0,
+ /* 8995 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'Q', 'B', 0,
+ /* 9005 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'Q', 'B', 0,
+ /* 9015 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0,
+ /* 9028 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0,
+ /* 9040 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0,
+ /* 9057 */ 'S', 'U', 'B', 'U', '_', 'Q', 'B', 0,
+ /* 9065 */ 'A', 'D', 'D', 'U', '_', 'Q', 'B', 0,
+ /* 9073 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', 0,
+ /* 9082 */ 'S', 'H', 'L', 'L', 'V', '_', 'Q', 'B', 0,
+ /* 9091 */ 'R', 'E', 'P', 'L', 'V', '_', 'Q', 'B', 0,
+ /* 9100 */ 'S', 'H', 'R', 'L', 'V', '_', 'Q', 'B', 0,
+ /* 9109 */ 'R', 'A', 'D', 'D', 'U', '_', 'W', '_', 'Q', 'B', 0,
+ /* 9120 */ 'S', 'B', 0,
+ /* 9123 */ 'M', 'O', 'D', 'S', 'U', 'B', 0,
+ /* 9130 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
+ /* 9137 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', 0,
+ /* 9148 */ 'G', '_', 'S', 'U', 'B', 0,
+ /* 9154 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
+ /* 9170 */ 'S', 'R', 'A', '_', 'B', 0,
+ /* 9176 */ 'A', 'D', 'D', '_', 'A', '_', 'B', 0,
+ /* 9184 */ 'M', 'I', 'N', '_', 'A', '_', 'B', 0,
+ /* 9192 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'B', 0,
+ /* 9201 */ 'M', 'A', 'X', '_', 'A', '_', 'B', 0,
+ /* 9209 */ 'N', 'L', 'O', 'C', '_', 'B', 0,
+ /* 9216 */ 'N', 'L', 'Z', 'C', '_', 'B', 0,
+ /* 9223 */ 'S', 'L', 'D', '_', 'B', 0,
+ /* 9229 */ 'P', 'C', 'K', 'O', 'D', '_', 'B', 0,
+ /* 9237 */ 'I', 'L', 'V', 'O', 'D', '_', 'B', 0,
+ /* 9245 */ 'I', 'N', 'S', 'V', 'E', '_', 'B', 0,
+ /* 9253 */ 'V', 'S', 'H', 'F', '_', 'B', 0,
+ /* 9260 */ 'B', 'N', 'E', 'G', '_', 'B', 0,
+ /* 9267 */ 'S', 'R', 'A', 'I', '_', 'B', 0,
+ /* 9274 */ 'S', 'L', 'D', 'I', '_', 'B', 0,
+ /* 9281 */ 'A', 'N', 'D', 'I', '_', 'B', 0,
+ /* 9288 */ 'B', 'N', 'E', 'G', 'I', '_', 'B', 0,
+ /* 9296 */ 'B', 'S', 'E', 'L', 'I', '_', 'B', 0,
+ /* 9304 */ 'S', 'L', 'L', 'I', '_', 'B', 0,
+ /* 9311 */ 'S', 'R', 'L', 'I', '_', 'B', 0,
+ /* 9318 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'B', 0,
+ /* 9327 */ 'C', 'E', 'Q', 'I', '_', 'B', 0,
+ /* 9334 */ 'S', 'R', 'A', 'R', 'I', '_', 'B', 0,
+ /* 9342 */ 'B', 'C', 'L', 'R', 'I', '_', 'B', 0,
+ /* 9350 */ 'S', 'R', 'L', 'R', 'I', '_', 'B', 0,
+ /* 9358 */ 'N', 'O', 'R', 'I', '_', 'B', 0,
+ /* 9365 */ 'X', 'O', 'R', 'I', '_', 'B', 0,
+ /* 9372 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'B', 0,
+ /* 9381 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'B', 0,
+ /* 9390 */ 'B', 'S', 'E', 'T', 'I', '_', 'B', 0,
+ /* 9398 */ 'S', 'U', 'B', 'V', 'I', '_', 'B', 0,
+ /* 9406 */ 'A', 'D', 'D', 'V', 'I', '_', 'B', 0,
+ /* 9414 */ 'B', 'M', 'Z', 'I', '_', 'B', 0,
+ /* 9421 */ 'B', 'M', 'N', 'Z', 'I', '_', 'B', 0,
+ /* 9429 */ 'F', 'I', 'L', 'L', '_', 'B', 0,
+ /* 9436 */ 'S', 'L', 'L', '_', 'B', 0,
+ /* 9442 */ 'S', 'R', 'L', '_', 'B', 0,
+ /* 9448 */ 'B', 'I', 'N', 'S', 'L', '_', 'B', 0,
+ /* 9456 */ 'I', 'L', 'V', 'L', '_', 'B', 0,
+ /* 9463 */ 'C', 'E', 'Q', '_', 'B', 0,
+ /* 9469 */ 'S', 'R', 'A', 'R', '_', 'B', 0,
+ /* 9476 */ 'B', 'C', 'L', 'R', '_', 'B', 0,
+ /* 9483 */ 'S', 'R', 'L', 'R', '_', 'B', 0,
+ /* 9490 */ 'B', 'I', 'N', 'S', 'R', '_', 'B', 0,
+ /* 9498 */ 'I', 'L', 'V', 'R', '_', 'B', 0,
+ /* 9505 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'B', 0,
+ /* 9514 */ 'M', 'O', 'D', '_', 'S', '_', 'B', 0,
+ /* 9522 */ 'C', 'L', 'E', '_', 'S', '_', 'B', 0,
+ /* 9530 */ 'A', 'V', 'E', '_', 'S', '_', 'B', 0,
+ /* 9538 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'B', 0,
+ /* 9547 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'B', 0,
+ /* 9556 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'B', 0,
+ /* 9565 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'B', 0,
+ /* 9574 */ 'M', 'I', 'N', '_', 'S', '_', 'B', 0,
+ /* 9582 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'B', 0,
+ /* 9591 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'B', 0,
+ /* 9600 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'B', 0,
+ /* 9609 */ 'S', 'A', 'T', '_', 'S', '_', 'B', 0,
+ /* 9617 */ 'C', 'L', 'T', '_', 'S', '_', 'B', 0,
+ /* 9625 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'B', 0,
+ /* 9636 */ 'D', 'I', 'V', '_', 'S', '_', 'B', 0,
+ /* 9644 */ 'M', 'A', 'X', '_', 'S', '_', 'B', 0,
+ /* 9652 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'B', 0,
+ /* 9661 */ 'S', 'P', 'L', 'A', 'T', '_', 'B', 0,
+ /* 9669 */ 'B', 'S', 'E', 'T', '_', 'B', 0,
+ /* 9676 */ 'P', 'C', 'N', 'T', '_', 'B', 0,
+ /* 9683 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', 0,
+ /* 9692 */ 'S', 'T', '_', 'B', 0,
+ /* 9697 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'B', 0,
+ /* 9706 */ 'M', 'O', 'D', '_', 'U', '_', 'B', 0,
+ /* 9714 */ 'C', 'L', 'E', '_', 'U', '_', 'B', 0,
+ /* 9722 */ 'A', 'V', 'E', '_', 'U', '_', 'B', 0,
+ /* 9730 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'B', 0,
+ /* 9739 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'B', 0,
+ /* 9748 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'B', 0,
+ /* 9757 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'B', 0,
+ /* 9766 */ 'M', 'I', 'N', '_', 'U', '_', 'B', 0,
+ /* 9774 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'B', 0,
+ /* 9783 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'B', 0,
+ /* 9792 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'B', 0,
+ /* 9801 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'B', 0,
+ /* 9812 */ 'S', 'A', 'T', '_', 'U', '_', 'B', 0,
+ /* 9820 */ 'C', 'L', 'T', '_', 'U', '_', 'B', 0,
+ /* 9828 */ 'D', 'I', 'V', '_', 'U', '_', 'B', 0,
+ /* 9836 */ 'M', 'A', 'X', '_', 'U', '_', 'B', 0,
+ /* 9844 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'B', 0,
+ /* 9853 */ 'M', 'S', 'U', 'B', 'V', '_', 'B', 0,
+ /* 9861 */ 'M', 'A', 'D', 'D', 'V', '_', 'B', 0,
+ /* 9869 */ 'P', 'C', 'K', 'E', 'V', '_', 'B', 0,
+ /* 9877 */ 'I', 'L', 'V', 'E', 'V', '_', 'B', 0,
+ /* 9885 */ 'M', 'U', 'L', 'V', '_', 'B', 0,
+ /* 9892 */ 'B', 'Z', '_', 'B', 0,
+ /* 9897 */ 'B', 'N', 'Z', '_', 'B', 0,
+ /* 9903 */ 'B', 'C', 0,
+ /* 9906 */ 'B', 'G', 'E', 'C', 0,
+ /* 9911 */ 'B', 'N', 'E', 'C', 0,
+ /* 9916 */ 'J', 'I', 'C', 0,
+ /* 9920 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
+ /* 9932 */ 'B', 'A', 'L', 'C', 0,
+ /* 9937 */ 'J', 'I', 'A', 'L', 'C', 0,
+ /* 9943 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'C', 0,
+ /* 9951 */ 'B', 'L', 'E', 'Z', 'A', 'L', 'C', 0,
+ /* 9959 */ 'B', 'N', 'E', 'Z', 'A', 'L', 'C', 0,
+ /* 9967 */ 'B', 'E', 'Q', 'Z', 'A', 'L', 'C', 0,
+ /* 9975 */ 'B', 'G', 'T', 'Z', 'A', 'L', 'C', 0,
+ /* 9983 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'C', 0,
+ /* 9991 */ 'E', 'R', 'E', 'T', 'N', 'C', 0,
+ /* 9998 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
+ /* 10008 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
+ /* 10016 */ 'S', 'Y', 'N', 'C', 0,
+ /* 10021 */ 'L', 'D', 'P', 'C', 0,
+ /* 10026 */ 'A', 'U', 'I', 'P', 'C', 0,
+ /* 10032 */ 'A', 'L', 'U', 'I', 'P', 'C', 0,
+ /* 10039 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', 0,
+ /* 10047 */ 'L', 'W', 'U', 'P', 'C', 0,
+ /* 10053 */ 'L', 'W', 'P', 'C', 0,
+ /* 10058 */ 'B', 'E', 'Q', 'C', 0,
+ /* 10063 */ 'A', 'D', 'D', 'S', 'C', 0,
+ /* 10069 */ 'B', 'L', 'T', 'C', 0,
+ /* 10074 */ 'B', 'G', 'E', 'U', 'C', 0,
+ /* 10080 */ 'B', 'L', 'T', 'U', 'C', 0,
+ /* 10086 */ 'B', 'N', 'V', 'C', 0,
+ /* 10091 */ 'B', 'O', 'V', 'C', 0,
+ /* 10096 */ 'A', 'D', 'D', 'W', 'C', 0,
+ /* 10102 */ 'B', 'G', 'E', 'Z', 'C', 0,
+ /* 10108 */ 'B', 'L', 'E', 'Z', 'C', 0,
+ /* 10114 */ 'B', 'N', 'E', 'Z', 'C', 0,
+ /* 10120 */ 'B', 'E', 'Q', 'Z', 'C', 0,
+ /* 10126 */ 'B', 'G', 'T', 'Z', 'C', 0,
+ /* 10132 */ 'B', 'L', 'T', 'Z', 'C', 0,
+ /* 10138 */ 'C', 'R', 'C', '3', '2', 'D', 0,
+ /* 10145 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
+ /* 10156 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
+ /* 10167 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
+ /* 10174 */ 'C', 'R', 'C', '3', '2', 'C', 'D', 0,
+ /* 10182 */ 'S', 'C', 'D', 0,
+ /* 10186 */ 'D', 'A', 'D', 'D', 0,
+ /* 10191 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
+ /* 10198 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', 0,
+ /* 10209 */ 'G', '_', 'A', 'D', 'D', 0,
+ /* 10215 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
+ /* 10231 */ 'D', 'S', 'H', 'D', 0,
+ /* 10236 */ 'Y', 'I', 'E', 'L', 'D', 0,
+ /* 10242 */ 'L', 'L', 'D', 0,
+ /* 10246 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
+ /* 10263 */ 'G', '_', 'A', 'N', 'D', 0,
+ /* 10269 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
+ /* 10285 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', 0,
+ /* 10293 */ 'A', 'P', 'P', 'E', 'N', 'D', 0,
+ /* 10300 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+ /* 10313 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
+ /* 10322 */ 'D', 'M', 'O', 'D', 0,
+ /* 10327 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
+ /* 10344 */ 'S', 'D', 0,
+ /* 10347 */ 'F', 'L', 'O', 'G', '2', '_', 'D', 0,
+ /* 10355 */ 'F', 'E', 'X', 'P', '2', '_', 'D', 0,
+ /* 10363 */ 'M', 'I', 'N', 'A', '_', 'D', 0,
+ /* 10370 */ 'S', 'R', 'A', '_', 'D', 0,
+ /* 10376 */ 'M', 'A', 'X', 'A', '_', 'D', 0,
+ /* 10383 */ 'A', 'D', 'D', '_', 'A', '_', 'D', 0,
+ /* 10391 */ 'F', 'M', 'I', 'N', '_', 'A', '_', 'D', 0,
+ /* 10400 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'D', 0,
+ /* 10409 */ 'F', 'M', 'A', 'X', '_', 'A', '_', 'D', 0,
+ /* 10418 */ 'F', 'S', 'U', 'B', '_', 'D', 0,
+ /* 10425 */ 'F', 'M', 'S', 'U', 'B', '_', 'D', 0,
+ /* 10433 */ 'N', 'L', 'O', 'C', '_', 'D', 0,
+ /* 10440 */ 'N', 'L', 'Z', 'C', '_', 'D', 0,
+ /* 10447 */ 'F', 'A', 'D', 'D', '_', 'D', 0,
+ /* 10454 */ 'F', 'M', 'A', 'D', 'D', '_', 'D', 0,
+ /* 10462 */ 'S', 'L', 'D', '_', 'D', 0,
+ /* 10468 */ 'P', 'C', 'K', 'O', 'D', '_', 'D', 0,
+ /* 10476 */ 'I', 'L', 'V', 'O', 'D', '_', 'D', 0,
+ /* 10484 */ 'F', 'C', 'L', 'E', '_', 'D', 0,
+ /* 10491 */ 'F', 'S', 'L', 'E', '_', 'D', 0,
+ /* 10498 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'D', 0,
+ /* 10508 */ 'F', 'C', 'U', 'L', 'E', '_', 'D', 0,
+ /* 10516 */ 'F', 'S', 'U', 'L', 'E', '_', 'D', 0,
+ /* 10524 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'D', 0,
+ /* 10535 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'D', 0,
+ /* 10545 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'D', 0,
+ /* 10554 */ 'F', 'C', 'N', 'E', '_', 'D', 0,
+ /* 10561 */ 'F', 'S', 'N', 'E', '_', 'D', 0,
+ /* 10568 */ 'F', 'C', 'U', 'N', 'E', '_', 'D', 0,
+ /* 10576 */ 'F', 'S', 'U', 'N', 'E', '_', 'D', 0,
+ /* 10584 */ 'I', 'N', 'S', 'V', 'E', '_', 'D', 0,
+ /* 10592 */ 'F', 'C', 'A', 'F', '_', 'D', 0,
+ /* 10599 */ 'F', 'S', 'A', 'F', '_', 'D', 0,
+ /* 10606 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'D', 0,
+ /* 10616 */ 'M', 'S', 'U', 'B', 'F', '_', 'D', 0,
+ /* 10624 */ 'M', 'A', 'D', 'D', 'F', '_', 'D', 0,
+ /* 10632 */ 'V', 'S', 'H', 'F', '_', 'D', 0,
+ /* 10639 */ 'C', 'M', 'P', '_', 'F', '_', 'D', 0,
+ /* 10647 */ 'B', 'N', 'E', 'G', '_', 'D', 0,
+ /* 10654 */ 'S', 'R', 'A', 'I', '_', 'D', 0,
+ /* 10661 */ 'S', 'L', 'D', 'I', '_', 'D', 0,
+ /* 10668 */ 'B', 'N', 'E', 'G', 'I', '_', 'D', 0,
+ /* 10676 */ 'S', 'L', 'L', 'I', '_', 'D', 0,
+ /* 10683 */ 'S', 'R', 'L', 'I', '_', 'D', 0,
+ /* 10690 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'D', 0,
+ /* 10699 */ 'C', 'E', 'Q', 'I', '_', 'D', 0,
+ /* 10706 */ 'S', 'R', 'A', 'R', 'I', '_', 'D', 0,
+ /* 10714 */ 'B', 'C', 'L', 'R', 'I', '_', 'D', 0,
+ /* 10722 */ 'S', 'R', 'L', 'R', 'I', '_', 'D', 0,
+ /* 10730 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'D', 0,
+ /* 10739 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'D', 0,
+ /* 10748 */ 'B', 'S', 'E', 'T', 'I', '_', 'D', 0,
+ /* 10756 */ 'S', 'U', 'B', 'V', 'I', '_', 'D', 0,
+ /* 10764 */ 'A', 'D', 'D', 'V', 'I', '_', 'D', 0,
+ /* 10772 */ 'S', 'E', 'L', '_', 'D', 0,
+ /* 10778 */ 'F', 'I', 'L', 'L', '_', 'D', 0,
+ /* 10785 */ 'S', 'L', 'L', '_', 'D', 0,
+ /* 10791 */ 'F', 'E', 'X', 'U', 'P', 'L', '_', 'D', 0,
+ /* 10800 */ 'F', 'F', 'Q', 'L', '_', 'D', 0,
+ /* 10807 */ 'S', 'R', 'L', '_', 'D', 0,
+ /* 10813 */ 'B', 'I', 'N', 'S', 'L', '_', 'D', 0,
+ /* 10821 */ 'F', 'M', 'U', 'L', '_', 'D', 0,
+ /* 10828 */ 'I', 'L', 'V', 'L', '_', 'D', 0,
+ /* 10835 */ 'F', 'M', 'I', 'N', '_', 'D', 0,
+ /* 10842 */ 'F', 'C', 'U', 'N', '_', 'D', 0,
+ /* 10849 */ 'F', 'S', 'U', 'N', '_', 'D', 0,
+ /* 10856 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'D', 0,
+ /* 10866 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'D', 0,
+ /* 10875 */ 'F', 'R', 'C', 'P', '_', 'D', 0,
+ /* 10882 */ 'F', 'C', 'E', 'Q', '_', 'D', 0,
+ /* 10889 */ 'F', 'S', 'E', 'Q', '_', 'D', 0,
+ /* 10896 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'D', 0,
+ /* 10906 */ 'F', 'C', 'U', 'E', 'Q', '_', 'D', 0,
+ /* 10914 */ 'F', 'S', 'U', 'E', 'Q', '_', 'D', 0,
+ /* 10922 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'D', 0,
+ /* 10933 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'D', 0,
+ /* 10943 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'D', 0,
+ /* 10952 */ 'S', 'R', 'A', 'R', '_', 'D', 0,
+ /* 10959 */ 'B', 'C', 'L', 'R', '_', 'D', 0,
+ /* 10966 */ 'S', 'R', 'L', 'R', '_', 'D', 0,
+ /* 10973 */ 'F', 'C', 'O', 'R', '_', 'D', 0,
+ /* 10980 */ 'F', 'S', 'O', 'R', '_', 'D', 0,
+ /* 10987 */ 'F', 'E', 'X', 'U', 'P', 'R', '_', 'D', 0,
+ /* 10996 */ 'F', 'F', 'Q', 'R', '_', 'D', 0,
+ /* 11003 */ 'B', 'I', 'N', 'S', 'R', '_', 'D', 0,
+ /* 11011 */ 'I', 'L', 'V', 'R', '_', 'D', 0,
+ /* 11018 */ 'F', 'A', 'B', 'S', '_', 'D', 0,
+ /* 11025 */ 'F', 'C', 'L', 'A', 'S', 'S', '_', 'D', 0,
+ /* 11034 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'D', 0,
+ /* 11043 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'D', 0,
+ /* 11052 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'D', 0,
+ /* 11062 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'D', 0,
+ /* 11073 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'D', 0,
+ /* 11082 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'D', 0,
+ /* 11092 */ 'M', 'O', 'D', '_', 'S', '_', 'D', 0,
+ /* 11100 */ 'C', 'L', 'E', '_', 'S', '_', 'D', 0,
+ /* 11108 */ 'A', 'V', 'E', '_', 'S', '_', 'D', 0,
+ /* 11116 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'D', 0,
+ /* 11125 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'D', 0,
+ /* 11134 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'D', 0,
+ /* 11143 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'D', 0,
+ /* 11152 */ 'M', 'I', 'N', '_', 'S', '_', 'D', 0,
+ /* 11160 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'D', 0,
+ /* 11169 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'D', 0,
+ /* 11178 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'D', 0,
+ /* 11187 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'D', 0,
+ /* 11196 */ 'S', 'A', 'T', '_', 'S', '_', 'D', 0,
+ /* 11204 */ 'C', 'L', 'T', '_', 'S', '_', 'D', 0,
+ /* 11212 */ 'F', 'F', 'I', 'N', 'T', '_', 'S', '_', 'D', 0,
+ /* 11222 */ 'F', 'T', 'I', 'N', 'T', '_', 'S', '_', 'D', 0,
+ /* 11232 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'D', 0,
+ /* 11243 */ 'D', 'I', 'V', '_', 'S', '_', 'D', 0,
+ /* 11251 */ 'M', 'A', 'X', '_', 'S', '_', 'D', 0,
+ /* 11259 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'D', 0,
+ /* 11268 */ 'S', 'P', 'L', 'A', 'T', '_', 'D', 0,
+ /* 11276 */ 'B', 'S', 'E', 'T', '_', 'D', 0,
+ /* 11283 */ 'F', 'C', 'L', 'T', '_', 'D', 0,
+ /* 11290 */ 'F', 'S', 'L', 'T', '_', 'D', 0,
+ /* 11297 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'D', 0,
+ /* 11307 */ 'F', 'C', 'U', 'L', 'T', '_', 'D', 0,
+ /* 11315 */ 'F', 'S', 'U', 'L', 'T', '_', 'D', 0,
+ /* 11323 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'D', 0,
+ /* 11334 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'D', 0,
+ /* 11344 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'D', 0,
+ /* 11353 */ 'P', 'C', 'N', 'T', '_', 'D', 0,
+ /* 11360 */ 'F', 'R', 'I', 'N', 'T', '_', 'D', 0,
+ /* 11368 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', 0,
+ /* 11377 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', 0,
+ /* 11385 */ 'F', 'R', 'S', 'Q', 'R', 'T', '_', 'D', 0,
+ /* 11394 */ 'S', 'T', '_', 'D', 0,
+ /* 11399 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'D', 0,
+ /* 11408 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'D', 0,
+ /* 11417 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'D', 0,
+ /* 11427 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'D', 0,
+ /* 11438 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'D', 0,
+ /* 11447 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'D', 0,
+ /* 11457 */ 'M', 'O', 'D', '_', 'U', '_', 'D', 0,
+ /* 11465 */ 'C', 'L', 'E', '_', 'U', '_', 'D', 0,
+ /* 11473 */ 'A', 'V', 'E', '_', 'U', '_', 'D', 0,
+ /* 11481 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'D', 0,
+ /* 11490 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'D', 0,
+ /* 11499 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'D', 0,
+ /* 11508 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'D', 0,
+ /* 11517 */ 'M', 'I', 'N', '_', 'U', '_', 'D', 0,
+ /* 11525 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'D', 0,
+ /* 11534 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'D', 0,
+ /* 11543 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'D', 0,
+ /* 11552 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'D', 0,
+ /* 11561 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'D', 0,
+ /* 11572 */ 'S', 'A', 'T', '_', 'U', '_', 'D', 0,
+ /* 11580 */ 'C', 'L', 'T', '_', 'U', '_', 'D', 0,
+ /* 11588 */ 'F', 'F', 'I', 'N', 'T', '_', 'U', '_', 'D', 0,
+ /* 11598 */ 'F', 'T', 'I', 'N', 'T', '_', 'U', '_', 'D', 0,
+ /* 11608 */ 'D', 'I', 'V', '_', 'U', '_', 'D', 0,
+ /* 11616 */ 'M', 'A', 'X', '_', 'U', '_', 'D', 0,
+ /* 11624 */ 'M', 'S', 'U', 'B', 'V', '_', 'D', 0,
+ /* 11632 */ 'M', 'A', 'D', 'D', 'V', '_', 'D', 0,
+ /* 11640 */ 'P', 'C', 'K', 'E', 'V', '_', 'D', 0,
+ /* 11648 */ 'I', 'L', 'V', 'E', 'V', '_', 'D', 0,
+ /* 11656 */ 'F', 'D', 'I', 'V', '_', 'D', 0,
+ /* 11663 */ 'M', 'U', 'L', 'V', '_', 'D', 0,
+ /* 11670 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', 0,
+ /* 11686 */ 'F', 'M', 'A', 'X', '_', 'D', 0,
+ /* 11693 */ 'B', 'Z', '_', 'D', 0,
+ /* 11698 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'D', 0,
+ /* 11707 */ 'B', 'N', 'Z', '_', 'D', 0,
+ /* 11713 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'D', 0,
+ /* 11722 */ 'L', 'B', 'E', 0,
+ /* 11726 */ 'S', 'B', 'E', 0,
+ /* 11730 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
+ /* 11738 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
+ /* 11751 */ 'S', 'C', 'E', 0,
+ /* 11755 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
+ /* 11763 */ 'C', 'A', 'C', 'H', 'E', 'E', 0,
+ /* 11770 */ 'P', 'R', 'E', 'F', 'E', 0,
+ /* 11776 */ 'B', 'G', 'E', 0,
+ /* 11780 */ 'T', 'G', 'E', 0,
+ /* 11784 */ 'C', 'A', 'C', 'H', 'E', 0,
+ /* 11790 */ 'L', 'H', 'E', 0,
+ /* 11794 */ 'S', 'H', 'E', 0,
+ /* 11798 */ 'B', 'L', 'E', 0,
+ /* 11802 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+ /* 11809 */ 'L', 'L', 'E', 0,
+ /* 11813 */ 'L', 'W', 'L', 'E', 0,
+ /* 11818 */ 'S', 'W', 'L', 'E', 0,
+ /* 11823 */ 'B', 'N', 'E', 0,
+ /* 11827 */ 'S', 'N', 'E', 0,
+ /* 11831 */ 'T', 'N', 'E', 0,
+ /* 11835 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
+ /* 11848 */ 'D', 'V', 'P', 'E', 0,
+ /* 11853 */ 'E', 'V', 'P', 'E', 0,
+ /* 11858 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
+ /* 11866 */ 'L', 'W', 'R', 'E', 0,
+ /* 11871 */ 'S', 'W', 'R', 'E', 0,
+ /* 11876 */ 'P', 'A', 'U', 'S', 'E', 0,
+ /* 11882 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 11892 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 11907 */ 'L', 'W', 'E', 0,
+ /* 11911 */ 'S', 'W', 'E', 0,
+ /* 11915 */ 'L', 'B', 'u', 'E', 0,
+ /* 11920 */ 'L', 'H', 'u', 'E', 0,
+ /* 11925 */ 'B', 'C', '1', 'F', 0,
+ /* 11930 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
+ /* 11945 */ 'P', 'R', 'E', 'F', 0,
+ /* 11950 */ 'T', 'L', 'B', 'I', 'N', 'V', 'F', 0,
+ /* 11958 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 'F', 0,
+ /* 11967 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
+ /* 11974 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'H', 'B', '6', '4', 'R', '6', 'R', 'E', 'G', 0,
+ /* 11992 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '6', '4', 'R', '6', 'R', 'E', 'G', 0,
+ /* 12008 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'H', 'B', 'R', '6', 'R', 'E', 'G', 0,
+ /* 12024 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', '6', 'R', 'E', 'G', 0,
+ /* 12038 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
+ /* 12053 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
+ /* 12067 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 0,
+ /* 12079 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
+ /* 12093 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
+ /* 12110 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
+ /* 12127 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
+ /* 12134 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
+ /* 12142 */ 'C', 'R', 'C', '3', '2', 'H', 0,
+ /* 12149 */ 'D', 'S', 'B', 'H', 0,
+ /* 12154 */ 'W', 'S', 'B', 'H', 0,
+ /* 12159 */ 'C', 'R', 'C', '3', '2', 'C', 'H', 0,
+ /* 12167 */ 'S', 'E', 'H', 0,
+ /* 12171 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
+ /* 12179 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
+ /* 12187 */ 'S', 'H', 'R', 'A', '_', 'P', 'H', 0,
+ /* 12195 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'Q', 'B', '_', 'P', 'H', 0,
+ /* 12208 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', 0,
+ /* 12220 */ 'P', 'R', 'E', 'C', 'R', 'Q', 'U', '_', 'S', '_', 'Q', 'B', '_', 'P', 'H', 0,
+ /* 12236 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'L', 'E', '_', 'P', 'H', 0,
+ /* 12252 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', 0,
+ /* 12261 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', 0,
+ /* 12270 */ 'P', 's', 'e', 'u', 'd', 'o', 'P', 'I', 'C', 'K', '_', 'P', 'H', 0,
+ /* 12284 */ 'S', 'H', 'L', 'L', '_', 'P', 'H', 0,
+ /* 12292 */ 'R', 'E', 'P', 'L', '_', 'P', 'H', 0,
+ /* 12300 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', 0,
+ /* 12308 */ 'P', 'A', 'C', 'K', 'R', 'L', '_', 'P', 'H', 0,
+ /* 12318 */ 'M', 'U', 'L', '_', 'P', 'H', 0,
+ /* 12325 */ 'S', 'U', 'B', 'Q', '_', 'P', 'H', 0,
+ /* 12333 */ 'A', 'D', 'D', 'Q', '_', 'P', 'H', 0,
+ /* 12341 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'E', 'Q', '_', 'P', 'H', 0,
+ /* 12357 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'P', 'H', 0,
+ /* 12367 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', 0,
+ /* 12378 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', 0,
+ /* 12389 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'P', 'H', 0,
+ /* 12400 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'P', 'H', 0,
+ /* 12411 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'P', 'H', 0,
+ /* 12421 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', 0,
+ /* 12430 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'P', 'H', 0,
+ /* 12440 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'P', 'H', 0,
+ /* 12450 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', 0,
+ /* 12460 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'P', 'H', 0,
+ /* 12470 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', 0,
+ /* 12480 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', 0,
+ /* 12490 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'P', 'H', 0,
+ /* 12501 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'L', 'T', '_', 'P', 'H', 0,
+ /* 12517 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', 0,
+ /* 12525 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', 0,
+ /* 12533 */ 'S', 'H', 'R', 'A', 'V', '_', 'P', 'H', 0,
+ /* 12542 */ 'S', 'H', 'L', 'L', 'V', '_', 'P', 'H', 0,
+ /* 12551 */ 'R', 'E', 'P', 'L', 'V', '_', 'P', 'H', 0,
+ /* 12560 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', 0,
+ /* 12569 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', 0,
+ /* 12578 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', 0,
+ /* 12589 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 0,
+ /* 12603 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 0,
+ /* 12617 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', 0,
+ /* 12626 */ 'D', 'P', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0,
+ /* 12638 */ 'M', 'U', 'L', 'S', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0,
+ /* 12652 */ 'D', 'P', 'S', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0,
+ /* 12664 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', 0,
+ /* 12677 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', 0,
+ /* 12690 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', 0,
+ /* 12700 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', 0,
+ /* 12710 */ 'S', 'H', 0,
+ /* 12713 */ 'D', 'M', 'U', 'H', 0,
+ /* 12718 */ 'S', 'R', 'A', '_', 'H', 0,
+ /* 12724 */ 'A', 'D', 'D', '_', 'A', '_', 'H', 0,
+ /* 12732 */ 'M', 'I', 'N', '_', 'A', '_', 'H', 0,
+ /* 12740 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'H', 0,
+ /* 12749 */ 'M', 'A', 'X', '_', 'A', '_', 'H', 0,
+ /* 12757 */ 'N', 'L', 'O', 'C', '_', 'H', 0,
+ /* 12764 */ 'N', 'L', 'Z', 'C', '_', 'H', 0,
+ /* 12771 */ 'S', 'L', 'D', '_', 'H', 0,
+ /* 12777 */ 'P', 'C', 'K', 'O', 'D', '_', 'H', 0,
+ /* 12785 */ 'I', 'L', 'V', 'O', 'D', '_', 'H', 0,
+ /* 12793 */ 'I', 'N', 'S', 'V', 'E', '_', 'H', 0,
+ /* 12801 */ 'V', 'S', 'H', 'F', '_', 'H', 0,
+ /* 12808 */ 'B', 'N', 'E', 'G', '_', 'H', 0,
+ /* 12815 */ 'S', 'R', 'A', 'I', '_', 'H', 0,
+ /* 12822 */ 'S', 'L', 'D', 'I', '_', 'H', 0,
+ /* 12829 */ 'B', 'N', 'E', 'G', 'I', '_', 'H', 0,
+ /* 12837 */ 'S', 'L', 'L', 'I', '_', 'H', 0,
+ /* 12844 */ 'S', 'R', 'L', 'I', '_', 'H', 0,
+ /* 12851 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'H', 0,
+ /* 12860 */ 'C', 'E', 'Q', 'I', '_', 'H', 0,
+ /* 12867 */ 'S', 'R', 'A', 'R', 'I', '_', 'H', 0,
+ /* 12875 */ 'B', 'C', 'L', 'R', 'I', '_', 'H', 0,
+ /* 12883 */ 'S', 'R', 'L', 'R', 'I', '_', 'H', 0,
+ /* 12891 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'H', 0,
+ /* 12900 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'H', 0,
+ /* 12909 */ 'B', 'S', 'E', 'T', 'I', '_', 'H', 0,
+ /* 12917 */ 'S', 'U', 'B', 'V', 'I', '_', 'H', 0,
+ /* 12925 */ 'A', 'D', 'D', 'V', 'I', '_', 'H', 0,
+ /* 12933 */ 'F', 'I', 'L', 'L', '_', 'H', 0,
+ /* 12940 */ 'S', 'L', 'L', '_', 'H', 0,
+ /* 12946 */ 'S', 'R', 'L', '_', 'H', 0,
+ /* 12952 */ 'B', 'I', 'N', 'S', 'L', '_', 'H', 0,
+ /* 12960 */ 'I', 'L', 'V', 'L', '_', 'H', 0,
+ /* 12967 */ 'F', 'E', 'X', 'D', 'O', '_', 'H', 0,
+ /* 12975 */ 'C', 'E', 'Q', '_', 'H', 0,
+ /* 12981 */ 'F', 'T', 'Q', '_', 'H', 0,
+ /* 12987 */ 'M', 'S', 'U', 'B', '_', 'Q', '_', 'H', 0,
+ /* 12996 */ 'M', 'A', 'D', 'D', '_', 'Q', '_', 'H', 0,
+ /* 13005 */ 'M', 'U', 'L', '_', 'Q', '_', 'H', 0,
+ /* 13013 */ 'M', 'S', 'U', 'B', 'R', '_', 'Q', '_', 'H', 0,
+ /* 13023 */ 'M', 'A', 'D', 'D', 'R', '_', 'Q', '_', 'H', 0,
+ /* 13033 */ 'M', 'U', 'L', 'R', '_', 'Q', '_', 'H', 0,
+ /* 13042 */ 'S', 'R', 'A', 'R', '_', 'H', 0,
+ /* 13049 */ 'B', 'C', 'L', 'R', '_', 'H', 0,
+ /* 13056 */ 'S', 'R', 'L', 'R', '_', 'H', 0,
+ /* 13063 */ 'B', 'I', 'N', 'S', 'R', '_', 'H', 0,
+ /* 13071 */ 'I', 'L', 'V', 'R', '_', 'H', 0,
+ /* 13078 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'H', 0,
+ /* 13087 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'H', 0,
+ /* 13096 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'H', 0,
+ /* 13106 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'H', 0,
+ /* 13115 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'H', 0,
+ /* 13125 */ 'M', 'O', 'D', '_', 'S', '_', 'H', 0,
+ /* 13133 */ 'C', 'L', 'E', '_', 'S', '_', 'H', 0,
+ /* 13141 */ 'A', 'V', 'E', '_', 'S', '_', 'H', 0,
+ /* 13149 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'H', 0,
+ /* 13158 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'H', 0,
+ /* 13167 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'H', 0,
+ /* 13176 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'H', 0,
+ /* 13185 */ 'M', 'I', 'N', '_', 'S', '_', 'H', 0,
+ /* 13193 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'H', 0,
+ /* 13202 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'H', 0,
+ /* 13211 */ 'E', 'X', 'T', 'R', '_', 'S', '_', 'H', 0,
+ /* 13220 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'H', 0,
+ /* 13229 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'H', 0,
+ /* 13238 */ 'S', 'A', 'T', '_', 'S', '_', 'H', 0,
+ /* 13246 */ 'C', 'L', 'T', '_', 'S', '_', 'H', 0,
+ /* 13254 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'H', 0,
+ /* 13265 */ 'D', 'I', 'V', '_', 'S', '_', 'H', 0,
+ /* 13273 */ 'E', 'X', 'T', 'R', 'V', '_', 'S', '_', 'H', 0,
+ /* 13283 */ 'M', 'A', 'X', '_', 'S', '_', 'H', 0,
+ /* 13291 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'H', 0,
+ /* 13300 */ 'S', 'P', 'L', 'A', 'T', '_', 'H', 0,
+ /* 13308 */ 'B', 'S', 'E', 'T', '_', 'H', 0,
+ /* 13315 */ 'P', 'C', 'N', 'T', '_', 'H', 0,
+ /* 13322 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', 0,
+ /* 13331 */ 'S', 'T', '_', 'H', 0,
+ /* 13336 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'H', 0,
+ /* 13345 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'H', 0,
+ /* 13354 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'H', 0,
+ /* 13364 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'H', 0,
+ /* 13373 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'H', 0,
+ /* 13383 */ 'M', 'O', 'D', '_', 'U', '_', 'H', 0,
+ /* 13391 */ 'C', 'L', 'E', '_', 'U', '_', 'H', 0,
+ /* 13399 */ 'A', 'V', 'E', '_', 'U', '_', 'H', 0,
+ /* 13407 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'H', 0,
+ /* 13416 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'H', 0,
+ /* 13425 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'H', 0,
+ /* 13434 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'H', 0,
+ /* 13443 */ 'M', 'I', 'N', '_', 'U', '_', 'H', 0,
+ /* 13451 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'H', 0,
+ /* 13460 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'H', 0,
+ /* 13469 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'H', 0,
+ /* 13478 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'H', 0,
+ /* 13487 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'H', 0,
+ /* 13498 */ 'S', 'A', 'T', '_', 'U', '_', 'H', 0,
+ /* 13506 */ 'C', 'L', 'T', '_', 'U', '_', 'H', 0,
+ /* 13514 */ 'D', 'I', 'V', '_', 'U', '_', 'H', 0,
+ /* 13522 */ 'M', 'A', 'X', '_', 'U', '_', 'H', 0,
+ /* 13530 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'H', 0,
+ /* 13539 */ 'M', 'S', 'U', 'B', 'V', '_', 'H', 0,
+ /* 13547 */ 'M', 'A', 'D', 'D', 'V', '_', 'H', 0,
+ /* 13555 */ 'P', 'C', 'K', 'E', 'V', '_', 'H', 0,
+ /* 13563 */ 'I', 'L', 'V', 'E', 'V', '_', 'H', 0,
+ /* 13571 */ 'M', 'U', 'L', 'V', '_', 'H', 0,
+ /* 13578 */ 'B', 'Z', '_', 'H', 0,
+ /* 13583 */ 'B', 'N', 'Z', '_', 'H', 0,
+ /* 13589 */ 'S', 'Y', 'N', 'C', 'I', 0,
+ /* 13595 */ 'D', 'I', 0,
+ /* 13598 */ 'T', 'G', 'E', 'I', 0,
+ /* 13603 */ 'T', 'N', 'E', 'I', 0,
+ /* 13608 */ 'D', 'A', 'H', 'I', 0,
+ /* 13613 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', 0,
+ /* 13624 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', 0,
+ /* 13637 */ 'G', '_', 'P', 'H', 'I', 0,
+ /* 13643 */ 'M', 'F', 'T', 'H', 'I', 0,
+ /* 13649 */ 'M', 'T', 'H', 'I', 0,
+ /* 13654 */ 'M', 'T', 'T', 'H', 'I', 0,
+ /* 13660 */ 'T', 'E', 'Q', 'I', 0,
+ /* 13665 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
+ /* 13674 */ 'D', 'A', 'T', 'I', 0,
+ /* 13679 */ 'T', 'L', 'T', 'I', 0,
+ /* 13684 */ 'D', 'A', 'U', 'I', 0,
+ /* 13689 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
+ /* 13698 */ 'G', 'I', 'N', 'V', 'I', 0,
+ /* 13704 */ 'T', 'L', 'B', 'W', 'I', 0,
+ /* 13710 */ 'T', 'L', 'B', 'G', 'W', 'I', 0,
+ /* 13717 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'I', 0,
+ /* 13728 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'I', 0,
+ /* 13739 */ 'M', 'O', 'V', 'F', '_', 'I', 0,
+ /* 13746 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'I', 0,
+ /* 13765 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'I', 0,
+ /* 13774 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'I', 0,
+ /* 13783 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', 0,
+ /* 13798 */ 'M', 'O', 'V', 'T', '_', 'I', 0,
+ /* 13805 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'I', 0,
+ /* 13824 */ 'J', 0,
+ /* 13826 */ 'B', 'R', 'E', 'A', 'K', 0,
+ /* 13832 */ 'F', 'O', 'R', 'K', 0,
+ /* 13837 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
+ /* 13848 */ 'B', 'A', 'L', 0,
+ /* 13852 */ 'J', 'A', 'L', 0,
+ /* 13856 */ 'B', 'G', 'E', 'Z', 'A', 'L', 0,
+ /* 13863 */ 'B', 'L', 'T', 'Z', 'A', 'L', 0,
+ /* 13870 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0,
+ /* 13885 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0,
+ /* 13899 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0,
+ /* 13914 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'L', 0,
+ /* 13925 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'L', 0,
+ /* 13936 */ 'L', 'D', 'L', 0,
+ /* 13940 */ 'S', 'D', 'L', 0,
+ /* 13944 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 13953 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 13963 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 13972 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 13989 */ 'B', 'G', 'E', 'L', 0,
+ /* 13994 */ 'B', 'L', 'E', 'L', 0,
+ /* 13999 */ 'B', 'N', 'E', 'L', 0,
+ /* 14004 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
+ /* 14024 */ 'B', 'C', '1', 'F', 'L', 0,
+ /* 14030 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'L', 0,
+ /* 14043 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'L', 0,
+ /* 14056 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', 0,
+ /* 14068 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', 0,
+ /* 14082 */ 'G', '_', 'S', 'H', 'L', 0,
+ /* 14088 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 0,
+ /* 14097 */ 'H', 'Y', 'P', 'C', 'A', 'L', 'L', 0,
+ /* 14105 */ 'S', 'Y', 'S', 'C', 'A', 'L', 'L', 0,
+ /* 14113 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
+ /* 14133 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
+ /* 14160 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
+ /* 14181 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
+ /* 14193 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'L', 0,
+ /* 14201 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'L', 0,
+ /* 14209 */ 'K', 'I', 'L', 'L', 0,
+ /* 14214 */ 'D', 'S', 'L', 'L', 0,
+ /* 14219 */ 'D', 'R', 'O', 'L', 0,
+ /* 14224 */ 'B', 'E', 'Q', 'L', 0,
+ /* 14229 */ 'D', 'S', 'R', 'L', 0,
+ /* 14234 */ 'B', 'C', '1', 'T', 'L', 0,
+ /* 14240 */ 'B', 'G', 'T', 'L', 0,
+ /* 14245 */ 'B', 'L', 'T', 'L', 0,
+ /* 14250 */ 'B', 'G', 'E', 'U', 'L', 0,
+ /* 14256 */ 'B', 'L', 'E', 'U', 'L', 0,
+ /* 14262 */ 'D', 'M', 'U', 'L', 0,
+ /* 14267 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
+ /* 14274 */ 'G', '_', 'M', 'U', 'L', 0,
+ /* 14280 */ 'B', 'G', 'T', 'U', 'L', 0,
+ /* 14286 */ 'B', 'L', 'T', 'U', 'L', 0,
+ /* 14292 */ 'L', 'W', 'L', 0,
+ /* 14296 */ 'S', 'W', 'L', 0,
+ /* 14300 */ 'B', 'G', 'E', 'Z', 'L', 0,
+ /* 14306 */ 'B', 'L', 'E', 'Z', 'L', 0,
+ /* 14312 */ 'B', 'G', 'T', 'Z', 'L', 0,
+ /* 14318 */ 'B', 'L', 'T', 'Z', 'L', 0,
+ /* 14324 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'L', 0,
+ /* 14340 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'S', '_', 'L', 0,
+ /* 14354 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
+ /* 14361 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
+ /* 14368 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
+ /* 14375 */ 'M', 'F', 'G', 'C', '0', '_', 'M', 'M', 0,
+ /* 14384 */ 'M', 'F', 'H', 'G', 'C', '0', '_', 'M', 'M', 0,
+ /* 14394 */ 'M', 'T', 'H', 'G', 'C', '0', '_', 'M', 'M', 0,
+ /* 14404 */ 'M', 'T', 'G', 'C', '0', '_', 'M', 'M', 0,
+ /* 14413 */ 'L', 'D', 'C', '1', '_', 'M', 'M', 0,
+ /* 14421 */ 'S', 'D', 'C', '1', '_', 'M', 'M', 0,
+ /* 14429 */ 'C', 'F', 'C', '1', '_', 'M', 'M', 0,
+ /* 14437 */ 'M', 'F', 'C', '1', '_', 'M', 'M', 0,
+ /* 14445 */ 'C', 'T', 'C', '1', '_', 'M', 'M', 0,
+ /* 14453 */ 'M', 'T', 'C', '1', '_', 'M', 'M', 0,
+ /* 14461 */ 'L', 'W', 'C', '1', '_', 'M', 'M', 0,
+ /* 14469 */ 'S', 'W', 'C', '1', '_', 'M', 'M', 0,
+ /* 14477 */ 'L', 'U', 'X', 'C', '1', '_', 'M', 'M', 0,
+ /* 14486 */ 'S', 'U', 'X', 'C', '1', '_', 'M', 'M', 0,
+ /* 14495 */ 'L', 'W', 'X', 'C', '1', '_', 'M', 'M', 0,
+ /* 14504 */ 'S', 'W', 'X', 'C', '1', '_', 'M', 'M', 0,
+ /* 14513 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14526 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14539 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14551 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14564 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14576 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14589 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14602 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14616 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14629 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14642 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14654 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14666 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14678 */ 'C', '_', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14689 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14701 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14715 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14729 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14742 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14754 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14766 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14779 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14791 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14804 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14817 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14829 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14841 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14854 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14867 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14880 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14893 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14905 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14918 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14931 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14943 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14955 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14967 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', '_', 'M', 'M', 0,
+ /* 14980 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', '_', 'M', 'M', 0,
+ /* 14992 */ 'L', 'W', 'M', '3', '2', '_', 'M', 'M', 0,
+ /* 15001 */ 'S', 'W', 'M', '3', '2', '_', 'M', 'M', 0,
+ /* 15010 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', '_', 'M', 'M', 0,
+ /* 15022 */ 'C', 'F', 'C', '2', '_', 'M', 'M', 0,
+ /* 15030 */ 'C', 'T', 'C', '2', '_', 'M', 'M', 0,
+ /* 15038 */ 'A', 'D', 'D', 'I', 'U', 'R', '2', '_', 'M', 'M', 0,
+ /* 15049 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15062 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15075 */ 'F', 'S', 'U', 'B', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15087 */ 'F', 'A', 'D', 'D', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15099 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15112 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15126 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15139 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15152 */ 'C', '_', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15164 */ 'C', '_', 'S', 'F', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15176 */ 'C', '_', 'F', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15187 */ 'F', 'N', 'E', 'G', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15199 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15212 */ 'F', 'M', 'U', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15224 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15237 */ 'C', '_', 'U', 'N', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15249 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15262 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15275 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15288 */ 'C', '_', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15300 */ 'F', 'A', 'B', 'S', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15312 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15325 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15338 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15351 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15364 */ 'C', '_', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15376 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15389 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15402 */ 'F', 'D', 'I', 'V', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15414 */ 'F', 'M', 'O', 'V', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15426 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '6', '4', '_', 'M', 'M', 0,
+ /* 15439 */ 'A', 'D', 'D', 'I', 'U', 'S', '5', '_', 'M', 'M', 0,
+ /* 15450 */ 'S', 'B', '1', '6', '_', 'M', 'M', 0,
+ /* 15458 */ 'J', 'R', 'C', '1', '6', '_', 'M', 'M', 0,
+ /* 15467 */ 'A', 'N', 'D', '1', '6', '_', 'M', 'M', 0,
+ /* 15476 */ 'M', 'O', 'V', 'E', '1', '6', '_', 'M', 'M', 0,
+ /* 15486 */ 'S', 'H', '1', '6', '_', 'M', 'M', 0,
+ /* 15494 */ 'A', 'N', 'D', 'I', '1', '6', '_', 'M', 'M', 0,
+ /* 15504 */ 'M', 'F', 'H', 'I', '1', '6', '_', 'M', 'M', 0,
+ /* 15514 */ 'L', 'I', '1', '6', '_', 'M', 'M', 0,
+ /* 15522 */ 'B', 'R', 'E', 'A', 'K', '1', '6', '_', 'M', 'M', 0,
+ /* 15533 */ 'S', 'L', 'L', '1', '6', '_', 'M', 'M', 0,
+ /* 15542 */ 'S', 'R', 'L', '1', '6', '_', 'M', 'M', 0,
+ /* 15551 */ 'L', 'W', 'M', '1', '6', '_', 'M', 'M', 0,
+ /* 15560 */ 'S', 'W', 'M', '1', '6', '_', 'M', 'M', 0,
+ /* 15569 */ 'M', 'F', 'L', 'O', '1', '6', '_', 'M', 'M', 0,
+ /* 15579 */ 'S', 'D', 'B', 'B', 'P', '1', '6', '_', 'M', 'M', 0,
+ /* 15590 */ 'J', 'R', '1', '6', '_', 'M', 'M', 0,
+ /* 15598 */ 'J', 'A', 'L', 'R', '1', '6', '_', 'M', 'M', 0,
+ /* 15608 */ 'X', 'O', 'R', '1', '6', '_', 'M', 'M', 0,
+ /* 15617 */ 'J', 'A', 'L', 'R', 'S', '1', '6', '_', 'M', 'M', 0,
+ /* 15628 */ 'N', 'O', 'T', '1', '6', '_', 'M', 'M', 0,
+ /* 15637 */ 'L', 'B', 'U', '1', '6', '_', 'M', 'M', 0,
+ /* 15646 */ 'S', 'U', 'B', 'U', '1', '6', '_', 'M', 'M', 0,
+ /* 15656 */ 'A', 'D', 'D', 'U', '1', '6', '_', 'M', 'M', 0,
+ /* 15666 */ 'L', 'H', 'U', '1', '6', '_', 'M', 'M', 0,
+ /* 15675 */ 'L', 'W', '1', '6', '_', 'M', 'M', 0,
+ /* 15683 */ 'S', 'W', '1', '6', '_', 'M', 'M', 0,
+ /* 15691 */ 'B', 'N', 'E', 'Z', '1', '6', '_', 'M', 'M', 0,
+ /* 15701 */ 'B', 'E', 'Q', 'Z', '1', '6', '_', 'M', 'M', 0,
+ /* 15711 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', '_', 'M', 'M', 0,
+ /* 15729 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', '_', 'M', 'M', 0,
+ /* 15748 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', '_', 'M', 'M', 0,
+ /* 15766 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', '_', 'M', 'M', 0,
+ /* 15785 */ 'S', 'R', 'A', '_', 'M', 'M', 0,
+ /* 15792 */ 'S', 'E', 'B', '_', 'M', 'M', 0,
+ /* 15799 */ 'E', 'H', 'B', '_', 'M', 'M', 0,
+ /* 15806 */ 'L', 'B', '_', 'M', 'M', 0,
+ /* 15812 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15827 */ 'C', 'M', 'P', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15841 */ 'P', 'I', 'C', 'K', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15852 */ 'S', 'H', 'L', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15863 */ 'R', 'E', 'P', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15874 */ 'S', 'H', 'R', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15885 */ 'C', 'M', 'P', 'G', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15900 */ 'C', 'M', 'P', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15914 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15927 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15940 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15955 */ 'C', 'M', 'P', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15969 */ 'S', 'U', 'B', 'U', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15980 */ 'A', 'D', 'D', 'U', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 15991 */ 'S', 'H', 'L', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 16003 */ 'R', 'E', 'P', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 16015 */ 'S', 'H', 'R', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 16027 */ 'R', 'A', 'D', 'D', 'U', '_', 'W', '_', 'Q', 'B', '_', 'M', 'M', 0,
+ /* 16041 */ 'S', 'B', '_', 'M', 'M', 0,
+ /* 16047 */ 'M', 'O', 'D', 'S', 'U', 'B', '_', 'M', 'M', 0,
+ /* 16057 */ 'M', 'S', 'U', 'B', '_', 'M', 'M', 0,
+ /* 16065 */ 'S', 'Y', 'N', 'C', '_', 'M', 'M', 0,
+ /* 16073 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', '_', 'M', 'M', 0,
+ /* 16084 */ 'A', 'D', 'D', 'S', 'C', '_', 'M', 'M', 0,
+ /* 16093 */ 'A', 'D', 'D', 'W', 'C', '_', 'M', 'M', 0,
+ /* 16102 */ 'B', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 0,
+ /* 16111 */ 'B', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 0,
+ /* 16120 */ 'M', 'A', 'D', 'D', '_', 'M', 'M', 0,
+ /* 16128 */ 'A', 'N', 'D', '_', 'M', 'M', 0,
+ /* 16135 */ 'L', 'B', 'E', '_', 'M', 'M', 0,
+ /* 16142 */ 'S', 'B', 'E', '_', 'M', 'M', 0,
+ /* 16149 */ 'S', 'C', 'E', '_', 'M', 'M', 0,
+ /* 16156 */ 'C', 'A', 'C', 'H', 'E', 'E', '_', 'M', 'M', 0,
+ /* 16166 */ 'P', 'R', 'E', 'F', 'E', '_', 'M', 'M', 0,
+ /* 16175 */ 'T', 'G', 'E', '_', 'M', 'M', 0,
+ /* 16182 */ 'C', 'A', 'C', 'H', 'E', '_', 'M', 'M', 0,
+ /* 16191 */ 'L', 'H', 'E', '_', 'M', 'M', 0,
+ /* 16198 */ 'S', 'H', 'E', '_', 'M', 'M', 0,
+ /* 16205 */ 'L', 'L', 'E', '_', 'M', 'M', 0,
+ /* 16212 */ 'L', 'W', 'L', 'E', '_', 'M', 'M', 0,
+ /* 16220 */ 'S', 'W', 'L', 'E', '_', 'M', 'M', 0,
+ /* 16228 */ 'B', 'N', 'E', '_', 'M', 'M', 0,
+ /* 16235 */ 'T', 'N', 'E', '_', 'M', 'M', 0,
+ /* 16242 */ 'L', 'W', 'R', 'E', '_', 'M', 'M', 0,
+ /* 16250 */ 'S', 'W', 'R', 'E', '_', 'M', 'M', 0,
+ /* 16258 */ 'P', 'A', 'U', 'S', 'E', '_', 'M', 'M', 0,
+ /* 16267 */ 'L', 'W', 'E', '_', 'M', 'M', 0,
+ /* 16274 */ 'S', 'W', 'E', '_', 'M', 'M', 0,
+ /* 16281 */ 'L', 'B', 'u', 'E', '_', 'M', 'M', 0,
+ /* 16289 */ 'L', 'H', 'u', 'E', '_', 'M', 'M', 0,
+ /* 16297 */ 'B', 'C', '1', 'F', '_', 'M', 'M', 0,
+ /* 16305 */ 'P', 'R', 'E', 'F', '_', 'M', 'M', 0,
+ /* 16313 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 'F', '_', 'M', 'M', 0,
+ /* 16325 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '_', 'M', 'M', 0,
+ /* 16340 */ 'W', 'S', 'B', 'H', '_', 'M', 'M', 0,
+ /* 16348 */ 'S', 'E', 'H', '_', 'M', 'M', 0,
+ /* 16355 */ 'L', 'H', '_', 'M', 'M', 0,
+ /* 16361 */ 'S', 'H', 'R', 'A', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16372 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16388 */ 'P', 'R', 'E', 'C', 'R', 'Q', 'U', '_', 'S', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16407 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16420 */ 'P', 'I', 'C', 'K', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16431 */ 'S', 'H', 'L', 'L', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16442 */ 'R', 'E', 'P', 'L', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16453 */ 'P', 'A', 'C', 'K', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16466 */ 'S', 'U', 'B', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16477 */ 'A', 'D', 'D', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16488 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16501 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16514 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16528 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16542 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16555 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16568 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16581 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16594 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16608 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16621 */ 'S', 'H', 'R', 'A', 'V', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16633 */ 'S', 'H', 'L', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16645 */ 'R', 'E', 'P', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16657 */ 'D', 'P', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16672 */ 'M', 'U', 'L', 'S', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16689 */ 'D', 'P', 'S', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0,
+ /* 16704 */ 'S', 'H', '_', 'M', 'M', 0,
+ /* 16710 */ 'E', 'X', 'T', 'R', '_', 'S', '_', 'H', '_', 'M', 'M', 0,
+ /* 16722 */ 'E', 'X', 'T', 'R', 'V', '_', 'S', '_', 'H', '_', 'M', 'M', 0,
+ /* 16735 */ 'S', 'Y', 'N', 'C', 'I', '_', 'M', 'M', 0,
+ /* 16744 */ 'D', 'I', '_', 'M', 'M', 0,
+ /* 16750 */ 'T', 'G', 'E', 'I', '_', 'M', 'M', 0,
+ /* 16758 */ 'T', 'N', 'E', 'I', '_', 'M', 'M', 0,
+ /* 16766 */ 'M', 'F', 'H', 'I', '_', 'M', 'M', 0,
+ /* 16774 */ 'M', 'T', 'H', 'I', '_', 'M', 'M', 0,
+ /* 16782 */ 'T', 'E', 'Q', 'I', '_', 'M', 'M', 0,
+ /* 16790 */ 'T', 'L', 'T', 'I', '_', 'M', 'M', 0,
+ /* 16798 */ 'T', 'L', 'B', 'W', 'I', '_', 'M', 'M', 0,
+ /* 16807 */ 'T', 'L', 'B', 'G', 'W', 'I', '_', 'M', 'M', 0,
+ /* 16817 */ 'M', 'O', 'V', 'F', '_', 'I', '_', 'M', 'M', 0,
+ /* 16827 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'M', 'M', 0,
+ /* 16837 */ 'M', 'O', 'V', 'T', '_', 'I', '_', 'M', 'M', 0,
+ /* 16847 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'M', 'M', 0,
+ /* 16857 */ 'J', '_', 'M', 'M', 0,
+ /* 16862 */ 'B', 'R', 'E', 'A', 'K', '_', 'M', 'M', 0,
+ /* 16871 */ 'J', 'A', 'L', '_', 'M', 'M', 0,
+ /* 16878 */ 'B', 'G', 'E', 'Z', 'A', 'L', '_', 'M', 'M', 0,
+ /* 16888 */ 'B', 'L', 'T', 'Z', 'A', 'L', '_', 'M', 'M', 0,
+ /* 16898 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0,
+ /* 16916 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0,
+ /* 16933 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0,
+ /* 16951 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0,
+ /* 16965 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0,
+ /* 16979 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0,
+ /* 16995 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0,
+ /* 17011 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0,
+ /* 17026 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0,
+ /* 17043 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0,
+ /* 17055 */ 'H', 'Y', 'P', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0,
+ /* 17066 */ 'S', 'Y', 'S', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0,
+ /* 17077 */ 'S', 'L', 'L', '_', 'M', 'M', 0,
+ /* 17084 */ 'S', 'R', 'L', '_', 'M', 'M', 0,
+ /* 17091 */ 'M', 'U', 'L', '_', 'M', 'M', 0,
+ /* 17098 */ 'L', 'W', 'L', '_', 'M', 'M', 0,
+ /* 17105 */ 'S', 'W', 'L', '_', 'M', 'M', 0,
+ /* 17112 */ 'L', 'W', 'M', '_', 'M', 'M', 0,
+ /* 17119 */ 'S', 'W', 'M', '_', 'M', 'M', 0,
+ /* 17126 */ 'C', 'L', 'O', '_', 'M', 'M', 0,
+ /* 17133 */ 'M', 'F', 'L', 'O', '_', 'M', 'M', 0,
+ /* 17141 */ 'S', 'H', 'I', 'L', 'O', '_', 'M', 'M', 0,
+ /* 17150 */ 'M', 'T', 'L', 'O', '_', 'M', 'M', 0,
+ /* 17158 */ 'T', 'R', 'A', 'P', '_', 'M', 'M', 0,
+ /* 17166 */ 'S', 'D', 'B', 'B', 'P', '_', 'M', 'M', 0,
+ /* 17175 */ 'T', 'L', 'B', 'P', '_', 'M', 'M', 0,
+ /* 17183 */ 'E', 'X', 'T', 'P', 'D', 'P', '_', 'M', 'M', 0,
+ /* 17193 */ 'M', 'O', 'V', 'E', 'P', '_', 'M', 'M', 0,
+ /* 17202 */ 'T', 'L', 'B', 'G', 'P', '_', 'M', 'M', 0,
+ /* 17211 */ 'L', 'W', 'G', 'P', '_', 'M', 'M', 0,
+ /* 17219 */ 'M', 'T', 'H', 'L', 'I', 'P', '_', 'M', 'M', 0,
+ /* 17229 */ 'S', 'S', 'N', 'O', 'P', '_', 'M', 'M', 0,
+ /* 17238 */ 'A', 'D', 'D', 'I', 'U', 'R', '1', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17251 */ 'R', 'D', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17260 */ 'W', 'R', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17269 */ 'L', 'W', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17278 */ 'S', 'W', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17287 */ 'M', 'S', 'U', 'B', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17299 */ 'M', 'A', 'D', 'D', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17311 */ 'M', 'F', 'H', 'I', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17323 */ 'M', 'T', 'H', 'I', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17335 */ 'M', 'F', 'L', 'O', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17347 */ 'M', 'T', 'L', 'O', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17359 */ 'M', 'U', 'L', 'T', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17371 */ 'M', 'S', 'U', 'B', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17384 */ 'M', 'A', 'D', 'D', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17397 */ 'M', 'U', 'L', 'T', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17410 */ 'A', 'D', 'D', 'I', 'U', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17421 */ 'L', 'W', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17429 */ 'S', 'W', 'S', 'P', '_', 'M', 'M', 0,
+ /* 17437 */ 'E', 'X', 'T', 'P', '_', 'M', 'M', 0,
+ /* 17445 */ 'L', 'W', 'P', '_', 'M', 'M', 0,
+ /* 17452 */ 'S', 'W', 'P', '_', 'M', 'M', 0,
+ /* 17459 */ 'B', 'E', 'Q', '_', 'M', 'M', 0,
+ /* 17466 */ 'T', 'E', 'Q', '_', 'M', 'M', 0,
+ /* 17473 */ 'T', 'L', 'B', 'R', '_', 'M', 'M', 0,
+ /* 17481 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0,
+ /* 17499 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0,
+ /* 17516 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0,
+ /* 17534 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0,
+ /* 17548 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0,
+ /* 17562 */ 'B', 'A', 'L', '_', 'B', 'R', '_', 'M', 'M', 0,
+ /* 17572 */ 'T', 'L', 'B', 'G', 'R', '_', 'M', 'M', 0,
+ /* 17581 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0,
+ /* 17597 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0,
+ /* 17613 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0,
+ /* 17628 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0,
+ /* 17645 */ 'J', 'R', '_', 'M', 'M', 0,
+ /* 17651 */ 'J', 'A', 'L', 'R', '_', 'M', 'M', 0,
+ /* 17659 */ 'N', 'O', 'R', '_', 'M', 'M', 0,
+ /* 17666 */ 'X', 'O', 'R', '_', 'M', 'M', 0,
+ /* 17673 */ 'R', 'O', 'T', 'R', '_', 'M', 'M', 0,
+ /* 17681 */ 'T', 'L', 'B', 'W', 'R', '_', 'M', 'M', 0,
+ /* 17690 */ 'T', 'L', 'B', 'G', 'W', 'R', '_', 'M', 'M', 0,
+ /* 17700 */ 'R', 'D', 'H', 'W', 'R', '_', 'M', 'M', 0,
+ /* 17709 */ 'L', 'W', 'R', '_', 'M', 'M', 0,
+ /* 17716 */ 'S', 'W', 'R', '_', 'M', 'M', 0,
+ /* 17723 */ 'J', 'A', 'L', 'S', '_', 'M', 'M', 0,
+ /* 17731 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'S', '_', 'M', 'M', 0,
+ /* 17742 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'S', '_', 'M', 'M', 0,
+ /* 17753 */ 'I', 'N', 'S', '_', 'M', 'M', 0,
+ /* 17760 */ 'J', 'A', 'L', 'R', 'S', '_', 'M', 'M', 0,
+ /* 17769 */ 'L', 'W', 'X', 'S', '_', 'M', 'M', 0,
+ /* 17777 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'S', '_', 'M', 'M', 0,
+ /* 17790 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'S', '_', 'M', 'M', 0,
+ /* 17803 */ 'F', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 0,
+ /* 17813 */ 'N', 'M', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 0,
+ /* 17824 */ 'F', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 0,
+ /* 17834 */ 'N', 'M', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 0,
+ /* 17845 */ 'C', '_', 'N', 'G', 'E', '_', 'S', '_', 'M', 'M', 0,
+ /* 17856 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'S', '_', 'M', 'M', 0,
+ /* 17868 */ 'C', '_', 'O', 'L', 'E', '_', 'S', '_', 'M', 'M', 0,
+ /* 17879 */ 'C', '_', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 0,
+ /* 17890 */ 'C', '_', 'L', 'E', '_', 'S', '_', 'M', 'M', 0,
+ /* 17900 */ 'C', '_', 'S', 'F', '_', 'S', '_', 'M', 'M', 0,
+ /* 17910 */ 'M', 'O', 'V', 'F', '_', 'S', '_', 'M', 'M', 0,
+ /* 17920 */ 'C', '_', 'F', '_', 'S', '_', 'M', 'M', 0,
+ /* 17929 */ 'F', 'N', 'E', 'G', '_', 'S', '_', 'M', 'M', 0,
+ /* 17939 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'S', '_', 'M', 'M', 0,
+ /* 17951 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'S', '_', 'M', 'M', 0,
+ /* 17963 */ 'C', '_', 'N', 'G', 'L', '_', 'S', '_', 'M', 'M', 0,
+ /* 17974 */ 'F', 'M', 'U', 'L', '_', 'S', '_', 'M', 'M', 0,
+ /* 17984 */ 'C', 'V', 'T', '_', 'L', '_', 'S', '_', 'M', 'M', 0,
+ /* 17995 */ 'C', '_', 'U', 'N', '_', 'S', '_', 'M', 'M', 0,
+ /* 18005 */ 'R', 'E', 'C', 'I', 'P', '_', 'S', '_', 'M', 'M', 0,
+ /* 18016 */ 'C', '_', 'S', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0,
+ /* 18027 */ 'C', '_', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0,
+ /* 18038 */ 'C', '_', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0,
+ /* 18048 */ 'F', 'A', 'B', 'S', '_', 'S', '_', 'M', 'M', 0,
+ /* 18058 */ 'C', '_', 'N', 'G', 'T', '_', 'S', '_', 'M', 'M', 0,
+ /* 18069 */ 'C', '_', 'O', 'L', 'T', '_', 'S', '_', 'M', 'M', 0,
+ /* 18080 */ 'C', '_', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 0,
+ /* 18091 */ 'C', '_', 'L', 'T', '_', 'S', '_', 'M', 'M', 0,
+ /* 18101 */ 'F', 'S', 'Q', 'R', 'T', '_', 'S', '_', 'M', 'M', 0,
+ /* 18112 */ 'R', 'S', 'Q', 'R', 'T', '_', 'S', '_', 'M', 'M', 0,
+ /* 18123 */ 'M', 'O', 'V', 'T', '_', 'S', '_', 'M', 'M', 0,
+ /* 18133 */ 'F', 'D', 'I', 'V', '_', 'S', '_', 'M', 'M', 0,
+ /* 18143 */ 'F', 'M', 'O', 'V', '_', 'S', '_', 'M', 'M', 0,
+ /* 18153 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', '_', 'M', 'M', 0,
+ /* 18166 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', '_', 'M', 'M', 0,
+ /* 18179 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', '_', 'M', 'M', 0,
+ /* 18191 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', '_', 'M', 'M', 0,
+ /* 18204 */ 'C', 'V', 'T', '_', 'W', '_', 'S', '_', 'M', 'M', 0,
+ /* 18215 */ 'B', 'C', '1', 'T', '_', 'M', 'M', 0,
+ /* 18223 */ 'D', 'E', 'R', 'E', 'T', '_', 'M', 'M', 0,
+ /* 18232 */ 'W', 'A', 'I', 'T', '_', 'M', 'M', 0,
+ /* 18240 */ 'S', 'L', 'T', '_', 'M', 'M', 0,
+ /* 18247 */ 'T', 'L', 'T', '_', 'M', 'M', 0,
+ /* 18254 */ 'M', 'U', 'L', 'T', '_', 'M', 'M', 0,
+ /* 18262 */ 'E', 'X', 'T', '_', 'M', 'M', 0,
+ /* 18269 */ 'M', 'S', 'U', 'B', 'U', '_', 'M', 'M', 0,
+ /* 18278 */ 'M', 'A', 'D', 'D', 'U', '_', 'M', 'M', 0,
+ /* 18287 */ 'T', 'G', 'E', 'U', '_', 'M', 'M', 0,
+ /* 18295 */ 'T', 'G', 'E', 'I', 'U', '_', 'M', 'M', 0,
+ /* 18304 */ 'T', 'L', 'T', 'I', 'U', '_', 'M', 'M', 0,
+ /* 18313 */ 'T', 'L', 'T', 'U', '_', 'M', 'M', 0,
+ /* 18321 */ 'L', 'W', 'U', '_', 'M', 'M', 0,
+ /* 18328 */ 'S', 'R', 'A', 'V', '_', 'M', 'M', 0,
+ /* 18336 */ 'B', 'I', 'T', 'R', 'E', 'V', '_', 'M', 'M', 0,
+ /* 18346 */ 'S', 'D', 'I', 'V', '_', 'M', 'M', 0,
+ /* 18354 */ 'U', 'D', 'I', 'V', '_', 'M', 'M', 0,
+ /* 18362 */ 'S', 'L', 'L', 'V', '_', 'M', 'M', 0,
+ /* 18370 */ 'S', 'R', 'L', 'V', '_', 'M', 'M', 0,
+ /* 18378 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', '_', 'M', 'M', 0,
+ /* 18389 */ 'S', 'H', 'I', 'L', 'O', 'V', '_', 'M', 'M', 0,
+ /* 18399 */ 'E', 'X', 'T', 'P', 'D', 'P', 'V', '_', 'M', 'M', 0,
+ /* 18410 */ 'E', 'X', 'T', 'P', 'V', '_', 'M', 'M', 0,
+ /* 18419 */ 'R', 'O', 'T', 'R', 'V', '_', 'M', 'M', 0,
+ /* 18428 */ 'I', 'N', 'S', 'V', '_', 'M', 'M', 0,
+ /* 18436 */ 'L', 'W', '_', 'M', 'M', 0,
+ /* 18442 */ 'S', 'W', '_', 'M', 'M', 0,
+ /* 18448 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'W', '_', 'M', 'M', 0,
+ /* 18461 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'W', '_', 'M', 'M', 0,
+ /* 18474 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'M', 'M', 0,
+ /* 18485 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'M', 'M', 0,
+ /* 18496 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 0,
+ /* 18511 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 0,
+ /* 18529 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'M', 'M', 0,
+ /* 18539 */ 'D', 'P', 'A', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', '_', 'M', 'M', 0,
+ /* 18554 */ 'D', 'P', 'S', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', '_', 'M', 'M', 0,
+ /* 18569 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'M', 'M', 0,
+ /* 18580 */ 'E', 'X', 'T', 'R', '_', 'W', '_', 'M', 'M', 0,
+ /* 18590 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'W', '_', 'M', 'M', 0,
+ /* 18602 */ 'E', 'X', 'T', 'R', '_', 'R', '_', 'W', '_', 'M', 'M', 0,
+ /* 18614 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'W', '_', 'M', 'M', 0,
+ /* 18627 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', '_', 'W', '_', 'M', 'M', 0,
+ /* 18640 */ 'E', 'X', 'T', 'R', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 0,
+ /* 18653 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 0,
+ /* 18667 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'W', '_', 'M', 'M', 0,
+ /* 18679 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0,
+ /* 18691 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0,
+ /* 18703 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0,
+ /* 18715 */ 'C', 'V', 'T', '_', 'S', '_', 'W', '_', 'M', 'M', 0,
+ /* 18726 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'W', '_', 'M', 'M', 0,
+ /* 18739 */ 'E', 'X', 'T', 'R', 'V', '_', 'W', '_', 'M', 'M', 0,
+ /* 18750 */ 'P', 'R', 'E', 'F', 'X', '_', 'M', 'M', 0,
+ /* 18759 */ 'L', 'H', 'X', '_', 'M', 'M', 0,
+ /* 18766 */ 'J', 'A', 'L', 'X', '_', 'M', 'M', 0,
+ /* 18774 */ 'L', 'B', 'U', 'X', '_', 'M', 'M', 0,
+ /* 18782 */ 'L', 'W', 'X', '_', 'M', 'M', 0,
+ /* 18789 */ 'B', 'G', 'E', 'Z', '_', 'M', 'M', 0,
+ /* 18797 */ 'B', 'L', 'E', 'Z', '_', 'M', 'M', 0,
+ /* 18805 */ 'C', 'L', 'Z', '_', 'M', 'M', 0,
+ /* 18812 */ 'B', 'G', 'T', 'Z', '_', 'M', 'M', 0,
+ /* 18820 */ 'B', 'L', 'T', 'Z', '_', 'M', 'M', 0,
+ /* 18828 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '_', 'M', 'M', 0,
+ /* 18852 */ 'A', 'D', 'D', 'i', '_', 'M', 'M', 0,
+ /* 18860 */ 'A', 'N', 'D', 'i', '_', 'M', 'M', 0,
+ /* 18868 */ 'X', 'O', 'R', 'i', '_', 'M', 'M', 0,
+ /* 18876 */ 'S', 'L', 'T', 'i', '_', 'M', 'M', 0,
+ /* 18884 */ 'L', 'U', 'i', '_', 'M', 'M', 0,
+ /* 18891 */ 'L', 'B', 'u', '_', 'M', 'M', 0,
+ /* 18898 */ 'S', 'U', 'B', 'u', '_', 'M', 'M', 0,
+ /* 18906 */ 'A', 'D', 'D', 'u', '_', 'M', 'M', 0,
+ /* 18914 */ 'L', 'H', 'u', '_', 'M', 'M', 0,
+ /* 18921 */ 'S', 'L', 'T', 'u', '_', 'M', 'M', 0,
+ /* 18929 */ 'M', 'U', 'L', 'T', 'u', '_', 'M', 'M', 0,
+ /* 18938 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', '_', 'M', 'M', 0,
+ /* 18951 */ 'S', 'L', 'T', 'i', 'u', '_', 'M', 'M', 0,
+ /* 18960 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
+ /* 18970 */ 'D', 'I', 'N', 'S', 'M', 0,
+ /* 18976 */ 'D', 'E', 'X', 'T', 'M', 0,
+ /* 18982 */ 'B', 'A', 'L', 'I', 'G', 'N', 0,
+ /* 18989 */ 'D', 'A', 'L', 'I', 'G', 'N', 0,
+ /* 18996 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
+ /* 19013 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
+ /* 19029 */ 'D', 'M', 'F', 'C', '2', '_', 'O', 'C', 'T', 'E', 'O', 'N', 0,
+ /* 19042 */ 'D', 'M', 'T', 'C', '2', '_', 'O', 'C', 'T', 'E', 'O', 'N', 0,
+ /* 19055 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
+ /* 19071 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
+ /* 19088 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
+ /* 19096 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
+ /* 19104 */ 'F', 'E', 'X', 'P', '2', '_', 'D', '_', '1', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19121 */ 'F', 'E', 'X', 'P', '2', '_', 'W', '_', '1', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19138 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19154 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19177 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19201 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19224 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19247 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19271 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19294 */ 'S', 'N', 'Z', '_', 'B', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19307 */ 'S', 'Z', '_', 'B', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19319 */ 'B', 'S', 'E', 'L', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19334 */ 'F', 'I', 'L', 'L', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19349 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19366 */ 'C', 'O', 'P', 'Y', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19381 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19404 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'R', 'O', 'U', 'N', 'D', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19426 */ 'B', 'S', 'E', 'L', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19440 */ 'A', 'N', 'D', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19455 */ 'N', 'O', 'R', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19470 */ 'X', 'O', 'R', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19485 */ 'S', 'N', 'Z', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19498 */ 'S', 'Z', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19510 */ 'B', 'S', 'E', 'L', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19524 */ 'A', 'N', 'D', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19539 */ 'N', 'O', 'R', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19554 */ 'X', 'O', 'R', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19569 */ 'S', 'N', 'Z', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19582 */ 'S', 'Z', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19594 */ 'S', 'N', 'Z', '_', 'V', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19607 */ 'S', 'Z', '_', 'V', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19619 */ 'B', 'S', 'E', 'L', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19634 */ 'F', 'I', 'L', 'L', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19649 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19666 */ 'C', 'O', 'P', 'Y', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19681 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19704 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19726 */ 'B', 'S', 'E', 'L', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19740 */ 'A', 'N', 'D', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19755 */ 'N', 'O', 'R', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19770 */ 'X', 'O', 'R', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19785 */ 'S', 'N', 'Z', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19798 */ 'S', 'Z', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19810 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19831 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19853 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19874 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19895 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19917 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0,
+ /* 19938 */ 'D', 'C', 'L', 'O', 0,
+ /* 19943 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', 0,
+ /* 19954 */ 'S', 'H', 'I', 'L', 'O', 0,
+ /* 19960 */ 'M', 'F', 'T', 'L', 'O', 0,
+ /* 19966 */ 'M', 'T', 'L', 'O', 0,
+ /* 19971 */ 'M', 'T', 'T', 'L', 'O', 0,
+ /* 19977 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
+ /* 19985 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
+ /* 19993 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
+ /* 20002 */ 'T', 'R', 'A', 'P', 0,
+ /* 20007 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
+ /* 20015 */ 'D', 'B', 'I', 'T', 'S', 'W', 'A', 'P', 0,
+ /* 20024 */ 'S', 'D', 'B', 'B', 'P', 0,
+ /* 20030 */ 'T', 'L', 'B', 'P', 0,
+ /* 20035 */ 'E', 'X', 'T', 'P', 'D', 'P', 0,
+ /* 20042 */ 'G', '_', 'G', 'E', 'P', 0,
+ /* 20048 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
+ /* 20057 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
+ /* 20066 */ 'T', 'L', 'B', 'G', 'P', 0,
+ /* 20072 */ 'M', 'T', 'H', 'L', 'I', 'P', 0,
+ /* 20079 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
+ /* 20086 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
+ /* 20093 */ 'S', 'S', 'N', 'O', 'P', 0,
+ /* 20099 */ 'D', 'P', 'O', 'P', 0,
+ /* 20104 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
+ /* 20117 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
+ /* 20129 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
+ /* 20143 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
+ /* 20158 */ 'R', 'D', 'D', 'S', 'P', 0,
+ /* 20164 */ 'W', 'R', 'D', 'S', 'P', 0,
+ /* 20170 */ 'M', 'F', 'T', 'D', 'S', 'P', 0,
+ /* 20177 */ 'M', 'T', 'T', 'D', 'S', 'P', 0,
+ /* 20184 */ 'L', 'W', 'D', 'S', 'P', 0,
+ /* 20190 */ 'S', 'W', 'D', 'S', 'P', 0,
+ /* 20196 */ 'M', 'S', 'U', 'B', '_', 'D', 'S', 'P', 0,
+ /* 20205 */ 'M', 'A', 'D', 'D', '_', 'D', 'S', 'P', 0,
+ /* 20214 */ 'L', 'O', 'A', 'D', '_', 'C', 'C', 'O', 'N', 'D', '_', 'D', 'S', 'P', 0,
+ /* 20229 */ 'S', 'T', 'O', 'R', 'E', '_', 'C', 'C', 'O', 'N', 'D', '_', 'D', 'S', 'P', 0,
+ /* 20245 */ 'M', 'F', 'H', 'I', '_', 'D', 'S', 'P', 0,
+ /* 20254 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '_', 'D', 'S', 'P', 0,
+ /* 20271 */ 'M', 'T', 'H', 'I', '_', 'D', 'S', 'P', 0,
+ /* 20280 */ 'M', 'F', 'L', 'O', '_', 'D', 'S', 'P', 0,
+ /* 20289 */ 'M', 'T', 'L', 'O', '_', 'D', 'S', 'P', 0,
+ /* 20298 */ 'M', 'U', 'L', 'T', '_', 'D', 'S', 'P', 0,
+ /* 20307 */ 'M', 'S', 'U', 'B', 'U', '_', 'D', 'S', 'P', 0,
+ /* 20317 */ 'M', 'A', 'D', 'D', 'U', '_', 'D', 'S', 'P', 0,
+ /* 20327 */ 'M', 'U', 'L', 'T', 'U', '_', 'D', 'S', 'P', 0,
+ /* 20337 */ 'J', 'R', 'A', 'D', 'D', 'I', 'U', 'S', 'P', 0,
+ /* 20347 */ 'E', 'X', 'T', 'P', 0,
+ /* 20352 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
+ /* 20367 */ 'D', 'V', 'P', 0,
+ /* 20371 */ 'E', 'V', 'P', 0,
+ /* 20375 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
+ /* 20382 */ 'B', 'E', 'Q', 0,
+ /* 20386 */ 'S', 'E', 'Q', 0,
+ /* 20390 */ 'T', 'E', 'Q', 0,
+ /* 20394 */ 'T', 'L', 'B', 'R', 0,
+ /* 20399 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0,
+ /* 20414 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0,
+ /* 20428 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0,
+ /* 20443 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'R', 0,
+ /* 20454 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'R', 0,
+ /* 20465 */ 'G', '_', 'B', 'R', 0,
+ /* 20470 */ 'B', 'A', 'L', '_', 'B', 'R', 0,
+ /* 20477 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
+ /* 20490 */ 'L', 'D', 'R', 0,
+ /* 20494 */ 'S', 'D', 'R', 0,
+ /* 20498 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
+ /* 20523 */ 'T', 'L', 'B', 'G', 'R', 0,
+ /* 20529 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', 0,
+ /* 20546 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'S', 'i', 'n', 'g', 'l', 'e', 'F', 'G', 'R', 0,
+ /* 20563 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'R', 0,
+ /* 20576 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'R', 0,
+ /* 20589 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', 0,
+ /* 20601 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', 0,
+ /* 20615 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
+ /* 20622 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
+ /* 20629 */ 'J', 'R', 0,
+ /* 20632 */ 'J', 'A', 'L', 'R', 0,
+ /* 20637 */ 'N', 'O', 'R', 0,
+ /* 20641 */ 'D', 'R', 'O', 'R', 0,
+ /* 20646 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
+ /* 20663 */ 'G', '_', 'X', 'O', 'R', 0,
+ /* 20669 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
+ /* 20685 */ 'G', '_', 'O', 'R', 0,
+ /* 20690 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
+ /* 20705 */ 'M', 'F', 'T', 'G', 'P', 'R', 0,
+ /* 20712 */ 'M', 'T', 'T', 'G', 'P', 'R', 0,
+ /* 20719 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'G', 'P', 'R', 0,
+ /* 20736 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'S', 'i', 'n', 'g', 'l', 'e', 'G', 'P', 'R', 0,
+ /* 20753 */ 'M', 'F', 'T', 'R', 0,
+ /* 20758 */ 'D', 'R', 'O', 'T', 'R', 0,
+ /* 20764 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
+ /* 20775 */ 'M', 'T', 'T', 'R', 0,
+ /* 20780 */ 'T', 'L', 'B', 'W', 'R', 0,
+ /* 20786 */ 'T', 'L', 'B', 'G', 'W', 'R', 0,
+ /* 20793 */ 'R', 'D', 'H', 'W', 'R', 0,
+ /* 20799 */ 'L', 'W', 'R', 0,
+ /* 20803 */ 'S', 'W', 'R', 0,
+ /* 20807 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
+ /* 20814 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
+ /* 20831 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
+ /* 20846 */ 'C', 'I', 'N', 'S', 0,
+ /* 20851 */ 'D', 'I', 'N', 'S', 0,
+ /* 20856 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
+ /* 20873 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
+ /* 20903 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
+ /* 20930 */ 'E', 'X', 'T', 'S', 0,
+ /* 20935 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'S', 0,
+ /* 20945 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'S', 0,
+ /* 20955 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'S', 0,
+ /* 20966 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'S', 0,
+ /* 20977 */ 'M', 'I', 'N', 'A', '_', 'S', 0,
+ /* 20984 */ 'M', 'A', 'X', 'A', '_', 'S', 0,
+ /* 20991 */ 'F', 'S', 'U', 'B', '_', 'S', 0,
+ /* 20998 */ 'N', 'M', 'S', 'U', 'B', '_', 'S', 0,
+ /* 21006 */ 'F', 'A', 'D', 'D', '_', 'S', 0,
+ /* 21013 */ 'N', 'M', 'A', 'D', 'D', '_', 'S', 0,
+ /* 21021 */ 'C', '_', 'N', 'G', 'E', '_', 'S', 0,
+ /* 21029 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'S', 0,
+ /* 21038 */ 'C', '_', 'O', 'L', 'E', '_', 'S', 0,
+ /* 21046 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'S', 0,
+ /* 21056 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'S', 0,
+ /* 21067 */ 'C', '_', 'U', 'L', 'E', '_', 'S', 0,
+ /* 21075 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'S', 0,
+ /* 21085 */ 'C', '_', 'L', 'E', '_', 'S', 0,
+ /* 21092 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'S', 0,
+ /* 21101 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'S', 0,
+ /* 21111 */ 'M', 'S', 'U', 'B', 'F', '_', 'S', 0,
+ /* 21119 */ 'M', 'A', 'D', 'D', 'F', '_', 'S', 0,
+ /* 21127 */ 'C', '_', 'S', 'F', '_', 'S', 0,
+ /* 21134 */ 'M', 'O', 'V', 'F', '_', 'S', 0,
+ /* 21141 */ 'C', '_', 'F', '_', 'S', 0,
+ /* 21147 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'S', 0,
+ /* 21166 */ 'C', 'M', 'P', '_', 'F', '_', 'S', 0,
+ /* 21174 */ 'F', 'N', 'E', 'G', '_', 'S', 0,
+ /* 21181 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'S', 0,
+ /* 21190 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'S', 0,
+ /* 21199 */ 'S', 'E', 'L', '_', 'S', 0,
+ /* 21205 */ 'C', '_', 'N', 'G', 'L', '_', 'S', 0,
+ /* 21213 */ 'F', 'M', 'U', 'L', '_', 'S', 0,
+ /* 21220 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'S', 0,
+ /* 21230 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'S', 0,
+ /* 21240 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'S', 0,
+ /* 21249 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'S', 0,
+ /* 21259 */ 'C', 'V', 'T', '_', 'L', '_', 'S', 0,
+ /* 21267 */ 'M', 'I', 'N', '_', 'S', 0,
+ /* 21273 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'S', 0,
+ /* 21283 */ 'C', '_', 'U', 'N', '_', 'S', 0,
+ /* 21290 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'S', 0,
+ /* 21299 */ 'R', 'E', 'C', 'I', 'P', '_', 'S', 0,
+ /* 21307 */ 'C', '_', 'S', 'E', 'Q', '_', 'S', 0,
+ /* 21315 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'S', 0,
+ /* 21325 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'S', 0,
+ /* 21336 */ 'C', '_', 'U', 'E', 'Q', '_', 'S', 0,
+ /* 21344 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'S', 0,
+ /* 21354 */ 'C', '_', 'E', 'Q', '_', 'S', 0,
+ /* 21361 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'S', 0,
+ /* 21370 */ 'F', 'A', 'B', 'S', '_', 'S', 0,
+ /* 21377 */ 'C', 'L', 'A', 'S', 'S', '_', 'S', 0,
+ /* 21385 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 0,
+ /* 21400 */ 'C', '_', 'N', 'G', 'T', '_', 'S', 0,
+ /* 21408 */ 'C', '_', 'O', 'L', 'T', '_', 'S', 0,
+ /* 21416 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'S', 0,
+ /* 21426 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'S', 0,
+ /* 21437 */ 'C', '_', 'U', 'L', 'T', '_', 'S', 0,
+ /* 21445 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'S', 0,
+ /* 21455 */ 'C', '_', 'L', 'T', '_', 'S', 0,
+ /* 21462 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'S', 0,
+ /* 21471 */ 'R', 'I', 'N', 'T', '_', 'S', 0,
+ /* 21478 */ 'F', 'S', 'Q', 'R', 'T', '_', 'S', 0,
+ /* 21486 */ 'R', 'S', 'Q', 'R', 'T', '_', 'S', 0,
+ /* 21494 */ 'M', 'O', 'V', 'T', '_', 'S', 0,
+ /* 21501 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'S', 0,
+ /* 21520 */ 'F', 'D', 'I', 'V', '_', 'S', 0,
+ /* 21527 */ 'F', 'M', 'O', 'V', '_', 'S', 0,
+ /* 21534 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', 0,
+ /* 21550 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', 0,
+ /* 21560 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', 0,
+ /* 21569 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', 0,
+ /* 21579 */ 'C', 'V', 'T', '_', 'W', '_', 'S', 0,
+ /* 21587 */ 'M', 'A', 'X', '_', 'S', 0,
+ /* 21593 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'S', 0,
+ /* 21602 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'S', 0,
+ /* 21611 */ 'B', 'C', '1', 'T', 0,
+ /* 21616 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
+ /* 21626 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
+ /* 21635 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
+ /* 21648 */ 'D', 'E', 'R', 'E', 'T', 0,
+ /* 21654 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
+ /* 21668 */ 'B', 'G', 'T', 0,
+ /* 21672 */ 'W', 'A', 'I', 'T', 0,
+ /* 21677 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
+ /* 21701 */ 'B', 'L', 'T', 0,
+ /* 21705 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
+ /* 21726 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
+ /* 21746 */ 'S', 'L', 'T', 0,
+ /* 21750 */ 'T', 'L', 'T', 0,
+ /* 21754 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'M', 'U', 'L', 'T', 0,
+ /* 21766 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', 0,
+ /* 21777 */ 'D', 'M', 'T', 0,
+ /* 21781 */ 'E', 'M', 'T', 0,
+ /* 21785 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
+ /* 21797 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
+ /* 21808 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
+ /* 21819 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
+ /* 21830 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
+ /* 21841 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 21851 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 21866 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
+ /* 21875 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
+ /* 21885 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
+ /* 21902 */ 'G', 'I', 'N', 'V', 'T', 0,
+ /* 21908 */ 'D', 'E', 'X', 'T', 0,
+ /* 21913 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
+ /* 21921 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
+ /* 21928 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
+ /* 21937 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
+ /* 21944 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', 'U', 0,
+ /* 21956 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', 'U', 0,
+ /* 21968 */ 'D', 'M', 'O', 'D', 'U', 0,
+ /* 21974 */ 'B', 'G', 'E', 'U', 0,
+ /* 21979 */ 'T', 'G', 'E', 'U', 0,
+ /* 21984 */ 'B', 'L', 'E', 'U', 0,
+ /* 21989 */ 'D', 'M', 'U', 'H', 'U', 0,
+ /* 21995 */ 'T', 'G', 'E', 'I', 'U', 0,
+ /* 22001 */ 'T', 'T', 'L', 'T', 'I', 'U', 0,
+ /* 22008 */ 'V', '3', 'M', 'U', 'L', 'U', 0,
+ /* 22015 */ 'D', 'M', 'U', 'L', 'U', 0,
+ /* 22021 */ 'V', 'M', 'U', 'L', 'U', 0,
+ /* 22027 */ 'D', 'I', 'N', 'S', 'U', 0,
+ /* 22033 */ 'B', 'G', 'T', 'U', 0,
+ /* 22038 */ 'B', 'L', 'T', 'U', 0,
+ /* 22043 */ 'T', 'L', 'T', 'U', 0,
+ /* 22048 */ 'D', 'E', 'X', 'T', 'U', 0,
+ /* 22054 */ 'D', 'D', 'I', 'V', 'U', 0,
+ /* 22060 */ 'D', 'S', 'R', 'A', 'V', 0,
+ /* 22066 */ 'B', 'I', 'T', 'R', 'E', 'V', 0,
+ /* 22073 */ 'D', 'D', 'I', 'V', 0,
+ /* 22078 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
+ /* 22085 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'S', 'D', 'I', 'V', 0,
+ /* 22097 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
+ /* 22104 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'D', 'I', 'V', 0,
+ /* 22115 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'U', 'D', 'I', 'V', 0,
+ /* 22127 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
+ /* 22134 */ 'P', 's', 'e', 'u', 'd', 'o', 'U', 'D', 'I', 'V', 0,
+ /* 22145 */ 'D', 'S', 'L', 'L', 'V', 0,
+ /* 22151 */ 'D', 'S', 'R', 'L', 'V', 0,
+ /* 22157 */ 'T', 'L', 'B', 'I', 'N', 'V', 0,
+ /* 22164 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 0,
+ /* 22172 */ 'S', 'H', 'I', 'L', 'O', 'V', 0,
+ /* 22179 */ 'E', 'X', 'T', 'P', 'D', 'P', 'V', 0,
+ /* 22187 */ 'E', 'X', 'T', 'P', 'V', 0,
+ /* 22193 */ 'D', 'R', 'O', 'T', 'R', 'V', 0,
+ /* 22200 */ 'I', 'N', 'S', 'V', 0,
+ /* 22205 */ 'A', 'N', 'D', '_', 'V', 0,
+ /* 22211 */ 'M', 'O', 'V', 'E', '_', 'V', 0,
+ /* 22218 */ 'B', 'S', 'E', 'L', '_', 'V', 0,
+ /* 22225 */ 'N', 'O', 'R', '_', 'V', 0,
+ /* 22231 */ 'X', 'O', 'R', '_', 'V', 0,
+ /* 22237 */ 'B', 'Z', '_', 'V', 0,
+ /* 22242 */ 'B', 'M', 'Z', '_', 'V', 0,
+ /* 22248 */ 'B', 'N', 'Z', '_', 'V', 0,
+ /* 22254 */ 'B', 'M', 'N', 'Z', '_', 'V', 0,
+ /* 22261 */ 'C', 'R', 'C', '3', '2', 'W', 0,
+ /* 22268 */ 'C', 'R', 'C', '3', '2', 'C', 'W', 0,
+ /* 22276 */ 'L', 'W', 0,
+ /* 22279 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
+ /* 22286 */ 'S', 'W', 0,
+ /* 22289 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'W', 0,
+ /* 22305 */ 'F', 'L', 'O', 'G', '2', '_', 'W', 0,
+ /* 22313 */ 'F', 'E', 'X', 'P', '2', '_', 'W', 0,
+ /* 22321 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'W', 0,
+ /* 22337 */ 'S', 'R', 'A', '_', 'W', 0,
+ /* 22343 */ 'A', 'D', 'D', '_', 'A', '_', 'W', 0,
+ /* 22351 */ 'F', 'M', 'I', 'N', '_', 'A', '_', 'W', 0,
+ /* 22360 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'W', 0,
+ /* 22369 */ 'F', 'M', 'A', 'X', '_', 'A', '_', 'W', 0,
+ /* 22378 */ 'F', 'S', 'U', 'B', '_', 'W', 0,
+ /* 22385 */ 'F', 'M', 'S', 'U', 'B', '_', 'W', 0,
+ /* 22393 */ 'N', 'L', 'O', 'C', '_', 'W', 0,
+ /* 22400 */ 'N', 'L', 'Z', 'C', '_', 'W', 0,
+ /* 22407 */ 'F', 'A', 'D', 'D', '_', 'W', 0,
+ /* 22414 */ 'F', 'M', 'A', 'D', 'D', '_', 'W', 0,
+ /* 22422 */ 'S', 'L', 'D', '_', 'W', 0,
+ /* 22428 */ 'P', 'C', 'K', 'O', 'D', '_', 'W', 0,
+ /* 22436 */ 'I', 'L', 'V', 'O', 'D', '_', 'W', 0,
+ /* 22444 */ 'F', 'C', 'L', 'E', '_', 'W', 0,
+ /* 22451 */ 'F', 'S', 'L', 'E', '_', 'W', 0,
+ /* 22458 */ 'F', 'C', 'U', 'L', 'E', '_', 'W', 0,
+ /* 22466 */ 'F', 'S', 'U', 'L', 'E', '_', 'W', 0,
+ /* 22474 */ 'F', 'C', 'N', 'E', '_', 'W', 0,
+ /* 22481 */ 'F', 'S', 'N', 'E', '_', 'W', 0,
+ /* 22488 */ 'F', 'C', 'U', 'N', 'E', '_', 'W', 0,
+ /* 22496 */ 'F', 'S', 'U', 'N', 'E', '_', 'W', 0,
+ /* 22504 */ 'I', 'N', 'S', 'V', 'E', '_', 'W', 0,
+ /* 22512 */ 'F', 'C', 'A', 'F', '_', 'W', 0,
+ /* 22519 */ 'F', 'S', 'A', 'F', '_', 'W', 0,
+ /* 22526 */ 'V', 'S', 'H', 'F', '_', 'W', 0,
+ /* 22533 */ 'B', 'N', 'E', 'G', '_', 'W', 0,
+ /* 22540 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', 0,
+ /* 22555 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'P', 'H', '_', 'W', 0,
+ /* 22567 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', 0,
+ /* 22584 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'W', 0,
+ /* 22599 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', 0,
+ /* 22607 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', 0,
+ /* 22615 */ 'S', 'R', 'A', 'I', '_', 'W', 0,
+ /* 22622 */ 'S', 'L', 'D', 'I', '_', 'W', 0,
+ /* 22629 */ 'B', 'N', 'E', 'G', 'I', '_', 'W', 0,
+ /* 22637 */ 'S', 'L', 'L', 'I', '_', 'W', 0,
+ /* 22644 */ 'S', 'R', 'L', 'I', '_', 'W', 0,
+ /* 22651 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'W', 0,
+ /* 22660 */ 'C', 'E', 'Q', 'I', '_', 'W', 0,
+ /* 22667 */ 'S', 'R', 'A', 'R', 'I', '_', 'W', 0,
+ /* 22675 */ 'B', 'C', 'L', 'R', 'I', '_', 'W', 0,
+ /* 22683 */ 'S', 'R', 'L', 'R', 'I', '_', 'W', 0,
+ /* 22691 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'W', 0,
+ /* 22700 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'W', 0,
+ /* 22709 */ 'B', 'S', 'E', 'T', 'I', '_', 'W', 0,
+ /* 22717 */ 'S', 'U', 'B', 'V', 'I', '_', 'W', 0,
+ /* 22725 */ 'A', 'D', 'D', 'V', 'I', '_', 'W', 0,
+ /* 22733 */ 'F', 'I', 'L', 'L', '_', 'W', 0,
+ /* 22740 */ 'S', 'L', 'L', '_', 'W', 0,
+ /* 22746 */ 'F', 'E', 'X', 'U', 'P', 'L', '_', 'W', 0,
+ /* 22755 */ 'F', 'F', 'Q', 'L', '_', 'W', 0,
+ /* 22762 */ 'S', 'R', 'L', '_', 'W', 0,
+ /* 22768 */ 'B', 'I', 'N', 'S', 'L', '_', 'W', 0,
+ /* 22776 */ 'F', 'M', 'U', 'L', '_', 'W', 0,
+ /* 22783 */ 'I', 'L', 'V', 'L', '_', 'W', 0,
+ /* 22790 */ 'D', 'P', 'A', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', 0,
+ /* 22802 */ 'D', 'P', 'S', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', 0,
+ /* 22814 */ 'F', 'M', 'I', 'N', '_', 'W', 0,
+ /* 22821 */ 'F', 'C', 'U', 'N', '_', 'W', 0,
+ /* 22828 */ 'F', 'S', 'U', 'N', '_', 'W', 0,
+ /* 22835 */ 'F', 'E', 'X', 'D', 'O', '_', 'W', 0,
+ /* 22843 */ 'F', 'R', 'C', 'P', '_', 'W', 0,
+ /* 22850 */ 'F', 'C', 'E', 'Q', '_', 'W', 0,
+ /* 22857 */ 'F', 'S', 'E', 'Q', '_', 'W', 0,
+ /* 22864 */ 'F', 'C', 'U', 'E', 'Q', '_', 'W', 0,
+ /* 22872 */ 'F', 'S', 'U', 'E', 'Q', '_', 'W', 0,
+ /* 22880 */ 'F', 'T', 'Q', '_', 'W', 0,
+ /* 22886 */ 'M', 'S', 'U', 'B', '_', 'Q', '_', 'W', 0,
+ /* 22895 */ 'M', 'A', 'D', 'D', '_', 'Q', '_', 'W', 0,
+ /* 22904 */ 'M', 'U', 'L', '_', 'Q', '_', 'W', 0,
+ /* 22912 */ 'M', 'S', 'U', 'B', 'R', '_', 'Q', '_', 'W', 0,
+ /* 22922 */ 'M', 'A', 'D', 'D', 'R', '_', 'Q', '_', 'W', 0,
+ /* 22932 */ 'M', 'U', 'L', 'R', '_', 'Q', '_', 'W', 0,
+ /* 22941 */ 'S', 'R', 'A', 'R', '_', 'W', 0,
+ /* 22948 */ 'B', 'C', 'L', 'R', '_', 'W', 0,
+ /* 22955 */ 'S', 'R', 'L', 'R', '_', 'W', 0,
+ /* 22962 */ 'F', 'C', 'O', 'R', '_', 'W', 0,
+ /* 22969 */ 'F', 'S', 'O', 'R', '_', 'W', 0,
+ /* 22976 */ 'F', 'E', 'X', 'U', 'P', 'R', '_', 'W', 0,
+ /* 22985 */ 'F', 'F', 'Q', 'R', '_', 'W', 0,
+ /* 22992 */ 'B', 'I', 'N', 'S', 'R', '_', 'W', 0,
+ /* 23000 */ 'E', 'X', 'T', 'R', '_', 'W', 0,
+ /* 23007 */ 'I', 'L', 'V', 'R', '_', 'W', 0,
+ /* 23014 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'W', 0,
+ /* 23023 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', 0,
+ /* 23033 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', 0,
+ /* 23043 */ 'E', 'X', 'T', 'R', '_', 'R', '_', 'W', 0,
+ /* 23052 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'W', 0,
+ /* 23062 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', '_', 'W', 0,
+ /* 23072 */ 'F', 'A', 'B', 'S', '_', 'W', 0,
+ /* 23079 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', 0,
+ /* 23089 */ 'E', 'X', 'T', 'R', '_', 'R', 'S', '_', 'W', 0,
+ /* 23099 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', 'S', '_', 'W', 0,
+ /* 23110 */ 'F', 'C', 'L', 'A', 'S', 'S', '_', 'W', 0,
+ /* 23119 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'W', 0,
+ /* 23128 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'W', 0,
+ /* 23137 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'W', 0,
+ /* 23147 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'W', 0,
+ /* 23158 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'W', 0,
+ /* 23167 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'W', 0,
+ /* 23177 */ 'M', 'O', 'D', '_', 'S', '_', 'W', 0,
+ /* 23185 */ 'C', 'L', 'E', '_', 'S', '_', 'W', 0,
+ /* 23193 */ 'A', 'V', 'E', '_', 'S', '_', 'W', 0,
+ /* 23201 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'W', 0,
+ /* 23210 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'W', 0,
+ /* 23219 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'W', 0,
+ /* 23228 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'W', 0,
+ /* 23237 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'W', 0,
+ /* 23246 */ 'M', 'I', 'N', '_', 'S', '_', 'W', 0,
+ /* 23254 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'W', 0,
+ /* 23263 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'W', 0,
+ /* 23272 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'W', 0,
+ /* 23281 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', 0,
+ /* 23290 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'W', 0,
+ /* 23299 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'W', 0,
+ /* 23308 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'W', 0,
+ /* 23317 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'W', 0,
+ /* 23326 */ 'S', 'A', 'T', '_', 'S', '_', 'W', 0,
+ /* 23334 */ 'C', 'L', 'T', '_', 'S', '_', 'W', 0,
+ /* 23342 */ 'F', 'F', 'I', 'N', 'T', '_', 'S', '_', 'W', 0,
+ /* 23352 */ 'F', 'T', 'I', 'N', 'T', '_', 'S', '_', 'W', 0,
+ /* 23362 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'S', '_', 'W', 0,
+ /* 23376 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'W', 0,
+ /* 23387 */ 'D', 'I', 'V', '_', 'S', '_', 'W', 0,
+ /* 23395 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'W', 0,
+ /* 23405 */ 'M', 'A', 'X', '_', 'S', '_', 'W', 0,
+ /* 23413 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'W', 0,
+ /* 23422 */ 'S', 'P', 'L', 'A', 'T', '_', 'W', 0,
+ /* 23430 */ 'B', 'S', 'E', 'T', '_', 'W', 0,
+ /* 23437 */ 'F', 'C', 'L', 'T', '_', 'W', 0,
+ /* 23444 */ 'F', 'S', 'L', 'T', '_', 'W', 0,
+ /* 23451 */ 'F', 'C', 'U', 'L', 'T', '_', 'W', 0,
+ /* 23459 */ 'F', 'S', 'U', 'L', 'T', '_', 'W', 0,
+ /* 23467 */ 'P', 'C', 'N', 'T', '_', 'W', 0,
+ /* 23474 */ 'F', 'R', 'I', 'N', 'T', '_', 'W', 0,
+ /* 23482 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', 0,
+ /* 23491 */ 'F', 'S', 'Q', 'R', 'T', '_', 'W', 0,
+ /* 23499 */ 'F', 'R', 'S', 'Q', 'R', 'T', '_', 'W', 0,
+ /* 23508 */ 'S', 'T', '_', 'W', 0,
+ /* 23513 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'W', 0,
+ /* 23522 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'W', 0,
+ /* 23531 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'W', 0,
+ /* 23541 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'W', 0,
+ /* 23552 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'W', 0,
+ /* 23561 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'W', 0,
+ /* 23571 */ 'M', 'O', 'D', '_', 'U', '_', 'W', 0,
+ /* 23579 */ 'C', 'L', 'E', '_', 'U', '_', 'W', 0,
+ /* 23587 */ 'A', 'V', 'E', '_', 'U', '_', 'W', 0,
+ /* 23595 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'W', 0,
+ /* 23604 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'W', 0,
+ /* 23613 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'W', 0,
+ /* 23622 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'W', 0,
+ /* 23631 */ 'M', 'I', 'N', '_', 'U', '_', 'W', 0,
+ /* 23639 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'W', 0,
+ /* 23648 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'W', 0,
+ /* 23657 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'W', 0,
+ /* 23666 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'W', 0,
+ /* 23675 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'W', 0,
+ /* 23686 */ 'S', 'A', 'T', '_', 'U', '_', 'W', 0,
+ /* 23694 */ 'C', 'L', 'T', '_', 'U', '_', 'W', 0,
+ /* 23702 */ 'F', 'F', 'I', 'N', 'T', '_', 'U', '_', 'W', 0,
+ /* 23712 */ 'F', 'T', 'I', 'N', 'T', '_', 'U', '_', 'W', 0,
+ /* 23722 */ 'D', 'I', 'V', '_', 'U', '_', 'W', 0,
+ /* 23730 */ 'M', 'A', 'X', '_', 'U', '_', 'W', 0,
+ /* 23738 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'W', 0,
+ /* 23747 */ 'M', 'S', 'U', 'B', 'V', '_', 'W', 0,
+ /* 23755 */ 'M', 'A', 'D', 'D', 'V', '_', 'W', 0,
+ /* 23763 */ 'P', 'C', 'K', 'E', 'V', '_', 'W', 0,
+ /* 23771 */ 'I', 'L', 'V', 'E', 'V', '_', 'W', 0,
+ /* 23779 */ 'F', 'D', 'I', 'V', '_', 'W', 0,
+ /* 23786 */ 'M', 'U', 'L', 'V', '_', 'W', 0,
+ /* 23793 */ 'E', 'X', 'T', 'R', 'V', '_', 'W', 0,
+ /* 23801 */ 'F', 'M', 'A', 'X', '_', 'W', 0,
+ /* 23808 */ 'B', 'Z', '_', 'W', 0,
+ /* 23813 */ 'B', 'N', 'Z', '_', 'W', 0,
+ /* 23819 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
+ /* 23836 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
+ /* 23852 */ 'M', 'F', 'T', 'A', 'C', 'X', 0,
+ /* 23859 */ 'M', 'T', 'T', 'A', 'C', 'X', 0,
+ /* 23866 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
+ /* 23880 */ 'L', 'H', 'X', 0,
+ /* 23884 */ 'J', 'A', 'L', 'X', 0,
+ /* 23889 */ 'L', 'B', 'U', 'X', 0,
+ /* 23894 */ 'L', 'W', 'X', 0,
+ /* 23898 */ 'C', 'O', 'P', 'Y', 0,
+ /* 23903 */ 'C', 'O', 'N', 'S', 'T', 'P', 'O', 'O', 'L', '_', 'E', 'N', 'T', 'R', 'Y', 0,
+ /* 23919 */ 'B', 'G', 'E', 'Z', 0,
+ /* 23924 */ 'B', 'L', 'E', 'Z', 0,
+ /* 23929 */ 'B', 'C', '1', 'N', 'E', 'Z', 0,
+ /* 23936 */ 'B', 'C', '2', 'N', 'E', 'Z', 0,
+ /* 23943 */ 'S', 'E', 'L', 'N', 'E', 'Z', 0,
+ /* 23950 */ 'D', 'C', 'L', 'Z', 0,
+ /* 23955 */ 'B', 'C', '1', 'E', 'Q', 'Z', 0,
+ /* 23962 */ 'B', 'C', '2', 'E', 'Q', 'Z', 0,
+ /* 23969 */ 'S', 'E', 'L', 'E', 'Q', 'Z', 0,
+ /* 23976 */ 'B', 'G', 'T', 'Z', 0,
+ /* 23981 */ 'B', 'L', 'T', 'Z', 0,
+ /* 23986 */ 'S', 'e', 'l', 'B', 'n', 'e', 'Z', 0,
+ /* 23994 */ 'S', 'e', 'l', 'B', 'e', 'q', 'Z', 0,
+ /* 24002 */ 'J', 'a', 'l', 'O', 'n', 'e', 'R', 'e', 'g', 0,
+ /* 24012 */ 'J', 'a', 'l', 'T', 'w', 'o', 'R', 'e', 'g', 0,
+ /* 24022 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', 0,
+ /* 24049 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', 0,
+ /* 24070 */ 'U', 'l', 'h', 0,
+ /* 24074 */ 'U', 's', 'h', 0,
+ /* 24078 */ 'D', 'A', 'D', 'D', 'i', 0,
+ /* 24084 */ 'A', 'N', 'D', 'i', 0,
+ /* 24089 */ 'S', 'N', 'E', 'i', 0,
+ /* 24094 */ 'S', 'E', 'Q', 'i', 0,
+ /* 24099 */ 'X', 'O', 'R', 'i', 0,
+ /* 24104 */ 'S', 'L', 'T', 'i', 0,
+ /* 24109 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', 0,
+ /* 24125 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 'i', 0,
+ /* 24139 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 'i', 0,
+ /* 24153 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 0,
+ /* 24167 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 0,
+ /* 24181 */ 'D', 'R', 'O', 'L', 'I', 'm', 'm', 0,
+ /* 24189 */ 'N', 'O', 'R', 'I', 'm', 'm', 0,
+ /* 24196 */ 'D', 'R', 'O', 'R', 'I', 'm', 'm', 0,
+ /* 24204 */ 'B', 'n', 'e', 'I', 'm', 'm', 0,
+ /* 24211 */ 'B', 'e', 'q', 'I', 'm', 'm', 0,
+ /* 24218 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', 0,
+ /* 24231 */ 'J', 'A', 'L', 'R', 'H', 'B', '6', '4', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 24246 */ 'J', 'A', 'L', 'R', '6', '4', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 24259 */ 'J', 'A', 'L', 'R', 'H', 'B', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 24272 */ 'J', 'A', 'L', 'R', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 24283 */ 'B', '_', 'M', 'M', 'R', '6', '_', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 24297 */ 'B', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 24309 */ 'S', 'D', 'I', 'V', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 24324 */ 'U', 'D', 'I', 'V', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 24339 */ 'L', 'D', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24347 */ 'S', 'D', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24355 */ 'S', 'E', 'Q', 'I', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24365 */ 'D', 'S', 'R', 'e', 'm', 'I', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24377 */ 'D', 'U', 'R', 'e', 'm', 'I', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24389 */ 'D', 'S', 'D', 'i', 'v', 'I', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24401 */ 'D', 'U', 'D', 'i', 'v', 'I', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24413 */ 'D', 'M', 'U', 'L', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24423 */ 'D', 'M', 'U', 'L', 'O', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24434 */ 'S', 'E', 'Q', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24443 */ 'A', 'B', 'S', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24452 */ 'D', 'M', 'U', 'L', 'O', 'U', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24464 */ 'D', 'S', 'R', 'e', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24475 */ 'D', 'U', 'R', 'e', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24486 */ 'B', 'G', 'E', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24498 */ 'B', 'L', 'E', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24510 */ 'B', 'G', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24523 */ 'B', 'L', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24536 */ 'B', 'N', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24549 */ 'B', 'E', 'Q', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24562 */ 'B', 'G', 'T', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24575 */ 'B', 'L', 'T', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24588 */ 'B', 'G', 'E', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24602 */ 'B', 'L', 'E', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24616 */ 'D', 'M', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24629 */ 'B', 'G', 'T', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24643 */ 'B', 'L', 'T', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24657 */ 'B', 'G', 'T', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24669 */ 'B', 'L', 'T', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24681 */ 'B', 'G', 'E', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24694 */ 'B', 'L', 'E', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24707 */ 'B', 'G', 'T', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24720 */ 'B', 'L', 'T', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24733 */ 'D', 'S', 'D', 'i', 'v', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24744 */ 'D', 'U', 'D', 'i', 'v', 'M', 'a', 'c', 'r', 'o', 0,
+ /* 24755 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 0,
+ /* 24768 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 0,
+ /* 24781 */ 'E', 'R', 'e', 't', 0,
+ /* 24786 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 0,
+ /* 24799 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 0,
+ /* 24812 */ 'L', 'B', 'u', 0,
+ /* 24816 */ 'D', 'S', 'U', 'B', 'u', 0,
+ /* 24822 */ 'B', 'A', 'D', 'D', 'u', 0,
+ /* 24828 */ 'D', 'A', 'D', 'D', 'u', 0,
+ /* 24834 */ 'L', 'H', 'u', 0,
+ /* 24838 */ 'S', 'L', 'T', 'u', 0,
+ /* 24843 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'M', 'U', 'L', 'T', 'u', 0,
+ /* 24856 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', 'u', 0,
+ /* 24868 */ 'L', 'W', 'u', 0,
+ /* 24872 */ 'U', 'l', 'h', 'u', 0,
+ /* 24877 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'D', 'A', 'D', 'D', 'i', 'u', 0,
+ /* 24896 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', 0,
+ /* 24906 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'A', 'D', 'D', 'i', 'u', 0,
+ /* 24924 */ 'S', 'L', 'T', 'i', 'u', 0,
+ /* 24930 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 'u', 0,
+ /* 24945 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 'u', 0,
+ /* 24960 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'u', 0,
+ /* 24974 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'u', 0,
+ /* 24988 */ 'U', 'l', 'w', 0,
+ /* 24992 */ 'U', 's', 'w', 0,
+};
+
+extern const unsigned MipsInstrNameIndices[] = {
+ 13639U, 18960U, 19055U, 13963U, 13944U, 13972U, 14209U, 12038U,
+ 12053U, 11932U, 12079U, 20856U, 11882U, 13953U, 11738U, 23898U,
+ 11802U, 21851U, 10300U, 19993U, 14181U, 21819U, 10327U, 21808U,
+ 11835U, 20117U, 20104U, 20498U, 21654U, 21677U, 14113U, 14160U,
+ 14133U, 14004U, 10209U, 9148U, 14274U, 22097U, 22127U, 14361U,
+ 14368U, 10263U, 20685U, 20663U, 11930U, 13637U, 23866U, 11892U,
+ 21616U, 20814U, 21866U, 20831U, 21830U, 20764U, 21875U, 10167U,
+ 10145U, 10156U, 11858U, 20873U, 12093U, 12110U, 10215U, 9154U,
+ 10269U, 10246U, 20690U, 20669U, 23836U, 19013U, 23819U, 18996U,
+ 10313U, 21635U, 9920U, 20903U, 21928U, 10008U, 21797U, 21785U,
+ 21841U, 12134U, 21921U, 21937U, 14082U, 20622U, 20615U, 20086U,
+ 20079U, 21626U, 11755U, 11730U, 19096U, 19088U, 19985U, 19977U,
+ 12179U, 12171U, 10191U, 9130U, 14267U, 7833U, 22078U, 14354U,
+ 22279U, 20375U, 1082U, 12127U, 1064U, 11967U, 21913U, 9998U,
+ 13665U, 13689U, 20048U, 20057U, 20807U, 20042U, 13837U, 20465U,
+ 21726U, 21705U, 20646U, 20007U, 21885U, 20477U, 24443U, 19071U,
+ 20352U, 19440U, 19524U, 19740U, 3553U, 8431U, 802U, 8007U,
+ 2901U, 8219U, 7746U, 8638U, 3476U, 8326U, 725U, 7902U,
+ 2772U, 8114U, 7673U, 8537U, 3517U, 8381U, 766U, 7957U,
+ 2813U, 8169U, 7712U, 8590U, 3496U, 8353U, 745U, 7929U,
+ 2792U, 8141U, 7692U, 8563U, 3593U, 8485U, 842U, 8061U,
+ 2941U, 8273U, 7784U, 8690U, 3456U, 8299U, 705U, 7875U,
+ 2752U, 8087U, 7654U, 8511U, 3573U, 8458U, 822U, 8034U,
+ 2921U, 8246U, 7765U, 8664U, 3537U, 8408U, 786U, 7984U,
+ 2885U, 8196U, 7731U, 8616U, 8745U, 20470U, 17562U, 24549U,
+ 11776U, 24486U, 13989U, 24510U, 21974U, 24681U, 14250U, 24588U,
+ 21668U, 24657U, 14240U, 24562U, 22033U, 24707U, 14280U, 24629U,
+ 11798U, 24498U, 13994U, 24523U, 21984U, 24694U, 14256U, 24602U,
+ 21701U, 24669U, 14245U, 24575U, 22038U, 24720U, 14286U, 24643U,
+ 24536U, 19138U, 19426U, 19319U, 19619U, 19510U, 19726U, 15794U,
+ 24283U, 24297U, 24211U, 24204U, 4116U, 3663U, 4144U, 3693U,
+ 4174U, 4205U, 4102U, 3648U, 4130U, 3678U, 4158U, 4190U,
+ 2630U, 3156U, 113U, 23903U, 19366U, 19666U, 131U, 1021U,
+ 24616U, 24413U, 24423U, 24452U, 14219U, 24181U, 20641U, 24196U,
+ 24389U, 24733U, 24365U, 24464U, 24401U, 24744U, 24377U, 24475U,
+ 24781U, 2643U, 3172U, 11018U, 23072U, 19104U, 19121U, 19334U,
+ 19634U, 4263U, 19154U, 19810U, 19201U, 19853U, 19349U, 19177U,
+ 19831U, 19649U, 19247U, 19895U, 19224U, 19874U, 19271U, 19917U,
+ 24246U, 24231U, 24259U, 24272U, 24002U, 24012U, 24339U, 3442U,
+ 7629U, 1921U, 20129U, 20214U, 24906U, 24877U, 24109U, 17112U,
+ 989U, 3333U, 956U, 3202U, 979U, 3323U, 20529U, 936U,
+ 20719U, 20546U, 20736U, 1019U, 23852U, 34U, 119U, 20170U,
+ 20705U, 94U, 13643U, 19960U, 1003U, 3362U, 19381U, 19681U,
+ 19404U, 19704U, 23859U, 46U, 137U, 20177U, 20712U, 101U,
+ 13654U, 19971U, 24617U, 24424U, 24453U, 4523U, 4656U, 4555U,
+ 4708U, 20095U, 24189U, 3295U, 19455U, 19539U, 19755U, 19456U,
+ 19540U, 19756U, 8925U, 8827U, 9040U, 12341U, 12236U, 12501U,
+ 22289U, 14324U, 22321U, 14340U, 23362U, 21754U, 24843U, 22085U,
+ 22115U, 24049U, 3245U, 4768U, 7606U, 18828U, 7400U, 24022U,
+ 3216U, 4738U, 7578U, 10198U, 21956U, 13613U, 2691U, 19943U,
+ 3024U, 9137U, 21944U, 13624U, 2704U, 20254U, 21766U, 24856U,
+ 12270U, 8862U, 24218U, 3347U, 22104U, 362U, 2239U, 13746U,
+ 2842U, 21147U, 594U, 2528U, 13805U, 2986U, 21501U, 509U,
+ 2443U, 13783U, 2960U, 21385U, 11670U, 633U, 21534U, 22134U,
+ 14220U, 24182U, 20642U, 24197U, 8715U, 3427U, 24309U, 24347U,
+ 24390U, 24734U, 24355U, 24434U, 3304U, 3313U, 19294U, 19485U,
+ 19569U, 19594U, 19785U, 24366U, 24465U, 7641U, 1932U, 20143U,
+ 20229U, 3449U, 17119U, 19307U, 19498U, 19582U, 19607U, 19798U,
+ 23994U, 23986U, 24768U, 24139U, 24799U, 24167U, 24945U, 24974U,
+ 24755U, 24125U, 24786U, 24153U, 24930U, 24960U, 4468U, 3927U,
+ 3942U, 4480U, 4695U, 14088U, 11992U, 11974U, 12008U, 12024U,
+ 12067U, 2661U, 8763U, 1877U, 16325U, 6253U, 17043U, 6376U,
+ 20002U, 17158U, 24324U, 24402U, 24745U, 24378U, 24476U, 24070U,
+ 24872U, 24988U, 24074U, 24992U, 19470U, 19554U, 19770U, 12460U,
+ 16581U, 8985U, 1230U, 23290U, 18703U, 10187U, 10039U, 16073U,
+ 5454U, 17238U, 15038U, 15439U, 17410U, 7286U, 12261U, 1333U,
+ 12378U, 1388U, 23033U, 1746U, 22607U, 1718U, 12333U, 16477U,
+ 12440U, 16568U, 23272U, 18691U, 10063U, 16084U, 9192U, 10400U,
+ 12740U, 22360U, 9600U, 11187U, 13229U, 23317U, 9792U, 11552U,
+ 13478U, 23666U, 15656U, 5194U, 8853U, 1135U, 8963U, 1198U,
+ 7256U, 12525U, 1476U, 9065U, 15980U, 12480U, 1448U, 9005U,
+ 15927U, 9406U, 10764U, 12925U, 22725U, 9862U, 11633U, 13548U,
+ 23756U, 10096U, 16093U, 9176U, 10383U, 12724U, 22343U, 16121U,
+ 5676U, 24079U, 18852U, 24890U, 18942U, 24823U, 18906U, 18983U,
+ 6434U, 10032U, 5442U, 10259U, 15467U, 5035U, 2055U, 15494U,
+ 5068U, 9281U, 6308U, 16128U, 5685U, 22205U, 24084U, 3268U,
+ 18860U, 10293U, 1290U, 9505U, 11034U, 13078U, 23119U, 9697U,
+ 11399U, 13336U, 23513U, 13685U, 10026U, 5431U, 6336U, 9582U,
+ 11169U, 13202U, 23299U, 9774U, 11534U, 13460U, 23648U, 9530U,
+ 11108U, 13141U, 23193U, 9722U, 11473U, 13399U, 23587U, 3995U,
+ 3871U, 4379U, 4023U, 3820U, 4319U, 3887U, 4682U, 4621U,
+ 15451U, 24822U, 13848U, 9932U, 5310U, 18982U, 1651U, 67U,
+ 205U, 199U, 213U, 9903U, 4975U, 23955U, 5617U, 11925U,
+ 14024U, 16297U, 23929U, 5580U, 21611U, 14234U, 18215U, 23962U,
+ 5630U, 23936U, 5593U, 9342U, 10714U, 12875U, 22675U, 9476U,
+ 10959U, 13049U, 22948U, 5273U, 20382U, 3044U, 10058U, 1972U,
+ 5477U, 14224U, 15701U, 9967U, 5370U, 10120U, 5022U, 2031U,
+ 16111U, 5643U, 17459U, 9906U, 1944U, 5281U, 10074U, 1991U,
+ 5516U, 23919U, 3110U, 13856U, 9943U, 5331U, 14193U, 17731U,
+ 16878U, 10102U, 2007U, 5558U, 14300U, 18789U, 23976U, 3142U,
+ 9975U, 5383U, 10126U, 2039U, 5654U, 14312U, 18812U, 9318U,
+ 10690U, 12851U, 22651U, 9448U, 10813U, 12952U, 22768U, 9372U,
+ 10730U, 12891U, 22691U, 9490U, 11003U, 13063U, 22992U, 22066U,
+ 18336U, 20016U, 6454U, 23924U, 3117U, 9951U, 5344U, 10108U,
+ 2015U, 5569U, 14306U, 18797U, 10069U, 1984U, 5506U, 10080U,
+ 1999U, 5527U, 23981U, 3149U, 13863U, 9983U, 5396U, 14201U,
+ 17742U, 16888U, 10132U, 2047U, 5665U, 14318U, 18820U, 9421U,
+ 22254U, 9414U, 22242U, 11823U, 2624U, 9911U, 1951U, 5291U,
+ 9288U, 10668U, 12829U, 22629U, 9260U, 10647U, 12808U, 22533U,
+ 13999U, 15691U, 9959U, 5357U, 10114U, 5009U, 2023U, 16102U,
+ 5606U, 16228U, 10086U, 5538U, 9897U, 11707U, 13583U, 22248U,
+ 23813U, 10091U, 5548U, 696U, 1810U, 14980U, 13826U, 15522U,
+ 5090U, 16862U, 6365U, 9296U, 22218U, 9390U, 10748U, 12909U,
+ 22709U, 9669U, 11276U, 13308U, 23430U, 9892U, 11693U, 13578U,
+ 22237U, 23808U, 4406U, 4052U, 4418U, 4065U, 4394U, 4039U,
+ 4305U, 4730U, 4229U, 4722U, 4220U, 11784U, 11763U, 16156U,
+ 16182U, 6208U, 7522U, 2334U, 5883U, 21240U, 6834U, 663U,
+ 2591U, 6140U, 18529U, 21560U, 18179U, 7115U, 9327U, 10699U,
+ 12860U, 22660U, 9463U, 10883U, 12975U, 22851U, 83U, 14429U,
+ 15022U, 8726U, 20846U, 883U, 916U, 970U, 11026U, 6025U,
+ 21377U, 6976U, 9538U, 11116U, 13149U, 23201U, 9730U, 11481U,
+ 13407U, 23595U, 9522U, 11100U, 13133U, 23185U, 9714U, 11465U,
+ 13391U, 23579U, 19939U, 17126U, 6445U, 7554U, 9556U, 11134U,
+ 13167U, 23219U, 9748U, 11499U, 13425U, 23613U, 9617U, 11204U,
+ 13246U, 23334U, 9820U, 11580U, 13506U, 23694U, 23951U, 18805U,
+ 7379U, 7571U, 8900U, 1149U, 8802U, 1103U, 9015U, 1245U,
+ 8913U, 15885U, 8815U, 15812U, 9028U, 15940U, 8931U, 15900U,
+ 8833U, 15827U, 9046U, 15955U, 5802U, 6729U, 10943U, 6011U,
+ 12347U, 16488U, 21361U, 6962U, 10639U, 21166U, 10545U, 5773U,
+ 12242U, 16407U, 21092U, 6700U, 11344U, 6084U, 12507U, 16608U,
+ 21462U, 7035U, 10606U, 5787U, 21101U, 6714U, 10896U, 5965U,
+ 21315U, 6916U, 10498U, 5727U, 21046U, 6654U, 11297U, 6038U,
+ 21416U, 6989U, 10922U, 5980U, 21325U, 6931U, 10524U, 5742U,
+ 21056U, 6669U, 11323U, 6053U, 21426U, 7004U, 10856U, 5936U,
+ 21273U, 6887U, 10933U, 5996U, 21344U, 6947U, 10535U, 5758U,
+ 21075U, 6685U, 11334U, 6069U, 21445U, 7020U, 10866U, 5951U,
+ 21290U, 6902U, 9652U, 11259U, 13291U, 23413U, 9844U, 13530U,
+ 23738U, 8740U, 8747U, 10174U, 12159U, 22268U, 10138U, 12142U,
+ 22261U, 108U, 14445U, 15030U, 8733U, 20935U, 17777U, 22295U,
+ 18448U, 14330U, 20945U, 17790U, 22327U, 18461U, 6408U, 2357U,
+ 15224U, 5912U, 21259U, 17984U, 6863U, 499U, 14841U, 2433U,
+ 15312U, 14346U, 6421U, 23368U, 18715U, 7354U, 686U, 14967U,
+ 2614U, 15426U, 21579U, 18204U, 7144U, 481U, 14817U, 2415U,
+ 15288U, 21354U, 18038U, 354U, 14678U, 2231U, 15176U, 21141U,
+ 17920U, 327U, 14642U, 2204U, 15152U, 21085U, 17890U, 556U,
+ 14893U, 2490U, 15364U, 21455U, 18091U, 286U, 14589U, 2163U,
+ 15099U, 21021U, 17845U, 296U, 14602U, 2173U, 15112U, 21029U,
+ 17856U, 414U, 14729U, 2291U, 15199U, 21205U, 17963U, 526U,
+ 14854U, 2460U, 15325U, 21400U, 18058U, 307U, 14616U, 2184U,
+ 15126U, 21038U, 17868U, 536U, 14867U, 2470U, 15338U, 21408U,
+ 18069U, 461U, 14791U, 2395U, 15262U, 21307U, 18016U, 336U,
+ 14654U, 2213U, 15164U, 21127U, 17900U, 471U, 14804U, 2405U,
+ 15275U, 21336U, 18027U, 317U, 14629U, 2194U, 15139U, 21067U,
+ 17879U, 546U, 14880U, 2480U, 15351U, 21437U, 18080U, 433U,
+ 14754U, 2367U, 15237U, 21283U, 17995U, 4503U, 4342U, 3969U,
+ 10186U, 24078U, 24889U, 24828U, 13608U, 18989U, 13674U, 13684U,
+ 20015U, 19938U, 7553U, 23950U, 7570U, 22073U, 22054U, 21648U,
+ 18223U, 7196U, 21908U, 926U, 18976U, 22048U, 13595U, 20851U,
+ 18970U, 22027U, 22074U, 22055U, 7307U, 7317U, 9636U, 11243U,
+ 13265U, 23387U, 9828U, 11608U, 13514U, 23722U, 16744U, 6310U,
+ 8721U, 7485U, 0U, 88U, 1042U, 19029U, 6U, 10322U,
+ 21968U, 21777U, 40U, 125U, 1048U, 19042U, 27U, 12713U,
+ 21989U, 14262U, 21760U, 24849U, 22015U, 7545U, 11160U, 13193U,
+ 23254U, 11525U, 13451U, 23639U, 11082U, 13115U, 23167U, 11447U,
+ 13373U, 23561U, 12589U, 1533U, 12664U, 1585U, 22790U, 18539U,
+ 12626U, 16657U, 13914U, 16951U, 20443U, 17534U, 12690U, 1621U,
+ 12569U, 1503U, 20099U, 12603U, 1552U, 12677U, 1603U, 22802U,
+ 18554U, 12652U, 16689U, 11052U, 13096U, 23137U, 11417U, 13354U,
+ 23531U, 13925U, 16965U, 20454U, 17548U, 12700U, 1636U, 12617U,
+ 1571U, 20758U, 875U, 22193U, 12149U, 22091U, 10231U, 14214U,
+ 861U, 906U, 22145U, 7870U, 221U, 22060U, 14229U, 868U,
+ 22151U, 9125U, 24816U, 22121U, 20367U, 11848U, 6526U, 4589U,
+ 4567U, 8759U, 15799U, 5225U, 13600U, 16752U, 6318U, 21781U,
+ 21649U, 9991U, 5409U, 18224U, 7197U, 20371U, 11853U, 6535U,
+ 21909U, 20347U, 20035U, 22179U, 18399U, 17183U, 22187U, 18410U,
+ 17437U, 23099U, 18653U, 23062U, 18627U, 13273U, 16722U, 23793U,
+ 18739U, 23089U, 18640U, 23043U, 18602U, 13211U, 16710U, 23000U,
+ 18580U, 20930U, 890U, 18262U, 7228U, 490U, 14829U, 2424U,
+ 15300U, 21370U, 18048U, 10447U, 267U, 14564U, 2144U, 15087U,
+ 21006U, 17824U, 6642U, 22407U, 10592U, 22512U, 10882U, 22850U,
+ 11025U, 23110U, 10484U, 22444U, 11283U, 23437U, 452U, 14779U,
+ 2386U, 897U, 15010U, 10554U, 22474U, 10973U, 22962U, 10906U,
+ 22864U, 10508U, 22458U, 11307U, 23451U, 10568U, 22488U, 10842U,
+ 22821U, 11656U, 615U, 14943U, 2549U, 15402U, 21520U, 18133U,
+ 7061U, 23779U, 12967U, 22835U, 10355U, 22313U, 10791U, 22746U,
+ 10987U, 22976U, 11212U, 23342U, 11588U, 23702U, 10800U, 22755U,
+ 10996U, 22985U, 9429U, 10778U, 12933U, 22733U, 10347U, 22305U,
+ 2345U, 5897U, 21249U, 6848U, 674U, 2602U, 6154U, 18569U,
+ 21569U, 18191U, 7129U, 10454U, 22414U, 10409U, 22369U, 11686U,
+ 23801U, 10391U, 22351U, 10835U, 22814U, 624U, 14955U, 2558U,
+ 15414U, 21527U, 18143U, 7073U, 10425U, 22385U, 10821U, 424U,
+ 14742U, 2301U, 15212U, 21213U, 17974U, 6792U, 22776U, 383U,
+ 14689U, 2260U, 15187U, 21174U, 17929U, 6769U, 13832U, 10875U,
+ 22843U, 11360U, 23474U, 11385U, 23499U, 10599U, 22519U, 10889U,
+ 22857U, 10491U, 22451U, 11290U, 23444U, 10561U, 22481U, 10980U,
+ 22969U, 11377U, 565U, 14905U, 2499U, 15376U, 21478U, 18101U,
+ 23491U, 10418U, 248U, 14539U, 2125U, 15075U, 20991U, 17803U,
+ 6630U, 22378U, 10914U, 22872U, 10516U, 22466U, 11315U, 23459U,
+ 10576U, 22496U, 10849U, 22828U, 11222U, 23352U, 11598U, 23712U,
+ 12981U, 22880U, 11062U, 23147U, 11427U, 23541U, 13698U, 6354U,
+ 21902U, 7217U, 11073U, 13106U, 23158U, 11438U, 13364U, 23552U,
+ 11043U, 13087U, 23128U, 11408U, 13345U, 23522U, 14097U, 17055U,
+ 9877U, 11648U, 13563U, 23771U, 9456U, 10828U, 12960U, 22783U,
+ 9237U, 10476U, 12785U, 22436U, 9498U, 11011U, 13071U, 23007U,
+ 20847U, 9683U, 11368U, 13322U, 23482U, 22200U, 9245U, 10584U,
+ 12793U, 22504U, 18428U, 17753U, 6597U, 13824U, 13852U, 20632U,
+ 15598U, 3055U, 4996U, 5234U, 5487U, 15617U, 17760U, 8783U,
+ 1901U, 17651U, 17723U, 23884U, 18766U, 16871U, 9937U, 1964U,
+ 5320U, 9916U, 1958U, 5301U, 20629U, 15590U, 3050U, 20337U,
+ 15458U, 4985U, 6500U, 8777U, 1893U, 7458U, 7493U, 17645U,
+ 16857U, 4313U, 3435U, 4246U, 4238U, 4452U, 4284U, 8791U,
+ 1911U, 11722U, 16135U, 15637U, 23889U, 18774U, 7237U, 15806U,
+ 5248U, 24812U, 3378U, 11915U, 16281U, 18891U, 10239U, 73U,
+ 1825U, 4937U, 14413U, 1032U, 4855U, 7426U, 1790U, 9275U,
+ 10662U, 12823U, 22623U, 13936U, 10021U, 20490U, 153U, 1839U,
+ 9224U, 10463U, 12772U, 22423U, 24896U, 3397U, 18938U, 12176U,
+ 2681U, 11790U, 16191U, 15666U, 23880U, 18759U, 16355U, 24834U,
+ 3384U, 11920U, 16289U, 18914U, 15514U, 5080U, 14094U, 3007U,
+ 7477U, 10242U, 7515U, 11809U, 16205U, 17049U, 6382U, 7539U,
+ 8722U, 5216U, 7486U, 6345U, 165U, 1855U, 14477U, 24121U,
+ 3289U, 18884U, 22276U, 15675U, 3100U, 143U, 14461U, 1054U,
+ 4917U, 7442U, 1800U, 20184U, 17269U, 11907U, 16267U, 17211U,
+ 14292U, 3012U, 11813U, 16212U, 17098U, 15551U, 5125U, 14992U,
+ 10053U, 5467U, 17445U, 20799U, 3082U, 11866U, 16242U, 17709U,
+ 17421U, 10047U, 18321U, 23894U, 177U, 14495U, 17769U, 18782U,
+ 18436U, 7338U, 24868U, 3722U, 3786U, 3754U, 3803U, 4332U,
+ 4073U, 3958U, 4432U, 4089U, 3839U, 3901U, 10204U, 10624U,
+ 5829U, 21119U, 6756U, 13023U, 22922U, 21962U, 20317U, 17384U,
+ 18278U, 9861U, 11632U, 13547U, 23755U, 277U, 14577U, 2154U,
+ 20205U, 17299U, 16120U, 12996U, 22895U, 21014U, 17835U, 14030U,
+ 16979U, 20563U, 17581U, 14056U, 17011U, 20589U, 17613U, 10376U,
+ 5715U, 20984U, 6618U, 9565U, 11143U, 13176U, 23228U, 9757U,
+ 11508U, 13434U, 23622U, 9201U, 10410U, 12749U, 22370U, 11687U,
+ 6169U, 21587U, 9644U, 11251U, 13283U, 7157U, 23405U, 9836U,
+ 11616U, 13522U, 23730U, 1U, 4793U, 89U, 2061U, 14437U,
+ 4835U, 1043U, 4875U, 7U, 14375U, 4803U, 228U, 14513U,
+ 2070U, 15049U, 4885U, 13U, 14384U, 13619U, 15504U, 2697U,
+ 20245U, 17311U, 16766U, 19949U, 15569U, 3030U, 20280U, 17335U,
+ 17133U, 20753U, 10363U, 5703U, 20977U, 6606U, 9547U, 11125U,
+ 13158U, 23210U, 9739U, 11490U, 13416U, 23604U, 9184U, 10392U,
+ 12732U, 22352U, 10836U, 5925U, 21267U, 9574U, 11152U, 13185U,
+ 6876U, 23246U, 9766U, 11517U, 13443U, 23631U, 10323U, 9123U,
+ 16047U, 21969U, 7266U, 5694U, 9514U, 11092U, 13125U, 23177U,
+ 9706U, 11457U, 13383U, 23571U, 15476U, 5046U, 17193U, 6478U,
+ 22211U, 345U, 14666U, 2222U, 13739U, 2833U, 16817U, 21134U,
+ 17910U, 2099U, 13717U, 2726U, 20955U, 392U, 14701U, 2269U,
+ 13765U, 2863U, 16827U, 21181U, 17939U, 585U, 14931U, 2519U,
+ 13798U, 2977U, 16837U, 21494U, 18123U, 2112U, 13728U, 2739U,
+ 20966U, 403U, 14715U, 2280U, 13774U, 2874U, 16847U, 21190U,
+ 17951U, 9143U, 10616U, 5816U, 21111U, 6743U, 13013U, 22912U,
+ 21950U, 20307U, 17371U, 18269U, 9853U, 11624U, 13539U, 23747U,
+ 258U, 14552U, 2135U, 20196U, 17287U, 16057U, 12987U, 22886U,
+ 20999U, 17814U, 41U, 4825U, 126U, 2090U, 14453U, 4845U,
+ 1049U, 4907U, 28U, 14404U, 4814U, 238U, 14526U, 2080U,
+ 15062U, 4896U, 20U, 14394U, 13649U, 2719U, 20271U, 17323U,
+ 16774U, 20072U, 17219U, 19966U, 3037U, 20289U, 17347U, 17150U,
+ 57U, 189U, 1072U, 62U, 194U, 1077U, 20775U, 12714U,
+ 21990U, 7276U, 6288U, 14263U, 14068U, 17026U, 20601U, 17628U,
+ 13870U, 16898U, 20399U, 17481U, 12400U, 16528U, 23079U, 1761U,
+ 12450U, 1418U, 23281U, 1776U, 13033U, 22932U, 12638U, 16672U,
+ 12578U, 1517U, 21761U, 20327U, 17397U, 20298U, 17359U, 18254U,
+ 24850U, 18929U, 22010U, 7297U, 9885U, 11663U, 13571U, 23786U,
+ 17091U, 6399U, 12318U, 1360U, 13005U, 22904U, 7546U, 12421U,
+ 1404U, 4298U, 4425U, 3612U, 3417U, 9209U, 10433U, 12757U,
+ 22393U, 9216U, 10440U, 12764U, 22400U, 276U, 14576U, 2153U,
+ 21013U, 17834U, 257U, 14551U, 2134U, 20998U, 17813U, 20637U,
+ 3062U, 9358U, 17659U, 6544U, 22225U, 15628U, 5171U, 4493U,
+ 4534U, 20638U, 15609U, 5161U, 3063U, 9359U, 6327U, 17660U,
+ 6545U, 22226U, 24100U, 3276U, 18869U, 4633U, 12308U, 16453U,
+ 11876U, 16258U, 6219U, 9869U, 11640U, 13555U, 23763U, 9229U,
+ 10468U, 12777U, 22428U, 9676U, 11353U, 13315U, 23467U, 12276U,
+ 16420U, 8868U, 15841U, 20100U, 13899U, 7817U, 15729U, 16933U,
+ 20428U, 7854U, 15766U, 17516U, 14043U, 16995U, 20576U, 17597U,
+ 13885U, 7802U, 15711U, 16916U, 20414U, 7839U, 15748U, 17499U,
+ 12220U, 16388U, 22555U, 18496U, 12195U, 16372U, 22584U, 18511U,
+ 12208U, 1302U, 22540U, 1663U, 22567U, 1683U, 11945U, 11770U,
+ 16166U, 18750U, 16305U, 6230U, 7531U, 10285U, 1277U, 9109U,
+ 16027U, 20158U, 17251U, 20793U, 3074U, 17700U, 6586U, 6562U,
+ 442U, 14766U, 2376U, 15249U, 21299U, 18005U, 12551U, 16645U,
+ 9091U, 16003U, 12292U, 16442U, 8884U, 15863U, 11361U, 6098U,
+ 21471U, 7049U, 20759U, 22194U, 18419U, 17673U, 2322U, 5868U,
+ 21230U, 6819U, 651U, 2579U, 6125U, 18485U, 21550U, 18166U,
+ 7100U, 575U, 14918U, 2509U, 15389U, 21486U, 18112U, 4253U,
+ 3629U, 9609U, 11196U, 13238U, 23326U, 9812U, 11572U, 13498U,
+ 23686U, 9120U, 15450U, 4965U, 1916U, 11726U, 16142U, 16041U,
+ 5256U, 10066U, 1979U, 7469U, 10182U, 7508U, 11751U, 16149U,
+ 16087U, 5498U, 7502U, 10344U, 20024U, 15579U, 5147U, 17166U,
+ 6467U, 7561U, 78U, 1832U, 4951U, 14421U, 1037U, 4865U,
+ 7434U, 1795U, 22092U, 18346U, 13940U, 20494U, 159U, 1847U,
+ 8755U, 1871U, 15792U, 12167U, 2675U, 16348U, 23969U, 3133U,
+ 11713U, 6194U, 7388U, 21602U, 7182U, 23943U, 3124U, 11698U,
+ 6180U, 7367U, 21593U, 7168U, 10772U, 5842U, 21199U, 6781U,
+ 20386U, 24094U, 12710U, 15486U, 5058U, 2686U, 11794U, 16198U,
+ 9254U, 12802U, 22527U, 19954U, 22172U, 18389U, 17141U, 12542U,
+ 16633U, 9082U, 15991U, 12490U, 16594U, 23395U, 18726U, 12284U,
+ 16431U, 8876U, 15852U, 12411U, 16542U, 23237U, 18667U, 12533U,
+ 16621U, 9073U, 1263U, 12389U, 16514U, 8974U, 1214U, 23052U,
+ 18614U, 12187U, 16361U, 8794U, 1090U, 12357U, 16501U, 8942U,
+ 1167U, 23014U, 18590U, 12560U, 1489U, 9100U, 16015U, 12300U,
+ 1347U, 8892U, 15874U, 16704U, 6280U, 9274U, 10661U, 12822U,
+ 22622U, 9223U, 10462U, 12771U, 22422U, 14215U, 15533U, 5103U,
+ 907U, 3193U, 9304U, 10676U, 12837U, 22637U, 22146U, 18362U,
+ 9436U, 10785U, 12940U, 17077U, 6390U, 22740U, 21746U, 3094U,
+ 18240U, 24104U, 3282U, 18876U, 24924U, 3409U, 18951U, 24838U,
+ 3390U, 18921U, 11827U, 24089U, 9381U, 10739U, 12900U, 22700U,
+ 9661U, 11268U, 13300U, 23422U, 7871U, 9267U, 10654U, 12815U,
+ 22615U, 9334U, 10706U, 12867U, 22667U, 9469U, 10952U, 13042U,
+ 22941U, 22061U, 18328U, 9170U, 10370U, 12718U, 15785U, 22337U,
+ 14230U, 15542U, 5114U, 9311U, 10683U, 12844U, 22644U, 9350U,
+ 10722U, 12883U, 22683U, 9483U, 10966U, 13056U, 22955U, 22152U,
+ 18370U, 9442U, 10807U, 12946U, 17084U, 22762U, 20093U, 17229U,
+ 6489U, 9692U, 11394U, 13331U, 23508U, 9126U, 12252U, 1319U,
+ 12367U, 1372U, 23023U, 1731U, 22599U, 1705U, 12325U, 16466U,
+ 12430U, 16555U, 23263U, 18679U, 9801U, 11561U, 13487U, 23675U,
+ 9625U, 11232U, 13254U, 23376U, 9591U, 11178U, 13220U, 23308U,
+ 9783U, 11543U, 13469U, 23657U, 15646U, 5182U, 8844U, 1121U,
+ 8952U, 1182U, 7246U, 12517U, 1463U, 9057U, 15969U, 12470U,
+ 1433U, 8995U, 15914U, 9398U, 10756U, 12917U, 22717U, 9854U,
+ 11625U, 13540U, 23748U, 16050U, 5264U, 24817U, 18898U, 171U,
+ 1863U, 14486U, 22286U, 15683U, 5206U, 3105U, 148U, 14469U,
+ 1059U, 4927U, 7450U, 1805U, 20190U, 17278U, 11911U, 16274U,
+ 14296U, 3018U, 11818U, 16220U, 17105U, 15560U, 5136U, 15001U,
+ 17452U, 20803U, 3088U, 11871U, 16250U, 17716U, 17429U, 6516U,
+ 183U, 14504U, 18442U, 7346U, 10016U, 13589U, 16735U, 6297U,
+ 16065U, 5421U, 14105U, 17066U, 4277U, 3640U, 3738U, 4444U,
+ 4460U, 3770U, 3708U, 4599U, 4513U, 4354U, 3982U, 4366U,
+ 4009U, 4544U, 3622U, 4578U, 3715U, 4610U, 4669U, 3855U,
+ 3914U, 20390U, 13660U, 16782U, 17466U, 11780U, 13598U, 21995U,
+ 18295U, 16750U, 21979U, 18287U, 16175U, 22164U, 11958U, 16313U,
+ 18378U, 20066U, 17202U, 20523U, 17572U, 13710U, 16807U, 20786U,
+ 17690U, 22157U, 11950U, 6240U, 7326U, 20030U, 17175U, 20394U,
+ 17473U, 13704U, 16798U, 20780U, 17681U, 21750U, 13679U, 18304U,
+ 16790U, 22043U, 18313U, 18247U, 11831U, 13603U, 16758U, 16235U,
+ 2310U, 5853U, 21220U, 6804U, 639U, 2567U, 6110U, 18474U,
+ 21540U, 18153U, 7085U, 22001U, 22122U, 18354U, 22008U, 52U,
+ 22021U, 9253U, 10632U, 12801U, 22526U, 21672U, 18232U, 7207U,
+ 20164U, 17260U, 6574U, 12154U, 16340U, 6270U, 20665U, 15608U,
+ 5160U, 3068U, 9365U, 6326U, 17666U, 6553U, 22231U, 24099U,
+ 3275U, 18868U, 4644U, 10236U,
+};
+
+static inline void InitMipsMCInstrInfo(MCInstrInfo *II) {
+ II->InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, 2628);
+}
+
+} // end llvm namespace
+#endif // GET_INSTRINFO_MC_DESC
+
+#ifdef GET_INSTRINFO_HEADER
+#undef GET_INSTRINFO_HEADER
+namespace llvm {
+struct MipsGenInstrInfo : public TargetInstrInfo {
+ explicit MipsGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
+ ~MipsGenInstrInfo() override = default;
+
+};
+} // end llvm namespace
+#endif // GET_INSTRINFO_HEADER
+
+#ifdef GET_INSTRINFO_CTOR_DTOR
+#undef GET_INSTRINFO_CTOR_DTOR
+namespace llvm {
+extern const MCInstrDesc MipsInsts[];
+extern const unsigned MipsInstrNameIndices[];
+extern const char MipsInstrNameData[];
+MipsGenInstrInfo::MipsGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
+ : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
+ InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, 2628);
+}
+} // end llvm namespace
+#endif // GET_INSTRINFO_CTOR_DTOR
+
+#ifdef GET_INSTRINFO_OPERAND_ENUM
+#undef GET_INSTRINFO_OPERAND_ENUM
+namespace llvm {
+namespace Mips {
+namespace OpName {
+enum {
+OPERAND_LAST
+};
+} // end namespace OpName
+} // end namespace Mips
+} // end namespace llvm
+#endif //GET_INSTRINFO_OPERAND_ENUM
+
+#ifdef GET_INSTRINFO_NAMED_OPS
+#undef GET_INSTRINFO_NAMED_OPS
+namespace llvm {
+namespace Mips {
+LLVM_READONLY
+int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
+ return -1;
+}
+} // end namespace Mips
+} // end namespace llvm
+#endif //GET_INSTRINFO_NAMED_OPS
+
+#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
+#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
+namespace llvm {
+namespace Mips {
+namespace OpTypes {
+enum OperandType {
+ InvertedImOperand = 0,
+ InvertedImOperand64 = 1,
+ PtrRC = 2,
+ brtarget = 3,
+ brtarget10_mm = 4,
+ brtarget1SImm16 = 5,
+ brtarget21 = 6,
+ brtarget21_mm = 7,
+ brtarget26 = 8,
+ brtarget26_mm = 9,
+ brtarget7_mm = 10,
+ brtarget_lsl2_mm = 11,
+ brtarget_mm = 12,
+ brtargetr6 = 13,
+ calloffset16 = 14,
+ calltarget = 15,
+ calltarget_mm = 16,
+ condcode = 17,
+ cpinst_operand = 18,
+ f32imm = 19,
+ f64imm = 20,
+ i16imm = 21,
+ i1imm = 22,
+ i32imm = 23,
+ i64imm = 24,
+ i8imm = 25,
+ imm64 = 26,
+ jmpoffset16 = 27,
+ jmptarget = 28,
+ jmptarget_mm = 29,
+ li16_imm = 30,
+ mem = 31,
+ mem16 = 32,
+ mem16_ea = 33,
+ mem16sp = 34,
+ mem_ea = 35,
+ mem_mm_11 = 36,
+ mem_mm_12 = 37,
+ mem_mm_16 = 38,
+ mem_mm_4 = 39,
+ mem_mm_4_lsl1 = 40,
+ mem_mm_4_lsl2 = 41,
+ mem_mm_4sp = 42,
+ mem_mm_9 = 43,
+ mem_mm_gp_simm7_lsl2 = 44,
+ mem_mm_sp_imm5_lsl2 = 45,
+ mem_msa = 46,
+ mem_simm10 = 47,
+ mem_simm10_lsl1 = 48,
+ mem_simm10_lsl2 = 49,
+ mem_simm10_lsl3 = 50,
+ mem_simm11 = 51,
+ mem_simm12 = 52,
+ mem_simm16 = 53,
+ mem_simm9 = 54,
+ mem_simmptr = 55,
+ movep_regpair = 56,
+ pcrel16 = 57,
+ ptype0 = 58,
+ ptype1 = 59,
+ ptype2 = 60,
+ ptype3 = 61,
+ ptype4 = 62,
+ ptype5 = 63,
+ reglist = 64,
+ reglist16 = 65,
+ simm10 = 66,
+ simm10_64 = 67,
+ simm10_lsl1 = 68,
+ simm10_lsl2 = 69,
+ simm10_lsl3 = 70,
+ simm11 = 71,
+ simm12 = 72,
+ simm16 = 73,
+ simm16_64 = 74,
+ simm16_relaxed = 75,
+ simm18_lsl3 = 76,
+ simm19_lsl2 = 77,
+ simm23_lsl2 = 78,
+ simm32 = 79,
+ simm32_relaxed = 80,
+ simm3_lsa2 = 81,
+ simm4 = 82,
+ simm5 = 83,
+ simm6 = 84,
+ simm7_lsl2 = 85,
+ simm9 = 86,
+ simm9_addiusp = 87,
+ size_ins = 88,
+ type0 = 89,
+ type1 = 90,
+ type2 = 91,
+ type3 = 92,
+ type4 = 93,
+ type5 = 94,
+ uimm1 = 95,
+ uimm10 = 96,
+ uimm16 = 97,
+ uimm16_64 = 98,
+ uimm16_64_relaxed = 99,
+ uimm16_altrelaxed = 100,
+ uimm16_relaxed = 101,
+ uimm1_ptr = 102,
+ uimm2 = 103,
+ uimm20 = 104,
+ uimm26 = 105,
+ uimm2_plus1 = 106,
+ uimm2_ptr = 107,
+ uimm3 = 108,
+ uimm32_coerced = 109,
+ uimm3_ptr = 110,
+ uimm3_shift = 111,
+ uimm4 = 112,
+ uimm4_andi = 113,
+ uimm4_ptr = 114,
+ uimm5 = 115,
+ uimm5_64 = 116,
+ uimm5_64_report_uimm6 = 117,
+ uimm5_inssize_plus1 = 118,
+ uimm5_lsl2 = 119,
+ uimm5_plus1 = 120,
+ uimm5_plus1_report_uimm6 = 121,
+ uimm5_plus32 = 122,
+ uimm5_plus32_normalize = 123,
+ uimm5_plus32_normalize_64 = 124,
+ uimm5_plus33 = 125,
+ uimm5_report_uimm6 = 126,
+ uimm6 = 127,
+ uimm6_lsl2 = 128,
+ uimm7 = 129,
+ uimm8 = 130,
+ uimm_range_2_64 = 131,
+ uimmz = 132,
+ vsplat_simm10 = 133,
+ vsplat_simm5 = 134,
+ vsplat_uimm1 = 135,
+ vsplat_uimm2 = 136,
+ vsplat_uimm3 = 137,
+ vsplat_uimm4 = 138,
+ vsplat_uimm5 = 139,
+ vsplat_uimm6 = 140,
+ vsplat_uimm8 = 141,
+ OPERAND_TYPE_LIST_END
+};
+} // end namespace OpTypes
+} // end namespace Mips
+} // end namespace llvm
+#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
+
+#ifdef GET_INSTRMAP_INFO
+#undef GET_INSTRMAP_INFO
+namespace llvm {
+
+namespace Mips {
+
+enum Arch {
+ Arch_dsp,
+ Arch_mmdsp,
+ Arch_mipsr6,
+ Arch_micromipsr6,
+ Arch_se,
+ Arch_micromips
+};
+
+// Dsp2MicroMips
+LLVM_READONLY
+int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) {
+static const uint16_t Dsp2MicroMipsTable[][3] = {
+ { Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM },
+ { Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 },
+ { Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM },
+ { Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 },
+ { Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 },
+ { Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 },
+ { Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 },
+ { Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM },
+ { Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM },
+ { Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM },
+ { Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM },
+ { Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 },
+ { Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 },
+ { Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 },
+ { Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM },
+ { Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 },
+ { Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM },
+ { Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM },
+ { Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 },
+ { Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 },
+ { Mips::BITREV, Mips::BITREV, Mips::BITREV_MM },
+ { Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM },
+ { Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 },
+ { Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 },
+ { Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 },
+ { Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM },
+ { Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM },
+ { Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM },
+ { Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM },
+ { Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM },
+ { Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM },
+ { Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM },
+ { Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM },
+ { Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM },
+ { Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 },
+ { Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 },
+ { Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM },
+ { Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM },
+ { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM },
+ { Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM },
+ { Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 },
+ { Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 },
+ { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 },
+ { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 },
+ { Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM },
+ { Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM },
+ { Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM },
+ { Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM },
+ { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 },
+ { Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 },
+ { Mips::EXTP, Mips::EXTP, Mips::EXTP_MM },
+ { Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM },
+ { Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM },
+ { Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM },
+ { Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM },
+ { Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM },
+ { Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM },
+ { Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM },
+ { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM },
+ { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM },
+ { Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM },
+ { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM },
+ { Mips::INSV, Mips::INSV, Mips::INSV_MM },
+ { Mips::LBUX, Mips::LBUX, Mips::LBUX_MM },
+ { Mips::LHX, Mips::LHX, Mips::LHX_MM },
+ { Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM },
+ { Mips::LWX, Mips::LWX, Mips::LWX_MM },
+ { Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM },
+ { Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM },
+ { Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM },
+ { Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM },
+ { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM },
+ { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM },
+ { Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM },
+ { Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM },
+ { Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM },
+ { Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM },
+ { Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM },
+ { Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM },
+ { Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM },
+ { Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM },
+ { Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM },
+ { Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM },
+ { Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM },
+ { Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM },
+ { Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM },
+ { Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 },
+ { Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 },
+ { Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 },
+ { Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM },
+ { Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 },
+ { Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM },
+ { Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM },
+ { Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 },
+ { Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 },
+ { Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM },
+ { Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM },
+ { Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM },
+ { Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM },
+ { Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM },
+ { Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM },
+ { Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM },
+ { Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM },
+ { Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM },
+ { Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM },
+ { Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM },
+ { Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM },
+ { Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM },
+ { Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM },
+ { Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM },
+ { Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM },
+ { Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM },
+ { Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 },
+ { Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 },
+ { Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 },
+ { Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 },
+ { Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM },
+ { Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM },
+ { Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM },
+ { Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM },
+ { Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM },
+ { Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM },
+ { Mips::SHILO, Mips::SHILO, Mips::SHILO_MM },
+ { Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM },
+ { Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM },
+ { Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM },
+ { Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM },
+ { Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM },
+ { Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM },
+ { Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM },
+ { Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM },
+ { Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM },
+ { Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM },
+ { Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 },
+ { Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM },
+ { Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 },
+ { Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM },
+ { Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM },
+ { Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 },
+ { Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM },
+ { Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 },
+ { Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM },
+ { Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 },
+ { Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM },
+ { Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 },
+ { Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM },
+ { Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 },
+ { Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 },
+ { Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 },
+ { Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 },
+ { Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM },
+ { Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM },
+ { Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM },
+ { Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 },
+ { Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 },
+ { Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 },
+ { Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM },
+ { Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 },
+ { Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM },
+ { Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM },
+}; // End of Dsp2MicroMipsTable
+
+ unsigned mid;
+ unsigned start = 0;
+ unsigned end = 160;
+ while (start < end) {
+ mid = start + (end - start)/2;
+ if (Opcode == Dsp2MicroMipsTable[mid][0]) {
+ break;
+ }
+ if (Opcode < Dsp2MicroMipsTable[mid][0])
+ end = mid;
+ else
+ start = mid + 1;
+ }
+ if (start == end)
+ return -1; // Instruction doesn't exist in this table.
+
+ if (inArch == Arch_dsp)
+ return Dsp2MicroMipsTable[mid][1];
+ if (inArch == Arch_mmdsp)
+ return Dsp2MicroMipsTable[mid][2];
+ return -1;}
+
+// MipsR62MicroMipsR6
+LLVM_READONLY
+int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) {
+static const uint16_t MipsR62MicroMipsR6Table[][3] = {
+ { Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 },
+ { Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 },
+ { Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 },
+ { Mips::AUI, Mips::AUI, Mips::AUI_MMR6 },
+ { Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 },
+ { Mips::BALC, Mips::BALC, Mips::BALC_MMR6 },
+ { Mips::BC, Mips::BC, Mips::BC_MMR6 },
+ { Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 },
+ { Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 },
+ { Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 },
+ { Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 },
+ { Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 },
+ { Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 },
+ { Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 },
+ { Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 },
+ { Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 },
+ { Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 },
+ { Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 },
+ { Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 },
+ { Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 },
+ { Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 },
+ { Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 },
+ { Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 },
+ { Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 },
+ { Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 },
+ { Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 },
+ { Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 },
+ { Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 },
+ { Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 },
+ { Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 },
+ { Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 },
+ { Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 },
+ { Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 },
+ { Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 },
+ { Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 },
+ { Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 },
+ { Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 },
+ { Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 },
+ { Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 },
+ { Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 },
+ { Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 },
+ { Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 },
+ { Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 },
+ { Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 },
+ { Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 },
+ { Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 },
+ { Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 },
+ { Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 },
+ { Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 },
+ { Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 },
+ { Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 },
+ { Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 },
+ { Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 },
+ { Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 },
+ { Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 },
+ { Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 },
+ { Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 },
+ { Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 },
+ { Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 },
+ { Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 },
+ { Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 },
+ { Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 },
+ { Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 },
+ { Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U },
+ { Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U },
+ { Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U },
+ { Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U },
+ { Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U },
+ { Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U },
+ { Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U },
+ { Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U },
+ { Mips::DIV, Mips::DIV, Mips::DIV_MMR6 },
+ { Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 },
+ { Mips::DVP, Mips::DVP, Mips::DVP_MMR6 },
+ { Mips::EVP, Mips::EVP, Mips::EVP_MMR6 },
+ { Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 },
+ { Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 },
+ { Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 },
+ { Mips::JIC, Mips::JIC, Mips::JIC_MMR6 },
+ { Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 },
+ { Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 },
+ { Mips::LWUPC, Mips::LWUPC, (uint16_t)-1U },
+ { Mips::MOD, Mips::MOD, Mips::MOD_MMR6 },
+ { Mips::MODU, Mips::MODU, Mips::MODU_MMR6 },
+ { Mips::MUH, Mips::MUH, Mips::MUH_MMR6 },
+ { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 },
+ { Mips::MULU, Mips::MULU, Mips::MULU_MMR6 },
+ { Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 },
+ { Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 },
+ { Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 },
+ { Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 },
+ { Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 },
+ { Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 },
+ { Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 },
+ { Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 },
+ { Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 },
+ { Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 },
+}; // End of MipsR62MicroMipsR6Table
+
+ unsigned mid;
+ unsigned start = 0;
+ unsigned end = 97;
+ while (start < end) {
+ mid = start + (end - start)/2;
+ if (Opcode == MipsR62MicroMipsR6Table[mid][0]) {
+ break;
+ }
+ if (Opcode < MipsR62MicroMipsR6Table[mid][0])
+ end = mid;
+ else
+ start = mid + 1;
+ }
+ if (start == end)
+ return -1; // Instruction doesn't exist in this table.
+
+ if (inArch == Arch_mipsr6)
+ return MipsR62MicroMipsR6Table[mid][1];
+ if (inArch == Arch_micromipsr6)
+ return MipsR62MicroMipsR6Table[mid][2];
+ return -1;}
+
+// Std2MicroMips
+LLVM_READONLY
+int Std2MicroMips(uint16_t Opcode, enum Arch inArch) {
+static const uint16_t Std2MicroMipsTable[][3] = {
+ { Mips::ADD, Mips::ADD, Mips::ADD_MM },
+ { Mips::ADDi, Mips::ADDi, Mips::ADDi_MM },
+ { Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM },
+ { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM },
+ { Mips::AND, Mips::AND, Mips::AND_MM },
+ { Mips::ANDi, Mips::ANDi, Mips::ANDi_MM },
+ { Mips::BC1F, Mips::BC1F, Mips::BC1F_MM },
+ { Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U },
+ { Mips::BC1T, Mips::BC1T, Mips::BC1T_MM },
+ { Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U },
+ { Mips::BEQ, Mips::BEQ, Mips::BEQ_MM },
+ { Mips::BEQL, Mips::BEQL, (uint16_t)-1U },
+ { Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM },
+ { Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM },
+ { Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U },
+ { Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U },
+ { Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM },
+ { Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U },
+ { Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM },
+ { Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U },
+ { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM },
+ { Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM },
+ { Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U },
+ { Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U },
+ { Mips::BNE, Mips::BNE, Mips::BNE_MM },
+ { Mips::BNEL, Mips::BNEL, (uint16_t)-1U },
+ { Mips::BREAK, Mips::BREAK, Mips::BREAK_MM },
+ { Mips::CACHE, Mips::CACHE, Mips::CACHE_MM },
+ { Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM },
+ { Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM },
+ { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM },
+ { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM },
+ { Mips::CLO, Mips::CLO, Mips::CLO_MM },
+ { Mips::CLZ, Mips::CLZ, Mips::CLZ_MM },
+ { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM },
+ { Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM },
+ { Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM },
+ { Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM },
+ { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM },
+ { Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM },
+ { Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM },
+ { Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM },
+ { Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM },
+ { Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM },
+ { Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM },
+ { Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM },
+ { Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM },
+ { Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM },
+ { Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM },
+ { Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM },
+ { Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM },
+ { Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM },
+ { Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM },
+ { Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM },
+ { Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM },
+ { Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM },
+ { Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM },
+ { Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM },
+ { Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM },
+ { Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM },
+ { Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM },
+ { Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM },
+ { Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM },
+ { Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM },
+ { Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM },
+ { Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM },
+ { Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM },
+ { Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM },
+ { Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM },
+ { Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM },
+ { Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM },
+ { Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM },
+ { Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM },
+ { Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM },
+ { Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM },
+ { Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM },
+ { Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM },
+ { Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM },
+ { Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM },
+ { Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM },
+ { Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM },
+ { Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM },
+ { Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM },
+ { Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM },
+ { Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM },
+ { Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM },
+ { Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM },
+ { Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM },
+ { Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM },
+ { Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM },
+ { Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM },
+ { Mips::DERET, Mips::DERET, Mips::DERET_MM },
+ { Mips::DI, Mips::DI, Mips::DI_MM },
+ { Mips::EHB, Mips::EHB, Mips::EHB_MM },
+ { Mips::EI, Mips::EI, Mips::EI_MM },
+ { Mips::ERET, Mips::ERET, Mips::ERET_MM },
+ { Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U },
+ { Mips::EXT, Mips::EXT, Mips::EXT_MM },
+ { Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM },
+ { Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM },
+ { Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM },
+ { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM },
+ { Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM },
+ { Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM },
+ { Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM },
+ { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM },
+ { Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM },
+ { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM },
+ { Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM },
+ { Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM },
+ { Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM },
+ { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM },
+ { Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM },
+ { Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM },
+ { Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM },
+ { Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM },
+ { Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM },
+ { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM },
+ { Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM },
+ { Mips::INS, Mips::INS, Mips::INS_MM },
+ { Mips::J, Mips::J, Mips::J_MM },
+ { Mips::JAL, Mips::JAL, Mips::JAL_MM },
+ { Mips::JALX, Mips::JALX, Mips::JALX_MM },
+ { Mips::JR, Mips::JR, Mips::JR_MM },
+ { Mips::LB, Mips::LB, Mips::LB_MM },
+ { Mips::LBE, Mips::LBE, Mips::LBE_MM },
+ { Mips::LBu, Mips::LBu, Mips::LBu_MM },
+ { Mips::LBuE, Mips::LBuE, Mips::LBuE_MM },
+ { Mips::LDC1, Mips::LDC1, Mips::LDC1_MM },
+ { Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM },
+ { Mips::LH, Mips::LH, Mips::LH_MM },
+ { Mips::LHE, Mips::LHE, Mips::LHE_MM },
+ { Mips::LHu, Mips::LHu, Mips::LHu_MM },
+ { Mips::LHuE, Mips::LHuE, Mips::LHuE_MM },
+ { Mips::LLE, Mips::LLE, Mips::LLE_MM },
+ { Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM },
+ { Mips::LUi, Mips::LUi, Mips::LUi_MM },
+ { Mips::LW, Mips::LW, Mips::LW_MM },
+ { Mips::LWC1, Mips::LWC1, Mips::LWC1_MM },
+ { Mips::LWE, Mips::LWE, Mips::LWE_MM },
+ { Mips::LWL, Mips::LWL, Mips::LWL_MM },
+ { Mips::LWLE, Mips::LWLE, Mips::LWLE_MM },
+ { Mips::LWR, Mips::LWR, Mips::LWR_MM },
+ { Mips::LWRE, Mips::LWRE, Mips::LWRE_MM },
+ { Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM },
+ { Mips::LWu, Mips::LWu, Mips::LWU_MM },
+ { Mips::MADD, Mips::MADD, Mips::MADD_MM },
+ { Mips::MADDU, Mips::MADDU, Mips::MADDU_MM },
+ { Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM },
+ { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM },
+ { Mips::MFC1, Mips::MFC1, Mips::MFC1_MM },
+ { Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM },
+ { Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM },
+ { Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM },
+ { Mips::MFHI, Mips::MFHI, Mips::MFHI_MM },
+ { Mips::MFLO, Mips::MFLO, Mips::MFLO_MM },
+ { Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM },
+ { Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM },
+ { Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM },
+ { Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM },
+ { Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM },
+ { Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM },
+ { Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM },
+ { Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM },
+ { Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM },
+ { Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM },
+ { Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM },
+ { Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM },
+ { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM },
+ { Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM },
+ { Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM },
+ { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM },
+ { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM },
+ { Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM },
+ { Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM },
+ { Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM },
+ { Mips::MTHI, Mips::MTHI, Mips::MTHI_MM },
+ { Mips::MTLO, Mips::MTLO, Mips::MTLO_MM },
+ { Mips::MUL, Mips::MUL, Mips::MUL_MM },
+ { Mips::MULT, Mips::MULT, Mips::MULT_MM },
+ { Mips::MULTu, Mips::MULTu, Mips::MULTu_MM },
+ { Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM },
+ { Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM },
+ { Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM },
+ { Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM },
+ { Mips::NOR, Mips::NOR, Mips::NOR_MM },
+ { Mips::OR, Mips::OR, Mips::OR_MM },
+ { Mips::ORi, Mips::ORi, Mips::ORi_MM },
+ { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM },
+ { Mips::PREF, Mips::PREF, Mips::PREF_MM },
+ { Mips::PREFE, Mips::PREFE, Mips::PREFE_MM },
+ { Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM },
+ { Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM },
+ { Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM },
+ { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM },
+ { Mips::ROTR, Mips::ROTR, Mips::ROTR_MM },
+ { Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM },
+ { Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM },
+ { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM },
+ { Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM },
+ { Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM },
+ { Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM },
+ { Mips::SB, Mips::SB, Mips::SB_MM },
+ { Mips::SBE, Mips::SBE, Mips::SBE_MM },
+ { Mips::SCE, Mips::SCE, Mips::SCE_MM },
+ { Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM },
+ { Mips::SDC1, Mips::SDC1, Mips::SDC1_MM },
+ { Mips::SDIV, Mips::SDIV, Mips::SDIV_MM },
+ { Mips::SEB, Mips::SEB, Mips::SEB_MM },
+ { Mips::SEH, Mips::SEH, Mips::SEH_MM },
+ { Mips::SH, Mips::SH, Mips::SH_MM },
+ { Mips::SHE, Mips::SHE, Mips::SHE_MM },
+ { Mips::SLL, Mips::SLL, Mips::SLL_MM },
+ { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM },
+ { Mips::SLT, Mips::SLT, Mips::SLT_MM },
+ { Mips::SLTi, Mips::SLTi, Mips::SLTi_MM },
+ { Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM },
+ { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM },
+ { Mips::SRA, Mips::SRA, Mips::SRA_MM },
+ { Mips::SRAV, Mips::SRAV, Mips::SRAV_MM },
+ { Mips::SRL, Mips::SRL, Mips::SRL_MM },
+ { Mips::SRLV, Mips::SRLV, Mips::SRLV_MM },
+ { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM },
+ { Mips::SUB, Mips::SUB, Mips::SUB_MM },
+ { Mips::SUBu, Mips::SUBu, Mips::SUBu_MM },
+ { Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM },
+ { Mips::SW, Mips::SW, Mips::SW_MM },
+ { Mips::SWC1, Mips::SWC1, Mips::SWC1_MM },
+ { Mips::SWE, Mips::SWE, Mips::SWE_MM },
+ { Mips::SWL, Mips::SWL, Mips::SWL_MM },
+ { Mips::SWLE, Mips::SWLE, Mips::SWLE_MM },
+ { Mips::SWR, Mips::SWR, Mips::SWR_MM },
+ { Mips::SWRE, Mips::SWRE, Mips::SWRE_MM },
+ { Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM },
+ { Mips::SYNC, Mips::SYNC, Mips::SYNC_MM },
+ { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM },
+ { Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM },
+ { Mips::TEQ, Mips::TEQ, Mips::TEQ_MM },
+ { Mips::TEQI, Mips::TEQI, Mips::TEQI_MM },
+ { Mips::TGE, Mips::TGE, Mips::TGE_MM },
+ { Mips::TGEI, Mips::TGEI, Mips::TGEI_MM },
+ { Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM },
+ { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM },
+ { Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM },
+ { Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM },
+ { Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM },
+ { Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM },
+ { Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM },
+ { Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM },
+ { Mips::TLBP, Mips::TLBP, Mips::TLBP_MM },
+ { Mips::TLBR, Mips::TLBR, Mips::TLBR_MM },
+ { Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM },
+ { Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM },
+ { Mips::TLT, Mips::TLT, Mips::TLT_MM },
+ { Mips::TLTI, Mips::TLTI, Mips::TLTI_MM },
+ { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM },
+ { Mips::TNE, Mips::TNE, Mips::TNE_MM },
+ { Mips::TNEI, Mips::TNEI, Mips::TNEI_MM },
+ { Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM },
+ { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM },
+ { Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM },
+ { Mips::UDIV, Mips::UDIV, Mips::UDIV_MM },
+ { Mips::WAIT, Mips::WAIT, Mips::WAIT_MM },
+ { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM },
+ { Mips::XOR, Mips::XOR, Mips::XOR_MM },
+ { Mips::XORi, Mips::XORi, Mips::XORi_MM },
+}; // End of Std2MicroMipsTable
+
+ unsigned mid;
+ unsigned start = 0;
+ unsigned end = 266;
+ while (start < end) {
+ mid = start + (end - start)/2;
+ if (Opcode == Std2MicroMipsTable[mid][0]) {
+ break;
+ }
+ if (Opcode < Std2MicroMipsTable[mid][0])
+ end = mid;
+ else
+ start = mid + 1;
+ }
+ if (start == end)
+ return -1; // Instruction doesn't exist in this table.
+
+ if (inArch == Arch_se)
+ return Std2MicroMipsTable[mid][1];
+ if (inArch == Arch_micromips)
+ return Std2MicroMipsTable[mid][2];
+ return -1;}
+
+// Std2MicroMipsR6
+LLVM_READONLY
+int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) {
+static const uint16_t Std2MicroMipsR6Table[][3] = {
+ { Mips::ADD, Mips::ADD, Mips::ADD_MMR6 },
+ { Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 },
+ { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 },
+ { Mips::AND, Mips::AND, Mips::AND_MMR6 },
+ { Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 },
+ { Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 },
+ { Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 },
+ { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 },
+ { Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U },
+ { Mips::DI, Mips::DI, Mips::DI_MMR6 },
+ { Mips::EI, Mips::EI, Mips::EI_MMR6 },
+ { Mips::EXT, Mips::EXT, Mips::EXT_MMR6 },
+ { Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 },
+ { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 },
+ { Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U },
+ { Mips::INS, Mips::INS, Mips::INS_MMR6 },
+ { Mips::LDC1, Mips::LDC1, (uint16_t)-1U },
+ { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 },
+ { Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 },
+ { Mips::LW, Mips::LW, Mips::LW_MMR6 },
+ { Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 },
+ { Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U },
+ { Mips::NOR, Mips::NOR, Mips::NOR_MMR6 },
+ { Mips::OR, Mips::OR, Mips::OR_MMR6 },
+ { Mips::ORi, Mips::ORi, Mips::ORI_MMR6 },
+ { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 },
+ { Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 },
+ { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 },
+ { Mips::SB, Mips::SB, Mips::SB_MMR6 },
+ { Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 },
+ { Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 },
+ { Mips::SEB, Mips::SEB, (uint16_t)-1U },
+ { Mips::SEH, Mips::SEH, (uint16_t)-1U },
+ { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 },
+ { Mips::SUB, Mips::SUB, Mips::SUB_MMR6 },
+ { Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 },
+ { Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 },
+ { Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 },
+ { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 },
+ { Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 },
+ { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 },
+ { Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 },
+ { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 },
+ { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 },
+}; // End of Std2MicroMipsR6Table
+
+ unsigned mid;
+ unsigned start = 0;
+ unsigned end = 44;
+ while (start < end) {
+ mid = start + (end - start)/2;
+ if (Opcode == Std2MicroMipsR6Table[mid][0]) {
+ break;
+ }
+ if (Opcode < Std2MicroMipsR6Table[mid][0])
+ end = mid;
+ else
+ start = mid + 1;
+ }
+ if (start == end)
+ return -1; // Instruction doesn't exist in this table.
+
+ if (inArch == Arch_se)
+ return Std2MicroMipsR6Table[mid][1];
+ if (inArch == Arch_micromipsr6)
+ return Std2MicroMipsR6Table[mid][2];
+ return -1;}
+
+} // End Mips namespace
+} // End llvm namespace
+#endif // GET_INSTRMAP_INFO
+
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenMCCodeEmitter.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenMCCodeEmitter.inc
new file mode 100644
index 0000000..b66faa3
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenMCCodeEmitter.inc
@@ -0,0 +1,10388 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Machine Code Emitter *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ static const uint64_t InstBits[] = {
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(2080375378), // ABSQ_S_PH
+ UINT64_C(4412), // ABSQ_S_PH_MM
+ UINT64_C(2080374866), // ABSQ_S_QB
+ UINT64_C(316), // ABSQ_S_QB_MMR2
+ UINT64_C(2080375890), // ABSQ_S_W
+ UINT64_C(8508), // ABSQ_S_W_MM
+ UINT64_C(32), // ADD
+ UINT64_C(3959422976), // ADDIUPC
+ UINT64_C(2013265920), // ADDIUPC_MM
+ UINT64_C(2013265920), // ADDIUPC_MMR6
+ UINT64_C(27649), // ADDIUR1SP_MM
+ UINT64_C(27648), // ADDIUR2_MM
+ UINT64_C(19456), // ADDIUS5_MM
+ UINT64_C(19457), // ADDIUSP_MM
+ UINT64_C(805306368), // ADDIU_MMR6
+ UINT64_C(2080375320), // ADDQH_PH
+ UINT64_C(77), // ADDQH_PH_MMR2
+ UINT64_C(2080375448), // ADDQH_R_PH
+ UINT64_C(1101), // ADDQH_R_PH_MMR2
+ UINT64_C(2080375960), // ADDQH_R_W
+ UINT64_C(1165), // ADDQH_R_W_MMR2
+ UINT64_C(2080375832), // ADDQH_W
+ UINT64_C(141), // ADDQH_W_MMR2
+ UINT64_C(2080375440), // ADDQ_PH
+ UINT64_C(13), // ADDQ_PH_MM
+ UINT64_C(2080375696), // ADDQ_S_PH
+ UINT64_C(1037), // ADDQ_S_PH_MM
+ UINT64_C(2080376208), // ADDQ_S_W
+ UINT64_C(773), // ADDQ_S_W_MM
+ UINT64_C(2080375824), // ADDSC
+ UINT64_C(901), // ADDSC_MM
+ UINT64_C(2021654544), // ADDS_A_B
+ UINT64_C(2027946000), // ADDS_A_D
+ UINT64_C(2023751696), // ADDS_A_H
+ UINT64_C(2025848848), // ADDS_A_W
+ UINT64_C(2030043152), // ADDS_S_B
+ UINT64_C(2036334608), // ADDS_S_D
+ UINT64_C(2032140304), // ADDS_S_H
+ UINT64_C(2034237456), // ADDS_S_W
+ UINT64_C(2038431760), // ADDS_U_B
+ UINT64_C(2044723216), // ADDS_U_D
+ UINT64_C(2040528912), // ADDS_U_H
+ UINT64_C(2042626064), // ADDS_U_W
+ UINT64_C(1024), // ADDU16_MM
+ UINT64_C(1024), // ADDU16_MMR6
+ UINT64_C(2080374808), // ADDUH_QB
+ UINT64_C(333), // ADDUH_QB_MMR2
+ UINT64_C(2080374936), // ADDUH_R_QB
+ UINT64_C(1357), // ADDUH_R_QB_MMR2
+ UINT64_C(336), // ADDU_MMR6
+ UINT64_C(2080375312), // ADDU_PH
+ UINT64_C(269), // ADDU_PH_MMR2
+ UINT64_C(2080374800), // ADDU_QB
+ UINT64_C(205), // ADDU_QB_MM
+ UINT64_C(2080375568), // ADDU_S_PH
+ UINT64_C(1293), // ADDU_S_PH_MMR2
+ UINT64_C(2080375056), // ADDU_S_QB
+ UINT64_C(1229), // ADDU_S_QB_MM
+ UINT64_C(2013265926), // ADDVI_B
+ UINT64_C(2019557382), // ADDVI_D
+ UINT64_C(2015363078), // ADDVI_H
+ UINT64_C(2017460230), // ADDVI_W
+ UINT64_C(2013265934), // ADDV_B
+ UINT64_C(2019557390), // ADDV_D
+ UINT64_C(2015363086), // ADDV_H
+ UINT64_C(2017460238), // ADDV_W
+ UINT64_C(2080375888), // ADDWC
+ UINT64_C(965), // ADDWC_MM
+ UINT64_C(2013265936), // ADD_A_B
+ UINT64_C(2019557392), // ADD_A_D
+ UINT64_C(2015363088), // ADD_A_H
+ UINT64_C(2017460240), // ADD_A_W
+ UINT64_C(272), // ADD_MM
+ UINT64_C(272), // ADD_MMR6
+ UINT64_C(536870912), // ADDi
+ UINT64_C(268435456), // ADDi_MM
+ UINT64_C(603979776), // ADDiu
+ UINT64_C(805306368), // ADDiu_MM
+ UINT64_C(33), // ADDu
+ UINT64_C(336), // ADDu_MM
+ UINT64_C(2080375328), // ALIGN
+ UINT64_C(31), // ALIGN_MMR6
+ UINT64_C(3961454592), // ALUIPC
+ UINT64_C(2015297536), // ALUIPC_MMR6
+ UINT64_C(36), // AND
+ UINT64_C(17536), // AND16_MM
+ UINT64_C(17409), // AND16_MMR6
+ UINT64_C(36), // AND64
+ UINT64_C(11264), // ANDI16_MM
+ UINT64_C(11264), // ANDI16_MMR6
+ UINT64_C(2013265920), // ANDI_B
+ UINT64_C(3489660928), // ANDI_MMR6
+ UINT64_C(592), // AND_MM
+ UINT64_C(592), // AND_MMR6
+ UINT64_C(2013265950), // AND_V
+ UINT64_C(805306368), // ANDi
+ UINT64_C(805306368), // ANDi64
+ UINT64_C(3489660928), // ANDi_MM
+ UINT64_C(2080374833), // APPEND
+ UINT64_C(533), // APPEND_MMR2
+ UINT64_C(2046820369), // ASUB_S_B
+ UINT64_C(2053111825), // ASUB_S_D
+ UINT64_C(2048917521), // ASUB_S_H
+ UINT64_C(2051014673), // ASUB_S_W
+ UINT64_C(2055208977), // ASUB_U_B
+ UINT64_C(2061500433), // ASUB_U_D
+ UINT64_C(2057306129), // ASUB_U_H
+ UINT64_C(2059403281), // ASUB_U_W
+ UINT64_C(1006632960), // AUI
+ UINT64_C(3961389056), // AUIPC
+ UINT64_C(2015232000), // AUIPC_MMR6
+ UINT64_C(268435456), // AUI_MMR6
+ UINT64_C(2063597584), // AVER_S_B
+ UINT64_C(2069889040), // AVER_S_D
+ UINT64_C(2065694736), // AVER_S_H
+ UINT64_C(2067791888), // AVER_S_W
+ UINT64_C(2071986192), // AVER_U_B
+ UINT64_C(2078277648), // AVER_U_D
+ UINT64_C(2074083344), // AVER_U_H
+ UINT64_C(2076180496), // AVER_U_W
+ UINT64_C(2046820368), // AVE_S_B
+ UINT64_C(2053111824), // AVE_S_D
+ UINT64_C(2048917520), // AVE_S_H
+ UINT64_C(2051014672), // AVE_S_W
+ UINT64_C(2055208976), // AVE_U_B
+ UINT64_C(2061500432), // AVE_U_D
+ UINT64_C(2057306128), // AVE_U_H
+ UINT64_C(2059403280), // AVE_U_W
+ UINT64_C(4026550272), // AddiuRxImmX16
+ UINT64_C(4026533888), // AddiuRxPcImmX16
+ UINT64_C(18432), // AddiuRxRxImm16
+ UINT64_C(4026550272), // AddiuRxRxImmX16
+ UINT64_C(4026548224), // AddiuRxRyOffMemX16
+ UINT64_C(25344), // AddiuSpImm16
+ UINT64_C(4026544896), // AddiuSpImmX16
+ UINT64_C(57345), // AdduRxRyRz16
+ UINT64_C(59404), // AndRxRxRy16
+ UINT64_C(52224), // B16_MM
+ UINT64_C(1879048232), // BADDu
+ UINT64_C(68222976), // BAL
+ UINT64_C(3892314112), // BALC
+ UINT64_C(3019898880), // BALC_MMR6
+ UINT64_C(2080375857), // BALIGN
+ UINT64_C(2236), // BALIGN_MMR2
+ UINT64_C(3355443200), // BBIT0
+ UINT64_C(3623878656), // BBIT032
+ UINT64_C(3892314112), // BBIT1
+ UINT64_C(4160749568), // BBIT132
+ UINT64_C(3355443200), // BC
+ UINT64_C(52224), // BC16_MMR6
+ UINT64_C(1159725056), // BC1EQZ
+ UINT64_C(1090519040), // BC1EQZC_MMR6
+ UINT64_C(1157627904), // BC1F
+ UINT64_C(1157758976), // BC1FL
+ UINT64_C(1132462080), // BC1F_MM
+ UINT64_C(1168113664), // BC1NEZ
+ UINT64_C(1092616192), // BC1NEZC_MMR6
+ UINT64_C(1157693440), // BC1T
+ UINT64_C(1157824512), // BC1TL
+ UINT64_C(1134559232), // BC1T_MM
+ UINT64_C(1226833920), // BC2EQZ
+ UINT64_C(1094713344), // BC2EQZC_MMR6
+ UINT64_C(1235222528), // BC2NEZ
+ UINT64_C(1096810496), // BC2NEZC_MMR6
+ UINT64_C(2045771785), // BCLRI_B
+ UINT64_C(2038431753), // BCLRI_D
+ UINT64_C(2044723209), // BCLRI_H
+ UINT64_C(2042626057), // BCLRI_W
+ UINT64_C(2038431757), // BCLR_B
+ UINT64_C(2044723213), // BCLR_D
+ UINT64_C(2040528909), // BCLR_H
+ UINT64_C(2042626061), // BCLR_W
+ UINT64_C(2483027968), // BC_MMR6
+ UINT64_C(268435456), // BEQ
+ UINT64_C(268435456), // BEQ64
+ UINT64_C(536870912), // BEQC
+ UINT64_C(536870912), // BEQC64
+ UINT64_C(1946157056), // BEQC_MMR6
+ UINT64_C(1342177280), // BEQL
+ UINT64_C(35840), // BEQZ16_MM
+ UINT64_C(536870912), // BEQZALC
+ UINT64_C(1946157056), // BEQZALC_MMR6
+ UINT64_C(3623878656), // BEQZC
+ UINT64_C(35840), // BEQZC16_MMR6
+ UINT64_C(3623878656), // BEQZC64
+ UINT64_C(1088421888), // BEQZC_MM
+ UINT64_C(2147483648), // BEQZC_MMR6
+ UINT64_C(2483027968), // BEQ_MM
+ UINT64_C(1476395008), // BGEC
+ UINT64_C(1476395008), // BGEC64
+ UINT64_C(4093640704), // BGEC_MMR6
+ UINT64_C(402653184), // BGEUC
+ UINT64_C(402653184), // BGEUC64
+ UINT64_C(3221225472), // BGEUC_MMR6
+ UINT64_C(67174400), // BGEZ
+ UINT64_C(67174400), // BGEZ64
+ UINT64_C(68222976), // BGEZAL
+ UINT64_C(402653184), // BGEZALC
+ UINT64_C(3221225472), // BGEZALC_MMR6
+ UINT64_C(68354048), // BGEZALL
+ UINT64_C(1113587712), // BGEZALS_MM
+ UINT64_C(1080033280), // BGEZAL_MM
+ UINT64_C(1476395008), // BGEZC
+ UINT64_C(1476395008), // BGEZC64
+ UINT64_C(4093640704), // BGEZC_MMR6
+ UINT64_C(67305472), // BGEZL
+ UINT64_C(1077936128), // BGEZ_MM
+ UINT64_C(469762048), // BGTZ
+ UINT64_C(469762048), // BGTZ64
+ UINT64_C(469762048), // BGTZALC
+ UINT64_C(3758096384), // BGTZALC_MMR6
+ UINT64_C(1543503872), // BGTZC
+ UINT64_C(1543503872), // BGTZC64
+ UINT64_C(3556769792), // BGTZC_MMR6
+ UINT64_C(1543503872), // BGTZL
+ UINT64_C(1086324736), // BGTZ_MM
+ UINT64_C(2070937609), // BINSLI_B
+ UINT64_C(2063597577), // BINSLI_D
+ UINT64_C(2069889033), // BINSLI_H
+ UINT64_C(2067791881), // BINSLI_W
+ UINT64_C(2063597581), // BINSL_B
+ UINT64_C(2069889037), // BINSL_D
+ UINT64_C(2065694733), // BINSL_H
+ UINT64_C(2067791885), // BINSL_W
+ UINT64_C(2079326217), // BINSRI_B
+ UINT64_C(2071986185), // BINSRI_D
+ UINT64_C(2078277641), // BINSRI_H
+ UINT64_C(2076180489), // BINSRI_W
+ UINT64_C(2071986189), // BINSR_B
+ UINT64_C(2078277645), // BINSR_D
+ UINT64_C(2074083341), // BINSR_H
+ UINT64_C(2076180493), // BINSR_W
+ UINT64_C(2080376530), // BITREV
+ UINT64_C(12604), // BITREV_MM
+ UINT64_C(2080374816), // BITSWAP
+ UINT64_C(2876), // BITSWAP_MMR6
+ UINT64_C(402653184), // BLEZ
+ UINT64_C(402653184), // BLEZ64
+ UINT64_C(402653184), // BLEZALC
+ UINT64_C(3221225472), // BLEZALC_MMR6
+ UINT64_C(1476395008), // BLEZC
+ UINT64_C(1476395008), // BLEZC64
+ UINT64_C(4093640704), // BLEZC_MMR6
+ UINT64_C(1476395008), // BLEZL
+ UINT64_C(1082130432), // BLEZ_MM
+ UINT64_C(1543503872), // BLTC
+ UINT64_C(1543503872), // BLTC64
+ UINT64_C(3556769792), // BLTC_MMR6
+ UINT64_C(469762048), // BLTUC
+ UINT64_C(469762048), // BLTUC64
+ UINT64_C(3758096384), // BLTUC_MMR6
+ UINT64_C(67108864), // BLTZ
+ UINT64_C(67108864), // BLTZ64
+ UINT64_C(68157440), // BLTZAL
+ UINT64_C(469762048), // BLTZALC
+ UINT64_C(3758096384), // BLTZALC_MMR6
+ UINT64_C(68288512), // BLTZALL
+ UINT64_C(1109393408), // BLTZALS_MM
+ UINT64_C(1075838976), // BLTZAL_MM
+ UINT64_C(1543503872), // BLTZC
+ UINT64_C(1543503872), // BLTZC64
+ UINT64_C(3556769792), // BLTZC_MMR6
+ UINT64_C(67239936), // BLTZL
+ UINT64_C(1073741824), // BLTZ_MM
+ UINT64_C(2013265921), // BMNZI_B
+ UINT64_C(2021654558), // BMNZ_V
+ UINT64_C(2030043137), // BMZI_B
+ UINT64_C(2023751710), // BMZ_V
+ UINT64_C(335544320), // BNE
+ UINT64_C(335544320), // BNE64
+ UINT64_C(1610612736), // BNEC
+ UINT64_C(1610612736), // BNEC64
+ UINT64_C(2080374784), // BNEC_MMR6
+ UINT64_C(2062549001), // BNEGI_B
+ UINT64_C(2055208969), // BNEGI_D
+ UINT64_C(2061500425), // BNEGI_H
+ UINT64_C(2059403273), // BNEGI_W
+ UINT64_C(2055208973), // BNEG_B
+ UINT64_C(2061500429), // BNEG_D
+ UINT64_C(2057306125), // BNEG_H
+ UINT64_C(2059403277), // BNEG_W
+ UINT64_C(1409286144), // BNEL
+ UINT64_C(44032), // BNEZ16_MM
+ UINT64_C(1610612736), // BNEZALC
+ UINT64_C(2080374784), // BNEZALC_MMR6
+ UINT64_C(4160749568), // BNEZC
+ UINT64_C(44032), // BNEZC16_MMR6
+ UINT64_C(4160749568), // BNEZC64
+ UINT64_C(1084227584), // BNEZC_MM
+ UINT64_C(2684354560), // BNEZC_MMR6
+ UINT64_C(3019898880), // BNE_MM
+ UINT64_C(1610612736), // BNVC
+ UINT64_C(2080374784), // BNVC_MMR6
+ UINT64_C(1199570944), // BNZ_B
+ UINT64_C(1205862400), // BNZ_D
+ UINT64_C(1201668096), // BNZ_H
+ UINT64_C(1172307968), // BNZ_V
+ UINT64_C(1203765248), // BNZ_W
+ UINT64_C(536870912), // BOVC
+ UINT64_C(1946157056), // BOVC_MMR6
+ UINT64_C(68943872), // BPOSGE32
+ UINT64_C(1126170624), // BPOSGE32C_MMR3
+ UINT64_C(1130364928), // BPOSGE32_MM
+ UINT64_C(13), // BREAK
+ UINT64_C(18048), // BREAK16_MM
+ UINT64_C(17435), // BREAK16_MMR6
+ UINT64_C(7), // BREAK_MM
+ UINT64_C(7), // BREAK_MMR6
+ UINT64_C(2046820353), // BSELI_B
+ UINT64_C(2025848862), // BSEL_V
+ UINT64_C(2054160393), // BSETI_B
+ UINT64_C(2046820361), // BSETI_D
+ UINT64_C(2053111817), // BSETI_H
+ UINT64_C(2051014665), // BSETI_W
+ UINT64_C(2046820365), // BSET_B
+ UINT64_C(2053111821), // BSET_D
+ UINT64_C(2048917517), // BSET_H
+ UINT64_C(2051014669), // BSET_W
+ UINT64_C(1191182336), // BZ_B
+ UINT64_C(1197473792), // BZ_D
+ UINT64_C(1193279488), // BZ_H
+ UINT64_C(1163919360), // BZ_V
+ UINT64_C(1195376640), // BZ_W
+ UINT64_C(8192), // BeqzRxImm16
+ UINT64_C(4026540032), // BeqzRxImmX16
+ UINT64_C(4096), // Bimm16
+ UINT64_C(4026535936), // BimmX16
+ UINT64_C(10240), // BnezRxImm16
+ UINT64_C(4026542080), // BnezRxImmX16
+ UINT64_C(59397), // Break16
+ UINT64_C(24576), // Bteqz16
+ UINT64_C(4026544128), // BteqzX16
+ UINT64_C(24832), // Btnez16
+ UINT64_C(4026544384), // BtnezX16
+ UINT64_C(3154116608), // CACHE
+ UINT64_C(2080374811), // CACHEE
+ UINT64_C(1610655232), // CACHEE_MM
+ UINT64_C(536895488), // CACHE_MM
+ UINT64_C(536895488), // CACHE_MMR6
+ UINT64_C(2080374821), // CACHE_R6
+ UINT64_C(1176502282), // CEIL_L_D64
+ UINT64_C(1409307451), // CEIL_L_D_MMR6
+ UINT64_C(1174405130), // CEIL_L_S
+ UINT64_C(1409291067), // CEIL_L_S_MMR6
+ UINT64_C(1176502286), // CEIL_W_D32
+ UINT64_C(1176502286), // CEIL_W_D64
+ UINT64_C(1409309499), // CEIL_W_D_MMR6
+ UINT64_C(1409309499), // CEIL_W_MM
+ UINT64_C(1174405134), // CEIL_W_S
+ UINT64_C(1409293115), // CEIL_W_S_MM
+ UINT64_C(1409293115), // CEIL_W_S_MMR6
+ UINT64_C(2013265927), // CEQI_B
+ UINT64_C(2019557383), // CEQI_D
+ UINT64_C(2015363079), // CEQI_H
+ UINT64_C(2017460231), // CEQI_W
+ UINT64_C(2013265935), // CEQ_B
+ UINT64_C(2019557391), // CEQ_D
+ UINT64_C(2015363087), // CEQ_H
+ UINT64_C(2017460239), // CEQ_W
+ UINT64_C(1145044992), // CFC1
+ UINT64_C(1409290299), // CFC1_MM
+ UINT64_C(52540), // CFC2_MM
+ UINT64_C(2021523481), // CFCMSA
+ UINT64_C(1879048242), // CINS
+ UINT64_C(1879048243), // CINS32
+ UINT64_C(1879048242), // CINS64_32
+ UINT64_C(1879048242), // CINS_i32
+ UINT64_C(1176502299), // CLASS_D
+ UINT64_C(1409286752), // CLASS_D_MMR6
+ UINT64_C(1174405147), // CLASS_S
+ UINT64_C(1409286240), // CLASS_S_MMR6
+ UINT64_C(2046820359), // CLEI_S_B
+ UINT64_C(2053111815), // CLEI_S_D
+ UINT64_C(2048917511), // CLEI_S_H
+ UINT64_C(2051014663), // CLEI_S_W
+ UINT64_C(2055208967), // CLEI_U_B
+ UINT64_C(2061500423), // CLEI_U_D
+ UINT64_C(2057306119), // CLEI_U_H
+ UINT64_C(2059403271), // CLEI_U_W
+ UINT64_C(2046820367), // CLE_S_B
+ UINT64_C(2053111823), // CLE_S_D
+ UINT64_C(2048917519), // CLE_S_H
+ UINT64_C(2051014671), // CLE_S_W
+ UINT64_C(2055208975), // CLE_U_B
+ UINT64_C(2061500431), // CLE_U_D
+ UINT64_C(2057306127), // CLE_U_H
+ UINT64_C(2059403279), // CLE_U_W
+ UINT64_C(1879048225), // CLO
+ UINT64_C(19260), // CLO_MM
+ UINT64_C(19260), // CLO_MMR6
+ UINT64_C(81), // CLO_R6
+ UINT64_C(2030043143), // CLTI_S_B
+ UINT64_C(2036334599), // CLTI_S_D
+ UINT64_C(2032140295), // CLTI_S_H
+ UINT64_C(2034237447), // CLTI_S_W
+ UINT64_C(2038431751), // CLTI_U_B
+ UINT64_C(2044723207), // CLTI_U_D
+ UINT64_C(2040528903), // CLTI_U_H
+ UINT64_C(2042626055), // CLTI_U_W
+ UINT64_C(2030043151), // CLT_S_B
+ UINT64_C(2036334607), // CLT_S_D
+ UINT64_C(2032140303), // CLT_S_H
+ UINT64_C(2034237455), // CLT_S_W
+ UINT64_C(2038431759), // CLT_U_B
+ UINT64_C(2044723215), // CLT_U_D
+ UINT64_C(2040528911), // CLT_U_H
+ UINT64_C(2042626063), // CLT_U_W
+ UINT64_C(1879048224), // CLZ
+ UINT64_C(23356), // CLZ_MM
+ UINT64_C(80), // CLZ_MMR6
+ UINT64_C(80), // CLZ_R6
+ UINT64_C(2080376337), // CMPGDU_EQ_QB
+ UINT64_C(389), // CMPGDU_EQ_QB_MMR2
+ UINT64_C(2080376465), // CMPGDU_LE_QB
+ UINT64_C(517), // CMPGDU_LE_QB_MMR2
+ UINT64_C(2080376401), // CMPGDU_LT_QB
+ UINT64_C(453), // CMPGDU_LT_QB_MMR2
+ UINT64_C(2080375057), // CMPGU_EQ_QB
+ UINT64_C(1476395205), // CMPGU_EQ_QB_MM
+ UINT64_C(2080375185), // CMPGU_LE_QB
+ UINT64_C(1476395333), // CMPGU_LE_QB_MM
+ UINT64_C(2080375121), // CMPGU_LT_QB
+ UINT64_C(1476395269), // CMPGU_LT_QB_MM
+ UINT64_C(2080374801), // CMPU_EQ_QB
+ UINT64_C(581), // CMPU_EQ_QB_MM
+ UINT64_C(2080374929), // CMPU_LE_QB
+ UINT64_C(709), // CMPU_LE_QB_MM
+ UINT64_C(2080374865), // CMPU_LT_QB
+ UINT64_C(645), // CMPU_LT_QB_MM
+ UINT64_C(1409286165), // CMP_AF_D_MMR6
+ UINT64_C(1409286149), // CMP_AF_S_MMR6
+ UINT64_C(1184890882), // CMP_EQ_D
+ UINT64_C(1409286293), // CMP_EQ_D_MMR6
+ UINT64_C(2080375313), // CMP_EQ_PH
+ UINT64_C(5), // CMP_EQ_PH_MM
+ UINT64_C(1182793730), // CMP_EQ_S
+ UINT64_C(1409286277), // CMP_EQ_S_MMR6
+ UINT64_C(1184890880), // CMP_F_D
+ UINT64_C(1182793728), // CMP_F_S
+ UINT64_C(1184890886), // CMP_LE_D
+ UINT64_C(1409286549), // CMP_LE_D_MMR6
+ UINT64_C(2080375441), // CMP_LE_PH
+ UINT64_C(133), // CMP_LE_PH_MM
+ UINT64_C(1182793734), // CMP_LE_S
+ UINT64_C(1409286533), // CMP_LE_S_MMR6
+ UINT64_C(1184890884), // CMP_LT_D
+ UINT64_C(1409286421), // CMP_LT_D_MMR6
+ UINT64_C(2080375377), // CMP_LT_PH
+ UINT64_C(69), // CMP_LT_PH_MM
+ UINT64_C(1182793732), // CMP_LT_S
+ UINT64_C(1409286405), // CMP_LT_S_MMR6
+ UINT64_C(1184890888), // CMP_SAF_D
+ UINT64_C(1409286677), // CMP_SAF_D_MMR6
+ UINT64_C(1182793736), // CMP_SAF_S
+ UINT64_C(1409286661), // CMP_SAF_S_MMR6
+ UINT64_C(1184890890), // CMP_SEQ_D
+ UINT64_C(1409286805), // CMP_SEQ_D_MMR6
+ UINT64_C(1182793738), // CMP_SEQ_S
+ UINT64_C(1409286789), // CMP_SEQ_S_MMR6
+ UINT64_C(1184890894), // CMP_SLE_D
+ UINT64_C(1409287061), // CMP_SLE_D_MMR6
+ UINT64_C(1182793742), // CMP_SLE_S
+ UINT64_C(1409287045), // CMP_SLE_S_MMR6
+ UINT64_C(1184890892), // CMP_SLT_D
+ UINT64_C(1409286933), // CMP_SLT_D_MMR6
+ UINT64_C(1182793740), // CMP_SLT_S
+ UINT64_C(1409286917), // CMP_SLT_S_MMR6
+ UINT64_C(1184890891), // CMP_SUEQ_D
+ UINT64_C(1409286869), // CMP_SUEQ_D_MMR6
+ UINT64_C(1182793739), // CMP_SUEQ_S
+ UINT64_C(1409286853), // CMP_SUEQ_S_MMR6
+ UINT64_C(1184890895), // CMP_SULE_D
+ UINT64_C(1409287125), // CMP_SULE_D_MMR6
+ UINT64_C(1182793743), // CMP_SULE_S
+ UINT64_C(1409287109), // CMP_SULE_S_MMR6
+ UINT64_C(1184890893), // CMP_SULT_D
+ UINT64_C(1409286997), // CMP_SULT_D_MMR6
+ UINT64_C(1182793741), // CMP_SULT_S
+ UINT64_C(1409286981), // CMP_SULT_S_MMR6
+ UINT64_C(1184890889), // CMP_SUN_D
+ UINT64_C(1409286741), // CMP_SUN_D_MMR6
+ UINT64_C(1182793737), // CMP_SUN_S
+ UINT64_C(1409286725), // CMP_SUN_S_MMR6
+ UINT64_C(1184890883), // CMP_UEQ_D
+ UINT64_C(1409286357), // CMP_UEQ_D_MMR6
+ UINT64_C(1182793731), // CMP_UEQ_S
+ UINT64_C(1409286341), // CMP_UEQ_S_MMR6
+ UINT64_C(1184890887), // CMP_ULE_D
+ UINT64_C(1409286613), // CMP_ULE_D_MMR6
+ UINT64_C(1182793735), // CMP_ULE_S
+ UINT64_C(1409286597), // CMP_ULE_S_MMR6
+ UINT64_C(1184890885), // CMP_ULT_D
+ UINT64_C(1409286485), // CMP_ULT_D_MMR6
+ UINT64_C(1182793733), // CMP_ULT_S
+ UINT64_C(1409286469), // CMP_ULT_S_MMR6
+ UINT64_C(1184890881), // CMP_UN_D
+ UINT64_C(1409286229), // CMP_UN_D_MMR6
+ UINT64_C(1182793729), // CMP_UN_S
+ UINT64_C(1409286213), // CMP_UN_S_MMR6
+ UINT64_C(2021654553), // COPY_S_B
+ UINT64_C(2025324569), // COPY_S_D
+ UINT64_C(2023751705), // COPY_S_H
+ UINT64_C(2024800281), // COPY_S_W
+ UINT64_C(2025848857), // COPY_U_B
+ UINT64_C(2027946009), // COPY_U_H
+ UINT64_C(2028994585), // COPY_U_W
+ UINT64_C(2080374799), // CRC32B
+ UINT64_C(2080375055), // CRC32CB
+ UINT64_C(2080375247), // CRC32CD
+ UINT64_C(2080375119), // CRC32CH
+ UINT64_C(2080375183), // CRC32CW
+ UINT64_C(2080374991), // CRC32D
+ UINT64_C(2080374863), // CRC32H
+ UINT64_C(2080374927), // CRC32W
+ UINT64_C(1153433600), // CTC1
+ UINT64_C(1409292347), // CTC1_MM
+ UINT64_C(56636), // CTC2_MM
+ UINT64_C(2017329177), // CTCMSA
+ UINT64_C(1174405153), // CVT_D32_S
+ UINT64_C(1409291131), // CVT_D32_S_MM
+ UINT64_C(1182793761), // CVT_D32_W
+ UINT64_C(1409299323), // CVT_D32_W_MM
+ UINT64_C(1184890913), // CVT_D64_L
+ UINT64_C(1174405153), // CVT_D64_S
+ UINT64_C(1409291131), // CVT_D64_S_MM
+ UINT64_C(1182793761), // CVT_D64_W
+ UINT64_C(1409299323), // CVT_D64_W_MM
+ UINT64_C(1409307515), // CVT_D_L_MMR6
+ UINT64_C(1176502309), // CVT_L_D64
+ UINT64_C(1409302843), // CVT_L_D64_MM
+ UINT64_C(1409302843), // CVT_L_D_MMR6
+ UINT64_C(1174405157), // CVT_L_S
+ UINT64_C(1409286459), // CVT_L_S_MM
+ UINT64_C(1409286459), // CVT_L_S_MMR6
+ UINT64_C(1176502304), // CVT_S_D32
+ UINT64_C(1409293179), // CVT_S_D32_MM
+ UINT64_C(1176502304), // CVT_S_D64
+ UINT64_C(1409293179), // CVT_S_D64_MM
+ UINT64_C(1184890912), // CVT_S_L
+ UINT64_C(1409309563), // CVT_S_L_MMR6
+ UINT64_C(1182793760), // CVT_S_W
+ UINT64_C(1409301371), // CVT_S_W_MM
+ UINT64_C(1409301371), // CVT_S_W_MMR6
+ UINT64_C(1176502308), // CVT_W_D32
+ UINT64_C(1409304891), // CVT_W_D32_MM
+ UINT64_C(1176502308), // CVT_W_D64
+ UINT64_C(1409304891), // CVT_W_D64_MM
+ UINT64_C(1174405156), // CVT_W_S
+ UINT64_C(1409288507), // CVT_W_S_MM
+ UINT64_C(1409288507), // CVT_W_S_MMR6
+ UINT64_C(1176502322), // C_EQ_D32
+ UINT64_C(1409287356), // C_EQ_D32_MM
+ UINT64_C(1176502322), // C_EQ_D64
+ UINT64_C(1409287356), // C_EQ_D64_MM
+ UINT64_C(1174405170), // C_EQ_S
+ UINT64_C(1409286332), // C_EQ_S_MM
+ UINT64_C(1176502320), // C_F_D32
+ UINT64_C(1409287228), // C_F_D32_MM
+ UINT64_C(1176502320), // C_F_D64
+ UINT64_C(1409287228), // C_F_D64_MM
+ UINT64_C(1174405168), // C_F_S
+ UINT64_C(1409286204), // C_F_S_MM
+ UINT64_C(1176502334), // C_LE_D32
+ UINT64_C(1409288124), // C_LE_D32_MM
+ UINT64_C(1176502334), // C_LE_D64
+ UINT64_C(1409288124), // C_LE_D64_MM
+ UINT64_C(1174405182), // C_LE_S
+ UINT64_C(1409287100), // C_LE_S_MM
+ UINT64_C(1176502332), // C_LT_D32
+ UINT64_C(1409287996), // C_LT_D32_MM
+ UINT64_C(1176502332), // C_LT_D64
+ UINT64_C(1409287996), // C_LT_D64_MM
+ UINT64_C(1174405180), // C_LT_S
+ UINT64_C(1409286972), // C_LT_S_MM
+ UINT64_C(1176502333), // C_NGE_D32
+ UINT64_C(1409288060), // C_NGE_D32_MM
+ UINT64_C(1176502333), // C_NGE_D64
+ UINT64_C(1409288060), // C_NGE_D64_MM
+ UINT64_C(1174405181), // C_NGE_S
+ UINT64_C(1409287036), // C_NGE_S_MM
+ UINT64_C(1176502329), // C_NGLE_D32
+ UINT64_C(1409287804), // C_NGLE_D32_MM
+ UINT64_C(1176502329), // C_NGLE_D64
+ UINT64_C(1409287804), // C_NGLE_D64_MM
+ UINT64_C(1174405177), // C_NGLE_S
+ UINT64_C(1409286780), // C_NGLE_S_MM
+ UINT64_C(1176502331), // C_NGL_D32
+ UINT64_C(1409287932), // C_NGL_D32_MM
+ UINT64_C(1176502331), // C_NGL_D64
+ UINT64_C(1409287932), // C_NGL_D64_MM
+ UINT64_C(1174405179), // C_NGL_S
+ UINT64_C(1409286908), // C_NGL_S_MM
+ UINT64_C(1176502335), // C_NGT_D32
+ UINT64_C(1409288188), // C_NGT_D32_MM
+ UINT64_C(1176502335), // C_NGT_D64
+ UINT64_C(1409288188), // C_NGT_D64_MM
+ UINT64_C(1174405183), // C_NGT_S
+ UINT64_C(1409287164), // C_NGT_S_MM
+ UINT64_C(1176502326), // C_OLE_D32
+ UINT64_C(1409287612), // C_OLE_D32_MM
+ UINT64_C(1176502326), // C_OLE_D64
+ UINT64_C(1409287612), // C_OLE_D64_MM
+ UINT64_C(1174405174), // C_OLE_S
+ UINT64_C(1409286588), // C_OLE_S_MM
+ UINT64_C(1176502324), // C_OLT_D32
+ UINT64_C(1409287484), // C_OLT_D32_MM
+ UINT64_C(1176502324), // C_OLT_D64
+ UINT64_C(1409287484), // C_OLT_D64_MM
+ UINT64_C(1174405172), // C_OLT_S
+ UINT64_C(1409286460), // C_OLT_S_MM
+ UINT64_C(1176502330), // C_SEQ_D32
+ UINT64_C(1409287868), // C_SEQ_D32_MM
+ UINT64_C(1176502330), // C_SEQ_D64
+ UINT64_C(1409287868), // C_SEQ_D64_MM
+ UINT64_C(1174405178), // C_SEQ_S
+ UINT64_C(1409286844), // C_SEQ_S_MM
+ UINT64_C(1176502328), // C_SF_D32
+ UINT64_C(1409287740), // C_SF_D32_MM
+ UINT64_C(1176502328), // C_SF_D64
+ UINT64_C(1409287740), // C_SF_D64_MM
+ UINT64_C(1174405176), // C_SF_S
+ UINT64_C(1409286716), // C_SF_S_MM
+ UINT64_C(1176502323), // C_UEQ_D32
+ UINT64_C(1409287420), // C_UEQ_D32_MM
+ UINT64_C(1176502323), // C_UEQ_D64
+ UINT64_C(1409287420), // C_UEQ_D64_MM
+ UINT64_C(1174405171), // C_UEQ_S
+ UINT64_C(1409286396), // C_UEQ_S_MM
+ UINT64_C(1176502327), // C_ULE_D32
+ UINT64_C(1409287676), // C_ULE_D32_MM
+ UINT64_C(1176502327), // C_ULE_D64
+ UINT64_C(1409287676), // C_ULE_D64_MM
+ UINT64_C(1174405175), // C_ULE_S
+ UINT64_C(1409286652), // C_ULE_S_MM
+ UINT64_C(1176502325), // C_ULT_D32
+ UINT64_C(1409287548), // C_ULT_D32_MM
+ UINT64_C(1176502325), // C_ULT_D64
+ UINT64_C(1409287548), // C_ULT_D64_MM
+ UINT64_C(1174405173), // C_ULT_S
+ UINT64_C(1409286524), // C_ULT_S_MM
+ UINT64_C(1176502321), // C_UN_D32
+ UINT64_C(1409287292), // C_UN_D32_MM
+ UINT64_C(1176502321), // C_UN_D64
+ UINT64_C(1409287292), // C_UN_D64_MM
+ UINT64_C(1174405169), // C_UN_S
+ UINT64_C(1409286268), // C_UN_S_MM
+ UINT64_C(59402), // CmpRxRy16
+ UINT64_C(28672), // CmpiRxImm16
+ UINT64_C(4026560512), // CmpiRxImmX16
+ UINT64_C(44), // DADD
+ UINT64_C(1610612736), // DADDi
+ UINT64_C(1677721600), // DADDiu
+ UINT64_C(45), // DADDu
+ UINT64_C(67502080), // DAHI
+ UINT64_C(2080375332), // DALIGN
+ UINT64_C(69074944), // DATI
+ UINT64_C(1946157056), // DAUI
+ UINT64_C(2080374820), // DBITSWAP
+ UINT64_C(1879048229), // DCLO
+ UINT64_C(83), // DCLO_R6
+ UINT64_C(1879048228), // DCLZ
+ UINT64_C(82), // DCLZ_R6
+ UINT64_C(158), // DDIV
+ UINT64_C(159), // DDIVU
+ UINT64_C(1107296287), // DERET
+ UINT64_C(58236), // DERET_MM
+ UINT64_C(58236), // DERET_MMR6
+ UINT64_C(2080374787), // DEXT
+ UINT64_C(2080374787), // DEXT64_32
+ UINT64_C(2080374785), // DEXTM
+ UINT64_C(2080374786), // DEXTU
+ UINT64_C(1096835072), // DI
+ UINT64_C(2080374791), // DINS
+ UINT64_C(2080374789), // DINSM
+ UINT64_C(2080374790), // DINSU
+ UINT64_C(154), // DIV
+ UINT64_C(155), // DIVU
+ UINT64_C(408), // DIVU_MMR6
+ UINT64_C(280), // DIV_MMR6
+ UINT64_C(2046820370), // DIV_S_B
+ UINT64_C(2053111826), // DIV_S_D
+ UINT64_C(2048917522), // DIV_S_H
+ UINT64_C(2051014674), // DIV_S_W
+ UINT64_C(2055208978), // DIV_U_B
+ UINT64_C(2061500434), // DIV_U_D
+ UINT64_C(2057306130), // DIV_U_H
+ UINT64_C(2059403282), // DIV_U_W
+ UINT64_C(18300), // DI_MM
+ UINT64_C(18300), // DI_MMR6
+ UINT64_C(21), // DLSA
+ UINT64_C(21), // DLSA_R6
+ UINT64_C(1075838976), // DMFC0
+ UINT64_C(1142947840), // DMFC1
+ UINT64_C(1210056704), // DMFC2
+ UINT64_C(1210056704), // DMFC2_OCTEON
+ UINT64_C(1080033536), // DMFGC0
+ UINT64_C(222), // DMOD
+ UINT64_C(223), // DMODU
+ UINT64_C(1096813505), // DMT
+ UINT64_C(1084227584), // DMTC0
+ UINT64_C(1151336448), // DMTC1
+ UINT64_C(1218445312), // DMTC2
+ UINT64_C(1218445312), // DMTC2_OCTEON
+ UINT64_C(1080034048), // DMTGC0
+ UINT64_C(220), // DMUH
+ UINT64_C(221), // DMUHU
+ UINT64_C(1879048195), // DMUL
+ UINT64_C(28), // DMULT
+ UINT64_C(29), // DMULTu
+ UINT64_C(157), // DMULU
+ UINT64_C(156), // DMUL_R6
+ UINT64_C(2019557395), // DOTP_S_D
+ UINT64_C(2015363091), // DOTP_S_H
+ UINT64_C(2017460243), // DOTP_S_W
+ UINT64_C(2027946003), // DOTP_U_D
+ UINT64_C(2023751699), // DOTP_U_H
+ UINT64_C(2025848851), // DOTP_U_W
+ UINT64_C(2036334611), // DPADD_S_D
+ UINT64_C(2032140307), // DPADD_S_H
+ UINT64_C(2034237459), // DPADD_S_W
+ UINT64_C(2044723219), // DPADD_U_D
+ UINT64_C(2040528915), // DPADD_U_H
+ UINT64_C(2042626067), // DPADD_U_W
+ UINT64_C(2080376496), // DPAQX_SA_W_PH
+ UINT64_C(12988), // DPAQX_SA_W_PH_MMR2
+ UINT64_C(2080376368), // DPAQX_S_W_PH
+ UINT64_C(8892), // DPAQX_S_W_PH_MMR2
+ UINT64_C(2080375600), // DPAQ_SA_L_W
+ UINT64_C(4796), // DPAQ_SA_L_W_MM
+ UINT64_C(2080375088), // DPAQ_S_W_PH
+ UINT64_C(700), // DPAQ_S_W_PH_MM
+ UINT64_C(2080375024), // DPAU_H_QBL
+ UINT64_C(8380), // DPAU_H_QBL_MM
+ UINT64_C(2080375280), // DPAU_H_QBR
+ UINT64_C(12476), // DPAU_H_QBR_MM
+ UINT64_C(2080375344), // DPAX_W_PH
+ UINT64_C(4284), // DPAX_W_PH_MMR2
+ UINT64_C(2080374832), // DPA_W_PH
+ UINT64_C(188), // DPA_W_PH_MMR2
+ UINT64_C(1879048237), // DPOP
+ UINT64_C(2080376560), // DPSQX_SA_W_PH
+ UINT64_C(14012), // DPSQX_SA_W_PH_MMR2
+ UINT64_C(2080376432), // DPSQX_S_W_PH
+ UINT64_C(9916), // DPSQX_S_W_PH_MMR2
+ UINT64_C(2080375664), // DPSQ_SA_L_W
+ UINT64_C(5820), // DPSQ_SA_L_W_MM
+ UINT64_C(2080375152), // DPSQ_S_W_PH
+ UINT64_C(1724), // DPSQ_S_W_PH_MM
+ UINT64_C(2053111827), // DPSUB_S_D
+ UINT64_C(2048917523), // DPSUB_S_H
+ UINT64_C(2051014675), // DPSUB_S_W
+ UINT64_C(2061500435), // DPSUB_U_D
+ UINT64_C(2057306131), // DPSUB_U_H
+ UINT64_C(2059403283), // DPSUB_U_W
+ UINT64_C(2080375536), // DPSU_H_QBL
+ UINT64_C(9404), // DPSU_H_QBL_MM
+ UINT64_C(2080375792), // DPSU_H_QBR
+ UINT64_C(13500), // DPSU_H_QBR_MM
+ UINT64_C(2080375408), // DPSX_W_PH
+ UINT64_C(5308), // DPSX_W_PH_MMR2
+ UINT64_C(2080374896), // DPS_W_PH
+ UINT64_C(1212), // DPS_W_PH_MMR2
+ UINT64_C(2097210), // DROTR
+ UINT64_C(2097214), // DROTR32
+ UINT64_C(86), // DROTRV
+ UINT64_C(2080374948), // DSBH
+ UINT64_C(30), // DSDIV
+ UINT64_C(2080375140), // DSHD
+ UINT64_C(56), // DSLL
+ UINT64_C(60), // DSLL32
+ UINT64_C(60), // DSLL64_32
+ UINT64_C(20), // DSLLV
+ UINT64_C(59), // DSRA
+ UINT64_C(63), // DSRA32
+ UINT64_C(23), // DSRAV
+ UINT64_C(58), // DSRL
+ UINT64_C(62), // DSRL32
+ UINT64_C(22), // DSRLV
+ UINT64_C(46), // DSUB
+ UINT64_C(47), // DSUBu
+ UINT64_C(31), // DUDIV
+ UINT64_C(1096810532), // DVP
+ UINT64_C(1096810497), // DVPE
+ UINT64_C(6524), // DVP_MMR6
+ UINT64_C(59418), // DivRxRy16
+ UINT64_C(59419), // DivuRxRy16
+ UINT64_C(192), // EHB
+ UINT64_C(6144), // EHB_MM
+ UINT64_C(6144), // EHB_MMR6
+ UINT64_C(1096835104), // EI
+ UINT64_C(22396), // EI_MM
+ UINT64_C(22396), // EI_MMR6
+ UINT64_C(1096813537), // EMT
+ UINT64_C(1107296280), // ERET
+ UINT64_C(1107296344), // ERETNC
+ UINT64_C(127868), // ERETNC_MMR6
+ UINT64_C(62332), // ERET_MM
+ UINT64_C(62332), // ERET_MMR6
+ UINT64_C(1096810500), // EVP
+ UINT64_C(1096810529), // EVPE
+ UINT64_C(14716), // EVP_MMR6
+ UINT64_C(2080374784), // EXT
+ UINT64_C(2080374968), // EXTP
+ UINT64_C(2080375480), // EXTPDP
+ UINT64_C(2080375544), // EXTPDPV
+ UINT64_C(14524), // EXTPDPV_MM
+ UINT64_C(13948), // EXTPDP_MM
+ UINT64_C(2080375032), // EXTPV
+ UINT64_C(10428), // EXTPV_MM
+ UINT64_C(9852), // EXTP_MM
+ UINT64_C(2080375288), // EXTRV_RS_W
+ UINT64_C(11964), // EXTRV_RS_W_MM
+ UINT64_C(2080375160), // EXTRV_R_W
+ UINT64_C(7868), // EXTRV_R_W_MM
+ UINT64_C(2080375800), // EXTRV_S_H
+ UINT64_C(16060), // EXTRV_S_H_MM
+ UINT64_C(2080374904), // EXTRV_W
+ UINT64_C(3772), // EXTRV_W_MM
+ UINT64_C(2080375224), // EXTR_RS_W
+ UINT64_C(11900), // EXTR_RS_W_MM
+ UINT64_C(2080375096), // EXTR_R_W
+ UINT64_C(7804), // EXTR_R_W_MM
+ UINT64_C(2080375736), // EXTR_S_H
+ UINT64_C(15996), // EXTR_S_H_MM
+ UINT64_C(2080374840), // EXTR_W
+ UINT64_C(3708), // EXTR_W_MM
+ UINT64_C(1879048250), // EXTS
+ UINT64_C(1879048251), // EXTS32
+ UINT64_C(44), // EXT_MM
+ UINT64_C(44), // EXT_MMR6
+ UINT64_C(1176502277), // FABS_D32
+ UINT64_C(1409295227), // FABS_D32_MM
+ UINT64_C(1176502277), // FABS_D64
+ UINT64_C(1409295227), // FABS_D64_MM
+ UINT64_C(1174405125), // FABS_S
+ UINT64_C(1409287035), // FABS_S_MM
+ UINT64_C(2015363099), // FADD_D
+ UINT64_C(1176502272), // FADD_D32
+ UINT64_C(1409286448), // FADD_D32_MM
+ UINT64_C(1176502272), // FADD_D64
+ UINT64_C(1409286448), // FADD_D64_MM
+ UINT64_C(1174405120), // FADD_S
+ UINT64_C(1409286192), // FADD_S_MM
+ UINT64_C(1409286192), // FADD_S_MMR6
+ UINT64_C(2013265947), // FADD_W
+ UINT64_C(2015363098), // FCAF_D
+ UINT64_C(2013265946), // FCAF_W
+ UINT64_C(2023751706), // FCEQ_D
+ UINT64_C(2021654554), // FCEQ_W
+ UINT64_C(2065760286), // FCLASS_D
+ UINT64_C(2065694750), // FCLASS_W
+ UINT64_C(2040528922), // FCLE_D
+ UINT64_C(2038431770), // FCLE_W
+ UINT64_C(2032140314), // FCLT_D
+ UINT64_C(2030043162), // FCLT_W
+ UINT64_C(1176502320), // FCMP_D32
+ UINT64_C(1409287228), // FCMP_D32_MM
+ UINT64_C(1176502320), // FCMP_D64
+ UINT64_C(1174405168), // FCMP_S32
+ UINT64_C(1409286204), // FCMP_S32_MM
+ UINT64_C(2027946012), // FCNE_D
+ UINT64_C(2025848860), // FCNE_W
+ UINT64_C(2019557404), // FCOR_D
+ UINT64_C(2017460252), // FCOR_W
+ UINT64_C(2027946010), // FCUEQ_D
+ UINT64_C(2025848858), // FCUEQ_W
+ UINT64_C(2044723226), // FCULE_D
+ UINT64_C(2042626074), // FCULE_W
+ UINT64_C(2036334618), // FCULT_D
+ UINT64_C(2034237466), // FCULT_W
+ UINT64_C(2023751708), // FCUNE_D
+ UINT64_C(2021654556), // FCUNE_W
+ UINT64_C(2019557402), // FCUN_D
+ UINT64_C(2017460250), // FCUN_W
+ UINT64_C(2027946011), // FDIV_D
+ UINT64_C(1176502275), // FDIV_D32
+ UINT64_C(1409286640), // FDIV_D32_MM
+ UINT64_C(1176502275), // FDIV_D64
+ UINT64_C(1409286640), // FDIV_D64_MM
+ UINT64_C(1174405123), // FDIV_S
+ UINT64_C(1409286384), // FDIV_S_MM
+ UINT64_C(1409286384), // FDIV_S_MMR6
+ UINT64_C(2025848859), // FDIV_W
+ UINT64_C(2046820379), // FEXDO_H
+ UINT64_C(2048917531), // FEXDO_W
+ UINT64_C(2044723227), // FEXP2_D
+ UINT64_C(2042626075), // FEXP2_W
+ UINT64_C(2066808862), // FEXUPL_D
+ UINT64_C(2066743326), // FEXUPL_W
+ UINT64_C(2066939934), // FEXUPR_D
+ UINT64_C(2066874398), // FEXUPR_W
+ UINT64_C(2067595294), // FFINT_S_D
+ UINT64_C(2067529758), // FFINT_S_W
+ UINT64_C(2067726366), // FFINT_U_D
+ UINT64_C(2067660830), // FFINT_U_W
+ UINT64_C(2067071006), // FFQL_D
+ UINT64_C(2067005470), // FFQL_W
+ UINT64_C(2067202078), // FFQR_D
+ UINT64_C(2067136542), // FFQR_W
+ UINT64_C(2063597598), // FILL_B
+ UINT64_C(2063794206), // FILL_D
+ UINT64_C(2063663134), // FILL_H
+ UINT64_C(2063728670), // FILL_W
+ UINT64_C(2066677790), // FLOG2_D
+ UINT64_C(2066612254), // FLOG2_W
+ UINT64_C(1176502283), // FLOOR_L_D64
+ UINT64_C(1409303355), // FLOOR_L_D_MMR6
+ UINT64_C(1174405131), // FLOOR_L_S
+ UINT64_C(1409286971), // FLOOR_L_S_MMR6
+ UINT64_C(1176502287), // FLOOR_W_D32
+ UINT64_C(1176502287), // FLOOR_W_D64
+ UINT64_C(1409305403), // FLOOR_W_D_MMR6
+ UINT64_C(1409305403), // FLOOR_W_MM
+ UINT64_C(1174405135), // FLOOR_W_S
+ UINT64_C(1409289019), // FLOOR_W_S_MM
+ UINT64_C(1409289019), // FLOOR_W_S_MMR6
+ UINT64_C(2032140315), // FMADD_D
+ UINT64_C(2030043163), // FMADD_W
+ UINT64_C(2078277659), // FMAX_A_D
+ UINT64_C(2076180507), // FMAX_A_W
+ UINT64_C(2074083355), // FMAX_D
+ UINT64_C(2071986203), // FMAX_W
+ UINT64_C(2069889051), // FMIN_A_D
+ UINT64_C(2067791899), // FMIN_A_W
+ UINT64_C(2065694747), // FMIN_D
+ UINT64_C(2063597595), // FMIN_W
+ UINT64_C(1176502278), // FMOV_D32
+ UINT64_C(1409294459), // FMOV_D32_MM
+ UINT64_C(1176502278), // FMOV_D64
+ UINT64_C(1409294459), // FMOV_D64_MM
+ UINT64_C(1174405126), // FMOV_S
+ UINT64_C(1409286267), // FMOV_S_MM
+ UINT64_C(1409286267), // FMOV_S_MMR6
+ UINT64_C(2036334619), // FMSUB_D
+ UINT64_C(2034237467), // FMSUB_W
+ UINT64_C(2023751707), // FMUL_D
+ UINT64_C(1176502274), // FMUL_D32
+ UINT64_C(1409286576), // FMUL_D32_MM
+ UINT64_C(1176502274), // FMUL_D64
+ UINT64_C(1409286576), // FMUL_D64_MM
+ UINT64_C(1174405122), // FMUL_S
+ UINT64_C(1409286320), // FMUL_S_MM
+ UINT64_C(1409286320), // FMUL_S_MMR6
+ UINT64_C(2021654555), // FMUL_W
+ UINT64_C(1176502279), // FNEG_D32
+ UINT64_C(1409297275), // FNEG_D32_MM
+ UINT64_C(1176502279), // FNEG_D64
+ UINT64_C(1409297275), // FNEG_D64_MM
+ UINT64_C(1174405127), // FNEG_S
+ UINT64_C(1409289083), // FNEG_S_MM
+ UINT64_C(1409289083), // FNEG_S_MMR6
+ UINT64_C(2080374792), // FORK
+ UINT64_C(2066415646), // FRCP_D
+ UINT64_C(2066350110), // FRCP_W
+ UINT64_C(2066546718), // FRINT_D
+ UINT64_C(2066481182), // FRINT_W
+ UINT64_C(2066284574), // FRSQRT_D
+ UINT64_C(2066219038), // FRSQRT_W
+ UINT64_C(2048917530), // FSAF_D
+ UINT64_C(2046820378), // FSAF_W
+ UINT64_C(2057306138), // FSEQ_D
+ UINT64_C(2055208986), // FSEQ_W
+ UINT64_C(2074083354), // FSLE_D
+ UINT64_C(2071986202), // FSLE_W
+ UINT64_C(2065694746), // FSLT_D
+ UINT64_C(2063597594), // FSLT_W
+ UINT64_C(2061500444), // FSNE_D
+ UINT64_C(2059403292), // FSNE_W
+ UINT64_C(2053111836), // FSOR_D
+ UINT64_C(2051014684), // FSOR_W
+ UINT64_C(2066153502), // FSQRT_D
+ UINT64_C(1176502276), // FSQRT_D32
+ UINT64_C(1409305147), // FSQRT_D32_MM
+ UINT64_C(1176502276), // FSQRT_D64
+ UINT64_C(1409305147), // FSQRT_D64_MM
+ UINT64_C(1174405124), // FSQRT_S
+ UINT64_C(1409288763), // FSQRT_S_MM
+ UINT64_C(2066087966), // FSQRT_W
+ UINT64_C(2019557403), // FSUB_D
+ UINT64_C(1176502273), // FSUB_D32
+ UINT64_C(1409286512), // FSUB_D32_MM
+ UINT64_C(1176502273), // FSUB_D64
+ UINT64_C(1409286512), // FSUB_D64_MM
+ UINT64_C(1174405121), // FSUB_S
+ UINT64_C(1409286256), // FSUB_S_MM
+ UINT64_C(1409286256), // FSUB_S_MMR6
+ UINT64_C(2017460251), // FSUB_W
+ UINT64_C(2061500442), // FSUEQ_D
+ UINT64_C(2059403290), // FSUEQ_W
+ UINT64_C(2078277658), // FSULE_D
+ UINT64_C(2076180506), // FSULE_W
+ UINT64_C(2069889050), // FSULT_D
+ UINT64_C(2067791898), // FSULT_W
+ UINT64_C(2057306140), // FSUNE_D
+ UINT64_C(2055208988), // FSUNE_W
+ UINT64_C(2053111834), // FSUN_D
+ UINT64_C(2051014682), // FSUN_W
+ UINT64_C(2067333150), // FTINT_S_D
+ UINT64_C(2067267614), // FTINT_S_W
+ UINT64_C(2067464222), // FTINT_U_D
+ UINT64_C(2067398686), // FTINT_U_W
+ UINT64_C(2055208987), // FTQ_H
+ UINT64_C(2057306139), // FTQ_W
+ UINT64_C(2065891358), // FTRUNC_S_D
+ UINT64_C(2065825822), // FTRUNC_S_W
+ UINT64_C(2066022430), // FTRUNC_U_D
+ UINT64_C(2065956894), // FTRUNC_U_W
+ UINT64_C(2080374845), // GINVI
+ UINT64_C(24956), // GINVI_MMR6
+ UINT64_C(2080374973), // GINVT
+ UINT64_C(29052), // GINVT_MMR6
+ UINT64_C(2053111829), // HADD_S_D
+ UINT64_C(2048917525), // HADD_S_H
+ UINT64_C(2051014677), // HADD_S_W
+ UINT64_C(2061500437), // HADD_U_D
+ UINT64_C(2057306133), // HADD_U_H
+ UINT64_C(2059403285), // HADD_U_W
+ UINT64_C(2069889045), // HSUB_S_D
+ UINT64_C(2065694741), // HSUB_S_H
+ UINT64_C(2067791893), // HSUB_S_W
+ UINT64_C(2078277653), // HSUB_U_D
+ UINT64_C(2074083349), // HSUB_U_H
+ UINT64_C(2076180501), // HSUB_U_W
+ UINT64_C(1107296296), // HYPCALL
+ UINT64_C(50044), // HYPCALL_MM
+ UINT64_C(2063597588), // ILVEV_B
+ UINT64_C(2069889044), // ILVEV_D
+ UINT64_C(2065694740), // ILVEV_H
+ UINT64_C(2067791892), // ILVEV_W
+ UINT64_C(2046820372), // ILVL_B
+ UINT64_C(2053111828), // ILVL_D
+ UINT64_C(2048917524), // ILVL_H
+ UINT64_C(2051014676), // ILVL_W
+ UINT64_C(2071986196), // ILVOD_B
+ UINT64_C(2078277652), // ILVOD_D
+ UINT64_C(2074083348), // ILVOD_H
+ UINT64_C(2076180500), // ILVOD_W
+ UINT64_C(2055208980), // ILVR_B
+ UINT64_C(2061500436), // ILVR_D
+ UINT64_C(2057306132), // ILVR_H
+ UINT64_C(2059403284), // ILVR_W
+ UINT64_C(2080374788), // INS
+ UINT64_C(2030043161), // INSERT_B
+ UINT64_C(2033713177), // INSERT_D
+ UINT64_C(2032140313), // INSERT_H
+ UINT64_C(2033188889), // INSERT_W
+ UINT64_C(2080374796), // INSV
+ UINT64_C(2034237465), // INSVE_B
+ UINT64_C(2037907481), // INSVE_D
+ UINT64_C(2036334617), // INSVE_H
+ UINT64_C(2037383193), // INSVE_W
+ UINT64_C(16700), // INSV_MM
+ UINT64_C(12), // INS_MM
+ UINT64_C(12), // INS_MMR6
+ UINT64_C(134217728), // J
+ UINT64_C(201326592), // JAL
+ UINT64_C(9), // JALR
+ UINT64_C(17856), // JALR16_MM
+ UINT64_C(9), // JALR64
+ UINT64_C(17419), // JALRC16_MMR6
+ UINT64_C(7996), // JALRC_HB_MMR6
+ UINT64_C(3900), // JALRC_MMR6
+ UINT64_C(17888), // JALRS16_MM
+ UINT64_C(20284), // JALRS_MM
+ UINT64_C(1033), // JALR_HB
+ UINT64_C(1033), // JALR_HB64
+ UINT64_C(3900), // JALR_MM
+ UINT64_C(1946157056), // JALS_MM
+ UINT64_C(1946157056), // JALX
+ UINT64_C(4026531840), // JALX_MM
+ UINT64_C(4093640704), // JAL_MM
+ UINT64_C(4160749568), // JIALC
+ UINT64_C(4160749568), // JIALC64
+ UINT64_C(2147483648), // JIALC_MMR6
+ UINT64_C(3623878656), // JIC
+ UINT64_C(3623878656), // JIC64
+ UINT64_C(2684354560), // JIC_MMR6
+ UINT64_C(8), // JR
+ UINT64_C(17792), // JR16_MM
+ UINT64_C(8), // JR64
+ UINT64_C(18176), // JRADDIUSP
+ UINT64_C(17824), // JRC16_MM
+ UINT64_C(17411), // JRC16_MMR6
+ UINT64_C(17427), // JRCADDIUSP_MMR6
+ UINT64_C(1032), // JR_HB
+ UINT64_C(1032), // JR_HB64
+ UINT64_C(1033), // JR_HB64_R6
+ UINT64_C(1033), // JR_HB_R6
+ UINT64_C(3900), // JR_MM
+ UINT64_C(3556769792), // J_MM
+ UINT64_C(402653184), // Jal16
+ UINT64_C(402653184), // JalB16
+ UINT64_C(59424), // JrRa16
+ UINT64_C(59616), // JrcRa16
+ UINT64_C(59584), // JrcRx16
+ UINT64_C(59392), // JumpLinkReg16
+ UINT64_C(2147483648), // LB
+ UINT64_C(2147483648), // LB64
+ UINT64_C(2080374828), // LBE
+ UINT64_C(1610639360), // LBE_MM
+ UINT64_C(2048), // LBU16_MM
+ UINT64_C(2080375178), // LBUX
+ UINT64_C(549), // LBUX_MM
+ UINT64_C(335544320), // LBU_MMR6
+ UINT64_C(469762048), // LB_MM
+ UINT64_C(469762048), // LB_MMR6
+ UINT64_C(2415919104), // LBu
+ UINT64_C(2415919104), // LBu64
+ UINT64_C(2080374824), // LBuE
+ UINT64_C(1610637312), // LBuE_MM
+ UINT64_C(335544320), // LBu_MM
+ UINT64_C(3690987520), // LD
+ UINT64_C(3556769792), // LDC1
+ UINT64_C(3556769792), // LDC164
+ UINT64_C(3154116608), // LDC1_D64_MMR6
+ UINT64_C(3154116608), // LDC1_MM
+ UINT64_C(3623878656), // LDC2
+ UINT64_C(536879104), // LDC2_MMR6
+ UINT64_C(1237319680), // LDC2_R6
+ UINT64_C(3690987520), // LDC3
+ UINT64_C(2063597575), // LDI_B
+ UINT64_C(2069889031), // LDI_D
+ UINT64_C(2065694727), // LDI_H
+ UINT64_C(2067791879), // LDI_W
+ UINT64_C(1744830464), // LDL
+ UINT64_C(3960995840), // LDPC
+ UINT64_C(1811939328), // LDR
+ UINT64_C(1275068417), // LDXC1
+ UINT64_C(1275068417), // LDXC164
+ UINT64_C(2013265952), // LD_B
+ UINT64_C(2013265955), // LD_D
+ UINT64_C(2013265953), // LD_H
+ UINT64_C(2013265954), // LD_W
+ UINT64_C(603979776), // LEA_ADDiu
+ UINT64_C(1677721600), // LEA_ADDiu64
+ UINT64_C(805306368), // LEA_ADDiu_MM
+ UINT64_C(2214592512), // LH
+ UINT64_C(2214592512), // LH64
+ UINT64_C(2080374829), // LHE
+ UINT64_C(1610639872), // LHE_MM
+ UINT64_C(10240), // LHU16_MM
+ UINT64_C(2080375050), // LHX
+ UINT64_C(357), // LHX_MM
+ UINT64_C(1006632960), // LH_MM
+ UINT64_C(2483027968), // LHu
+ UINT64_C(2483027968), // LHu64
+ UINT64_C(2080374825), // LHuE
+ UINT64_C(1610637824), // LHuE_MM
+ UINT64_C(872415232), // LHu_MM
+ UINT64_C(60416), // LI16_MM
+ UINT64_C(60416), // LI16_MMR6
+ UINT64_C(3221225472), // LL
+ UINT64_C(3221225472), // LL64
+ UINT64_C(2080374838), // LL64_R6
+ UINT64_C(3489660928), // LLD
+ UINT64_C(2080374839), // LLD_R6
+ UINT64_C(2080374830), // LLE
+ UINT64_C(1610640384), // LLE_MM
+ UINT64_C(1610625024), // LL_MM
+ UINT64_C(1610625024), // LL_MMR6
+ UINT64_C(2080374838), // LL_R6
+ UINT64_C(5), // LSA
+ UINT64_C(15), // LSA_MMR6
+ UINT64_C(5), // LSA_R6
+ UINT64_C(268435456), // LUI_MMR6
+ UINT64_C(1275068421), // LUXC1
+ UINT64_C(1275068421), // LUXC164
+ UINT64_C(1409286472), // LUXC1_MM
+ UINT64_C(1006632960), // LUi
+ UINT64_C(1006632960), // LUi64
+ UINT64_C(1101004800), // LUi_MM
+ UINT64_C(2348810240), // LW
+ UINT64_C(26624), // LW16_MM
+ UINT64_C(2348810240), // LW64
+ UINT64_C(3288334336), // LWC1
+ UINT64_C(2617245696), // LWC1_MM
+ UINT64_C(3355443200), // LWC2
+ UINT64_C(536870912), // LWC2_MMR6
+ UINT64_C(1228931072), // LWC2_R6
+ UINT64_C(3422552064), // LWC3
+ UINT64_C(2348810240), // LWDSP
+ UINT64_C(4227858432), // LWDSP_MM
+ UINT64_C(2080374831), // LWE
+ UINT64_C(1610640896), // LWE_MM
+ UINT64_C(25600), // LWGP_MM
+ UINT64_C(2281701376), // LWL
+ UINT64_C(2281701376), // LWL64
+ UINT64_C(2080374809), // LWLE
+ UINT64_C(1610638336), // LWLE_MM
+ UINT64_C(1610612736), // LWL_MM
+ UINT64_C(17664), // LWM16_MM
+ UINT64_C(17410), // LWM16_MMR6
+ UINT64_C(536891392), // LWM32_MM
+ UINT64_C(3959947264), // LWPC
+ UINT64_C(2013790208), // LWPC_MMR6
+ UINT64_C(536875008), // LWP_MM
+ UINT64_C(2550136832), // LWR
+ UINT64_C(2550136832), // LWR64
+ UINT64_C(2080374810), // LWRE
+ UINT64_C(1610638848), // LWRE_MM
+ UINT64_C(1610616832), // LWR_MM
+ UINT64_C(18432), // LWSP_MM
+ UINT64_C(3960471552), // LWUPC
+ UINT64_C(1610670080), // LWU_MM
+ UINT64_C(2080374794), // LWX
+ UINT64_C(1275068416), // LWXC1
+ UINT64_C(1409286216), // LWXC1_MM
+ UINT64_C(280), // LWXS_MM
+ UINT64_C(421), // LWX_MM
+ UINT64_C(4227858432), // LW_MM
+ UINT64_C(4227858432), // LW_MMR6
+ UINT64_C(2617245696), // LWu
+ UINT64_C(4026570752), // LbRxRyOffMemX16
+ UINT64_C(4026572800), // LbuRxRyOffMemX16
+ UINT64_C(4026572800), // LhRxRyOffMemX16
+ UINT64_C(4026572800), // LhuRxRyOffMemX16
+ UINT64_C(26624), // LiRxImm16
+ UINT64_C(4026558464), // LiRxImmAlignX16
+ UINT64_C(4026558464), // LiRxImmX16
+ UINT64_C(45056), // LwRxPcTcp16
+ UINT64_C(4026576896), // LwRxPcTcpX16
+ UINT64_C(4026570752), // LwRxRyOffMemX16
+ UINT64_C(4026568704), // LwRxSpImmX16
+ UINT64_C(1879048192), // MADD
+ UINT64_C(1176502296), // MADDF_D
+ UINT64_C(1409287096), // MADDF_D_MMR6
+ UINT64_C(1174405144), // MADDF_S
+ UINT64_C(1409286584), // MADDF_S_MMR6
+ UINT64_C(2067791900), // MADDR_Q_H
+ UINT64_C(2069889052), // MADDR_Q_W
+ UINT64_C(1879048193), // MADDU
+ UINT64_C(1879048193), // MADDU_DSP
+ UINT64_C(6844), // MADDU_DSP_MM
+ UINT64_C(56124), // MADDU_MM
+ UINT64_C(2021654546), // MADDV_B
+ UINT64_C(2027946002), // MADDV_D
+ UINT64_C(2023751698), // MADDV_H
+ UINT64_C(2025848850), // MADDV_W
+ UINT64_C(1275068449), // MADD_D32
+ UINT64_C(1409286153), // MADD_D32_MM
+ UINT64_C(1275068449), // MADD_D64
+ UINT64_C(1879048192), // MADD_DSP
+ UINT64_C(2748), // MADD_DSP_MM
+ UINT64_C(52028), // MADD_MM
+ UINT64_C(2034237468), // MADD_Q_H
+ UINT64_C(2036334620), // MADD_Q_W
+ UINT64_C(1275068448), // MADD_S
+ UINT64_C(1409286145), // MADD_S_MM
+ UINT64_C(2080375856), // MAQ_SA_W_PHL
+ UINT64_C(14972), // MAQ_SA_W_PHL_MM
+ UINT64_C(2080375984), // MAQ_SA_W_PHR
+ UINT64_C(10876), // MAQ_SA_W_PHR_MM
+ UINT64_C(2080376112), // MAQ_S_W_PHL
+ UINT64_C(6780), // MAQ_S_W_PHL_MM
+ UINT64_C(2080376240), // MAQ_S_W_PHR
+ UINT64_C(2684), // MAQ_S_W_PHR_MM
+ UINT64_C(1176502303), // MAXA_D
+ UINT64_C(1409286699), // MAXA_D_MMR6
+ UINT64_C(1174405151), // MAXA_S
+ UINT64_C(1409286187), // MAXA_S_MMR6
+ UINT64_C(2030043142), // MAXI_S_B
+ UINT64_C(2036334598), // MAXI_S_D
+ UINT64_C(2032140294), // MAXI_S_H
+ UINT64_C(2034237446), // MAXI_S_W
+ UINT64_C(2038431750), // MAXI_U_B
+ UINT64_C(2044723206), // MAXI_U_D
+ UINT64_C(2040528902), // MAXI_U_H
+ UINT64_C(2042626054), // MAXI_U_W
+ UINT64_C(2063597582), // MAX_A_B
+ UINT64_C(2069889038), // MAX_A_D
+ UINT64_C(2065694734), // MAX_A_H
+ UINT64_C(2067791886), // MAX_A_W
+ UINT64_C(1176502301), // MAX_D
+ UINT64_C(1409286667), // MAX_D_MMR6
+ UINT64_C(1174405149), // MAX_S
+ UINT64_C(2030043150), // MAX_S_B
+ UINT64_C(2036334606), // MAX_S_D
+ UINT64_C(2032140302), // MAX_S_H
+ UINT64_C(1409286155), // MAX_S_MMR6
+ UINT64_C(2034237454), // MAX_S_W
+ UINT64_C(2038431758), // MAX_U_B
+ UINT64_C(2044723214), // MAX_U_D
+ UINT64_C(2040528910), // MAX_U_H
+ UINT64_C(2042626062), // MAX_U_W
+ UINT64_C(1073741824), // MFC0
+ UINT64_C(252), // MFC0_MMR6
+ UINT64_C(1140850688), // MFC1
+ UINT64_C(1140850688), // MFC1_D64
+ UINT64_C(1409294395), // MFC1_MM
+ UINT64_C(1409294395), // MFC1_MMR6
+ UINT64_C(1207959552), // MFC2
+ UINT64_C(19772), // MFC2_MMR6
+ UINT64_C(1080033280), // MFGC0
+ UINT64_C(1276), // MFGC0_MM
+ UINT64_C(244), // MFHC0_MMR6
+ UINT64_C(1147142144), // MFHC1_D32
+ UINT64_C(1409298491), // MFHC1_D32_MM
+ UINT64_C(1147142144), // MFHC1_D64
+ UINT64_C(1409298491), // MFHC1_D64_MM
+ UINT64_C(36156), // MFHC2_MMR6
+ UINT64_C(1080034304), // MFHGC0
+ UINT64_C(1268), // MFHGC0_MM
+ UINT64_C(16), // MFHI
+ UINT64_C(17920), // MFHI16_MM
+ UINT64_C(16), // MFHI64
+ UINT64_C(16), // MFHI_DSP
+ UINT64_C(124), // MFHI_DSP_MM
+ UINT64_C(3452), // MFHI_MM
+ UINT64_C(18), // MFLO
+ UINT64_C(17984), // MFLO16_MM
+ UINT64_C(18), // MFLO64
+ UINT64_C(18), // MFLO_DSP
+ UINT64_C(4220), // MFLO_DSP_MM
+ UINT64_C(7548), // MFLO_MM
+ UINT64_C(1090519040), // MFTR
+ UINT64_C(1176502302), // MINA_D
+ UINT64_C(1409286691), // MINA_D_MMR6
+ UINT64_C(1174405150), // MINA_S
+ UINT64_C(1409286179), // MINA_S_MMR6
+ UINT64_C(2046820358), // MINI_S_B
+ UINT64_C(2053111814), // MINI_S_D
+ UINT64_C(2048917510), // MINI_S_H
+ UINT64_C(2051014662), // MINI_S_W
+ UINT64_C(2055208966), // MINI_U_B
+ UINT64_C(2061500422), // MINI_U_D
+ UINT64_C(2057306118), // MINI_U_H
+ UINT64_C(2059403270), // MINI_U_W
+ UINT64_C(2071986190), // MIN_A_B
+ UINT64_C(2078277646), // MIN_A_D
+ UINT64_C(2074083342), // MIN_A_H
+ UINT64_C(2076180494), // MIN_A_W
+ UINT64_C(1176502300), // MIN_D
+ UINT64_C(1409286659), // MIN_D_MMR6
+ UINT64_C(1174405148), // MIN_S
+ UINT64_C(2046820366), // MIN_S_B
+ UINT64_C(2053111822), // MIN_S_D
+ UINT64_C(2048917518), // MIN_S_H
+ UINT64_C(1409286147), // MIN_S_MMR6
+ UINT64_C(2051014670), // MIN_S_W
+ UINT64_C(2055208974), // MIN_U_B
+ UINT64_C(2061500430), // MIN_U_D
+ UINT64_C(2057306126), // MIN_U_H
+ UINT64_C(2059403278), // MIN_U_W
+ UINT64_C(218), // MOD
+ UINT64_C(2080375952), // MODSUB
+ UINT64_C(661), // MODSUB_MM
+ UINT64_C(219), // MODU
+ UINT64_C(472), // MODU_MMR6
+ UINT64_C(344), // MOD_MMR6
+ UINT64_C(2063597586), // MOD_S_B
+ UINT64_C(2069889042), // MOD_S_D
+ UINT64_C(2065694738), // MOD_S_H
+ UINT64_C(2067791890), // MOD_S_W
+ UINT64_C(2071986194), // MOD_U_B
+ UINT64_C(2078277650), // MOD_U_D
+ UINT64_C(2074083346), // MOD_U_H
+ UINT64_C(2076180498), // MOD_U_W
+ UINT64_C(3072), // MOVE16_MM
+ UINT64_C(3072), // MOVE16_MMR6
+ UINT64_C(33792), // MOVEP_MM
+ UINT64_C(17412), // MOVEP_MMR6
+ UINT64_C(2025717785), // MOVE_V
+ UINT64_C(1176502289), // MOVF_D32
+ UINT64_C(1409286688), // MOVF_D32_MM
+ UINT64_C(1176502289), // MOVF_D64
+ UINT64_C(1), // MOVF_I
+ UINT64_C(1), // MOVF_I64
+ UINT64_C(1409286523), // MOVF_I_MM
+ UINT64_C(1174405137), // MOVF_S
+ UINT64_C(1409286176), // MOVF_S_MM
+ UINT64_C(1176502291), // MOVN_I64_D64
+ UINT64_C(11), // MOVN_I64_I
+ UINT64_C(11), // MOVN_I64_I64
+ UINT64_C(1174405139), // MOVN_I64_S
+ UINT64_C(1176502291), // MOVN_I_D32
+ UINT64_C(1409286456), // MOVN_I_D32_MM
+ UINT64_C(1176502291), // MOVN_I_D64
+ UINT64_C(11), // MOVN_I_I
+ UINT64_C(11), // MOVN_I_I64
+ UINT64_C(24), // MOVN_I_MM
+ UINT64_C(1174405139), // MOVN_I_S
+ UINT64_C(1409286200), // MOVN_I_S_MM
+ UINT64_C(1176567825), // MOVT_D32
+ UINT64_C(1409286752), // MOVT_D32_MM
+ UINT64_C(1176567825), // MOVT_D64
+ UINT64_C(65537), // MOVT_I
+ UINT64_C(65537), // MOVT_I64
+ UINT64_C(1409288571), // MOVT_I_MM
+ UINT64_C(1174470673), // MOVT_S
+ UINT64_C(1409286240), // MOVT_S_MM
+ UINT64_C(1176502290), // MOVZ_I64_D64
+ UINT64_C(10), // MOVZ_I64_I
+ UINT64_C(10), // MOVZ_I64_I64
+ UINT64_C(1174405138), // MOVZ_I64_S
+ UINT64_C(1176502290), // MOVZ_I_D32
+ UINT64_C(1409286520), // MOVZ_I_D32_MM
+ UINT64_C(1176502290), // MOVZ_I_D64
+ UINT64_C(10), // MOVZ_I_I
+ UINT64_C(10), // MOVZ_I_I64
+ UINT64_C(88), // MOVZ_I_MM
+ UINT64_C(1174405138), // MOVZ_I_S
+ UINT64_C(1409286264), // MOVZ_I_S_MM
+ UINT64_C(1879048196), // MSUB
+ UINT64_C(1176502297), // MSUBF_D
+ UINT64_C(1409287160), // MSUBF_D_MMR6
+ UINT64_C(1174405145), // MSUBF_S
+ UINT64_C(1409286648), // MSUBF_S_MMR6
+ UINT64_C(2071986204), // MSUBR_Q_H
+ UINT64_C(2074083356), // MSUBR_Q_W
+ UINT64_C(1879048197), // MSUBU
+ UINT64_C(1879048197), // MSUBU_DSP
+ UINT64_C(15036), // MSUBU_DSP_MM
+ UINT64_C(64316), // MSUBU_MM
+ UINT64_C(2030043154), // MSUBV_B
+ UINT64_C(2036334610), // MSUBV_D
+ UINT64_C(2032140306), // MSUBV_H
+ UINT64_C(2034237458), // MSUBV_W
+ UINT64_C(1275068457), // MSUB_D32
+ UINT64_C(1409286185), // MSUB_D32_MM
+ UINT64_C(1275068457), // MSUB_D64
+ UINT64_C(1879048196), // MSUB_DSP
+ UINT64_C(10940), // MSUB_DSP_MM
+ UINT64_C(60220), // MSUB_MM
+ UINT64_C(2038431772), // MSUB_Q_H
+ UINT64_C(2040528924), // MSUB_Q_W
+ UINT64_C(1275068456), // MSUB_S
+ UINT64_C(1409286177), // MSUB_S_MM
+ UINT64_C(1082130432), // MTC0
+ UINT64_C(764), // MTC0_MMR6
+ UINT64_C(1149239296), // MTC1
+ UINT64_C(1149239296), // MTC1_D64
+ UINT64_C(1409296443), // MTC1_MM
+ UINT64_C(1409296443), // MTC1_MMR6
+ UINT64_C(1216348160), // MTC2
+ UINT64_C(23868), // MTC2_MMR6
+ UINT64_C(1080033792), // MTGC0
+ UINT64_C(1788), // MTGC0_MM
+ UINT64_C(756), // MTHC0_MMR6
+ UINT64_C(1155530752), // MTHC1_D32
+ UINT64_C(1409300539), // MTHC1_D32_MM
+ UINT64_C(1155530752), // MTHC1_D64
+ UINT64_C(1409300539), // MTHC1_D64_MM
+ UINT64_C(40252), // MTHC2_MMR6
+ UINT64_C(1080034816), // MTHGC0
+ UINT64_C(1780), // MTHGC0_MM
+ UINT64_C(17), // MTHI
+ UINT64_C(17), // MTHI64
+ UINT64_C(17), // MTHI_DSP
+ UINT64_C(8316), // MTHI_DSP_MM
+ UINT64_C(11644), // MTHI_MM
+ UINT64_C(2080376824), // MTHLIP
+ UINT64_C(636), // MTHLIP_MM
+ UINT64_C(19), // MTLO
+ UINT64_C(19), // MTLO64
+ UINT64_C(19), // MTLO_DSP
+ UINT64_C(12412), // MTLO_DSP_MM
+ UINT64_C(15740), // MTLO_MM
+ UINT64_C(1879048200), // MTM0
+ UINT64_C(1879048204), // MTM1
+ UINT64_C(1879048205), // MTM2
+ UINT64_C(1879048201), // MTP0
+ UINT64_C(1879048202), // MTP1
+ UINT64_C(1879048203), // MTP2
+ UINT64_C(1098907648), // MTTR
+ UINT64_C(216), // MUH
+ UINT64_C(217), // MUHU
+ UINT64_C(216), // MUHU_MMR6
+ UINT64_C(88), // MUH_MMR6
+ UINT64_C(1879048194), // MUL
+ UINT64_C(2080376592), // MULEQ_S_W_PHL
+ UINT64_C(37), // MULEQ_S_W_PHL_MM
+ UINT64_C(2080376656), // MULEQ_S_W_PHR
+ UINT64_C(101), // MULEQ_S_W_PHR_MM
+ UINT64_C(2080375184), // MULEU_S_PH_QBL
+ UINT64_C(149), // MULEU_S_PH_QBL_MM
+ UINT64_C(2080375248), // MULEU_S_PH_QBR
+ UINT64_C(213), // MULEU_S_PH_QBR_MM
+ UINT64_C(2080376784), // MULQ_RS_PH
+ UINT64_C(277), // MULQ_RS_PH_MM
+ UINT64_C(2080376280), // MULQ_RS_W
+ UINT64_C(405), // MULQ_RS_W_MMR2
+ UINT64_C(2080376720), // MULQ_S_PH
+ UINT64_C(341), // MULQ_S_PH_MMR2
+ UINT64_C(2080376216), // MULQ_S_W
+ UINT64_C(469), // MULQ_S_W_MMR2
+ UINT64_C(2063597596), // MULR_Q_H
+ UINT64_C(2065694748), // MULR_Q_W
+ UINT64_C(2080375216), // MULSAQ_S_W_PH
+ UINT64_C(15548), // MULSAQ_S_W_PH_MM
+ UINT64_C(2080374960), // MULSA_W_PH
+ UINT64_C(11452), // MULSA_W_PH_MMR2
+ UINT64_C(24), // MULT
+ UINT64_C(25), // MULTU_DSP
+ UINT64_C(7356), // MULTU_DSP_MM
+ UINT64_C(24), // MULT_DSP
+ UINT64_C(3260), // MULT_DSP_MM
+ UINT64_C(35644), // MULT_MM
+ UINT64_C(25), // MULTu
+ UINT64_C(39740), // MULTu_MM
+ UINT64_C(153), // MULU
+ UINT64_C(152), // MULU_MMR6
+ UINT64_C(2013265938), // MULV_B
+ UINT64_C(2019557394), // MULV_D
+ UINT64_C(2015363090), // MULV_H
+ UINT64_C(2017460242), // MULV_W
+ UINT64_C(528), // MUL_MM
+ UINT64_C(24), // MUL_MMR6
+ UINT64_C(2080375576), // MUL_PH
+ UINT64_C(45), // MUL_PH_MMR2
+ UINT64_C(2030043164), // MUL_Q_H
+ UINT64_C(2032140316), // MUL_Q_W
+ UINT64_C(152), // MUL_R6
+ UINT64_C(2080375704), // MUL_S_PH
+ UINT64_C(1069), // MUL_S_PH_MMR2
+ UINT64_C(59408), // Mfhi16
+ UINT64_C(59410), // Mflo16
+ UINT64_C(25856), // Move32R16
+ UINT64_C(26368), // MoveR3216
+ UINT64_C(2064121886), // NLOC_B
+ UINT64_C(2064318494), // NLOC_D
+ UINT64_C(2064187422), // NLOC_H
+ UINT64_C(2064252958), // NLOC_W
+ UINT64_C(2064384030), // NLZC_B
+ UINT64_C(2064580638), // NLZC_D
+ UINT64_C(2064449566), // NLZC_H
+ UINT64_C(2064515102), // NLZC_W
+ UINT64_C(1275068465), // NMADD_D32
+ UINT64_C(1409286154), // NMADD_D32_MM
+ UINT64_C(1275068465), // NMADD_D64
+ UINT64_C(1275068464), // NMADD_S
+ UINT64_C(1409286146), // NMADD_S_MM
+ UINT64_C(1275068473), // NMSUB_D32
+ UINT64_C(1409286186), // NMSUB_D32_MM
+ UINT64_C(1275068473), // NMSUB_D64
+ UINT64_C(1275068472), // NMSUB_S
+ UINT64_C(1409286178), // NMSUB_S_MM
+ UINT64_C(39), // NOR
+ UINT64_C(39), // NOR64
+ UINT64_C(2046820352), // NORI_B
+ UINT64_C(720), // NOR_MM
+ UINT64_C(720), // NOR_MMR6
+ UINT64_C(2017460254), // NOR_V
+ UINT64_C(17408), // NOT16_MM
+ UINT64_C(17408), // NOT16_MMR6
+ UINT64_C(59421), // NegRxRy16
+ UINT64_C(59407), // NotRxRy16
+ UINT64_C(37), // OR
+ UINT64_C(17600), // OR16_MM
+ UINT64_C(17417), // OR16_MMR6
+ UINT64_C(37), // OR64
+ UINT64_C(2030043136), // ORI_B
+ UINT64_C(1342177280), // ORI_MMR6
+ UINT64_C(656), // OR_MM
+ UINT64_C(656), // OR_MMR6
+ UINT64_C(2015363102), // OR_V
+ UINT64_C(872415232), // ORi
+ UINT64_C(872415232), // ORi64
+ UINT64_C(1342177280), // ORi_MM
+ UINT64_C(59405), // OrRxRxRy16
+ UINT64_C(2080375697), // PACKRL_PH
+ UINT64_C(429), // PACKRL_PH_MM
+ UINT64_C(320), // PAUSE
+ UINT64_C(10240), // PAUSE_MM
+ UINT64_C(10240), // PAUSE_MMR6
+ UINT64_C(2030043156), // PCKEV_B
+ UINT64_C(2036334612), // PCKEV_D
+ UINT64_C(2032140308), // PCKEV_H
+ UINT64_C(2034237460), // PCKEV_W
+ UINT64_C(2038431764), // PCKOD_B
+ UINT64_C(2044723220), // PCKOD_D
+ UINT64_C(2040528916), // PCKOD_H
+ UINT64_C(2042626068), // PCKOD_W
+ UINT64_C(2063859742), // PCNT_B
+ UINT64_C(2064056350), // PCNT_D
+ UINT64_C(2063925278), // PCNT_H
+ UINT64_C(2063990814), // PCNT_W
+ UINT64_C(2080375505), // PICK_PH
+ UINT64_C(557), // PICK_PH_MM
+ UINT64_C(2080374993), // PICK_QB
+ UINT64_C(493), // PICK_QB_MM
+ UINT64_C(1879048236), // POP
+ UINT64_C(2080375058), // PRECEQU_PH_QBL
+ UINT64_C(2080375186), // PRECEQU_PH_QBLA
+ UINT64_C(29500), // PRECEQU_PH_QBLA_MM
+ UINT64_C(28988), // PRECEQU_PH_QBL_MM
+ UINT64_C(2080375122), // PRECEQU_PH_QBR
+ UINT64_C(2080375250), // PRECEQU_PH_QBRA
+ UINT64_C(37692), // PRECEQU_PH_QBRA_MM
+ UINT64_C(37180), // PRECEQU_PH_QBR_MM
+ UINT64_C(2080375570), // PRECEQ_W_PHL
+ UINT64_C(20796), // PRECEQ_W_PHL_MM
+ UINT64_C(2080375634), // PRECEQ_W_PHR
+ UINT64_C(24892), // PRECEQ_W_PHR_MM
+ UINT64_C(2080376594), // PRECEU_PH_QBL
+ UINT64_C(2080376722), // PRECEU_PH_QBLA
+ UINT64_C(45884), // PRECEU_PH_QBLA_MM
+ UINT64_C(45372), // PRECEU_PH_QBL_MM
+ UINT64_C(2080376658), // PRECEU_PH_QBR
+ UINT64_C(2080376786), // PRECEU_PH_QBRA
+ UINT64_C(54076), // PRECEU_PH_QBRA_MM
+ UINT64_C(53564), // PRECEU_PH_QBR_MM
+ UINT64_C(2080375761), // PRECRQU_S_QB_PH
+ UINT64_C(365), // PRECRQU_S_QB_PH_MM
+ UINT64_C(2080376081), // PRECRQ_PH_W
+ UINT64_C(237), // PRECRQ_PH_W_MM
+ UINT64_C(2080375569), // PRECRQ_QB_PH
+ UINT64_C(173), // PRECRQ_QB_PH_MM
+ UINT64_C(2080376145), // PRECRQ_RS_PH_W
+ UINT64_C(301), // PRECRQ_RS_PH_W_MM
+ UINT64_C(2080375633), // PRECR_QB_PH
+ UINT64_C(109), // PRECR_QB_PH_MMR2
+ UINT64_C(2080376721), // PRECR_SRA_PH_W
+ UINT64_C(973), // PRECR_SRA_PH_W_MMR2
+ UINT64_C(2080376785), // PRECR_SRA_R_PH_W
+ UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2
+ UINT64_C(3422552064), // PREF
+ UINT64_C(2080374819), // PREFE
+ UINT64_C(1610654720), // PREFE_MM
+ UINT64_C(1409286560), // PREFX_MM
+ UINT64_C(1610620928), // PREF_MM
+ UINT64_C(1610620928), // PREF_MMR6
+ UINT64_C(2080374837), // PREF_R6
+ UINT64_C(2080374897), // PREPEND
+ UINT64_C(597), // PREPEND_MMR2
+ UINT64_C(2080376080), // RADDU_W_QB
+ UINT64_C(61756), // RADDU_W_QB_MM
+ UINT64_C(2080375992), // RDDSP
+ UINT64_C(1660), // RDDSP_MM
+ UINT64_C(2080374843), // RDHWR
+ UINT64_C(2080374843), // RDHWR64
+ UINT64_C(27452), // RDHWR_MM
+ UINT64_C(448), // RDHWR_MMR6
+ UINT64_C(57724), // RDPGPR_MMR6
+ UINT64_C(1176502293), // RECIP_D32
+ UINT64_C(1409307195), // RECIP_D32_MM
+ UINT64_C(1176502293), // RECIP_D64
+ UINT64_C(1409307195), // RECIP_D64_MM
+ UINT64_C(1174405141), // RECIP_S
+ UINT64_C(1409290811), // RECIP_S_MM
+ UINT64_C(2080375506), // REPLV_PH
+ UINT64_C(828), // REPLV_PH_MM
+ UINT64_C(2080374994), // REPLV_QB
+ UINT64_C(4924), // REPLV_QB_MM
+ UINT64_C(2080375442), // REPL_PH
+ UINT64_C(61), // REPL_PH_MM
+ UINT64_C(2080374930), // REPL_QB
+ UINT64_C(1532), // REPL_QB_MM
+ UINT64_C(1176502298), // RINT_D
+ UINT64_C(1409286688), // RINT_D_MMR6
+ UINT64_C(1174405146), // RINT_S
+ UINT64_C(1409286176), // RINT_S_MMR6
+ UINT64_C(2097154), // ROTR
+ UINT64_C(70), // ROTRV
+ UINT64_C(208), // ROTRV_MM
+ UINT64_C(192), // ROTR_MM
+ UINT64_C(1176502280), // ROUND_L_D64
+ UINT64_C(1409315643), // ROUND_L_D_MMR6
+ UINT64_C(1174405128), // ROUND_L_S
+ UINT64_C(1409299259), // ROUND_L_S_MMR6
+ UINT64_C(1176502284), // ROUND_W_D32
+ UINT64_C(1176502284), // ROUND_W_D64
+ UINT64_C(1409317691), // ROUND_W_D_MMR6
+ UINT64_C(1409317691), // ROUND_W_MM
+ UINT64_C(1174405132), // ROUND_W_S
+ UINT64_C(1409301307), // ROUND_W_S_MM
+ UINT64_C(1409301307), // ROUND_W_S_MMR6
+ UINT64_C(1176502294), // RSQRT_D32
+ UINT64_C(1409303099), // RSQRT_D32_MM
+ UINT64_C(1176502294), // RSQRT_D64
+ UINT64_C(1409303099), // RSQRT_D64_MM
+ UINT64_C(1174405142), // RSQRT_S
+ UINT64_C(1409286715), // RSQRT_S_MM
+ UINT64_C(25728), // Restore16
+ UINT64_C(25728), // RestoreX16
+ UINT64_C(2020605962), // SAT_S_B
+ UINT64_C(2013265930), // SAT_S_D
+ UINT64_C(2019557386), // SAT_S_H
+ UINT64_C(2017460234), // SAT_S_W
+ UINT64_C(2028994570), // SAT_U_B
+ UINT64_C(2021654538), // SAT_U_D
+ UINT64_C(2027945994), // SAT_U_H
+ UINT64_C(2025848842), // SAT_U_W
+ UINT64_C(2684354560), // SB
+ UINT64_C(34816), // SB16_MM
+ UINT64_C(34816), // SB16_MMR6
+ UINT64_C(2684354560), // SB64
+ UINT64_C(2080374812), // SBE
+ UINT64_C(1610655744), // SBE_MM
+ UINT64_C(402653184), // SB_MM
+ UINT64_C(402653184), // SB_MMR6
+ UINT64_C(3758096384), // SC
+ UINT64_C(3758096384), // SC64
+ UINT64_C(2080374822), // SC64_R6
+ UINT64_C(4026531840), // SCD
+ UINT64_C(2080374823), // SCD_R6
+ UINT64_C(2080374814), // SCE
+ UINT64_C(1610656768), // SCE_MM
+ UINT64_C(1610657792), // SC_MM
+ UINT64_C(1610657792), // SC_MMR6
+ UINT64_C(2080374822), // SC_R6
+ UINT64_C(4227858432), // SD
+ UINT64_C(1879048255), // SDBBP
+ UINT64_C(18112), // SDBBP16_MM
+ UINT64_C(17467), // SDBBP16_MMR6
+ UINT64_C(56188), // SDBBP_MM
+ UINT64_C(56188), // SDBBP_MMR6
+ UINT64_C(14), // SDBBP_R6
+ UINT64_C(4093640704), // SDC1
+ UINT64_C(4093640704), // SDC164
+ UINT64_C(3087007744), // SDC1_D64_MMR6
+ UINT64_C(3087007744), // SDC1_MM
+ UINT64_C(4160749568), // SDC2
+ UINT64_C(536911872), // SDC2_MMR6
+ UINT64_C(1239416832), // SDC2_R6
+ UINT64_C(4227858432), // SDC3
+ UINT64_C(26), // SDIV
+ UINT64_C(43836), // SDIV_MM
+ UINT64_C(2952790016), // SDL
+ UINT64_C(3019898880), // SDR
+ UINT64_C(1275068425), // SDXC1
+ UINT64_C(1275068425), // SDXC164
+ UINT64_C(2080375840), // SEB
+ UINT64_C(2080375840), // SEB64
+ UINT64_C(11068), // SEB_MM
+ UINT64_C(2080376352), // SEH
+ UINT64_C(2080376352), // SEH64
+ UINT64_C(15164), // SEH_MM
+ UINT64_C(53), // SELEQZ
+ UINT64_C(53), // SELEQZ64
+ UINT64_C(1176502292), // SELEQZ_D
+ UINT64_C(1409286712), // SELEQZ_D_MMR6
+ UINT64_C(320), // SELEQZ_MMR6
+ UINT64_C(1174405140), // SELEQZ_S
+ UINT64_C(1409286200), // SELEQZ_S_MMR6
+ UINT64_C(55), // SELNEZ
+ UINT64_C(55), // SELNEZ64
+ UINT64_C(1176502295), // SELNEZ_D
+ UINT64_C(1409286776), // SELNEZ_D_MMR6
+ UINT64_C(384), // SELNEZ_MMR6
+ UINT64_C(1174405143), // SELNEZ_S
+ UINT64_C(1409286264), // SELNEZ_S_MMR6
+ UINT64_C(1176502288), // SEL_D
+ UINT64_C(1409286840), // SEL_D_MMR6
+ UINT64_C(1174405136), // SEL_S
+ UINT64_C(1409286328), // SEL_S_MMR6
+ UINT64_C(1879048234), // SEQ
+ UINT64_C(1879048238), // SEQi
+ UINT64_C(2751463424), // SH
+ UINT64_C(43008), // SH16_MM
+ UINT64_C(43008), // SH16_MMR6
+ UINT64_C(2751463424), // SH64
+ UINT64_C(2080374813), // SHE
+ UINT64_C(1610656256), // SHE_MM
+ UINT64_C(2013265922), // SHF_B
+ UINT64_C(2030043138), // SHF_H
+ UINT64_C(2046820354), // SHF_W
+ UINT64_C(2080376504), // SHILO
+ UINT64_C(2080376568), // SHILOV
+ UINT64_C(4732), // SHILOV_MM
+ UINT64_C(29), // SHILO_MM
+ UINT64_C(2080375443), // SHLLV_PH
+ UINT64_C(14), // SHLLV_PH_MM
+ UINT64_C(2080374931), // SHLLV_QB
+ UINT64_C(917), // SHLLV_QB_MM
+ UINT64_C(2080375699), // SHLLV_S_PH
+ UINT64_C(1038), // SHLLV_S_PH_MM
+ UINT64_C(2080376211), // SHLLV_S_W
+ UINT64_C(981), // SHLLV_S_W_MM
+ UINT64_C(2080375315), // SHLL_PH
+ UINT64_C(949), // SHLL_PH_MM
+ UINT64_C(2080374803), // SHLL_QB
+ UINT64_C(2172), // SHLL_QB_MM
+ UINT64_C(2080375571), // SHLL_S_PH
+ UINT64_C(2997), // SHLL_S_PH_MM
+ UINT64_C(2080376083), // SHLL_S_W
+ UINT64_C(1013), // SHLL_S_W_MM
+ UINT64_C(2080375507), // SHRAV_PH
+ UINT64_C(397), // SHRAV_PH_MM
+ UINT64_C(2080375187), // SHRAV_QB
+ UINT64_C(461), // SHRAV_QB_MMR2
+ UINT64_C(2080375763), // SHRAV_R_PH
+ UINT64_C(1421), // SHRAV_R_PH_MM
+ UINT64_C(2080375251), // SHRAV_R_QB
+ UINT64_C(1485), // SHRAV_R_QB_MMR2
+ UINT64_C(2080376275), // SHRAV_R_W
+ UINT64_C(725), // SHRAV_R_W_MM
+ UINT64_C(2080375379), // SHRA_PH
+ UINT64_C(821), // SHRA_PH_MM
+ UINT64_C(2080375059), // SHRA_QB
+ UINT64_C(508), // SHRA_QB_MMR2
+ UINT64_C(2080375635), // SHRA_R_PH
+ UINT64_C(1845), // SHRA_R_PH_MM
+ UINT64_C(2080375123), // SHRA_R_QB
+ UINT64_C(4604), // SHRA_R_QB_MMR2
+ UINT64_C(2080376147), // SHRA_R_W
+ UINT64_C(757), // SHRA_R_W_MM
+ UINT64_C(2080376531), // SHRLV_PH
+ UINT64_C(789), // SHRLV_PH_MMR2
+ UINT64_C(2080374995), // SHRLV_QB
+ UINT64_C(853), // SHRLV_QB_MM
+ UINT64_C(2080376403), // SHRL_PH
+ UINT64_C(1020), // SHRL_PH_MMR2
+ UINT64_C(2080374867), // SHRL_QB
+ UINT64_C(6268), // SHRL_QB_MM
+ UINT64_C(939524096), // SH_MM
+ UINT64_C(939524096), // SH_MMR6
+ UINT64_C(2013265945), // SLDI_B
+ UINT64_C(2016935961), // SLDI_D
+ UINT64_C(2015363097), // SLDI_H
+ UINT64_C(2016411673), // SLDI_W
+ UINT64_C(2013265940), // SLD_B
+ UINT64_C(2019557396), // SLD_D
+ UINT64_C(2015363092), // SLD_H
+ UINT64_C(2017460244), // SLD_W
+ UINT64_C(0), // SLL
+ UINT64_C(9216), // SLL16_MM
+ UINT64_C(9216), // SLL16_MMR6
+ UINT64_C(0), // SLL64_32
+ UINT64_C(0), // SLL64_64
+ UINT64_C(2020605961), // SLLI_B
+ UINT64_C(2013265929), // SLLI_D
+ UINT64_C(2019557385), // SLLI_H
+ UINT64_C(2017460233), // SLLI_W
+ UINT64_C(4), // SLLV
+ UINT64_C(16), // SLLV_MM
+ UINT64_C(2013265933), // SLL_B
+ UINT64_C(2019557389), // SLL_D
+ UINT64_C(2015363085), // SLL_H
+ UINT64_C(0), // SLL_MM
+ UINT64_C(0), // SLL_MMR6
+ UINT64_C(2017460237), // SLL_W
+ UINT64_C(42), // SLT
+ UINT64_C(42), // SLT64
+ UINT64_C(848), // SLT_MM
+ UINT64_C(671088640), // SLTi
+ UINT64_C(671088640), // SLTi64
+ UINT64_C(2415919104), // SLTi_MM
+ UINT64_C(738197504), // SLTiu
+ UINT64_C(738197504), // SLTiu64
+ UINT64_C(2952790016), // SLTiu_MM
+ UINT64_C(43), // SLTu
+ UINT64_C(43), // SLTu64
+ UINT64_C(912), // SLTu_MM
+ UINT64_C(1879048235), // SNE
+ UINT64_C(1879048239), // SNEi
+ UINT64_C(2017460249), // SPLATI_B
+ UINT64_C(2021130265), // SPLATI_D
+ UINT64_C(2019557401), // SPLATI_H
+ UINT64_C(2020605977), // SPLATI_W
+ UINT64_C(2021654548), // SPLAT_B
+ UINT64_C(2027946004), // SPLAT_D
+ UINT64_C(2023751700), // SPLAT_H
+ UINT64_C(2025848852), // SPLAT_W
+ UINT64_C(3), // SRA
+ UINT64_C(2028994569), // SRAI_B
+ UINT64_C(2021654537), // SRAI_D
+ UINT64_C(2027945993), // SRAI_H
+ UINT64_C(2025848841), // SRAI_W
+ UINT64_C(2037383178), // SRARI_B
+ UINT64_C(2030043146), // SRARI_D
+ UINT64_C(2036334602), // SRARI_H
+ UINT64_C(2034237450), // SRARI_W
+ UINT64_C(2021654549), // SRAR_B
+ UINT64_C(2027946005), // SRAR_D
+ UINT64_C(2023751701), // SRAR_H
+ UINT64_C(2025848853), // SRAR_W
+ UINT64_C(7), // SRAV
+ UINT64_C(144), // SRAV_MM
+ UINT64_C(2021654541), // SRA_B
+ UINT64_C(2027945997), // SRA_D
+ UINT64_C(2023751693), // SRA_H
+ UINT64_C(128), // SRA_MM
+ UINT64_C(2025848845), // SRA_W
+ UINT64_C(2), // SRL
+ UINT64_C(9217), // SRL16_MM
+ UINT64_C(9217), // SRL16_MMR6
+ UINT64_C(2037383177), // SRLI_B
+ UINT64_C(2030043145), // SRLI_D
+ UINT64_C(2036334601), // SRLI_H
+ UINT64_C(2034237449), // SRLI_W
+ UINT64_C(2045771786), // SRLRI_B
+ UINT64_C(2038431754), // SRLRI_D
+ UINT64_C(2044723210), // SRLRI_H
+ UINT64_C(2042626058), // SRLRI_W
+ UINT64_C(2030043157), // SRLR_B
+ UINT64_C(2036334613), // SRLR_D
+ UINT64_C(2032140309), // SRLR_H
+ UINT64_C(2034237461), // SRLR_W
+ UINT64_C(6), // SRLV
+ UINT64_C(80), // SRLV_MM
+ UINT64_C(2030043149), // SRL_B
+ UINT64_C(2036334605), // SRL_D
+ UINT64_C(2032140301), // SRL_H
+ UINT64_C(64), // SRL_MM
+ UINT64_C(2034237453), // SRL_W
+ UINT64_C(64), // SSNOP
+ UINT64_C(2048), // SSNOP_MM
+ UINT64_C(2048), // SSNOP_MMR6
+ UINT64_C(2013265956), // ST_B
+ UINT64_C(2013265959), // ST_D
+ UINT64_C(2013265957), // ST_H
+ UINT64_C(2013265958), // ST_W
+ UINT64_C(34), // SUB
+ UINT64_C(2080375384), // SUBQH_PH
+ UINT64_C(589), // SUBQH_PH_MMR2
+ UINT64_C(2080375512), // SUBQH_R_PH
+ UINT64_C(1613), // SUBQH_R_PH_MMR2
+ UINT64_C(2080376024), // SUBQH_R_W
+ UINT64_C(1677), // SUBQH_R_W_MMR2
+ UINT64_C(2080375896), // SUBQH_W
+ UINT64_C(653), // SUBQH_W_MMR2
+ UINT64_C(2080375504), // SUBQ_PH
+ UINT64_C(525), // SUBQ_PH_MM
+ UINT64_C(2080375760), // SUBQ_S_PH
+ UINT64_C(1549), // SUBQ_S_PH_MM
+ UINT64_C(2080376272), // SUBQ_S_W
+ UINT64_C(837), // SUBQ_S_W_MM
+ UINT64_C(2030043153), // SUBSUS_U_B
+ UINT64_C(2036334609), // SUBSUS_U_D
+ UINT64_C(2032140305), // SUBSUS_U_H
+ UINT64_C(2034237457), // SUBSUS_U_W
+ UINT64_C(2038431761), // SUBSUU_S_B
+ UINT64_C(2044723217), // SUBSUU_S_D
+ UINT64_C(2040528913), // SUBSUU_S_H
+ UINT64_C(2042626065), // SUBSUU_S_W
+ UINT64_C(2013265937), // SUBS_S_B
+ UINT64_C(2019557393), // SUBS_S_D
+ UINT64_C(2015363089), // SUBS_S_H
+ UINT64_C(2017460241), // SUBS_S_W
+ UINT64_C(2021654545), // SUBS_U_B
+ UINT64_C(2027946001), // SUBS_U_D
+ UINT64_C(2023751697), // SUBS_U_H
+ UINT64_C(2025848849), // SUBS_U_W
+ UINT64_C(1025), // SUBU16_MM
+ UINT64_C(1025), // SUBU16_MMR6
+ UINT64_C(2080374872), // SUBUH_QB
+ UINT64_C(845), // SUBUH_QB_MMR2
+ UINT64_C(2080375000), // SUBUH_R_QB
+ UINT64_C(1869), // SUBUH_R_QB_MMR2
+ UINT64_C(464), // SUBU_MMR6
+ UINT64_C(2080375376), // SUBU_PH
+ UINT64_C(781), // SUBU_PH_MMR2
+ UINT64_C(2080374864), // SUBU_QB
+ UINT64_C(717), // SUBU_QB_MM
+ UINT64_C(2080375632), // SUBU_S_PH
+ UINT64_C(1805), // SUBU_S_PH_MMR2
+ UINT64_C(2080375120), // SUBU_S_QB
+ UINT64_C(1741), // SUBU_S_QB_MM
+ UINT64_C(2021654534), // SUBVI_B
+ UINT64_C(2027945990), // SUBVI_D
+ UINT64_C(2023751686), // SUBVI_H
+ UINT64_C(2025848838), // SUBVI_W
+ UINT64_C(2021654542), // SUBV_B
+ UINT64_C(2027945998), // SUBV_D
+ UINT64_C(2023751694), // SUBV_H
+ UINT64_C(2025848846), // SUBV_W
+ UINT64_C(400), // SUB_MM
+ UINT64_C(400), // SUB_MMR6
+ UINT64_C(35), // SUBu
+ UINT64_C(464), // SUBu_MM
+ UINT64_C(1275068429), // SUXC1
+ UINT64_C(1275068429), // SUXC164
+ UINT64_C(1409286536), // SUXC1_MM
+ UINT64_C(2885681152), // SW
+ UINT64_C(59392), // SW16_MM
+ UINT64_C(59392), // SW16_MMR6
+ UINT64_C(2885681152), // SW64
+ UINT64_C(3825205248), // SWC1
+ UINT64_C(2550136832), // SWC1_MM
+ UINT64_C(3892314112), // SWC2
+ UINT64_C(536903680), // SWC2_MMR6
+ UINT64_C(1231028224), // SWC2_R6
+ UINT64_C(3959422976), // SWC3
+ UINT64_C(2885681152), // SWDSP
+ UINT64_C(4160749568), // SWDSP_MM
+ UINT64_C(2080374815), // SWE
+ UINT64_C(1610657280), // SWE_MM
+ UINT64_C(2818572288), // SWL
+ UINT64_C(2818572288), // SWL64
+ UINT64_C(2080374817), // SWLE
+ UINT64_C(1610653696), // SWLE_MM
+ UINT64_C(1610645504), // SWL_MM
+ UINT64_C(17728), // SWM16_MM
+ UINT64_C(17418), // SWM16_MMR6
+ UINT64_C(536924160), // SWM32_MM
+ UINT64_C(536907776), // SWP_MM
+ UINT64_C(3087007744), // SWR
+ UINT64_C(3087007744), // SWR64
+ UINT64_C(2080374818), // SWRE
+ UINT64_C(1610654208), // SWRE_MM
+ UINT64_C(1610649600), // SWR_MM
+ UINT64_C(51200), // SWSP_MM
+ UINT64_C(51200), // SWSP_MMR6
+ UINT64_C(1275068424), // SWXC1
+ UINT64_C(1409286280), // SWXC1_MM
+ UINT64_C(4160749568), // SW_MM
+ UINT64_C(4160749568), // SW_MMR6
+ UINT64_C(15), // SYNC
+ UINT64_C(69140480), // SYNCI
+ UINT64_C(1107296256), // SYNCI_MM
+ UINT64_C(1098907648), // SYNCI_MMR6
+ UINT64_C(27516), // SYNC_MM
+ UINT64_C(27516), // SYNC_MMR6
+ UINT64_C(12), // SYSCALL
+ UINT64_C(35708), // SYSCALL_MM
+ UINT64_C(25728), // Save16
+ UINT64_C(25728), // SaveX16
+ UINT64_C(4026580992), // SbRxRyOffMemX16
+ UINT64_C(59537), // SebRx16
+ UINT64_C(59569), // SehRx16
+ UINT64_C(4026583040), // ShRxRyOffMemX16
+ UINT64_C(4026544128), // SllX16
+ UINT64_C(59396), // SllvRxRy16
+ UINT64_C(59394), // SltRxRy16
+ UINT64_C(20480), // SltiRxImm16
+ UINT64_C(4026552320), // SltiRxImmX16
+ UINT64_C(22528), // SltiuRxImm16
+ UINT64_C(4026554368), // SltiuRxImmX16
+ UINT64_C(59395), // SltuRxRy16
+ UINT64_C(4026544131), // SraX16
+ UINT64_C(59399), // SravRxRy16
+ UINT64_C(4026544130), // SrlX16
+ UINT64_C(59398), // SrlvRxRy16
+ UINT64_C(57347), // SubuRxRyRz16
+ UINT64_C(4026587136), // SwRxRyOffMemX16
+ UINT64_C(4026585088), // SwRxSpImmX16
+ UINT64_C(52), // TEQ
+ UINT64_C(67895296), // TEQI
+ UINT64_C(1103101952), // TEQI_MM
+ UINT64_C(60), // TEQ_MM
+ UINT64_C(48), // TGE
+ UINT64_C(67633152), // TGEI
+ UINT64_C(67698688), // TGEIU
+ UINT64_C(1096810496), // TGEIU_MM
+ UINT64_C(1092616192), // TGEI_MM
+ UINT64_C(49), // TGEU
+ UINT64_C(1084), // TGEU_MM
+ UINT64_C(572), // TGE_MM
+ UINT64_C(1107296267), // TLBGINV
+ UINT64_C(1107296268), // TLBGINVF
+ UINT64_C(20860), // TLBGINVF_MM
+ UINT64_C(16764), // TLBGINV_MM
+ UINT64_C(1107296272), // TLBGP
+ UINT64_C(380), // TLBGP_MM
+ UINT64_C(1107296265), // TLBGR
+ UINT64_C(4476), // TLBGR_MM
+ UINT64_C(1107296266), // TLBGWI
+ UINT64_C(8572), // TLBGWI_MM
+ UINT64_C(1107296270), // TLBGWR
+ UINT64_C(12668), // TLBGWR_MM
+ UINT64_C(1107296259), // TLBINV
+ UINT64_C(1107296260), // TLBINVF
+ UINT64_C(21372), // TLBINVF_MMR6
+ UINT64_C(17276), // TLBINV_MMR6
+ UINT64_C(1107296264), // TLBP
+ UINT64_C(892), // TLBP_MM
+ UINT64_C(1107296257), // TLBR
+ UINT64_C(4988), // TLBR_MM
+ UINT64_C(1107296258), // TLBWI
+ UINT64_C(9084), // TLBWI_MM
+ UINT64_C(1107296262), // TLBWR
+ UINT64_C(13180), // TLBWR_MM
+ UINT64_C(50), // TLT
+ UINT64_C(67764224), // TLTI
+ UINT64_C(1094713344), // TLTIU_MM
+ UINT64_C(1090519040), // TLTI_MM
+ UINT64_C(51), // TLTU
+ UINT64_C(2620), // TLTU_MM
+ UINT64_C(2108), // TLT_MM
+ UINT64_C(54), // TNE
+ UINT64_C(68026368), // TNEI
+ UINT64_C(1098907648), // TNEI_MM
+ UINT64_C(3132), // TNE_MM
+ UINT64_C(1176502281), // TRUNC_L_D64
+ UINT64_C(1409311547), // TRUNC_L_D_MMR6
+ UINT64_C(1174405129), // TRUNC_L_S
+ UINT64_C(1409295163), // TRUNC_L_S_MMR6
+ UINT64_C(1176502285), // TRUNC_W_D32
+ UINT64_C(1176502285), // TRUNC_W_D64
+ UINT64_C(1409313595), // TRUNC_W_D_MMR6
+ UINT64_C(1409313595), // TRUNC_W_MM
+ UINT64_C(1174405133), // TRUNC_W_S
+ UINT64_C(1409297211), // TRUNC_W_S_MM
+ UINT64_C(1409297211), // TRUNC_W_S_MMR6
+ UINT64_C(67829760), // TTLTIU
+ UINT64_C(27), // UDIV
+ UINT64_C(47932), // UDIV_MM
+ UINT64_C(1879048209), // V3MULU
+ UINT64_C(1879048208), // VMM0
+ UINT64_C(1879048207), // VMULU
+ UINT64_C(2013265941), // VSHF_B
+ UINT64_C(2019557397), // VSHF_D
+ UINT64_C(2015363093), // VSHF_H
+ UINT64_C(2017460245), // VSHF_W
+ UINT64_C(1107296288), // WAIT
+ UINT64_C(37756), // WAIT_MM
+ UINT64_C(37756), // WAIT_MMR6
+ UINT64_C(2080376056), // WRDSP
+ UINT64_C(5756), // WRDSP_MM
+ UINT64_C(61820), // WRPGPR_MMR6
+ UINT64_C(2080374944), // WSBH
+ UINT64_C(31548), // WSBH_MM
+ UINT64_C(31548), // WSBH_MMR6
+ UINT64_C(38), // XOR
+ UINT64_C(17472), // XOR16_MM
+ UINT64_C(17416), // XOR16_MMR6
+ UINT64_C(38), // XOR64
+ UINT64_C(2063597568), // XORI_B
+ UINT64_C(1879048192), // XORI_MMR6
+ UINT64_C(784), // XOR_MM
+ UINT64_C(784), // XOR_MMR6
+ UINT64_C(2019557406), // XOR_V
+ UINT64_C(939524096), // XORi
+ UINT64_C(939524096), // XORi64
+ UINT64_C(1879048192), // XORi_MM
+ UINT64_C(59406), // XorRxRxRy16
+ UINT64_C(2080374793), // YIELD
+ UINT64_C(0)
+ };
+ const unsigned opcode = MI.getOpcode();
+ uint64_t Value = InstBits[opcode];
+ uint64_t op = 0;
+ (void)op; // suppress warning
+ switch (opcode) {
+ case Mips::Break16:
+ case Mips::DERET:
+ case Mips::DERET_MM:
+ case Mips::DERET_MMR6:
+ case Mips::EHB:
+ case Mips::EHB_MM:
+ case Mips::EHB_MMR6:
+ case Mips::ERET:
+ case Mips::ERETNC:
+ case Mips::ERETNC_MMR6:
+ case Mips::ERET_MM:
+ case Mips::ERET_MMR6:
+ case Mips::JrRa16:
+ case Mips::JrcRa16:
+ case Mips::PAUSE:
+ case Mips::PAUSE_MM:
+ case Mips::PAUSE_MMR6:
+ case Mips::Restore16:
+ case Mips::RestoreX16:
+ case Mips::SSNOP:
+ case Mips::SSNOP_MM:
+ case Mips::SSNOP_MMR6:
+ case Mips::Save16:
+ case Mips::SaveX16:
+ case Mips::TLBGINV:
+ case Mips::TLBGINVF:
+ case Mips::TLBGINVF_MM:
+ case Mips::TLBGINV_MM:
+ case Mips::TLBGP:
+ case Mips::TLBGP_MM:
+ case Mips::TLBGR:
+ case Mips::TLBGR_MM:
+ case Mips::TLBGWI:
+ case Mips::TLBGWI_MM:
+ case Mips::TLBGWR:
+ case Mips::TLBGWR_MM:
+ case Mips::TLBINV:
+ case Mips::TLBINVF:
+ case Mips::TLBINVF_MMR6:
+ case Mips::TLBINV_MMR6:
+ case Mips::TLBP:
+ case Mips::TLBP_MM:
+ case Mips::TLBR:
+ case Mips::TLBR_MM:
+ case Mips::TLBWI:
+ case Mips::TLBWI_MM:
+ case Mips::TLBWR:
+ case Mips::TLBWR_MM:
+ case Mips::WAIT: {
+ break;
+ }
+ case Mips::MTHLIP:
+ case Mips::SHILOV: {
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::DPAQX_SA_W_PH:
+ case Mips::DPAQX_S_W_PH:
+ case Mips::DPAQ_SA_L_W:
+ case Mips::DPAQ_S_W_PH:
+ case Mips::DPAU_H_QBL:
+ case Mips::DPAU_H_QBR:
+ case Mips::DPAX_W_PH:
+ case Mips::DPA_W_PH:
+ case Mips::DPSQX_SA_W_PH:
+ case Mips::DPSQX_S_W_PH:
+ case Mips::DPSQ_SA_L_W:
+ case Mips::DPSQ_S_W_PH:
+ case Mips::DPSU_H_QBL:
+ case Mips::DPSU_H_QBR:
+ case Mips::DPSX_W_PH:
+ case Mips::DPS_W_PH:
+ case Mips::MADDU_DSP:
+ case Mips::MADD_DSP:
+ case Mips::MAQ_SA_W_PHL:
+ case Mips::MAQ_SA_W_PHR:
+ case Mips::MAQ_S_W_PHL:
+ case Mips::MAQ_S_W_PHR:
+ case Mips::MSUBU_DSP:
+ case Mips::MSUB_DSP:
+ case Mips::MULSAQ_S_W_PH:
+ case Mips::MULSA_W_PH:
+ case Mips::MULTU_DSP:
+ case Mips::MULT_DSP: {
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::SHILO: {
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 11;
+ // op: shift
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(63)) << 20;
+ break;
+ }
+ case Mips::CACHEE:
+ case Mips::CACHE_R6:
+ case Mips::PREFE:
+ case Mips::PREF_R6: {
+ // op: addr
+ op = getMemEncoding(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= (op & UINT64_C(511)) << 7;
+ // op: hint
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::SYNCI: {
+ // op: addr
+ op = getMemEncoding(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::CACHE:
+ case Mips::PREF: {
+ // op: addr
+ op = getMemEncoding(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= op & UINT64_C(65535);
+ // op: hint
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::LD_B:
+ case Mips::ST_B: {
+ // op: addr
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 16;
+ Value |= (op & UINT64_C(2031616)) >> 5;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::LBE:
+ case Mips::LBuE:
+ case Mips::LHE:
+ case Mips::LHuE:
+ case Mips::LLE:
+ case Mips::LWE:
+ case Mips::LWLE:
+ case Mips::LWRE:
+ case Mips::SBE:
+ case Mips::SHE:
+ case Mips::SWE:
+ case Mips::SWLE:
+ case Mips::SWRE: {
+ // op: addr
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= (op & UINT64_C(511)) << 7;
+ // op: hint
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::SCE: {
+ // op: addr
+ op = getMemEncoding(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= (op & UINT64_C(511)) << 7;
+ // op: hint
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::LD_H:
+ case Mips::ST_H: {
+ // op: addr
+ op = getMemEncoding<1>(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 16;
+ Value |= (op & UINT64_C(2031616)) >> 5;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::LD_W:
+ case Mips::ST_W: {
+ // op: addr
+ op = getMemEncoding<2>(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 16;
+ Value |= (op & UINT64_C(2031616)) >> 5;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::LD_D:
+ case Mips::ST_D: {
+ // op: addr
+ op = getMemEncoding<3>(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 16;
+ Value |= (op & UINT64_C(2031616)) >> 5;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::CACHE_MM:
+ case Mips::CACHE_MMR6:
+ case Mips::PREF_MM:
+ case Mips::PREF_MMR6: {
+ // op: addr
+ op = getMemEncodingMMImm12(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(4095);
+ // op: hint
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::SYNCI_MM:
+ case Mips::SYNCI_MMR6: {
+ // op: addr
+ op = getMemEncodingMMImm16(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(2097151);
+ break;
+ }
+ case Mips::LBU_MMR6:
+ case Mips::LB_MMR6: {
+ // op: addr
+ op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2097151);
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::CACHEE_MM:
+ case Mips::PREFE_MM: {
+ // op: addr
+ op = getMemEncodingMMImm9(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(511);
+ // op: hint
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::HYPCALL: {
+ // op: code_
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 11;
+ break;
+ }
+ case Mips::HYPCALL_MM:
+ case Mips::SDBBP_MM:
+ case Mips::SDBBP_MMR6:
+ case Mips::SYSCALL_MM:
+ case Mips::WAIT_MM:
+ case Mips::WAIT_MMR6: {
+ // op: code_
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 16;
+ break;
+ }
+ case Mips::SDBBP:
+ case Mips::SDBBP_R6:
+ case Mips::SYSCALL: {
+ // op: code_
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(1048575)) << 6;
+ break;
+ }
+ case Mips::BREAK16_MMR6:
+ case Mips::SDBBP16_MMR6: {
+ // op: code_
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 6;
+ break;
+ }
+ case Mips::BREAK16_MM:
+ case Mips::SDBBP16_MM: {
+ // op: code_
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= op & UINT64_C(15);
+ break;
+ }
+ case Mips::BREAK:
+ case Mips::BREAK_MM:
+ case Mips::BREAK_MMR6: {
+ // op: code_1
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 16;
+ // op: code_2
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 6;
+ break;
+ }
+ case Mips::BC2EQZ:
+ case Mips::BC2NEZ: {
+ // op: ct
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::MOVEP_MMR6: {
+ // op: dst_regs
+ op = getMovePRegPairOpValue(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rt
+ op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ // op: rs
+ op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(4)) << 1;
+ Value |= op & UINT64_C(3);
+ break;
+ }
+ case Mips::MOVEP_MM: {
+ // op: dst_regs
+ op = getMovePRegPairOpValue(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rt
+ op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ // op: rs
+ op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 1;
+ break;
+ }
+ case Mips::BC1F:
+ case Mips::BC1FL:
+ case Mips::BC1T:
+ case Mips::BC1TL: {
+ // op: fcc
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 18;
+ // op: offset
+ op = getBranchTargetOpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BC1F_MM:
+ case Mips::BC1T_MM: {
+ // op: fcc
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 18;
+ // op: offset
+ op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::LUXC1_MM:
+ case Mips::LWXC1_MM: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: base
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: index
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::MOVN_I_D32_MM:
+ case Mips::MOVN_I_S_MM:
+ case Mips::MOVZ_I_D32_MM:
+ case Mips::MOVZ_I_S_MM: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::CEIL_W_MM:
+ case Mips::CEIL_W_S_MM:
+ case Mips::CVT_D32_S_MM:
+ case Mips::CVT_D32_W_MM:
+ case Mips::CVT_D64_S_MM:
+ case Mips::CVT_D64_W_MM:
+ case Mips::CVT_L_D64_MM:
+ case Mips::CVT_L_S_MM:
+ case Mips::CVT_S_D32_MM:
+ case Mips::CVT_S_D64_MM:
+ case Mips::CVT_S_W_MM:
+ case Mips::CVT_W_D32_MM:
+ case Mips::CVT_W_D64_MM:
+ case Mips::CVT_W_S_MM:
+ case Mips::FABS_D32_MM:
+ case Mips::FABS_D64_MM:
+ case Mips::FABS_S_MM:
+ case Mips::FLOOR_W_MM:
+ case Mips::FLOOR_W_S_MM:
+ case Mips::FMOV_D32_MM:
+ case Mips::FMOV_D64_MM:
+ case Mips::FMOV_S_MM:
+ case Mips::FNEG_D32_MM:
+ case Mips::FNEG_D64_MM:
+ case Mips::FNEG_S_MM:
+ case Mips::FSQRT_D32_MM:
+ case Mips::FSQRT_D64_MM:
+ case Mips::FSQRT_S_MM:
+ case Mips::RECIP_D32_MM:
+ case Mips::RECIP_D64_MM:
+ case Mips::RECIP_S_MM:
+ case Mips::ROUND_W_MM:
+ case Mips::ROUND_W_S_MM:
+ case Mips::RSQRT_D32_MM:
+ case Mips::RSQRT_D64_MM:
+ case Mips::RSQRT_S_MM:
+ case Mips::TRUNC_W_MM:
+ case Mips::TRUNC_W_S_MM: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::MOVF_D32_MM:
+ case Mips::MOVF_S_MM:
+ case Mips::MOVT_D32_MM:
+ case Mips::MOVT_S_MM: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fcc
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 13;
+ break;
+ }
+ case Mips::LDXC1:
+ case Mips::LDXC164:
+ case Mips::LUXC1:
+ case Mips::LUXC164:
+ case Mips::LWXC1: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: base
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: index
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::MADD_D32:
+ case Mips::MADD_D64:
+ case Mips::MADD_S:
+ case Mips::MSUB_D32:
+ case Mips::MSUB_D64:
+ case Mips::MSUB_S:
+ case Mips::NMADD_D32:
+ case Mips::NMADD_D64:
+ case Mips::NMADD_S:
+ case Mips::NMSUB_D32:
+ case Mips::NMSUB_D64:
+ case Mips::NMSUB_S: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: fr
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::CEIL_L_D64:
+ case Mips::CEIL_L_S:
+ case Mips::CEIL_W_D32:
+ case Mips::CEIL_W_D64:
+ case Mips::CEIL_W_S:
+ case Mips::CVT_D32_S:
+ case Mips::CVT_D32_W:
+ case Mips::CVT_D64_L:
+ case Mips::CVT_D64_S:
+ case Mips::CVT_D64_W:
+ case Mips::CVT_L_D64:
+ case Mips::CVT_L_S:
+ case Mips::CVT_S_D32:
+ case Mips::CVT_S_D64:
+ case Mips::CVT_S_L:
+ case Mips::CVT_S_W:
+ case Mips::CVT_W_D32:
+ case Mips::CVT_W_D64:
+ case Mips::CVT_W_S:
+ case Mips::FABS_D32:
+ case Mips::FABS_D64:
+ case Mips::FABS_S:
+ case Mips::FLOOR_L_D64:
+ case Mips::FLOOR_L_S:
+ case Mips::FLOOR_W_D32:
+ case Mips::FLOOR_W_D64:
+ case Mips::FLOOR_W_S:
+ case Mips::FMOV_D32:
+ case Mips::FMOV_D64:
+ case Mips::FMOV_S:
+ case Mips::FNEG_D32:
+ case Mips::FNEG_D64:
+ case Mips::FNEG_S:
+ case Mips::FSQRT_D32:
+ case Mips::FSQRT_D64:
+ case Mips::FSQRT_S:
+ case Mips::RECIP_D32:
+ case Mips::RECIP_D64:
+ case Mips::RECIP_S:
+ case Mips::ROUND_L_D64:
+ case Mips::ROUND_L_S:
+ case Mips::ROUND_W_D32:
+ case Mips::ROUND_W_D64:
+ case Mips::ROUND_W_S:
+ case Mips::RSQRT_D32:
+ case Mips::RSQRT_D64:
+ case Mips::RSQRT_S:
+ case Mips::TRUNC_L_D64:
+ case Mips::TRUNC_L_S:
+ case Mips::TRUNC_W_D32:
+ case Mips::TRUNC_W_D64:
+ case Mips::TRUNC_W_S: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::MOVF_D32:
+ case Mips::MOVF_D64:
+ case Mips::MOVF_S:
+ case Mips::MOVT_D32:
+ case Mips::MOVT_D64:
+ case Mips::MOVT_S: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: fcc
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 18;
+ break;
+ }
+ case Mips::CMP_EQ_D:
+ case Mips::CMP_EQ_S:
+ case Mips::CMP_F_D:
+ case Mips::CMP_F_S:
+ case Mips::CMP_LE_D:
+ case Mips::CMP_LE_S:
+ case Mips::CMP_LT_D:
+ case Mips::CMP_LT_S:
+ case Mips::CMP_SAF_D:
+ case Mips::CMP_SAF_S:
+ case Mips::CMP_SEQ_D:
+ case Mips::CMP_SEQ_S:
+ case Mips::CMP_SLE_D:
+ case Mips::CMP_SLE_S:
+ case Mips::CMP_SLT_D:
+ case Mips::CMP_SLT_S:
+ case Mips::CMP_SUEQ_D:
+ case Mips::CMP_SUEQ_S:
+ case Mips::CMP_SULE_D:
+ case Mips::CMP_SULE_S:
+ case Mips::CMP_SULT_D:
+ case Mips::CMP_SULT_S:
+ case Mips::CMP_SUN_D:
+ case Mips::CMP_SUN_S:
+ case Mips::CMP_UEQ_D:
+ case Mips::CMP_UEQ_S:
+ case Mips::CMP_ULE_D:
+ case Mips::CMP_ULE_S:
+ case Mips::CMP_ULT_D:
+ case Mips::CMP_ULT_S:
+ case Mips::CMP_UN_D:
+ case Mips::CMP_UN_S:
+ case Mips::FADD_D32:
+ case Mips::FADD_D64:
+ case Mips::FADD_S:
+ case Mips::FDIV_D32:
+ case Mips::FDIV_D64:
+ case Mips::FDIV_S:
+ case Mips::FMUL_D32:
+ case Mips::FMUL_D64:
+ case Mips::FMUL_S:
+ case Mips::FSUB_D32:
+ case Mips::FSUB_D64:
+ case Mips::FSUB_S: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::MOVN_I64_D64:
+ case Mips::MOVN_I64_S:
+ case Mips::MOVN_I_D32:
+ case Mips::MOVN_I_D64:
+ case Mips::MOVN_I_S:
+ case Mips::MOVZ_I64_D64:
+ case Mips::MOVZ_I64_S:
+ case Mips::MOVZ_I_D32:
+ case Mips::MOVZ_I_D64:
+ case Mips::MOVZ_I_S: {
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::SUXC1_MM:
+ case Mips::SWXC1_MM: {
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: base
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: index
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::SDXC1:
+ case Mips::SDXC164:
+ case Mips::SUXC1:
+ case Mips::SUXC164:
+ case Mips::SWXC1: {
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: base
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: index
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::FCMP_D32:
+ case Mips::FCMP_D64:
+ case Mips::FCMP_S32: {
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: cond
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(15);
+ break;
+ }
+ case Mips::FCMP_D32_MM:
+ case Mips::FCMP_S32_MM: {
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: cond
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 6;
+ break;
+ }
+ case Mips::CLASS_D:
+ case Mips::CLASS_S:
+ case Mips::RINT_D:
+ case Mips::RINT_S: {
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::C_EQ_D32:
+ case Mips::C_EQ_D64:
+ case Mips::C_EQ_S:
+ case Mips::C_F_D32:
+ case Mips::C_F_D64:
+ case Mips::C_F_S:
+ case Mips::C_LE_D32:
+ case Mips::C_LE_D64:
+ case Mips::C_LE_S:
+ case Mips::C_LT_D32:
+ case Mips::C_LT_D64:
+ case Mips::C_LT_S:
+ case Mips::C_NGE_D32:
+ case Mips::C_NGE_D64:
+ case Mips::C_NGE_S:
+ case Mips::C_NGLE_D32:
+ case Mips::C_NGLE_D64:
+ case Mips::C_NGLE_S:
+ case Mips::C_NGL_D32:
+ case Mips::C_NGL_D64:
+ case Mips::C_NGL_S:
+ case Mips::C_NGT_D32:
+ case Mips::C_NGT_D64:
+ case Mips::C_NGT_S:
+ case Mips::C_OLE_D32:
+ case Mips::C_OLE_D64:
+ case Mips::C_OLE_S:
+ case Mips::C_OLT_D32:
+ case Mips::C_OLT_D64:
+ case Mips::C_OLT_S:
+ case Mips::C_SEQ_D32:
+ case Mips::C_SEQ_D64:
+ case Mips::C_SEQ_S:
+ case Mips::C_SF_D32:
+ case Mips::C_SF_D64:
+ case Mips::C_SF_S:
+ case Mips::C_UEQ_D32:
+ case Mips::C_UEQ_D64:
+ case Mips::C_UEQ_S:
+ case Mips::C_ULE_D32:
+ case Mips::C_ULE_D64:
+ case Mips::C_ULE_S:
+ case Mips::C_ULT_D32:
+ case Mips::C_ULT_D64:
+ case Mips::C_ULT_S:
+ case Mips::C_UN_D32:
+ case Mips::C_UN_D64:
+ case Mips::C_UN_S: {
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fcc
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ break;
+ }
+ case Mips::C_EQ_D32_MM:
+ case Mips::C_EQ_D64_MM:
+ case Mips::C_EQ_S_MM:
+ case Mips::C_F_D32_MM:
+ case Mips::C_F_D64_MM:
+ case Mips::C_F_S_MM:
+ case Mips::C_LE_D32_MM:
+ case Mips::C_LE_D64_MM:
+ case Mips::C_LE_S_MM:
+ case Mips::C_LT_D32_MM:
+ case Mips::C_LT_D64_MM:
+ case Mips::C_LT_S_MM:
+ case Mips::C_NGE_D32_MM:
+ case Mips::C_NGE_D64_MM:
+ case Mips::C_NGE_S_MM:
+ case Mips::C_NGLE_D32_MM:
+ case Mips::C_NGLE_D64_MM:
+ case Mips::C_NGLE_S_MM:
+ case Mips::C_NGL_D32_MM:
+ case Mips::C_NGL_D64_MM:
+ case Mips::C_NGL_S_MM:
+ case Mips::C_NGT_D32_MM:
+ case Mips::C_NGT_D64_MM:
+ case Mips::C_NGT_S_MM:
+ case Mips::C_OLE_D32_MM:
+ case Mips::C_OLE_D64_MM:
+ case Mips::C_OLE_S_MM:
+ case Mips::C_OLT_D32_MM:
+ case Mips::C_OLT_D64_MM:
+ case Mips::C_OLT_S_MM:
+ case Mips::C_SEQ_D32_MM:
+ case Mips::C_SEQ_D64_MM:
+ case Mips::C_SEQ_S_MM:
+ case Mips::C_SF_D32_MM:
+ case Mips::C_SF_D64_MM:
+ case Mips::C_SF_S_MM:
+ case Mips::C_UEQ_D32_MM:
+ case Mips::C_UEQ_D64_MM:
+ case Mips::C_UEQ_S_MM:
+ case Mips::C_ULE_D32_MM:
+ case Mips::C_ULE_D64_MM:
+ case Mips::C_ULE_S_MM:
+ case Mips::C_ULT_D32_MM:
+ case Mips::C_ULT_D64_MM:
+ case Mips::C_ULT_S_MM:
+ case Mips::C_UN_D32_MM:
+ case Mips::C_UN_D64_MM:
+ case Mips::C_UN_S_MM: {
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fcc
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 13;
+ break;
+ }
+ case Mips::CLASS_D_MMR6:
+ case Mips::CLASS_S_MMR6:
+ case Mips::RINT_D_MMR6:
+ case Mips::RINT_S_MMR6: {
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::BC1EQZ:
+ case Mips::BC1NEZ: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::LDC1_D64_MMR6:
+ case Mips::SDC1_D64_MMR6: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2097151);
+ break;
+ }
+ case Mips::CEIL_L_D_MMR6:
+ case Mips::CEIL_L_S_MMR6:
+ case Mips::CEIL_W_D_MMR6:
+ case Mips::CEIL_W_S_MMR6:
+ case Mips::CVT_D_L_MMR6:
+ case Mips::CVT_L_D_MMR6:
+ case Mips::CVT_L_S_MMR6:
+ case Mips::CVT_S_L_MMR6:
+ case Mips::CVT_S_W_MMR6:
+ case Mips::CVT_W_S_MMR6:
+ case Mips::FLOOR_L_D_MMR6:
+ case Mips::FLOOR_L_S_MMR6:
+ case Mips::FLOOR_W_D_MMR6:
+ case Mips::FLOOR_W_S_MMR6:
+ case Mips::FMOV_S_MMR6:
+ case Mips::FNEG_S_MMR6:
+ case Mips::ROUND_L_D_MMR6:
+ case Mips::ROUND_L_S_MMR6:
+ case Mips::ROUND_W_D_MMR6:
+ case Mips::ROUND_W_S_MMR6:
+ case Mips::TRUNC_L_D_MMR6:
+ case Mips::TRUNC_L_S_MMR6:
+ case Mips::TRUNC_W_D_MMR6:
+ case Mips::TRUNC_W_S_MMR6: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::FADD_S_MMR6:
+ case Mips::FDIV_S_MMR6:
+ case Mips::FMUL_S_MMR6:
+ case Mips::FSUB_S_MMR6: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::MAXA_D:
+ case Mips::MAXA_S:
+ case Mips::MAX_D:
+ case Mips::MAX_S:
+ case Mips::MINA_D:
+ case Mips::MINA_S:
+ case Mips::MIN_D:
+ case Mips::MIN_S:
+ case Mips::SELEQZ_D:
+ case Mips::SELEQZ_S:
+ case Mips::SELNEZ_D:
+ case Mips::SELNEZ_S: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::CMP_AF_D_MMR6:
+ case Mips::CMP_AF_S_MMR6:
+ case Mips::CMP_EQ_D_MMR6:
+ case Mips::CMP_EQ_S_MMR6:
+ case Mips::CMP_LE_D_MMR6:
+ case Mips::CMP_LE_S_MMR6:
+ case Mips::CMP_LT_D_MMR6:
+ case Mips::CMP_LT_S_MMR6:
+ case Mips::CMP_SAF_D_MMR6:
+ case Mips::CMP_SAF_S_MMR6:
+ case Mips::CMP_SEQ_D_MMR6:
+ case Mips::CMP_SEQ_S_MMR6:
+ case Mips::CMP_SLE_D_MMR6:
+ case Mips::CMP_SLE_S_MMR6:
+ case Mips::CMP_SLT_D_MMR6:
+ case Mips::CMP_SLT_S_MMR6:
+ case Mips::CMP_SUEQ_D_MMR6:
+ case Mips::CMP_SUEQ_S_MMR6:
+ case Mips::CMP_SULE_D_MMR6:
+ case Mips::CMP_SULE_S_MMR6:
+ case Mips::CMP_SULT_D_MMR6:
+ case Mips::CMP_SULT_S_MMR6:
+ case Mips::CMP_SUN_D_MMR6:
+ case Mips::CMP_SUN_S_MMR6:
+ case Mips::CMP_UEQ_D_MMR6:
+ case Mips::CMP_UEQ_S_MMR6:
+ case Mips::CMP_ULE_D_MMR6:
+ case Mips::CMP_ULE_S_MMR6:
+ case Mips::CMP_ULT_D_MMR6:
+ case Mips::CMP_ULT_S_MMR6:
+ case Mips::CMP_UN_D_MMR6:
+ case Mips::CMP_UN_S_MMR6:
+ case Mips::FADD_D32_MM:
+ case Mips::FADD_D64_MM:
+ case Mips::FADD_S_MM:
+ case Mips::FDIV_D32_MM:
+ case Mips::FDIV_D64_MM:
+ case Mips::FDIV_S_MM:
+ case Mips::FMUL_D32_MM:
+ case Mips::FMUL_D64_MM:
+ case Mips::FMUL_S_MM:
+ case Mips::FSUB_D32_MM:
+ case Mips::FSUB_D64_MM:
+ case Mips::FSUB_S_MM:
+ case Mips::MAXA_D_MMR6:
+ case Mips::MAXA_S_MMR6:
+ case Mips::MAX_D_MMR6:
+ case Mips::MAX_S_MMR6:
+ case Mips::MINA_D_MMR6:
+ case Mips::MINA_S_MMR6:
+ case Mips::MIN_D_MMR6:
+ case Mips::MIN_S_MMR6:
+ case Mips::SELEQZ_D_MMR6:
+ case Mips::SELEQZ_S_MMR6:
+ case Mips::SELNEZ_D_MMR6:
+ case Mips::SELNEZ_S_MMR6: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::MADDF_D:
+ case Mips::MADDF_S:
+ case Mips::MSUBF_D:
+ case Mips::MSUBF_S:
+ case Mips::SEL_D:
+ case Mips::SEL_S: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::MADDF_D_MMR6:
+ case Mips::MADDF_S_MMR6:
+ case Mips::MSUBF_D_MMR6:
+ case Mips::MSUBF_S_MMR6:
+ case Mips::SEL_D_MMR6:
+ case Mips::SEL_S_MMR6: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::MADD_D32_MM:
+ case Mips::MADD_S_MM:
+ case Mips::MSUB_D32_MM:
+ case Mips::MSUB_S_MM:
+ case Mips::NMADD_D32_MM:
+ case Mips::NMADD_S_MM:
+ case Mips::NMSUB_D32_MM:
+ case Mips::NMSUB_S_MM: {
+ // op: ft
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: fr
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::ADDVI_B:
+ case Mips::ADDVI_D:
+ case Mips::ADDVI_H:
+ case Mips::ADDVI_W:
+ case Mips::CEQI_B:
+ case Mips::CEQI_D:
+ case Mips::CEQI_H:
+ case Mips::CEQI_W:
+ case Mips::CLEI_S_B:
+ case Mips::CLEI_S_D:
+ case Mips::CLEI_S_H:
+ case Mips::CLEI_S_W:
+ case Mips::CLEI_U_B:
+ case Mips::CLEI_U_D:
+ case Mips::CLEI_U_H:
+ case Mips::CLEI_U_W:
+ case Mips::CLTI_S_B:
+ case Mips::CLTI_S_D:
+ case Mips::CLTI_S_H:
+ case Mips::CLTI_S_W:
+ case Mips::CLTI_U_B:
+ case Mips::CLTI_U_D:
+ case Mips::CLTI_U_H:
+ case Mips::CLTI_U_W:
+ case Mips::MAXI_S_B:
+ case Mips::MAXI_S_D:
+ case Mips::MAXI_S_H:
+ case Mips::MAXI_S_W:
+ case Mips::MAXI_U_B:
+ case Mips::MAXI_U_D:
+ case Mips::MAXI_U_H:
+ case Mips::MAXI_U_W:
+ case Mips::MINI_S_B:
+ case Mips::MINI_S_D:
+ case Mips::MINI_S_H:
+ case Mips::MINI_S_W:
+ case Mips::MINI_U_B:
+ case Mips::MINI_U_D:
+ case Mips::MINI_U_H:
+ case Mips::MINI_U_W:
+ case Mips::SUBVI_B:
+ case Mips::SUBVI_D:
+ case Mips::SUBVI_H:
+ case Mips::SUBVI_W: {
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::ADDIUSP_MM: {
+ // op: imm
+ op = getSImm9AddiuspValue(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(511)) << 1;
+ break;
+ }
+ case Mips::JRCADDIUSP_MMR6: {
+ // op: imm
+ op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 5;
+ break;
+ }
+ case Mips::JRADDIUSP: {
+ // op: imm
+ op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(31);
+ break;
+ }
+ case Mips::Bimm16: {
+ // op: imm11
+ op = getBranchTargetOpValue(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(2047);
+ break;
+ }
+ case Mips::AddiuRxRyOffMemX16: {
+ // op: imm15
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(2032)) << 16;
+ Value |= (op & UINT64_C(30720)) << 5;
+ Value |= op & UINT64_C(15);
+ // op: rx
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ // op: ry
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 5;
+ break;
+ }
+ case Mips::BimmX16: {
+ // op: imm16
+ op = getBranchTargetOpValue(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(2016)) << 16;
+ Value |= (op & UINT64_C(63488)) << 5;
+ Value |= op & UINT64_C(31);
+ break;
+ }
+ case Mips::AddiuSpImmX16:
+ case Mips::BteqzX16:
+ case Mips::BtnezX16: {
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(2016)) << 16;
+ Value |= (op & UINT64_C(63488)) << 5;
+ Value |= op & UINT64_C(31);
+ break;
+ }
+ case Mips::AddiuRxImmX16:
+ case Mips::AddiuRxPcImmX16:
+ case Mips::AddiuRxRxImmX16:
+ case Mips::BeqzRxImmX16:
+ case Mips::BnezRxImmX16:
+ case Mips::CmpiRxImmX16:
+ case Mips::LiRxImmAlignX16:
+ case Mips::LiRxImmX16:
+ case Mips::LwRxPcTcpX16:
+ case Mips::SltiRxImmX16:
+ case Mips::SltiuRxImmX16: {
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(2016)) << 16;
+ Value |= (op & UINT64_C(63488)) << 5;
+ Value |= op & UINT64_C(31);
+ // op: rx
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ break;
+ }
+ case Mips::LbRxRyOffMemX16:
+ case Mips::LbuRxRyOffMemX16:
+ case Mips::LhRxRyOffMemX16:
+ case Mips::LhuRxRyOffMemX16:
+ case Mips::LwRxRyOffMemX16:
+ case Mips::LwRxSpImmX16:
+ case Mips::SbRxRyOffMemX16:
+ case Mips::ShRxRyOffMemX16:
+ case Mips::SwRxRyOffMemX16:
+ case Mips::SwRxSpImmX16: {
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(2016)) << 16;
+ Value |= (op & UINT64_C(63488)) << 5;
+ Value |= op & UINT64_C(31);
+ // op: rx
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ // op: ry
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 5;
+ break;
+ }
+ case Mips::Jal16:
+ case Mips::JalB16: {
+ // op: imm26
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= (op & UINT64_C(65011712)) >> 5;
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::AddiuSpImm16:
+ case Mips::Bteqz16:
+ case Mips::Btnez16: {
+ // op: imm8
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= op & UINT64_C(255);
+ break;
+ }
+ case Mips::PREFX_MM: {
+ // op: index
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: base
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: hint
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::LBUX_MM:
+ case Mips::LHX_MM:
+ case Mips::LWX_MM: {
+ // op: index
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: base
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::COPY_S_D: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(1)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SPLATI_D: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(1)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSVE_D: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(1)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::COPY_S_B:
+ case Mips::COPY_U_B: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SPLATI_B: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSVE_B: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::COPY_S_W:
+ case Mips::COPY_U_W: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SPLATI_W: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSVE_W: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::COPY_S_H:
+ case Mips::COPY_U_H: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SPLATI_H: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSVE_H: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSERT_D: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(1)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SLDI_D: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(1)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSERT_B: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SLDI_B: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSERT_W: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SLDI_W: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSERT_H: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SLDI_H: {
+ // op: n
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::BALC:
+ case Mips::BC: {
+ // op: offset
+ op = getBranchTarget26OpValue(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(67108863);
+ break;
+ }
+ case Mips::BALC_MMR6:
+ case Mips::BC_MMR6: {
+ // op: offset
+ op = getBranchTarget26OpValueMM(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(67108863);
+ break;
+ }
+ case Mips::BAL:
+ case Mips::BPOSGE32: {
+ // op: offset
+ op = getBranchTargetOpValue(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BNZ_B:
+ case Mips::BNZ_D:
+ case Mips::BNZ_H:
+ case Mips::BNZ_V:
+ case Mips::BNZ_W:
+ case Mips::BZ_B:
+ case Mips::BZ_D:
+ case Mips::BZ_H:
+ case Mips::BZ_V:
+ case Mips::BZ_W: {
+ // op: offset
+ op = getBranchTargetOpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ // op: wt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::BPOSGE32C_MMR3: {
+ // op: offset
+ op = getBranchTargetOpValue1SImm16(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BPOSGE32_MM: {
+ // op: offset
+ op = getBranchTargetOpValueMM(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::B16_MM:
+ case Mips::BC16_MMR6: {
+ // op: offset
+ op = getBranchTargetOpValueMMPC10(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(1023);
+ break;
+ }
+ case Mips::Move32R16: {
+ // op: r32
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 5;
+ Value |= op & UINT64_C(24);
+ // op: rz
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(7);
+ break;
+ }
+ case Mips::MFHI:
+ case Mips::MFHI64:
+ case Mips::MFLO:
+ case Mips::MFLO64: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::MFHI_DSP:
+ case Mips::MFLO_DSP: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 21;
+ break;
+ }
+ case Mips::LWXS_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: base
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: index
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::LBUX:
+ case Mips::LHX:
+ case Mips::LWX: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: base
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: index
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::REPL_PH:
+ case Mips::REPL_PH_MM:
+ case Mips::REPL_QB: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 16;
+ break;
+ }
+ case Mips::RDDSP: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: mask
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 16;
+ break;
+ }
+ case Mips::ADDQH_PH_MMR2:
+ case Mips::ADDQH_R_PH_MMR2:
+ case Mips::ADDQH_R_W_MMR2:
+ case Mips::ADDQH_W_MMR2:
+ case Mips::ADDQ_PH_MM:
+ case Mips::ADDQ_S_PH_MM:
+ case Mips::ADDQ_S_W_MM:
+ case Mips::ADDSC_MM:
+ case Mips::ADDUH_QB_MMR2:
+ case Mips::ADDUH_R_QB_MMR2:
+ case Mips::ADDU_PH_MMR2:
+ case Mips::ADDU_QB_MM:
+ case Mips::ADDU_S_PH_MMR2:
+ case Mips::ADDU_S_QB_MM:
+ case Mips::ADDWC_MM:
+ case Mips::CMPGDU_EQ_QB_MMR2:
+ case Mips::CMPGDU_LE_QB_MMR2:
+ case Mips::CMPGDU_LT_QB_MMR2:
+ case Mips::MODSUB_MM:
+ case Mips::MULEQ_S_W_PHL_MM:
+ case Mips::MULEQ_S_W_PHR_MM:
+ case Mips::MULEU_S_PH_QBL_MM:
+ case Mips::MULEU_S_PH_QBR_MM:
+ case Mips::MULQ_RS_PH_MM:
+ case Mips::MULQ_RS_W_MMR2:
+ case Mips::MULQ_S_PH_MMR2:
+ case Mips::MULQ_S_W_MMR2:
+ case Mips::MUL_PH_MMR2:
+ case Mips::MUL_S_PH_MMR2:
+ case Mips::PACKRL_PH_MM:
+ case Mips::PICK_PH_MM:
+ case Mips::PICK_QB_MM:
+ case Mips::PRECRQU_S_QB_PH_MM:
+ case Mips::PRECRQ_PH_W_MM:
+ case Mips::PRECRQ_QB_PH_MM:
+ case Mips::PRECRQ_RS_PH_W_MM:
+ case Mips::PRECR_QB_PH_MMR2:
+ case Mips::SELEQZ_MMR6:
+ case Mips::SELNEZ_MMR6:
+ case Mips::SUBQH_PH_MMR2:
+ case Mips::SUBQH_R_PH_MMR2:
+ case Mips::SUBQH_R_W_MMR2:
+ case Mips::SUBQH_W_MMR2:
+ case Mips::SUBQ_PH_MM:
+ case Mips::SUBQ_S_PH_MM:
+ case Mips::SUBQ_S_W_MM:
+ case Mips::SUBUH_QB_MMR2:
+ case Mips::SUBUH_R_QB_MMR2:
+ case Mips::SUBU_PH_MMR2:
+ case Mips::SUBU_QB_MM:
+ case Mips::SUBU_S_PH_MMR2:
+ case Mips::SUBU_S_QB_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::LSA_MMR6: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm2
+ op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 9;
+ break;
+ }
+ case Mips::CLO_R6:
+ case Mips::CLZ_R6:
+ case Mips::DCLO_R6:
+ case Mips::DCLZ_R6:
+ case Mips::DPOP:
+ case Mips::JALR:
+ case Mips::JALR64:
+ case Mips::JALR_HB:
+ case Mips::JALR_HB64:
+ case Mips::POP:
+ case Mips::RADDU_W_QB: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::MOVF_I:
+ case Mips::MOVF_I64:
+ case Mips::MOVT_I:
+ case Mips::MOVT_I64: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fcc
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 18;
+ break;
+ }
+ case Mips::ADD:
+ case Mips::ADDQH_PH:
+ case Mips::ADDQH_R_PH:
+ case Mips::ADDQH_R_W:
+ case Mips::ADDQH_W:
+ case Mips::ADDQ_PH:
+ case Mips::ADDQ_S_PH:
+ case Mips::ADDQ_S_W:
+ case Mips::ADDSC:
+ case Mips::ADDUH_QB:
+ case Mips::ADDUH_R_QB:
+ case Mips::ADDU_PH:
+ case Mips::ADDU_QB:
+ case Mips::ADDU_S_PH:
+ case Mips::ADDU_S_QB:
+ case Mips::ADDWC:
+ case Mips::ADDu:
+ case Mips::AND:
+ case Mips::AND64:
+ case Mips::BADDu:
+ case Mips::DADD:
+ case Mips::DADDu:
+ case Mips::DDIV:
+ case Mips::DDIVU:
+ case Mips::DIV:
+ case Mips::DIVU:
+ case Mips::DMOD:
+ case Mips::DMODU:
+ case Mips::DMUH:
+ case Mips::DMUHU:
+ case Mips::DMUL:
+ case Mips::DMULU:
+ case Mips::DMUL_R6:
+ case Mips::DSUB:
+ case Mips::DSUBu:
+ case Mips::MOD:
+ case Mips::MODSUB:
+ case Mips::MODU:
+ case Mips::MOVN_I64_I:
+ case Mips::MOVN_I64_I64:
+ case Mips::MOVN_I_I:
+ case Mips::MOVN_I_I64:
+ case Mips::MOVZ_I64_I:
+ case Mips::MOVZ_I64_I64:
+ case Mips::MOVZ_I_I:
+ case Mips::MOVZ_I_I64:
+ case Mips::MUH:
+ case Mips::MUHU:
+ case Mips::MUL:
+ case Mips::MULEQ_S_W_PHL:
+ case Mips::MULEQ_S_W_PHR:
+ case Mips::MULEU_S_PH_QBL:
+ case Mips::MULEU_S_PH_QBR:
+ case Mips::MULQ_RS_PH:
+ case Mips::MULQ_RS_W:
+ case Mips::MULQ_S_PH:
+ case Mips::MULQ_S_W:
+ case Mips::MULU:
+ case Mips::MUL_PH:
+ case Mips::MUL_R6:
+ case Mips::MUL_S_PH:
+ case Mips::NOR:
+ case Mips::NOR64:
+ case Mips::OR:
+ case Mips::OR64:
+ case Mips::SELEQZ:
+ case Mips::SELEQZ64:
+ case Mips::SELNEZ:
+ case Mips::SELNEZ64:
+ case Mips::SEQ:
+ case Mips::SLT:
+ case Mips::SLT64:
+ case Mips::SLTu:
+ case Mips::SLTu64:
+ case Mips::SNE:
+ case Mips::SUB:
+ case Mips::SUBQH_PH:
+ case Mips::SUBQH_R_PH:
+ case Mips::SUBQH_R_W:
+ case Mips::SUBQH_W:
+ case Mips::SUBQ_PH:
+ case Mips::SUBQ_S_PH:
+ case Mips::SUBQ_S_W:
+ case Mips::SUBUH_QB:
+ case Mips::SUBUH_R_QB:
+ case Mips::SUBU_PH:
+ case Mips::SUBU_QB:
+ case Mips::SUBU_S_PH:
+ case Mips::SUBU_S_QB:
+ case Mips::SUBu:
+ case Mips::V3MULU:
+ case Mips::VMM0:
+ case Mips::VMULU:
+ case Mips::XOR:
+ case Mips::XOR64: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::ALIGN: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: bp
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 6;
+ break;
+ }
+ case Mips::ALIGN_MMR6: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: bp
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 9;
+ break;
+ }
+ case Mips::DALIGN: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: bp
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 6;
+ break;
+ }
+ case Mips::DLSA_R6:
+ case Mips::LSA_R6: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: imm2
+ op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 6;
+ break;
+ }
+ case Mips::SHLLV_PH_MM:
+ case Mips::SHLLV_QB_MM:
+ case Mips::SHLLV_S_PH_MM:
+ case Mips::SHLLV_S_W_MM:
+ case Mips::SHRAV_PH_MM:
+ case Mips::SHRAV_QB_MMR2:
+ case Mips::SHRAV_R_PH_MM:
+ case Mips::SHRAV_R_QB_MMR2:
+ case Mips::SHRAV_R_W_MM:
+ case Mips::SHRLV_PH_MMR2:
+ case Mips::SHRLV_QB_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::ABSQ_S_PH:
+ case Mips::ABSQ_S_QB:
+ case Mips::ABSQ_S_W:
+ case Mips::BITREV:
+ case Mips::BITSWAP:
+ case Mips::DBITSWAP:
+ case Mips::DSBH:
+ case Mips::DSHD:
+ case Mips::DSLL64_32:
+ case Mips::PRECEQU_PH_QBL:
+ case Mips::PRECEQU_PH_QBLA:
+ case Mips::PRECEQU_PH_QBR:
+ case Mips::PRECEQU_PH_QBRA:
+ case Mips::PRECEQ_W_PHL:
+ case Mips::PRECEQ_W_PHR:
+ case Mips::PRECEU_PH_QBL:
+ case Mips::PRECEU_PH_QBLA:
+ case Mips::PRECEU_PH_QBR:
+ case Mips::PRECEU_PH_QBRA:
+ case Mips::REPLV_PH:
+ case Mips::REPLV_QB:
+ case Mips::SEB:
+ case Mips::SEB64:
+ case Mips::SEH:
+ case Mips::SEH64:
+ case Mips::SLL64_32:
+ case Mips::SLL64_64:
+ case Mips::WSBH: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::DROTRV:
+ case Mips::DSLLV:
+ case Mips::DSRAV:
+ case Mips::DSRLV:
+ case Mips::ROTRV:
+ case Mips::SLLV:
+ case Mips::SRAV:
+ case Mips::SRLV: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::SHLLV_PH:
+ case Mips::SHLLV_QB:
+ case Mips::SHLLV_S_PH:
+ case Mips::SHLLV_S_W:
+ case Mips::SHLL_PH:
+ case Mips::SHLL_QB:
+ case Mips::SHLL_S_PH:
+ case Mips::SHLL_S_W:
+ case Mips::SHRAV_PH:
+ case Mips::SHRAV_QB:
+ case Mips::SHRAV_R_PH:
+ case Mips::SHRAV_R_QB:
+ case Mips::SHRAV_R_W:
+ case Mips::SHRA_PH:
+ case Mips::SHRA_QB:
+ case Mips::SHRA_R_PH:
+ case Mips::SHRA_R_QB:
+ case Mips::SHRA_R_W:
+ case Mips::SHRLV_PH:
+ case Mips::SHRLV_QB:
+ case Mips::SHRL_PH:
+ case Mips::SHRL_QB: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rs_sa
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::DROTR:
+ case Mips::DROTR32:
+ case Mips::DSLL:
+ case Mips::DSLL32:
+ case Mips::DSRA:
+ case Mips::DSRA32:
+ case Mips::DSRL:
+ case Mips::DSRL32:
+ case Mips::ROTR:
+ case Mips::SLL:
+ case Mips::SRA:
+ case Mips::SRL: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: shamt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::ROTRV_MM:
+ case Mips::SLLV_MM:
+ case Mips::SRAV_MM:
+ case Mips::SRLV_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::ADDU_MMR6:
+ case Mips::ADD_MMR6:
+ case Mips::AND_MMR6:
+ case Mips::DIVU_MMR6:
+ case Mips::DIV_MMR6:
+ case Mips::MODU_MMR6:
+ case Mips::MOD_MMR6:
+ case Mips::MUHU_MMR6:
+ case Mips::MUH_MMR6:
+ case Mips::MULU_MMR6:
+ case Mips::MUL_MMR6:
+ case Mips::NOR_MMR6:
+ case Mips::OR_MMR6:
+ case Mips::SUBU_MMR6:
+ case Mips::SUB_MMR6:
+ case Mips::XOR_MMR6: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::MFHI_MM:
+ case Mips::MFLO_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::BITSWAP_MMR6: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::CLO:
+ case Mips::CLZ:
+ case Mips::DCLO:
+ case Mips::DCLZ: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::CLO_MM:
+ case Mips::CLZ_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::MOVF_I_MM:
+ case Mips::MOVT_I_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fcc
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 13;
+ break;
+ }
+ case Mips::SEB_MM:
+ case Mips::SEH_MM:
+ case Mips::WSBH_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::ROTR_MM:
+ case Mips::SLL_MM:
+ case Mips::SLL_MMR6:
+ case Mips::SRA_MM:
+ case Mips::SRL_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: shamt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::CFCMSA: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: cs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::LI16_MM:
+ case Mips::LI16_MMR6: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(127);
+ break;
+ }
+ case Mips::ADDIUR1SP_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: imm
+ op = getUImm6Lsl2Encoding(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(63)) << 1;
+ break;
+ }
+ case Mips::ADDIUR2_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ // op: imm
+ op = getSImm3Lsa2Value(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 1;
+ break;
+ }
+ case Mips::ANDI16_MM:
+ case Mips::ANDI16_MMR6: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ // op: imm
+ op = getUImm4AndValue(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(15);
+ break;
+ }
+ case Mips::SLL16_MM:
+ case Mips::SLL16_MMR6:
+ case Mips::SRL16_MM:
+ case Mips::SRL16_MMR6: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ // op: shamt
+ op = getUImm3Mod8Encoding(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 1;
+ break;
+ }
+ case Mips::ADDU16_MM:
+ case Mips::SUBU16_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 1;
+ break;
+ }
+ case Mips::MFHI16_MM:
+ case Mips::MFLO16_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= op & UINT64_C(31);
+ break;
+ }
+ case Mips::ADDIUS5_MM: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 5;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 1;
+ break;
+ }
+ case Mips::DVP_MMR6:
+ case Mips::EVP_MMR6:
+ case Mips::JR_MM:
+ case Mips::MTHI_MM:
+ case Mips::MTLO_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::MFHI_DSP_MM:
+ case Mips::MFLO_DSP_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 14;
+ break;
+ }
+ case Mips::TEQI_MM:
+ case Mips::TGEIU_MM:
+ case Mips::TGEI_MM:
+ case Mips::TLTIU_MM:
+ case Mips::TLTI_MM:
+ case Mips::TNEI_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BEQZC_MM:
+ case Mips::BGEZALS_MM:
+ case Mips::BGEZAL_MM:
+ case Mips::BGEZ_MM:
+ case Mips::BGTZ_MM:
+ case Mips::BLEZ_MM:
+ case Mips::BLTZALS_MM:
+ case Mips::BLTZAL_MM:
+ case Mips::BLTZ_MM:
+ case Mips::BNEZC_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::MADDU_MM:
+ case Mips::MADD_MM:
+ case Mips::MSUBU_MM:
+ case Mips::MSUB_MM:
+ case Mips::MULT_MM:
+ case Mips::MULTu_MM:
+ case Mips::SDIV_MM:
+ case Mips::UDIV_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::TEQ_MM:
+ case Mips::TGEU_MM:
+ case Mips::TGE_MM:
+ case Mips::TLTU_MM:
+ case Mips::TLT_MM:
+ case Mips::TNE_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: code_
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 12;
+ break;
+ }
+ case Mips::BEQ_MM:
+ case Mips::BNE_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: offset
+ op = getBranchTargetOpValueMM(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::GINVI_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: type
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 9;
+ break;
+ }
+ case Mips::GINVT_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: type
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 9;
+ break;
+ }
+ case Mips::JR:
+ case Mips::JR64:
+ case Mips::JR_HB:
+ case Mips::JR_HB64:
+ case Mips::JR_HB64_R6:
+ case Mips::JR_HB_R6:
+ case Mips::MTHI:
+ case Mips::MTHI64:
+ case Mips::MTLO:
+ case Mips::MTLO64:
+ case Mips::MTM0:
+ case Mips::MTM1:
+ case Mips::MTM2:
+ case Mips::MTP0:
+ case Mips::MTP1:
+ case Mips::MTP2: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::ALUIPC:
+ case Mips::AUIPC: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::DAHI:
+ case Mips::DATI: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::LDPC: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getSimm18Lsl3Encoding(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(262143);
+ break;
+ }
+ case Mips::ADDIUPC:
+ case Mips::LWPC:
+ case Mips::LWUPC: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(524287);
+ break;
+ }
+ case Mips::TEQI:
+ case Mips::TGEI:
+ case Mips::TGEIU:
+ case Mips::TLTI:
+ case Mips::TNEI:
+ case Mips::TTLTIU: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::WRDSP: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: mask
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 11;
+ break;
+ }
+ case Mips::BEQZC:
+ case Mips::BEQZC64:
+ case Mips::BNEZC:
+ case Mips::BNEZC64: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: offset
+ op = getBranchTarget21OpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2097151);
+ break;
+ }
+ case Mips::BEQZC_MMR6:
+ case Mips::BNEZC_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: offset
+ op = getBranchTarget21OpValueMM(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2097151);
+ break;
+ }
+ case Mips::BGEZ:
+ case Mips::BGEZ64:
+ case Mips::BGEZAL:
+ case Mips::BGEZALL:
+ case Mips::BGEZL:
+ case Mips::BGTZ:
+ case Mips::BGTZ64:
+ case Mips::BGTZL:
+ case Mips::BLEZ:
+ case Mips::BLEZ64:
+ case Mips::BLEZL:
+ case Mips::BLTZ:
+ case Mips::BLTZ64:
+ case Mips::BLTZAL:
+ case Mips::BLTZALL:
+ case Mips::BLTZL: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: offset
+ op = getBranchTargetOpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BBIT0:
+ case Mips::BBIT032:
+ case Mips::BBIT1:
+ case Mips::BBIT132: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: p
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValue(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::CMPU_EQ_QB:
+ case Mips::CMPU_LE_QB:
+ case Mips::CMPU_LT_QB:
+ case Mips::CMP_EQ_PH:
+ case Mips::CMP_LE_PH:
+ case Mips::CMP_LT_PH:
+ case Mips::DMULT:
+ case Mips::DMULTu:
+ case Mips::DSDIV:
+ case Mips::DUDIV:
+ case Mips::MADD:
+ case Mips::MADDU:
+ case Mips::MSUB:
+ case Mips::MSUBU:
+ case Mips::MULT:
+ case Mips::MULTu:
+ case Mips::SDIV:
+ case Mips::UDIV: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::TEQ:
+ case Mips::TGE:
+ case Mips::TGEU:
+ case Mips::TLT:
+ case Mips::TLTU:
+ case Mips::TNE: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: code_
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 6;
+ break;
+ }
+ case Mips::BEQ:
+ case Mips::BEQ64:
+ case Mips::BEQC:
+ case Mips::BEQC64:
+ case Mips::BEQL:
+ case Mips::BGEC:
+ case Mips::BGEC64:
+ case Mips::BGEUC:
+ case Mips::BGEUC64:
+ case Mips::BLTC:
+ case Mips::BLTC64:
+ case Mips::BLTUC:
+ case Mips::BLTUC64:
+ case Mips::BNE:
+ case Mips::BNE64:
+ case Mips::BNEC:
+ case Mips::BNEC64:
+ case Mips::BNEL:
+ case Mips::BNVC:
+ case Mips::BOVC: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValue(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::FORK: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::GINVI: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: type_
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 8;
+ break;
+ }
+ case Mips::GINVT: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: type_
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 8;
+ break;
+ }
+ case Mips::JALRC16_MMR6:
+ case Mips::JRC16_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 5;
+ break;
+ }
+ case Mips::ADDIUPC_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 23;
+ // op: imm
+ op = getSimm23Lsl2Encoding(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(8388607);
+ break;
+ }
+ case Mips::BEQZ16_MM:
+ case Mips::BEQZC16_MMR6:
+ case Mips::BNEZ16_MM:
+ case Mips::BNEZC16_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: offset
+ op = getBranchTarget7OpValueMM(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(127);
+ break;
+ }
+ case Mips::JALR16_MM:
+ case Mips::JALRS16_MM:
+ case Mips::JR16_MM:
+ case Mips::JRC16_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= op & UINT64_C(31);
+ break;
+ }
+ case Mips::CTCMSA: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: cd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::FILL_B:
+ case Mips::FILL_D:
+ case Mips::FILL_H:
+ case Mips::FILL_W: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::MTHI_DSP_MM:
+ case Mips::MTHLIP_MM:
+ case Mips::MTLO_DSP_MM:
+ case Mips::SHILOV_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 14;
+ break;
+ }
+ case Mips::JALRS_MM:
+ case Mips::JALR_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::CLO_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::AUI_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::ADDi_MM:
+ case Mips::ADDiu_MM:
+ case Mips::ANDi_MM:
+ case Mips::ORi_MM:
+ case Mips::XORi_MM: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::MTHI_DSP:
+ case Mips::MTLO_DSP: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 11;
+ break;
+ }
+ case Mips::YIELD: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::CLZ_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::AUI:
+ case Mips::DAUI: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::SEQi:
+ case Mips::SNEi: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: imm10
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 6;
+ break;
+ }
+ case Mips::ADDi:
+ case Mips::ADDiu:
+ case Mips::ANDi:
+ case Mips::ANDi64:
+ case Mips::DADDi:
+ case Mips::DADDiu:
+ case Mips::ORi:
+ case Mips::ORi64:
+ case Mips::XORi:
+ case Mips::XORi64: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::PRECR_SRA_PH_W:
+ case Mips::PRECR_SRA_R_PH_W: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: sa
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::CRC32B:
+ case Mips::CRC32CB:
+ case Mips::CRC32CD:
+ case Mips::CRC32CH:
+ case Mips::CRC32CW:
+ case Mips::CRC32D:
+ case Mips::CRC32H:
+ case Mips::CRC32W: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::CMPGDU_EQ_QB:
+ case Mips::CMPGDU_LE_QB:
+ case Mips::CMPGDU_LT_QB:
+ case Mips::CMPGU_EQ_QB:
+ case Mips::CMPGU_LE_QB:
+ case Mips::CMPGU_LT_QB:
+ case Mips::PACKRL_PH:
+ case Mips::PICK_PH:
+ case Mips::PICK_QB:
+ case Mips::PRECRQU_S_QB_PH:
+ case Mips::PRECRQ_PH_W:
+ case Mips::PRECRQ_QB_PH:
+ case Mips::PRECRQ_RS_PH_W:
+ case Mips::PRECR_QB_PH: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::DLSA:
+ case Mips::LSA: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: sa
+ op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 6;
+ break;
+ }
+ case Mips::ADDU16_MMR6:
+ case Mips::SUBU16_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 1;
+ break;
+ }
+ case Mips::MOVE16_MM:
+ case Mips::MOVE16_MMR6: {
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(31);
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 5;
+ break;
+ }
+ case Mips::DI:
+ case Mips::DI_MM:
+ case Mips::DI_MMR6:
+ case Mips::DMT:
+ case Mips::DVP:
+ case Mips::DVPE:
+ case Mips::EI:
+ case Mips::EI_MM:
+ case Mips::EI_MMR6:
+ case Mips::EMT:
+ case Mips::EVP:
+ case Mips::EVPE: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::EXTP:
+ case Mips::EXTPDP:
+ case Mips::EXTPDPV:
+ case Mips::EXTPV:
+ case Mips::EXTRV_RS_W:
+ case Mips::EXTRV_R_W:
+ case Mips::EXTRV_S_H:
+ case Mips::EXTRV_W:
+ case Mips::EXTR_RS_W:
+ case Mips::EXTR_R_W:
+ case Mips::EXTR_S_H:
+ case Mips::EXTR_W: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 11;
+ // op: shift_rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::LL64_R6:
+ case Mips::LLD_R6:
+ case Mips::LL_R6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: addr
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= (op & UINT64_C(511)) << 7;
+ break;
+ }
+ case Mips::LB:
+ case Mips::LB64:
+ case Mips::LBu:
+ case Mips::LBu64:
+ case Mips::LD:
+ case Mips::LDC1:
+ case Mips::LDC164:
+ case Mips::LDC2:
+ case Mips::LDC3:
+ case Mips::LDL:
+ case Mips::LDR:
+ case Mips::LEA_ADDiu:
+ case Mips::LEA_ADDiu64:
+ case Mips::LH:
+ case Mips::LH64:
+ case Mips::LHu:
+ case Mips::LHu64:
+ case Mips::LL:
+ case Mips::LL64:
+ case Mips::LLD:
+ case Mips::LW:
+ case Mips::LW64:
+ case Mips::LWC1:
+ case Mips::LWC2:
+ case Mips::LWC3:
+ case Mips::LWDSP:
+ case Mips::LWL:
+ case Mips::LWL64:
+ case Mips::LWR:
+ case Mips::LWR64:
+ case Mips::LWu:
+ case Mips::SB:
+ case Mips::SB64:
+ case Mips::SD:
+ case Mips::SDC1:
+ case Mips::SDC164:
+ case Mips::SDC2:
+ case Mips::SDC3:
+ case Mips::SDL:
+ case Mips::SDR:
+ case Mips::SH:
+ case Mips::SH64:
+ case Mips::SW:
+ case Mips::SW64:
+ case Mips::SWC1:
+ case Mips::SWC2:
+ case Mips::SWC3:
+ case Mips::SWDSP:
+ case Mips::SWL:
+ case Mips::SWL64:
+ case Mips::SWR:
+ case Mips::SWR64: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: addr
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::LDC2_R6:
+ case Mips::LWC2_R6:
+ case Mips::SDC2_R6:
+ case Mips::SWC2_R6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: addr
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) >> 5;
+ Value |= op & UINT64_C(2047);
+ break;
+ }
+ case Mips::CFC1:
+ case Mips::DMFC1:
+ case Mips::MFC1:
+ case Mips::MFC1_D64:
+ case Mips::MFHC1_D32:
+ case Mips::MFHC1_D64: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::DMFC2_OCTEON:
+ case Mips::DMTC2_OCTEON:
+ case Mips::LUi:
+ case Mips::LUi64:
+ case Mips::LUi_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BEQZALC:
+ case Mips::BGTZALC:
+ case Mips::BGTZC:
+ case Mips::BGTZC64:
+ case Mips::BLEZALC:
+ case Mips::BLEZC:
+ case Mips::BLEZC64:
+ case Mips::BNEZALC: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BC1EQZC_MMR6:
+ case Mips::BC1NEZC_MMR6:
+ case Mips::BC2EQZC_MMR6:
+ case Mips::BC2NEZC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::JIALC:
+ case Mips::JIALC64:
+ case Mips::JIALC_MMR6:
+ case Mips::JIC:
+ case Mips::JIC64:
+ case Mips::JIC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getJumpOffset16OpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::RDHWR:
+ case Mips::RDHWR64: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: sel
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 6;
+ break;
+ }
+ case Mips::DMFC0:
+ case Mips::DMFC2:
+ case Mips::DMFGC0:
+ case Mips::MFC0:
+ case Mips::MFC2:
+ case Mips::MFGC0:
+ case Mips::MFHGC0: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: sel
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(7);
+ break;
+ }
+ case Mips::SLTi:
+ case Mips::SLTi64:
+ case Mips::SLTiu:
+ case Mips::SLTiu64: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::CINS:
+ case Mips::CINS32:
+ case Mips::CINS64_32:
+ case Mips::CINS_i32:
+ case Mips::EXTS:
+ case Mips::EXTS32: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: pos
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: lenm1
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::DINS:
+ case Mips::DINSM:
+ case Mips::DINSU:
+ case Mips::INS: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: pos
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: size
+ op = getSizeInsEncoding(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::DEXT:
+ case Mips::DEXT64_32:
+ case Mips::DEXTM:
+ case Mips::DEXTU:
+ case Mips::EXT: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: pos
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: size
+ op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::APPEND:
+ case Mips::BALIGN:
+ case Mips::PREPEND: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: sa
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::INSV: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ break;
+ }
+ case Mips::LWU_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(4095);
+ break;
+ }
+ case Mips::LBE_MM:
+ case Mips::LBuE_MM:
+ case Mips::LHE_MM:
+ case Mips::LHuE_MM:
+ case Mips::LLE_MM:
+ case Mips::LWE_MM:
+ case Mips::SBE_MM:
+ case Mips::SHE_MM:
+ case Mips::SWE_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(511);
+ break;
+ }
+ case Mips::LEA_ADDiu_MM:
+ case Mips::LH_MM:
+ case Mips::LHu_MM:
+ case Mips::LWDSP_MM:
+ case Mips::LW_MM:
+ case Mips::LW_MMR6:
+ case Mips::SB_MM:
+ case Mips::SB_MMR6:
+ case Mips::SH_MM:
+ case Mips::SH_MMR6:
+ case Mips::SWDSP_MM:
+ case Mips::SW_MM:
+ case Mips::SW_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncoding(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2097151);
+ break;
+ }
+ case Mips::LWP_MM:
+ case Mips::SWP_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncoding(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(4095);
+ break;
+ }
+ case Mips::LDC2_MMR6:
+ case Mips::LWC2_MMR6:
+ case Mips::SDC2_MMR6:
+ case Mips::SWC2_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncodingMMImm11(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(2047);
+ break;
+ }
+ case Mips::LL_MM:
+ case Mips::LWL_MM:
+ case Mips::LWR_MM:
+ case Mips::SWL_MM:
+ case Mips::SWR_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncodingMMImm12(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(4095);
+ break;
+ }
+ case Mips::LB_MM:
+ case Mips::LBu_MM:
+ case Mips::LDC1_MM:
+ case Mips::LWC1_MM:
+ case Mips::SDC1_MM:
+ case Mips::SWC1_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2097151);
+ break;
+ }
+ case Mips::LL_MMR6:
+ case Mips::LWLE_MM:
+ case Mips::LWRE_MM:
+ case Mips::SWLE_MM:
+ case Mips::SWRE_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncodingMMImm9(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(511);
+ break;
+ }
+ case Mips::CFC1_MM:
+ case Mips::MFC1_MM:
+ case Mips::MFC1_MMR6:
+ case Mips::MFHC1_D32_MM:
+ case Mips::MFHC1_D64_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::REPL_QB_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(255)) << 13;
+ break;
+ }
+ case Mips::ALUIPC_MMR6:
+ case Mips::AUIPC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::EXTPDP_MM:
+ case Mips::EXTP_MM:
+ case Mips::EXTR_RS_W_MM:
+ case Mips::EXTR_R_W_MM:
+ case Mips::EXTR_S_H_MM:
+ case Mips::EXTR_W_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 14;
+ break;
+ }
+ case Mips::ADDIUPC_MMR6:
+ case Mips::LWPC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm
+ op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(524287);
+ break;
+ }
+ case Mips::LUI_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::CFC2_MM:
+ case Mips::MFC2_MMR6:
+ case Mips::MFHC2_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: impl
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::RDDSP_MM:
+ case Mips::WRDSP_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: mask
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(127)) << 14;
+ break;
+ }
+ case Mips::BGTZC_MMR6:
+ case Mips::BLEZC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: offset
+ op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BEQZALC_MMR6:
+ case Mips::BGTZALC_MMR6:
+ case Mips::BLEZALC_MMR6:
+ case Mips::BNEZALC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: offset
+ op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::RDHWR_MM:
+ case Mips::RDPGPR_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::ABSQ_S_PH_MM:
+ case Mips::ABSQ_S_QB_MMR2:
+ case Mips::ABSQ_S_W_MM:
+ case Mips::BITREV_MM:
+ case Mips::JALRC_HB_MMR6:
+ case Mips::JALRC_MMR6:
+ case Mips::PRECEQU_PH_QBLA_MM:
+ case Mips::PRECEQU_PH_QBL_MM:
+ case Mips::PRECEQU_PH_QBRA_MM:
+ case Mips::PRECEQU_PH_QBR_MM:
+ case Mips::PRECEQ_W_PHL_MM:
+ case Mips::PRECEQ_W_PHR_MM:
+ case Mips::PRECEU_PH_QBLA_MM:
+ case Mips::PRECEU_PH_QBL_MM:
+ case Mips::PRECEU_PH_QBRA_MM:
+ case Mips::PRECEU_PH_QBR_MM:
+ case Mips::RADDU_W_QB_MM:
+ case Mips::REPLV_PH_MM:
+ case Mips::REPLV_QB_MM:
+ case Mips::WRPGPR_MMR6:
+ case Mips::WSBH_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::BALIGN_MMR2: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: bp
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 14;
+ break;
+ }
+ case Mips::ADDIU_MMR6:
+ case Mips::ANDI_MMR6:
+ case Mips::ORI_MMR6:
+ case Mips::SLTi_MM:
+ case Mips::SLTiu_MM:
+ case Mips::XORI_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: imm16
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BNVC_MMR6:
+ case Mips::BOVC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValueMMR6(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::INS_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: pos
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: size
+ op = getSizeInsEncoding(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::EXT_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: pos
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: size
+ op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::SHLL_PH_MM:
+ case Mips::SHLL_S_PH_MM:
+ case Mips::SHRA_PH_MM:
+ case Mips::SHRA_R_PH_MM:
+ case Mips::SHRL_PH_MMR2: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: sa
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 12;
+ break;
+ }
+ case Mips::APPEND_MMR2:
+ case Mips::PRECR_SRA_PH_W_MMR2:
+ case Mips::PRECR_SRA_R_PH_W_MMR2:
+ case Mips::PREPEND_MMR2:
+ case Mips::SHLL_S_W_MM:
+ case Mips::SHRA_R_W_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: sa
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::SHLL_QB_MM:
+ case Mips::SHRA_QB_MMR2:
+ case Mips::SHRA_R_QB_MMR2:
+ case Mips::SHRL_QB_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: sa
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 13;
+ break;
+ }
+ case Mips::MFC0_MMR6:
+ case Mips::MFGC0_MM:
+ case Mips::MFHC0_MMR6:
+ case Mips::MFHGC0_MM:
+ case Mips::RDHWR_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: sel
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 11;
+ break;
+ }
+ case Mips::INS_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: size
+ op = getSizeInsEncoding(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: pos
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::EXT_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: size
+ op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: pos
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::INSV_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::EXTPDPV_MM:
+ case Mips::EXTPV_MM:
+ case Mips::EXTRV_RS_W_MM:
+ case Mips::EXTRV_R_W_MM:
+ case Mips::EXTRV_S_H_MM:
+ case Mips::EXTRV_W_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 14;
+ break;
+ }
+ case Mips::BGEZALC:
+ case Mips::BGEZC:
+ case Mips::BGEZC64:
+ case Mips::BLTZALC:
+ case Mips::BLTZC:
+ case Mips::BLTZC64: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValue(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BGEZC_MMR6:
+ case Mips::BLTZC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::BGEZALC_MMR6:
+ case Mips::BLTZALC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::LWSP_MM:
+ case Mips::SWSP_MM:
+ case Mips::SWSP_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 5;
+ // op: offset
+ op = getMemEncodingMMSPImm5Lsl2(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(31);
+ break;
+ }
+ case Mips::NOT16_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 3;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(7);
+ break;
+ }
+ case Mips::LBU16_MM:
+ case Mips::SB16_MM:
+ case Mips::SB16_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: addr
+ op = getMemEncodingMMImm4(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(127);
+ break;
+ }
+ case Mips::LHU16_MM:
+ case Mips::SH16_MM:
+ case Mips::SH16_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: addr
+ op = getMemEncodingMMImm4Lsl1(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(127);
+ break;
+ }
+ case Mips::LW16_MM:
+ case Mips::SW16_MM:
+ case Mips::SW16_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: addr
+ op = getMemEncodingMMImm4Lsl2(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(127);
+ break;
+ }
+ case Mips::LWGP_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: offset
+ op = getMemEncodingMMGPImm7Lsl2(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(127);
+ break;
+ }
+ case Mips::NOT16_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ break;
+ }
+ case Mips::SC64_R6:
+ case Mips::SCD_R6:
+ case Mips::SC_R6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: addr
+ op = getMemEncoding(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= (op & UINT64_C(511)) << 7;
+ break;
+ }
+ case Mips::SC:
+ case Mips::SC64:
+ case Mips::SCD: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: addr
+ op = getMemEncoding(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(2031616)) << 5;
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::CTC1:
+ case Mips::DMTC1:
+ case Mips::MTC1:
+ case Mips::MTC1_D64: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::DMTC0:
+ case Mips::DMTC2:
+ case Mips::DMTGC0:
+ case Mips::MTC0:
+ case Mips::MTC2:
+ case Mips::MTGC0:
+ case Mips::MTHGC0: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: sel
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= op & UINT64_C(7);
+ break;
+ }
+ case Mips::MFTR:
+ case Mips::MTTR: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: u
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(1)) << 5;
+ // op: h
+ op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
+ Value |= (op & UINT64_C(1)) << 4;
+ // op: sel
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= op & UINT64_C(7);
+ break;
+ }
+ case Mips::SCE_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncoding(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(511);
+ break;
+ }
+ case Mips::SC_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncodingMMImm12(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(4095);
+ break;
+ }
+ case Mips::SC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncodingMMImm9(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(511);
+ break;
+ }
+ case Mips::CTC1_MM:
+ case Mips::MTC1_MM:
+ case Mips::MTC1_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::CTC2_MM:
+ case Mips::MTC2_MMR6:
+ case Mips::MTHC2_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: impl
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::CMPU_EQ_QB_MM:
+ case Mips::CMPU_LE_QB_MM:
+ case Mips::CMPU_LT_QB_MM:
+ case Mips::CMP_EQ_PH_MM:
+ case Mips::CMP_LE_PH_MM:
+ case Mips::CMP_LT_PH_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::BEQC_MMR6:
+ case Mips::BGEC_MMR6:
+ case Mips::BGEUC_MMR6:
+ case Mips::BLTC_MMR6:
+ case Mips::BLTUC_MMR6:
+ case Mips::BNEC_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: offset
+ op = getBranchTargetOpValueLsl2MMR6(MI, 2, Fixups, STI);
+ Value |= op & UINT64_C(65535);
+ break;
+ }
+ case Mips::MTC0_MMR6:
+ case Mips::MTGC0_MM:
+ case Mips::MTHC0_MMR6:
+ case Mips::MTHGC0_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: sel
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 11;
+ break;
+ }
+ case Mips::MTHC1_D32:
+ case Mips::MTHC1_D64: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::SPLAT_B:
+ case Mips::SPLAT_D:
+ case Mips::SPLAT_H:
+ case Mips::SPLAT_W: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::MTHC1_D32_MM:
+ case Mips::MTHC1_D64_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: fs
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::DPAQX_SA_W_PH_MMR2:
+ case Mips::DPAQX_S_W_PH_MMR2:
+ case Mips::DPAQ_SA_L_W_MM:
+ case Mips::DPAQ_S_W_PH_MM:
+ case Mips::DPAU_H_QBL_MM:
+ case Mips::DPAU_H_QBR_MM:
+ case Mips::DPAX_W_PH_MMR2:
+ case Mips::DPA_W_PH_MMR2:
+ case Mips::DPSQX_SA_W_PH_MMR2:
+ case Mips::DPSQX_S_W_PH_MMR2:
+ case Mips::DPSQ_SA_L_W_MM:
+ case Mips::DPSQ_S_W_PH_MM:
+ case Mips::DPSU_H_QBL_MM:
+ case Mips::DPSU_H_QBR_MM:
+ case Mips::DPSX_W_PH_MMR2:
+ case Mips::DPS_W_PH_MMR2:
+ case Mips::MADDU_DSP_MM:
+ case Mips::MADD_DSP_MM:
+ case Mips::MAQ_SA_W_PHL_MM:
+ case Mips::MAQ_SA_W_PHR_MM:
+ case Mips::MAQ_S_W_PHL_MM:
+ case Mips::MAQ_S_W_PHR_MM:
+ case Mips::MSUBU_DSP_MM:
+ case Mips::MSUB_DSP_MM:
+ case Mips::MULSAQ_S_W_PH_MM:
+ case Mips::MULSA_W_PH_MMR2:
+ case Mips::MULTU_DSP_MM:
+ case Mips::MULT_DSP_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 14;
+ break;
+ }
+ case Mips::ADD_MM:
+ case Mips::ADDu_MM:
+ case Mips::AND_MM:
+ case Mips::CMPGU_EQ_QB_MM:
+ case Mips::CMPGU_LE_QB_MM:
+ case Mips::CMPGU_LT_QB_MM:
+ case Mips::MOVN_I_MM:
+ case Mips::MOVZ_I_MM:
+ case Mips::MUL_MM:
+ case Mips::NOR_MM:
+ case Mips::OR_MM:
+ case Mips::SLT_MM:
+ case Mips::SLTu_MM:
+ case Mips::SUB_MM:
+ case Mips::SUBu_MM:
+ case Mips::XOR_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ break;
+ }
+ case Mips::AND16_MM:
+ case Mips::OR16_MM:
+ case Mips::XOR16_MM: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 3;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(7);
+ break;
+ }
+ case Mips::AND16_MMR6:
+ case Mips::OR16_MMR6:
+ case Mips::XOR16_MMR6: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 7;
+ // op: rs
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 4;
+ break;
+ }
+ case Mips::SLD_B:
+ case Mips::SLD_D:
+ case Mips::SLD_H:
+ case Mips::SLD_W: {
+ // op: rt
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::LWM32_MM:
+ case Mips::SWM32_MM: {
+ // op: rt
+ op = getRegisterListOpValue(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 21;
+ // op: addr
+ op = getMemEncodingMMImm12(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(2031616);
+ Value |= op & UINT64_C(4095);
+ break;
+ }
+ case Mips::LWM16_MM:
+ case Mips::SWM16_MM: {
+ // op: rt
+ op = getRegisterListOpValue16(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 4;
+ // op: addr
+ op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI);
+ Value |= op & UINT64_C(15);
+ break;
+ }
+ case Mips::LWM16_MMR6:
+ case Mips::SWM16_MMR6: {
+ // op: rt
+ op = getRegisterListOpValue16(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 8;
+ // op: addr
+ op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 4;
+ break;
+ }
+ case Mips::JrcRx16:
+ case Mips::JumpLinkReg16:
+ case Mips::SebRx16:
+ case Mips::SehRx16: {
+ // op: rx
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ break;
+ }
+ case Mips::AddiuRxRxImm16:
+ case Mips::BeqzRxImm16:
+ case Mips::BnezRxImm16:
+ case Mips::CmpiRxImm16:
+ case Mips::LiRxImm16:
+ case Mips::LwRxPcTcp16:
+ case Mips::SltiRxImm16:
+ case Mips::SltiuRxImm16: {
+ // op: rx
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ // op: imm8
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= op & UINT64_C(255);
+ break;
+ }
+ case Mips::Mfhi16:
+ case Mips::Mflo16: {
+ // op: rx
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ // op: ry
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 5;
+ break;
+ }
+ case Mips::CmpRxRy16:
+ case Mips::DivRxRy16:
+ case Mips::DivuRxRy16:
+ case Mips::NegRxRy16:
+ case Mips::NotRxRy16:
+ case Mips::SltRxRy16:
+ case Mips::SltuRxRy16: {
+ // op: rx
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ // op: ry
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 5;
+ break;
+ }
+ case Mips::AndRxRxRy16:
+ case Mips::OrRxRxRy16:
+ case Mips::SllvRxRy16:
+ case Mips::SravRxRy16:
+ case Mips::SrlvRxRy16:
+ case Mips::XorRxRxRy16: {
+ // op: rx
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ // op: ry
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 5;
+ break;
+ }
+ case Mips::AdduRxRyRz16:
+ case Mips::SubuRxRyRz16: {
+ // op: rx
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ // op: ry
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 5;
+ // op: rz
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 2;
+ break;
+ }
+ case Mips::MoveR3216: {
+ // op: ry
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 4;
+ // op: r32
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= op & UINT64_C(15);
+ break;
+ }
+ case Mips::LDI_B:
+ case Mips::LDI_D:
+ case Mips::LDI_H:
+ case Mips::LDI_W: {
+ // op: s10
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(1023)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::SllX16:
+ case Mips::SraX16:
+ case Mips::SrlX16: {
+ // op: sa6
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 22;
+ Value |= (op & UINT64_C(32)) << 16;
+ // op: rx
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 8;
+ // op: ry
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 5;
+ break;
+ }
+ case Mips::SHILO_MM: {
+ // op: shift
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(63)) << 16;
+ // op: ac
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(3)) << 14;
+ break;
+ }
+ case Mips::SYNC_MM:
+ case Mips::SYNC_MMR6: {
+ // op: stype
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::SYNC: {
+ // op: stype
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::J:
+ case Mips::JAL:
+ case Mips::JALX:
+ case Mips::JALX_MM: {
+ // op: target
+ op = getJumpTargetOpValue(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(67108863);
+ break;
+ }
+ case Mips::JALS_MM:
+ case Mips::JAL_MM:
+ case Mips::J_MM: {
+ // op: target
+ op = getJumpTargetOpValueMM(MI, 0, Fixups, STI);
+ Value |= op & UINT64_C(67108863);
+ break;
+ }
+ case Mips::ANDI_B:
+ case Mips::NORI_B:
+ case Mips::ORI_B:
+ case Mips::SHF_B:
+ case Mips::SHF_H:
+ case Mips::SHF_W:
+ case Mips::XORI_B: {
+ // op: u8
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(255)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::BMNZI_B:
+ case Mips::BMZI_B:
+ case Mips::BSELI_B: {
+ // op: u8
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(255)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::FCLASS_D:
+ case Mips::FCLASS_W:
+ case Mips::FEXUPL_D:
+ case Mips::FEXUPL_W:
+ case Mips::FEXUPR_D:
+ case Mips::FEXUPR_W:
+ case Mips::FFINT_S_D:
+ case Mips::FFINT_S_W:
+ case Mips::FFINT_U_D:
+ case Mips::FFINT_U_W:
+ case Mips::FFQL_D:
+ case Mips::FFQL_W:
+ case Mips::FFQR_D:
+ case Mips::FFQR_W:
+ case Mips::FLOG2_D:
+ case Mips::FLOG2_W:
+ case Mips::FRCP_D:
+ case Mips::FRCP_W:
+ case Mips::FRINT_D:
+ case Mips::FRINT_W:
+ case Mips::FRSQRT_D:
+ case Mips::FRSQRT_W:
+ case Mips::FSQRT_D:
+ case Mips::FSQRT_W:
+ case Mips::FTINT_S_D:
+ case Mips::FTINT_S_W:
+ case Mips::FTINT_U_D:
+ case Mips::FTINT_U_W:
+ case Mips::FTRUNC_S_D:
+ case Mips::FTRUNC_S_W:
+ case Mips::FTRUNC_U_D:
+ case Mips::FTRUNC_U_W:
+ case Mips::MOVE_V:
+ case Mips::NLOC_B:
+ case Mips::NLOC_D:
+ case Mips::NLOC_H:
+ case Mips::NLOC_W:
+ case Mips::NLZC_B:
+ case Mips::NLZC_D:
+ case Mips::NLZC_H:
+ case Mips::NLZC_W:
+ case Mips::PCNT_B:
+ case Mips::PCNT_D:
+ case Mips::PCNT_H:
+ case Mips::PCNT_W: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::BCLRI_H:
+ case Mips::BNEGI_H:
+ case Mips::BSETI_H:
+ case Mips::SAT_S_H:
+ case Mips::SAT_U_H:
+ case Mips::SLLI_H:
+ case Mips::SRAI_H:
+ case Mips::SRARI_H:
+ case Mips::SRLI_H:
+ case Mips::SRLRI_H: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: m
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 16;
+ break;
+ }
+ case Mips::BCLRI_W:
+ case Mips::BNEGI_W:
+ case Mips::BSETI_W:
+ case Mips::SAT_S_W:
+ case Mips::SAT_U_W:
+ case Mips::SLLI_W:
+ case Mips::SRAI_W:
+ case Mips::SRARI_W:
+ case Mips::SRLI_W:
+ case Mips::SRLRI_W: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: m
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::BCLRI_D:
+ case Mips::BNEGI_D:
+ case Mips::BSETI_D:
+ case Mips::SAT_S_D:
+ case Mips::SAT_U_D:
+ case Mips::SLLI_D:
+ case Mips::SRAI_D:
+ case Mips::SRARI_D:
+ case Mips::SRLI_D:
+ case Mips::SRLRI_D: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: m
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(63)) << 16;
+ break;
+ }
+ case Mips::BCLRI_B:
+ case Mips::BNEGI_B:
+ case Mips::BSETI_B:
+ case Mips::SAT_S_B:
+ case Mips::SAT_U_B:
+ case Mips::SLLI_B:
+ case Mips::SRAI_B:
+ case Mips::SRARI_B:
+ case Mips::SRLI_B:
+ case Mips::SRLRI_B: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: m
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 16;
+ break;
+ }
+ case Mips::BINSLI_H:
+ case Mips::BINSRI_H: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: m
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(15)) << 16;
+ break;
+ }
+ case Mips::BINSLI_W:
+ case Mips::BINSRI_W: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: m
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ break;
+ }
+ case Mips::BINSLI_D:
+ case Mips::BINSRI_D: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: m
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(63)) << 16;
+ break;
+ }
+ case Mips::BINSLI_B:
+ case Mips::BINSRI_B: {
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ // op: m
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(7)) << 16;
+ break;
+ }
+ case Mips::ADDS_A_B:
+ case Mips::ADDS_A_D:
+ case Mips::ADDS_A_H:
+ case Mips::ADDS_A_W:
+ case Mips::ADDS_S_B:
+ case Mips::ADDS_S_D:
+ case Mips::ADDS_S_H:
+ case Mips::ADDS_S_W:
+ case Mips::ADDS_U_B:
+ case Mips::ADDS_U_D:
+ case Mips::ADDS_U_H:
+ case Mips::ADDS_U_W:
+ case Mips::ADDV_B:
+ case Mips::ADDV_D:
+ case Mips::ADDV_H:
+ case Mips::ADDV_W:
+ case Mips::ADD_A_B:
+ case Mips::ADD_A_D:
+ case Mips::ADD_A_H:
+ case Mips::ADD_A_W:
+ case Mips::AND_V:
+ case Mips::ASUB_S_B:
+ case Mips::ASUB_S_D:
+ case Mips::ASUB_S_H:
+ case Mips::ASUB_S_W:
+ case Mips::ASUB_U_B:
+ case Mips::ASUB_U_D:
+ case Mips::ASUB_U_H:
+ case Mips::ASUB_U_W:
+ case Mips::AVER_S_B:
+ case Mips::AVER_S_D:
+ case Mips::AVER_S_H:
+ case Mips::AVER_S_W:
+ case Mips::AVER_U_B:
+ case Mips::AVER_U_D:
+ case Mips::AVER_U_H:
+ case Mips::AVER_U_W:
+ case Mips::AVE_S_B:
+ case Mips::AVE_S_D:
+ case Mips::AVE_S_H:
+ case Mips::AVE_S_W:
+ case Mips::AVE_U_B:
+ case Mips::AVE_U_D:
+ case Mips::AVE_U_H:
+ case Mips::AVE_U_W:
+ case Mips::BCLR_B:
+ case Mips::BCLR_D:
+ case Mips::BCLR_H:
+ case Mips::BCLR_W:
+ case Mips::BNEG_B:
+ case Mips::BNEG_D:
+ case Mips::BNEG_H:
+ case Mips::BNEG_W:
+ case Mips::BSET_B:
+ case Mips::BSET_D:
+ case Mips::BSET_H:
+ case Mips::BSET_W:
+ case Mips::CEQ_B:
+ case Mips::CEQ_D:
+ case Mips::CEQ_H:
+ case Mips::CEQ_W:
+ case Mips::CLE_S_B:
+ case Mips::CLE_S_D:
+ case Mips::CLE_S_H:
+ case Mips::CLE_S_W:
+ case Mips::CLE_U_B:
+ case Mips::CLE_U_D:
+ case Mips::CLE_U_H:
+ case Mips::CLE_U_W:
+ case Mips::CLT_S_B:
+ case Mips::CLT_S_D:
+ case Mips::CLT_S_H:
+ case Mips::CLT_S_W:
+ case Mips::CLT_U_B:
+ case Mips::CLT_U_D:
+ case Mips::CLT_U_H:
+ case Mips::CLT_U_W:
+ case Mips::DIV_S_B:
+ case Mips::DIV_S_D:
+ case Mips::DIV_S_H:
+ case Mips::DIV_S_W:
+ case Mips::DIV_U_B:
+ case Mips::DIV_U_D:
+ case Mips::DIV_U_H:
+ case Mips::DIV_U_W:
+ case Mips::DOTP_S_D:
+ case Mips::DOTP_S_H:
+ case Mips::DOTP_S_W:
+ case Mips::DOTP_U_D:
+ case Mips::DOTP_U_H:
+ case Mips::DOTP_U_W:
+ case Mips::FADD_D:
+ case Mips::FADD_W:
+ case Mips::FCAF_D:
+ case Mips::FCAF_W:
+ case Mips::FCEQ_D:
+ case Mips::FCEQ_W:
+ case Mips::FCLE_D:
+ case Mips::FCLE_W:
+ case Mips::FCLT_D:
+ case Mips::FCLT_W:
+ case Mips::FCNE_D:
+ case Mips::FCNE_W:
+ case Mips::FCOR_D:
+ case Mips::FCOR_W:
+ case Mips::FCUEQ_D:
+ case Mips::FCUEQ_W:
+ case Mips::FCULE_D:
+ case Mips::FCULE_W:
+ case Mips::FCULT_D:
+ case Mips::FCULT_W:
+ case Mips::FCUNE_D:
+ case Mips::FCUNE_W:
+ case Mips::FCUN_D:
+ case Mips::FCUN_W:
+ case Mips::FDIV_D:
+ case Mips::FDIV_W:
+ case Mips::FEXDO_H:
+ case Mips::FEXDO_W:
+ case Mips::FEXP2_D:
+ case Mips::FEXP2_W:
+ case Mips::FMAX_A_D:
+ case Mips::FMAX_A_W:
+ case Mips::FMAX_D:
+ case Mips::FMAX_W:
+ case Mips::FMIN_A_D:
+ case Mips::FMIN_A_W:
+ case Mips::FMIN_D:
+ case Mips::FMIN_W:
+ case Mips::FMUL_D:
+ case Mips::FMUL_W:
+ case Mips::FSAF_D:
+ case Mips::FSAF_W:
+ case Mips::FSEQ_D:
+ case Mips::FSEQ_W:
+ case Mips::FSLE_D:
+ case Mips::FSLE_W:
+ case Mips::FSLT_D:
+ case Mips::FSLT_W:
+ case Mips::FSNE_D:
+ case Mips::FSNE_W:
+ case Mips::FSOR_D:
+ case Mips::FSOR_W:
+ case Mips::FSUB_D:
+ case Mips::FSUB_W:
+ case Mips::FSUEQ_D:
+ case Mips::FSUEQ_W:
+ case Mips::FSULE_D:
+ case Mips::FSULE_W:
+ case Mips::FSULT_D:
+ case Mips::FSULT_W:
+ case Mips::FSUNE_D:
+ case Mips::FSUNE_W:
+ case Mips::FSUN_D:
+ case Mips::FSUN_W:
+ case Mips::FTQ_H:
+ case Mips::FTQ_W:
+ case Mips::HADD_S_D:
+ case Mips::HADD_S_H:
+ case Mips::HADD_S_W:
+ case Mips::HADD_U_D:
+ case Mips::HADD_U_H:
+ case Mips::HADD_U_W:
+ case Mips::HSUB_S_D:
+ case Mips::HSUB_S_H:
+ case Mips::HSUB_S_W:
+ case Mips::HSUB_U_D:
+ case Mips::HSUB_U_H:
+ case Mips::HSUB_U_W:
+ case Mips::ILVEV_B:
+ case Mips::ILVEV_D:
+ case Mips::ILVEV_H:
+ case Mips::ILVEV_W:
+ case Mips::ILVL_B:
+ case Mips::ILVL_D:
+ case Mips::ILVL_H:
+ case Mips::ILVL_W:
+ case Mips::ILVOD_B:
+ case Mips::ILVOD_D:
+ case Mips::ILVOD_H:
+ case Mips::ILVOD_W:
+ case Mips::ILVR_B:
+ case Mips::ILVR_D:
+ case Mips::ILVR_H:
+ case Mips::ILVR_W:
+ case Mips::MAX_A_B:
+ case Mips::MAX_A_D:
+ case Mips::MAX_A_H:
+ case Mips::MAX_A_W:
+ case Mips::MAX_S_B:
+ case Mips::MAX_S_D:
+ case Mips::MAX_S_H:
+ case Mips::MAX_S_W:
+ case Mips::MAX_U_B:
+ case Mips::MAX_U_D:
+ case Mips::MAX_U_H:
+ case Mips::MAX_U_W:
+ case Mips::MIN_A_B:
+ case Mips::MIN_A_D:
+ case Mips::MIN_A_H:
+ case Mips::MIN_A_W:
+ case Mips::MIN_S_B:
+ case Mips::MIN_S_D:
+ case Mips::MIN_S_H:
+ case Mips::MIN_S_W:
+ case Mips::MIN_U_B:
+ case Mips::MIN_U_D:
+ case Mips::MIN_U_H:
+ case Mips::MIN_U_W:
+ case Mips::MOD_S_B:
+ case Mips::MOD_S_D:
+ case Mips::MOD_S_H:
+ case Mips::MOD_S_W:
+ case Mips::MOD_U_B:
+ case Mips::MOD_U_D:
+ case Mips::MOD_U_H:
+ case Mips::MOD_U_W:
+ case Mips::MULR_Q_H:
+ case Mips::MULR_Q_W:
+ case Mips::MULV_B:
+ case Mips::MULV_D:
+ case Mips::MULV_H:
+ case Mips::MULV_W:
+ case Mips::MUL_Q_H:
+ case Mips::MUL_Q_W:
+ case Mips::NOR_V:
+ case Mips::OR_V:
+ case Mips::PCKEV_B:
+ case Mips::PCKEV_D:
+ case Mips::PCKEV_H:
+ case Mips::PCKEV_W:
+ case Mips::PCKOD_B:
+ case Mips::PCKOD_D:
+ case Mips::PCKOD_H:
+ case Mips::PCKOD_W:
+ case Mips::SLL_B:
+ case Mips::SLL_D:
+ case Mips::SLL_H:
+ case Mips::SLL_W:
+ case Mips::SRAR_B:
+ case Mips::SRAR_D:
+ case Mips::SRAR_H:
+ case Mips::SRAR_W:
+ case Mips::SRA_B:
+ case Mips::SRA_D:
+ case Mips::SRA_H:
+ case Mips::SRA_W:
+ case Mips::SRLR_B:
+ case Mips::SRLR_D:
+ case Mips::SRLR_H:
+ case Mips::SRLR_W:
+ case Mips::SRL_B:
+ case Mips::SRL_D:
+ case Mips::SRL_H:
+ case Mips::SRL_W:
+ case Mips::SUBSUS_U_B:
+ case Mips::SUBSUS_U_D:
+ case Mips::SUBSUS_U_H:
+ case Mips::SUBSUS_U_W:
+ case Mips::SUBSUU_S_B:
+ case Mips::SUBSUU_S_D:
+ case Mips::SUBSUU_S_H:
+ case Mips::SUBSUU_S_W:
+ case Mips::SUBS_S_B:
+ case Mips::SUBS_S_D:
+ case Mips::SUBS_S_H:
+ case Mips::SUBS_S_W:
+ case Mips::SUBS_U_B:
+ case Mips::SUBS_U_D:
+ case Mips::SUBS_U_H:
+ case Mips::SUBS_U_W:
+ case Mips::SUBV_B:
+ case Mips::SUBV_D:
+ case Mips::SUBV_H:
+ case Mips::SUBV_W:
+ case Mips::XOR_V: {
+ // op: wt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ case Mips::BINSL_B:
+ case Mips::BINSL_D:
+ case Mips::BINSL_H:
+ case Mips::BINSL_W:
+ case Mips::BINSR_B:
+ case Mips::BINSR_D:
+ case Mips::BINSR_H:
+ case Mips::BINSR_W:
+ case Mips::BMNZ_V:
+ case Mips::BMZ_V:
+ case Mips::BSEL_V:
+ case Mips::DPADD_S_D:
+ case Mips::DPADD_S_H:
+ case Mips::DPADD_S_W:
+ case Mips::DPADD_U_D:
+ case Mips::DPADD_U_H:
+ case Mips::DPADD_U_W:
+ case Mips::DPSUB_S_D:
+ case Mips::DPSUB_S_H:
+ case Mips::DPSUB_S_W:
+ case Mips::DPSUB_U_D:
+ case Mips::DPSUB_U_H:
+ case Mips::DPSUB_U_W:
+ case Mips::FMADD_D:
+ case Mips::FMADD_W:
+ case Mips::FMSUB_D:
+ case Mips::FMSUB_W:
+ case Mips::MADDR_Q_H:
+ case Mips::MADDR_Q_W:
+ case Mips::MADDV_B:
+ case Mips::MADDV_D:
+ case Mips::MADDV_H:
+ case Mips::MADDV_W:
+ case Mips::MADD_Q_H:
+ case Mips::MADD_Q_W:
+ case Mips::MSUBR_Q_H:
+ case Mips::MSUBR_Q_W:
+ case Mips::MSUBV_B:
+ case Mips::MSUBV_D:
+ case Mips::MSUBV_H:
+ case Mips::MSUBV_W:
+ case Mips::MSUB_Q_H:
+ case Mips::MSUB_Q_W:
+ case Mips::VSHF_B:
+ case Mips::VSHF_D:
+ case Mips::VSHF_H:
+ case Mips::VSHF_W: {
+ // op: wt
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 16;
+ // op: ws
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 11;
+ // op: wd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ Value |= (op & UINT64_C(31)) << 6;
+ break;
+ }
+ default:
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "Not supported instr: " << MI;
+ report_fatal_error(Msg.str());
+ }
+ return Value;
+}
+
+#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
+#undef ENABLE_INSTR_PREDICATE_VERIFIER
+#include <sstream>
+
+// Flags for subtarget features that participate in instruction matching.
+enum SubtargetFeatureFlag : uint64_t {
+ Feature_HasMips2 = (1ULL << 10),
+ Feature_HasMips3_32 = (1ULL << 16),
+ Feature_HasMips3_32r2 = (1ULL << 17),
+ Feature_HasMips3 = (1ULL << 11),
+ Feature_NotMips3 = (1ULL << 44),
+ Feature_HasMips4_32 = (1ULL << 18),
+ Feature_NotMips4_32 = (1ULL << 46),
+ Feature_HasMips4_32r2 = (1ULL << 19),
+ Feature_HasMips5_32r2 = (1ULL << 20),
+ Feature_HasMips32 = (1ULL << 12),
+ Feature_HasMips32r2 = (1ULL << 13),
+ Feature_HasMips32r5 = (1ULL << 14),
+ Feature_HasMips32r6 = (1ULL << 15),
+ Feature_NotMips32r6 = (1ULL << 45),
+ Feature_IsGP64bit = (1ULL << 31),
+ Feature_IsGP32bit = (1ULL << 30),
+ Feature_IsPTR64bit = (1ULL << 35),
+ Feature_IsPTR32bit = (1ULL << 34),
+ Feature_HasMips64 = (1ULL << 21),
+ Feature_NotMips64 = (1ULL << 47),
+ Feature_HasMips64r2 = (1ULL << 22),
+ Feature_HasMips64r5 = (1ULL << 23),
+ Feature_HasMips64r6 = (1ULL << 24),
+ Feature_NotMips64r6 = (1ULL << 48),
+ Feature_InMips16Mode = (1ULL << 28),
+ Feature_NotInMips16Mode = (1ULL << 43),
+ Feature_HasCnMips = (1ULL << 1),
+ Feature_NotCnMips = (1ULL << 40),
+ Feature_IsSym32 = (1ULL << 37),
+ Feature_IsSym64 = (1ULL << 38),
+ Feature_HasStdEnc = (1ULL << 25),
+ Feature_InMicroMips = (1ULL << 27),
+ Feature_NotInMicroMips = (1ULL << 42),
+ Feature_HasEVA = (1ULL << 5),
+ Feature_HasMSA = (1ULL << 7),
+ Feature_HasMadd4 = (1ULL << 9),
+ Feature_HasMT = (1ULL << 8),
+ Feature_UseIndirectJumpsHazard = (1ULL << 49),
+ Feature_NoIndirectJumpGuards = (1ULL << 39),
+ Feature_HasCRC = (1ULL << 0),
+ Feature_HasVirt = (1ULL << 26),
+ Feature_HasGINV = (1ULL << 6),
+ Feature_IsFP64bit = (1ULL << 29),
+ Feature_NotFP64bit = (1ULL << 41),
+ Feature_IsSingleFloat = (1ULL << 36),
+ Feature_IsNotSingleFloat = (1ULL << 32),
+ Feature_IsNotSoftFloat = (1ULL << 33),
+ Feature_HasDSP = (1ULL << 2),
+ Feature_HasDSPR2 = (1ULL << 3),
+ Feature_HasDSPR3 = (1ULL << 4),
+ Feature_None = 0
+};
+
+#ifndef NDEBUG
+static const char *SubtargetFeatureNames[] = {
+ "Feature_HasCRC",
+ "Feature_HasCnMips",
+ "Feature_HasDSP",
+ "Feature_HasDSPR2",
+ "Feature_HasDSPR3",
+ "Feature_HasEVA",
+ "Feature_HasGINV",
+ "Feature_HasMSA",
+ "Feature_HasMT",
+ "Feature_HasMadd4",
+ "Feature_HasMips2",
+ "Feature_HasMips3",
+ "Feature_HasMips32",
+ "Feature_HasMips32r2",
+ "Feature_HasMips32r5",
+ "Feature_HasMips32r6",
+ "Feature_HasMips3_32",
+ "Feature_HasMips3_32r2",
+ "Feature_HasMips4_32",
+ "Feature_HasMips4_32r2",
+ "Feature_HasMips5_32r2",
+ "Feature_HasMips64",
+ "Feature_HasMips64r2",
+ "Feature_HasMips64r5",
+ "Feature_HasMips64r6",
+ "Feature_HasStdEnc",
+ "Feature_HasVirt",
+ "Feature_InMicroMips",
+ "Feature_InMips16Mode",
+ "Feature_IsFP64bit",
+ "Feature_IsGP32bit",
+ "Feature_IsGP64bit",
+ "Feature_IsNotSingleFloat",
+ "Feature_IsNotSoftFloat",
+ "Feature_IsPTR32bit",
+ "Feature_IsPTR64bit",
+ "Feature_IsSingleFloat",
+ "Feature_IsSym32",
+ "Feature_IsSym64",
+ "Feature_NoIndirectJumpGuards",
+ "Feature_NotCnMips",
+ "Feature_NotFP64bit",
+ "Feature_NotInMicroMips",
+ "Feature_NotInMips16Mode",
+ "Feature_NotMips3",
+ "Feature_NotMips32r6",
+ "Feature_NotMips4_32",
+ "Feature_NotMips64",
+ "Feature_NotMips64r6",
+ "Feature_UseIndirectJumpsHazard",
+ nullptr
+};
+
+#endif // NDEBUG
+uint64_t MipsMCCodeEmitter::
+computeAvailableFeatures(const FeatureBitset& FB) const {
+ uint64_t Features = 0;
+ if ((FB[Mips::FeatureMips2]))
+ Features |= Feature_HasMips2;
+ if ((FB[Mips::FeatureMips3_32]))
+ Features |= Feature_HasMips3_32;
+ if ((FB[Mips::FeatureMips3_32r2]))
+ Features |= Feature_HasMips3_32r2;
+ if ((FB[Mips::FeatureMips3]))
+ Features |= Feature_HasMips3;
+ if ((!FB[Mips::FeatureMips3]))
+ Features |= Feature_NotMips3;
+ if ((FB[Mips::FeatureMips4_32]))
+ Features |= Feature_HasMips4_32;
+ if ((!FB[Mips::FeatureMips4_32]))
+ Features |= Feature_NotMips4_32;
+ if ((FB[Mips::FeatureMips4_32r2]))
+ Features |= Feature_HasMips4_32r2;
+ if ((FB[Mips::FeatureMips5_32r2]))
+ Features |= Feature_HasMips5_32r2;
+ if ((FB[Mips::FeatureMips32]))
+ Features |= Feature_HasMips32;
+ if ((FB[Mips::FeatureMips32r2]))
+ Features |= Feature_HasMips32r2;
+ if ((FB[Mips::FeatureMips32r5]))
+ Features |= Feature_HasMips32r5;
+ if ((FB[Mips::FeatureMips32r6]))
+ Features |= Feature_HasMips32r6;
+ if ((!FB[Mips::FeatureMips32r6]))
+ Features |= Feature_NotMips32r6;
+ if ((FB[Mips::FeatureGP64Bit]))
+ Features |= Feature_IsGP64bit;
+ if ((!FB[Mips::FeatureGP64Bit]))
+ Features |= Feature_IsGP32bit;
+ if ((FB[Mips::FeaturePTR64Bit]))
+ Features |= Feature_IsPTR64bit;
+ if ((!FB[Mips::FeaturePTR64Bit]))
+ Features |= Feature_IsPTR32bit;
+ if ((FB[Mips::FeatureMips64]))
+ Features |= Feature_HasMips64;
+ if ((!FB[Mips::FeatureMips64]))
+ Features |= Feature_NotMips64;
+ if ((FB[Mips::FeatureMips64r2]))
+ Features |= Feature_HasMips64r2;
+ if ((FB[Mips::FeatureMips64r5]))
+ Features |= Feature_HasMips64r5;
+ if ((FB[Mips::FeatureMips64r6]))
+ Features |= Feature_HasMips64r6;
+ if ((!FB[Mips::FeatureMips64r6]))
+ Features |= Feature_NotMips64r6;
+ if ((FB[Mips::FeatureMips16]))
+ Features |= Feature_InMips16Mode;
+ if ((!FB[Mips::FeatureMips16]))
+ Features |= Feature_NotInMips16Mode;
+ if ((FB[Mips::FeatureCnMips]))
+ Features |= Feature_HasCnMips;
+ if ((!FB[Mips::FeatureCnMips]))
+ Features |= Feature_NotCnMips;
+ if ((FB[Mips::FeatureSym32]))
+ Features |= Feature_IsSym32;
+ if ((!FB[Mips::FeatureSym32]))
+ Features |= Feature_IsSym64;
+ if ((!FB[Mips::FeatureMips16]))
+ Features |= Feature_HasStdEnc;
+ if ((FB[Mips::FeatureMicroMips]))
+ Features |= Feature_InMicroMips;
+ if ((!FB[Mips::FeatureMicroMips]))
+ Features |= Feature_NotInMicroMips;
+ if ((FB[Mips::FeatureEVA]))
+ Features |= Feature_HasEVA;
+ if ((FB[Mips::FeatureMSA]))
+ Features |= Feature_HasMSA;
+ if ((!FB[Mips::FeatureMadd4]))
+ Features |= Feature_HasMadd4;
+ if ((FB[Mips::FeatureMT]))
+ Features |= Feature_HasMT;
+ if ((FB[Mips::FeatureUseIndirectJumpsHazard]))
+ Features |= Feature_UseIndirectJumpsHazard;
+ if ((!FB[Mips::FeatureUseIndirectJumpsHazard]))
+ Features |= Feature_NoIndirectJumpGuards;
+ if ((FB[Mips::FeatureCRC]))
+ Features |= Feature_HasCRC;
+ if ((FB[Mips::FeatureVirt]))
+ Features |= Feature_HasVirt;
+ if ((FB[Mips::FeatureGINV]))
+ Features |= Feature_HasGINV;
+ if ((FB[Mips::FeatureFP64Bit]))
+ Features |= Feature_IsFP64bit;
+ if ((!FB[Mips::FeatureFP64Bit]))
+ Features |= Feature_NotFP64bit;
+ if ((FB[Mips::FeatureSingleFloat]))
+ Features |= Feature_IsSingleFloat;
+ if ((!FB[Mips::FeatureSingleFloat]))
+ Features |= Feature_IsNotSingleFloat;
+ if ((!FB[Mips::FeatureSoftFloat]))
+ Features |= Feature_IsNotSoftFloat;
+ if ((FB[Mips::FeatureDSP]))
+ Features |= Feature_HasDSP;
+ if ((FB[Mips::FeatureDSPR2]))
+ Features |= Feature_HasDSPR2;
+ if ((FB[Mips::FeatureDSPR3]))
+ Features |= Feature_HasDSPR3;
+ return Features;
+}
+
+void MipsMCCodeEmitter::verifyInstructionPredicates(
+ const MCInst &Inst, uint64_t AvailableFeatures) const {
+#ifndef NDEBUG
+ static uint64_t RequiredFeatures[] = {
+ 0, // PHI = 0
+ 0, // INLINEASM = 1
+ 0, // CFI_INSTRUCTION = 2
+ 0, // EH_LABEL = 3
+ 0, // GC_LABEL = 4
+ 0, // ANNOTATION_LABEL = 5
+ 0, // KILL = 6
+ 0, // EXTRACT_SUBREG = 7
+ 0, // INSERT_SUBREG = 8
+ 0, // IMPLICIT_DEF = 9
+ 0, // SUBREG_TO_REG = 10
+ 0, // COPY_TO_REGCLASS = 11
+ 0, // DBG_VALUE = 12
+ 0, // DBG_LABEL = 13
+ 0, // REG_SEQUENCE = 14
+ 0, // COPY = 15
+ 0, // BUNDLE = 16
+ 0, // LIFETIME_START = 17
+ 0, // LIFETIME_END = 18
+ 0, // STACKMAP = 19
+ 0, // FENTRY_CALL = 20
+ 0, // PATCHPOINT = 21
+ 0, // LOAD_STACK_GUARD = 22
+ 0, // STATEPOINT = 23
+ 0, // LOCAL_ESCAPE = 24
+ 0, // FAULTING_OP = 25
+ 0, // PATCHABLE_OP = 26
+ 0, // PATCHABLE_FUNCTION_ENTER = 27
+ 0, // PATCHABLE_RET = 28
+ 0, // PATCHABLE_FUNCTION_EXIT = 29
+ 0, // PATCHABLE_TAIL_CALL = 30
+ 0, // PATCHABLE_EVENT_CALL = 31
+ 0, // PATCHABLE_TYPED_EVENT_CALL = 32
+ 0, // ICALL_BRANCH_FUNNEL = 33
+ 0, // G_ADD = 34
+ 0, // G_SUB = 35
+ 0, // G_MUL = 36
+ 0, // G_SDIV = 37
+ 0, // G_UDIV = 38
+ 0, // G_SREM = 39
+ 0, // G_UREM = 40
+ 0, // G_AND = 41
+ 0, // G_OR = 42
+ 0, // G_XOR = 43
+ 0, // G_IMPLICIT_DEF = 44
+ 0, // G_PHI = 45
+ 0, // G_FRAME_INDEX = 46
+ 0, // G_GLOBAL_VALUE = 47
+ 0, // G_EXTRACT = 48
+ 0, // G_UNMERGE_VALUES = 49
+ 0, // G_INSERT = 50
+ 0, // G_MERGE_VALUES = 51
+ 0, // G_PTRTOINT = 52
+ 0, // G_INTTOPTR = 53
+ 0, // G_BITCAST = 54
+ 0, // G_LOAD = 55
+ 0, // G_SEXTLOAD = 56
+ 0, // G_ZEXTLOAD = 57
+ 0, // G_STORE = 58
+ 0, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59
+ 0, // G_ATOMIC_CMPXCHG = 60
+ 0, // G_ATOMICRMW_XCHG = 61
+ 0, // G_ATOMICRMW_ADD = 62
+ 0, // G_ATOMICRMW_SUB = 63
+ 0, // G_ATOMICRMW_AND = 64
+ 0, // G_ATOMICRMW_NAND = 65
+ 0, // G_ATOMICRMW_OR = 66
+ 0, // G_ATOMICRMW_XOR = 67
+ 0, // G_ATOMICRMW_MAX = 68
+ 0, // G_ATOMICRMW_MIN = 69
+ 0, // G_ATOMICRMW_UMAX = 70
+ 0, // G_ATOMICRMW_UMIN = 71
+ 0, // G_BRCOND = 72
+ 0, // G_BRINDIRECT = 73
+ 0, // G_INTRINSIC = 74
+ 0, // G_INTRINSIC_W_SIDE_EFFECTS = 75
+ 0, // G_ANYEXT = 76
+ 0, // G_TRUNC = 77
+ 0, // G_CONSTANT = 78
+ 0, // G_FCONSTANT = 79
+ 0, // G_VASTART = 80
+ 0, // G_VAARG = 81
+ 0, // G_SEXT = 82
+ 0, // G_ZEXT = 83
+ 0, // G_SHL = 84
+ 0, // G_LSHR = 85
+ 0, // G_ASHR = 86
+ 0, // G_ICMP = 87
+ 0, // G_FCMP = 88
+ 0, // G_SELECT = 89
+ 0, // G_UADDE = 90
+ 0, // G_USUBE = 91
+ 0, // G_SADDO = 92
+ 0, // G_SSUBO = 93
+ 0, // G_UMULO = 94
+ 0, // G_SMULO = 95
+ 0, // G_UMULH = 96
+ 0, // G_SMULH = 97
+ 0, // G_FADD = 98
+ 0, // G_FSUB = 99
+ 0, // G_FMUL = 100
+ 0, // G_FMA = 101
+ 0, // G_FDIV = 102
+ 0, // G_FREM = 103
+ 0, // G_FPOW = 104
+ 0, // G_FEXP = 105
+ 0, // G_FEXP2 = 106
+ 0, // G_FLOG = 107
+ 0, // G_FLOG2 = 108
+ 0, // G_FNEG = 109
+ 0, // G_FPEXT = 110
+ 0, // G_FPTRUNC = 111
+ 0, // G_FPTOSI = 112
+ 0, // G_FPTOUI = 113
+ 0, // G_SITOFP = 114
+ 0, // G_UITOFP = 115
+ 0, // G_FABS = 116
+ 0, // G_GEP = 117
+ 0, // G_PTR_MASK = 118
+ 0, // G_BR = 119
+ 0, // G_INSERT_VECTOR_ELT = 120
+ 0, // G_EXTRACT_VECTOR_ELT = 121
+ 0, // G_SHUFFLE_VECTOR = 122
+ 0, // G_BSWAP = 123
+ 0, // G_ADDRSPACE_CAST = 124
+ 0, // G_BLOCK_ADDR = 125
+ 0, // ABSMacro = 126
+ 0, // ADJCALLSTACKDOWN = 127
+ 0, // ADJCALLSTACKUP = 128
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AND_V_D_PSEUDO = 129
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AND_V_H_PSEUDO = 130
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AND_V_W_PSEUDO = 131
+ Feature_NotInMips16Mode | 0, // ATOMIC_CMP_SWAP_I16 = 132
+ Feature_NotInMips16Mode | 0, // ATOMIC_CMP_SWAP_I16_POSTRA = 133
+ Feature_NotInMips16Mode | 0, // ATOMIC_CMP_SWAP_I32 = 134
+ Feature_NotInMips16Mode | 0, // ATOMIC_CMP_SWAP_I32_POSTRA = 135
+ Feature_NotInMips16Mode | 0, // ATOMIC_CMP_SWAP_I64 = 136
+ Feature_NotInMips16Mode | 0, // ATOMIC_CMP_SWAP_I64_POSTRA = 137
+ Feature_NotInMips16Mode | 0, // ATOMIC_CMP_SWAP_I8 = 138
+ Feature_NotInMips16Mode | 0, // ATOMIC_CMP_SWAP_I8_POSTRA = 139
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_ADD_I16 = 140
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_ADD_I16_POSTRA = 141
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_ADD_I32 = 142
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_ADD_I32_POSTRA = 143
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_ADD_I64 = 144
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_ADD_I64_POSTRA = 145
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_ADD_I8 = 146
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_ADD_I8_POSTRA = 147
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_AND_I16 = 148
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_AND_I16_POSTRA = 149
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_AND_I32 = 150
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_AND_I32_POSTRA = 151
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_AND_I64 = 152
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_AND_I64_POSTRA = 153
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_AND_I8 = 154
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_AND_I8_POSTRA = 155
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_NAND_I16 = 156
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_NAND_I16_POSTRA = 157
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_NAND_I32 = 158
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_NAND_I32_POSTRA = 159
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_NAND_I64 = 160
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_NAND_I64_POSTRA = 161
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_NAND_I8 = 162
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_NAND_I8_POSTRA = 163
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_OR_I16 = 164
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_OR_I16_POSTRA = 165
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_OR_I32 = 166
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_OR_I32_POSTRA = 167
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_OR_I64 = 168
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_OR_I64_POSTRA = 169
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_OR_I8 = 170
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_OR_I8_POSTRA = 171
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_SUB_I16 = 172
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_SUB_I16_POSTRA = 173
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_SUB_I32 = 174
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_SUB_I32_POSTRA = 175
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_SUB_I64 = 176
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_SUB_I64_POSTRA = 177
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_SUB_I8 = 178
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_SUB_I8_POSTRA = 179
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_XOR_I16 = 180
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_XOR_I16_POSTRA = 181
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_XOR_I32 = 182
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_XOR_I32_POSTRA = 183
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_XOR_I64 = 184
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_XOR_I64_POSTRA = 185
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_XOR_I8 = 186
+ Feature_NotInMips16Mode | 0, // ATOMIC_LOAD_XOR_I8_POSTRA = 187
+ Feature_NotInMips16Mode | 0, // ATOMIC_SWAP_I16 = 188
+ Feature_NotInMips16Mode | 0, // ATOMIC_SWAP_I16_POSTRA = 189
+ Feature_NotInMips16Mode | 0, // ATOMIC_SWAP_I32 = 190
+ Feature_NotInMips16Mode | 0, // ATOMIC_SWAP_I32_POSTRA = 191
+ Feature_NotInMips16Mode | 0, // ATOMIC_SWAP_I64 = 192
+ Feature_NotInMips16Mode | 0, // ATOMIC_SWAP_I64_POSTRA = 193
+ Feature_NotInMips16Mode | 0, // ATOMIC_SWAP_I8 = 194
+ Feature_NotInMips16Mode | 0, // ATOMIC_SWAP_I8_POSTRA = 195
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // B = 196
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BAL_BR = 197
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BAL_BR_MM = 198
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BEQLImmMacro = 199
+ 0, // BGE = 200
+ 0, // BGEImmMacro = 201
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BGEL = 202
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BGELImmMacro = 203
+ 0, // BGEU = 204
+ 0, // BGEUImmMacro = 205
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BGEUL = 206
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BGEULImmMacro = 207
+ 0, // BGT = 208
+ 0, // BGTImmMacro = 209
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BGTL = 210
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BGTLImmMacro = 211
+ 0, // BGTU = 212
+ 0, // BGTUImmMacro = 213
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BGTUL = 214
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BGTULImmMacro = 215
+ 0, // BLE = 216
+ 0, // BLEImmMacro = 217
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BLEL = 218
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BLELImmMacro = 219
+ 0, // BLEU = 220
+ 0, // BLEUImmMacro = 221
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BLEUL = 222
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BLEULImmMacro = 223
+ 0, // BLT = 224
+ 0, // BLTImmMacro = 225
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BLTL = 226
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BLTLImmMacro = 227
+ 0, // BLTU = 228
+ 0, // BLTUImmMacro = 229
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BLTUL = 230
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BLTULImmMacro = 231
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // BNELImmMacro = 232
+ 0, // BPOSGE32_PSEUDO = 233
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSEL_D_PSEUDO = 234
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSEL_FD_PSEUDO = 235
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSEL_FW_PSEUDO = 236
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSEL_H_PSEUDO = 237
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSEL_W_PSEUDO = 238
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // B_MM = 239
+ 0, // B_MMR6_Pseudo = 240
+ Feature_InMicroMips | 0, // B_MM_Pseudo = 241
+ 0, // BeqImm = 242
+ 0, // BneImm = 243
+ Feature_InMips16Mode | 0, // BteqzT8CmpX16 = 244
+ Feature_InMips16Mode | 0, // BteqzT8CmpiX16 = 245
+ Feature_InMips16Mode | 0, // BteqzT8SltX16 = 246
+ Feature_InMips16Mode | 0, // BteqzT8SltiX16 = 247
+ Feature_InMips16Mode | 0, // BteqzT8SltiuX16 = 248
+ Feature_InMips16Mode | 0, // BteqzT8SltuX16 = 249
+ Feature_InMips16Mode | 0, // BtnezT8CmpX16 = 250
+ Feature_InMips16Mode | 0, // BtnezT8CmpiX16 = 251
+ Feature_InMips16Mode | 0, // BtnezT8SltX16 = 252
+ Feature_InMips16Mode | 0, // BtnezT8SltiX16 = 253
+ Feature_InMips16Mode | 0, // BtnezT8SltiuX16 = 254
+ Feature_InMips16Mode | 0, // BtnezT8SltuX16 = 255
+ Feature_NotInMips16Mode | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // BuildPairF64 = 256
+ Feature_NotInMips16Mode | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // BuildPairF64_64 = 257
+ Feature_HasMT | 0, // CFTC1 = 258
+ Feature_InMips16Mode | 0, // CONSTPOOL_ENTRY = 259
+ Feature_HasStdEnc | Feature_HasMSA | 0, // COPY_FD_PSEUDO = 260
+ Feature_HasStdEnc | Feature_HasMSA | 0, // COPY_FW_PSEUDO = 261
+ Feature_HasMT | 0, // CTTC1 = 262
+ Feature_InMips16Mode | 0, // Constant32 = 263
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // DMULImmMacro = 264
+ Feature_HasMips3 | Feature_NotMips64r6 | Feature_NotCnMips | 0, // DMULMacro = 265
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // DMULOMacro = 266
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // DMULOUMacro = 267
+ Feature_HasStdEnc | Feature_HasMips64 | 0, // DROL = 268
+ Feature_HasStdEnc | Feature_HasMips64 | 0, // DROLImm = 269
+ Feature_HasStdEnc | Feature_HasMips64 | 0, // DROR = 270
+ Feature_HasStdEnc | Feature_HasMips64 | 0, // DRORImm = 271
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DSDivIMacro = 272
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DSDivMacro = 273
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DSRemIMacro = 274
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DSRemMacro = 275
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DUDivIMacro = 276
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DUDivMacro = 277
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DURemIMacro = 278
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DURemMacro = 279
+ Feature_NotInMips16Mode | 0, // ERet = 280
+ Feature_NotInMips16Mode | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // ExtractElementF64 = 281
+ Feature_NotInMips16Mode | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // ExtractElementF64_64 = 282
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FABS_D = 283
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FABS_W = 284
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXP2_D_1_PSEUDO = 285
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXP2_W_1_PSEUDO = 286
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FILL_FD_PSEUDO = 287
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FILL_FW_PSEUDO = 288
+ Feature_InMips16Mode | 0, // GotPrologue16 = 289
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_B_VIDX64_PSEUDO = 290
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_B_VIDX_PSEUDO = 291
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_D_VIDX64_PSEUDO = 292
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_D_VIDX_PSEUDO = 293
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_FD_PSEUDO = 294
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_FD_VIDX64_PSEUDO = 295
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_FD_VIDX_PSEUDO = 296
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_FW_PSEUDO = 297
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_FW_VIDX64_PSEUDO = 298
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_FW_VIDX_PSEUDO = 299
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_H_VIDX64_PSEUDO = 300
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_H_VIDX_PSEUDO = 301
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_W_VIDX64_PSEUDO = 302
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_W_VIDX_PSEUDO = 303
+ Feature_NotInMips16Mode | Feature_NoIndirectJumpGuards | 0, // JALR64Pseudo = 304
+ Feature_NotInMips16Mode | Feature_UseIndirectJumpsHazard | 0, // JALRHB64Pseudo = 305
+ Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // JALRHBPseudo = 306
+ Feature_HasStdEnc | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // JALRPseudo = 307
+ 0, // JalOneReg = 308
+ 0, // JalTwoReg = 309
+ Feature_HasStdEnc | Feature_NotMips3 | 0, // LDMacro = 310
+ Feature_HasMSA | 0, // LD_F16 = 311
+ Feature_NotInMips16Mode | 0, // LOAD_ACC128 = 312
+ Feature_NotInMips16Mode | 0, // LOAD_ACC64 = 313
+ Feature_NotInMips16Mode | 0, // LOAD_ACC64DSP = 314
+ Feature_NotInMips16Mode | 0, // LOAD_CCOND_DSP = 315
+ Feature_NotInMips16Mode | 0, // LONG_BRANCH_ADDiu = 316
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LONG_BRANCH_DADDiu = 317
+ Feature_NotInMips16Mode | 0, // LONG_BRANCH_LUi = 318
+ Feature_InMicroMips | 0, // LWM_MM = 319
+ 0, // LoadAddrImm32 = 320
+ 0, // LoadAddrImm64 = 321
+ 0, // LoadAddrReg32 = 322
+ 0, // LoadAddrReg64 = 323
+ 0, // LoadImm32 = 324
+ 0, // LoadImm64 = 325
+ Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // LoadImmDoubleFGR = 326
+ Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // LoadImmDoubleFGR_32 = 327
+ 0, // LoadImmDoubleGPR = 328
+ Feature_IsNotSoftFloat | 0, // LoadImmSingleFGR = 329
+ 0, // LoadImmSingleGPR = 330
+ Feature_InMips16Mode | 0, // LwConstant32 = 331
+ Feature_HasMT | 0, // MFTACX = 332
+ Feature_HasMT | 0, // MFTC0 = 333
+ Feature_HasMT | 0, // MFTC1 = 334
+ Feature_HasMT | 0, // MFTDSP = 335
+ Feature_HasMT | 0, // MFTGPR = 336
+ Feature_HasMT | 0, // MFTHC1 = 337
+ Feature_HasMT | 0, // MFTHI = 338
+ Feature_HasMT | 0, // MFTLO = 339
+ 0, // MIPSeh_return32 = 340
+ 0, // MIPSeh_return64 = 341
+ Feature_HasMSA | 0, // MSA_FP_EXTEND_D_PSEUDO = 342
+ Feature_HasMSA | 0, // MSA_FP_EXTEND_W_PSEUDO = 343
+ Feature_HasMSA | 0, // MSA_FP_ROUND_D_PSEUDO = 344
+ Feature_HasMSA | 0, // MSA_FP_ROUND_W_PSEUDO = 345
+ Feature_HasMT | 0, // MTTACX = 346
+ Feature_HasMT | 0, // MTTC0 = 347
+ Feature_HasMT | 0, // MTTC1 = 348
+ Feature_HasMT | 0, // MTTDSP = 349
+ Feature_HasMT | 0, // MTTGPR = 350
+ Feature_HasMT | 0, // MTTHC1 = 351
+ Feature_HasMT | 0, // MTTHI = 352
+ Feature_HasMT | 0, // MTTLO = 353
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // MULImmMacro = 354
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // MULOMacro = 355
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // MULOUMacro = 356
+ Feature_InMips16Mode | 0, // MultRxRy16 = 357
+ Feature_InMips16Mode | 0, // MultRxRyRz16 = 358
+ Feature_InMips16Mode | 0, // MultuRxRy16 = 359
+ Feature_InMips16Mode | 0, // MultuRxRyRz16 = 360
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // NOP = 361
+ Feature_IsGP32bit | 0, // NORImm = 362
+ Feature_IsGP64bit | 0, // NORImm64 = 363
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NOR_V_D_PSEUDO = 364
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NOR_V_H_PSEUDO = 365
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NOR_V_W_PSEUDO = 366
+ Feature_HasStdEnc | Feature_HasMSA | 0, // OR_V_D_PSEUDO = 367
+ Feature_HasStdEnc | Feature_HasMSA | 0, // OR_V_H_PSEUDO = 368
+ Feature_HasStdEnc | Feature_HasMSA | 0, // OR_V_W_PSEUDO = 369
+ Feature_HasDSP | 0, // PseudoCMPU_EQ_QB = 370
+ Feature_HasDSP | 0, // PseudoCMPU_LE_QB = 371
+ Feature_HasDSP | 0, // PseudoCMPU_LT_QB = 372
+ Feature_HasDSP | 0, // PseudoCMP_EQ_PH = 373
+ Feature_HasDSP | 0, // PseudoCMP_LE_PH = 374
+ Feature_HasDSP | 0, // PseudoCMP_LT_PH = 375
+ Feature_NotInMips16Mode | Feature_IsNotSoftFloat | 0, // PseudoCVT_D32_W = 376
+ Feature_NotInMips16Mode | Feature_IsNotSoftFloat | 0, // PseudoCVT_D64_L = 377
+ Feature_NotInMips16Mode | Feature_IsNotSoftFloat | 0, // PseudoCVT_D64_W = 378
+ Feature_NotInMips16Mode | Feature_IsNotSoftFloat | 0, // PseudoCVT_S_L = 379
+ Feature_NotInMips16Mode | Feature_IsNotSoftFloat | 0, // PseudoCVT_S_W = 380
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoDMULT = 381
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoDMULTu = 382
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoDSDIV = 383
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoDUDIV = 384
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // PseudoIndirectBranch = 385
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // PseudoIndirectBranch64 = 386
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // PseudoIndirectBranch64R6 = 387
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // PseudoIndirectBranchR6 = 388
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // PseudoIndirectBranch_MM = 389
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // PseudoIndirectBranch_MMR6 = 390
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // PseudoIndirectHazardBranch = 391
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // PseudoIndirectHazardBranch64 = 392
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // PseudoIndrectHazardBranch64R6 = 393
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // PseudoIndrectHazardBranchR6 = 394
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMADD = 395
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMADDU = 396
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMFHI = 397
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMFHI64 = 398
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMFLO = 399
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMFLO64 = 400
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMSUB = 401
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMSUBU = 402
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMTLOHI = 403
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMTLOHI64 = 404
+ Feature_NotInMips16Mode | 0, // PseudoMTLOHI_DSP = 405
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMULT = 406
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // PseudoMULTu = 407
+ Feature_HasDSP | 0, // PseudoPICK_PH = 408
+ Feature_HasDSP | 0, // PseudoPICK_QB = 409
+ 0, // PseudoReturn = 410
+ 0, // PseudoReturn64 = 411
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // PseudoSDIV = 412
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips4_32 | 0, // PseudoSELECTFP_F_D32 = 413
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips4_32 | 0, // PseudoSELECTFP_F_D64 = 414
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECTFP_F_I = 415
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECTFP_F_I64 = 416
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECTFP_F_S = 417
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips4_32 | 0, // PseudoSELECTFP_T_D32 = 418
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips4_32 | 0, // PseudoSELECTFP_T_D64 = 419
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECTFP_T_I = 420
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECTFP_T_I64 = 421
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECTFP_T_S = 422
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips4_32 | 0, // PseudoSELECT_D32 = 423
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips4_32 | 0, // PseudoSELECT_D64 = 424
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECT_I = 425
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECT_I64 = 426
+ Feature_HasStdEnc | Feature_NotMips4_32 | 0, // PseudoSELECT_S = 427
+ Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // PseudoTRUNC_W_D = 428
+ Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // PseudoTRUNC_W_D32 = 429
+ 0, // PseudoTRUNC_W_S = 430
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // PseudoUDIV = 431
+ 0, // ROL = 432
+ 0, // ROLImm = 433
+ 0, // ROR = 434
+ 0, // RORImm = 435
+ Feature_NotInMips16Mode | 0, // RetRA = 436
+ Feature_InMips16Mode | 0, // RetRA16 = 437
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // SDIV_MM_Pseudo = 438
+ Feature_HasStdEnc | Feature_NotMips3 | 0, // SDMacro = 439
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // SDivIMacro = 440
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // SDivMacro = 441
+ Feature_NotCnMips | 0, // SEQIMacro = 442
+ Feature_NotCnMips | 0, // SEQMacro = 443
+ Feature_IsGP64bit | 0, // SLTImm64 = 444
+ Feature_IsGP64bit | 0, // SLTUImm64 = 445
+ 0, // SNZ_B_PSEUDO = 446
+ 0, // SNZ_D_PSEUDO = 447
+ 0, // SNZ_H_PSEUDO = 448
+ 0, // SNZ_V_PSEUDO = 449
+ 0, // SNZ_W_PSEUDO = 450
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // SRemIMacro = 451
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // SRemMacro = 452
+ Feature_NotInMips16Mode | 0, // STORE_ACC128 = 453
+ Feature_NotInMips16Mode | 0, // STORE_ACC64 = 454
+ Feature_NotInMips16Mode | 0, // STORE_ACC64DSP = 455
+ Feature_NotInMips16Mode | 0, // STORE_CCOND_DSP = 456
+ Feature_HasMSA | 0, // ST_F16 = 457
+ Feature_InMicroMips | 0, // SWM_MM = 458
+ 0, // SZ_B_PSEUDO = 459
+ 0, // SZ_D_PSEUDO = 460
+ 0, // SZ_H_PSEUDO = 461
+ 0, // SZ_V_PSEUDO = 462
+ 0, // SZ_W_PSEUDO = 463
+ Feature_InMips16Mode | 0, // SelBeqZ = 464
+ Feature_InMips16Mode | 0, // SelBneZ = 465
+ Feature_InMips16Mode | 0, // SelTBteqZCmp = 466
+ Feature_InMips16Mode | 0, // SelTBteqZCmpi = 467
+ Feature_InMips16Mode | 0, // SelTBteqZSlt = 468
+ Feature_InMips16Mode | 0, // SelTBteqZSlti = 469
+ Feature_InMips16Mode | 0, // SelTBteqZSltiu = 470
+ Feature_InMips16Mode | 0, // SelTBteqZSltu = 471
+ Feature_InMips16Mode | 0, // SelTBtneZCmp = 472
+ Feature_InMips16Mode | 0, // SelTBtneZCmpi = 473
+ Feature_InMips16Mode | 0, // SelTBtneZSlt = 474
+ Feature_InMips16Mode | 0, // SelTBtneZSlti = 475
+ Feature_InMips16Mode | 0, // SelTBtneZSltiu = 476
+ Feature_InMips16Mode | 0, // SelTBtneZSltu = 477
+ Feature_InMips16Mode | 0, // SltCCRxRy16 = 478
+ Feature_InMips16Mode | 0, // SltiCCRxImmX16 = 479
+ Feature_InMips16Mode | 0, // SltiuCCRxImmX16 = 480
+ Feature_InMips16Mode | 0, // SltuCCRxRy16 = 481
+ Feature_InMips16Mode | 0, // SltuRxRyRz16 = 482
+ Feature_HasStdEnc | Feature_NotInMips16Mode | Feature_NotInMicroMips | 0, // TAILCALL = 483
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // TAILCALL64R6REG = 484
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // TAILCALLHB64R6REG = 485
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // TAILCALLHBR6REG = 486
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // TAILCALLR6REG = 487
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // TAILCALLREG = 488
+ Feature_HasStdEnc | Feature_IsPTR64bit | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // TAILCALLREG64 = 489
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // TAILCALLREGHB = 490
+ Feature_HasStdEnc | Feature_IsPTR64bit | Feature_HasMips32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMips16Mode | Feature_NotInMicroMips | Feature_UseIndirectJumpsHazard | 0, // TAILCALLREGHB64 = 491
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // TAILCALLREG_MM = 492
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // TAILCALLREG_MMR6 = 493
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // TAILCALL_MM = 494
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // TAILCALL_MMR6 = 495
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // TRAP = 496
+ Feature_InMicroMips | 0, // TRAP_MM = 497
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // UDIV_MM_Pseudo = 498
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // UDivIMacro = 499
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // UDivMacro = 500
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // URemIMacro = 501
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // URemMacro = 502
+ 0, // Ulh = 503
+ 0, // Ulhu = 504
+ 0, // Ulw = 505
+ 0, // Ush = 506
+ 0, // Usw = 507
+ Feature_HasStdEnc | Feature_HasMSA | 0, // XOR_V_D_PSEUDO = 508
+ Feature_HasStdEnc | Feature_HasMSA | 0, // XOR_V_H_PSEUDO = 509
+ Feature_HasStdEnc | Feature_HasMSA | 0, // XOR_V_W_PSEUDO = 510
+ Feature_HasDSP | 0, // ABSQ_S_PH = 511
+ Feature_InMicroMips | Feature_HasDSP | 0, // ABSQ_S_PH_MM = 512
+ Feature_HasDSPR2 | 0, // ABSQ_S_QB = 513
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ABSQ_S_QB_MMR2 = 514
+ Feature_HasDSP | 0, // ABSQ_S_W = 515
+ Feature_InMicroMips | Feature_HasDSP | 0, // ABSQ_S_W_MM = 516
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // ADD = 517
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // ADDIUPC = 518
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ADDIUPC_MM = 519
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ADDIUPC_MMR6 = 520
+ Feature_InMicroMips | 0, // ADDIUR1SP_MM = 521
+ Feature_InMicroMips | 0, // ADDIUR2_MM = 522
+ Feature_InMicroMips | 0, // ADDIUS5_MM = 523
+ Feature_InMicroMips | 0, // ADDIUSP_MM = 524
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ADDIU_MMR6 = 525
+ Feature_HasDSPR2 | 0, // ADDQH_PH = 526
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ADDQH_PH_MMR2 = 527
+ Feature_HasDSPR2 | 0, // ADDQH_R_PH = 528
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ADDQH_R_PH_MMR2 = 529
+ Feature_HasDSPR2 | 0, // ADDQH_R_W = 530
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ADDQH_R_W_MMR2 = 531
+ Feature_HasDSPR2 | 0, // ADDQH_W = 532
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ADDQH_W_MMR2 = 533
+ Feature_HasDSP | 0, // ADDQ_PH = 534
+ Feature_InMicroMips | Feature_HasDSP | 0, // ADDQ_PH_MM = 535
+ Feature_HasDSP | 0, // ADDQ_S_PH = 536
+ Feature_InMicroMips | Feature_HasDSP | 0, // ADDQ_S_PH_MM = 537
+ Feature_HasDSP | 0, // ADDQ_S_W = 538
+ Feature_InMicroMips | Feature_HasDSP | 0, // ADDQ_S_W_MM = 539
+ Feature_HasDSP | 0, // ADDSC = 540
+ Feature_InMicroMips | Feature_HasDSP | 0, // ADDSC_MM = 541
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_A_B = 542
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_A_D = 543
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_A_H = 544
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_A_W = 545
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_S_B = 546
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_S_D = 547
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_S_H = 548
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_S_W = 549
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_U_B = 550
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_U_D = 551
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_U_H = 552
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDS_U_W = 553
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ADDU16_MM = 554
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ADDU16_MMR6 = 555
+ Feature_HasDSPR2 | 0, // ADDUH_QB = 556
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ADDUH_QB_MMR2 = 557
+ Feature_HasDSPR2 | 0, // ADDUH_R_QB = 558
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ADDUH_R_QB_MMR2 = 559
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ADDU_MMR6 = 560
+ Feature_HasDSPR2 | 0, // ADDU_PH = 561
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ADDU_PH_MMR2 = 562
+ Feature_HasDSP | 0, // ADDU_QB = 563
+ Feature_InMicroMips | Feature_HasDSP | 0, // ADDU_QB_MM = 564
+ Feature_HasDSPR2 | 0, // ADDU_S_PH = 565
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // ADDU_S_PH_MMR2 = 566
+ Feature_HasDSP | 0, // ADDU_S_QB = 567
+ Feature_InMicroMips | Feature_HasDSP | 0, // ADDU_S_QB_MM = 568
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDVI_B = 569
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDVI_D = 570
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDVI_H = 571
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDVI_W = 572
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDV_B = 573
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDV_D = 574
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDV_H = 575
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADDV_W = 576
+ Feature_HasDSP | 0, // ADDWC = 577
+ Feature_InMicroMips | Feature_HasDSP | 0, // ADDWC_MM = 578
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADD_A_B = 579
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADD_A_D = 580
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADD_A_H = 581
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ADD_A_W = 582
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ADD_MM = 583
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ADD_MMR6 = 584
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // ADDi = 585
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ADDi_MM = 586
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // ADDiu = 587
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ADDiu_MM = 588
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // ADDu = 589
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ADDu_MM = 590
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // ALIGN = 591
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ALIGN_MMR6 = 592
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // ALUIPC = 593
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ALUIPC_MMR6 = 594
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // AND = 595
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // AND16_MM = 596
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // AND16_MMR6 = 597
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // AND64 = 598
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ANDI16_MM = 599
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ANDI16_MMR6 = 600
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ANDI_B = 601
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ANDI_MMR6 = 602
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // AND_MM = 603
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // AND_MMR6 = 604
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AND_V = 605
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // ANDi = 606
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // ANDi64 = 607
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ANDi_MM = 608
+ Feature_HasDSPR2 | 0, // APPEND = 609
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // APPEND_MMR2 = 610
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ASUB_S_B = 611
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ASUB_S_D = 612
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ASUB_S_H = 613
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ASUB_S_W = 614
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ASUB_U_B = 615
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ASUB_U_D = 616
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ASUB_U_H = 617
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ASUB_U_W = 618
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // AUI = 619
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // AUIPC = 620
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // AUIPC_MMR6 = 621
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // AUI_MMR6 = 622
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVER_S_B = 623
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVER_S_D = 624
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVER_S_H = 625
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVER_S_W = 626
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVER_U_B = 627
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVER_U_D = 628
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVER_U_H = 629
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVER_U_W = 630
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVE_S_B = 631
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVE_S_D = 632
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVE_S_H = 633
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVE_S_W = 634
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVE_U_B = 635
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVE_U_D = 636
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVE_U_H = 637
+ Feature_HasStdEnc | Feature_HasMSA | 0, // AVE_U_W = 638
+ Feature_InMips16Mode | 0, // AddiuRxImmX16 = 639
+ Feature_InMips16Mode | 0, // AddiuRxPcImmX16 = 640
+ Feature_InMips16Mode | 0, // AddiuRxRxImm16 = 641
+ Feature_InMips16Mode | 0, // AddiuRxRxImmX16 = 642
+ Feature_InMips16Mode | 0, // AddiuRxRyOffMemX16 = 643
+ Feature_InMips16Mode | 0, // AddiuSpImm16 = 644
+ Feature_InMips16Mode | 0, // AddiuSpImmX16 = 645
+ Feature_InMips16Mode | 0, // AdduRxRyRz16 = 646
+ Feature_InMips16Mode | 0, // AndRxRxRy16 = 647
+ Feature_InMicroMips | 0, // B16_MM = 648
+ Feature_HasCnMips | 0, // BADDu = 649
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // BAL = 650
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // BALC = 651
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BALC_MMR6 = 652
+ Feature_HasDSPR2 | 0, // BALIGN = 653
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // BALIGN_MMR2 = 654
+ Feature_HasCnMips | 0, // BBIT0 = 655
+ Feature_HasCnMips | 0, // BBIT032 = 656
+ Feature_HasCnMips | 0, // BBIT1 = 657
+ Feature_HasCnMips | 0, // BBIT132 = 658
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BC = 659
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BC16_MMR6 = 660
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // BC1EQZ = 661
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // BC1EQZC_MMR6 = 662
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // BC1F = 663
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // BC1FL = 664
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // BC1F_MM = 665
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // BC1NEZ = 666
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // BC1NEZC_MMR6 = 667
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // BC1T = 668
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // BC1TL = 669
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // BC1T_MM = 670
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BC2EQZ = 671
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BC2EQZC_MMR6 = 672
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BC2NEZ = 673
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BC2NEZC_MMR6 = 674
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BCLRI_B = 675
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BCLRI_D = 676
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BCLRI_H = 677
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BCLRI_W = 678
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BCLR_B = 679
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BCLR_D = 680
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BCLR_H = 681
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BCLR_W = 682
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BC_MMR6 = 683
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BEQ = 684
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // BEQ64 = 685
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BEQC = 686
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BEQC64 = 687
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BEQC_MMR6 = 688
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BEQL = 689
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BEQZ16_MM = 690
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BEQZALC = 691
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BEQZALC_MMR6 = 692
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BEQZC = 693
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BEQZC16_MMR6 = 694
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BEQZC64 = 695
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BEQZC_MM = 696
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BEQZC_MMR6 = 697
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BEQ_MM = 698
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BGEC = 699
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BGEC64 = 700
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BGEC_MMR6 = 701
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BGEUC = 702
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BGEUC64 = 703
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BGEUC_MMR6 = 704
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BGEZ = 705
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // BGEZ64 = 706
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BGEZAL = 707
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BGEZALC = 708
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BGEZALC_MMR6 = 709
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BGEZALL = 710
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BGEZALS_MM = 711
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BGEZAL_MM = 712
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BGEZC = 713
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BGEZC64 = 714
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BGEZC_MMR6 = 715
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BGEZL = 716
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BGEZ_MM = 717
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BGTZ = 718
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // BGTZ64 = 719
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BGTZALC = 720
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BGTZALC_MMR6 = 721
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BGTZC = 722
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BGTZC64 = 723
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BGTZC_MMR6 = 724
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BGTZL = 725
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BGTZ_MM = 726
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSLI_B = 727
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSLI_D = 728
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSLI_H = 729
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSLI_W = 730
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSL_B = 731
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSL_D = 732
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSL_H = 733
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSL_W = 734
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSRI_B = 735
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSRI_D = 736
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSRI_H = 737
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSRI_W = 738
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSR_B = 739
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSR_D = 740
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSR_H = 741
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BINSR_W = 742
+ Feature_HasDSP | 0, // BITREV = 743
+ Feature_InMicroMips | Feature_HasDSP | 0, // BITREV_MM = 744
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // BITSWAP = 745
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BITSWAP_MMR6 = 746
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BLEZ = 747
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // BLEZ64 = 748
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BLEZALC = 749
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BLEZALC_MMR6 = 750
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BLEZC = 751
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BLEZC64 = 752
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BLEZC_MMR6 = 753
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BLEZL = 754
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BLEZ_MM = 755
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BLTC = 756
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BLTC64 = 757
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BLTC_MMR6 = 758
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BLTUC = 759
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BLTUC64 = 760
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BLTUC_MMR6 = 761
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BLTZ = 762
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // BLTZ64 = 763
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BLTZAL = 764
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BLTZALC = 765
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BLTZALC_MMR6 = 766
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BLTZALL = 767
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BLTZALS_MM = 768
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BLTZAL_MM = 769
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BLTZC = 770
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BLTZC64 = 771
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BLTZC_MMR6 = 772
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BLTZL = 773
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BLTZ_MM = 774
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BMNZI_B = 775
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BMNZ_V = 776
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BMZI_B = 777
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BMZ_V = 778
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BNE = 779
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // BNE64 = 780
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BNEC = 781
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BNEC64 = 782
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BNEC_MMR6 = 783
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNEGI_B = 784
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNEGI_D = 785
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNEGI_H = 786
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNEGI_W = 787
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNEG_B = 788
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNEG_D = 789
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNEG_H = 790
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNEG_W = 791
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // BNEL = 792
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BNEZ16_MM = 793
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BNEZALC = 794
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BNEZALC_MMR6 = 795
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BNEZC = 796
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BNEZC16_MMR6 = 797
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // BNEZC64 = 798
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BNEZC_MM = 799
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BNEZC_MMR6 = 800
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BNE_MM = 801
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BNVC = 802
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BNVC_MMR6 = 803
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNZ_B = 804
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNZ_D = 805
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNZ_H = 806
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNZ_V = 807
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BNZ_W = 808
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // BOVC = 809
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BOVC_MMR6 = 810
+ Feature_HasDSP | Feature_NotInMicroMips | 0, // BPOSGE32 = 811
+ Feature_InMicroMips | Feature_HasDSPR3 | 0, // BPOSGE32C_MMR3 = 812
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_HasDSP | 0, // BPOSGE32_MM = 813
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // BREAK = 814
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // BREAK16_MM = 815
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BREAK16_MMR6 = 816
+ Feature_InMicroMips | 0, // BREAK_MM = 817
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // BREAK_MMR6 = 818
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSELI_B = 819
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSEL_V = 820
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSETI_B = 821
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSETI_D = 822
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSETI_H = 823
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSETI_W = 824
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSET_B = 825
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSET_D = 826
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSET_H = 827
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BSET_W = 828
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BZ_B = 829
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BZ_D = 830
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BZ_H = 831
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BZ_V = 832
+ Feature_HasStdEnc | Feature_HasMSA | 0, // BZ_W = 833
+ Feature_InMips16Mode | 0, // BeqzRxImm16 = 834
+ Feature_InMips16Mode | 0, // BeqzRxImmX16 = 835
+ Feature_InMips16Mode | 0, // Bimm16 = 836
+ Feature_InMips16Mode | 0, // BimmX16 = 837
+ Feature_InMips16Mode | 0, // BnezRxImm16 = 838
+ Feature_InMips16Mode | 0, // BnezRxImmX16 = 839
+ Feature_InMips16Mode | 0, // Break16 = 840
+ Feature_InMips16Mode | 0, // Bteqz16 = 841
+ Feature_InMips16Mode | 0, // BteqzX16 = 842
+ Feature_InMips16Mode | 0, // Btnez16 = 843
+ Feature_InMips16Mode | 0, // BtnezX16 = 844
+ Feature_HasStdEnc | Feature_HasMips3_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // CACHE = 845
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // CACHEE = 846
+ Feature_InMicroMips | Feature_HasEVA | 0, // CACHEE_MM = 847
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // CACHE_MM = 848
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // CACHE_MMR6 = 849
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // CACHE_R6 = 850
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips3_32 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CEIL_L_D64 = 851
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CEIL_L_D_MMR6 = 852
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CEIL_L_S = 853
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CEIL_L_S_MMR6 = 854
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CEIL_W_D32 = 855
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CEIL_W_D64 = 856
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CEIL_W_D_MMR6 = 857
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // CEIL_W_MM = 858
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CEIL_W_S = 859
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // CEIL_W_S_MM = 860
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CEIL_W_S_MMR6 = 861
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CEQI_B = 862
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CEQI_D = 863
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CEQI_H = 864
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CEQI_W = 865
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CEQ_B = 866
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CEQ_D = 867
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CEQ_H = 868
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CEQ_W = 869
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CFC1 = 870
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // CFC1_MM = 871
+ Feature_InMicroMips | 0, // CFC2_MM = 872
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CFCMSA = 873
+ Feature_HasMips64 | Feature_HasCnMips | Feature_NotInMicroMips | 0, // CINS = 874
+ Feature_HasMips64 | Feature_HasCnMips | Feature_NotInMicroMips | 0, // CINS32 = 875
+ Feature_HasMips64 | Feature_HasCnMips | Feature_NotInMicroMips | 0, // CINS64_32 = 876
+ Feature_HasMips64 | Feature_HasCnMips | Feature_NotInMicroMips | 0, // CINS_i32 = 877
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CLASS_D = 878
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // CLASS_D_MMR6 = 879
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CLASS_S = 880
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // CLASS_S_MMR6 = 881
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLEI_S_B = 882
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLEI_S_D = 883
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLEI_S_H = 884
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLEI_S_W = 885
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLEI_U_B = 886
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLEI_U_D = 887
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLEI_U_H = 888
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLEI_U_W = 889
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLE_S_B = 890
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLE_S_D = 891
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLE_S_H = 892
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLE_S_W = 893
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLE_U_B = 894
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLE_U_D = 895
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLE_U_H = 896
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLE_U_W = 897
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // CLO = 898
+ Feature_InMicroMips | 0, // CLO_MM = 899
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // CLO_MMR6 = 900
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // CLO_R6 = 901
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLTI_S_B = 902
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLTI_S_D = 903
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLTI_S_H = 904
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLTI_S_W = 905
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLTI_U_B = 906
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLTI_U_D = 907
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLTI_U_H = 908
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLTI_U_W = 909
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLT_S_B = 910
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLT_S_D = 911
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLT_S_H = 912
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLT_S_W = 913
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLT_U_B = 914
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLT_U_D = 915
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLT_U_H = 916
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CLT_U_W = 917
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // CLZ = 918
+ Feature_InMicroMips | 0, // CLZ_MM = 919
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // CLZ_MMR6 = 920
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // CLZ_R6 = 921
+ Feature_HasDSPR2 | 0, // CMPGDU_EQ_QB = 922
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // CMPGDU_EQ_QB_MMR2 = 923
+ Feature_HasDSPR2 | 0, // CMPGDU_LE_QB = 924
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // CMPGDU_LE_QB_MMR2 = 925
+ Feature_HasDSPR2 | 0, // CMPGDU_LT_QB = 926
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // CMPGDU_LT_QB_MMR2 = 927
+ Feature_HasDSP | 0, // CMPGU_EQ_QB = 928
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMPGU_EQ_QB_MM = 929
+ Feature_HasDSP | 0, // CMPGU_LE_QB = 930
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMPGU_LE_QB_MM = 931
+ Feature_HasDSP | 0, // CMPGU_LT_QB = 932
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMPGU_LT_QB_MM = 933
+ Feature_HasDSP | 0, // CMPU_EQ_QB = 934
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMPU_EQ_QB_MM = 935
+ Feature_HasDSP | 0, // CMPU_LE_QB = 936
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMPU_LE_QB_MM = 937
+ Feature_HasDSP | 0, // CMPU_LT_QB = 938
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMPU_LT_QB_MM = 939
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_AF_D_MMR6 = 940
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_AF_S_MMR6 = 941
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_EQ_D = 942
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_EQ_D_MMR6 = 943
+ Feature_HasDSP | 0, // CMP_EQ_PH = 944
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMP_EQ_PH_MM = 945
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_EQ_S = 946
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_EQ_S_MMR6 = 947
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_F_D = 948
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_F_S = 949
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_LE_D = 950
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_LE_D_MMR6 = 951
+ Feature_HasDSP | 0, // CMP_LE_PH = 952
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMP_LE_PH_MM = 953
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_LE_S = 954
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_LE_S_MMR6 = 955
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_LT_D = 956
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_LT_D_MMR6 = 957
+ Feature_HasDSP | 0, // CMP_LT_PH = 958
+ Feature_InMicroMips | Feature_HasDSP | 0, // CMP_LT_PH_MM = 959
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_LT_S = 960
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_LT_S_MMR6 = 961
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SAF_D = 962
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SAF_D_MMR6 = 963
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SAF_S = 964
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SAF_S_MMR6 = 965
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SEQ_D = 966
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SEQ_D_MMR6 = 967
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SEQ_S = 968
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SEQ_S_MMR6 = 969
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SLE_D = 970
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SLE_D_MMR6 = 971
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SLE_S = 972
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SLE_S_MMR6 = 973
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SLT_D = 974
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SLT_D_MMR6 = 975
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SLT_S = 976
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SLT_S_MMR6 = 977
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SUEQ_D = 978
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SUEQ_D_MMR6 = 979
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SUEQ_S = 980
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SUEQ_S_MMR6 = 981
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SULE_D = 982
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SULE_D_MMR6 = 983
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SULE_S = 984
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SULE_S_MMR6 = 985
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SULT_D = 986
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SULT_D_MMR6 = 987
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SULT_S = 988
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SULT_S_MMR6 = 989
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SUN_D = 990
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SUN_D_MMR6 = 991
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_SUN_S = 992
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_SUN_S_MMR6 = 993
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_UEQ_D = 994
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_UEQ_D_MMR6 = 995
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_UEQ_S = 996
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_UEQ_S_MMR6 = 997
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_ULE_D = 998
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_ULE_D_MMR6 = 999
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_ULE_S = 1000
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_ULE_S_MMR6 = 1001
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_ULT_D = 1002
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_ULT_D_MMR6 = 1003
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_ULT_S = 1004
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_ULT_S_MMR6 = 1005
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_UN_D = 1006
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_UN_D_MMR6 = 1007
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CMP_UN_S = 1008
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CMP_UN_S_MMR6 = 1009
+ Feature_HasStdEnc | Feature_HasMSA | 0, // COPY_S_B = 1010
+ Feature_HasStdEnc | Feature_HasMSA | Feature_HasMips64 | 0, // COPY_S_D = 1011
+ Feature_HasStdEnc | Feature_HasMSA | 0, // COPY_S_H = 1012
+ Feature_HasStdEnc | Feature_HasMSA | 0, // COPY_S_W = 1013
+ Feature_HasStdEnc | Feature_HasMSA | 0, // COPY_U_B = 1014
+ Feature_HasStdEnc | Feature_HasMSA | 0, // COPY_U_H = 1015
+ Feature_HasStdEnc | Feature_HasMSA | Feature_HasMips64 | 0, // COPY_U_W = 1016
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_HasCRC | Feature_NotInMicroMips | 0, // CRC32B = 1017
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_HasCRC | Feature_NotInMicroMips | 0, // CRC32CB = 1018
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_HasCRC | Feature_NotInMicroMips | 0, // CRC32CD = 1019
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_HasCRC | Feature_NotInMicroMips | 0, // CRC32CH = 1020
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_HasCRC | Feature_NotInMicroMips | 0, // CRC32CW = 1021
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_HasCRC | Feature_NotInMicroMips | 0, // CRC32D = 1022
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_HasCRC | Feature_NotInMicroMips | 0, // CRC32H = 1023
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_HasCRC | Feature_NotInMicroMips | 0, // CRC32W = 1024
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CTC1 = 1025
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // CTC1_MM = 1026
+ Feature_InMicroMips | 0, // CTC2_MM = 1027
+ Feature_HasStdEnc | Feature_HasMSA | 0, // CTCMSA = 1028
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_D32_S = 1029
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // CVT_D32_S_MM = 1030
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_D32_W = 1031
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // CVT_D32_W_MM = 1032
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips3_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_D64_L = 1033
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_D64_S = 1034
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // CVT_D64_S_MM = 1035
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_D64_W = 1036
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // CVT_D64_W_MM = 1037
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CVT_D_L_MMR6 = 1038
+ Feature_HasStdEnc | Feature_HasMips3_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_L_D64 = 1039
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // CVT_L_D64_MM = 1040
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CVT_L_D_MMR6 = 1041
+ Feature_HasStdEnc | Feature_HasMips3_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_L_S = 1042
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // CVT_L_S_MM = 1043
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CVT_L_S_MMR6 = 1044
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_S_D32 = 1045
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // CVT_S_D32_MM = 1046
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_S_D64 = 1047
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // CVT_S_D64_MM = 1048
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips3_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_S_L = 1049
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CVT_S_L_MMR6 = 1050
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_S_W = 1051
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // CVT_S_W_MM = 1052
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CVT_S_W_MMR6 = 1053
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_W_D32 = 1054
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // CVT_W_D32_MM = 1055
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_W_D64 = 1056
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // CVT_W_D64_MM = 1057
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // CVT_W_S = 1058
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // CVT_W_S_MM = 1059
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // CVT_W_S_MMR6 = 1060
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_EQ_D32 = 1061
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_EQ_D32_MM = 1062
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_EQ_D64 = 1063
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_EQ_D64_MM = 1064
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_EQ_S = 1065
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_EQ_S_MM = 1066
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_F_D32 = 1067
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_F_D32_MM = 1068
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_F_D64 = 1069
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_F_D64_MM = 1070
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_F_S = 1071
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_F_S_MM = 1072
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_LE_D32 = 1073
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_LE_D32_MM = 1074
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_LE_D64 = 1075
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_LE_D64_MM = 1076
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_LE_S = 1077
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_LE_S_MM = 1078
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_LT_D32 = 1079
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_LT_D32_MM = 1080
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_LT_D64 = 1081
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_LT_D64_MM = 1082
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_LT_S = 1083
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_LT_S_MM = 1084
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGE_D32 = 1085
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGE_D32_MM = 1086
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGE_D64 = 1087
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGE_D64_MM = 1088
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGE_S = 1089
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGE_S_MM = 1090
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGLE_D32 = 1091
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGLE_D32_MM = 1092
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGLE_D64 = 1093
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGLE_D64_MM = 1094
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGLE_S = 1095
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGLE_S_MM = 1096
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGL_D32 = 1097
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGL_D32_MM = 1098
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGL_D64 = 1099
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGL_D64_MM = 1100
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGL_S = 1101
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGL_S_MM = 1102
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGT_D32 = 1103
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGT_D32_MM = 1104
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGT_D64 = 1105
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGT_D64_MM = 1106
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_NGT_S = 1107
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_NGT_S_MM = 1108
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_OLE_D32 = 1109
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_OLE_D32_MM = 1110
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_OLE_D64 = 1111
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_OLE_D64_MM = 1112
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_OLE_S = 1113
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_OLE_S_MM = 1114
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_OLT_D32 = 1115
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_OLT_D32_MM = 1116
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_OLT_D64 = 1117
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_OLT_D64_MM = 1118
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_OLT_S = 1119
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_OLT_S_MM = 1120
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_SEQ_D32 = 1121
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_SEQ_D32_MM = 1122
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_SEQ_D64 = 1123
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_SEQ_D64_MM = 1124
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_SEQ_S = 1125
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_SEQ_S_MM = 1126
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_SF_D32 = 1127
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_SF_D32_MM = 1128
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_SF_D64 = 1129
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_SF_D64_MM = 1130
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_SF_S = 1131
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_SF_S_MM = 1132
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_UEQ_D32 = 1133
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_UEQ_D32_MM = 1134
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_UEQ_D64 = 1135
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_UEQ_D64_MM = 1136
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_UEQ_S = 1137
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_UEQ_S_MM = 1138
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_ULE_D32 = 1139
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_ULE_D32_MM = 1140
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_ULE_D64 = 1141
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_ULE_D64_MM = 1142
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_ULE_S = 1143
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_ULE_S_MM = 1144
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_ULT_D32 = 1145
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_ULT_D32_MM = 1146
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_ULT_D64 = 1147
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_ULT_D64_MM = 1148
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_ULT_S = 1149
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_ULT_S_MM = 1150
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_UN_D32 = 1151
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_UN_D32_MM = 1152
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_UN_D64 = 1153
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_UN_D64_MM = 1154
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // C_UN_S = 1155
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // C_UN_S_MM = 1156
+ Feature_InMips16Mode | 0, // CmpRxRy16 = 1157
+ Feature_InMips16Mode | 0, // CmpiRxImm16 = 1158
+ Feature_InMips16Mode | 0, // CmpiRxImmX16 = 1159
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DADD = 1160
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // DADDi = 1161
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DADDiu = 1162
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DADDu = 1163
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DAHI = 1164
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DALIGN = 1165
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DATI = 1166
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DAUI = 1167
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DBITSWAP = 1168
+ Feature_HasStdEnc | Feature_HasMips64 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DCLO = 1169
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DCLO_R6 = 1170
+ Feature_HasStdEnc | Feature_HasMips64 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DCLZ = 1171
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DCLZ_R6 = 1172
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DDIV = 1173
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DDIVU = 1174
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotInMicroMips | 0, // DERET = 1175
+ Feature_InMicroMips | 0, // DERET_MM = 1176
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // DERET_MMR6 = 1177
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DEXT = 1178
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DEXT64_32 = 1179
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DEXTM = 1180
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DEXTU = 1181
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // DI = 1182
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DINS = 1183
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DINSM = 1184
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DINSU = 1185
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // DIV = 1186
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // DIVU = 1187
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // DIVU_MMR6 = 1188
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // DIV_MMR6 = 1189
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DIV_S_B = 1190
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DIV_S_D = 1191
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DIV_S_H = 1192
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DIV_S_W = 1193
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DIV_U_B = 1194
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DIV_U_D = 1195
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DIV_U_H = 1196
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DIV_U_W = 1197
+ Feature_InMicroMips | 0, // DI_MM = 1198
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // DI_MMR6 = 1199
+ Feature_HasStdEnc | Feature_HasMSA | Feature_HasMips64 | 0, // DLSA = 1200
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DLSA_R6 = 1201
+ Feature_HasMips64 | 0, // DMFC0 = 1202
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // DMFC1 = 1203
+ Feature_HasMips64 | 0, // DMFC2 = 1204
+ Feature_HasCnMips | 0, // DMFC2_OCTEON = 1205
+ Feature_HasStdEnc | Feature_HasMips64r5 | Feature_HasVirt | 0, // DMFGC0 = 1206
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DMOD = 1207
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DMODU = 1208
+ Feature_HasStdEnc | Feature_HasMT | Feature_NotInMicroMips | 0, // DMT = 1209
+ Feature_HasMips64 | 0, // DMTC0 = 1210
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // DMTC1 = 1211
+ Feature_HasMips64 | 0, // DMTC2 = 1212
+ Feature_HasCnMips | 0, // DMTC2_OCTEON = 1213
+ Feature_HasStdEnc | Feature_HasMips64r5 | Feature_HasVirt | 0, // DMTGC0 = 1214
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DMUH = 1215
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DMUHU = 1216
+ Feature_HasCnMips | 0, // DMUL = 1217
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DMULT = 1218
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DMULTu = 1219
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DMULU = 1220
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // DMUL_R6 = 1221
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DOTP_S_D = 1222
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DOTP_S_H = 1223
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DOTP_S_W = 1224
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DOTP_U_D = 1225
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DOTP_U_H = 1226
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DOTP_U_W = 1227
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPADD_S_D = 1228
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPADD_S_H = 1229
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPADD_S_W = 1230
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPADD_U_D = 1231
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPADD_U_H = 1232
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPADD_U_W = 1233
+ Feature_HasDSPR2 | 0, // DPAQX_SA_W_PH = 1234
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // DPAQX_SA_W_PH_MMR2 = 1235
+ Feature_HasDSPR2 | 0, // DPAQX_S_W_PH = 1236
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // DPAQX_S_W_PH_MMR2 = 1237
+ Feature_HasDSP | 0, // DPAQ_SA_L_W = 1238
+ Feature_InMicroMips | Feature_HasDSP | 0, // DPAQ_SA_L_W_MM = 1239
+ Feature_HasDSP | 0, // DPAQ_S_W_PH = 1240
+ Feature_InMicroMips | Feature_HasDSP | 0, // DPAQ_S_W_PH_MM = 1241
+ Feature_HasDSP | 0, // DPAU_H_QBL = 1242
+ Feature_InMicroMips | Feature_HasDSP | 0, // DPAU_H_QBL_MM = 1243
+ Feature_HasDSP | 0, // DPAU_H_QBR = 1244
+ Feature_InMicroMips | Feature_HasDSP | 0, // DPAU_H_QBR_MM = 1245
+ Feature_HasDSPR2 | 0, // DPAX_W_PH = 1246
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // DPAX_W_PH_MMR2 = 1247
+ Feature_HasDSPR2 | 0, // DPA_W_PH = 1248
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // DPA_W_PH_MMR2 = 1249
+ Feature_HasCnMips | 0, // DPOP = 1250
+ Feature_HasDSPR2 | 0, // DPSQX_SA_W_PH = 1251
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // DPSQX_SA_W_PH_MMR2 = 1252
+ Feature_HasDSPR2 | 0, // DPSQX_S_W_PH = 1253
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // DPSQX_S_W_PH_MMR2 = 1254
+ Feature_HasDSP | 0, // DPSQ_SA_L_W = 1255
+ Feature_InMicroMips | Feature_HasDSP | 0, // DPSQ_SA_L_W_MM = 1256
+ Feature_HasDSP | 0, // DPSQ_S_W_PH = 1257
+ Feature_InMicroMips | Feature_HasDSP | 0, // DPSQ_S_W_PH_MM = 1258
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPSUB_S_D = 1259
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPSUB_S_H = 1260
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPSUB_S_W = 1261
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPSUB_U_D = 1262
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPSUB_U_H = 1263
+ Feature_HasStdEnc | Feature_HasMSA | 0, // DPSUB_U_W = 1264
+ Feature_HasDSP | 0, // DPSU_H_QBL = 1265
+ Feature_InMicroMips | Feature_HasDSP | 0, // DPSU_H_QBL_MM = 1266
+ Feature_HasDSP | 0, // DPSU_H_QBR = 1267
+ Feature_InMicroMips | Feature_HasDSP | 0, // DPSU_H_QBR_MM = 1268
+ Feature_HasDSPR2 | 0, // DPSX_W_PH = 1269
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // DPSX_W_PH_MMR2 = 1270
+ Feature_HasDSPR2 | 0, // DPS_W_PH = 1271
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // DPS_W_PH_MMR2 = 1272
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DROTR = 1273
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DROTR32 = 1274
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DROTRV = 1275
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DSBH = 1276
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DSDIV = 1277
+ Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DSHD = 1278
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSLL = 1279
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSLL32 = 1280
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // DSLL64_32 = 1281
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSLLV = 1282
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRA = 1283
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRA32 = 1284
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRAV = 1285
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRL = 1286
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRL32 = 1287
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSRLV = 1288
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSUB = 1289
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // DSUBu = 1290
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // DUDIV = 1291
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // DVP = 1292
+ Feature_HasStdEnc | Feature_HasMT | Feature_NotInMicroMips | 0, // DVPE = 1293
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // DVP_MMR6 = 1294
+ Feature_InMips16Mode | 0, // DivRxRy16 = 1295
+ Feature_InMips16Mode | 0, // DivuRxRy16 = 1296
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // EHB = 1297
+ Feature_InMicroMips | 0, // EHB_MM = 1298
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // EHB_MMR6 = 1299
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // EI = 1300
+ Feature_InMicroMips | 0, // EI_MM = 1301
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // EI_MMR6 = 1302
+ Feature_HasStdEnc | Feature_HasMT | Feature_NotInMicroMips | 0, // EMT = 1303
+ Feature_HasStdEnc | Feature_HasMips3_32 | Feature_NotInMicroMips | 0, // ERET = 1304
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_NotInMicroMips | 0, // ERETNC = 1305
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ERETNC_MMR6 = 1306
+ Feature_InMicroMips | 0, // ERET_MM = 1307
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ERET_MMR6 = 1308
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // EVP = 1309
+ Feature_HasStdEnc | Feature_HasMT | Feature_NotInMicroMips | 0, // EVPE = 1310
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // EVP_MMR6 = 1311
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // EXT = 1312
+ Feature_HasDSP | 0, // EXTP = 1313
+ Feature_HasDSP | 0, // EXTPDP = 1314
+ Feature_HasDSP | 0, // EXTPDPV = 1315
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTPDPV_MM = 1316
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTPDP_MM = 1317
+ Feature_HasDSP | 0, // EXTPV = 1318
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTPV_MM = 1319
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTP_MM = 1320
+ Feature_HasDSP | 0, // EXTRV_RS_W = 1321
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTRV_RS_W_MM = 1322
+ Feature_HasDSP | 0, // EXTRV_R_W = 1323
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTRV_R_W_MM = 1324
+ Feature_HasDSP | 0, // EXTRV_S_H = 1325
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTRV_S_H_MM = 1326
+ Feature_HasDSP | 0, // EXTRV_W = 1327
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTRV_W_MM = 1328
+ Feature_HasDSP | 0, // EXTR_RS_W = 1329
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTR_RS_W_MM = 1330
+ Feature_HasDSP | 0, // EXTR_R_W = 1331
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTR_R_W_MM = 1332
+ Feature_HasDSP | 0, // EXTR_S_H = 1333
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTR_S_H_MM = 1334
+ Feature_HasDSP | 0, // EXTR_W = 1335
+ Feature_InMicroMips | Feature_HasDSP | 0, // EXTR_W_MM = 1336
+ Feature_HasMips64 | Feature_HasCnMips | Feature_NotInMicroMips | 0, // EXTS = 1337
+ Feature_HasMips64 | Feature_HasCnMips | Feature_NotInMicroMips | 0, // EXTS32 = 1338
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // EXT_MM = 1339
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // EXT_MMR6 = 1340
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FABS_D32 = 1341
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FABS_D32_MM = 1342
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FABS_D64 = 1343
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // FABS_D64_MM = 1344
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FABS_S = 1345
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FABS_S_MM = 1346
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FADD_D = 1347
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FADD_D32 = 1348
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FADD_D32_MM = 1349
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FADD_D64 = 1350
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // FADD_D64_MM = 1351
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FADD_S = 1352
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FADD_S_MM = 1353
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FADD_S_MMR6 = 1354
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FADD_W = 1355
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCAF_D = 1356
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCAF_W = 1357
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCEQ_D = 1358
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCEQ_W = 1359
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCLASS_D = 1360
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCLASS_W = 1361
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCLE_D = 1362
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCLE_W = 1363
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCLT_D = 1364
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCLT_W = 1365
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FCMP_D32 = 1366
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // FCMP_D32_MM = 1367
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | 0, // FCMP_D64 = 1368
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FCMP_S32 = 1369
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // FCMP_S32_MM = 1370
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCNE_D = 1371
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCNE_W = 1372
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCOR_D = 1373
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCOR_W = 1374
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCUEQ_D = 1375
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCUEQ_W = 1376
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCULE_D = 1377
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCULE_W = 1378
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCULT_D = 1379
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCULT_W = 1380
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCUNE_D = 1381
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCUNE_W = 1382
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCUN_D = 1383
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FCUN_W = 1384
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FDIV_D = 1385
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FDIV_D32 = 1386
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FDIV_D32_MM = 1387
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FDIV_D64 = 1388
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // FDIV_D64_MM = 1389
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FDIV_S = 1390
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FDIV_S_MM = 1391
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FDIV_S_MMR6 = 1392
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FDIV_W = 1393
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXDO_H = 1394
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXDO_W = 1395
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXP2_D = 1396
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXP2_W = 1397
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXUPL_D = 1398
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXUPL_W = 1399
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXUPR_D = 1400
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FEXUPR_W = 1401
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FFINT_S_D = 1402
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FFINT_S_W = 1403
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FFINT_U_D = 1404
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FFINT_U_W = 1405
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FFQL_D = 1406
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FFQL_W = 1407
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FFQR_D = 1408
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FFQR_W = 1409
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FILL_B = 1410
+ Feature_HasStdEnc | Feature_HasMSA | Feature_HasMips64 | 0, // FILL_D = 1411
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FILL_H = 1412
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FILL_W = 1413
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FLOG2_D = 1414
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FLOG2_W = 1415
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips3_32 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FLOOR_L_D64 = 1416
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FLOOR_L_D_MMR6 = 1417
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FLOOR_L_S = 1418
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FLOOR_L_S_MMR6 = 1419
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FLOOR_W_D32 = 1420
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FLOOR_W_D64 = 1421
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FLOOR_W_D_MMR6 = 1422
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FLOOR_W_MM = 1423
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FLOOR_W_S = 1424
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FLOOR_W_S_MM = 1425
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FLOOR_W_S_MMR6 = 1426
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMADD_D = 1427
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMADD_W = 1428
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMAX_A_D = 1429
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMAX_A_W = 1430
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMAX_D = 1431
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMAX_W = 1432
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMIN_A_D = 1433
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMIN_A_W = 1434
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMIN_D = 1435
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMIN_W = 1436
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FMOV_D32 = 1437
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FMOV_D32_MM = 1438
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FMOV_D64 = 1439
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // FMOV_D64_MM = 1440
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FMOV_S = 1441
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FMOV_S_MM = 1442
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FMOV_S_MMR6 = 1443
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMSUB_D = 1444
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMSUB_W = 1445
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMUL_D = 1446
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FMUL_D32 = 1447
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FMUL_D32_MM = 1448
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FMUL_D64 = 1449
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // FMUL_D64_MM = 1450
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FMUL_S = 1451
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FMUL_S_MM = 1452
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FMUL_S_MMR6 = 1453
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FMUL_W = 1454
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FNEG_D32 = 1455
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FNEG_D32_MM = 1456
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FNEG_D64 = 1457
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // FNEG_D64_MM = 1458
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | 0, // FNEG_S = 1459
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FNEG_S_MM = 1460
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FNEG_S_MMR6 = 1461
+ Feature_HasStdEnc | Feature_HasMT | Feature_NotInMicroMips | 0, // FORK = 1462
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FRCP_D = 1463
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FRCP_W = 1464
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FRINT_D = 1465
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FRINT_W = 1466
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FRSQRT_D = 1467
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FRSQRT_W = 1468
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSAF_D = 1469
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSAF_W = 1470
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSEQ_D = 1471
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSEQ_W = 1472
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSLE_D = 1473
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSLE_W = 1474
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSLT_D = 1475
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSLT_W = 1476
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSNE_D = 1477
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSNE_W = 1478
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSOR_D = 1479
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSOR_W = 1480
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSQRT_D = 1481
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FSQRT_D32 = 1482
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FSQRT_D32_MM = 1483
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FSQRT_D64 = 1484
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // FSQRT_D64_MM = 1485
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FSQRT_S = 1486
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FSQRT_S_MM = 1487
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSQRT_W = 1488
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSUB_D = 1489
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FSUB_D32 = 1490
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // FSUB_D32_MM = 1491
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FSUB_D64 = 1492
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // FSUB_D64_MM = 1493
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // FSUB_S = 1494
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // FSUB_S_MM = 1495
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // FSUB_S_MMR6 = 1496
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSUB_W = 1497
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSUEQ_D = 1498
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSUEQ_W = 1499
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSULE_D = 1500
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSULE_W = 1501
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSULT_D = 1502
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSULT_W = 1503
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSUNE_D = 1504
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSUNE_W = 1505
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSUN_D = 1506
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FSUN_W = 1507
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTINT_S_D = 1508
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTINT_S_W = 1509
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTINT_U_D = 1510
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTINT_U_W = 1511
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTQ_H = 1512
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTQ_W = 1513
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTRUNC_S_D = 1514
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTRUNC_S_W = 1515
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTRUNC_U_D = 1516
+ Feature_HasStdEnc | Feature_HasMSA | 0, // FTRUNC_U_W = 1517
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_HasGINV | Feature_NotInMicroMips | 0, // GINVI = 1518
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_HasGINV | 0, // GINVI_MMR6 = 1519
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_HasGINV | Feature_NotInMicroMips | 0, // GINVT = 1520
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_HasGINV | 0, // GINVT_MMR6 = 1521
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HADD_S_D = 1522
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HADD_S_H = 1523
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HADD_S_W = 1524
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HADD_U_D = 1525
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HADD_U_H = 1526
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HADD_U_W = 1527
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HSUB_S_D = 1528
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HSUB_S_H = 1529
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HSUB_S_W = 1530
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HSUB_U_D = 1531
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HSUB_U_H = 1532
+ Feature_HasStdEnc | Feature_HasMSA | 0, // HSUB_U_W = 1533
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // HYPCALL = 1534
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // HYPCALL_MM = 1535
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVEV_B = 1536
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVEV_D = 1537
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVEV_H = 1538
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVEV_W = 1539
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVL_B = 1540
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVL_D = 1541
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVL_H = 1542
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVL_W = 1543
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVOD_B = 1544
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVOD_D = 1545
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVOD_H = 1546
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVOD_W = 1547
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVR_B = 1548
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVR_D = 1549
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVR_H = 1550
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ILVR_W = 1551
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // INS = 1552
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_B = 1553
+ Feature_HasStdEnc | Feature_HasMSA | Feature_HasMips64 | 0, // INSERT_D = 1554
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_H = 1555
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSERT_W = 1556
+ Feature_HasDSP | 0, // INSV = 1557
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSVE_B = 1558
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSVE_D = 1559
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSVE_H = 1560
+ Feature_HasStdEnc | Feature_HasMSA | 0, // INSVE_W = 1561
+ Feature_InMicroMips | Feature_HasDSP | 0, // INSV_MM = 1562
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // INS_MM = 1563
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // INS_MMR6 = 1564
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // J = 1565
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // JAL = 1566
+ Feature_HasStdEnc | Feature_NotInMicroMips | Feature_NoIndirectJumpGuards | 0, // JALR = 1567
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JALR16_MM = 1568
+ Feature_NotInMips16Mode | 0, // JALR64 = 1569
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // JALRC16_MMR6 = 1570
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // JALRC_HB_MMR6 = 1571
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // JALRC_MMR6 = 1572
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JALRS16_MM = 1573
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JALRS_MM = 1574
+ Feature_HasStdEnc | Feature_HasMips32 | 0, // JALR_HB = 1575
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // JALR_HB64 = 1576
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JALR_MM = 1577
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JALS_MM = 1578
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // JALX = 1579
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JALX_MM = 1580
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JAL_MM = 1581
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // JIALC = 1582
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // JIALC64 = 1583
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // JIALC_MMR6 = 1584
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // JIC = 1585
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips64r6 | 0, // JIC64 = 1586
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // JIC_MMR6 = 1587
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // JR = 1588
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JR16_MM = 1589
+ Feature_NotInMips16Mode | Feature_IsPTR64bit | Feature_NotInMicroMips | 0, // JR64 = 1590
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JRADDIUSP = 1591
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JRC16_MM = 1592
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // JRC16_MMR6 = 1593
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // JRCADDIUSP_MMR6 = 1594
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // JR_HB = 1595
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // JR_HB64 = 1596
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // JR_HB64_R6 = 1597
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // JR_HB_R6 = 1598
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // JR_MM = 1599
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // J_MM = 1600
+ Feature_InMips16Mode | 0, // Jal16 = 1601
+ Feature_InMips16Mode | 0, // JalB16 = 1602
+ Feature_InMips16Mode | 0, // JrRa16 = 1603
+ Feature_InMips16Mode | 0, // JrcRa16 = 1604
+ Feature_InMips16Mode | 0, // JrcRx16 = 1605
+ Feature_InMips16Mode | 0, // JumpLinkReg16 = 1606
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // LB = 1607
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LB64 = 1608
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // LBE = 1609
+ Feature_InMicroMips | Feature_HasEVA | 0, // LBE_MM = 1610
+ Feature_InMicroMips | 0, // LBU16_MM = 1611
+ Feature_HasDSP | 0, // LBUX = 1612
+ Feature_InMicroMips | Feature_HasDSP | 0, // LBUX_MM = 1613
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LBU_MMR6 = 1614
+ Feature_InMicroMips | 0, // LB_MM = 1615
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LB_MMR6 = 1616
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // LBu = 1617
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LBu64 = 1618
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // LBuE = 1619
+ Feature_InMicroMips | Feature_HasEVA | 0, // LBuE_MM = 1620
+ Feature_InMicroMips | 0, // LBu_MM = 1621
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // LD = 1622
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // LDC1 = 1623
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // LDC164 = 1624
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // LDC1_D64_MMR6 = 1625
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // LDC1_MM = 1626
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LDC2 = 1627
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LDC2_MMR6 = 1628
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // LDC2_R6 = 1629
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotCnMips | Feature_NotInMicroMips | 0, // LDC3 = 1630
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LDI_B = 1631
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LDI_D = 1632
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LDI_H = 1633
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LDI_W = 1634
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // LDL = 1635
+ Feature_HasStdEnc | Feature_HasMips64r6 | 0, // LDPC = 1636
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // LDR = 1637
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // LDXC1 = 1638
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | 0, // LDXC164 = 1639
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LD_B = 1640
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LD_D = 1641
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LD_H = 1642
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LD_W = 1643
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // LEA_ADDiu = 1644
+ Feature_NotInMips16Mode | Feature_IsGP64bit | Feature_NotInMicroMips | 0, // LEA_ADDiu64 = 1645
+ Feature_InMicroMips | 0, // LEA_ADDiu_MM = 1646
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // LH = 1647
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LH64 = 1648
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // LHE = 1649
+ Feature_InMicroMips | Feature_HasEVA | 0, // LHE_MM = 1650
+ Feature_InMicroMips | 0, // LHU16_MM = 1651
+ Feature_HasDSP | 0, // LHX = 1652
+ Feature_InMicroMips | Feature_HasDSP | 0, // LHX_MM = 1653
+ Feature_InMicroMips | 0, // LH_MM = 1654
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // LHu = 1655
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LHu64 = 1656
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // LHuE = 1657
+ Feature_InMicroMips | Feature_HasEVA | 0, // LHuE_MM = 1658
+ Feature_InMicroMips | 0, // LHu_MM = 1659
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // LI16_MM = 1660
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LI16_MMR6 = 1661
+ Feature_HasStdEnc | Feature_IsPTR32bit | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LL = 1662
+ Feature_HasStdEnc | Feature_IsPTR64bit | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LL64 = 1663
+ Feature_HasStdEnc | Feature_IsPTR64bit | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // LL64_R6 = 1664
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LLD = 1665
+ Feature_HasStdEnc | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // LLD_R6 = 1666
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // LLE = 1667
+ Feature_InMicroMips | Feature_HasEVA | 0, // LLE_MM = 1668
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // LL_MM = 1669
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LL_MMR6 = 1670
+ Feature_HasStdEnc | Feature_IsPTR32bit | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // LL_R6 = 1671
+ Feature_HasStdEnc | Feature_HasMSA | 0, // LSA = 1672
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LSA_MMR6 = 1673
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // LSA_R6 = 1674
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LUI_MMR6 = 1675
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips5_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // LUXC1 = 1676
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips5_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // LUXC164 = 1677
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // LUXC1_MM = 1678
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // LUi = 1679
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LUi64 = 1680
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // LUi_MM = 1681
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // LW = 1682
+ Feature_InMicroMips | 0, // LW16_MM = 1683
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LW64 = 1684
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // LWC1 = 1685
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // LWC1_MM = 1686
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LWC2 = 1687
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LWC2_MMR6 = 1688
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // LWC2_R6 = 1689
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotCnMips | Feature_NotInMicroMips | 0, // LWC3 = 1690
+ Feature_NotInMips16Mode | Feature_HasDSP | 0, // LWDSP = 1691
+ Feature_InMicroMips | Feature_HasDSP | 0, // LWDSP_MM = 1692
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // LWE = 1693
+ Feature_InMicroMips | Feature_HasEVA | 0, // LWE_MM = 1694
+ Feature_InMicroMips | 0, // LWGP_MM = 1695
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LWL = 1696
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LWL64 = 1697
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_HasEVA | Feature_NotInMicroMips | 0, // LWLE = 1698
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_HasEVA | 0, // LWLE_MM = 1699
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // LWL_MM = 1700
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // LWM16_MM = 1701
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LWM16_MMR6 = 1702
+ Feature_InMicroMips | 0, // LWM32_MM = 1703
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // LWPC = 1704
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LWPC_MMR6 = 1705
+ Feature_InMicroMips | 0, // LWP_MM = 1706
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // LWR = 1707
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // LWR64 = 1708
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_HasEVA | Feature_NotInMicroMips | 0, // LWRE = 1709
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_HasEVA | 0, // LWRE_MM = 1710
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // LWR_MM = 1711
+ Feature_InMicroMips | 0, // LWSP_MM = 1712
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // LWUPC = 1713
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // LWU_MM = 1714
+ Feature_HasDSP | 0, // LWX = 1715
+ Feature_HasStdEnc | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | 0, // LWXC1 = 1716
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // LWXC1_MM = 1717
+ Feature_InMicroMips | 0, // LWXS_MM = 1718
+ Feature_InMicroMips | Feature_HasDSP | 0, // LWX_MM = 1719
+ Feature_InMicroMips | 0, // LW_MM = 1720
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // LW_MMR6 = 1721
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // LWu = 1722
+ Feature_InMips16Mode | 0, // LbRxRyOffMemX16 = 1723
+ Feature_InMips16Mode | 0, // LbuRxRyOffMemX16 = 1724
+ Feature_InMips16Mode | 0, // LhRxRyOffMemX16 = 1725
+ Feature_InMips16Mode | 0, // LhuRxRyOffMemX16 = 1726
+ Feature_InMips16Mode | 0, // LiRxImm16 = 1727
+ Feature_InMips16Mode | 0, // LiRxImmAlignX16 = 1728
+ Feature_InMips16Mode | 0, // LiRxImmX16 = 1729
+ Feature_InMips16Mode | 0, // LwRxPcTcp16 = 1730
+ Feature_InMips16Mode | 0, // LwRxPcTcpX16 = 1731
+ Feature_InMips16Mode | 0, // LwRxRyOffMemX16 = 1732
+ Feature_InMips16Mode | 0, // LwRxSpImmX16 = 1733
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MADD = 1734
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MADDF_D = 1735
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MADDF_D_MMR6 = 1736
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MADDF_S = 1737
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MADDF_S_MMR6 = 1738
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MADDR_Q_H = 1739
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MADDR_Q_W = 1740
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MADDU = 1741
+ Feature_HasDSP | 0, // MADDU_DSP = 1742
+ Feature_InMicroMips | Feature_HasDSP | 0, // MADDU_DSP_MM = 1743
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MADDU_MM = 1744
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MADDV_B = 1745
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MADDV_D = 1746
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MADDV_H = 1747
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MADDV_W = 1748
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | Feature_HasMadd4 | 0, // MADD_D32 = 1749
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | 0, // MADD_D32_MM = 1750
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | Feature_HasMadd4 | 0, // MADD_D64 = 1751
+ Feature_HasDSP | 0, // MADD_DSP = 1752
+ Feature_InMicroMips | Feature_HasDSP | 0, // MADD_DSP_MM = 1753
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MADD_MM = 1754
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MADD_Q_H = 1755
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MADD_Q_W = 1756
+ Feature_HasStdEnc | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | Feature_HasMadd4 | 0, // MADD_S = 1757
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | 0, // MADD_S_MM = 1758
+ Feature_HasDSP | 0, // MAQ_SA_W_PHL = 1759
+ Feature_InMicroMips | Feature_HasDSP | 0, // MAQ_SA_W_PHL_MM = 1760
+ Feature_HasDSP | 0, // MAQ_SA_W_PHR = 1761
+ Feature_InMicroMips | Feature_HasDSP | 0, // MAQ_SA_W_PHR_MM = 1762
+ Feature_HasDSP | 0, // MAQ_S_W_PHL = 1763
+ Feature_InMicroMips | Feature_HasDSP | 0, // MAQ_S_W_PHL_MM = 1764
+ Feature_HasDSP | 0, // MAQ_S_W_PHR = 1765
+ Feature_InMicroMips | Feature_HasDSP | 0, // MAQ_S_W_PHR_MM = 1766
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MAXA_D = 1767
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MAXA_D_MMR6 = 1768
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MAXA_S = 1769
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MAXA_S_MMR6 = 1770
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAXI_S_B = 1771
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAXI_S_D = 1772
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAXI_S_H = 1773
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAXI_S_W = 1774
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAXI_U_B = 1775
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAXI_U_D = 1776
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAXI_U_H = 1777
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAXI_U_W = 1778
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_A_B = 1779
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_A_D = 1780
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_A_H = 1781
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_A_W = 1782
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MAX_D = 1783
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MAX_D_MMR6 = 1784
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MAX_S = 1785
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_S_B = 1786
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_S_D = 1787
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_S_H = 1788
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MAX_S_MMR6 = 1789
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_S_W = 1790
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_U_B = 1791
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_U_D = 1792
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_U_H = 1793
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MAX_U_W = 1794
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // MFC0 = 1795
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MFC0_MMR6 = 1796
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MFC1 = 1797
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MFC1_D64 = 1798
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // MFC1_MM = 1799
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MFC1_MMR6 = 1800
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // MFC2 = 1801
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MFC2_MMR6 = 1802
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // MFGC0 = 1803
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // MFGC0_MM = 1804
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MFHC0_MMR6 = 1805
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MFHC1_D32 = 1806
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // MFHC1_D32_MM = 1807
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MFHC1_D64 = 1808
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // MFHC1_D64_MM = 1809
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MFHC2_MMR6 = 1810
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // MFHGC0 = 1811
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // MFHGC0_MM = 1812
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MFHI = 1813
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MFHI16_MM = 1814
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // MFHI64 = 1815
+ Feature_HasDSP | 0, // MFHI_DSP = 1816
+ Feature_InMicroMips | Feature_HasDSP | 0, // MFHI_DSP_MM = 1817
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MFHI_MM = 1818
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MFLO = 1819
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MFLO16_MM = 1820
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // MFLO64 = 1821
+ Feature_HasDSP | 0, // MFLO_DSP = 1822
+ Feature_InMicroMips | Feature_HasDSP | 0, // MFLO_DSP_MM = 1823
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MFLO_MM = 1824
+ Feature_HasStdEnc | Feature_HasMT | Feature_NotInMicroMips | 0, // MFTR = 1825
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MINA_D = 1826
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MINA_D_MMR6 = 1827
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MINA_S = 1828
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MINA_S_MMR6 = 1829
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MINI_S_B = 1830
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MINI_S_D = 1831
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MINI_S_H = 1832
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MINI_S_W = 1833
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MINI_U_B = 1834
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MINI_U_D = 1835
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MINI_U_H = 1836
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MINI_U_W = 1837
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_A_B = 1838
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_A_D = 1839
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_A_H = 1840
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_A_W = 1841
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MIN_D = 1842
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MIN_D_MMR6 = 1843
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MIN_S = 1844
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_S_B = 1845
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_S_D = 1846
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_S_H = 1847
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MIN_S_MMR6 = 1848
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_S_W = 1849
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_U_B = 1850
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_U_D = 1851
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_U_H = 1852
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MIN_U_W = 1853
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // MOD = 1854
+ Feature_HasDSP | 0, // MODSUB = 1855
+ Feature_InMicroMips | Feature_HasDSP | 0, // MODSUB_MM = 1856
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // MODU = 1857
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MODU_MMR6 = 1858
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MOD_MMR6 = 1859
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOD_S_B = 1860
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOD_S_D = 1861
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOD_S_H = 1862
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOD_S_W = 1863
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOD_U_B = 1864
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOD_U_D = 1865
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOD_U_H = 1866
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOD_U_W = 1867
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MOVE16_MM = 1868
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MOVE16_MMR6 = 1869
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MOVEP_MM = 1870
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MOVEP_MMR6 = 1871
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MOVE_V = 1872
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVF_D32 = 1873
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVF_D32_MM = 1874
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVF_D64 = 1875
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVF_I = 1876
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVF_I64 = 1877
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVF_I_MM = 1878
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVF_S = 1879
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVF_S_MM = 1880
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVN_I64_D64 = 1881
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MOVN_I64_I = 1882
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MOVN_I64_I64 = 1883
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVN_I64_S = 1884
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVN_I_D32 = 1885
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVN_I_D32_MM = 1886
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVN_I_D64 = 1887
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MOVN_I_I = 1888
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MOVN_I_I64 = 1889
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MOVN_I_MM = 1890
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVN_I_S = 1891
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVN_I_S_MM = 1892
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVT_D32 = 1893
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVT_D32_MM = 1894
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVT_D64 = 1895
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVT_I = 1896
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVT_I64 = 1897
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVT_I_MM = 1898
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVT_S = 1899
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVT_S_MM = 1900
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVZ_I64_D64 = 1901
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MOVZ_I64_I = 1902
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MOVZ_I64_I64 = 1903
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVZ_I64_S = 1904
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVZ_I_D32 = 1905
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVZ_I_D32_MM = 1906
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVZ_I_D64 = 1907
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MOVZ_I_I = 1908
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MOVZ_I_I64 = 1909
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MOVZ_I_MM = 1910
+ Feature_HasStdEnc | Feature_HasMips4_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MOVZ_I_S = 1911
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // MOVZ_I_S_MM = 1912
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MSUB = 1913
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MSUBF_D = 1914
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MSUBF_D_MMR6 = 1915
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MSUBF_S = 1916
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MSUBF_S_MMR6 = 1917
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MSUBR_Q_H = 1918
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MSUBR_Q_W = 1919
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MSUBU = 1920
+ Feature_HasDSP | 0, // MSUBU_DSP = 1921
+ Feature_InMicroMips | Feature_HasDSP | 0, // MSUBU_DSP_MM = 1922
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MSUBU_MM = 1923
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MSUBV_B = 1924
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MSUBV_D = 1925
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MSUBV_H = 1926
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MSUBV_W = 1927
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | Feature_HasMadd4 | 0, // MSUB_D32 = 1928
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | 0, // MSUB_D32_MM = 1929
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | Feature_HasMadd4 | 0, // MSUB_D64 = 1930
+ Feature_HasDSP | 0, // MSUB_DSP = 1931
+ Feature_InMicroMips | Feature_HasDSP | 0, // MSUB_DSP_MM = 1932
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MSUB_MM = 1933
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MSUB_Q_H = 1934
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MSUB_Q_W = 1935
+ Feature_HasStdEnc | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | Feature_HasMadd4 | 0, // MSUB_S = 1936
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | 0, // MSUB_S_MM = 1937
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // MTC0 = 1938
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MTC0_MMR6 = 1939
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MTC1 = 1940
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MTC1_D64 = 1941
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // MTC1_MM = 1942
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // MTC1_MMR6 = 1943
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // MTC2 = 1944
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MTC2_MMR6 = 1945
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // MTGC0 = 1946
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // MTGC0_MM = 1947
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MTHC0_MMR6 = 1948
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MTHC1_D32 = 1949
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // MTHC1_D32_MM = 1950
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // MTHC1_D64 = 1951
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // MTHC1_D64_MM = 1952
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MTHC2_MMR6 = 1953
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // MTHGC0 = 1954
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // MTHGC0_MM = 1955
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MTHI = 1956
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // MTHI64 = 1957
+ Feature_HasDSP | 0, // MTHI_DSP = 1958
+ Feature_InMicroMips | Feature_HasDSP | 0, // MTHI_DSP_MM = 1959
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MTHI_MM = 1960
+ Feature_HasDSP | 0, // MTHLIP = 1961
+ Feature_InMicroMips | Feature_HasDSP | 0, // MTHLIP_MM = 1962
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MTLO = 1963
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // MTLO64 = 1964
+ Feature_HasDSP | 0, // MTLO_DSP = 1965
+ Feature_InMicroMips | Feature_HasDSP | 0, // MTLO_DSP_MM = 1966
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MTLO_MM = 1967
+ Feature_HasCnMips | 0, // MTM0 = 1968
+ Feature_HasCnMips | 0, // MTM1 = 1969
+ Feature_HasCnMips | 0, // MTM2 = 1970
+ Feature_HasCnMips | 0, // MTP0 = 1971
+ Feature_HasCnMips | 0, // MTP1 = 1972
+ Feature_HasCnMips | 0, // MTP2 = 1973
+ Feature_HasStdEnc | Feature_HasMT | Feature_NotInMicroMips | 0, // MTTR = 1974
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // MUH = 1975
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // MUHU = 1976
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MUHU_MMR6 = 1977
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MUH_MMR6 = 1978
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MUL = 1979
+ Feature_HasDSP | 0, // MULEQ_S_W_PHL = 1980
+ Feature_InMicroMips | Feature_HasDSP | 0, // MULEQ_S_W_PHL_MM = 1981
+ Feature_HasDSP | 0, // MULEQ_S_W_PHR = 1982
+ Feature_InMicroMips | Feature_HasDSP | 0, // MULEQ_S_W_PHR_MM = 1983
+ Feature_HasDSP | 0, // MULEU_S_PH_QBL = 1984
+ Feature_InMicroMips | Feature_HasDSP | 0, // MULEU_S_PH_QBL_MM = 1985
+ Feature_HasDSP | 0, // MULEU_S_PH_QBR = 1986
+ Feature_InMicroMips | Feature_HasDSP | 0, // MULEU_S_PH_QBR_MM = 1987
+ Feature_HasDSP | 0, // MULQ_RS_PH = 1988
+ Feature_InMicroMips | Feature_HasDSP | 0, // MULQ_RS_PH_MM = 1989
+ Feature_HasDSPR2 | 0, // MULQ_RS_W = 1990
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // MULQ_RS_W_MMR2 = 1991
+ Feature_HasDSPR2 | 0, // MULQ_S_PH = 1992
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // MULQ_S_PH_MMR2 = 1993
+ Feature_HasDSPR2 | 0, // MULQ_S_W = 1994
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // MULQ_S_W_MMR2 = 1995
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MULR_Q_H = 1996
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MULR_Q_W = 1997
+ Feature_HasDSP | 0, // MULSAQ_S_W_PH = 1998
+ Feature_InMicroMips | Feature_HasDSP | 0, // MULSAQ_S_W_PH_MM = 1999
+ Feature_HasDSPR2 | 0, // MULSA_W_PH = 2000
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // MULSA_W_PH_MMR2 = 2001
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MULT = 2002
+ Feature_HasDSP | 0, // MULTU_DSP = 2003
+ Feature_InMicroMips | Feature_HasDSP | 0, // MULTU_DSP_MM = 2004
+ Feature_HasDSP | 0, // MULT_DSP = 2005
+ Feature_InMicroMips | Feature_HasDSP | 0, // MULT_DSP_MM = 2006
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MULT_MM = 2007
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // MULTu = 2008
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MULTu_MM = 2009
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // MULU = 2010
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MULU_MMR6 = 2011
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MULV_B = 2012
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MULV_D = 2013
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MULV_H = 2014
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MULV_W = 2015
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // MUL_MM = 2016
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // MUL_MMR6 = 2017
+ Feature_HasDSPR2 | 0, // MUL_PH = 2018
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // MUL_PH_MMR2 = 2019
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MUL_Q_H = 2020
+ Feature_HasStdEnc | Feature_HasMSA | 0, // MUL_Q_W = 2021
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // MUL_R6 = 2022
+ Feature_HasDSPR2 | 0, // MUL_S_PH = 2023
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // MUL_S_PH_MMR2 = 2024
+ Feature_InMips16Mode | 0, // Mfhi16 = 2025
+ Feature_InMips16Mode | 0, // Mflo16 = 2026
+ Feature_InMips16Mode | 0, // Move32R16 = 2027
+ Feature_InMips16Mode | 0, // MoveR3216 = 2028
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NLOC_B = 2029
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NLOC_D = 2030
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NLOC_H = 2031
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NLOC_W = 2032
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NLZC_B = 2033
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NLZC_D = 2034
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NLZC_H = 2035
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NLZC_W = 2036
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | Feature_NotInMicroMips | 0, // NMADD_D32 = 2037
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | 0, // NMADD_D32_MM = 2038
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | Feature_NotInMicroMips | 0, // NMADD_D64 = 2039
+ Feature_HasStdEnc | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | Feature_NotInMicroMips | 0, // NMADD_S = 2040
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | 0, // NMADD_S_MM = 2041
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | Feature_NotInMicroMips | 0, // NMSUB_D32 = 2042
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | 0, // NMSUB_D32_MM = 2043
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | Feature_NotInMicroMips | 0, // NMSUB_D64 = 2044
+ Feature_HasStdEnc | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | Feature_NotInMicroMips | 0, // NMSUB_S = 2045
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | Feature_HasMadd4 | 0, // NMSUB_S_MM = 2046
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // NOR = 2047
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // NOR64 = 2048
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NORI_B = 2049
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // NOR_MM = 2050
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // NOR_MMR6 = 2051
+ Feature_HasStdEnc | Feature_HasMSA | 0, // NOR_V = 2052
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // NOT16_MM = 2053
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // NOT16_MMR6 = 2054
+ Feature_InMips16Mode | 0, // NegRxRy16 = 2055
+ Feature_InMips16Mode | 0, // NotRxRy16 = 2056
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // OR = 2057
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // OR16_MM = 2058
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // OR16_MMR6 = 2059
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // OR64 = 2060
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ORI_B = 2061
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // ORI_MMR6 = 2062
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // OR_MM = 2063
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // OR_MMR6 = 2064
+ Feature_HasStdEnc | Feature_HasMSA | 0, // OR_V = 2065
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // ORi = 2066
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // ORi64 = 2067
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // ORi_MM = 2068
+ Feature_InMips16Mode | 0, // OrRxRxRy16 = 2069
+ Feature_HasDSP | 0, // PACKRL_PH = 2070
+ Feature_InMicroMips | Feature_HasDSP | 0, // PACKRL_PH_MM = 2071
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // PAUSE = 2072
+ Feature_InMicroMips | 0, // PAUSE_MM = 2073
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // PAUSE_MMR6 = 2074
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCKEV_B = 2075
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCKEV_D = 2076
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCKEV_H = 2077
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCKEV_W = 2078
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCKOD_B = 2079
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCKOD_D = 2080
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCKOD_H = 2081
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCKOD_W = 2082
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCNT_B = 2083
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCNT_D = 2084
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCNT_H = 2085
+ Feature_HasStdEnc | Feature_HasMSA | 0, // PCNT_W = 2086
+ Feature_HasDSP | 0, // PICK_PH = 2087
+ Feature_InMicroMips | Feature_HasDSP | 0, // PICK_PH_MM = 2088
+ Feature_HasDSP | 0, // PICK_QB = 2089
+ Feature_InMicroMips | Feature_HasDSP | 0, // PICK_QB_MM = 2090
+ Feature_HasCnMips | 0, // POP = 2091
+ Feature_HasDSP | 0, // PRECEQU_PH_QBL = 2092
+ Feature_HasDSP | 0, // PRECEQU_PH_QBLA = 2093
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEQU_PH_QBLA_MM = 2094
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEQU_PH_QBL_MM = 2095
+ Feature_HasDSP | 0, // PRECEQU_PH_QBR = 2096
+ Feature_HasDSP | 0, // PRECEQU_PH_QBRA = 2097
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEQU_PH_QBRA_MM = 2098
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEQU_PH_QBR_MM = 2099
+ Feature_HasDSP | 0, // PRECEQ_W_PHL = 2100
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEQ_W_PHL_MM = 2101
+ Feature_HasDSP | 0, // PRECEQ_W_PHR = 2102
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEQ_W_PHR_MM = 2103
+ Feature_HasDSP | 0, // PRECEU_PH_QBL = 2104
+ Feature_HasDSP | 0, // PRECEU_PH_QBLA = 2105
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEU_PH_QBLA_MM = 2106
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEU_PH_QBL_MM = 2107
+ Feature_HasDSP | 0, // PRECEU_PH_QBR = 2108
+ Feature_HasDSP | 0, // PRECEU_PH_QBRA = 2109
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEU_PH_QBRA_MM = 2110
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECEU_PH_QBR_MM = 2111
+ Feature_HasDSP | 0, // PRECRQU_S_QB_PH = 2112
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECRQU_S_QB_PH_MM = 2113
+ Feature_HasDSP | 0, // PRECRQ_PH_W = 2114
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECRQ_PH_W_MM = 2115
+ Feature_HasDSP | 0, // PRECRQ_QB_PH = 2116
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECRQ_QB_PH_MM = 2117
+ Feature_HasDSP | 0, // PRECRQ_RS_PH_W = 2118
+ Feature_InMicroMips | Feature_HasDSP | 0, // PRECRQ_RS_PH_W_MM = 2119
+ Feature_HasDSPR2 | 0, // PRECR_QB_PH = 2120
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // PRECR_QB_PH_MMR2 = 2121
+ Feature_HasDSPR2 | 0, // PRECR_SRA_PH_W = 2122
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // PRECR_SRA_PH_W_MMR2 = 2123
+ Feature_HasDSPR2 | 0, // PRECR_SRA_R_PH_W = 2124
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // PRECR_SRA_R_PH_W_MMR2 = 2125
+ Feature_HasStdEnc | Feature_HasMips3_32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // PREF = 2126
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // PREFE = 2127
+ Feature_InMicroMips | Feature_HasEVA | 0, // PREFE_MM = 2128
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // PREFX_MM = 2129
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // PREF_MM = 2130
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // PREF_MMR6 = 2131
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // PREF_R6 = 2132
+ Feature_HasDSPR2 | 0, // PREPEND = 2133
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // PREPEND_MMR2 = 2134
+ Feature_HasDSP | 0, // RADDU_W_QB = 2135
+ Feature_InMicroMips | Feature_HasDSP | 0, // RADDU_W_QB_MM = 2136
+ Feature_HasDSP | 0, // RDDSP = 2137
+ Feature_InMicroMips | Feature_HasDSP | 0, // RDDSP_MM = 2138
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // RDHWR = 2139
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // RDHWR64 = 2140
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // RDHWR_MM = 2141
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // RDHWR_MMR6 = 2142
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // RDPGPR_MMR6 = 2143
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RECIP_D32 = 2144
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // RECIP_D32_MM = 2145
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RECIP_D64 = 2146
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // RECIP_D64_MM = 2147
+ Feature_HasStdEnc | Feature_HasMips4_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RECIP_S = 2148
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // RECIP_S_MM = 2149
+ Feature_HasDSP | 0, // REPLV_PH = 2150
+ Feature_InMicroMips | Feature_HasDSP | 0, // REPLV_PH_MM = 2151
+ Feature_HasDSP | 0, // REPLV_QB = 2152
+ Feature_InMicroMips | Feature_HasDSP | 0, // REPLV_QB_MM = 2153
+ Feature_HasDSP | 0, // REPL_PH = 2154
+ Feature_InMicroMips | Feature_HasDSP | 0, // REPL_PH_MM = 2155
+ Feature_HasDSP | 0, // REPL_QB = 2156
+ Feature_InMicroMips | Feature_HasDSP | 0, // REPL_QB_MM = 2157
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RINT_D = 2158
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // RINT_D_MMR6 = 2159
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RINT_S = 2160
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // RINT_S_MMR6 = 2161
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // ROTR = 2162
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // ROTRV = 2163
+ Feature_InMicroMips | 0, // ROTRV_MM = 2164
+ Feature_InMicroMips | 0, // ROTR_MM = 2165
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips3_32 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // ROUND_L_D64 = 2166
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // ROUND_L_D_MMR6 = 2167
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // ROUND_L_S = 2168
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // ROUND_L_S_MMR6 = 2169
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // ROUND_W_D32 = 2170
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // ROUND_W_D64 = 2171
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // ROUND_W_D_MMR6 = 2172
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // ROUND_W_MM = 2173
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // ROUND_W_S = 2174
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // ROUND_W_S_MM = 2175
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // ROUND_W_S_MMR6 = 2176
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RSQRT_D32 = 2177
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // RSQRT_D32_MM = 2178
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RSQRT_D64 = 2179
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_IsNotSoftFloat | 0, // RSQRT_D64_MM = 2180
+ Feature_HasStdEnc | Feature_HasMips4_32r2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // RSQRT_S = 2181
+ Feature_NotInMips16Mode | Feature_IsNotSoftFloat | 0, // RSQRT_S_MM = 2182
+ Feature_InMips16Mode | 0, // Restore16 = 2183
+ Feature_InMips16Mode | 0, // RestoreX16 = 2184
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SAT_S_B = 2185
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SAT_S_D = 2186
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SAT_S_H = 2187
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SAT_S_W = 2188
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SAT_U_B = 2189
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SAT_U_D = 2190
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SAT_U_H = 2191
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SAT_U_W = 2192
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SB = 2193
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SB16_MM = 2194
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SB16_MMR6 = 2195
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SB64 = 2196
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // SBE = 2197
+ Feature_InMicroMips | Feature_HasEVA | 0, // SBE_MM = 2198
+ Feature_InMicroMips | 0, // SB_MM = 2199
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SB_MMR6 = 2200
+ Feature_HasStdEnc | Feature_IsPTR32bit | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SC = 2201
+ Feature_HasStdEnc | Feature_IsPTR64bit | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SC64 = 2202
+ Feature_HasStdEnc | Feature_IsPTR64bit | Feature_HasMips64r6 | Feature_NotInMicroMips | 0, // SC64_R6 = 2203
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // SCD = 2204
+ Feature_HasStdEnc | Feature_HasMips32r6 | 0, // SCD_R6 = 2205
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // SCE = 2206
+ Feature_InMicroMips | Feature_HasEVA | 0, // SCE_MM = 2207
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SC_MM = 2208
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SC_MMR6 = 2209
+ Feature_HasStdEnc | Feature_IsPTR32bit | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // SC_R6 = 2210
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotInMicroMips | 0, // SD = 2211
+ Feature_HasStdEnc | Feature_HasMips32 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SDBBP = 2212
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SDBBP16_MM = 2213
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SDBBP16_MMR6 = 2214
+ Feature_InMicroMips | 0, // SDBBP_MM = 2215
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SDBBP_MMR6 = 2216
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // SDBBP_R6 = 2217
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SDC1 = 2218
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SDC164 = 2219
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // SDC1_D64_MMR6 = 2220
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // SDC1_MM = 2221
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SDC2 = 2222
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SDC2_MMR6 = 2223
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // SDC2_R6 = 2224
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotCnMips | Feature_NotInMicroMips | 0, // SDC3 = 2225
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SDIV = 2226
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SDIV_MM = 2227
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // SDL = 2228
+ Feature_HasStdEnc | Feature_HasMips3 | Feature_NotMips32r6 | Feature_NotMips64r6 | 0, // SDR = 2229
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SDXC1 = 2230
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | 0, // SDXC164 = 2231
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // SEB = 2232
+ Feature_HasStdEnc | Feature_HasMips32r2 | 0, // SEB64 = 2233
+ Feature_InMicroMips | 0, // SEB_MM = 2234
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // SEH = 2235
+ Feature_HasStdEnc | Feature_HasMips32r2 | 0, // SEH64 = 2236
+ Feature_InMicroMips | 0, // SEH_MM = 2237
+ Feature_HasStdEnc | Feature_IsGP32bit | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // SELEQZ = 2238
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips32r6 | 0, // SELEQZ64 = 2239
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SELEQZ_D = 2240
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SELEQZ_D_MMR6 = 2241
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SELEQZ_MMR6 = 2242
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SELEQZ_S = 2243
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SELEQZ_S_MMR6 = 2244
+ Feature_HasStdEnc | Feature_IsGP32bit | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // SELNEZ = 2245
+ Feature_HasStdEnc | Feature_IsGP64bit | Feature_HasMips32r6 | 0, // SELNEZ64 = 2246
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SELNEZ_D = 2247
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SELNEZ_D_MMR6 = 2248
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SELNEZ_MMR6 = 2249
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SELNEZ_S = 2250
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SELNEZ_S_MMR6 = 2251
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SEL_D = 2252
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SEL_D_MMR6 = 2253
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SEL_S = 2254
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SEL_S_MMR6 = 2255
+ Feature_HasCnMips | 0, // SEQ = 2256
+ Feature_HasCnMips | 0, // SEQi = 2257
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SH = 2258
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SH16_MM = 2259
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SH16_MMR6 = 2260
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SH64 = 2261
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // SHE = 2262
+ Feature_InMicroMips | Feature_HasEVA | 0, // SHE_MM = 2263
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SHF_B = 2264
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SHF_H = 2265
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SHF_W = 2266
+ Feature_HasDSP | 0, // SHILO = 2267
+ Feature_HasDSP | 0, // SHILOV = 2268
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHILOV_MM = 2269
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHILO_MM = 2270
+ Feature_HasDSP | 0, // SHLLV_PH = 2271
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHLLV_PH_MM = 2272
+ Feature_HasDSP | 0, // SHLLV_QB = 2273
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHLLV_QB_MM = 2274
+ Feature_HasDSP | 0, // SHLLV_S_PH = 2275
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHLLV_S_PH_MM = 2276
+ Feature_HasDSP | 0, // SHLLV_S_W = 2277
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHLLV_S_W_MM = 2278
+ Feature_HasDSP | 0, // SHLL_PH = 2279
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHLL_PH_MM = 2280
+ Feature_HasDSP | 0, // SHLL_QB = 2281
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHLL_QB_MM = 2282
+ Feature_HasDSP | 0, // SHLL_S_PH = 2283
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHLL_S_PH_MM = 2284
+ Feature_HasDSP | 0, // SHLL_S_W = 2285
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHLL_S_W_MM = 2286
+ Feature_HasDSP | 0, // SHRAV_PH = 2287
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHRAV_PH_MM = 2288
+ Feature_HasDSPR2 | 0, // SHRAV_QB = 2289
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SHRAV_QB_MMR2 = 2290
+ Feature_HasDSP | 0, // SHRAV_R_PH = 2291
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHRAV_R_PH_MM = 2292
+ Feature_HasDSPR2 | 0, // SHRAV_R_QB = 2293
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SHRAV_R_QB_MMR2 = 2294
+ Feature_HasDSP | 0, // SHRAV_R_W = 2295
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHRAV_R_W_MM = 2296
+ Feature_HasDSP | 0, // SHRA_PH = 2297
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHRA_PH_MM = 2298
+ Feature_HasDSPR2 | 0, // SHRA_QB = 2299
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SHRA_QB_MMR2 = 2300
+ Feature_HasDSP | 0, // SHRA_R_PH = 2301
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHRA_R_PH_MM = 2302
+ Feature_HasDSPR2 | 0, // SHRA_R_QB = 2303
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SHRA_R_QB_MMR2 = 2304
+ Feature_HasDSP | 0, // SHRA_R_W = 2305
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHRA_R_W_MM = 2306
+ Feature_HasDSPR2 | 0, // SHRLV_PH = 2307
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SHRLV_PH_MMR2 = 2308
+ Feature_HasDSP | 0, // SHRLV_QB = 2309
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHRLV_QB_MM = 2310
+ Feature_HasDSPR2 | 0, // SHRL_PH = 2311
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SHRL_PH_MMR2 = 2312
+ Feature_HasDSP | 0, // SHRL_QB = 2313
+ Feature_InMicroMips | Feature_HasDSP | 0, // SHRL_QB_MM = 2314
+ Feature_InMicroMips | 0, // SH_MM = 2315
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SH_MMR6 = 2316
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLDI_B = 2317
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLDI_D = 2318
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLDI_H = 2319
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLDI_W = 2320
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLD_B = 2321
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLD_D = 2322
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLD_H = 2323
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLD_W = 2324
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SLL = 2325
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SLL16_MM = 2326
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SLL16_MMR6 = 2327
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SLL64_32 = 2328
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SLL64_64 = 2329
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLLI_B = 2330
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLLI_D = 2331
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLLI_H = 2332
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLLI_W = 2333
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SLLV = 2334
+ Feature_InMicroMips | 0, // SLLV_MM = 2335
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLL_B = 2336
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLL_D = 2337
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLL_H = 2338
+ Feature_InMicroMips | 0, // SLL_MM = 2339
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SLL_MMR6 = 2340
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SLL_W = 2341
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SLT = 2342
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SLT64 = 2343
+ Feature_InMicroMips | 0, // SLT_MM = 2344
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SLTi = 2345
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SLTi64 = 2346
+ Feature_InMicroMips | 0, // SLTi_MM = 2347
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SLTiu = 2348
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SLTiu64 = 2349
+ Feature_InMicroMips | 0, // SLTiu_MM = 2350
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SLTu = 2351
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SLTu64 = 2352
+ Feature_InMicroMips | 0, // SLTu_MM = 2353
+ Feature_HasCnMips | 0, // SNE = 2354
+ Feature_HasCnMips | 0, // SNEi = 2355
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SPLATI_B = 2356
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SPLATI_D = 2357
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SPLATI_H = 2358
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SPLATI_W = 2359
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SPLAT_B = 2360
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SPLAT_D = 2361
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SPLAT_H = 2362
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SPLAT_W = 2363
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SRA = 2364
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRAI_B = 2365
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRAI_D = 2366
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRAI_H = 2367
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRAI_W = 2368
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRARI_B = 2369
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRARI_D = 2370
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRARI_H = 2371
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRARI_W = 2372
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRAR_B = 2373
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRAR_D = 2374
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRAR_H = 2375
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRAR_W = 2376
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SRAV = 2377
+ Feature_InMicroMips | 0, // SRAV_MM = 2378
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRA_B = 2379
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRA_D = 2380
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRA_H = 2381
+ Feature_InMicroMips | 0, // SRA_MM = 2382
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRA_W = 2383
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SRL = 2384
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SRL16_MM = 2385
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SRL16_MMR6 = 2386
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLI_B = 2387
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLI_D = 2388
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLI_H = 2389
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLI_W = 2390
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLRI_B = 2391
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLRI_D = 2392
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLRI_H = 2393
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLRI_W = 2394
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLR_B = 2395
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLR_D = 2396
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLR_H = 2397
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRLR_W = 2398
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SRLV = 2399
+ Feature_InMicroMips | 0, // SRLV_MM = 2400
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRL_B = 2401
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRL_D = 2402
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRL_H = 2403
+ Feature_InMicroMips | 0, // SRL_MM = 2404
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SRL_W = 2405
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SSNOP = 2406
+ Feature_InMicroMips | 0, // SSNOP_MM = 2407
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SSNOP_MMR6 = 2408
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ST_B = 2409
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ST_D = 2410
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ST_H = 2411
+ Feature_HasStdEnc | Feature_HasMSA | 0, // ST_W = 2412
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SUB = 2413
+ Feature_HasDSPR2 | 0, // SUBQH_PH = 2414
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SUBQH_PH_MMR2 = 2415
+ Feature_HasDSPR2 | 0, // SUBQH_R_PH = 2416
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SUBQH_R_PH_MMR2 = 2417
+ Feature_HasDSPR2 | 0, // SUBQH_R_W = 2418
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SUBQH_R_W_MMR2 = 2419
+ Feature_HasDSPR2 | 0, // SUBQH_W = 2420
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SUBQH_W_MMR2 = 2421
+ Feature_HasDSP | 0, // SUBQ_PH = 2422
+ Feature_InMicroMips | Feature_HasDSP | 0, // SUBQ_PH_MM = 2423
+ Feature_HasDSP | 0, // SUBQ_S_PH = 2424
+ Feature_InMicroMips | Feature_HasDSP | 0, // SUBQ_S_PH_MM = 2425
+ Feature_HasDSP | 0, // SUBQ_S_W = 2426
+ Feature_InMicroMips | Feature_HasDSP | 0, // SUBQ_S_W_MM = 2427
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBSUS_U_B = 2428
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBSUS_U_D = 2429
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBSUS_U_H = 2430
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBSUS_U_W = 2431
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBSUU_S_B = 2432
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBSUU_S_D = 2433
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBSUU_S_H = 2434
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBSUU_S_W = 2435
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBS_S_B = 2436
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBS_S_D = 2437
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBS_S_H = 2438
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBS_S_W = 2439
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBS_U_B = 2440
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBS_U_D = 2441
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBS_U_H = 2442
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBS_U_W = 2443
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SUBU16_MM = 2444
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SUBU16_MMR6 = 2445
+ Feature_HasDSPR2 | 0, // SUBUH_QB = 2446
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SUBUH_QB_MMR2 = 2447
+ Feature_HasDSPR2 | 0, // SUBUH_R_QB = 2448
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SUBUH_R_QB_MMR2 = 2449
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SUBU_MMR6 = 2450
+ Feature_HasDSPR2 | 0, // SUBU_PH = 2451
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SUBU_PH_MMR2 = 2452
+ Feature_HasDSP | 0, // SUBU_QB = 2453
+ Feature_InMicroMips | Feature_HasDSP | 0, // SUBU_QB_MM = 2454
+ Feature_HasDSPR2 | 0, // SUBU_S_PH = 2455
+ Feature_InMicroMips | Feature_HasDSPR2 | 0, // SUBU_S_PH_MMR2 = 2456
+ Feature_HasDSP | 0, // SUBU_S_QB = 2457
+ Feature_InMicroMips | Feature_HasDSP | 0, // SUBU_S_QB_MM = 2458
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBVI_B = 2459
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBVI_D = 2460
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBVI_H = 2461
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBVI_W = 2462
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBV_B = 2463
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBV_D = 2464
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBV_H = 2465
+ Feature_HasStdEnc | Feature_HasMSA | 0, // SUBV_W = 2466
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SUB_MM = 2467
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SUB_MMR6 = 2468
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SUBu = 2469
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SUBu_MM = 2470
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips5_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SUXC1 = 2471
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips5_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SUXC164 = 2472
+ Feature_InMicroMips | Feature_IsFP64bit | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // SUXC1_MM = 2473
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SW = 2474
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SW16_MM = 2475
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SW16_MMR6 = 2476
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SW64 = 2477
+ Feature_HasStdEnc | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // SWC1 = 2478
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // SWC1_MM = 2479
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SWC2 = 2480
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SWC2_MMR6 = 2481
+ Feature_HasStdEnc | Feature_HasMips32r6 | Feature_NotInMicroMips | 0, // SWC2_R6 = 2482
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotCnMips | Feature_NotInMicroMips | 0, // SWC3 = 2483
+ Feature_NotInMips16Mode | Feature_HasDSP | 0, // SWDSP = 2484
+ Feature_InMicroMips | Feature_HasDSP | 0, // SWDSP_MM = 2485
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // SWE = 2486
+ Feature_InMicroMips | Feature_HasEVA | 0, // SWE_MM = 2487
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SWL = 2488
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SWL64 = 2489
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_HasEVA | Feature_NotInMicroMips | 0, // SWLE = 2490
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_HasEVA | 0, // SWLE_MM = 2491
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SWL_MM = 2492
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SWM16_MM = 2493
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SWM16_MMR6 = 2494
+ Feature_InMicroMips | 0, // SWM32_MM = 2495
+ Feature_InMicroMips | 0, // SWP_MM = 2496
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // SWR = 2497
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // SWR64 = 2498
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_HasEVA | Feature_NotInMicroMips | 0, // SWRE = 2499
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_HasEVA | 0, // SWRE_MM = 2500
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SWR_MM = 2501
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SWSP_MM = 2502
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SWSP_MMR6 = 2503
+ Feature_HasStdEnc | Feature_HasMips4_32r2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_IsNotSoftFloat | 0, // SWXC1 = 2504
+ Feature_InMicroMips | Feature_NotMips32r6 | Feature_IsNotSoftFloat | 0, // SWXC1_MM = 2505
+ Feature_InMicroMips | 0, // SW_MM = 2506
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SW_MMR6 = 2507
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // SYNC = 2508
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // SYNCI = 2509
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // SYNCI_MM = 2510
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SYNCI_MMR6 = 2511
+ Feature_InMicroMips | 0, // SYNC_MM = 2512
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // SYNC_MMR6 = 2513
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // SYSCALL = 2514
+ Feature_InMicroMips | 0, // SYSCALL_MM = 2515
+ Feature_InMips16Mode | 0, // Save16 = 2516
+ Feature_InMips16Mode | 0, // SaveX16 = 2517
+ Feature_InMips16Mode | 0, // SbRxRyOffMemX16 = 2518
+ Feature_InMips16Mode | 0, // SebRx16 = 2519
+ Feature_InMips16Mode | 0, // SehRx16 = 2520
+ Feature_InMips16Mode | 0, // ShRxRyOffMemX16 = 2521
+ Feature_InMips16Mode | 0, // SllX16 = 2522
+ Feature_InMips16Mode | 0, // SllvRxRy16 = 2523
+ Feature_InMips16Mode | 0, // SltRxRy16 = 2524
+ Feature_InMips16Mode | 0, // SltiRxImm16 = 2525
+ Feature_InMips16Mode | 0, // SltiRxImmX16 = 2526
+ Feature_InMips16Mode | 0, // SltiuRxImm16 = 2527
+ Feature_InMips16Mode | 0, // SltiuRxImmX16 = 2528
+ Feature_InMips16Mode | 0, // SltuRxRy16 = 2529
+ Feature_InMips16Mode | 0, // SraX16 = 2530
+ Feature_InMips16Mode | 0, // SravRxRy16 = 2531
+ Feature_InMips16Mode | 0, // SrlX16 = 2532
+ Feature_InMips16Mode | 0, // SrlvRxRy16 = 2533
+ Feature_InMips16Mode | 0, // SubuRxRyRz16 = 2534
+ Feature_InMips16Mode | 0, // SwRxRyOffMemX16 = 2535
+ Feature_InMips16Mode | 0, // SwRxSpImmX16 = 2536
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // TEQ = 2537
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // TEQI = 2538
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // TEQI_MM = 2539
+ Feature_InMicroMips | 0, // TEQ_MM = 2540
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // TGE = 2541
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // TGEI = 2542
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // TGEIU = 2543
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // TGEIU_MM = 2544
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // TGEI_MM = 2545
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // TGEU = 2546
+ Feature_InMicroMips | 0, // TGEU_MM = 2547
+ Feature_InMicroMips | 0, // TGE_MM = 2548
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // TLBGINV = 2549
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // TLBGINVF = 2550
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // TLBGINVF_MM = 2551
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // TLBGINV_MM = 2552
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // TLBGP = 2553
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // TLBGP_MM = 2554
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // TLBGR = 2555
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // TLBGR_MM = 2556
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // TLBGWI = 2557
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // TLBGWI_MM = 2558
+ Feature_HasStdEnc | Feature_HasMips32r5 | Feature_HasVirt | Feature_NotInMicroMips | 0, // TLBGWR = 2559
+ Feature_InMicroMips | Feature_HasMips32r5 | Feature_HasVirt | 0, // TLBGWR_MM = 2560
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // TLBINV = 2561
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_HasEVA | Feature_NotInMicroMips | 0, // TLBINVF = 2562
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // TLBINVF_MMR6 = 2563
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // TLBINV_MMR6 = 2564
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // TLBP = 2565
+ Feature_InMicroMips | 0, // TLBP_MM = 2566
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // TLBR = 2567
+ Feature_InMicroMips | 0, // TLBR_MM = 2568
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // TLBWI = 2569
+ Feature_InMicroMips | 0, // TLBWI_MM = 2570
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // TLBWR = 2571
+ Feature_InMicroMips | 0, // TLBWR_MM = 2572
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // TLT = 2573
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // TLTI = 2574
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // TLTIU_MM = 2575
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // TLTI_MM = 2576
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // TLTU = 2577
+ Feature_InMicroMips | 0, // TLTU_MM = 2578
+ Feature_InMicroMips | 0, // TLT_MM = 2579
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotInMicroMips | 0, // TNE = 2580
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // TNEI = 2581
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // TNEI_MM = 2582
+ Feature_InMicroMips | 0, // TNE_MM = 2583
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips3_32 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // TRUNC_L_D64 = 2584
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // TRUNC_L_D_MMR6 = 2585
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // TRUNC_L_S = 2586
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // TRUNC_L_S_MMR6 = 2587
+ Feature_HasStdEnc | Feature_NotFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // TRUNC_W_D32 = 2588
+ Feature_HasStdEnc | Feature_IsFP64bit | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // TRUNC_W_D64 = 2589
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // TRUNC_W_D_MMR6 = 2590
+ Feature_InMicroMips | Feature_NotFP64bit | Feature_IsNotSoftFloat | 0, // TRUNC_W_MM = 2591
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_IsNotSoftFloat | Feature_NotInMicroMips | 0, // TRUNC_W_S = 2592
+ Feature_InMicroMips | Feature_IsNotSoftFloat | 0, // TRUNC_W_S_MM = 2593
+ Feature_InMicroMips | Feature_HasMips32r6 | Feature_IsNotSoftFloat | 0, // TRUNC_W_S_MMR6 = 2594
+ Feature_HasStdEnc | Feature_HasMips2 | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // TTLTIU = 2595
+ Feature_HasStdEnc | Feature_NotMips32r6 | Feature_NotMips64r6 | Feature_NotInMicroMips | 0, // UDIV = 2596
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // UDIV_MM = 2597
+ Feature_HasCnMips | 0, // V3MULU = 2598
+ Feature_HasCnMips | 0, // VMM0 = 2599
+ Feature_HasCnMips | 0, // VMULU = 2600
+ Feature_HasStdEnc | Feature_HasMSA | 0, // VSHF_B = 2601
+ Feature_HasStdEnc | Feature_HasMSA | 0, // VSHF_D = 2602
+ Feature_HasStdEnc | Feature_HasMSA | 0, // VSHF_H = 2603
+ Feature_HasStdEnc | Feature_HasMSA | 0, // VSHF_W = 2604
+ Feature_HasStdEnc | Feature_HasMips3_32 | Feature_NotInMicroMips | 0, // WAIT = 2605
+ Feature_InMicroMips | 0, // WAIT_MM = 2606
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // WAIT_MMR6 = 2607
+ Feature_HasDSP | Feature_NotInMicroMips | 0, // WRDSP = 2608
+ Feature_InMicroMips | Feature_HasDSP | 0, // WRDSP_MM = 2609
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // WRPGPR_MMR6 = 2610
+ Feature_HasStdEnc | Feature_HasMips32r2 | Feature_NotInMicroMips | 0, // WSBH = 2611
+ Feature_InMicroMips | 0, // WSBH_MM = 2612
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // WSBH_MMR6 = 2613
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // XOR = 2614
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // XOR16_MM = 2615
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // XOR16_MMR6 = 2616
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // XOR64 = 2617
+ Feature_HasStdEnc | Feature_HasMSA | 0, // XORI_B = 2618
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // XORI_MMR6 = 2619
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // XOR_MM = 2620
+ Feature_InMicroMips | Feature_HasMips32r6 | 0, // XOR_MMR6 = 2621
+ Feature_HasStdEnc | Feature_HasMSA | 0, // XOR_V = 2622
+ Feature_HasStdEnc | Feature_NotInMicroMips | 0, // XORi = 2623
+ Feature_NotInMips16Mode | Feature_IsGP64bit | 0, // XORi64 = 2624
+ Feature_InMicroMips | Feature_NotMips32r6 | 0, // XORi_MM = 2625
+ Feature_InMips16Mode | 0, // XorRxRxRy16 = 2626
+ Feature_HasStdEnc | Feature_HasMT | Feature_NotInMicroMips | 0, // YIELD = 2627
+ };
+
+ assert(Inst.getOpcode() < 2628);
+ uint64_t MissingFeatures =
+ (AvailableFeatures & RequiredFeatures[Inst.getOpcode()]) ^
+ RequiredFeatures[Inst.getOpcode()];
+ if (MissingFeatures) {
+ std::ostringstream Msg;
+ Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
+ << " instruction but the ";
+ for (unsigned i = 0; i < 8 * sizeof(MissingFeatures); ++i)
+ if (MissingFeatures & (1ULL << i))
+ Msg << SubtargetFeatureNames[i] << " ";
+ Msg << "predicate(s) are not met";
+ report_fatal_error(Msg.str());
+ }
+#else
+// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF).
+(void)MCII;
+#endif // NDEBUG
+}
+#endif
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenMCPseudoLowering.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenMCPseudoLowering.inc
new file mode 100644
index 0000000..b223d5e
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenMCPseudoLowering.inc
@@ -0,0 +1,1001 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Pseudo-instruction MC lowering Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+bool MipsAsmPrinter::
+emitPseudoExpansionLowering(MCStreamer &OutStreamer,
+ const MachineInstr *MI) {
+ switch (MI->getOpcode()) {
+ default: return false;
+ case Mips::AND_V_D_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::AND_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::AND_V_H_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::AND_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::AND_V_W_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::AND_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::B: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BEQ);
+ // Operand: rs
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: rt
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: offset
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::BAL_BR: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BGEZAL);
+ // Operand: rs
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: offset
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::BAL_BR_MM: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BGEZAL_MM);
+ // Operand: rs
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: offset
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::BSEL_D_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BSEL_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wd_in
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(3), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::BSEL_FD_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BSEL_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wd_in
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(3), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::BSEL_FW_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BSEL_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wd_in
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(3), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::BSEL_H_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BSEL_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wd_in
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(3), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::BSEL_W_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BSEL_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wd_in
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(3), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::B_MM: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BEQ_MM);
+ // Operand: rs
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: rt
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: offset
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::FABS_D: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::FMAX_A_D);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::FABS_W: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::FMAX_A_W);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::JALR64Pseudo: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JALR);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::RA));
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::JALRHB64Pseudo: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JALR_HB64);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::RA_64));
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::JALRHBPseudo: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JALR_HB);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::RA));
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::JALRPseudo: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JALR);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::RA));
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::NOP: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::SLL);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: rt
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: shamt
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::NOR_V_D_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::NOR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::NOR_V_H_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::NOR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::NOR_V_W_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::NOR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::OR_V_D_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::OR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::OR_V_H_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::OR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::OR_V_W_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::OR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoCMPU_EQ_QB: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::CMPU_EQ_QB);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoCMPU_LE_QB: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::CMPU_LE_QB);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoCMPU_LT_QB: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::CMPU_LT_QB);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoCMP_EQ_PH: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::CMP_EQ_PH);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoCMP_LE_PH: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::CMP_LE_PH);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoCMP_LT_PH: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::CMP_LT_PH);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoDMULT: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::DMULT);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoDMULTu: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::DMULTu);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoDSDIV: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::DSDIV);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoDUDIV: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::DUDIV);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndirectBranch: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndirectBranch64: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR64);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndirectBranch64R6: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JALR64);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64));
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndirectBranchR6: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JALR);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndirectBranch_MM: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_MM);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndirectBranch_MMR6: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JRC16_MMR6);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndirectHazardBranch: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_HB);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndirectHazardBranch64: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_HB64);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndrectHazardBranch64R6: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_HB64_R6);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoIndrectHazardBranchR6: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_HB_R6);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoMADD: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::MADD);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoMADDU: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::MADDU);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoMSUB: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::MSUB);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoMSUBU: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::MSUBU);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoMULT: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::MULT);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoMULTu: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::MULTu);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoPICK_PH: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::PICK_PH);
+ // Operand: rd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rs
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(3), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoPICK_QB: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::PICK_QB);
+ // Operand: rd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rs
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(3), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoSDIV: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::SDIV);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::PseudoUDIV: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::UDIV);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::SDIV_MM_Pseudo: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::SDIV_MM);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALL: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::J);
+ // Operand: target
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALL64R6REG: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JALR64);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64));
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLHB64R6REG: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_HB64_R6);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLHBR6REG: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_HB_R6);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLR6REG: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JALR);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLREG: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLREG64: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR64);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLREGHB: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_HB);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLREGHB64: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JR_HB64);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLREG_MM: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JRC16_MM);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALLREG_MMR6: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::JRC16_MM);
+ // Operand: rs
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALL_MM: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::J_MM);
+ // Operand: target
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TAILCALL_MMR6: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BC_MMR6);
+ // Operand: offset
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TRAP: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BREAK);
+ // Operand: code_1
+ TmpInst.addOperand(MCOperand::createImm(0));
+ // Operand: code_2
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::TRAP_MM: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::BREAK_MM);
+ // Operand: code_1
+ TmpInst.addOperand(MCOperand::createImm(0));
+ // Operand: code_2
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::UDIV_MM_Pseudo: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::UDIV_MM);
+ // Operand: rs
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: rt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::XOR_V_D_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::XOR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::XOR_V_H_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::XOR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case Mips::XOR_V_W_PSEUDO: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(Mips::XOR_V);
+ // Operand: wd
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: ws
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: wt
+ lowerOperand(MI->getOperand(2), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ }
+ return true;
+}
+
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenRegisterBank.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenRegisterBank.inc
new file mode 100644
index 0000000..a3b30ba
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenRegisterBank.inc
@@ -0,0 +1,78 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Register Bank Source Fragments *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_REGBANK_DECLARATIONS
+#undef GET_REGBANK_DECLARATIONS
+namespace llvm {
+namespace Mips {
+enum {
+ GPRBRegBankID,
+ NumRegisterBanks,
+};
+} // end namespace Mips
+} // end namespace llvm
+#endif // GET_REGBANK_DECLARATIONS
+
+#ifdef GET_TARGET_REGBANK_CLASS
+#undef GET_TARGET_REGBANK_CLASS
+private:
+ static RegisterBank *RegBanks[];
+
+protected:
+ MipsGenRegisterBankInfo();
+
+#endif // GET_TARGET_REGBANK_CLASS
+
+#ifdef GET_TARGET_REGBANK_IMPL
+#undef GET_TARGET_REGBANK_IMPL
+namespace llvm {
+namespace Mips {
+const uint32_t GPRBRegBankCoverageData[] = {
+ // 0-31
+ (1u << (Mips::GPR32RegClassID - 0)) |
+ (1u << (Mips::GPR32NONZERORegClassID - 0)) |
+ (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
+ (1u << (Mips::CPU16RegsRegClassID - 0)) |
+ (1u << (Mips::GPRMM16RegClassID - 0)) |
+ (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
+ (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
+ (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
+ (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
+ (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
+ (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
+ 0,
+ // 32-63
+ (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 32)) |
+ (1u << (Mips::CPUSPRegRegClassID - 32)) |
+ (1u << (Mips::SP32RegClassID - 32)) |
+ (1u << (Mips::CPURARegRegClassID - 32)) |
+ (1u << (Mips::GP32RegClassID - 32)) |
+ (1u << (Mips::GPR32ZERORegClassID - 32)) |
+ 0,
+ // 64-95
+ 0,
+};
+
+RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 73);
+} // end namespace Mips
+
+RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
+ &Mips::GPRBRegBank,
+};
+
+MipsGenRegisterBankInfo::MipsGenRegisterBankInfo()
+ : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks) {
+ // Assert that RegBank indices match their ID's
+#ifndef NDEBUG
+ unsigned Index = 0;
+ for (const auto &RB : RegBanks)
+ assert(Index++ == RB->getID() && "Index != ID");
+#endif // NDEBUG
+}
+} // end namespace llvm
+#endif // GET_TARGET_REGBANK_IMPL
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenRegisterInfo.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenRegisterInfo.inc
new file mode 100644
index 0000000..e5d8e36
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenRegisterInfo.inc
@@ -0,0 +1,7418 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Register Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+namespace llvm {
+
+class MCRegisterClass;
+extern const MCRegisterClass MipsMCRegisterClasses[];
+
+namespace Mips {
+enum {
+ NoRegister,
+ AT = 1,
+ DSPCCond = 2,
+ DSPCarry = 3,
+ DSPEFI = 4,
+ DSPOutFlag = 5,
+ DSPPos = 6,
+ DSPSCount = 7,
+ FP = 8,
+ GP = 9,
+ MSAAccess = 10,
+ MSACSR = 11,
+ MSAIR = 12,
+ MSAMap = 13,
+ MSAModify = 14,
+ MSARequest = 15,
+ MSASave = 16,
+ MSAUnmap = 17,
+ PC = 18,
+ RA = 19,
+ SP = 20,
+ ZERO = 21,
+ A0 = 22,
+ A1 = 23,
+ A2 = 24,
+ A3 = 25,
+ AC0 = 26,
+ AC1 = 27,
+ AC2 = 28,
+ AC3 = 29,
+ AT_64 = 30,
+ COP00 = 31,
+ COP01 = 32,
+ COP02 = 33,
+ COP03 = 34,
+ COP04 = 35,
+ COP05 = 36,
+ COP06 = 37,
+ COP07 = 38,
+ COP08 = 39,
+ COP09 = 40,
+ COP20 = 41,
+ COP21 = 42,
+ COP22 = 43,
+ COP23 = 44,
+ COP24 = 45,
+ COP25 = 46,
+ COP26 = 47,
+ COP27 = 48,
+ COP28 = 49,
+ COP29 = 50,
+ COP30 = 51,
+ COP31 = 52,
+ COP32 = 53,
+ COP33 = 54,
+ COP34 = 55,
+ COP35 = 56,
+ COP36 = 57,
+ COP37 = 58,
+ COP38 = 59,
+ COP39 = 60,
+ COP010 = 61,
+ COP011 = 62,
+ COP012 = 63,
+ COP013 = 64,
+ COP014 = 65,
+ COP015 = 66,
+ COP016 = 67,
+ COP017 = 68,
+ COP018 = 69,
+ COP019 = 70,
+ COP020 = 71,
+ COP021 = 72,
+ COP022 = 73,
+ COP023 = 74,
+ COP024 = 75,
+ COP025 = 76,
+ COP026 = 77,
+ COP027 = 78,
+ COP028 = 79,
+ COP029 = 80,
+ COP030 = 81,
+ COP031 = 82,
+ COP210 = 83,
+ COP211 = 84,
+ COP212 = 85,
+ COP213 = 86,
+ COP214 = 87,
+ COP215 = 88,
+ COP216 = 89,
+ COP217 = 90,
+ COP218 = 91,
+ COP219 = 92,
+ COP220 = 93,
+ COP221 = 94,
+ COP222 = 95,
+ COP223 = 96,
+ COP224 = 97,
+ COP225 = 98,
+ COP226 = 99,
+ COP227 = 100,
+ COP228 = 101,
+ COP229 = 102,
+ COP230 = 103,
+ COP231 = 104,
+ COP310 = 105,
+ COP311 = 106,
+ COP312 = 107,
+ COP313 = 108,
+ COP314 = 109,
+ COP315 = 110,
+ COP316 = 111,
+ COP317 = 112,
+ COP318 = 113,
+ COP319 = 114,
+ COP320 = 115,
+ COP321 = 116,
+ COP322 = 117,
+ COP323 = 118,
+ COP324 = 119,
+ COP325 = 120,
+ COP326 = 121,
+ COP327 = 122,
+ COP328 = 123,
+ COP329 = 124,
+ COP330 = 125,
+ COP331 = 126,
+ D0 = 127,
+ D1 = 128,
+ D2 = 129,
+ D3 = 130,
+ D4 = 131,
+ D5 = 132,
+ D6 = 133,
+ D7 = 134,
+ D8 = 135,
+ D9 = 136,
+ D10 = 137,
+ D11 = 138,
+ D12 = 139,
+ D13 = 140,
+ D14 = 141,
+ D15 = 142,
+ DSPOutFlag20 = 143,
+ DSPOutFlag21 = 144,
+ DSPOutFlag22 = 145,
+ DSPOutFlag23 = 146,
+ F0 = 147,
+ F1 = 148,
+ F2 = 149,
+ F3 = 150,
+ F4 = 151,
+ F5 = 152,
+ F6 = 153,
+ F7 = 154,
+ F8 = 155,
+ F9 = 156,
+ F10 = 157,
+ F11 = 158,
+ F12 = 159,
+ F13 = 160,
+ F14 = 161,
+ F15 = 162,
+ F16 = 163,
+ F17 = 164,
+ F18 = 165,
+ F19 = 166,
+ F20 = 167,
+ F21 = 168,
+ F22 = 169,
+ F23 = 170,
+ F24 = 171,
+ F25 = 172,
+ F26 = 173,
+ F27 = 174,
+ F28 = 175,
+ F29 = 176,
+ F30 = 177,
+ F31 = 178,
+ FCC0 = 179,
+ FCC1 = 180,
+ FCC2 = 181,
+ FCC3 = 182,
+ FCC4 = 183,
+ FCC5 = 184,
+ FCC6 = 185,
+ FCC7 = 186,
+ FCR0 = 187,
+ FCR1 = 188,
+ FCR2 = 189,
+ FCR3 = 190,
+ FCR4 = 191,
+ FCR5 = 192,
+ FCR6 = 193,
+ FCR7 = 194,
+ FCR8 = 195,
+ FCR9 = 196,
+ FCR10 = 197,
+ FCR11 = 198,
+ FCR12 = 199,
+ FCR13 = 200,
+ FCR14 = 201,
+ FCR15 = 202,
+ FCR16 = 203,
+ FCR17 = 204,
+ FCR18 = 205,
+ FCR19 = 206,
+ FCR20 = 207,
+ FCR21 = 208,
+ FCR22 = 209,
+ FCR23 = 210,
+ FCR24 = 211,
+ FCR25 = 212,
+ FCR26 = 213,
+ FCR27 = 214,
+ FCR28 = 215,
+ FCR29 = 216,
+ FCR30 = 217,
+ FCR31 = 218,
+ FP_64 = 219,
+ F_HI0 = 220,
+ F_HI1 = 221,
+ F_HI2 = 222,
+ F_HI3 = 223,
+ F_HI4 = 224,
+ F_HI5 = 225,
+ F_HI6 = 226,
+ F_HI7 = 227,
+ F_HI8 = 228,
+ F_HI9 = 229,
+ F_HI10 = 230,
+ F_HI11 = 231,
+ F_HI12 = 232,
+ F_HI13 = 233,
+ F_HI14 = 234,
+ F_HI15 = 235,
+ F_HI16 = 236,
+ F_HI17 = 237,
+ F_HI18 = 238,
+ F_HI19 = 239,
+ F_HI20 = 240,
+ F_HI21 = 241,
+ F_HI22 = 242,
+ F_HI23 = 243,
+ F_HI24 = 244,
+ F_HI25 = 245,
+ F_HI26 = 246,
+ F_HI27 = 247,
+ F_HI28 = 248,
+ F_HI29 = 249,
+ F_HI30 = 250,
+ F_HI31 = 251,
+ GP_64 = 252,
+ HI0 = 253,
+ HI1 = 254,
+ HI2 = 255,
+ HI3 = 256,
+ HWR0 = 257,
+ HWR1 = 258,
+ HWR2 = 259,
+ HWR3 = 260,
+ HWR4 = 261,
+ HWR5 = 262,
+ HWR6 = 263,
+ HWR7 = 264,
+ HWR8 = 265,
+ HWR9 = 266,
+ HWR10 = 267,
+ HWR11 = 268,
+ HWR12 = 269,
+ HWR13 = 270,
+ HWR14 = 271,
+ HWR15 = 272,
+ HWR16 = 273,
+ HWR17 = 274,
+ HWR18 = 275,
+ HWR19 = 276,
+ HWR20 = 277,
+ HWR21 = 278,
+ HWR22 = 279,
+ HWR23 = 280,
+ HWR24 = 281,
+ HWR25 = 282,
+ HWR26 = 283,
+ HWR27 = 284,
+ HWR28 = 285,
+ HWR29 = 286,
+ HWR30 = 287,
+ HWR31 = 288,
+ K0 = 289,
+ K1 = 290,
+ LO0 = 291,
+ LO1 = 292,
+ LO2 = 293,
+ LO3 = 294,
+ MPL0 = 295,
+ MPL1 = 296,
+ MPL2 = 297,
+ P0 = 298,
+ P1 = 299,
+ P2 = 300,
+ RA_64 = 301,
+ S0 = 302,
+ S1 = 303,
+ S2 = 304,
+ S3 = 305,
+ S4 = 306,
+ S5 = 307,
+ S6 = 308,
+ S7 = 309,
+ SP_64 = 310,
+ T0 = 311,
+ T1 = 312,
+ T2 = 313,
+ T3 = 314,
+ T4 = 315,
+ T5 = 316,
+ T6 = 317,
+ T7 = 318,
+ T8 = 319,
+ T9 = 320,
+ V0 = 321,
+ V1 = 322,
+ W0 = 323,
+ W1 = 324,
+ W2 = 325,
+ W3 = 326,
+ W4 = 327,
+ W5 = 328,
+ W6 = 329,
+ W7 = 330,
+ W8 = 331,
+ W9 = 332,
+ W10 = 333,
+ W11 = 334,
+ W12 = 335,
+ W13 = 336,
+ W14 = 337,
+ W15 = 338,
+ W16 = 339,
+ W17 = 340,
+ W18 = 341,
+ W19 = 342,
+ W20 = 343,
+ W21 = 344,
+ W22 = 345,
+ W23 = 346,
+ W24 = 347,
+ W25 = 348,
+ W26 = 349,
+ W27 = 350,
+ W28 = 351,
+ W29 = 352,
+ W30 = 353,
+ W31 = 354,
+ ZERO_64 = 355,
+ A0_64 = 356,
+ A1_64 = 357,
+ A2_64 = 358,
+ A3_64 = 359,
+ AC0_64 = 360,
+ D0_64 = 361,
+ D1_64 = 362,
+ D2_64 = 363,
+ D3_64 = 364,
+ D4_64 = 365,
+ D5_64 = 366,
+ D6_64 = 367,
+ D7_64 = 368,
+ D8_64 = 369,
+ D9_64 = 370,
+ D10_64 = 371,
+ D11_64 = 372,
+ D12_64 = 373,
+ D13_64 = 374,
+ D14_64 = 375,
+ D15_64 = 376,
+ D16_64 = 377,
+ D17_64 = 378,
+ D18_64 = 379,
+ D19_64 = 380,
+ D20_64 = 381,
+ D21_64 = 382,
+ D22_64 = 383,
+ D23_64 = 384,
+ D24_64 = 385,
+ D25_64 = 386,
+ D26_64 = 387,
+ D27_64 = 388,
+ D28_64 = 389,
+ D29_64 = 390,
+ D30_64 = 391,
+ D31_64 = 392,
+ DSPOutFlag16_19 = 393,
+ HI0_64 = 394,
+ K0_64 = 395,
+ K1_64 = 396,
+ LO0_64 = 397,
+ S0_64 = 398,
+ S1_64 = 399,
+ S2_64 = 400,
+ S3_64 = 401,
+ S4_64 = 402,
+ S5_64 = 403,
+ S6_64 = 404,
+ S7_64 = 405,
+ T0_64 = 406,
+ T1_64 = 407,
+ T2_64 = 408,
+ T3_64 = 409,
+ T4_64 = 410,
+ T5_64 = 411,
+ T6_64 = 412,
+ T7_64 = 413,
+ T8_64 = 414,
+ T9_64 = 415,
+ V0_64 = 416,
+ V1_64 = 417,
+ NUM_TARGET_REGS // 418
+};
+} // end namespace Mips
+
+// Register classes
+
+namespace Mips {
+enum {
+ MSA128F16RegClassID = 0,
+ MSA128F16_with_sub_64_in_OddSPRegClassID = 1,
+ OddSPRegClassID = 2,
+ CCRRegClassID = 3,
+ COP0RegClassID = 4,
+ COP2RegClassID = 5,
+ COP3RegClassID = 6,
+ DSPRRegClassID = 7,
+ FGR32RegClassID = 8,
+ FGRCCRegClassID = 9,
+ FGRH32RegClassID = 10,
+ GPR32RegClassID = 11,
+ HWRegsRegClassID = 12,
+ GPR32NONZERORegClassID = 13,
+ OddSP_with_sub_hiRegClassID = 14,
+ FGR32_and_OddSPRegClassID = 15,
+ FGRH32_and_OddSPRegClassID = 16,
+ OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 17,
+ CPU16RegsPlusSPRegClassID = 18,
+ CPU16RegsRegClassID = 19,
+ FCCRegClassID = 20,
+ GPRMM16RegClassID = 21,
+ GPRMM16MovePRegClassID = 22,
+ GPRMM16ZeroRegClassID = 23,
+ MSACtrlRegClassID = 24,
+ OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 25,
+ CPU16Regs_and_GPRMM16ZeroRegClassID = 26,
+ GPR32NONZERO_and_GPRMM16MovePRegClassID = 27,
+ CPU16Regs_and_GPRMM16MovePRegClassID = 28,
+ GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 29,
+ HI32DSPRegClassID = 30,
+ LO32DSPRegClassID = 31,
+ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 32,
+ CPURARegRegClassID = 33,
+ CPUSPRegRegClassID = 34,
+ DSPCCRegClassID = 35,
+ GP32RegClassID = 36,
+ GPR32ZERORegClassID = 37,
+ HI32RegClassID = 38,
+ LO32RegClassID = 39,
+ SP32RegClassID = 40,
+ FGR64RegClassID = 41,
+ GPR64RegClassID = 42,
+ GPR64_with_sub_32_in_GPR32NONZERORegClassID = 43,
+ AFGR64RegClassID = 44,
+ FGR64_and_OddSPRegClassID = 45,
+ GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 46,
+ AFGR64_and_OddSPRegClassID = 47,
+ GPR64_with_sub_32_in_CPU16RegsRegClassID = 48,
+ GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 49,
+ GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 50,
+ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 51,
+ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 52,
+ ACC64DSPRegClassID = 53,
+ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 54,
+ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 55,
+ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 56,
+ OCTEON_MPLRegClassID = 57,
+ OCTEON_PRegClassID = 58,
+ ACC64RegClassID = 59,
+ GP64RegClassID = 60,
+ GPR64_with_sub_32_in_CPURARegRegClassID = 61,
+ GPR64_with_sub_32_in_GPR32ZERORegClassID = 62,
+ HI64RegClassID = 63,
+ LO64RegClassID = 64,
+ SP64RegClassID = 65,
+ MSA128BRegClassID = 66,
+ MSA128DRegClassID = 67,
+ MSA128HRegClassID = 68,
+ MSA128WRegClassID = 69,
+ MSA128B_with_sub_64_in_OddSPRegClassID = 70,
+ MSA128WEvensRegClassID = 71,
+ ACC128RegClassID = 72,
+
+ };
+} // end namespace Mips
+
+
+// Subregister indices
+
+namespace Mips {
+enum {
+ NoSubRegister,
+ sub_32, // 1
+ sub_64, // 2
+ sub_dsp16_19, // 3
+ sub_dsp20, // 4
+ sub_dsp21, // 5
+ sub_dsp22, // 6
+ sub_dsp23, // 7
+ sub_hi, // 8
+ sub_lo, // 9
+ sub_hi_then_sub_32, // 10
+ sub_32_sub_hi_then_sub_32, // 11
+ NUM_TARGET_SUBREGS
+};
+} // end namespace Mips
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* MC Register Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+namespace llvm {
+
+extern const MCPhysReg MipsRegDiffLists[] = {
+ /* 0 */ 0, 0,
+ /* 2 */ 4, 1, 1, 1, 1, 0,
+ /* 8 */ 388, 65286, 1, 1, 1, 0,
+ /* 14 */ 20, 1, 0,
+ /* 17 */ 21, 1, 0,
+ /* 20 */ 22, 1, 0,
+ /* 23 */ 23, 1, 0,
+ /* 26 */ 24, 1, 0,
+ /* 29 */ 25, 1, 0,
+ /* 32 */ 26, 1, 0,
+ /* 35 */ 27, 1, 0,
+ /* 38 */ 28, 1, 0,
+ /* 41 */ 29, 1, 0,
+ /* 44 */ 30, 1, 0,
+ /* 47 */ 31, 1, 0,
+ /* 50 */ 32, 1, 0,
+ /* 53 */ 33, 1, 0,
+ /* 56 */ 34, 1, 0,
+ /* 59 */ 35, 1, 0,
+ /* 62 */ 65415, 1, 0,
+ /* 65 */ 65513, 1, 0,
+ /* 68 */ 3, 0,
+ /* 70 */ 4, 0,
+ /* 72 */ 6, 0,
+ /* 74 */ 11, 0,
+ /* 76 */ 12, 0,
+ /* 78 */ 22, 0,
+ /* 80 */ 23, 0,
+ /* 82 */ 29, 0,
+ /* 84 */ 30, 0,
+ /* 86 */ 65308, 72, 0,
+ /* 89 */ 65346, 72, 0,
+ /* 92 */ 38, 65322, 73, 0,
+ /* 96 */ 95, 0,
+ /* 98 */ 96, 0,
+ /* 100 */ 106, 0,
+ /* 102 */ 211, 0,
+ /* 104 */ 243, 0,
+ /* 106 */ 282, 0,
+ /* 108 */ 290, 0,
+ /* 110 */ 334, 0,
+ /* 112 */ 64983, 0,
+ /* 114 */ 65060, 0,
+ /* 116 */ 65148, 0,
+ /* 118 */ 65202, 0,
+ /* 120 */ 65205, 0,
+ /* 122 */ 65246, 0,
+ /* 124 */ 65254, 0,
+ /* 126 */ 65271, 0,
+ /* 128 */ 65293, 0,
+ /* 130 */ 37, 65430, 103, 65395, 65309, 0,
+ /* 136 */ 65325, 0,
+ /* 138 */ 65395, 0,
+ /* 140 */ 65396, 0,
+ /* 142 */ 65397, 0,
+ /* 144 */ 65398, 0,
+ /* 146 */ 65410, 0,
+ /* 148 */ 65415, 0,
+ /* 150 */ 65430, 0,
+ /* 152 */ 65440, 0,
+ /* 154 */ 65441, 0,
+ /* 156 */ 141, 65498, 0,
+ /* 159 */ 65516, 234, 65498, 0,
+ /* 163 */ 65515, 235, 65498, 0,
+ /* 167 */ 65514, 236, 65498, 0,
+ /* 171 */ 65513, 237, 65498, 0,
+ /* 175 */ 65512, 238, 65498, 0,
+ /* 179 */ 65511, 239, 65498, 0,
+ /* 183 */ 65510, 240, 65498, 0,
+ /* 187 */ 65509, 241, 65498, 0,
+ /* 191 */ 65508, 242, 65498, 0,
+ /* 195 */ 65507, 243, 65498, 0,
+ /* 199 */ 65506, 244, 65498, 0,
+ /* 203 */ 65505, 245, 65498, 0,
+ /* 207 */ 65504, 246, 65498, 0,
+ /* 211 */ 65503, 247, 65498, 0,
+ /* 215 */ 65502, 248, 65498, 0,
+ /* 219 */ 65501, 249, 65498, 0,
+ /* 223 */ 65500, 250, 65498, 0,
+ /* 227 */ 265, 65498, 0,
+ /* 230 */ 65271, 371, 65499, 0,
+ /* 234 */ 65309, 368, 65502, 0,
+ /* 238 */ 65507, 0,
+ /* 240 */ 65510, 0,
+ /* 242 */ 65511, 0,
+ /* 244 */ 65512, 0,
+ /* 246 */ 65516, 0,
+ /* 248 */ 65521, 0,
+ /* 250 */ 65522, 0,
+ /* 252 */ 65535, 0,
+};
+
+extern const LaneBitmask MipsLaneMaskLists[] = {
+ /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
+ /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(),
+ /* 4 */ LaneBitmask(0x00000002), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(),
+ /* 10 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(),
+};
+
+extern const uint16_t MipsSubRegIdxLists[] = {
+ /* 0 */ 1, 0,
+ /* 2 */ 3, 4, 5, 6, 7, 0,
+ /* 8 */ 2, 9, 8, 0,
+ /* 12 */ 9, 1, 8, 10, 11, 0,
+};
+
+extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
+ { 65535, 65535 },
+ { 0, 32 }, // sub_32
+ { 0, 64 }, // sub_64
+ { 16, 4 }, // sub_dsp16_19
+ { 20, 1 }, // sub_dsp20
+ { 21, 1 }, // sub_dsp21
+ { 22, 1 }, // sub_dsp22
+ { 23, 1 }, // sub_dsp23
+ { 32, 32 }, // sub_hi
+ { 0, 32 }, // sub_lo
+ { 32, 32 }, // sub_hi_then_sub_32
+ { 0, 64 }, // sub_32_sub_hi_then_sub_32
+};
+
+extern const char MipsRegStrings[] = {
+ /* 0 */ 'C', 'O', 'P', '0', '0', 0,
+ /* 6 */ 'C', 'O', 'P', '0', '1', '0', 0,
+ /* 13 */ 'C', 'O', 'P', '2', '1', '0', 0,
+ /* 20 */ 'C', 'O', 'P', '3', '1', '0', 0,
+ /* 27 */ 'D', '1', '0', 0,
+ /* 31 */ 'F', '1', '0', 0,
+ /* 35 */ 'F', '_', 'H', 'I', '1', '0', 0,
+ /* 42 */ 'F', 'C', 'R', '1', '0', 0,
+ /* 48 */ 'H', 'W', 'R', '1', '0', 0,
+ /* 54 */ 'W', '1', '0', 0,
+ /* 58 */ 'C', 'O', 'P', '0', '2', '0', 0,
+ /* 65 */ 'C', 'O', 'P', '2', '2', '0', 0,
+ /* 72 */ 'C', 'O', 'P', '3', '2', '0', 0,
+ /* 79 */ 'F', '2', '0', 0,
+ /* 83 */ 'F', '_', 'H', 'I', '2', '0', 0,
+ /* 90 */ 'C', 'O', 'P', '2', '0', 0,
+ /* 96 */ 'F', 'C', 'R', '2', '0', 0,
+ /* 102 */ 'H', 'W', 'R', '2', '0', 0,
+ /* 108 */ 'W', '2', '0', 0,
+ /* 112 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0,
+ /* 125 */ 'C', 'O', 'P', '0', '3', '0', 0,
+ /* 132 */ 'C', 'O', 'P', '2', '3', '0', 0,
+ /* 139 */ 'C', 'O', 'P', '3', '3', '0', 0,
+ /* 146 */ 'F', '3', '0', 0,
+ /* 150 */ 'F', '_', 'H', 'I', '3', '0', 0,
+ /* 157 */ 'C', 'O', 'P', '3', '0', 0,
+ /* 163 */ 'F', 'C', 'R', '3', '0', 0,
+ /* 169 */ 'H', 'W', 'R', '3', '0', 0,
+ /* 175 */ 'W', '3', '0', 0,
+ /* 179 */ 'A', '0', 0,
+ /* 182 */ 'A', 'C', '0', 0,
+ /* 186 */ 'F', 'C', 'C', '0', 0,
+ /* 191 */ 'D', '0', 0,
+ /* 194 */ 'F', '0', 0,
+ /* 197 */ 'F', '_', 'H', 'I', '0', 0,
+ /* 203 */ 'K', '0', 0,
+ /* 206 */ 'M', 'P', 'L', '0', 0,
+ /* 211 */ 'L', 'O', '0', 0,
+ /* 215 */ 'P', '0', 0,
+ /* 218 */ 'F', 'C', 'R', '0', 0,
+ /* 223 */ 'H', 'W', 'R', '0', 0,
+ /* 228 */ 'S', '0', 0,
+ /* 231 */ 'T', '0', 0,
+ /* 234 */ 'V', '0', 0,
+ /* 237 */ 'W', '0', 0,
+ /* 240 */ 'C', 'O', 'P', '0', '1', 0,
+ /* 246 */ 'C', 'O', 'P', '0', '1', '1', 0,
+ /* 253 */ 'C', 'O', 'P', '2', '1', '1', 0,
+ /* 260 */ 'C', 'O', 'P', '3', '1', '1', 0,
+ /* 267 */ 'D', '1', '1', 0,
+ /* 271 */ 'F', '1', '1', 0,
+ /* 275 */ 'F', '_', 'H', 'I', '1', '1', 0,
+ /* 282 */ 'F', 'C', 'R', '1', '1', 0,
+ /* 288 */ 'H', 'W', 'R', '1', '1', 0,
+ /* 294 */ 'W', '1', '1', 0,
+ /* 298 */ 'C', 'O', 'P', '0', '2', '1', 0,
+ /* 305 */ 'C', 'O', 'P', '2', '2', '1', 0,
+ /* 312 */ 'C', 'O', 'P', '3', '2', '1', 0,
+ /* 319 */ 'F', '2', '1', 0,
+ /* 323 */ 'F', '_', 'H', 'I', '2', '1', 0,
+ /* 330 */ 'C', 'O', 'P', '2', '1', 0,
+ /* 336 */ 'F', 'C', 'R', '2', '1', 0,
+ /* 342 */ 'H', 'W', 'R', '2', '1', 0,
+ /* 348 */ 'W', '2', '1', 0,
+ /* 352 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0,
+ /* 365 */ 'C', 'O', 'P', '0', '3', '1', 0,
+ /* 372 */ 'C', 'O', 'P', '2', '3', '1', 0,
+ /* 379 */ 'C', 'O', 'P', '3', '3', '1', 0,
+ /* 386 */ 'F', '3', '1', 0,
+ /* 390 */ 'F', '_', 'H', 'I', '3', '1', 0,
+ /* 397 */ 'C', 'O', 'P', '3', '1', 0,
+ /* 403 */ 'F', 'C', 'R', '3', '1', 0,
+ /* 409 */ 'H', 'W', 'R', '3', '1', 0,
+ /* 415 */ 'W', '3', '1', 0,
+ /* 419 */ 'A', '1', 0,
+ /* 422 */ 'A', 'C', '1', 0,
+ /* 426 */ 'F', 'C', 'C', '1', 0,
+ /* 431 */ 'D', '1', 0,
+ /* 434 */ 'F', '1', 0,
+ /* 437 */ 'F', '_', 'H', 'I', '1', 0,
+ /* 443 */ 'K', '1', 0,
+ /* 446 */ 'M', 'P', 'L', '1', 0,
+ /* 451 */ 'L', 'O', '1', 0,
+ /* 455 */ 'P', '1', 0,
+ /* 458 */ 'F', 'C', 'R', '1', 0,
+ /* 463 */ 'H', 'W', 'R', '1', 0,
+ /* 468 */ 'S', '1', 0,
+ /* 471 */ 'T', '1', 0,
+ /* 474 */ 'V', '1', 0,
+ /* 477 */ 'W', '1', 0,
+ /* 480 */ 'C', 'O', 'P', '0', '2', 0,
+ /* 486 */ 'C', 'O', 'P', '0', '1', '2', 0,
+ /* 493 */ 'C', 'O', 'P', '2', '1', '2', 0,
+ /* 500 */ 'C', 'O', 'P', '3', '1', '2', 0,
+ /* 507 */ 'D', '1', '2', 0,
+ /* 511 */ 'F', '1', '2', 0,
+ /* 515 */ 'F', '_', 'H', 'I', '1', '2', 0,
+ /* 522 */ 'F', 'C', 'R', '1', '2', 0,
+ /* 528 */ 'H', 'W', 'R', '1', '2', 0,
+ /* 534 */ 'W', '1', '2', 0,
+ /* 538 */ 'C', 'O', 'P', '0', '2', '2', 0,
+ /* 545 */ 'C', 'O', 'P', '2', '2', '2', 0,
+ /* 552 */ 'C', 'O', 'P', '3', '2', '2', 0,
+ /* 559 */ 'F', '2', '2', 0,
+ /* 563 */ 'F', '_', 'H', 'I', '2', '2', 0,
+ /* 570 */ 'C', 'O', 'P', '2', '2', 0,
+ /* 576 */ 'F', 'C', 'R', '2', '2', 0,
+ /* 582 */ 'H', 'W', 'R', '2', '2', 0,
+ /* 588 */ 'W', '2', '2', 0,
+ /* 592 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0,
+ /* 605 */ 'C', 'O', 'P', '3', '2', 0,
+ /* 611 */ 'A', '2', 0,
+ /* 614 */ 'A', 'C', '2', 0,
+ /* 618 */ 'F', 'C', 'C', '2', 0,
+ /* 623 */ 'D', '2', 0,
+ /* 626 */ 'F', '2', 0,
+ /* 629 */ 'F', '_', 'H', 'I', '2', 0,
+ /* 635 */ 'M', 'P', 'L', '2', 0,
+ /* 640 */ 'L', 'O', '2', 0,
+ /* 644 */ 'P', '2', 0,
+ /* 647 */ 'F', 'C', 'R', '2', 0,
+ /* 652 */ 'H', 'W', 'R', '2', 0,
+ /* 657 */ 'S', '2', 0,
+ /* 660 */ 'T', '2', 0,
+ /* 663 */ 'W', '2', 0,
+ /* 666 */ 'C', 'O', 'P', '0', '3', 0,
+ /* 672 */ 'C', 'O', 'P', '0', '1', '3', 0,
+ /* 679 */ 'C', 'O', 'P', '2', '1', '3', 0,
+ /* 686 */ 'C', 'O', 'P', '3', '1', '3', 0,
+ /* 693 */ 'D', '1', '3', 0,
+ /* 697 */ 'F', '1', '3', 0,
+ /* 701 */ 'F', '_', 'H', 'I', '1', '3', 0,
+ /* 708 */ 'F', 'C', 'R', '1', '3', 0,
+ /* 714 */ 'H', 'W', 'R', '1', '3', 0,
+ /* 720 */ 'W', '1', '3', 0,
+ /* 724 */ 'C', 'O', 'P', '0', '2', '3', 0,
+ /* 731 */ 'C', 'O', 'P', '2', '2', '3', 0,
+ /* 738 */ 'C', 'O', 'P', '3', '2', '3', 0,
+ /* 745 */ 'F', '2', '3', 0,
+ /* 749 */ 'F', '_', 'H', 'I', '2', '3', 0,
+ /* 756 */ 'C', 'O', 'P', '2', '3', 0,
+ /* 762 */ 'F', 'C', 'R', '2', '3', 0,
+ /* 768 */ 'H', 'W', 'R', '2', '3', 0,
+ /* 774 */ 'W', '2', '3', 0,
+ /* 778 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0,
+ /* 791 */ 'C', 'O', 'P', '3', '3', 0,
+ /* 797 */ 'A', '3', 0,
+ /* 800 */ 'A', 'C', '3', 0,
+ /* 804 */ 'F', 'C', 'C', '3', 0,
+ /* 809 */ 'D', '3', 0,
+ /* 812 */ 'F', '3', 0,
+ /* 815 */ 'F', '_', 'H', 'I', '3', 0,
+ /* 821 */ 'L', 'O', '3', 0,
+ /* 825 */ 'F', 'C', 'R', '3', 0,
+ /* 830 */ 'H', 'W', 'R', '3', 0,
+ /* 835 */ 'S', '3', 0,
+ /* 838 */ 'T', '3', 0,
+ /* 841 */ 'W', '3', 0,
+ /* 844 */ 'C', 'O', 'P', '0', '4', 0,
+ /* 850 */ 'C', 'O', 'P', '0', '1', '4', 0,
+ /* 857 */ 'C', 'O', 'P', '2', '1', '4', 0,
+ /* 864 */ 'C', 'O', 'P', '3', '1', '4', 0,
+ /* 871 */ 'D', '1', '4', 0,
+ /* 875 */ 'F', '1', '4', 0,
+ /* 879 */ 'F', '_', 'H', 'I', '1', '4', 0,
+ /* 886 */ 'F', 'C', 'R', '1', '4', 0,
+ /* 892 */ 'H', 'W', 'R', '1', '4', 0,
+ /* 898 */ 'W', '1', '4', 0,
+ /* 902 */ 'C', 'O', 'P', '0', '2', '4', 0,
+ /* 909 */ 'C', 'O', 'P', '2', '2', '4', 0,
+ /* 916 */ 'C', 'O', 'P', '3', '2', '4', 0,
+ /* 923 */ 'F', '2', '4', 0,
+ /* 927 */ 'F', '_', 'H', 'I', '2', '4', 0,
+ /* 934 */ 'C', 'O', 'P', '2', '4', 0,
+ /* 940 */ 'F', 'C', 'R', '2', '4', 0,
+ /* 946 */ 'H', 'W', 'R', '2', '4', 0,
+ /* 952 */ 'W', '2', '4', 0,
+ /* 956 */ 'C', 'O', 'P', '3', '4', 0,
+ /* 962 */ 'D', '1', '0', '_', '6', '4', 0,
+ /* 969 */ 'D', '2', '0', '_', '6', '4', 0,
+ /* 976 */ 'D', '3', '0', '_', '6', '4', 0,
+ /* 983 */ 'A', '0', '_', '6', '4', 0,
+ /* 989 */ 'A', 'C', '0', '_', '6', '4', 0,
+ /* 996 */ 'D', '0', '_', '6', '4', 0,
+ /* 1002 */ 'H', 'I', '0', '_', '6', '4', 0,
+ /* 1009 */ 'K', '0', '_', '6', '4', 0,
+ /* 1015 */ 'L', 'O', '0', '_', '6', '4', 0,
+ /* 1022 */ 'S', '0', '_', '6', '4', 0,
+ /* 1028 */ 'T', '0', '_', '6', '4', 0,
+ /* 1034 */ 'V', '0', '_', '6', '4', 0,
+ /* 1040 */ 'D', '1', '1', '_', '6', '4', 0,
+ /* 1047 */ 'D', '2', '1', '_', '6', '4', 0,
+ /* 1054 */ 'D', '3', '1', '_', '6', '4', 0,
+ /* 1061 */ 'A', '1', '_', '6', '4', 0,
+ /* 1067 */ 'D', '1', '_', '6', '4', 0,
+ /* 1073 */ 'K', '1', '_', '6', '4', 0,
+ /* 1079 */ 'S', '1', '_', '6', '4', 0,
+ /* 1085 */ 'T', '1', '_', '6', '4', 0,
+ /* 1091 */ 'V', '1', '_', '6', '4', 0,
+ /* 1097 */ 'D', '1', '2', '_', '6', '4', 0,
+ /* 1104 */ 'D', '2', '2', '_', '6', '4', 0,
+ /* 1111 */ 'A', '2', '_', '6', '4', 0,
+ /* 1117 */ 'D', '2', '_', '6', '4', 0,
+ /* 1123 */ 'S', '2', '_', '6', '4', 0,
+ /* 1129 */ 'T', '2', '_', '6', '4', 0,
+ /* 1135 */ 'D', '1', '3', '_', '6', '4', 0,
+ /* 1142 */ 'D', '2', '3', '_', '6', '4', 0,
+ /* 1149 */ 'A', '3', '_', '6', '4', 0,
+ /* 1155 */ 'D', '3', '_', '6', '4', 0,
+ /* 1161 */ 'S', '3', '_', '6', '4', 0,
+ /* 1167 */ 'T', '3', '_', '6', '4', 0,
+ /* 1173 */ 'D', '1', '4', '_', '6', '4', 0,
+ /* 1180 */ 'D', '2', '4', '_', '6', '4', 0,
+ /* 1187 */ 'D', '4', '_', '6', '4', 0,
+ /* 1193 */ 'S', '4', '_', '6', '4', 0,
+ /* 1199 */ 'T', '4', '_', '6', '4', 0,
+ /* 1205 */ 'D', '1', '5', '_', '6', '4', 0,
+ /* 1212 */ 'D', '2', '5', '_', '6', '4', 0,
+ /* 1219 */ 'D', '5', '_', '6', '4', 0,
+ /* 1225 */ 'S', '5', '_', '6', '4', 0,
+ /* 1231 */ 'T', '5', '_', '6', '4', 0,
+ /* 1237 */ 'D', '1', '6', '_', '6', '4', 0,
+ /* 1244 */ 'D', '2', '6', '_', '6', '4', 0,
+ /* 1251 */ 'D', '6', '_', '6', '4', 0,
+ /* 1257 */ 'S', '6', '_', '6', '4', 0,
+ /* 1263 */ 'T', '6', '_', '6', '4', 0,
+ /* 1269 */ 'D', '1', '7', '_', '6', '4', 0,
+ /* 1276 */ 'D', '2', '7', '_', '6', '4', 0,
+ /* 1283 */ 'D', '7', '_', '6', '4', 0,
+ /* 1289 */ 'S', '7', '_', '6', '4', 0,
+ /* 1295 */ 'T', '7', '_', '6', '4', 0,
+ /* 1301 */ 'D', '1', '8', '_', '6', '4', 0,
+ /* 1308 */ 'D', '2', '8', '_', '6', '4', 0,
+ /* 1315 */ 'D', '8', '_', '6', '4', 0,
+ /* 1321 */ 'T', '8', '_', '6', '4', 0,
+ /* 1327 */ 'D', '1', '9', '_', '6', '4', 0,
+ /* 1334 */ 'D', '2', '9', '_', '6', '4', 0,
+ /* 1341 */ 'D', '9', '_', '6', '4', 0,
+ /* 1347 */ 'T', '9', '_', '6', '4', 0,
+ /* 1353 */ 'R', 'A', '_', '6', '4', 0,
+ /* 1359 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0,
+ /* 1367 */ 'F', 'P', '_', '6', '4', 0,
+ /* 1373 */ 'G', 'P', '_', '6', '4', 0,
+ /* 1379 */ 'S', 'P', '_', '6', '4', 0,
+ /* 1385 */ 'A', 'T', '_', '6', '4', 0,
+ /* 1391 */ 'F', 'C', 'C', '4', 0,
+ /* 1396 */ 'D', '4', 0,
+ /* 1399 */ 'F', '4', 0,
+ /* 1402 */ 'F', '_', 'H', 'I', '4', 0,
+ /* 1408 */ 'F', 'C', 'R', '4', 0,
+ /* 1413 */ 'H', 'W', 'R', '4', 0,
+ /* 1418 */ 'S', '4', 0,
+ /* 1421 */ 'T', '4', 0,
+ /* 1424 */ 'W', '4', 0,
+ /* 1427 */ 'C', 'O', 'P', '0', '5', 0,
+ /* 1433 */ 'C', 'O', 'P', '0', '1', '5', 0,
+ /* 1440 */ 'C', 'O', 'P', '2', '1', '5', 0,
+ /* 1447 */ 'C', 'O', 'P', '3', '1', '5', 0,
+ /* 1454 */ 'D', '1', '5', 0,
+ /* 1458 */ 'F', '1', '5', 0,
+ /* 1462 */ 'F', '_', 'H', 'I', '1', '5', 0,
+ /* 1469 */ 'F', 'C', 'R', '1', '5', 0,
+ /* 1475 */ 'H', 'W', 'R', '1', '5', 0,
+ /* 1481 */ 'W', '1', '5', 0,
+ /* 1485 */ 'C', 'O', 'P', '0', '2', '5', 0,
+ /* 1492 */ 'C', 'O', 'P', '2', '2', '5', 0,
+ /* 1499 */ 'C', 'O', 'P', '3', '2', '5', 0,
+ /* 1506 */ 'F', '2', '5', 0,
+ /* 1510 */ 'F', '_', 'H', 'I', '2', '5', 0,
+ /* 1517 */ 'C', 'O', 'P', '2', '5', 0,
+ /* 1523 */ 'F', 'C', 'R', '2', '5', 0,
+ /* 1529 */ 'H', 'W', 'R', '2', '5', 0,
+ /* 1535 */ 'W', '2', '5', 0,
+ /* 1539 */ 'C', 'O', 'P', '3', '5', 0,
+ /* 1545 */ 'F', 'C', 'C', '5', 0,
+ /* 1550 */ 'D', '5', 0,
+ /* 1553 */ 'F', '5', 0,
+ /* 1556 */ 'F', '_', 'H', 'I', '5', 0,
+ /* 1562 */ 'F', 'C', 'R', '5', 0,
+ /* 1567 */ 'H', 'W', 'R', '5', 0,
+ /* 1572 */ 'S', '5', 0,
+ /* 1575 */ 'T', '5', 0,
+ /* 1578 */ 'W', '5', 0,
+ /* 1581 */ 'C', 'O', 'P', '0', '6', 0,
+ /* 1587 */ 'C', 'O', 'P', '0', '1', '6', 0,
+ /* 1594 */ 'C', 'O', 'P', '2', '1', '6', 0,
+ /* 1601 */ 'C', 'O', 'P', '3', '1', '6', 0,
+ /* 1608 */ 'F', '1', '6', 0,
+ /* 1612 */ 'F', '_', 'H', 'I', '1', '6', 0,
+ /* 1619 */ 'F', 'C', 'R', '1', '6', 0,
+ /* 1625 */ 'H', 'W', 'R', '1', '6', 0,
+ /* 1631 */ 'W', '1', '6', 0,
+ /* 1635 */ 'C', 'O', 'P', '0', '2', '6', 0,
+ /* 1642 */ 'C', 'O', 'P', '2', '2', '6', 0,
+ /* 1649 */ 'C', 'O', 'P', '3', '2', '6', 0,
+ /* 1656 */ 'F', '2', '6', 0,
+ /* 1660 */ 'F', '_', 'H', 'I', '2', '6', 0,
+ /* 1667 */ 'C', 'O', 'P', '2', '6', 0,
+ /* 1673 */ 'F', 'C', 'R', '2', '6', 0,
+ /* 1679 */ 'H', 'W', 'R', '2', '6', 0,
+ /* 1685 */ 'W', '2', '6', 0,
+ /* 1689 */ 'C', 'O', 'P', '3', '6', 0,
+ /* 1695 */ 'F', 'C', 'C', '6', 0,
+ /* 1700 */ 'D', '6', 0,
+ /* 1703 */ 'F', '6', 0,
+ /* 1706 */ 'F', '_', 'H', 'I', '6', 0,
+ /* 1712 */ 'F', 'C', 'R', '6', 0,
+ /* 1717 */ 'H', 'W', 'R', '6', 0,
+ /* 1722 */ 'S', '6', 0,
+ /* 1725 */ 'T', '6', 0,
+ /* 1728 */ 'W', '6', 0,
+ /* 1731 */ 'C', 'O', 'P', '0', '7', 0,
+ /* 1737 */ 'C', 'O', 'P', '0', '1', '7', 0,
+ /* 1744 */ 'C', 'O', 'P', '2', '1', '7', 0,
+ /* 1751 */ 'C', 'O', 'P', '3', '1', '7', 0,
+ /* 1758 */ 'F', '1', '7', 0,
+ /* 1762 */ 'F', '_', 'H', 'I', '1', '7', 0,
+ /* 1769 */ 'F', 'C', 'R', '1', '7', 0,
+ /* 1775 */ 'H', 'W', 'R', '1', '7', 0,
+ /* 1781 */ 'W', '1', '7', 0,
+ /* 1785 */ 'C', 'O', 'P', '0', '2', '7', 0,
+ /* 1792 */ 'C', 'O', 'P', '2', '2', '7', 0,
+ /* 1799 */ 'C', 'O', 'P', '3', '2', '7', 0,
+ /* 1806 */ 'F', '2', '7', 0,
+ /* 1810 */ 'F', '_', 'H', 'I', '2', '7', 0,
+ /* 1817 */ 'C', 'O', 'P', '2', '7', 0,
+ /* 1823 */ 'F', 'C', 'R', '2', '7', 0,
+ /* 1829 */ 'H', 'W', 'R', '2', '7', 0,
+ /* 1835 */ 'W', '2', '7', 0,
+ /* 1839 */ 'C', 'O', 'P', '3', '7', 0,
+ /* 1845 */ 'F', 'C', 'C', '7', 0,
+ /* 1850 */ 'D', '7', 0,
+ /* 1853 */ 'F', '7', 0,
+ /* 1856 */ 'F', '_', 'H', 'I', '7', 0,
+ /* 1862 */ 'F', 'C', 'R', '7', 0,
+ /* 1867 */ 'H', 'W', 'R', '7', 0,
+ /* 1872 */ 'S', '7', 0,
+ /* 1875 */ 'T', '7', 0,
+ /* 1878 */ 'W', '7', 0,
+ /* 1881 */ 'C', 'O', 'P', '0', '8', 0,
+ /* 1887 */ 'C', 'O', 'P', '0', '1', '8', 0,
+ /* 1894 */ 'C', 'O', 'P', '2', '1', '8', 0,
+ /* 1901 */ 'C', 'O', 'P', '3', '1', '8', 0,
+ /* 1908 */ 'F', '1', '8', 0,
+ /* 1912 */ 'F', '_', 'H', 'I', '1', '8', 0,
+ /* 1919 */ 'F', 'C', 'R', '1', '8', 0,
+ /* 1925 */ 'H', 'W', 'R', '1', '8', 0,
+ /* 1931 */ 'W', '1', '8', 0,
+ /* 1935 */ 'C', 'O', 'P', '0', '2', '8', 0,
+ /* 1942 */ 'C', 'O', 'P', '2', '2', '8', 0,
+ /* 1949 */ 'C', 'O', 'P', '3', '2', '8', 0,
+ /* 1956 */ 'F', '2', '8', 0,
+ /* 1960 */ 'F', '_', 'H', 'I', '2', '8', 0,
+ /* 1967 */ 'C', 'O', 'P', '2', '8', 0,
+ /* 1973 */ 'F', 'C', 'R', '2', '8', 0,
+ /* 1979 */ 'H', 'W', 'R', '2', '8', 0,
+ /* 1985 */ 'W', '2', '8', 0,
+ /* 1989 */ 'C', 'O', 'P', '3', '8', 0,
+ /* 1995 */ 'D', '8', 0,
+ /* 1998 */ 'F', '8', 0,
+ /* 2001 */ 'F', '_', 'H', 'I', '8', 0,
+ /* 2007 */ 'F', 'C', 'R', '8', 0,
+ /* 2012 */ 'H', 'W', 'R', '8', 0,
+ /* 2017 */ 'T', '8', 0,
+ /* 2020 */ 'W', '8', 0,
+ /* 2023 */ 'C', 'O', 'P', '0', '9', 0,
+ /* 2029 */ 'C', 'O', 'P', '0', '1', '9', 0,
+ /* 2036 */ 'C', 'O', 'P', '2', '1', '9', 0,
+ /* 2043 */ 'C', 'O', 'P', '3', '1', '9', 0,
+ /* 2050 */ 'F', '1', '9', 0,
+ /* 2054 */ 'F', '_', 'H', 'I', '1', '9', 0,
+ /* 2061 */ 'F', 'C', 'R', '1', '9', 0,
+ /* 2067 */ 'H', 'W', 'R', '1', '9', 0,
+ /* 2073 */ 'W', '1', '9', 0,
+ /* 2077 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0,
+ /* 2093 */ 'C', 'O', 'P', '0', '2', '9', 0,
+ /* 2100 */ 'C', 'O', 'P', '2', '2', '9', 0,
+ /* 2107 */ 'C', 'O', 'P', '3', '2', '9', 0,
+ /* 2114 */ 'F', '2', '9', 0,
+ /* 2118 */ 'F', '_', 'H', 'I', '2', '9', 0,
+ /* 2125 */ 'C', 'O', 'P', '2', '9', 0,
+ /* 2131 */ 'F', 'C', 'R', '2', '9', 0,
+ /* 2137 */ 'H', 'W', 'R', '2', '9', 0,
+ /* 2143 */ 'W', '2', '9', 0,
+ /* 2147 */ 'C', 'O', 'P', '3', '9', 0,
+ /* 2153 */ 'D', '9', 0,
+ /* 2156 */ 'F', '9', 0,
+ /* 2159 */ 'F', '_', 'H', 'I', '9', 0,
+ /* 2165 */ 'F', 'C', 'R', '9', 0,
+ /* 2170 */ 'H', 'W', 'R', '9', 0,
+ /* 2175 */ 'T', '9', 0,
+ /* 2178 */ 'W', '9', 0,
+ /* 2181 */ 'R', 'A', 0,
+ /* 2184 */ 'P', 'C', 0,
+ /* 2187 */ 'D', 'S', 'P', 'E', 'F', 'I', 0,
+ /* 2194 */ 'Z', 'E', 'R', 'O', 0,
+ /* 2199 */ 'F', 'P', 0,
+ /* 2202 */ 'G', 'P', 0,
+ /* 2205 */ 'S', 'P', 0,
+ /* 2208 */ 'M', 'S', 'A', 'I', 'R', 0,
+ /* 2214 */ 'M', 'S', 'A', 'C', 'S', 'R', 0,
+ /* 2221 */ 'A', 'T', 0,
+ /* 2224 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0,
+ /* 2233 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0,
+ /* 2241 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0,
+ /* 2252 */ 'M', 'S', 'A', 'M', 'a', 'p', 0,
+ /* 2259 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0,
+ /* 2268 */ 'D', 'S', 'P', 'P', 'o', 's', 0,
+ /* 2275 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0,
+ /* 2285 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0,
+ /* 2295 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0,
+ /* 2306 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0,
+ /* 2316 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0,
+};
+
+extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
+ { 5, 0, 0, 0, 0, 0 },
+ { 2221, 1, 82, 1, 4033, 0 },
+ { 2224, 1, 1, 1, 4033, 0 },
+ { 2316, 1, 1, 1, 4033, 0 },
+ { 2187, 1, 1, 1, 4033, 0 },
+ { 2241, 8, 1, 2, 32, 4 },
+ { 2268, 1, 1, 1, 1089, 0 },
+ { 2285, 1, 1, 1, 1089, 0 },
+ { 2199, 1, 102, 1, 1089, 0 },
+ { 2202, 1, 104, 1, 1089, 0 },
+ { 2275, 1, 1, 1, 1089, 0 },
+ { 2214, 1, 1, 1, 1089, 0 },
+ { 2208, 1, 1, 1, 1089, 0 },
+ { 2252, 1, 1, 1, 1089, 0 },
+ { 2306, 1, 1, 1, 1089, 0 },
+ { 2295, 1, 1, 1, 1089, 0 },
+ { 2233, 1, 1, 1, 1089, 0 },
+ { 2259, 1, 1, 1, 1089, 0 },
+ { 2184, 1, 1, 1, 1089, 0 },
+ { 2181, 1, 106, 1, 1089, 0 },
+ { 2205, 1, 108, 1, 1089, 0 },
+ { 2194, 1, 110, 1, 1089, 0 },
+ { 179, 1, 110, 1, 1089, 0 },
+ { 419, 1, 110, 1, 1089, 0 },
+ { 611, 1, 110, 1, 1089, 0 },
+ { 797, 1, 110, 1, 1089, 0 },
+ { 182, 227, 110, 9, 1042, 10 },
+ { 422, 227, 1, 9, 1042, 10 },
+ { 614, 227, 1, 9, 1042, 10 },
+ { 800, 227, 1, 9, 1042, 10 },
+ { 1385, 238, 1, 0, 0, 2 },
+ { 0, 1, 1, 1, 1153, 0 },
+ { 240, 1, 1, 1, 1153, 0 },
+ { 480, 1, 1, 1, 1153, 0 },
+ { 666, 1, 1, 1, 1153, 0 },
+ { 844, 1, 1, 1, 1153, 0 },
+ { 1427, 1, 1, 1, 1153, 0 },
+ { 1581, 1, 1, 1, 1153, 0 },
+ { 1731, 1, 1, 1, 1153, 0 },
+ { 1881, 1, 1, 1, 1153, 0 },
+ { 2023, 1, 1, 1, 1153, 0 },
+ { 90, 1, 1, 1, 1153, 0 },
+ { 330, 1, 1, 1, 1153, 0 },
+ { 570, 1, 1, 1, 1153, 0 },
+ { 756, 1, 1, 1, 1153, 0 },
+ { 934, 1, 1, 1, 1153, 0 },
+ { 1517, 1, 1, 1, 1153, 0 },
+ { 1667, 1, 1, 1, 1153, 0 },
+ { 1817, 1, 1, 1, 1153, 0 },
+ { 1967, 1, 1, 1, 1153, 0 },
+ { 2125, 1, 1, 1, 1153, 0 },
+ { 157, 1, 1, 1, 1153, 0 },
+ { 397, 1, 1, 1, 1153, 0 },
+ { 605, 1, 1, 1, 1153, 0 },
+ { 791, 1, 1, 1, 1153, 0 },
+ { 956, 1, 1, 1, 1153, 0 },
+ { 1539, 1, 1, 1, 1153, 0 },
+ { 1689, 1, 1, 1, 1153, 0 },
+ { 1839, 1, 1, 1, 1153, 0 },
+ { 1989, 1, 1, 1, 1153, 0 },
+ { 2147, 1, 1, 1, 1153, 0 },
+ { 6, 1, 1, 1, 1153, 0 },
+ { 246, 1, 1, 1, 1153, 0 },
+ { 486, 1, 1, 1, 1153, 0 },
+ { 672, 1, 1, 1, 1153, 0 },
+ { 850, 1, 1, 1, 1153, 0 },
+ { 1433, 1, 1, 1, 1153, 0 },
+ { 1587, 1, 1, 1, 1153, 0 },
+ { 1737, 1, 1, 1, 1153, 0 },
+ { 1887, 1, 1, 1, 1153, 0 },
+ { 2029, 1, 1, 1, 1153, 0 },
+ { 58, 1, 1, 1, 1153, 0 },
+ { 298, 1, 1, 1, 1153, 0 },
+ { 538, 1, 1, 1, 1153, 0 },
+ { 724, 1, 1, 1, 1153, 0 },
+ { 902, 1, 1, 1, 1153, 0 },
+ { 1485, 1, 1, 1, 1153, 0 },
+ { 1635, 1, 1, 1, 1153, 0 },
+ { 1785, 1, 1, 1, 1153, 0 },
+ { 1935, 1, 1, 1, 1153, 0 },
+ { 2093, 1, 1, 1, 1153, 0 },
+ { 125, 1, 1, 1, 1153, 0 },
+ { 365, 1, 1, 1, 1153, 0 },
+ { 13, 1, 1, 1, 1153, 0 },
+ { 253, 1, 1, 1, 1153, 0 },
+ { 493, 1, 1, 1, 1153, 0 },
+ { 679, 1, 1, 1, 1153, 0 },
+ { 857, 1, 1, 1, 1153, 0 },
+ { 1440, 1, 1, 1, 1153, 0 },
+ { 1594, 1, 1, 1, 1153, 0 },
+ { 1744, 1, 1, 1, 1153, 0 },
+ { 1894, 1, 1, 1, 1153, 0 },
+ { 2036, 1, 1, 1, 1153, 0 },
+ { 65, 1, 1, 1, 1153, 0 },
+ { 305, 1, 1, 1, 1153, 0 },
+ { 545, 1, 1, 1, 1153, 0 },
+ { 731, 1, 1, 1, 1153, 0 },
+ { 909, 1, 1, 1, 1153, 0 },
+ { 1492, 1, 1, 1, 1153, 0 },
+ { 1642, 1, 1, 1, 1153, 0 },
+ { 1792, 1, 1, 1, 1153, 0 },
+ { 1942, 1, 1, 1, 1153, 0 },
+ { 2100, 1, 1, 1, 1153, 0 },
+ { 132, 1, 1, 1, 1153, 0 },
+ { 372, 1, 1, 1, 1153, 0 },
+ { 20, 1, 1, 1, 1153, 0 },
+ { 260, 1, 1, 1, 1153, 0 },
+ { 500, 1, 1, 1, 1153, 0 },
+ { 686, 1, 1, 1, 1153, 0 },
+ { 864, 1, 1, 1, 1153, 0 },
+ { 1447, 1, 1, 1, 1153, 0 },
+ { 1601, 1, 1, 1, 1153, 0 },
+ { 1751, 1, 1, 1, 1153, 0 },
+ { 1901, 1, 1, 1, 1153, 0 },
+ { 2043, 1, 1, 1, 1153, 0 },
+ { 72, 1, 1, 1, 1153, 0 },
+ { 312, 1, 1, 1, 1153, 0 },
+ { 552, 1, 1, 1, 1153, 0 },
+ { 738, 1, 1, 1, 1153, 0 },
+ { 916, 1, 1, 1, 1153, 0 },
+ { 1499, 1, 1, 1, 1153, 0 },
+ { 1649, 1, 1, 1, 1153, 0 },
+ { 1799, 1, 1, 1, 1153, 0 },
+ { 1949, 1, 1, 1, 1153, 0 },
+ { 2107, 1, 1, 1, 1153, 0 },
+ { 139, 1, 1, 1, 1153, 0 },
+ { 379, 1, 1, 1, 1153, 0 },
+ { 191, 14, 1, 9, 994, 10 },
+ { 431, 17, 1, 9, 994, 10 },
+ { 623, 20, 1, 9, 994, 10 },
+ { 809, 23, 1, 9, 994, 10 },
+ { 1396, 26, 1, 9, 994, 10 },
+ { 1550, 29, 1, 9, 994, 10 },
+ { 1700, 32, 1, 9, 994, 10 },
+ { 1850, 35, 1, 9, 994, 10 },
+ { 1995, 38, 1, 9, 994, 10 },
+ { 2153, 41, 1, 9, 994, 10 },
+ { 27, 44, 1, 9, 994, 10 },
+ { 267, 47, 1, 9, 994, 10 },
+ { 507, 50, 1, 9, 994, 10 },
+ { 693, 53, 1, 9, 994, 10 },
+ { 871, 56, 1, 9, 994, 10 },
+ { 1454, 59, 1, 9, 994, 10 },
+ { 112, 1, 144, 1, 2305, 0 },
+ { 352, 1, 142, 1, 2305, 0 },
+ { 592, 1, 140, 1, 2305, 0 },
+ { 778, 1, 138, 1, 2305, 0 },
+ { 194, 1, 159, 1, 4001, 0 },
+ { 434, 1, 163, 1, 4001, 0 },
+ { 626, 1, 163, 1, 4001, 0 },
+ { 812, 1, 167, 1, 4001, 0 },
+ { 1399, 1, 167, 1, 4001, 0 },
+ { 1553, 1, 171, 1, 4001, 0 },
+ { 1703, 1, 171, 1, 4001, 0 },
+ { 1853, 1, 175, 1, 4001, 0 },
+ { 1998, 1, 175, 1, 4001, 0 },
+ { 2156, 1, 179, 1, 4001, 0 },
+ { 31, 1, 179, 1, 4001, 0 },
+ { 271, 1, 183, 1, 4001, 0 },
+ { 511, 1, 183, 1, 4001, 0 },
+ { 697, 1, 187, 1, 4001, 0 },
+ { 875, 1, 187, 1, 4001, 0 },
+ { 1458, 1, 191, 1, 4001, 0 },
+ { 1608, 1, 191, 1, 4001, 0 },
+ { 1758, 1, 195, 1, 4001, 0 },
+ { 1908, 1, 195, 1, 4001, 0 },
+ { 2050, 1, 199, 1, 4001, 0 },
+ { 79, 1, 199, 1, 4001, 0 },
+ { 319, 1, 203, 1, 4001, 0 },
+ { 559, 1, 203, 1, 4001, 0 },
+ { 745, 1, 207, 1, 4001, 0 },
+ { 923, 1, 207, 1, 4001, 0 },
+ { 1506, 1, 211, 1, 4001, 0 },
+ { 1656, 1, 211, 1, 4001, 0 },
+ { 1806, 1, 215, 1, 4001, 0 },
+ { 1956, 1, 215, 1, 4001, 0 },
+ { 2114, 1, 219, 1, 4001, 0 },
+ { 146, 1, 219, 1, 4001, 0 },
+ { 386, 1, 223, 1, 4001, 0 },
+ { 186, 1, 1, 1, 4001, 0 },
+ { 426, 1, 1, 1, 4001, 0 },
+ { 618, 1, 1, 1, 4001, 0 },
+ { 804, 1, 1, 1, 4001, 0 },
+ { 1391, 1, 1, 1, 4001, 0 },
+ { 1545, 1, 1, 1, 4001, 0 },
+ { 1695, 1, 1, 1, 4001, 0 },
+ { 1845, 1, 1, 1, 4001, 0 },
+ { 218, 1, 1, 1, 4001, 0 },
+ { 458, 1, 1, 1, 4001, 0 },
+ { 647, 1, 1, 1, 4001, 0 },
+ { 825, 1, 1, 1, 4001, 0 },
+ { 1408, 1, 1, 1, 4001, 0 },
+ { 1562, 1, 1, 1, 4001, 0 },
+ { 1712, 1, 1, 1, 4001, 0 },
+ { 1862, 1, 1, 1, 4001, 0 },
+ { 2007, 1, 1, 1, 4001, 0 },
+ { 2165, 1, 1, 1, 4001, 0 },
+ { 42, 1, 1, 1, 4001, 0 },
+ { 282, 1, 1, 1, 4001, 0 },
+ { 522, 1, 1, 1, 4001, 0 },
+ { 708, 1, 1, 1, 4001, 0 },
+ { 886, 1, 1, 1, 4001, 0 },
+ { 1469, 1, 1, 1, 4001, 0 },
+ { 1619, 1, 1, 1, 4001, 0 },
+ { 1769, 1, 1, 1, 4001, 0 },
+ { 1919, 1, 1, 1, 4001, 0 },
+ { 2061, 1, 1, 1, 4001, 0 },
+ { 96, 1, 1, 1, 4001, 0 },
+ { 336, 1, 1, 1, 4001, 0 },
+ { 576, 1, 1, 1, 4001, 0 },
+ { 762, 1, 1, 1, 4001, 0 },
+ { 940, 1, 1, 1, 4001, 0 },
+ { 1523, 1, 1, 1, 4001, 0 },
+ { 1673, 1, 1, 1, 4001, 0 },
+ { 1823, 1, 1, 1, 4001, 0 },
+ { 1973, 1, 1, 1, 4001, 0 },
+ { 2131, 1, 1, 1, 4001, 0 },
+ { 163, 1, 1, 1, 4001, 0 },
+ { 403, 1, 1, 1, 4001, 0 },
+ { 1367, 136, 1, 0, 1184, 2 },
+ { 197, 1, 156, 1, 3969, 0 },
+ { 437, 1, 156, 1, 3969, 0 },
+ { 629, 1, 156, 1, 3969, 0 },
+ { 815, 1, 156, 1, 3969, 0 },
+ { 1402, 1, 156, 1, 3969, 0 },
+ { 1556, 1, 156, 1, 3969, 0 },
+ { 1706, 1, 156, 1, 3969, 0 },
+ { 1856, 1, 156, 1, 3969, 0 },
+ { 2001, 1, 156, 1, 3969, 0 },
+ { 2159, 1, 156, 1, 3969, 0 },
+ { 35, 1, 156, 1, 3969, 0 },
+ { 275, 1, 156, 1, 3969, 0 },
+ { 515, 1, 156, 1, 3969, 0 },
+ { 701, 1, 156, 1, 3969, 0 },
+ { 879, 1, 156, 1, 3969, 0 },
+ { 1462, 1, 156, 1, 3969, 0 },
+ { 1612, 1, 156, 1, 3969, 0 },
+ { 1762, 1, 156, 1, 3969, 0 },
+ { 1912, 1, 156, 1, 3969, 0 },
+ { 2054, 1, 156, 1, 3969, 0 },
+ { 83, 1, 156, 1, 3969, 0 },
+ { 323, 1, 156, 1, 3969, 0 },
+ { 563, 1, 156, 1, 3969, 0 },
+ { 749, 1, 156, 1, 3969, 0 },
+ { 927, 1, 156, 1, 3969, 0 },
+ { 1510, 1, 156, 1, 3969, 0 },
+ { 1660, 1, 156, 1, 3969, 0 },
+ { 1810, 1, 156, 1, 3969, 0 },
+ { 1960, 1, 156, 1, 3969, 0 },
+ { 2118, 1, 156, 1, 3969, 0 },
+ { 150, 1, 156, 1, 3969, 0 },
+ { 390, 1, 156, 1, 3969, 0 },
+ { 1373, 128, 1, 0, 1216, 2 },
+ { 199, 1, 234, 1, 1826, 0 },
+ { 439, 1, 134, 1, 1826, 0 },
+ { 631, 1, 134, 1, 1826, 0 },
+ { 817, 1, 134, 1, 1826, 0 },
+ { 223, 1, 1, 1, 3937, 0 },
+ { 463, 1, 1, 1, 3937, 0 },
+ { 652, 1, 1, 1, 3937, 0 },
+ { 830, 1, 1, 1, 3937, 0 },
+ { 1413, 1, 1, 1, 3937, 0 },
+ { 1567, 1, 1, 1, 3937, 0 },
+ { 1717, 1, 1, 1, 3937, 0 },
+ { 1867, 1, 1, 1, 3937, 0 },
+ { 2012, 1, 1, 1, 3937, 0 },
+ { 2170, 1, 1, 1, 3937, 0 },
+ { 48, 1, 1, 1, 3937, 0 },
+ { 288, 1, 1, 1, 3937, 0 },
+ { 528, 1, 1, 1, 3937, 0 },
+ { 714, 1, 1, 1, 3937, 0 },
+ { 892, 1, 1, 1, 3937, 0 },
+ { 1475, 1, 1, 1, 3937, 0 },
+ { 1625, 1, 1, 1, 3937, 0 },
+ { 1775, 1, 1, 1, 3937, 0 },
+ { 1925, 1, 1, 1, 3937, 0 },
+ { 2067, 1, 1, 1, 3937, 0 },
+ { 102, 1, 1, 1, 3937, 0 },
+ { 342, 1, 1, 1, 3937, 0 },
+ { 582, 1, 1, 1, 3937, 0 },
+ { 768, 1, 1, 1, 3937, 0 },
+ { 946, 1, 1, 1, 3937, 0 },
+ { 1529, 1, 1, 1, 3937, 0 },
+ { 1679, 1, 1, 1, 3937, 0 },
+ { 1829, 1, 1, 1, 3937, 0 },
+ { 1979, 1, 1, 1, 3937, 0 },
+ { 2137, 1, 1, 1, 3937, 0 },
+ { 169, 1, 1, 1, 3937, 0 },
+ { 409, 1, 1, 1, 3937, 0 },
+ { 203, 1, 100, 1, 3937, 0 },
+ { 443, 1, 100, 1, 3937, 0 },
+ { 211, 1, 230, 1, 1794, 0 },
+ { 451, 1, 126, 1, 1794, 0 },
+ { 640, 1, 126, 1, 1794, 0 },
+ { 821, 1, 126, 1, 1794, 0 },
+ { 206, 1, 1, 1, 3905, 0 },
+ { 446, 1, 1, 1, 3905, 0 },
+ { 635, 1, 1, 1, 3905, 0 },
+ { 215, 1, 1, 1, 3905, 0 },
+ { 455, 1, 1, 1, 3905, 0 },
+ { 644, 1, 1, 1, 3905, 0 },
+ { 1353, 124, 1, 0, 1248, 2 },
+ { 228, 1, 98, 1, 3873, 0 },
+ { 468, 1, 98, 1, 3873, 0 },
+ { 657, 1, 98, 1, 3873, 0 },
+ { 835, 1, 98, 1, 3873, 0 },
+ { 1418, 1, 98, 1, 3873, 0 },
+ { 1572, 1, 98, 1, 3873, 0 },
+ { 1722, 1, 98, 1, 3873, 0 },
+ { 1872, 1, 98, 1, 3873, 0 },
+ { 1379, 122, 1, 0, 1280, 2 },
+ { 231, 1, 96, 1, 3841, 0 },
+ { 471, 1, 96, 1, 3841, 0 },
+ { 660, 1, 96, 1, 3841, 0 },
+ { 838, 1, 96, 1, 3841, 0 },
+ { 1421, 1, 96, 1, 3841, 0 },
+ { 1575, 1, 96, 1, 3841, 0 },
+ { 1725, 1, 96, 1, 3841, 0 },
+ { 1875, 1, 96, 1, 3841, 0 },
+ { 2017, 1, 96, 1, 3841, 0 },
+ { 2175, 1, 96, 1, 3841, 0 },
+ { 234, 1, 96, 1, 3841, 0 },
+ { 474, 1, 96, 1, 3841, 0 },
+ { 237, 92, 1, 8, 1425, 10 },
+ { 477, 92, 1, 8, 1425, 10 },
+ { 663, 92, 1, 8, 1425, 10 },
+ { 841, 92, 1, 8, 1425, 10 },
+ { 1424, 92, 1, 8, 1425, 10 },
+ { 1578, 92, 1, 8, 1425, 10 },
+ { 1728, 92, 1, 8, 1425, 10 },
+ { 1878, 92, 1, 8, 1425, 10 },
+ { 2020, 92, 1, 8, 1425, 10 },
+ { 2178, 92, 1, 8, 1425, 10 },
+ { 54, 92, 1, 8, 1425, 10 },
+ { 294, 92, 1, 8, 1425, 10 },
+ { 534, 92, 1, 8, 1425, 10 },
+ { 720, 92, 1, 8, 1425, 10 },
+ { 898, 92, 1, 8, 1425, 10 },
+ { 1481, 92, 1, 8, 1425, 10 },
+ { 1631, 92, 1, 8, 1425, 10 },
+ { 1781, 92, 1, 8, 1425, 10 },
+ { 1931, 92, 1, 8, 1425, 10 },
+ { 2073, 92, 1, 8, 1425, 10 },
+ { 108, 92, 1, 8, 1425, 10 },
+ { 348, 92, 1, 8, 1425, 10 },
+ { 588, 92, 1, 8, 1425, 10 },
+ { 774, 92, 1, 8, 1425, 10 },
+ { 952, 92, 1, 8, 1425, 10 },
+ { 1535, 92, 1, 8, 1425, 10 },
+ { 1685, 92, 1, 8, 1425, 10 },
+ { 1835, 92, 1, 8, 1425, 10 },
+ { 1985, 92, 1, 8, 1425, 10 },
+ { 2143, 92, 1, 8, 1425, 10 },
+ { 175, 92, 1, 8, 1425, 10 },
+ { 415, 92, 1, 8, 1425, 10 },
+ { 1359, 118, 1, 0, 1921, 2 },
+ { 983, 118, 1, 0, 1921, 2 },
+ { 1061, 118, 1, 0, 1921, 2 },
+ { 1111, 118, 1, 0, 1921, 2 },
+ { 1149, 118, 1, 0, 1921, 2 },
+ { 989, 130, 1, 12, 656, 10 },
+ { 996, 93, 157, 9, 1377, 10 },
+ { 1067, 93, 157, 9, 1377, 10 },
+ { 1117, 93, 157, 9, 1377, 10 },
+ { 1155, 93, 157, 9, 1377, 10 },
+ { 1187, 93, 157, 9, 1377, 10 },
+ { 1219, 93, 157, 9, 1377, 10 },
+ { 1251, 93, 157, 9, 1377, 10 },
+ { 1283, 93, 157, 9, 1377, 10 },
+ { 1315, 93, 157, 9, 1377, 10 },
+ { 1341, 93, 157, 9, 1377, 10 },
+ { 962, 93, 157, 9, 1377, 10 },
+ { 1040, 93, 157, 9, 1377, 10 },
+ { 1097, 93, 157, 9, 1377, 10 },
+ { 1135, 93, 157, 9, 1377, 10 },
+ { 1173, 93, 157, 9, 1377, 10 },
+ { 1205, 93, 157, 9, 1377, 10 },
+ { 1237, 93, 157, 9, 1377, 10 },
+ { 1269, 93, 157, 9, 1377, 10 },
+ { 1301, 93, 157, 9, 1377, 10 },
+ { 1327, 93, 157, 9, 1377, 10 },
+ { 969, 93, 157, 9, 1377, 10 },
+ { 1047, 93, 157, 9, 1377, 10 },
+ { 1104, 93, 157, 9, 1377, 10 },
+ { 1142, 93, 157, 9, 1377, 10 },
+ { 1180, 93, 157, 9, 1377, 10 },
+ { 1212, 93, 157, 9, 1377, 10 },
+ { 1244, 93, 157, 9, 1377, 10 },
+ { 1276, 93, 157, 9, 1377, 10 },
+ { 1308, 93, 157, 9, 1377, 10 },
+ { 1334, 93, 157, 9, 1377, 10 },
+ { 976, 93, 157, 9, 1377, 10 },
+ { 1054, 93, 157, 9, 1377, 10 },
+ { 2077, 1, 116, 1, 1120, 0 },
+ { 1002, 138, 236, 0, 1344, 2 },
+ { 1009, 150, 1, 0, 2337, 2 },
+ { 1073, 150, 1, 0, 2337, 2 },
+ { 1015, 150, 232, 0, 1312, 2 },
+ { 1022, 152, 1, 0, 2369, 2 },
+ { 1079, 152, 1, 0, 2369, 2 },
+ { 1123, 152, 1, 0, 2369, 2 },
+ { 1161, 152, 1, 0, 2369, 2 },
+ { 1193, 152, 1, 0, 2369, 2 },
+ { 1225, 152, 1, 0, 2369, 2 },
+ { 1257, 152, 1, 0, 2369, 2 },
+ { 1289, 152, 1, 0, 2369, 2 },
+ { 1028, 154, 1, 0, 2369, 2 },
+ { 1085, 154, 1, 0, 2369, 2 },
+ { 1129, 154, 1, 0, 2369, 2 },
+ { 1167, 154, 1, 0, 2369, 2 },
+ { 1199, 154, 1, 0, 2369, 2 },
+ { 1231, 154, 1, 0, 2369, 2 },
+ { 1263, 154, 1, 0, 2369, 2 },
+ { 1295, 154, 1, 0, 2369, 2 },
+ { 1321, 154, 1, 0, 2369, 2 },
+ { 1347, 154, 1, 0, 2369, 2 },
+ { 1034, 154, 1, 0, 2369, 2 },
+ { 1091, 154, 1, 0, 2369, 2 },
+};
+
+extern const MCPhysReg MipsRegUnitRoots[][2] = {
+ { Mips::AT },
+ { Mips::DSPCCond },
+ { Mips::DSPCarry },
+ { Mips::DSPEFI },
+ { Mips::DSPOutFlag16_19 },
+ { Mips::DSPOutFlag20 },
+ { Mips::DSPOutFlag21 },
+ { Mips::DSPOutFlag22 },
+ { Mips::DSPOutFlag23 },
+ { Mips::DSPPos },
+ { Mips::DSPSCount },
+ { Mips::FP },
+ { Mips::GP },
+ { Mips::MSAAccess },
+ { Mips::MSACSR },
+ { Mips::MSAIR },
+ { Mips::MSAMap },
+ { Mips::MSAModify },
+ { Mips::MSARequest },
+ { Mips::MSASave },
+ { Mips::MSAUnmap },
+ { Mips::PC },
+ { Mips::RA },
+ { Mips::SP },
+ { Mips::ZERO },
+ { Mips::A0 },
+ { Mips::A1 },
+ { Mips::A2 },
+ { Mips::A3 },
+ { Mips::LO0 },
+ { Mips::HI0 },
+ { Mips::LO1 },
+ { Mips::HI1 },
+ { Mips::LO2 },
+ { Mips::HI2 },
+ { Mips::LO3 },
+ { Mips::HI3 },
+ { Mips::COP00 },
+ { Mips::COP01 },
+ { Mips::COP02 },
+ { Mips::COP03 },
+ { Mips::COP04 },
+ { Mips::COP05 },
+ { Mips::COP06 },
+ { Mips::COP07 },
+ { Mips::COP08 },
+ { Mips::COP09 },
+ { Mips::COP20 },
+ { Mips::COP21 },
+ { Mips::COP22 },
+ { Mips::COP23 },
+ { Mips::COP24 },
+ { Mips::COP25 },
+ { Mips::COP26 },
+ { Mips::COP27 },
+ { Mips::COP28 },
+ { Mips::COP29 },
+ { Mips::COP30 },
+ { Mips::COP31 },
+ { Mips::COP32 },
+ { Mips::COP33 },
+ { Mips::COP34 },
+ { Mips::COP35 },
+ { Mips::COP36 },
+ { Mips::COP37 },
+ { Mips::COP38 },
+ { Mips::COP39 },
+ { Mips::COP010 },
+ { Mips::COP011 },
+ { Mips::COP012 },
+ { Mips::COP013 },
+ { Mips::COP014 },
+ { Mips::COP015 },
+ { Mips::COP016 },
+ { Mips::COP017 },
+ { Mips::COP018 },
+ { Mips::COP019 },
+ { Mips::COP020 },
+ { Mips::COP021 },
+ { Mips::COP022 },
+ { Mips::COP023 },
+ { Mips::COP024 },
+ { Mips::COP025 },
+ { Mips::COP026 },
+ { Mips::COP027 },
+ { Mips::COP028 },
+ { Mips::COP029 },
+ { Mips::COP030 },
+ { Mips::COP031 },
+ { Mips::COP210 },
+ { Mips::COP211 },
+ { Mips::COP212 },
+ { Mips::COP213 },
+ { Mips::COP214 },
+ { Mips::COP215 },
+ { Mips::COP216 },
+ { Mips::COP217 },
+ { Mips::COP218 },
+ { Mips::COP219 },
+ { Mips::COP220 },
+ { Mips::COP221 },
+ { Mips::COP222 },
+ { Mips::COP223 },
+ { Mips::COP224 },
+ { Mips::COP225 },
+ { Mips::COP226 },
+ { Mips::COP227 },
+ { Mips::COP228 },
+ { Mips::COP229 },
+ { Mips::COP230 },
+ { Mips::COP231 },
+ { Mips::COP310 },
+ { Mips::COP311 },
+ { Mips::COP312 },
+ { Mips::COP313 },
+ { Mips::COP314 },
+ { Mips::COP315 },
+ { Mips::COP316 },
+ { Mips::COP317 },
+ { Mips::COP318 },
+ { Mips::COP319 },
+ { Mips::COP320 },
+ { Mips::COP321 },
+ { Mips::COP322 },
+ { Mips::COP323 },
+ { Mips::COP324 },
+ { Mips::COP325 },
+ { Mips::COP326 },
+ { Mips::COP327 },
+ { Mips::COP328 },
+ { Mips::COP329 },
+ { Mips::COP330 },
+ { Mips::COP331 },
+ { Mips::F0 },
+ { Mips::F1 },
+ { Mips::F2 },
+ { Mips::F3 },
+ { Mips::F4 },
+ { Mips::F5 },
+ { Mips::F6 },
+ { Mips::F7 },
+ { Mips::F8 },
+ { Mips::F9 },
+ { Mips::F10 },
+ { Mips::F11 },
+ { Mips::F12 },
+ { Mips::F13 },
+ { Mips::F14 },
+ { Mips::F15 },
+ { Mips::F16 },
+ { Mips::F17 },
+ { Mips::F18 },
+ { Mips::F19 },
+ { Mips::F20 },
+ { Mips::F21 },
+ { Mips::F22 },
+ { Mips::F23 },
+ { Mips::F24 },
+ { Mips::F25 },
+ { Mips::F26 },
+ { Mips::F27 },
+ { Mips::F28 },
+ { Mips::F29 },
+ { Mips::F30 },
+ { Mips::F31 },
+ { Mips::FCC0 },
+ { Mips::FCC1 },
+ { Mips::FCC2 },
+ { Mips::FCC3 },
+ { Mips::FCC4 },
+ { Mips::FCC5 },
+ { Mips::FCC6 },
+ { Mips::FCC7 },
+ { Mips::FCR0 },
+ { Mips::FCR1 },
+ { Mips::FCR2 },
+ { Mips::FCR3 },
+ { Mips::FCR4 },
+ { Mips::FCR5 },
+ { Mips::FCR6 },
+ { Mips::FCR7 },
+ { Mips::FCR8 },
+ { Mips::FCR9 },
+ { Mips::FCR10 },
+ { Mips::FCR11 },
+ { Mips::FCR12 },
+ { Mips::FCR13 },
+ { Mips::FCR14 },
+ { Mips::FCR15 },
+ { Mips::FCR16 },
+ { Mips::FCR17 },
+ { Mips::FCR18 },
+ { Mips::FCR19 },
+ { Mips::FCR20 },
+ { Mips::FCR21 },
+ { Mips::FCR22 },
+ { Mips::FCR23 },
+ { Mips::FCR24 },
+ { Mips::FCR25 },
+ { Mips::FCR26 },
+ { Mips::FCR27 },
+ { Mips::FCR28 },
+ { Mips::FCR29 },
+ { Mips::FCR30 },
+ { Mips::FCR31 },
+ { Mips::F_HI0 },
+ { Mips::F_HI1 },
+ { Mips::F_HI2 },
+ { Mips::F_HI3 },
+ { Mips::F_HI4 },
+ { Mips::F_HI5 },
+ { Mips::F_HI6 },
+ { Mips::F_HI7 },
+ { Mips::F_HI8 },
+ { Mips::F_HI9 },
+ { Mips::F_HI10 },
+ { Mips::F_HI11 },
+ { Mips::F_HI12 },
+ { Mips::F_HI13 },
+ { Mips::F_HI14 },
+ { Mips::F_HI15 },
+ { Mips::F_HI16 },
+ { Mips::F_HI17 },
+ { Mips::F_HI18 },
+ { Mips::F_HI19 },
+ { Mips::F_HI20 },
+ { Mips::F_HI21 },
+ { Mips::F_HI22 },
+ { Mips::F_HI23 },
+ { Mips::F_HI24 },
+ { Mips::F_HI25 },
+ { Mips::F_HI26 },
+ { Mips::F_HI27 },
+ { Mips::F_HI28 },
+ { Mips::F_HI29 },
+ { Mips::F_HI30 },
+ { Mips::F_HI31 },
+ { Mips::HWR0 },
+ { Mips::HWR1 },
+ { Mips::HWR2 },
+ { Mips::HWR3 },
+ { Mips::HWR4 },
+ { Mips::HWR5 },
+ { Mips::HWR6 },
+ { Mips::HWR7 },
+ { Mips::HWR8 },
+ { Mips::HWR9 },
+ { Mips::HWR10 },
+ { Mips::HWR11 },
+ { Mips::HWR12 },
+ { Mips::HWR13 },
+ { Mips::HWR14 },
+ { Mips::HWR15 },
+ { Mips::HWR16 },
+ { Mips::HWR17 },
+ { Mips::HWR18 },
+ { Mips::HWR19 },
+ { Mips::HWR20 },
+ { Mips::HWR21 },
+ { Mips::HWR22 },
+ { Mips::HWR23 },
+ { Mips::HWR24 },
+ { Mips::HWR25 },
+ { Mips::HWR26 },
+ { Mips::HWR27 },
+ { Mips::HWR28 },
+ { Mips::HWR29 },
+ { Mips::HWR30 },
+ { Mips::HWR31 },
+ { Mips::K0 },
+ { Mips::K1 },
+ { Mips::MPL0 },
+ { Mips::MPL1 },
+ { Mips::MPL2 },
+ { Mips::P0 },
+ { Mips::P1 },
+ { Mips::P2 },
+ { Mips::S0 },
+ { Mips::S1 },
+ { Mips::S2 },
+ { Mips::S3 },
+ { Mips::S4 },
+ { Mips::S5 },
+ { Mips::S6 },
+ { Mips::S7 },
+ { Mips::T0 },
+ { Mips::T1 },
+ { Mips::T2 },
+ { Mips::T3 },
+ { Mips::T4 },
+ { Mips::T5 },
+ { Mips::T6 },
+ { Mips::T7 },
+ { Mips::T8 },
+ { Mips::T9 },
+ { Mips::V0 },
+ { Mips::V1 },
+};
+
+namespace { // Register classes...
+ // MSA128F16 Register Class...
+ const MCPhysReg MSA128F16[] = {
+ Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
+ };
+
+ // MSA128F16 Bit set.
+ const uint8_t MSA128F16Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128F16_with_sub_64_in_OddSP Register Class...
+ const MCPhysReg MSA128F16_with_sub_64_in_OddSP[] = {
+ Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31,
+ };
+
+ // MSA128F16_with_sub_64_in_OddSP Bit set.
+ const uint8_t MSA128F16_with_sub_64_in_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
+ };
+
+ // OddSP Register Class...
+ const MCPhysReg OddSP[] = {
+ Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
+ };
+
+ // OddSP Bit set.
+ const uint8_t OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
+ };
+
+ // CCR Register Class...
+ const MCPhysReg CCR[] = {
+ Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31,
+ };
+
+ // CCR Bit set.
+ const uint8_t CCRBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // COP0 Register Class...
+ const MCPhysReg COP0[] = {
+ Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031,
+ };
+
+ // COP0 Bit set.
+ const uint8_t COP0Bits[] = {
+ 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07,
+ };
+
+ // COP2 Register Class...
+ const MCPhysReg COP2[] = {
+ Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231,
+ };
+
+ // COP2 Bit set.
+ const uint8_t COP2Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01,
+ };
+
+ // COP3 Register Class...
+ const MCPhysReg COP3[] = {
+ Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331,
+ };
+
+ // COP3 Bit set.
+ const uint8_t COP3Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f,
+ };
+
+ // DSPR Register Class...
+ const MCPhysReg DSPR[] = {
+ Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
+ };
+
+ // DSPR Bit set.
+ const uint8_t DSPRBits[] = {
+ 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
+ };
+
+ // FGR32 Register Class...
+ const MCPhysReg FGR32[] = {
+ Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
+ };
+
+ // FGR32 Bit set.
+ const uint8_t FGR32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // FGRCC Register Class...
+ const MCPhysReg FGRCC[] = {
+ Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31,
+ };
+
+ // FGRCC Bit set.
+ const uint8_t FGRCCBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // FGRH32 Register Class...
+ const MCPhysReg FGRH32[] = {
+ Mips::F_HI0, Mips::F_HI1, Mips::F_HI2, Mips::F_HI3, Mips::F_HI4, Mips::F_HI5, Mips::F_HI6, Mips::F_HI7, Mips::F_HI8, Mips::F_HI9, Mips::F_HI10, Mips::F_HI11, Mips::F_HI12, Mips::F_HI13, Mips::F_HI14, Mips::F_HI15, Mips::F_HI16, Mips::F_HI17, Mips::F_HI18, Mips::F_HI19, Mips::F_HI20, Mips::F_HI21, Mips::F_HI22, Mips::F_HI23, Mips::F_HI24, Mips::F_HI25, Mips::F_HI26, Mips::F_HI27, Mips::F_HI28, Mips::F_HI29, Mips::F_HI30, Mips::F_HI31,
+ };
+
+ // FGRH32 Bit set.
+ const uint8_t FGRH32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
+ };
+
+ // GPR32 Register Class...
+ const MCPhysReg GPR32[] = {
+ Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
+ };
+
+ // GPR32 Bit set.
+ const uint8_t GPR32Bits[] = {
+ 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
+ };
+
+ // HWRegs Register Class...
+ const MCPhysReg HWRegs[] = {
+ Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31,
+ };
+
+ // HWRegs Bit set.
+ const uint8_t HWRegsBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // GPR32NONZERO Register Class...
+ const MCPhysReg GPR32NONZERO[] = {
+ Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA,
+ };
+
+ // GPR32NONZERO Bit set.
+ const uint8_t GPR32NONZEROBits[] = {
+ 0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
+ };
+
+ // OddSP_with_sub_hi Register Class...
+ const MCPhysReg OddSP_with_sub_hi[] = {
+ Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
+ };
+
+ // OddSP_with_sub_hi Bit set.
+ const uint8_t OddSP_with_sub_hiBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
+ };
+
+ // FGR32_and_OddSP Register Class...
+ const MCPhysReg FGR32_and_OddSP[] = {
+ Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31,
+ };
+
+ // FGR32_and_OddSP Bit set.
+ const uint8_t FGR32_and_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
+ };
+
+ // FGRH32_and_OddSP Register Class...
+ const MCPhysReg FGRH32_and_OddSP[] = {
+ Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31,
+ };
+
+ // FGRH32_and_OddSP Bit set.
+ const uint8_t FGRH32_and_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
+ };
+
+ // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
+ const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
+ Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
+ };
+
+ // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
+ const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
+ };
+
+ // CPU16RegsPlusSP Register Class...
+ const MCPhysReg CPU16RegsPlusSP[] = {
+ Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP,
+ };
+
+ // CPU16RegsPlusSP Bit set.
+ const uint8_t CPU16RegsPlusSPBits[] = {
+ 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
+ };
+
+ // CPU16Regs Register Class...
+ const MCPhysReg CPU16Regs[] = {
+ Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1,
+ };
+
+ // CPU16Regs Bit set.
+ const uint8_t CPU16RegsBits[] = {
+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
+ };
+
+ // FCC Register Class...
+ const MCPhysReg FCC[] = {
+ Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7,
+ };
+
+ // FCC Bit set.
+ const uint8_t FCCBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
+ };
+
+ // GPRMM16 Register Class...
+ const MCPhysReg GPRMM16[] = {
+ Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
+ };
+
+ // GPRMM16 Bit set.
+ const uint8_t GPRMM16Bits[] = {
+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
+ };
+
+ // GPRMM16MoveP Register Class...
+ const MCPhysReg GPRMM16MoveP[] = {
+ Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
+ };
+
+ // GPRMM16MoveP Bit set.
+ const uint8_t GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
+ };
+
+ // GPRMM16Zero Register Class...
+ const MCPhysReg GPRMM16Zero[] = {
+ Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
+ };
+
+ // GPRMM16Zero Bit set.
+ const uint8_t GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
+ };
+
+ // MSACtrl Register Class...
+ const MCPhysReg MSACtrl[] = {
+ Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap,
+ };
+
+ // MSACtrl Bit set.
+ const uint8_t MSACtrlBits[] = {
+ 0x00, 0xfc, 0x03,
+ };
+
+ // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
+ const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
+ Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15,
+ };
+
+ // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
+ const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
+ };
+
+ // CPU16Regs_and_GPRMM16Zero Register Class...
+ const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
+ Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,
+ };
+
+ // CPU16Regs_and_GPRMM16Zero Bit set.
+ const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
+ };
+
+ // GPR32NONZERO_and_GPRMM16MoveP Register Class...
+ const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
+ Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4,
+ };
+
+ // GPR32NONZERO_and_GPRMM16MoveP Bit set.
+ const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
+ };
+
+ // CPU16Regs_and_GPRMM16MoveP Register Class...
+ const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
+ Mips::S1, Mips::V0, Mips::V1, Mips::S0,
+ };
+
+ // CPU16Regs_and_GPRMM16MoveP Bit set.
+ const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
+ };
+
+ // GPRMM16MoveP_and_GPRMM16Zero Register Class...
+ const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
+ Mips::ZERO, Mips::S1, Mips::V0, Mips::V1,
+ };
+
+ // GPRMM16MoveP_and_GPRMM16Zero Bit set.
+ const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
+ };
+
+ // HI32DSP Register Class...
+ const MCPhysReg HI32DSP[] = {
+ Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3,
+ };
+
+ // HI32DSP Bit set.
+ const uint8_t HI32DSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
+ };
+
+ // LO32DSP Register Class...
+ const MCPhysReg LO32DSP[] = {
+ Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3,
+ };
+
+ // LO32DSP Bit set.
+ const uint8_t LO32DSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
+ };
+
+ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
+ const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
+ Mips::S1, Mips::V0, Mips::V1,
+ };
+
+ // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
+ const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
+ };
+
+ // CPURAReg Register Class...
+ const MCPhysReg CPURAReg[] = {
+ Mips::RA,
+ };
+
+ // CPURAReg Bit set.
+ const uint8_t CPURARegBits[] = {
+ 0x00, 0x00, 0x08,
+ };
+
+ // CPUSPReg Register Class...
+ const MCPhysReg CPUSPReg[] = {
+ Mips::SP,
+ };
+
+ // CPUSPReg Bit set.
+ const uint8_t CPUSPRegBits[] = {
+ 0x00, 0x00, 0x10,
+ };
+
+ // DSPCC Register Class...
+ const MCPhysReg DSPCC[] = {
+ Mips::DSPCCond,
+ };
+
+ // DSPCC Bit set.
+ const uint8_t DSPCCBits[] = {
+ 0x04,
+ };
+
+ // GP32 Register Class...
+ const MCPhysReg GP32[] = {
+ Mips::GP,
+ };
+
+ // GP32 Bit set.
+ const uint8_t GP32Bits[] = {
+ 0x00, 0x02,
+ };
+
+ // GPR32ZERO Register Class...
+ const MCPhysReg GPR32ZERO[] = {
+ Mips::ZERO,
+ };
+
+ // GPR32ZERO Bit set.
+ const uint8_t GPR32ZEROBits[] = {
+ 0x00, 0x00, 0x20,
+ };
+
+ // HI32 Register Class...
+ const MCPhysReg HI32[] = {
+ Mips::HI0,
+ };
+
+ // HI32 Bit set.
+ const uint8_t HI32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+ };
+
+ // LO32 Register Class...
+ const MCPhysReg LO32[] = {
+ Mips::LO0,
+ };
+
+ // LO32 Bit set.
+ const uint8_t LO32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ };
+
+ // SP32 Register Class...
+ const MCPhysReg SP32[] = {
+ Mips::SP,
+ };
+
+ // SP32 Bit set.
+ const uint8_t SP32Bits[] = {
+ 0x00, 0x00, 0x10,
+ };
+
+ // FGR64 Register Class...
+ const MCPhysReg FGR64[] = {
+ Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64,
+ };
+
+ // FGR64 Bit set.
+ const uint8_t FGR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // GPR64 Register Class...
+ const MCPhysReg GPR64[] = {
+ Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
+ };
+
+ // GPR64 Bit set.
+ const uint8_t GPR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPR32NONZERO Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
+ Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64,
+ };
+
+ // GPR64_with_sub_32_in_GPR32NONZERO Bit set.
+ const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
+ 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
+ };
+
+ // AFGR64 Register Class...
+ const MCPhysReg AFGR64[] = {
+ Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15,
+ };
+
+ // AFGR64 Bit set.
+ const uint8_t AFGR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
+ };
+
+ // FGR64_and_OddSP Register Class...
+ const MCPhysReg FGR64_and_OddSP[] = {
+ Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64,
+ };
+
+ // FGR64_and_OddSP Bit set.
+ const uint8_t FGR64_and_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
+ };
+
+ // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
+ Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64,
+ };
+
+ // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
+ const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
+ };
+
+ // AFGR64_and_OddSP Register Class...
+ const MCPhysReg AFGR64_and_OddSP[] = {
+ Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15,
+ };
+
+ // AFGR64_and_OddSP Bit set.
+ const uint8_t AFGR64_and_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
+ Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs Bit set.
+ const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
+ Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
+ const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
+ Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
+ const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
+ Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
+ const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
+ Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64,
+ };
+
+ // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
+ const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
+ };
+
+ // ACC64DSP Register Class...
+ const MCPhysReg ACC64DSP[] = {
+ Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3,
+ };
+
+ // ACC64DSP Bit set.
+ const uint8_t ACC64DSPBits[] = {
+ 0x00, 0x00, 0x00, 0x3c,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
+ Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64,
+ };
+
+ // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
+ const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
+ Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
+ const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
+ Mips::V0_64, Mips::V1_64, Mips::S1_64,
+ };
+
+ // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
+ const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
+ };
+
+ // OCTEON_MPL Register Class...
+ const MCPhysReg OCTEON_MPL[] = {
+ Mips::MPL0, Mips::MPL1, Mips::MPL2,
+ };
+
+ // OCTEON_MPL Bit set.
+ const uint8_t OCTEON_MPLBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
+ };
+
+ // OCTEON_P Register Class...
+ const MCPhysReg OCTEON_P[] = {
+ Mips::P0, Mips::P1, Mips::P2,
+ };
+
+ // OCTEON_P Bit set.
+ const uint8_t OCTEON_PBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
+ };
+
+ // ACC64 Register Class...
+ const MCPhysReg ACC64[] = {
+ Mips::AC0,
+ };
+
+ // ACC64 Bit set.
+ const uint8_t ACC64Bits[] = {
+ 0x00, 0x00, 0x00, 0x04,
+ };
+
+ // GP64 Register Class...
+ const MCPhysReg GP64[] = {
+ Mips::GP_64,
+ };
+
+ // GP64 Bit set.
+ const uint8_t GP64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+ };
+
+ // GPR64_with_sub_32_in_CPURAReg Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
+ Mips::RA_64,
+ };
+
+ // GPR64_with_sub_32_in_CPURAReg Bit set.
+ const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+ };
+
+ // GPR64_with_sub_32_in_GPR32ZERO Register Class...
+ const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
+ Mips::ZERO_64,
+ };
+
+ // GPR64_with_sub_32_in_GPR32ZERO Bit set.
+ const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
+ };
+
+ // HI64 Register Class...
+ const MCPhysReg HI64[] = {
+ Mips::HI0_64,
+ };
+
+ // HI64 Bit set.
+ const uint8_t HI64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
+ };
+
+ // LO64 Register Class...
+ const MCPhysReg LO64[] = {
+ Mips::LO0_64,
+ };
+
+ // LO64 Bit set.
+ const uint8_t LO64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
+ };
+
+ // SP64 Register Class...
+ const MCPhysReg SP64[] = {
+ Mips::SP_64,
+ };
+
+ // SP64 Bit set.
+ const uint8_t SP64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+ };
+
+ // MSA128B Register Class...
+ const MCPhysReg MSA128B[] = {
+ Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
+ };
+
+ // MSA128B Bit set.
+ const uint8_t MSA128BBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128D Register Class...
+ const MCPhysReg MSA128D[] = {
+ Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
+ };
+
+ // MSA128D Bit set.
+ const uint8_t MSA128DBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128H Register Class...
+ const MCPhysReg MSA128H[] = {
+ Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
+ };
+
+ // MSA128H Bit set.
+ const uint8_t MSA128HBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128W Register Class...
+ const MCPhysReg MSA128W[] = {
+ Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31,
+ };
+
+ // MSA128W Bit set.
+ const uint8_t MSA128WBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
+ };
+
+ // MSA128B_with_sub_64_in_OddSP Register Class...
+ const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
+ Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31,
+ };
+
+ // MSA128B_with_sub_64_in_OddSP Bit set.
+ const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
+ };
+
+ // MSA128WEvens Register Class...
+ const MCPhysReg MSA128WEvens[] = {
+ Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30,
+ };
+
+ // MSA128WEvens Bit set.
+ const uint8_t MSA128WEvensBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
+ };
+
+ // ACC128 Register Class...
+ const MCPhysReg ACC128[] = {
+ Mips::AC0_64,
+ };
+
+ // ACC128 Bit set.
+ const uint8_t ACC128Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ };
+
+} // end anonymous namespace
+
+extern const char MipsRegClassStrings[] = {
+ /* 0 */ 'C', 'O', 'P', '0', 0,
+ /* 5 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', 'H', '3', '2', 0,
+ /* 45 */ 'H', 'I', '3', '2', 0,
+ /* 50 */ 'L', 'O', '3', '2', 0,
+ /* 55 */ 'G', 'P', '3', '2', 0,
+ /* 60 */ 'S', 'P', '3', '2', 0,
+ /* 65 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', '3', '2', 0,
+ /* 104 */ 'G', 'P', 'R', '3', '2', 0,
+ /* 110 */ 'C', 'O', 'P', '2', 0,
+ /* 115 */ 'C', 'O', 'P', '3', 0,
+ /* 120 */ 'A', 'C', 'C', '6', '4', 0,
+ /* 126 */ 'H', 'I', '6', '4', 0,
+ /* 131 */ 'L', 'O', '6', '4', 0,
+ /* 136 */ 'G', 'P', '6', '4', 0,
+ /* 141 */ 'S', 'P', '6', '4', 0,
+ /* 146 */ 'A', 'F', 'G', 'R', '6', '4', 0,
+ /* 153 */ 'G', 'P', 'R', '6', '4', 0,
+ /* 159 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', 0,
+ /* 169 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0,
+ /* 177 */ 'A', 'C', 'C', '1', '2', '8', 0,
+ /* 184 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0,
+ /* 192 */ 'F', 'C', 'C', 0,
+ /* 196 */ 'D', 'S', 'P', 'C', 'C', 0,
+ /* 202 */ 'F', 'G', 'R', 'C', 'C', 0,
+ /* 208 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0,
+ /* 216 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0,
+ /* 224 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0,
+ /* 235 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'Z', 'E', 'R', 'O', 0,
+ /* 266 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', 0,
+ /* 300 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0,
+ /* 308 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0,
+ /* 316 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0,
+ /* 325 */ 'F', 'G', 'R', 'H', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
+ /* 342 */ 'F', 'G', 'R', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
+ /* 358 */ 'A', 'F', 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0,
+ /* 375 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0,
+ /* 406 */ 'M', 'S', 'A', '1', '2', '8', 'B', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0,
+ /* 435 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0,
+ /* 472 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0,
+ /* 481 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
+ /* 532 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
+ /* 580 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0,
+ /* 614 */ 'C', 'C', 'R', 0,
+ /* 618 */ 'D', 'S', 'P', 'R', 0,
+ /* 623 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0,
+ /* 631 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0,
+ /* 661 */ 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0,
+ /* 670 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', 0,
+ /* 688 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0,
+ /* 696 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
+ /* 746 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
+ /* 810 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
+ /* 857 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0,
+ /* 890 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0,
+ /* 921 */ 'H', 'W', 'R', 'e', 'g', 's', 0,
+ /* 928 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0,
+};
+
+extern const MCRegisterClass MipsMCRegisterClasses[] = {
+ { MSA128F16, MSA128F16Bits, 159, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 2, 1, true },
+ { MSA128F16_with_sub_64_in_OddSP, MSA128F16_with_sub_64_in_OddSPBits, 375, 16, sizeof(MSA128F16_with_sub_64_in_OddSPBits), Mips::MSA128F16_with_sub_64_in_OddSPRegClassID, 2, 1, true },
+ { OddSP, OddSPBits, 336, 56, sizeof(OddSPBits), Mips::OddSPRegClassID, 4, 1, false },
+ { CCR, CCRBits, 614, 32, sizeof(CCRBits), Mips::CCRRegClassID, 4, 1, false },
+ { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 4, 1, false },
+ { COP2, COP2Bits, 110, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 4, 1, false },
+ { COP3, COP3Bits, 115, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 4, 1, false },
+ { DSPR, DSPRBits, 618, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 4, 1, true },
+ { FGR32, FGR32Bits, 98, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 4, 1, true },
+ { FGRCC, FGRCCBits, 202, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 4, 1, true },
+ { FGRH32, FGRH32Bits, 38, 32, sizeof(FGRH32Bits), Mips::FGRH32RegClassID, 4, 1, false },
+ { GPR32, GPR32Bits, 104, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 4, 1, true },
+ { HWRegs, HWRegsBits, 921, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 4, 1, false },
+ { GPR32NONZERO, GPR32NONZEROBits, 287, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 4, 1, true },
+ { OddSP_with_sub_hi, OddSP_with_sub_hiBits, 670, 24, sizeof(OddSP_with_sub_hiBits), Mips::OddSP_with_sub_hiRegClassID, 4, 1, false },
+ { FGR32_and_OddSP, FGR32_and_OddSPBits, 342, 16, sizeof(FGR32_and_OddSPBits), Mips::FGR32_and_OddSPRegClassID, 4, 1, true },
+ { FGRH32_and_OddSP, FGRH32_and_OddSPBits, 325, 16, sizeof(FGRH32_and_OddSPBits), Mips::FGRH32_and_OddSPRegClassID, 4, 1, false },
+ { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 5, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 1, false },
+ { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 456, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 4, 1, true },
+ { CPU16Regs, CPU16RegsBits, 911, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 4, 1, true },
+ { FCC, FCCBits, 192, 8, sizeof(FCCBits), Mips::FCCRegClassID, 4, 1, false },
+ { GPRMM16, GPRMM16Bits, 169, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 4, 1, true },
+ { GPRMM16MoveP, GPRMM16MovePBits, 519, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 4, 1, true },
+ { GPRMM16Zero, GPRMM16ZeroBits, 734, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 4, 1, true },
+ { MSACtrl, MSACtrlBits, 688, 8, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 4, 1, true },
+ { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 65, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 1, false },
+ { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 784, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 1, true },
+ { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 502, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 4, 1, true },
+ { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 553, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 4, 1, true },
+ { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 717, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 4, 1, true },
+ { HI32DSP, HI32DSPBits, 300, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 4, 1, true },
+ { LO32DSP, LO32DSPBits, 308, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 4, 1, true },
+ { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 767, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 1, true },
+ { CPURAReg, CPURARegBits, 652, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 4, 1, false },
+ { CPUSPReg, CPUSPRegBits, 661, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 4, 1, false },
+ { DSPCC, DSPCCBits, 196, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 4, 1, true },
+ { GP32, GP32Bits, 55, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 4, 1, false },
+ { GPR32ZERO, GPR32ZEROBits, 256, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 4, 1, true },
+ { HI32, HI32Bits, 45, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 4, 1, true },
+ { LO32, LO32Bits, 50, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 4, 1, true },
+ { SP32, SP32Bits, 60, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 4, 1, false },
+ { FGR64, FGR64Bits, 147, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 8, 1, true },
+ { GPR64, GPR64Bits, 153, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 266, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 8, 1, true },
+ { AFGR64, AFGR64Bits, 146, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 8, 1, true },
+ { FGR64_and_OddSP, FGR64_and_OddSPBits, 359, 16, sizeof(FGR64_and_OddSPBits), Mips::FGR64_and_OddSPRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 435, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 1, true },
+ { AFGR64_and_OddSP, AFGR64_and_OddSPBits, 358, 8, sizeof(AFGR64_and_OddSPBits), Mips::AFGR64_and_OddSPRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 890, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 580, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 857, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 810, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 481, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 8, 1, true },
+ { ACC64DSP, ACC64DSPBits, 316, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 532, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 696, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 746, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 1, true },
+ { OCTEON_MPL, OCTEON_MPLBits, 224, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 8, 1, false },
+ { OCTEON_P, OCTEON_PBits, 472, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 8, 1, false },
+ { ACC64, ACC64Bits, 120, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 8, 1, true },
+ { GP64, GP64Bits, 136, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 8, 1, false },
+ { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 631, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 8, 1, true },
+ { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 235, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 8, 1, true },
+ { HI64, HI64Bits, 126, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 8, 1, true },
+ { LO64, LO64Bits, 131, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 8, 1, true },
+ { SP64, SP64Bits, 141, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 8, 1, false },
+ { MSA128B, MSA128BBits, 184, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 16, 1, true },
+ { MSA128D, MSA128DBits, 208, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 16, 1, true },
+ { MSA128H, MSA128HBits, 216, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 16, 1, true },
+ { MSA128W, MSA128WBits, 623, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 16, 1, true },
+ { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 406, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips::MSA128B_with_sub_64_in_OddSPRegClassID, 16, 1, true },
+ { MSA128WEvens, MSA128WEvensBits, 928, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 16, 1, true },
+ { ACC128, ACC128Bits, 177, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 16, 1, true },
+};
+
+// Mips Dwarf<->LLVM register mappings.
+extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
+ { 0U, Mips::ZERO_64 },
+ { 1U, Mips::AT_64 },
+ { 2U, Mips::V0_64 },
+ { 3U, Mips::V1_64 },
+ { 4U, Mips::A0_64 },
+ { 5U, Mips::A1_64 },
+ { 6U, Mips::A2_64 },
+ { 7U, Mips::A3_64 },
+ { 8U, Mips::T0_64 },
+ { 9U, Mips::T1_64 },
+ { 10U, Mips::T2_64 },
+ { 11U, Mips::T3_64 },
+ { 12U, Mips::T4_64 },
+ { 13U, Mips::T5_64 },
+ { 14U, Mips::T6_64 },
+ { 15U, Mips::T7_64 },
+ { 16U, Mips::S0_64 },
+ { 17U, Mips::S1_64 },
+ { 18U, Mips::S2_64 },
+ { 19U, Mips::S3_64 },
+ { 20U, Mips::S4_64 },
+ { 21U, Mips::S5_64 },
+ { 22U, Mips::S6_64 },
+ { 23U, Mips::S7_64 },
+ { 24U, Mips::T8_64 },
+ { 25U, Mips::T9_64 },
+ { 26U, Mips::K0_64 },
+ { 27U, Mips::K1_64 },
+ { 28U, Mips::GP_64 },
+ { 29U, Mips::SP_64 },
+ { 30U, Mips::FP_64 },
+ { 31U, Mips::RA_64 },
+ { 32U, Mips::D0_64 },
+ { 33U, Mips::D1_64 },
+ { 34U, Mips::D2_64 },
+ { 35U, Mips::D3_64 },
+ { 36U, Mips::D4_64 },
+ { 37U, Mips::D5_64 },
+ { 38U, Mips::D6_64 },
+ { 39U, Mips::D7_64 },
+ { 40U, Mips::D8_64 },
+ { 41U, Mips::D9_64 },
+ { 42U, Mips::D10_64 },
+ { 43U, Mips::D11_64 },
+ { 44U, Mips::D12_64 },
+ { 45U, Mips::D13_64 },
+ { 46U, Mips::D14_64 },
+ { 47U, Mips::D15_64 },
+ { 48U, Mips::D16_64 },
+ { 49U, Mips::D17_64 },
+ { 50U, Mips::D18_64 },
+ { 51U, Mips::D19_64 },
+ { 52U, Mips::D20_64 },
+ { 53U, Mips::D21_64 },
+ { 54U, Mips::D22_64 },
+ { 55U, Mips::D23_64 },
+ { 56U, Mips::D24_64 },
+ { 57U, Mips::D25_64 },
+ { 58U, Mips::D26_64 },
+ { 59U, Mips::D27_64 },
+ { 60U, Mips::D28_64 },
+ { 61U, Mips::D29_64 },
+ { 62U, Mips::D30_64 },
+ { 63U, Mips::D31_64 },
+ { 64U, Mips::HI0 },
+ { 65U, Mips::LO0 },
+ { 176U, Mips::HI1 },
+ { 177U, Mips::LO1 },
+ { 178U, Mips::HI2 },
+ { 179U, Mips::LO2 },
+ { 180U, Mips::HI3 },
+ { 181U, Mips::LO3 },
+};
+extern const unsigned MipsDwarfFlavour0Dwarf2LSize = array_lengthof(MipsDwarfFlavour0Dwarf2L);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
+ { 0U, Mips::ZERO_64 },
+ { 1U, Mips::AT_64 },
+ { 2U, Mips::V0_64 },
+ { 3U, Mips::V1_64 },
+ { 4U, Mips::A0_64 },
+ { 5U, Mips::A1_64 },
+ { 6U, Mips::A2_64 },
+ { 7U, Mips::A3_64 },
+ { 8U, Mips::T0_64 },
+ { 9U, Mips::T1_64 },
+ { 10U, Mips::T2_64 },
+ { 11U, Mips::T3_64 },
+ { 12U, Mips::T4_64 },
+ { 13U, Mips::T5_64 },
+ { 14U, Mips::T6_64 },
+ { 15U, Mips::T7_64 },
+ { 16U, Mips::S0_64 },
+ { 17U, Mips::S1_64 },
+ { 18U, Mips::S2_64 },
+ { 19U, Mips::S3_64 },
+ { 20U, Mips::S4_64 },
+ { 21U, Mips::S5_64 },
+ { 22U, Mips::S6_64 },
+ { 23U, Mips::S7_64 },
+ { 24U, Mips::T8_64 },
+ { 25U, Mips::T9_64 },
+ { 26U, Mips::K0_64 },
+ { 27U, Mips::K1_64 },
+ { 28U, Mips::GP_64 },
+ { 29U, Mips::SP_64 },
+ { 30U, Mips::FP_64 },
+ { 31U, Mips::RA_64 },
+ { 32U, Mips::D0_64 },
+ { 33U, Mips::D1_64 },
+ { 34U, Mips::D2_64 },
+ { 35U, Mips::D3_64 },
+ { 36U, Mips::D4_64 },
+ { 37U, Mips::D5_64 },
+ { 38U, Mips::D6_64 },
+ { 39U, Mips::D7_64 },
+ { 40U, Mips::D8_64 },
+ { 41U, Mips::D9_64 },
+ { 42U, Mips::D10_64 },
+ { 43U, Mips::D11_64 },
+ { 44U, Mips::D12_64 },
+ { 45U, Mips::D13_64 },
+ { 46U, Mips::D14_64 },
+ { 47U, Mips::D15_64 },
+ { 48U, Mips::D16_64 },
+ { 49U, Mips::D17_64 },
+ { 50U, Mips::D18_64 },
+ { 51U, Mips::D19_64 },
+ { 52U, Mips::D20_64 },
+ { 53U, Mips::D21_64 },
+ { 54U, Mips::D22_64 },
+ { 55U, Mips::D23_64 },
+ { 56U, Mips::D24_64 },
+ { 57U, Mips::D25_64 },
+ { 58U, Mips::D26_64 },
+ { 59U, Mips::D27_64 },
+ { 60U, Mips::D28_64 },
+ { 61U, Mips::D29_64 },
+ { 62U, Mips::D30_64 },
+ { 63U, Mips::D31_64 },
+ { 64U, Mips::HI0 },
+ { 65U, Mips::LO0 },
+ { 176U, Mips::HI1 },
+ { 177U, Mips::LO1 },
+ { 178U, Mips::HI2 },
+ { 179U, Mips::LO2 },
+ { 180U, Mips::HI3 },
+ { 181U, Mips::LO3 },
+};
+extern const unsigned MipsEHFlavour0Dwarf2LSize = array_lengthof(MipsEHFlavour0Dwarf2L);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
+ { Mips::AT, 1U },
+ { Mips::FP, 30U },
+ { Mips::GP, 28U },
+ { Mips::RA, 31U },
+ { Mips::SP, 29U },
+ { Mips::ZERO, 0U },
+ { Mips::A0, 4U },
+ { Mips::A1, 5U },
+ { Mips::A2, 6U },
+ { Mips::A3, 7U },
+ { Mips::AT_64, 1U },
+ { Mips::F0, 32U },
+ { Mips::F1, 33U },
+ { Mips::F2, 34U },
+ { Mips::F3, 35U },
+ { Mips::F4, 36U },
+ { Mips::F5, 37U },
+ { Mips::F6, 38U },
+ { Mips::F7, 39U },
+ { Mips::F8, 40U },
+ { Mips::F9, 41U },
+ { Mips::F10, 42U },
+ { Mips::F11, 43U },
+ { Mips::F12, 44U },
+ { Mips::F13, 45U },
+ { Mips::F14, 46U },
+ { Mips::F15, 47U },
+ { Mips::F16, 48U },
+ { Mips::F17, 49U },
+ { Mips::F18, 50U },
+ { Mips::F19, 51U },
+ { Mips::F20, 52U },
+ { Mips::F21, 53U },
+ { Mips::F22, 54U },
+ { Mips::F23, 55U },
+ { Mips::F24, 56U },
+ { Mips::F25, 57U },
+ { Mips::F26, 58U },
+ { Mips::F27, 59U },
+ { Mips::F28, 60U },
+ { Mips::F29, 61U },
+ { Mips::F30, 62U },
+ { Mips::F31, 63U },
+ { Mips::FP_64, 30U },
+ { Mips::F_HI0, 32U },
+ { Mips::F_HI1, 33U },
+ { Mips::F_HI2, 34U },
+ { Mips::F_HI3, 35U },
+ { Mips::F_HI4, 36U },
+ { Mips::F_HI5, 37U },
+ { Mips::F_HI6, 38U },
+ { Mips::F_HI7, 39U },
+ { Mips::F_HI8, 40U },
+ { Mips::F_HI9, 41U },
+ { Mips::F_HI10, 42U },
+ { Mips::F_HI11, 43U },
+ { Mips::F_HI12, 44U },
+ { Mips::F_HI13, 45U },
+ { Mips::F_HI14, 46U },
+ { Mips::F_HI15, 47U },
+ { Mips::F_HI16, 48U },
+ { Mips::F_HI17, 49U },
+ { Mips::F_HI18, 50U },
+ { Mips::F_HI19, 51U },
+ { Mips::F_HI20, 52U },
+ { Mips::F_HI21, 53U },
+ { Mips::F_HI22, 54U },
+ { Mips::F_HI23, 55U },
+ { Mips::F_HI24, 56U },
+ { Mips::F_HI25, 57U },
+ { Mips::F_HI26, 58U },
+ { Mips::F_HI27, 59U },
+ { Mips::F_HI28, 60U },
+ { Mips::F_HI29, 61U },
+ { Mips::F_HI30, 62U },
+ { Mips::F_HI31, 63U },
+ { Mips::GP_64, 28U },
+ { Mips::HI0, 64U },
+ { Mips::HI1, 176U },
+ { Mips::HI2, 178U },
+ { Mips::HI3, 180U },
+ { Mips::K0, 26U },
+ { Mips::K1, 27U },
+ { Mips::LO0, 65U },
+ { Mips::LO1, 177U },
+ { Mips::LO2, 179U },
+ { Mips::LO3, 181U },
+ { Mips::RA_64, 31U },
+ { Mips::S0, 16U },
+ { Mips::S1, 17U },
+ { Mips::S2, 18U },
+ { Mips::S3, 19U },
+ { Mips::S4, 20U },
+ { Mips::S5, 21U },
+ { Mips::S6, 22U },
+ { Mips::S7, 23U },
+ { Mips::SP_64, 29U },
+ { Mips::T0, 8U },
+ { Mips::T1, 9U },
+ { Mips::T2, 10U },
+ { Mips::T3, 11U },
+ { Mips::T4, 12U },
+ { Mips::T5, 13U },
+ { Mips::T6, 14U },
+ { Mips::T7, 15U },
+ { Mips::T8, 24U },
+ { Mips::T9, 25U },
+ { Mips::V0, 2U },
+ { Mips::V1, 3U },
+ { Mips::W0, 32U },
+ { Mips::W1, 33U },
+ { Mips::W2, 34U },
+ { Mips::W3, 35U },
+ { Mips::W4, 36U },
+ { Mips::W5, 37U },
+ { Mips::W6, 38U },
+ { Mips::W7, 39U },
+ { Mips::W8, 40U },
+ { Mips::W9, 41U },
+ { Mips::W10, 42U },
+ { Mips::W11, 43U },
+ { Mips::W12, 44U },
+ { Mips::W13, 45U },
+ { Mips::W14, 46U },
+ { Mips::W15, 47U },
+ { Mips::W16, 48U },
+ { Mips::W17, 49U },
+ { Mips::W18, 50U },
+ { Mips::W19, 51U },
+ { Mips::W20, 52U },
+ { Mips::W21, 53U },
+ { Mips::W22, 54U },
+ { Mips::W23, 55U },
+ { Mips::W24, 56U },
+ { Mips::W25, 57U },
+ { Mips::W26, 58U },
+ { Mips::W27, 59U },
+ { Mips::W28, 60U },
+ { Mips::W29, 61U },
+ { Mips::W30, 62U },
+ { Mips::W31, 63U },
+ { Mips::ZERO_64, 0U },
+ { Mips::A0_64, 4U },
+ { Mips::A1_64, 5U },
+ { Mips::A2_64, 6U },
+ { Mips::A3_64, 7U },
+ { Mips::D0_64, 32U },
+ { Mips::D1_64, 33U },
+ { Mips::D2_64, 34U },
+ { Mips::D3_64, 35U },
+ { Mips::D4_64, 36U },
+ { Mips::D5_64, 37U },
+ { Mips::D6_64, 38U },
+ { Mips::D7_64, 39U },
+ { Mips::D8_64, 40U },
+ { Mips::D9_64, 41U },
+ { Mips::D10_64, 42U },
+ { Mips::D11_64, 43U },
+ { Mips::D12_64, 44U },
+ { Mips::D13_64, 45U },
+ { Mips::D14_64, 46U },
+ { Mips::D15_64, 47U },
+ { Mips::D16_64, 48U },
+ { Mips::D17_64, 49U },
+ { Mips::D18_64, 50U },
+ { Mips::D19_64, 51U },
+ { Mips::D20_64, 52U },
+ { Mips::D21_64, 53U },
+ { Mips::D22_64, 54U },
+ { Mips::D23_64, 55U },
+ { Mips::D24_64, 56U },
+ { Mips::D25_64, 57U },
+ { Mips::D26_64, 58U },
+ { Mips::D27_64, 59U },
+ { Mips::D28_64, 60U },
+ { Mips::D29_64, 61U },
+ { Mips::D30_64, 62U },
+ { Mips::D31_64, 63U },
+ { Mips::K0_64, 26U },
+ { Mips::K1_64, 27U },
+ { Mips::S0_64, 16U },
+ { Mips::S1_64, 17U },
+ { Mips::S2_64, 18U },
+ { Mips::S3_64, 19U },
+ { Mips::S4_64, 20U },
+ { Mips::S5_64, 21U },
+ { Mips::S6_64, 22U },
+ { Mips::S7_64, 23U },
+ { Mips::T0_64, 8U },
+ { Mips::T1_64, 9U },
+ { Mips::T2_64, 10U },
+ { Mips::T3_64, 11U },
+ { Mips::T4_64, 12U },
+ { Mips::T5_64, 13U },
+ { Mips::T6_64, 14U },
+ { Mips::T7_64, 15U },
+ { Mips::T8_64, 24U },
+ { Mips::T9_64, 25U },
+ { Mips::V0_64, 2U },
+ { Mips::V1_64, 3U },
+};
+extern const unsigned MipsDwarfFlavour0L2DwarfSize = array_lengthof(MipsDwarfFlavour0L2Dwarf);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
+ { Mips::AT, 1U },
+ { Mips::FP, 30U },
+ { Mips::GP, 28U },
+ { Mips::RA, 31U },
+ { Mips::SP, 29U },
+ { Mips::ZERO, 0U },
+ { Mips::A0, 4U },
+ { Mips::A1, 5U },
+ { Mips::A2, 6U },
+ { Mips::A3, 7U },
+ { Mips::AT_64, 1U },
+ { Mips::F0, 32U },
+ { Mips::F1, 33U },
+ { Mips::F2, 34U },
+ { Mips::F3, 35U },
+ { Mips::F4, 36U },
+ { Mips::F5, 37U },
+ { Mips::F6, 38U },
+ { Mips::F7, 39U },
+ { Mips::F8, 40U },
+ { Mips::F9, 41U },
+ { Mips::F10, 42U },
+ { Mips::F11, 43U },
+ { Mips::F12, 44U },
+ { Mips::F13, 45U },
+ { Mips::F14, 46U },
+ { Mips::F15, 47U },
+ { Mips::F16, 48U },
+ { Mips::F17, 49U },
+ { Mips::F18, 50U },
+ { Mips::F19, 51U },
+ { Mips::F20, 52U },
+ { Mips::F21, 53U },
+ { Mips::F22, 54U },
+ { Mips::F23, 55U },
+ { Mips::F24, 56U },
+ { Mips::F25, 57U },
+ { Mips::F26, 58U },
+ { Mips::F27, 59U },
+ { Mips::F28, 60U },
+ { Mips::F29, 61U },
+ { Mips::F30, 62U },
+ { Mips::F31, 63U },
+ { Mips::FP_64, 30U },
+ { Mips::F_HI0, 32U },
+ { Mips::F_HI1, 33U },
+ { Mips::F_HI2, 34U },
+ { Mips::F_HI3, 35U },
+ { Mips::F_HI4, 36U },
+ { Mips::F_HI5, 37U },
+ { Mips::F_HI6, 38U },
+ { Mips::F_HI7, 39U },
+ { Mips::F_HI8, 40U },
+ { Mips::F_HI9, 41U },
+ { Mips::F_HI10, 42U },
+ { Mips::F_HI11, 43U },
+ { Mips::F_HI12, 44U },
+ { Mips::F_HI13, 45U },
+ { Mips::F_HI14, 46U },
+ { Mips::F_HI15, 47U },
+ { Mips::F_HI16, 48U },
+ { Mips::F_HI17, 49U },
+ { Mips::F_HI18, 50U },
+ { Mips::F_HI19, 51U },
+ { Mips::F_HI20, 52U },
+ { Mips::F_HI21, 53U },
+ { Mips::F_HI22, 54U },
+ { Mips::F_HI23, 55U },
+ { Mips::F_HI24, 56U },
+ { Mips::F_HI25, 57U },
+ { Mips::F_HI26, 58U },
+ { Mips::F_HI27, 59U },
+ { Mips::F_HI28, 60U },
+ { Mips::F_HI29, 61U },
+ { Mips::F_HI30, 62U },
+ { Mips::F_HI31, 63U },
+ { Mips::GP_64, 28U },
+ { Mips::HI0, 64U },
+ { Mips::HI1, 176U },
+ { Mips::HI2, 178U },
+ { Mips::HI3, 180U },
+ { Mips::K0, 26U },
+ { Mips::K1, 27U },
+ { Mips::LO0, 65U },
+ { Mips::LO1, 177U },
+ { Mips::LO2, 179U },
+ { Mips::LO3, 181U },
+ { Mips::RA_64, 31U },
+ { Mips::S0, 16U },
+ { Mips::S1, 17U },
+ { Mips::S2, 18U },
+ { Mips::S3, 19U },
+ { Mips::S4, 20U },
+ { Mips::S5, 21U },
+ { Mips::S6, 22U },
+ { Mips::S7, 23U },
+ { Mips::SP_64, 29U },
+ { Mips::T0, 8U },
+ { Mips::T1, 9U },
+ { Mips::T2, 10U },
+ { Mips::T3, 11U },
+ { Mips::T4, 12U },
+ { Mips::T5, 13U },
+ { Mips::T6, 14U },
+ { Mips::T7, 15U },
+ { Mips::T8, 24U },
+ { Mips::T9, 25U },
+ { Mips::V0, 2U },
+ { Mips::V1, 3U },
+ { Mips::W0, 32U },
+ { Mips::W1, 33U },
+ { Mips::W2, 34U },
+ { Mips::W3, 35U },
+ { Mips::W4, 36U },
+ { Mips::W5, 37U },
+ { Mips::W6, 38U },
+ { Mips::W7, 39U },
+ { Mips::W8, 40U },
+ { Mips::W9, 41U },
+ { Mips::W10, 42U },
+ { Mips::W11, 43U },
+ { Mips::W12, 44U },
+ { Mips::W13, 45U },
+ { Mips::W14, 46U },
+ { Mips::W15, 47U },
+ { Mips::W16, 48U },
+ { Mips::W17, 49U },
+ { Mips::W18, 50U },
+ { Mips::W19, 51U },
+ { Mips::W20, 52U },
+ { Mips::W21, 53U },
+ { Mips::W22, 54U },
+ { Mips::W23, 55U },
+ { Mips::W24, 56U },
+ { Mips::W25, 57U },
+ { Mips::W26, 58U },
+ { Mips::W27, 59U },
+ { Mips::W28, 60U },
+ { Mips::W29, 61U },
+ { Mips::W30, 62U },
+ { Mips::W31, 63U },
+ { Mips::ZERO_64, 0U },
+ { Mips::A0_64, 4U },
+ { Mips::A1_64, 5U },
+ { Mips::A2_64, 6U },
+ { Mips::A3_64, 7U },
+ { Mips::D0_64, 32U },
+ { Mips::D1_64, 33U },
+ { Mips::D2_64, 34U },
+ { Mips::D3_64, 35U },
+ { Mips::D4_64, 36U },
+ { Mips::D5_64, 37U },
+ { Mips::D6_64, 38U },
+ { Mips::D7_64, 39U },
+ { Mips::D8_64, 40U },
+ { Mips::D9_64, 41U },
+ { Mips::D10_64, 42U },
+ { Mips::D11_64, 43U },
+ { Mips::D12_64, 44U },
+ { Mips::D13_64, 45U },
+ { Mips::D14_64, 46U },
+ { Mips::D15_64, 47U },
+ { Mips::D16_64, 48U },
+ { Mips::D17_64, 49U },
+ { Mips::D18_64, 50U },
+ { Mips::D19_64, 51U },
+ { Mips::D20_64, 52U },
+ { Mips::D21_64, 53U },
+ { Mips::D22_64, 54U },
+ { Mips::D23_64, 55U },
+ { Mips::D24_64, 56U },
+ { Mips::D25_64, 57U },
+ { Mips::D26_64, 58U },
+ { Mips::D27_64, 59U },
+ { Mips::D28_64, 60U },
+ { Mips::D29_64, 61U },
+ { Mips::D30_64, 62U },
+ { Mips::D31_64, 63U },
+ { Mips::K0_64, 26U },
+ { Mips::K1_64, 27U },
+ { Mips::S0_64, 16U },
+ { Mips::S1_64, 17U },
+ { Mips::S2_64, 18U },
+ { Mips::S3_64, 19U },
+ { Mips::S4_64, 20U },
+ { Mips::S5_64, 21U },
+ { Mips::S6_64, 22U },
+ { Mips::S7_64, 23U },
+ { Mips::T0_64, 8U },
+ { Mips::T1_64, 9U },
+ { Mips::T2_64, 10U },
+ { Mips::T3_64, 11U },
+ { Mips::T4_64, 12U },
+ { Mips::T5_64, 13U },
+ { Mips::T6_64, 14U },
+ { Mips::T7_64, 15U },
+ { Mips::T8_64, 24U },
+ { Mips::T9_64, 25U },
+ { Mips::V0_64, 2U },
+ { Mips::V1_64, 3U },
+};
+extern const unsigned MipsEHFlavour0L2DwarfSize = array_lengthof(MipsEHFlavour0L2Dwarf);
+
+extern const uint16_t MipsRegEncodingTable[] = {
+ 0,
+ 1,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 30,
+ 28,
+ 2,
+ 1,
+ 0,
+ 6,
+ 4,
+ 5,
+ 3,
+ 7,
+ 0,
+ 31,
+ 29,
+ 0,
+ 4,
+ 5,
+ 6,
+ 7,
+ 0,
+ 1,
+ 2,
+ 3,
+ 1,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 0,
+ 2,
+ 4,
+ 6,
+ 8,
+ 10,
+ 12,
+ 14,
+ 16,
+ 18,
+ 20,
+ 22,
+ 24,
+ 26,
+ 28,
+ 30,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 30,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 28,
+ 0,
+ 1,
+ 2,
+ 3,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 26,
+ 27,
+ 0,
+ 1,
+ 2,
+ 3,
+ 0,
+ 1,
+ 2,
+ 0,
+ 1,
+ 2,
+ 31,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 29,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 24,
+ 25,
+ 2,
+ 3,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 0,
+ 4,
+ 5,
+ 6,
+ 7,
+ 0,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 0,
+ 0,
+ 26,
+ 27,
+ 0,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 24,
+ 25,
+ 2,
+ 3,
+};
+static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
+ RI->InitMCRegisterInfo(MipsRegDesc, 418, RA, PC, MipsMCRegisterClasses, 73, MipsRegUnitRoots, 297, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
+MipsSubRegIdxRanges, MipsRegEncodingTable);
+
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
+ break;
+ }
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
+ break;
+ }
+}
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_MC_DESC
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Register Information Header Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_HEADER
+#undef GET_REGINFO_HEADER
+
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+namespace llvm {
+
+class MipsFrameLowering;
+
+struct MipsGenRegisterInfo : public TargetRegisterInfo {
+ explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
+ unsigned PC = 0, unsigned HwMode = 0);
+ unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
+ LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
+ LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
+ const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
+ const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
+ unsigned getRegUnitWeight(unsigned RegUnit) const override;
+ unsigned getNumRegPressureSets() const override;
+ const char *getRegPressureSetName(unsigned Idx) const override;
+ unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
+ const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
+ const int *getRegUnitPressureSets(unsigned RegUnit) const override;
+ ArrayRef<const char *> getRegMaskNames() const override;
+ ArrayRef<const uint32_t *> getRegMasks() const override;
+ /// Devirtualized TargetFrameLowering.
+ static const MipsFrameLowering *getFrameLowering(
+ const MachineFunction &MF);
+};
+
+namespace Mips { // Register classes
+ extern const TargetRegisterClass MSA128F16RegClass;
+ extern const TargetRegisterClass MSA128F16_with_sub_64_in_OddSPRegClass;
+ extern const TargetRegisterClass OddSPRegClass;
+ extern const TargetRegisterClass CCRRegClass;
+ extern const TargetRegisterClass COP0RegClass;
+ extern const TargetRegisterClass COP2RegClass;
+ extern const TargetRegisterClass COP3RegClass;
+ extern const TargetRegisterClass DSPRRegClass;
+ extern const TargetRegisterClass FGR32RegClass;
+ extern const TargetRegisterClass FGRCCRegClass;
+ extern const TargetRegisterClass FGRH32RegClass;
+ extern const TargetRegisterClass GPR32RegClass;
+ extern const TargetRegisterClass HWRegsRegClass;
+ extern const TargetRegisterClass GPR32NONZERORegClass;
+ extern const TargetRegisterClass OddSP_with_sub_hiRegClass;
+ extern const TargetRegisterClass FGR32_and_OddSPRegClass;
+ extern const TargetRegisterClass FGRH32_and_OddSPRegClass;
+ extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass;
+ extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
+ extern const TargetRegisterClass CPU16RegsRegClass;
+ extern const TargetRegisterClass FCCRegClass;
+ extern const TargetRegisterClass GPRMM16RegClass;
+ extern const TargetRegisterClass GPRMM16MovePRegClass;
+ extern const TargetRegisterClass GPRMM16ZeroRegClass;
+ extern const TargetRegisterClass MSACtrlRegClass;
+ extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass;
+ extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
+ extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
+ extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
+ extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
+ extern const TargetRegisterClass HI32DSPRegClass;
+ extern const TargetRegisterClass LO32DSPRegClass;
+ extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
+ extern const TargetRegisterClass CPURARegRegClass;
+ extern const TargetRegisterClass CPUSPRegRegClass;
+ extern const TargetRegisterClass DSPCCRegClass;
+ extern const TargetRegisterClass GP32RegClass;
+ extern const TargetRegisterClass GPR32ZERORegClass;
+ extern const TargetRegisterClass HI32RegClass;
+ extern const TargetRegisterClass LO32RegClass;
+ extern const TargetRegisterClass SP32RegClass;
+ extern const TargetRegisterClass FGR64RegClass;
+ extern const TargetRegisterClass GPR64RegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
+ extern const TargetRegisterClass AFGR64RegClass;
+ extern const TargetRegisterClass FGR64_and_OddSPRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
+ extern const TargetRegisterClass AFGR64_and_OddSPRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
+ extern const TargetRegisterClass ACC64DSPRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
+ extern const TargetRegisterClass OCTEON_MPLRegClass;
+ extern const TargetRegisterClass OCTEON_PRegClass;
+ extern const TargetRegisterClass ACC64RegClass;
+ extern const TargetRegisterClass GP64RegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
+ extern const TargetRegisterClass HI64RegClass;
+ extern const TargetRegisterClass LO64RegClass;
+ extern const TargetRegisterClass SP64RegClass;
+ extern const TargetRegisterClass MSA128BRegClass;
+ extern const TargetRegisterClass MSA128DRegClass;
+ extern const TargetRegisterClass MSA128HRegClass;
+ extern const TargetRegisterClass MSA128WRegClass;
+ extern const TargetRegisterClass MSA128B_with_sub_64_in_OddSPRegClass;
+ extern const TargetRegisterClass MSA128WEvensRegClass;
+ extern const TargetRegisterClass ACC128RegClass;
+} // end namespace Mips
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_HEADER
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Register and Register Classes Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_TARGET_DESC
+#undef GET_REGINFO_TARGET_DESC
+
+namespace llvm {
+
+extern const MCRegisterClass MipsMCRegisterClasses[];
+
+static const MVT::SimpleValueType VTLists[] = {
+ /* 0 */ MVT::i32, MVT::Other,
+ /* 2 */ MVT::i64, MVT::Other,
+ /* 4 */ MVT::f16, MVT::Other,
+ /* 6 */ MVT::f32, MVT::Other,
+ /* 8 */ MVT::f64, MVT::Other,
+ /* 10 */ MVT::v16i8, MVT::Other,
+ /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
+ /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
+ /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
+ /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
+ /* 24 */ MVT::Untyped, MVT::Other,
+};
+
+static const char *const SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };
+
+
+static const LaneBitmask SubRegIndexLaneMaskTable[] = {
+ LaneBitmask::getAll(),
+ LaneBitmask(0x00000001), // sub_32
+ LaneBitmask(0x00000041), // sub_64
+ LaneBitmask(0x00000002), // sub_dsp16_19
+ LaneBitmask(0x00000004), // sub_dsp20
+ LaneBitmask(0x00000008), // sub_dsp21
+ LaneBitmask(0x00000010), // sub_dsp22
+ LaneBitmask(0x00000020), // sub_dsp23
+ LaneBitmask(0x00000040), // sub_hi
+ LaneBitmask(0x00000001), // sub_lo
+ LaneBitmask(0x00000040), // sub_hi_then_sub_32
+ LaneBitmask(0x00000041), // sub_32_sub_hi_then_sub_32
+ };
+
+
+
+static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
+ // Mode = 0 (Default)
+ { 16, 16, 128, VTLists+4 }, // MSA128F16
+ { 16, 16, 128, VTLists+4 }, // MSA128F16_with_sub_64_in_OddSP
+ { 32, 32, 32, VTLists+6 }, // OddSP
+ { 32, 32, 32, VTLists+0 }, // CCR
+ { 32, 32, 32, VTLists+0 }, // COP0
+ { 32, 32, 32, VTLists+0 }, // COP2
+ { 32, 32, 32, VTLists+0 }, // COP3
+ { 32, 32, 32, VTLists+12 }, // DSPR
+ { 32, 32, 32, VTLists+6 }, // FGR32
+ { 32, 32, 32, VTLists+0 }, // FGRCC
+ { 32, 32, 32, VTLists+6 }, // FGRH32
+ { 32, 32, 32, VTLists+0 }, // GPR32
+ { 32, 32, 32, VTLists+0 }, // HWRegs
+ { 32, 32, 32, VTLists+0 }, // GPR32NONZERO
+ { 32, 32, 32, VTLists+6 }, // OddSP_with_sub_hi
+ { 32, 32, 32, VTLists+0 }, // FGR32_and_OddSP
+ { 32, 32, 32, VTLists+6 }, // FGRH32_and_OddSP
+ { 32, 32, 32, VTLists+6 }, // OddSP_with_sub_hi_with_sub_hi_in_FGRH32
+ { 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP
+ { 32, 32, 32, VTLists+0 }, // CPU16Regs
+ { 32, 32, 32, VTLists+0 }, // FCC
+ { 32, 32, 32, VTLists+0 }, // GPRMM16
+ { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP
+ { 32, 32, 32, VTLists+0 }, // GPRMM16Zero
+ { 32, 32, 32, VTLists+0 }, // MSACtrl
+ { 32, 32, 32, VTLists+6 }, // OddSP_with_sub_hi_with_sub_hi_in_FGR32
+ { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero
+ { 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP
+ { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP
+ { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero
+ { 32, 32, 32, VTLists+0 }, // HI32DSP
+ { 32, 32, 32, VTLists+0 }, // LO32DSP
+ { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
+ { 32, 32, 32, VTLists+0 }, // CPURAReg
+ { 32, 32, 32, VTLists+0 }, // CPUSPReg
+ { 32, 32, 32, VTLists+12 }, // DSPCC
+ { 32, 32, 32, VTLists+0 }, // GP32
+ { 32, 32, 32, VTLists+0 }, // GPR32ZERO
+ { 32, 32, 32, VTLists+0 }, // HI32
+ { 32, 32, 32, VTLists+0 }, // LO32
+ { 32, 32, 32, VTLists+0 }, // SP32
+ { 64, 64, 64, VTLists+8 }, // FGR64
+ { 64, 64, 64, VTLists+2 }, // GPR64
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO
+ { 64, 64, 64, VTLists+8 }, // AFGR64
+ { 64, 64, 64, VTLists+8 }, // FGR64_and_OddSP
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP
+ { 64, 64, 64, VTLists+8 }, // AFGR64_and_OddSP
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
+ { 64, 64, 64, VTLists+24 }, // ACC64DSP
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
+ { 64, 64, 64, VTLists+2 }, // OCTEON_MPL
+ { 64, 64, 64, VTLists+2 }, // OCTEON_P
+ { 64, 64, 64, VTLists+24 }, // ACC64
+ { 64, 64, 64, VTLists+2 }, // GP64
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg
+ { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO
+ { 64, 64, 64, VTLists+2 }, // HI64
+ { 64, 64, 64, VTLists+2 }, // LO64
+ { 64, 64, 64, VTLists+2 }, // SP64
+ { 128, 128, 128, VTLists+10 }, // MSA128B
+ { 128, 128, 128, VTLists+21 }, // MSA128D
+ { 128, 128, 128, VTLists+15 }, // MSA128H
+ { 128, 128, 128, VTLists+18 }, // MSA128W
+ { 128, 128, 128, VTLists+18 }, // MSA128B_with_sub_64_in_OddSP
+ { 128, 128, 128, VTLists+18 }, // MSA128WEvens
+ { 128, 128, 128, VTLists+24 }, // ACC128
+};
+
+static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
+
+static const uint32_t MSA128F16SubClassMask[] = {
+ 0x00000003, 0x00000000, 0x000000fc,
+};
+
+static const uint32_t MSA128F16_with_sub_64_in_OddSPSubClassMask[] = {
+ 0x00000002, 0x00000000, 0x00000040,
+};
+
+static const uint32_t OddSPSubClassMask[] = {
+ 0x0203c004, 0x0000a000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000040, // sub_64
+ 0x02024002, 0x0000b000, 0x00000040, // sub_hi
+ 0x00020002, 0x00002000, 0x00000040, // sub_lo
+};
+
+static const uint32_t CCRSubClassMask[] = {
+ 0x00000008, 0x00000000, 0x00000000,
+};
+
+static const uint32_t COP0SubClassMask[] = {
+ 0x00000010, 0x00000000, 0x00000000,
+};
+
+static const uint32_t COP2SubClassMask[] = {
+ 0x00000020, 0x00000000, 0x00000000,
+};
+
+static const uint32_t COP3SubClassMask[] = {
+ 0x00000040, 0x00000000, 0x00000000,
+};
+
+static const uint32_t DSPRSubClassMask[] = {
+ 0x3cec2880, 0x00000137, 0x00000000,
+ 0x00000000, 0x71df4c00, 0x00000002, // sub_32
+};
+
+static const uint32_t FGR32SubClassMask[] = {
+ 0x00008300, 0x00000000, 0x00000000,
+ 0x02000000, 0x00009000, 0x00000000, // sub_hi
+ 0x02024003, 0x0000b200, 0x000000fc, // sub_lo
+};
+
+static const uint32_t FGRCCSubClassMask[] = {
+ 0x00008300, 0x00000000, 0x00000000,
+ 0x02000000, 0x00009000, 0x00000000, // sub_hi
+ 0x02024003, 0x0000b200, 0x000000fc, // sub_lo
+};
+
+static const uint32_t FGRH32SubClassMask[] = {
+ 0x00010400, 0x00000000, 0x00000000,
+ 0x00020003, 0x00002200, 0x000000fc, // sub_hi
+};
+
+static const uint32_t GPR32SubClassMask[] = {
+ 0x3cec2800, 0x00000137, 0x00000000,
+ 0x00000000, 0x71df4c00, 0x00000002, // sub_32
+};
+
+static const uint32_t HWRegsSubClassMask[] = {
+ 0x00001000, 0x00000000, 0x00000000,
+};
+
+static const uint32_t GPR32NONZEROSubClassMask[] = {
+ 0x1c2c2000, 0x00000117, 0x00000000,
+ 0x00000000, 0x31594800, 0x00000002, // sub_32
+};
+
+static const uint32_t OddSP_with_sub_hiSubClassMask[] = {
+ 0x02024000, 0x0000a000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000040, // sub_64
+};
+
+static const uint32_t FGR32_and_OddSPSubClassMask[] = {
+ 0x00008000, 0x00000000, 0x00000000,
+ 0x02000000, 0x00009000, 0x00000000, // sub_hi
+ 0x00020002, 0x00002000, 0x00000040, // sub_lo
+};
+
+static const uint32_t FGRH32_and_OddSPSubClassMask[] = {
+ 0x00010000, 0x00000000, 0x00000000,
+ 0x00020002, 0x00002000, 0x00000040, // sub_hi
+};
+
+static const uint32_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32SubClassMask[] = {
+ 0x00020000, 0x00002000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000040, // sub_64
+};
+
+static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
+ 0x142c0000, 0x00000105, 0x00000000,
+ 0x00000000, 0x01494000, 0x00000002, // sub_32
+};
+
+static const uint32_t CPU16RegsSubClassMask[] = {
+ 0x14280000, 0x00000001, 0x00000000,
+ 0x00000000, 0x01490000, 0x00000000, // sub_32
+};
+
+static const uint32_t FCCSubClassMask[] = {
+ 0x00100000, 0x00000000, 0x00000000,
+};
+
+static const uint32_t GPRMM16SubClassMask[] = {
+ 0x14200000, 0x00000001, 0x00000000,
+ 0x00000000, 0x01490000, 0x00000000, // sub_32
+};
+
+static const uint32_t GPRMM16MovePSubClassMask[] = {
+ 0x38400000, 0x00000021, 0x00000000,
+ 0x00000000, 0x41d20000, 0x00000000, // sub_32
+};
+
+static const uint32_t GPRMM16ZeroSubClassMask[] = {
+ 0x24800000, 0x00000021, 0x00000000,
+ 0x00000000, 0x418c0000, 0x00000000, // sub_32
+};
+
+static const uint32_t MSACtrlSubClassMask[] = {
+ 0x01000000, 0x00000000, 0x00000000,
+};
+
+static const uint32_t OddSP_with_sub_hi_with_sub_hi_in_FGR32SubClassMask[] = {
+ 0x02000000, 0x00008000, 0x00000000,
+};
+
+static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
+ 0x04000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x01080000, 0x00000000, // sub_32
+};
+
+static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
+ 0x18000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x01500000, 0x00000000, // sub_32
+};
+
+static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
+ 0x10000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x01400000, 0x00000000, // sub_32
+};
+
+static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
+ 0x20000000, 0x00000021, 0x00000000,
+ 0x00000000, 0x41800000, 0x00000000, // sub_32
+};
+
+static const uint32_t HI32DSPSubClassMask[] = {
+ 0x40000000, 0x00000040, 0x00000000,
+ 0x00000000, 0x80000000, 0x00000000, // sub_32
+ 0x00000000, 0x08200000, 0x00000000, // sub_hi
+ 0x00000000, 0x00000000, 0x00000100, // sub_hi_then_sub_32
+};
+
+static const uint32_t LO32DSPSubClassMask[] = {
+ 0x80000000, 0x00000080, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000101, // sub_32
+ 0x00000000, 0x08200000, 0x00000000, // sub_lo
+};
+
+static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
+ 0x00000000, 0x00000001, 0x00000000,
+ 0x00000000, 0x01000000, 0x00000000, // sub_32
+};
+
+static const uint32_t CPURARegSubClassMask[] = {
+ 0x00000000, 0x00000002, 0x00000000,
+ 0x00000000, 0x20000000, 0x00000000, // sub_32
+};
+
+static const uint32_t CPUSPRegSubClassMask[] = {
+ 0x00000000, 0x00000104, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000002, // sub_32
+};
+
+static const uint32_t DSPCCSubClassMask[] = {
+ 0x00000000, 0x00000008, 0x00000000,
+};
+
+static const uint32_t GP32SubClassMask[] = {
+ 0x00000000, 0x00000010, 0x00000000,
+ 0x00000000, 0x10000000, 0x00000000, // sub_32
+};
+
+static const uint32_t GPR32ZEROSubClassMask[] = {
+ 0x00000000, 0x00000020, 0x00000000,
+ 0x00000000, 0x40000000, 0x00000000, // sub_32
+};
+
+static const uint32_t HI32SubClassMask[] = {
+ 0x00000000, 0x00000040, 0x00000000,
+ 0x00000000, 0x80000000, 0x00000000, // sub_32
+ 0x00000000, 0x08000000, 0x00000000, // sub_hi
+ 0x00000000, 0x00000000, 0x00000100, // sub_hi_then_sub_32
+};
+
+static const uint32_t LO32SubClassMask[] = {
+ 0x00000000, 0x00000080, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000101, // sub_32
+ 0x00000000, 0x08000000, 0x00000000, // sub_lo
+};
+
+static const uint32_t SP32SubClassMask[] = {
+ 0x00000000, 0x00000100, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000002, // sub_32
+};
+
+static const uint32_t FGR64SubClassMask[] = {
+ 0x00000000, 0x00002200, 0x00000000,
+ 0x00000003, 0x00000000, 0x000000fc, // sub_64
+};
+
+static const uint32_t GPR64SubClassMask[] = {
+ 0x00000000, 0x71df4c00, 0x00000002,
+};
+
+static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
+ 0x00000000, 0x31594800, 0x00000002,
+};
+
+static const uint32_t AFGR64SubClassMask[] = {
+ 0x00000000, 0x00009000, 0x00000000,
+};
+
+static const uint32_t FGR64_and_OddSPSubClassMask[] = {
+ 0x00000000, 0x00002000, 0x00000000,
+ 0x00000002, 0x00000000, 0x00000040, // sub_64
+};
+
+static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
+ 0x00000000, 0x01494000, 0x00000002,
+};
+
+static const uint32_t AFGR64_and_OddSPSubClassMask[] = {
+ 0x00000000, 0x00008000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
+ 0x00000000, 0x01490000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
+ 0x00000000, 0x41d20000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
+ 0x00000000, 0x418c0000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
+ 0x00000000, 0x01080000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
+ 0x00000000, 0x01500000, 0x00000000,
+};
+
+static const uint32_t ACC64DSPSubClassMask[] = {
+ 0x00000000, 0x08200000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000100, // sub_32_sub_hi_then_sub_32
+};
+
+static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
+ 0x00000000, 0x01400000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
+ 0x00000000, 0x41800000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
+ 0x00000000, 0x01000000, 0x00000000,
+};
+
+static const uint32_t OCTEON_MPLSubClassMask[] = {
+ 0x00000000, 0x02000000, 0x00000000,
+};
+
+static const uint32_t OCTEON_PSubClassMask[] = {
+ 0x00000000, 0x04000000, 0x00000000,
+};
+
+static const uint32_t ACC64SubClassMask[] = {
+ 0x00000000, 0x08000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000100, // sub_32_sub_hi_then_sub_32
+};
+
+static const uint32_t GP64SubClassMask[] = {
+ 0x00000000, 0x10000000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
+ 0x00000000, 0x20000000, 0x00000000,
+};
+
+static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
+ 0x00000000, 0x40000000, 0x00000000,
+};
+
+static const uint32_t HI64SubClassMask[] = {
+ 0x00000000, 0x80000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000100, // sub_hi
+};
+
+static const uint32_t LO64SubClassMask[] = {
+ 0x00000000, 0x00000000, 0x00000001,
+ 0x00000000, 0x00000000, 0x00000100, // sub_lo
+};
+
+static const uint32_t SP64SubClassMask[] = {
+ 0x00000000, 0x00000000, 0x00000002,
+};
+
+static const uint32_t MSA128BSubClassMask[] = {
+ 0x00000000, 0x00000000, 0x000000fc,
+};
+
+static const uint32_t MSA128DSubClassMask[] = {
+ 0x00000000, 0x00000000, 0x000000fc,
+};
+
+static const uint32_t MSA128HSubClassMask[] = {
+ 0x00000000, 0x00000000, 0x000000fc,
+};
+
+static const uint32_t MSA128WSubClassMask[] = {
+ 0x00000000, 0x00000000, 0x000000fc,
+};
+
+static const uint32_t MSA128B_with_sub_64_in_OddSPSubClassMask[] = {
+ 0x00000000, 0x00000000, 0x00000040,
+};
+
+static const uint32_t MSA128WEvensSubClassMask[] = {
+ 0x00000000, 0x00000000, 0x00000080,
+};
+
+static const uint32_t ACC128SubClassMask[] = {
+ 0x00000000, 0x00000000, 0x00000100,
+};
+
+static const uint16_t SuperRegIdxSeqs[] = {
+ /* 0 */ 1, 0,
+ /* 2 */ 2, 0,
+ /* 4 */ 8, 0,
+ /* 6 */ 1, 9, 0,
+ /* 9 */ 2, 8, 9, 0,
+ /* 13 */ 1, 8, 10, 0,
+ /* 17 */ 11, 0,
+};
+
+static const TargetRegisterClass *const MSA128F16_with_sub_64_in_OddSPSuperclasses[] = {
+ &Mips::MSA128F16RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const FGR32Superclasses[] = {
+ &Mips::FGRCCRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const FGRCCSuperclasses[] = {
+ &Mips::FGR32RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR32Superclasses[] = {
+ &Mips::DSPRRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const OddSP_with_sub_hiSuperclasses[] = {
+ &Mips::OddSPRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const FGR32_and_OddSPSuperclasses[] = {
+ &Mips::OddSPRegClass,
+ &Mips::FGR32RegClass,
+ &Mips::FGRCCRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const FGRH32_and_OddSPSuperclasses[] = {
+ &Mips::OddSPRegClass,
+ &Mips::FGRH32RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const OddSP_with_sub_hi_with_sub_hi_in_FGRH32Superclasses[] = {
+ &Mips::OddSPRegClass,
+ &Mips::OddSP_with_sub_hiRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::CPU16RegsPlusSPRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRMM16Superclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::CPU16RegsPlusSPRegClass,
+ &Mips::CPU16RegsRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const OddSP_with_sub_hi_with_sub_hi_in_FGR32Superclasses[] = {
+ &Mips::OddSPRegClass,
+ &Mips::OddSP_with_sub_hiRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::CPU16RegsPlusSPRegClass,
+ &Mips::CPU16RegsRegClass,
+ &Mips::GPRMM16RegClass,
+ &Mips::GPRMM16ZeroRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::GPRMM16MovePRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::CPU16RegsPlusSPRegClass,
+ &Mips::CPU16RegsRegClass,
+ &Mips::GPRMM16RegClass,
+ &Mips::GPRMM16MovePRegClass,
+ &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPRMM16MovePRegClass,
+ &Mips::GPRMM16ZeroRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::CPU16RegsPlusSPRegClass,
+ &Mips::CPU16RegsRegClass,
+ &Mips::GPRMM16RegClass,
+ &Mips::GPRMM16MovePRegClass,
+ &Mips::GPRMM16ZeroRegClass,
+ &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
+ &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
+ &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
+ &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const CPURARegSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::CPU16RegsPlusSPRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GP32Superclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPRMM16MovePRegClass,
+ &Mips::GPRMM16ZeroRegClass,
+ &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const HI32Superclasses[] = {
+ &Mips::HI32DSPRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const LO32Superclasses[] = {
+ &Mips::LO32DSPRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const SP32Superclasses[] = {
+ &Mips::DSPRRegClass,
+ &Mips::GPR32RegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::CPU16RegsPlusSPRegClass,
+ &Mips::CPUSPRegRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const FGR64_and_OddSPSuperclasses[] = {
+ &Mips::OddSPRegClass,
+ &Mips::OddSP_with_sub_hiRegClass,
+ &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass,
+ &Mips::FGR64RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const AFGR64_and_OddSPSuperclasses[] = {
+ &Mips::OddSPRegClass,
+ &Mips::OddSP_with_sub_hiRegClass,
+ &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass,
+ &Mips::AFGR64RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const ACC64Superclasses[] = {
+ &Mips::ACC64DSPRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GP64Superclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const SP64Superclasses[] = {
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const MSA128BSuperclasses[] = {
+ &Mips::MSA128F16RegClass,
+ &Mips::MSA128DRegClass,
+ &Mips::MSA128HRegClass,
+ &Mips::MSA128WRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const MSA128DSuperclasses[] = {
+ &Mips::MSA128F16RegClass,
+ &Mips::MSA128BRegClass,
+ &Mips::MSA128HRegClass,
+ &Mips::MSA128WRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const MSA128HSuperclasses[] = {
+ &Mips::MSA128F16RegClass,
+ &Mips::MSA128BRegClass,
+ &Mips::MSA128DRegClass,
+ &Mips::MSA128WRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const MSA128WSuperclasses[] = {
+ &Mips::MSA128F16RegClass,
+ &Mips::MSA128BRegClass,
+ &Mips::MSA128DRegClass,
+ &Mips::MSA128HRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const MSA128B_with_sub_64_in_OddSPSuperclasses[] = {
+ &Mips::MSA128F16RegClass,
+ &Mips::MSA128F16_with_sub_64_in_OddSPRegClass,
+ &Mips::MSA128BRegClass,
+ &Mips::MSA128DRegClass,
+ &Mips::MSA128HRegClass,
+ &Mips::MSA128WRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
+ &Mips::MSA128F16RegClass,
+ &Mips::MSA128BRegClass,
+ &Mips::MSA128DRegClass,
+ &Mips::MSA128HRegClass,
+ &Mips::MSA128WRegClass,
+ nullptr
+};
+
+
+namespace Mips { // Register class instances
+ extern const TargetRegisterClass MSA128F16RegClass = {
+ &MipsMCRegisterClasses[MSA128F16RegClassID],
+ MSA128F16SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass MSA128F16_with_sub_64_in_OddSPRegClass = {
+ &MipsMCRegisterClasses[MSA128F16_with_sub_64_in_OddSPRegClassID],
+ MSA128F16_with_sub_64_in_OddSPSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ MSA128F16_with_sub_64_in_OddSPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass OddSPRegClass = {
+ &MipsMCRegisterClasses[OddSPRegClassID],
+ OddSPSubClassMask,
+ SuperRegIdxSeqs + 9,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass CCRRegClass = {
+ &MipsMCRegisterClasses[CCRRegClassID],
+ CCRSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass COP0RegClass = {
+ &MipsMCRegisterClasses[COP0RegClassID],
+ COP0SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass COP2RegClass = {
+ &MipsMCRegisterClasses[COP2RegClassID],
+ COP2SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass COP3RegClass = {
+ &MipsMCRegisterClasses[COP3RegClassID],
+ COP3SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass DSPRRegClass = {
+ &MipsMCRegisterClasses[DSPRRegClassID],
+ DSPRSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FGR32RegClass = {
+ &MipsMCRegisterClasses[FGR32RegClassID],
+ FGR32SubClassMask,
+ SuperRegIdxSeqs + 10,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ FGR32Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FGRCCRegClass = {
+ &MipsMCRegisterClasses[FGRCCRegClassID],
+ FGRCCSubClassMask,
+ SuperRegIdxSeqs + 10,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ FGRCCSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FGRH32RegClass = {
+ &MipsMCRegisterClasses[FGRH32RegClassID],
+ FGRH32SubClassMask,
+ SuperRegIdxSeqs + 4,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR32RegClass = {
+ &MipsMCRegisterClasses[GPR32RegClassID],
+ GPR32SubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR32Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass HWRegsRegClass = {
+ &MipsMCRegisterClasses[HWRegsRegClassID],
+ HWRegsSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR32NONZERORegClass = {
+ &MipsMCRegisterClasses[GPR32NONZERORegClassID],
+ GPR32NONZEROSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR32NONZEROSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass OddSP_with_sub_hiRegClass = {
+ &MipsMCRegisterClasses[OddSP_with_sub_hiRegClassID],
+ OddSP_with_sub_hiSubClassMask,
+ SuperRegIdxSeqs + 2,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ OddSP_with_sub_hiSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FGR32_and_OddSPRegClass = {
+ &MipsMCRegisterClasses[FGR32_and_OddSPRegClassID],
+ FGR32_and_OddSPSubClassMask,
+ SuperRegIdxSeqs + 10,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ FGR32_and_OddSPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FGRH32_and_OddSPRegClass = {
+ &MipsMCRegisterClasses[FGRH32_and_OddSPRegClassID],
+ FGRH32_and_OddSPSubClassMask,
+ SuperRegIdxSeqs + 4,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ FGRH32_and_OddSPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass = {
+ &MipsMCRegisterClasses[OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID],
+ OddSP_with_sub_hi_with_sub_hi_in_FGRH32SubClassMask,
+ SuperRegIdxSeqs + 2,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ OddSP_with_sub_hi_with_sub_hi_in_FGRH32Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
+ &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
+ CPU16RegsPlusSPSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ CPU16RegsPlusSPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass CPU16RegsRegClass = {
+ &MipsMCRegisterClasses[CPU16RegsRegClassID],
+ CPU16RegsSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ CPU16RegsSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FCCRegClass = {
+ &MipsMCRegisterClasses[FCCRegClassID],
+ FCCSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRMM16RegClass = {
+ &MipsMCRegisterClasses[GPRMM16RegClassID],
+ GPRMM16SubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRMM16Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRMM16MovePRegClass = {
+ &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
+ GPRMM16MovePSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRMM16MovePSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRMM16ZeroRegClass = {
+ &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
+ GPRMM16ZeroSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRMM16ZeroSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass MSACtrlRegClass = {
+ &MipsMCRegisterClasses[MSACtrlRegClassID],
+ MSACtrlSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass = {
+ &MipsMCRegisterClasses[OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID],
+ OddSP_with_sub_hi_with_sub_hi_in_FGR32SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ OddSP_with_sub_hi_with_sub_hi_in_FGR32Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
+ &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
+ CPU16Regs_and_GPRMM16ZeroSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ CPU16Regs_and_GPRMM16ZeroSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
+ &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
+ GPR32NONZERO_and_GPRMM16MovePSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR32NONZERO_and_GPRMM16MovePSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
+ &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
+ CPU16Regs_and_GPRMM16MovePSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ CPU16Regs_and_GPRMM16MovePSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
+ &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
+ GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass HI32DSPRegClass = {
+ &MipsMCRegisterClasses[HI32DSPRegClassID],
+ HI32DSPSubClassMask,
+ SuperRegIdxSeqs + 13,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass LO32DSPRegClass = {
+ &MipsMCRegisterClasses[LO32DSPRegClassID],
+ LO32DSPSubClassMask,
+ SuperRegIdxSeqs + 6,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
+ &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
+ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass CPURARegRegClass = {
+ &MipsMCRegisterClasses[CPURARegRegClassID],
+ CPURARegSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ CPURARegSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass CPUSPRegRegClass = {
+ &MipsMCRegisterClasses[CPUSPRegRegClassID],
+ CPUSPRegSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ CPUSPRegSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass DSPCCRegClass = {
+ &MipsMCRegisterClasses[DSPCCRegClassID],
+ DSPCCSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GP32RegClass = {
+ &MipsMCRegisterClasses[GP32RegClassID],
+ GP32SubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GP32Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR32ZERORegClass = {
+ &MipsMCRegisterClasses[GPR32ZERORegClassID],
+ GPR32ZEROSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR32ZEROSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass HI32RegClass = {
+ &MipsMCRegisterClasses[HI32RegClassID],
+ HI32SubClassMask,
+ SuperRegIdxSeqs + 13,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ HI32Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass LO32RegClass = {
+ &MipsMCRegisterClasses[LO32RegClassID],
+ LO32SubClassMask,
+ SuperRegIdxSeqs + 6,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ LO32Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass SP32RegClass = {
+ &MipsMCRegisterClasses[SP32RegClassID],
+ SP32SubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ SP32Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FGR64RegClass = {
+ &MipsMCRegisterClasses[FGR64RegClassID],
+ FGR64SubClassMask,
+ SuperRegIdxSeqs + 2,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64RegClass = {
+ &MipsMCRegisterClasses[GPR64RegClassID],
+ GPR64SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
+ GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass AFGR64RegClass = {
+ &MipsMCRegisterClasses[AFGR64RegClassID],
+ AFGR64SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FGR64_and_OddSPRegClass = {
+ &MipsMCRegisterClasses[FGR64_and_OddSPRegClassID],
+ FGR64_and_OddSPSubClassMask,
+ SuperRegIdxSeqs + 2,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ FGR64_and_OddSPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
+ GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass AFGR64_and_OddSPRegClass = {
+ &MipsMCRegisterClasses[AFGR64_and_OddSPRegClassID],
+ AFGR64_and_OddSPSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ AFGR64_and_OddSPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
+ GPR64_with_sub_32_in_CPU16RegsSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_CPU16RegsSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
+ GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
+ GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
+ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
+ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass ACC64DSPRegClass = {
+ &MipsMCRegisterClasses[ACC64DSPRegClassID],
+ ACC64DSPSubClassMask,
+ SuperRegIdxSeqs + 17,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
+ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
+ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
+ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass OCTEON_MPLRegClass = {
+ &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
+ OCTEON_MPLSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass OCTEON_PRegClass = {
+ &MipsMCRegisterClasses[OCTEON_PRegClassID],
+ OCTEON_PSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass ACC64RegClass = {
+ &MipsMCRegisterClasses[ACC64RegClassID],
+ ACC64SubClassMask,
+ SuperRegIdxSeqs + 17,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ ACC64Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GP64RegClass = {
+ &MipsMCRegisterClasses[GP64RegClassID],
+ GP64SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GP64Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
+ GPR64_with_sub_32_in_CPURARegSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_CPURARegSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
+ &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
+ GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPR64_with_sub_32_in_GPR32ZEROSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass HI64RegClass = {
+ &MipsMCRegisterClasses[HI64RegClassID],
+ HI64SubClassMask,
+ SuperRegIdxSeqs + 4,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass LO64RegClass = {
+ &MipsMCRegisterClasses[LO64RegClassID],
+ LO64SubClassMask,
+ SuperRegIdxSeqs + 7,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass SP64RegClass = {
+ &MipsMCRegisterClasses[SP64RegClassID],
+ SP64SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ SP64Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass MSA128BRegClass = {
+ &MipsMCRegisterClasses[MSA128BRegClassID],
+ MSA128BSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ MSA128BSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass MSA128DRegClass = {
+ &MipsMCRegisterClasses[MSA128DRegClassID],
+ MSA128DSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ MSA128DSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass MSA128HRegClass = {
+ &MipsMCRegisterClasses[MSA128HRegClassID],
+ MSA128HSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ MSA128HSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass MSA128WRegClass = {
+ &MipsMCRegisterClasses[MSA128WRegClassID],
+ MSA128WSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ MSA128WSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass MSA128B_with_sub_64_in_OddSPRegClass = {
+ &MipsMCRegisterClasses[MSA128B_with_sub_64_in_OddSPRegClassID],
+ MSA128B_with_sub_64_in_OddSPSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ MSA128B_with_sub_64_in_OddSPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass MSA128WEvensRegClass = {
+ &MipsMCRegisterClasses[MSA128WEvensRegClassID],
+ MSA128WEvensSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ MSA128WEvensSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass ACC128RegClass = {
+ &MipsMCRegisterClasses[ACC128RegClassID],
+ ACC128SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000041),
+ 0,
+ true, /* HasDisjunctSubRegs */
+ true, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+} // end namespace Mips
+
+namespace {
+ const TargetRegisterClass* const RegisterClasses[] = {
+ &Mips::MSA128F16RegClass,
+ &Mips::MSA128F16_with_sub_64_in_OddSPRegClass,
+ &Mips::OddSPRegClass,
+ &Mips::CCRRegClass,
+ &Mips::COP0RegClass,
+ &Mips::COP2RegClass,
+ &Mips::COP3RegClass,
+ &Mips::DSPRRegClass,
+ &Mips::FGR32RegClass,
+ &Mips::FGRCCRegClass,
+ &Mips::FGRH32RegClass,
+ &Mips::GPR32RegClass,
+ &Mips::HWRegsRegClass,
+ &Mips::GPR32NONZERORegClass,
+ &Mips::OddSP_with_sub_hiRegClass,
+ &Mips::FGR32_and_OddSPRegClass,
+ &Mips::FGRH32_and_OddSPRegClass,
+ &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass,
+ &Mips::CPU16RegsPlusSPRegClass,
+ &Mips::CPU16RegsRegClass,
+ &Mips::FCCRegClass,
+ &Mips::GPRMM16RegClass,
+ &Mips::GPRMM16MovePRegClass,
+ &Mips::GPRMM16ZeroRegClass,
+ &Mips::MSACtrlRegClass,
+ &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass,
+ &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
+ &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
+ &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
+ &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
+ &Mips::HI32DSPRegClass,
+ &Mips::LO32DSPRegClass,
+ &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
+ &Mips::CPURARegRegClass,
+ &Mips::CPUSPRegRegClass,
+ &Mips::DSPCCRegClass,
+ &Mips::GP32RegClass,
+ &Mips::GPR32ZERORegClass,
+ &Mips::HI32RegClass,
+ &Mips::LO32RegClass,
+ &Mips::SP32RegClass,
+ &Mips::FGR64RegClass,
+ &Mips::GPR64RegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
+ &Mips::AFGR64RegClass,
+ &Mips::FGR64_and_OddSPRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
+ &Mips::AFGR64_and_OddSPRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
+ &Mips::ACC64DSPRegClass,
+ &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
+ &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
+ &Mips::OCTEON_MPLRegClass,
+ &Mips::OCTEON_PRegClass,
+ &Mips::ACC64RegClass,
+ &Mips::GP64RegClass,
+ &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
+ &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
+ &Mips::HI64RegClass,
+ &Mips::LO64RegClass,
+ &Mips::SP64RegClass,
+ &Mips::MSA128BRegClass,
+ &Mips::MSA128DRegClass,
+ &Mips::MSA128HRegClass,
+ &Mips::MSA128WRegClass,
+ &Mips::MSA128B_with_sub_64_in_OddSPRegClass,
+ &Mips::MSA128WEvensRegClass,
+ &Mips::ACC128RegClass,
+ };
+} // end anonymous namespace
+
+static const TargetRegisterInfoDesc MipsRegInfoDesc[] = { // Extra Descriptors
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, true },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, false },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+};
+unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
+ static const uint8_t RowMap[11] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
+ };
+ static const uint8_t Rows[2][11] = {
+ { 10, 0, 0, 0, 0, 0, 0, 8, 9, 0, 0, },
+ { 1, 0, 0, 0, 0, 0, 0, 10, 1, 0, 0, },
+ };
+
+ --IdxA; assert(IdxA < 11);
+ --IdxB; assert(IdxB < 11);
+ return Rows[RowMap[IdxA]][IdxB];
+}
+
+ struct MaskRolOp {
+ LaneBitmask Mask;
+ uint8_t RotateLeft;
+ };
+ static const MaskRolOp LaneMaskComposeSequences[] = {
+ { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
+ { LaneBitmask(0xFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
+ { LaneBitmask(0xFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
+ { LaneBitmask(0xFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
+ { LaneBitmask(0xFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
+ { LaneBitmask(0xFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
+ { LaneBitmask(0xFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12
+ };
+ static const MaskRolOp *const CompositeSequences[] = {
+ &LaneMaskComposeSequences[0], // to sub_32
+ &LaneMaskComposeSequences[0], // to sub_64
+ &LaneMaskComposeSequences[2], // to sub_dsp16_19
+ &LaneMaskComposeSequences[4], // to sub_dsp20
+ &LaneMaskComposeSequences[6], // to sub_dsp21
+ &LaneMaskComposeSequences[8], // to sub_dsp22
+ &LaneMaskComposeSequences[10], // to sub_dsp23
+ &LaneMaskComposeSequences[12], // to sub_hi
+ &LaneMaskComposeSequences[0], // to sub_lo
+ &LaneMaskComposeSequences[12], // to sub_hi_then_sub_32
+ &LaneMaskComposeSequences[0] // to sub_32_sub_hi_then_sub_32
+ };
+
+LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
+ --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
+ LaneBitmask Result;
+ for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
+ LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
+ if (unsigned S = Ops->RotateLeft)
+ Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
+ else
+ Result |= LaneBitmask(M);
+ }
+ return Result;
+}
+
+LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
+ LaneMask &= getSubRegIndexLaneMask(IdxA);
+ --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
+ LaneBitmask Result;
+ for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
+ LaneBitmask::Type M = LaneMask.getAsInteger();
+ if (unsigned S = Ops->RotateLeft)
+ Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
+ else
+ Result |= LaneBitmask(M);
+ }
+ return Result;
+}
+
+const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
+ static const uint8_t Table[73][11] = {
+ { // MSA128F16
+ 0, // sub_32
+ 1, // sub_64 -> MSA128F16
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 1, // sub_hi -> MSA128F16
+ 1, // sub_lo -> MSA128F16
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // MSA128F16_with_sub_64_in_OddSP
+ 0, // sub_32
+ 2, // sub_64 -> MSA128F16_with_sub_64_in_OddSP
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 2, // sub_hi -> MSA128F16_with_sub_64_in_OddSP
+ 2, // sub_lo -> MSA128F16_with_sub_64_in_OddSP
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // OddSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 15, // sub_hi -> OddSP_with_sub_hi
+ 15, // sub_lo -> OddSP_with_sub_hi
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // CCR
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // COP0
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // COP2
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // COP3
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // DSPR
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // FGR32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // FGRCC
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // FGRH32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // HWRegs
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR32NONZERO
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // OddSP_with_sub_hi
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 15, // sub_hi -> OddSP_with_sub_hi
+ 15, // sub_lo -> OddSP_with_sub_hi
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // FGR32_and_OddSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // FGRH32_and_OddSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // OddSP_with_sub_hi_with_sub_hi_in_FGRH32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 18, // sub_hi -> OddSP_with_sub_hi_with_sub_hi_in_FGRH32
+ 18, // sub_lo -> OddSP_with_sub_hi_with_sub_hi_in_FGRH32
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // CPU16RegsPlusSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // CPU16Regs
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // FCC
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPRMM16
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPRMM16MoveP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPRMM16Zero
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // MSACtrl
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // OddSP_with_sub_hi_with_sub_hi_in_FGR32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 26, // sub_hi -> OddSP_with_sub_hi_with_sub_hi_in_FGR32
+ 26, // sub_lo -> OddSP_with_sub_hi_with_sub_hi_in_FGR32
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // CPU16Regs_and_GPRMM16Zero
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR32NONZERO_and_GPRMM16MoveP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // CPU16Regs_and_GPRMM16MoveP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPRMM16MoveP_and_GPRMM16Zero
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // HI32DSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // LO32DSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // CPURAReg
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // CPUSPReg
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // DSPCC
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GP32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR32ZERO
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // HI32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // LO32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // SP32
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // FGR64
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 42, // sub_hi -> FGR64
+ 42, // sub_lo -> FGR64
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64
+ 43, // sub_32 -> GPR64
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_GPR32NONZERO
+ 44, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // AFGR64
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 45, // sub_hi -> AFGR64
+ 45, // sub_lo -> AFGR64
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // FGR64_and_OddSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 46, // sub_hi -> FGR64_and_OddSP
+ 46, // sub_lo -> FGR64_and_OddSP
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_CPU16RegsPlusSP
+ 47, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // AFGR64_and_OddSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 48, // sub_hi -> AFGR64_and_OddSP
+ 48, // sub_lo -> AFGR64_and_OddSP
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_CPU16Regs
+ 49, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_GPRMM16MoveP
+ 50, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_GPRMM16Zero
+ 51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
+ 52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
+ 53, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // ACC64DSP
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 54, // sub_hi -> ACC64DSP
+ 54, // sub_lo -> ACC64DSP
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
+ 55, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
+ 56, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
+ 57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // OCTEON_MPL
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // OCTEON_P
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // ACC64
+ 0, // sub_32
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 60, // sub_hi -> ACC64
+ 60, // sub_lo -> ACC64
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GP64
+ 61, // sub_32 -> GP64
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_CPURAReg
+ 62, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // GPR64_with_sub_32_in_GPR32ZERO
+ 63, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // HI64
+ 64, // sub_32 -> HI64
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // LO64
+ 65, // sub_32 -> LO64
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // SP64
+ 66, // sub_32 -> SP64
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 0, // sub_hi
+ 0, // sub_lo
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // MSA128B
+ 0, // sub_32
+ 67, // sub_64 -> MSA128B
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 67, // sub_hi -> MSA128B
+ 67, // sub_lo -> MSA128B
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // MSA128D
+ 0, // sub_32
+ 68, // sub_64 -> MSA128D
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 68, // sub_hi -> MSA128D
+ 68, // sub_lo -> MSA128D
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // MSA128H
+ 0, // sub_32
+ 69, // sub_64 -> MSA128H
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 69, // sub_hi -> MSA128H
+ 69, // sub_lo -> MSA128H
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // MSA128W
+ 0, // sub_32
+ 70, // sub_64 -> MSA128W
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 70, // sub_hi -> MSA128W
+ 70, // sub_lo -> MSA128W
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // MSA128B_with_sub_64_in_OddSP
+ 0, // sub_32
+ 71, // sub_64 -> MSA128B_with_sub_64_in_OddSP
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 71, // sub_hi -> MSA128B_with_sub_64_in_OddSP
+ 71, // sub_lo -> MSA128B_with_sub_64_in_OddSP
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // MSA128WEvens
+ 0, // sub_32
+ 72, // sub_64 -> MSA128WEvens
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 72, // sub_hi -> MSA128WEvens
+ 72, // sub_lo -> MSA128WEvens
+ 0, // sub_hi_then_sub_32
+ 0, // sub_32_sub_hi_then_sub_32
+ },
+ { // ACC128
+ 73, // sub_32 -> ACC128
+ 0, // sub_64
+ 0, // sub_dsp16_19
+ 0, // sub_dsp20
+ 0, // sub_dsp21
+ 0, // sub_dsp22
+ 0, // sub_dsp23
+ 73, // sub_hi -> ACC128
+ 73, // sub_lo -> ACC128
+ 73, // sub_hi_then_sub_32 -> ACC128
+ 73, // sub_32_sub_hi_then_sub_32 -> ACC128
+ },
+ };
+ assert(RC && "Missing regclass");
+ if (!Idx) return RC;
+ --Idx;
+ assert(Idx < 11 && "Bad subreg");
+ unsigned TV = Table[RC->getID()][Idx];
+ return TV ? getRegClass(TV - 1) : nullptr;
+}
+
+/// Get the weight in units of pressure for this register class.
+const RegClassWeight &MipsGenRegisterInfo::
+getRegClassWeight(const TargetRegisterClass *RC) const {
+ static const RegClassWeight RCWeightTable[] = {
+ {2, 64}, // MSA128F16
+ {2, 32}, // MSA128F16_with_sub_64_in_OddSP
+ {2, 40}, // OddSP
+ {0, 0}, // CCR
+ {0, 0}, // COP0
+ {0, 0}, // COP2
+ {0, 0}, // COP3
+ {1, 32}, // DSPR
+ {1, 32}, // FGR32
+ {1, 32}, // FGRCC
+ {1, 32}, // FGRH32
+ {1, 32}, // GPR32
+ {0, 0}, // HWRegs
+ {1, 31}, // GPR32NONZERO
+ {2, 40}, // OddSP_with_sub_hi
+ {1, 16}, // FGR32_and_OddSP
+ {1, 16}, // FGRH32_and_OddSP
+ {2, 32}, // OddSP_with_sub_hi_with_sub_hi_in_FGRH32
+ {1, 9}, // CPU16RegsPlusSP
+ {1, 8}, // CPU16Regs
+ {0, 0}, // FCC
+ {1, 8}, // GPRMM16
+ {1, 8}, // GPRMM16MoveP
+ {1, 8}, // GPRMM16Zero
+ {1, 8}, // MSACtrl
+ {2, 16}, // OddSP_with_sub_hi_with_sub_hi_in_FGR32
+ {1, 7}, // CPU16Regs_and_GPRMM16Zero
+ {1, 7}, // GPR32NONZERO_and_GPRMM16MoveP
+ {1, 4}, // CPU16Regs_and_GPRMM16MoveP
+ {1, 4}, // GPRMM16MoveP_and_GPRMM16Zero
+ {1, 4}, // HI32DSP
+ {1, 4}, // LO32DSP
+ {1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
+ {1, 1}, // CPURAReg
+ {1, 1}, // CPUSPReg
+ {1, 1}, // DSPCC
+ {1, 1}, // GP32
+ {1, 1}, // GPR32ZERO
+ {1, 1}, // HI32
+ {1, 1}, // LO32
+ {1, 1}, // SP32
+ {2, 64}, // FGR64
+ {1, 32}, // GPR64
+ {1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO
+ {2, 32}, // AFGR64
+ {2, 32}, // FGR64_and_OddSP
+ {1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP
+ {2, 16}, // AFGR64_and_OddSP
+ {1, 8}, // GPR64_with_sub_32_in_CPU16Regs
+ {1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP
+ {1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero
+ {1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
+ {1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
+ {2, 8}, // ACC64DSP
+ {1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
+ {1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
+ {1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
+ {0, 0}, // OCTEON_MPL
+ {0, 0}, // OCTEON_P
+ {2, 2}, // ACC64
+ {1, 1}, // GP64
+ {1, 1}, // GPR64_with_sub_32_in_CPURAReg
+ {1, 1}, // GPR64_with_sub_32_in_GPR32ZERO
+ {1, 1}, // HI64
+ {1, 1}, // LO64
+ {1, 1}, // SP64
+ {2, 64}, // MSA128B
+ {2, 64}, // MSA128D
+ {2, 64}, // MSA128H
+ {2, 64}, // MSA128W
+ {2, 32}, // MSA128B_with_sub_64_in_OddSP
+ {2, 32}, // MSA128WEvens
+ {2, 2}, // ACC128
+ };
+ return RCWeightTable[RC->getID()];
+}
+
+/// Get the weight in units of pressure for this register unit.
+unsigned MipsGenRegisterInfo::
+getRegUnitWeight(unsigned RegUnit) const {
+ assert(RegUnit < 297 && "invalid register unit");
+ // All register units have unit weight.
+ return 1;
+}
+
+
+// Get the number of dimensions of register pressure.
+unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
+ return 24;
+}
+
+// Get the name of this register unit pressure set.
+const char *MipsGenRegisterInfo::
+getRegPressureSetName(unsigned Idx) const {
+ static const char *const PressureNameTable[] = {
+ "DSPCC",
+ "GPR32ZERO",
+ "GPR64_with_sub_32_in_CPURAReg",
+ "HI32",
+ "CPU16Regs_and_GPRMM16MoveP",
+ "HI32DSP",
+ "LO32DSP",
+ "GPRMM16MoveP",
+ "MSACtrl",
+ "ACC64DSP",
+ "CPU16Regs",
+ "CPU16Regs+GPRMM16MoveP",
+ "FGR32_and_OddSP",
+ "AFGR64_and_OddSP",
+ "FGR32_and_OddSP+AFGR64_and_OddSP",
+ "MSA128F16_with_sub_64_in_OddSP",
+ "DSPR",
+ "FGR32",
+ "MSA128WEvens",
+ "MSA128F16_with_sub_64_in_OddSP+AFGR64_and_OddSP",
+ "AFGR64_and_OddSP+MSA128WEvens",
+ "MSA128F16_with_sub_64_in_OddSP+FGR32",
+ "FGR32+MSA128WEvens",
+ "MSA128F16",
+ };
+ return PressureNameTable[Idx];
+}
+
+// Get the register unit pressure limit for this dimension.
+// This limit must be adjusted dynamically for reserved registers.
+unsigned MipsGenRegisterInfo::
+getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
+ static const uint8_t PressureLimitTable[] = {
+ 1, // 0: DSPCC
+ 1, // 1: GPR32ZERO
+ 1, // 2: GPR64_with_sub_32_in_CPURAReg
+ 2, // 3: HI32
+ 5, // 4: CPU16Regs_and_GPRMM16MoveP
+ 5, // 5: HI32DSP
+ 5, // 6: LO32DSP
+ 8, // 7: GPRMM16MoveP
+ 8, // 8: MSACtrl
+ 8, // 9: ACC64DSP
+ 10, // 10: CPU16Regs
+ 13, // 11: CPU16Regs+GPRMM16MoveP
+ 16, // 12: FGR32_and_OddSP
+ 16, // 13: AFGR64_and_OddSP
+ 24, // 14: FGR32_and_OddSP+AFGR64_and_OddSP
+ 32, // 15: MSA128F16_with_sub_64_in_OddSP
+ 32, // 16: DSPR
+ 32, // 17: FGR32
+ 32, // 18: MSA128WEvens
+ 40, // 19: MSA128F16_with_sub_64_in_OddSP+AFGR64_and_OddSP
+ 40, // 20: AFGR64_and_OddSP+MSA128WEvens
+ 48, // 21: MSA128F16_with_sub_64_in_OddSP+FGR32
+ 48, // 22: FGR32+MSA128WEvens
+ 64, // 23: MSA128F16
+ };
+ return PressureLimitTable[Idx];
+}
+
+/// Table of pressure sets per register class or unit.
+static const int RCSetsTable[] = {
+ /* 0 */ 0, -1,
+ /* 2 */ 8, -1,
+ /* 4 */ 5, 9, -1,
+ /* 7 */ 3, 5, 6, 9, -1,
+ /* 12 */ 2, 16, -1,
+ /* 15 */ 7, 11, 16, -1,
+ /* 19 */ 1, 4, 7, 10, 11, 16, -1,
+ /* 26 */ 15, 19, 21, 23, -1,
+ /* 31 */ 18, 20, 22, 23, -1,
+ /* 36 */ 17, 21, 22, 23, -1,
+ /* 41 */ 12, 14, 15, 17, 19, 21, 22, 23, -1,
+ /* 50 */ 17, 18, 20, 21, 22, 23, -1,
+ /* 57 */ 13, 14, 17, 19, 20, 21, 22, 23, -1,
+ /* 66 */ 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, -1,
+ /* 77 */ 13, 14, 17, 18, 19, 20, 21, 22, 23, -1,
+};
+
+/// Get the dimensions of register pressure impacted by this register class.
+/// Returns a -1 terminated array of pressure set IDs
+const int* MipsGenRegisterInfo::
+getRegClassPressureSets(const TargetRegisterClass *RC) const {
+ static const uint8_t RCSetStartTable[] = {
+ 29,26,1,1,1,1,1,13,36,36,1,13,1,13,1,41,1,1,22,22,1,22,15,22,2,1,22,15,20,20,4,9,20,1,1,0,1,19,7,7,1,29,13,13,36,26,22,57,22,15,22,22,15,5,20,20,20,1,1,7,1,12,19,7,7,1,29,29,29,29,26,31,7,};
+ return &RCSetsTable[RCSetStartTable[RC->getID()]];
+}
+
+/// Get the dimensions of register pressure impacted by this register unit.
+/// Returns a -1 terminated array of pressure set IDs
+const int* MipsGenRegisterInfo::
+getRegUnitPressureSets(unsigned RegUnit) const {
+ assert(RegUnit < 297 && "invalid register unit");
+ static const uint8_t RUSetStartTable[] = {
+ 13,0,1,1,1,1,1,1,1,1,1,13,13,2,2,2,2,2,2,2,2,1,12,22,19,22,22,22,22,7,7,9,4,9,4,9,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,13,13,1,1,1,1,1,1,20,20,15,15,15,13,13,13,13,13,13,13,13,13,13,13,13,13,20,20,};
+ return &RCSetsTable[RUSetStartTable[RegUnit]];
+}
+
+extern const MCRegisterDesc MipsRegDesc[];
+extern const MCPhysReg MipsRegDiffLists[];
+extern const LaneBitmask MipsLaneMaskLists[];
+extern const char MipsRegStrings[];
+extern const char MipsRegClassStrings[];
+extern const MCPhysReg MipsRegUnitRoots[][2];
+extern const uint16_t MipsSubRegIdxLists[];
+extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];
+extern const uint16_t MipsRegEncodingTable[];
+// Mips Dwarf<->LLVM register mappings.
+extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
+extern const unsigned MipsDwarfFlavour0Dwarf2LSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
+extern const unsigned MipsEHFlavour0Dwarf2LSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
+extern const unsigned MipsDwarfFlavour0L2DwarfSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
+extern const unsigned MipsEHFlavour0L2DwarfSize;
+
+MipsGenRegisterInfo::
+MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
+ unsigned PC, unsigned HwMode)
+ : TargetRegisterInfo(MipsRegInfoDesc, RegisterClasses, RegisterClasses+73,
+ SubRegIndexNameTable, SubRegIndexLaneMaskTable,
+ LaneBitmask(0xFFFFFF80), RegClassInfos, HwMode) {
+ InitMCRegisterInfo(MipsRegDesc, 418, RA, PC,
+ MipsMCRegisterClasses, 73,
+ MipsRegUnitRoots,
+ 297,
+ MipsRegDiffLists,
+ MipsLaneMaskLists,
+ MipsRegStrings,
+ MipsRegClassStrings,
+ MipsSubRegIdxLists,
+ 12,
+ MipsSubRegIdxRanges,
+ MipsRegEncodingTable);
+
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
+ break;
+ }
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
+ break;
+ }
+}
+
+static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
+static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0xffbfc008, 0x00000007, 0x00000000, 0x00000000, 0x00000000, };
+static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
+static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffbfc000, 0x00000007, 0x00000000, 0x00000000, 0x00000000, };
+static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
+static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0xffbfe008, 0x00000007, 0x000001f0, 0xffffe400, 0x00000003, };
+static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
+static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0xffbfe000, 0x00000007, 0x000000f0, 0xffffc000, 0x00000003, };
+static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
+static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03c00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000006, 0x00000000, 0x00000000, 0x00000000, };
+static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
+static const uint32_t CSR_N32_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x003fe000, 0x00000000, 0xa0000000, 0x003fc0aa, 0x00000000, };
+static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
+static const uint32_t CSR_N64_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x003fe000, 0x00000000, 0x00000000, 0x003fc1fe, 0x00000000, };
+static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
+static const uint32_t CSR_O32_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
+static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
+static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x003fc000, 0x00000000, 0xa0000000, 0x000000aa, 0x00000000, };
+static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
+static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
+static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
+static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
+
+
+ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
+ static const uint32_t *const Masks[] = {
+ CSR_Interrupt_32_RegMask,
+ CSR_Interrupt_32R6_RegMask,
+ CSR_Interrupt_64_RegMask,
+ CSR_Interrupt_64R6_RegMask,
+ CSR_Mips16RetHelper_RegMask,
+ CSR_N32_RegMask,
+ CSR_N64_RegMask,
+ CSR_O32_RegMask,
+ CSR_O32_FP64_RegMask,
+ CSR_O32_FPXX_RegMask,
+ CSR_SingleFloatOnly_RegMask,
+ };
+ return makeArrayRef(Masks);
+}
+
+ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
+ static const char *const Names[] = {
+ "CSR_Interrupt_32",
+ "CSR_Interrupt_32R6",
+ "CSR_Interrupt_64",
+ "CSR_Interrupt_64R6",
+ "CSR_Mips16RetHelper",
+ "CSR_N32",
+ "CSR_N64",
+ "CSR_O32",
+ "CSR_O32_FP64",
+ "CSR_O32_FPXX",
+ "CSR_SingleFloatOnly",
+ };
+ return makeArrayRef(Names);
+}
+
+const MipsFrameLowering *
+MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
+ return static_cast<const MipsFrameLowering *>(
+ MF.getSubtarget().getFrameLowering());
+}
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_TARGET_DESC
+
diff --git a/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenSubtargetInfo.inc b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenSubtargetInfo.inc
new file mode 100644
index 0000000..9429f76
--- /dev/null
+++ b/third_party/llvm-7.0/configs/common/lib/Target/Mips/MipsGenSubtargetInfo.inc
@@ -0,0 +1,2750 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Subtarget Enumeration Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+namespace llvm {
+namespace Mips {
+enum {
+ FeatureCRC = 0,
+ FeatureCnMips = 1,
+ FeatureDSP = 2,
+ FeatureDSPR2 = 3,
+ FeatureDSPR3 = 4,
+ FeatureEVA = 5,
+ FeatureFP64Bit = 6,
+ FeatureFPXX = 7,
+ FeatureGINV = 8,
+ FeatureGP64Bit = 9,
+ FeatureLongCalls = 10,
+ FeatureMSA = 11,
+ FeatureMT = 12,
+ FeatureMadd4 = 13,
+ FeatureMicroMips = 14,
+ FeatureMips1 = 15,
+ FeatureMips2 = 16,
+ FeatureMips3 = 17,
+ FeatureMips3_32 = 18,
+ FeatureMips3_32r2 = 19,
+ FeatureMips4 = 20,
+ FeatureMips4_32 = 21,
+ FeatureMips4_32r2 = 22,
+ FeatureMips5 = 23,
+ FeatureMips5_32r2 = 24,
+ FeatureMips16 = 25,
+ FeatureMips32 = 26,
+ FeatureMips32r2 = 27,
+ FeatureMips32r3 = 28,
+ FeatureMips32r5 = 29,
+ FeatureMips32r6 = 30,
+ FeatureMips64 = 31,
+ FeatureMips64r2 = 32,
+ FeatureMips64r3 = 33,
+ FeatureMips64r5 = 34,
+ FeatureMips64r6 = 35,
+ FeatureNaN2008 = 36,
+ FeatureNoABICalls = 37,
+ FeatureNoOddSPReg = 38,
+ FeaturePTR64Bit = 39,
+ FeatureSingleFloat = 40,
+ FeatureSoftFloat = 41,
+ FeatureSym32 = 42,
+ FeatureUseIndirectJumpsHazard = 43,
+ FeatureUseTCCInDIV = 44,
+ FeatureVFPU = 45,
+ FeatureVirt = 46,
+ ImplP5600 = 47,
+};
+} // end namespace Mips
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+#ifdef GET_SUBTARGETINFO_MC_DESC
+#undef GET_SUBTARGETINFO_MC_DESC
+
+namespace llvm {
+// Sorted (by key) array of values for CPU features.
+extern const llvm::SubtargetFeatureKV MipsFeatureKV[] = {
+ { "cnmips", "Octeon cnMIPS Support", { Mips::FeatureCnMips }, { Mips::FeatureMips64r2 } },
+ { "crc", "Mips R6 CRC ASE", { Mips::FeatureCRC }, { } },
+ { "dsp", "Mips DSP ASE", { Mips::FeatureDSP }, { } },
+ { "dspr2", "Mips DSP-R2 ASE", { Mips::FeatureDSPR2 }, { Mips::FeatureDSP } },
+ { "dspr3", "Mips DSP-R3 ASE", { Mips::FeatureDSPR3 }, { Mips::FeatureDSP, Mips::FeatureDSPR2 } },
+ { "eva", "Mips EVA ASE", { Mips::FeatureEVA }, { } },
+ { "fp64", "Support 64-bit FP registers", { Mips::FeatureFP64Bit }, { } },
+ { "fpxx", "Support for FPXX", { Mips::FeatureFPXX }, { } },
+ { "ginv", "Mips Global Invalidate ASE", { Mips::FeatureGINV }, { } },
+ { "gp64", "General Purpose Registers are 64-bit wide", { Mips::FeatureGP64Bit }, { } },
+ { "long-calls", "Disable use of the jal instruction", { Mips::FeatureLongCalls }, { } },
+ { "micromips", "microMips mode", { Mips::FeatureMicroMips }, { } },
+ { "mips1", "Mips I ISA Support [highly experimental]", { Mips::FeatureMips1 }, { } },
+ { "mips16", "Mips16 mode", { Mips::FeatureMips16 }, { } },
+ { "mips2", "Mips II ISA Support [highly experimental]", { Mips::FeatureMips2 }, { Mips::FeatureMips1 } },
+ { "mips3", "MIPS III ISA Support [highly experimental]", { Mips::FeatureMips3 }, { Mips::FeatureMips2, Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureGP64Bit, Mips::FeatureFP64Bit } },
+ { "mips32", "Mips32 ISA Support", { Mips::FeatureMips32 }, { Mips::FeatureMips2, Mips::FeatureMips3_32, Mips::FeatureMips4_32 } },
+ { "mips32r2", "Mips32r2 ISA Support", { Mips::FeatureMips32r2 }, { Mips::FeatureMips3_32r2, Mips::FeatureMips4_32r2, Mips::FeatureMips5_32r2, Mips::FeatureMips32 } },
+ { "mips32r3", "Mips32r3 ISA Support", { Mips::FeatureMips32r3 }, { Mips::FeatureMips32r2 } },
+ { "mips32r5", "Mips32r5 ISA Support", { Mips::FeatureMips32r5 }, { Mips::FeatureMips32r3 } },
+ { "mips32r6", "Mips32r6 ISA Support [experimental]", { Mips::FeatureMips32r6 }, { Mips::FeatureMips32r5, Mips::FeatureFP64Bit, Mips::FeatureNaN2008 } },
+ { "mips3_32", "Subset of MIPS-III that is also in MIPS32 [highly experimental]", { Mips::FeatureMips3_32 }, { } },
+ { "mips3_32r2", "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]", { Mips::FeatureMips3_32r2 }, { } },
+ { "mips4", "MIPS IV ISA Support", { Mips::FeatureMips4 }, { Mips::FeatureMips3, Mips::FeatureMips4_32, Mips::FeatureMips4_32r2 } },
+ { "mips4_32", "Subset of MIPS-IV that is also in MIPS32 [highly experimental]", { Mips::FeatureMips4_32 }, { } },
+ { "mips4_32r2", "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]", { Mips::FeatureMips4_32r2 }, { } },
+ { "mips5", "MIPS V ISA Support [highly experimental]", { Mips::FeatureMips5 }, { Mips::FeatureMips4, Mips::FeatureMips5_32r2 } },
+ { "mips5_32r2", "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]", { Mips::FeatureMips5_32r2 }, { } },
+ { "mips64", "Mips64 ISA Support", { Mips::FeatureMips64 }, { Mips::FeatureMips5, Mips::FeatureMips32 } },
+ { "mips64r2", "Mips64r2 ISA Support", { Mips::FeatureMips64r2 }, { Mips::FeatureMips64, Mips::FeatureMips32r2 } },
+ { "mips64r3", "Mips64r3 ISA Support", { Mips::FeatureMips64r3 }, { Mips::FeatureMips64r2, Mips::FeatureMips32r3 } },
+ { "mips64r5", "Mips64r5 ISA Support", { Mips::FeatureMips64r5 }, { Mips::FeatureMips64r3, Mips::FeatureMips32r5 } },
+ { "mips64r6", "Mips64r6 ISA Support [experimental]", { Mips::FeatureMips64r6 }, { Mips::FeatureMips32r6, Mips::FeatureMips64r5, Mips::FeatureNaN2008 } },
+ { "msa", "Mips MSA ASE", { Mips::FeatureMSA }, { } },
+ { "mt", "Mips MT ASE", { Mips::FeatureMT }, { } },
+ { "nan2008", "IEEE 754-2008 NaN encoding", { Mips::FeatureNaN2008 }, { } },
+ { "noabicalls", "Disable SVR4-style position-independent code", { Mips::FeatureNoABICalls }, { } },
+ { "nomadd4", "Disable 4-operand madd.fmt and related instructions", { Mips::FeatureMadd4 }, { } },
+ { "nooddspreg", "Disable odd numbered single-precision registers", { Mips::FeatureNoOddSPReg }, { } },
+ { "p5600", "The P5600 Processor", { Mips::ImplP5600 }, { Mips::FeatureMips32r5 } },
+ { "ptr64", "Pointers are 64-bit wide", { Mips::FeaturePTR64Bit }, { } },
+ { "single-float", "Only supports single precision float", { Mips::FeatureSingleFloat }, { } },
+ { "soft-float", "Does not support floating point instructions", { Mips::FeatureSoftFloat }, { } },
+ { "sym32", "Symbols are 32 bit on Mips64", { Mips::FeatureSym32 }, { } },
+ { "use-indirect-jump-hazard", "Use indirect jump guards to prevent certain speculation based attacks", { Mips::FeatureUseIndirectJumpsHazard }, { } },
+ { "use-tcc-in-div", "Force the assembler to use trapping", { Mips::FeatureUseTCCInDIV }, { } },
+ { "vfpu", "Enable vector FPU instructions", { Mips::FeatureVFPU }, { } },
+ { "virt", "Mips Virtualization ASE", { Mips::FeatureVirt }, { } },
+};
+
+// Sorted (by key) array of values for CPU subtype.
+extern const llvm::SubtargetFeatureKV MipsSubTypeKV[] = {
+ { "mips1", "Select the mips1 processor", { Mips::FeatureMips1 }, { } },
+ { "mips2", "Select the mips2 processor", { Mips::FeatureMips2 }, { } },
+ { "mips3", "Select the mips3 processor", { Mips::FeatureMips3 }, { } },
+ { "mips32", "Select the mips32 processor", { Mips::FeatureMips32 }, { } },
+ { "mips32r2", "Select the mips32r2 processor", { Mips::FeatureMips32r2 }, { } },
+ { "mips32r3", "Select the mips32r3 processor", { Mips::FeatureMips32r3 }, { } },
+ { "mips32r5", "Select the mips32r5 processor", { Mips::FeatureMips32r5 }, { } },
+ { "mips32r6", "Select the mips32r6 processor", { Mips::FeatureMips32r6 }, { } },
+ { "mips4", "Select the mips4 processor", { Mips::FeatureMips4 }, { } },
+ { "mips5", "Select the mips5 processor", { Mips::FeatureMips5 }, { } },
+ { "mips64", "Select the mips64 processor", { Mips::FeatureMips64 }, { } },
+ { "mips64r2", "Select the mips64r2 processor", { Mips::FeatureMips64r2 }, { } },
+ { "mips64r3", "Select the mips64r3 processor", { Mips::FeatureMips64r3 }, { } },
+ { "mips64r5", "Select the mips64r5 processor", { Mips::FeatureMips64r5 }, { } },
+ { "mips64r6", "Select the mips64r6 processor", { Mips::FeatureMips64r6 }, { } },
+ { "octeon", "Select the octeon processor", { Mips::FeatureMips64r2, Mips::FeatureCnMips }, { } },
+ { "p5600", "Select the p5600 processor", { Mips::ImplP5600 }, { } },
+};
+
+#ifdef DBGFIELD
+#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
+#endif
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+#define DBGFIELD(x) x,
+#else
+#define DBGFIELD(x)
+#endif
+
+// ===============================================================
+// Data tables for the new per-operand machine model.
+
+// {ProcResourceIdx, Cycles}
+extern const llvm::MCWriteProcResEntry MipsWriteProcResTable[] = {
+ { 0, 0}, // Invalid
+ { 1, 1}, // #1
+ { 7, 1}, // #2
+ { 1, 1}, // #3
+ { 9, 1}, // #4
+ { 5, 1}, // #5
+ {13, 1}, // #6
+ { 5, 1}, // #7
+ {11, 1}, // #8
+ { 1, 1}, // #9
+ {17, 1}, // #10
+ {10, 33}, // #11
+ {19, 33}, // #12
+ {10, 31}, // #13
+ {19, 31}, // #14
+ { 5, 1}, // #15
+ {14, 1}, // #16
+ {16, 1}, // #17
+ {18, 1}, // #18
+ { 2, 1}, // #19
+ { 8, 1}, // #20
+ { 3, 1}, // #21
+ { 5, 29}, // #22
+ { 6, 29}, // #23
+ { 5, 14}, // #24
+ { 6, 14}, // #25
+ { 5, 1}, // #26
+ {12, 1}, // #27
+ { 5, 21}, // #28
+ { 6, 21}, // #29
+ { 5, 10}, // #30
+ { 6, 10}, // #31
+ { 5, 1}, // #32
+ {15, 1}, // #33
+ { 5, 33}, // #34
+ { 4, 1}, // #35
+ { 3, 1}, // #36
+ { 8, 1}, // #37
+ { 1, 1}, // #38
+ { 4, 1}, // #39
+ { 9, 1}, // #40
+ { 1, 1}, // #41
+ {13, 1}, // #42
+ { 1, 1}, // #43
+ { 4, 1}, // #44
+ {13, 1}, // #45
+ { 1, 1}, // #46
+ { 4, 3}, // #47
+ {13, 1}, // #48
+ { 1, 1}, // #49
+ { 4, 1}, // #50
+ { 7, 1}, // #51
+ { 1, 1}, // #52
+ { 2, 34}, // #53
+ { 7, 1}, // #54
+ { 5, 1}, // #55
+ { 6, 23}, // #56
+ {10, 1}, // #57
+ { 5, 1}, // #58
+ {10, 1}, // #59
+ { 5, 1}, // #60
+ { 6, 31}, // #61
+ {10, 1}, // #62
+ { 5, 1}, // #63
+ { 6, 27}, // #64
+ {10, 1}, // #65
+ { 5, 1}, // #66
+ { 6, 35}, // #67
+ {10, 1}, // #68
+ { 1, 1}, // #69
+ { 5, 1}, // #70
+ {12, 1}, // #71
+ {13, 1}, // #72
+ { 1, 1}, // #73
+ { 5, 1}, // #74
+ {10, 1}, // #75
+ {13, 1}, // #76
+ { 1, 1}, // #77
+ { 5, 1}, // #78
+ {11, 1}, // #79
+ {13, 1} // #80
+}; // MipsWriteProcResTable
+
+// {Cycles, WriteResourceID}
+extern const llvm::MCWriteLatencyEntry MipsWriteLatencyTable[] = {
+ { 0, 0}, // Invalid
+ { 1, 0}, // #1 GenericWriteALU_GenericWriteJump_GenericWriteHILO_GenericWriteTrap_GenericWriteCOPOther_GenericWriteCOP0Short_GenericWritePref_GenericWriteStore_GenericWriteFPUStore_GenericWriteSync_GenericWriteMSAShortLogic_P5600WriteALU_P5600WriteJump_P5600COP0_P5600COP2_P5600WriteStore_P5600WriteCache_P5600WriteAL2_P5600WriteMSAShortLogic_P5600WriteFPUS_P5600WriteMoveOtherUnitsToFPU_P5600WriteStoreFromOtherUnits
+ { 2, 0}, // #2 GenericWriteFPUMoveGPRFPU_GenericWriteJumpAndLink_GenericWriteMove_GenericWriteFPUCmp_GenericReadCOP0_GenericWriteLoad_GenericWriteFPULoad_GenericWriteStoreSC_GenericWriteMSAShortInt_GenericDSPShort_P5600WriteJumpAndLink_P5600WriteAL2ShadowMov_P5600WriteAL2CondMov_P5600WriteAL2BitExt_P5600WriteMSAShortInt_P5600WriteGPRFromBypass_P5600WriteStoreFromOtherUnits
+ { 5, 0}, // #3 GenericWriteFPUL_GenericWriteALULong_GenericWriteCache_GenericWriteMDUtoGPR_GenericReadWriteCOP0Long_GenericWriteMSALongInt_GenericDSPMTHLIP_GenericDSPMTHILO_P5600WriteAL2Mult_P5600WriteAL2MAdd_P5600WriteMSALongInt
+ {33, 0}, // #4 GenericWriteDIV_GenericWriteFPUDivI
+ {31, 0}, // #5 GenericWriteDIVU_P5600WriteFPUDivD
+ { 4, 0}, // #6 GenericWriteFPUS_GenericWriteFPUMoveFP_GenericWriteMul_GenericWriteCOP0TLB_P5600WriteLoad_P5600WriteLoadShifted_P5600WriteFPUL_P5600WriteLoadOtherUnitsToFPU
+ { 3, 0}, // #7 GenericWriteCOP0_GenericWriteMSAOther3_P5600WriteAL2Mul_P5600WriteMSAOther3
+ {29, 0}, // #8 GenericWriteFPUSqrtD
+ {32, 0}, // #9 GenericWriteFPUDivD
+ {17, 0}, // #10 GenericWriteFPUDivS_GenericWriteFPUSqrtS
+ {25, 0}, // #11 GenericWriteFPURcpD
+ {13, 0}, // #12 GenericWriteFPURcpS
+ { 6, 0}, // #13 GenericDSPLong_P5600WriteFPUL_MADDSUB
+ {34, 0}, // #14 P5600WriteAL2Div_P5600WriteAL2DivU
+ {23, 0}, // #15 P5600WriteFPUDivI_P5600WriteFPUDivS
+ {27, 0}, // #16 P5600WriteFPUSqrtS_P5600WriteFPURsqrtD_P5600WriteFPURsqrtS
+ {35, 0} // #17 P5600WriteFPUSqrtD
+}; // MipsWriteLatencyTable
+
+// {UseIdx, WriteResourceID, Cycles}
+extern const llvm::MCReadAdvanceEntry MipsReadAdvanceTable[] = {
+ {0, 0, 0}, // Invalid
+ {0, 0, 5} // #1
+}; // MipsReadAdvanceTable
+
+// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
+static const llvm::MCSchedClassDesc MipsGenericModelSchedClasses[] = {
+ {DBGFIELD("InvalidSchedClass") 16383, false, false, 0, 0, 0, 0, 0, 0},
+ {DBGFIELD("IIPseudo") 1, false, false, 1, 2, 1, 1, 0, 0}, // #1
+ {DBGFIELD("II_B") 1, false, false, 3, 2, 1, 1, 0, 0}, // #2
+ {DBGFIELD("II_BCCZAL") 1, false, false, 3, 2, 1, 1, 0, 0}, // #3
+ {DBGFIELD("II_MTC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #4
+ {DBGFIELD("II_MFC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #5
+ {DBGFIELD("II_JALR") 1, false, false, 3, 2, 2, 1, 0, 0}, // #6
+ {DBGFIELD("II_CVT") 1, false, false, 7, 2, 3, 1, 0, 0}, // #7
+ {DBGFIELD("II_DMULT") 1, false, false, 9, 2, 1, 1, 0, 0}, // #8
+ {DBGFIELD("II_DMULTU") 1, false, false, 9, 2, 1, 1, 0, 0}, // #9
+ {DBGFIELD("II_DDIV") 1, false, false, 11, 2, 4, 1, 0, 0}, // #10
+ {DBGFIELD("II_DDIVU") 1, false, false, 13, 2, 5, 1, 0, 0}, // #11
+ {DBGFIELD("II_IndirectBranchPseudo") 0, false, false, 0, 0, 0, 0, 0, 0}, // #12
+ {DBGFIELD("II_MADD") 1, false, false, 9, 2, 1, 1, 0, 0}, // #13
+ {DBGFIELD("II_MADDU") 1, false, false, 9, 2, 1, 1, 0, 0}, // #14
+ {DBGFIELD("II_MFHI_MFLO") 1, false, false, 1, 2, 3, 1, 0, 0}, // #15
+ {DBGFIELD("II_MSUB") 1, false, false, 9, 2, 1, 1, 0, 0}, // #16
+ {DBGFIELD("II_MSUBU") 1, false, false, 9, 2, 1, 1, 0, 0}, // #17
+ {DBGFIELD("II_MTHI_MTLO") 1, false, false, 1, 2, 2, 1, 0, 0}, // #18
+ {DBGFIELD("II_MULT") 1, false, false, 1, 2, 1, 1, 0, 0}, // #19
+ {DBGFIELD("II_MULTU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #20
+ {DBGFIELD("II_ReturnPseudo") 0, false, false, 0, 0, 0, 0, 0, 0}, // #21
+ {DBGFIELD("II_DIV") 1, false, false, 11, 2, 4, 1, 0, 0}, // #22
+ {DBGFIELD("II_DIVU") 1, false, false, 13, 2, 5, 1, 0, 0}, // #23
+ {DBGFIELD("II_J") 1, false, false, 3, 2, 1, 1, 0, 0}, // #24
+ {DBGFIELD("II_JR") 1, false, false, 3, 2, 1, 1, 0, 0}, // #25
+ {DBGFIELD("II_TRAP") 1, false, false, 3, 2, 1, 1, 0, 0}, // #26
+ {DBGFIELD("II_ADD") 1, false, false, 1, 2, 1, 1, 0, 0}, // #27
+ {DBGFIELD("II_ADDIUPC") 1, false, false, 1, 2, 1, 1, 0, 0}, // #28
+ {DBGFIELD("II_ADDIU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #29
+ {DBGFIELD("II_ADDU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #30
+ {DBGFIELD("II_ADDI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #31
+ {DBGFIELD("II_ALIGN") 1, false, false, 1, 2, 1, 1, 0, 0}, // #32
+ {DBGFIELD("II_ALUIPC") 1, false, false, 1, 2, 1, 1, 0, 0}, // #33
+ {DBGFIELD("II_AND") 1, false, false, 1, 2, 1, 1, 0, 0}, // #34
+ {DBGFIELD("II_ANDI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #35
+ {DBGFIELD("II_AUI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #36
+ {DBGFIELD("II_AUIPC") 1, false, false, 1, 2, 1, 1, 0, 0}, // #37
+ {DBGFIELD("IIM16Alu") 1, false, false, 1, 2, 1, 1, 0, 0}, // #38
+ {DBGFIELD("II_BADDU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #39
+ {DBGFIELD("II_BC") 1, false, false, 3, 2, 1, 1, 0, 0}, // #40
+ {DBGFIELD("II_BALC") 1, false, false, 3, 2, 2, 1, 0, 0}, // #41
+ {DBGFIELD("II_BBIT") 1, false, false, 1, 2, 1, 1, 0, 0}, // #42
+ {DBGFIELD("II_BC1CCZ") 1, false, false, 15, 2, 2, 1, 0, 0}, // #43
+ {DBGFIELD("II_BC1F") 1, false, false, 15, 2, 2, 1, 0, 0}, // #44
+ {DBGFIELD("II_BC1FL") 1, false, false, 15, 2, 2, 1, 0, 0}, // #45
+ {DBGFIELD("II_BC1T") 1, false, false, 15, 2, 2, 1, 0, 0}, // #46
+ {DBGFIELD("II_BC1TL") 1, false, false, 15, 2, 2, 1, 0, 0}, // #47
+ {DBGFIELD("II_BC2CCZ") 1, false, false, 3, 2, 2, 1, 0, 0}, // #48
+ {DBGFIELD("II_BCC") 1, false, false, 3, 2, 1, 1, 0, 0}, // #49
+ {DBGFIELD("II_BCCC") 1, false, false, 3, 2, 1, 1, 0, 0}, // #50
+ {DBGFIELD("II_BCCZ") 1, false, false, 3, 2, 1, 1, 0, 0}, // #51
+ {DBGFIELD("II_BCCZC") 1, false, false, 3, 2, 1, 1, 0, 0}, // #52
+ {DBGFIELD("II_BCCZALS") 1, false, false, 3, 2, 2, 1, 0, 0}, // #53
+ {DBGFIELD("II_BITSWAP") 1, false, false, 1, 2, 1, 1, 0, 0}, // #54
+ {DBGFIELD("II_BREAK") 1, false, false, 3, 2, 1, 1, 0, 0}, // #55
+ {DBGFIELD("II_CACHE") 1, false, false, 17, 2, 3, 1, 0, 0}, // #56
+ {DBGFIELD("II_CACHEE") 1, false, false, 17, 2, 3, 1, 0, 0}, // #57
+ {DBGFIELD("II_CEIL") 1, false, false, 7, 2, 3, 1, 0, 0}, // #58
+ {DBGFIELD("II_CFC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #59
+ {DBGFIELD("II_CFC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #60
+ {DBGFIELD("II_INS") 1, false, false, 1, 2, 1, 1, 0, 0}, // #61
+ {DBGFIELD("II_CLASS_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #62
+ {DBGFIELD("II_CLASS_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #63
+ {DBGFIELD("II_CLO") 1, false, false, 1, 2, 1, 1, 0, 0}, // #64
+ {DBGFIELD("II_CLZ") 1, false, false, 1, 2, 1, 1, 0, 0}, // #65
+ {DBGFIELD("II_CMP_CC_D") 1, false, false, 15, 2, 2, 1, 0, 0}, // #66
+ {DBGFIELD("II_CMP_CC_S") 1, false, false, 15, 2, 2, 1, 0, 0}, // #67
+ {DBGFIELD("II_CRC32B") 0, false, false, 0, 0, 0, 0, 0, 0}, // #68
+ {DBGFIELD("II_CRC32CB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #69
+ {DBGFIELD("II_CRC32CD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #70
+ {DBGFIELD("II_CRC32CH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #71
+ {DBGFIELD("II_CRC32CW") 0, false, false, 0, 0, 0, 0, 0, 0}, // #72
+ {DBGFIELD("II_CRC32D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #73
+ {DBGFIELD("II_CRC32H") 0, false, false, 0, 0, 0, 0, 0, 0}, // #74
+ {DBGFIELD("II_CRC32W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #75
+ {DBGFIELD("II_CTC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #76
+ {DBGFIELD("II_CTC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #77
+ {DBGFIELD("II_C_CC_D") 1, false, false, 15, 2, 2, 1, 0, 0}, // #78
+ {DBGFIELD("II_C_CC_S") 1, false, false, 15, 2, 2, 1, 0, 0}, // #79
+ {DBGFIELD("II_DADD") 1, false, false, 1, 2, 1, 1, 0, 0}, // #80
+ {DBGFIELD("II_DADDI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #81
+ {DBGFIELD("II_DADDIU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #82
+ {DBGFIELD("II_DADDU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #83
+ {DBGFIELD("II_DAHI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #84
+ {DBGFIELD("II_DALIGN") 1, false, false, 1, 2, 1, 1, 0, 0}, // #85
+ {DBGFIELD("II_DATI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #86
+ {DBGFIELD("II_DAUI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #87
+ {DBGFIELD("II_DBITSWAP") 1, false, false, 1, 2, 1, 1, 0, 0}, // #88
+ {DBGFIELD("II_DCLO") 1, false, false, 1, 2, 1, 1, 0, 0}, // #89
+ {DBGFIELD("II_DCLZ") 1, false, false, 1, 2, 1, 1, 0, 0}, // #90
+ {DBGFIELD("II_DERET") 1, false, false, 3, 2, 1, 1, 0, 0}, // #91
+ {DBGFIELD("II_EXT") 1, false, false, 1, 2, 1, 1, 0, 0}, // #92
+ {DBGFIELD("II_DI") 1, false, false, 19, 2, 7, 1, 0, 0}, // #93
+ {DBGFIELD("II_DLSA") 1, false, false, 1, 2, 1, 1, 0, 0}, // #94
+ {DBGFIELD("II_DMFC0") 1, false, false, 19, 2, 2, 1, 0, 0}, // #95
+ {DBGFIELD("II_DMFC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #96
+ {DBGFIELD("II_DMFC2") 1, false, false, 21, 1, 1, 1, 0, 0}, // #97
+ {DBGFIELD("II_DMFGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #98
+ {DBGFIELD("II_DMOD") 1, false, false, 11, 2, 4, 1, 0, 0}, // #99
+ {DBGFIELD("II_DMODU") 1, false, false, 11, 2, 4, 1, 0, 0}, // #100
+ {DBGFIELD("II_DMT") 1, false, false, 1, 2, 2, 1, 0, 0}, // #101
+ {DBGFIELD("II_DMTC0") 1, false, false, 19, 2, 7, 1, 0, 0}, // #102
+ {DBGFIELD("II_DMTC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #103
+ {DBGFIELD("II_DMTC2") 1, false, false, 21, 1, 1, 1, 0, 0}, // #104
+ {DBGFIELD("II_DMTGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #105
+ {DBGFIELD("II_DMUH") 1, false, false, 9, 2, 3, 1, 0, 0}, // #106
+ {DBGFIELD("II_DMUHU") 1, false, false, 9, 2, 3, 1, 0, 0}, // #107
+ {DBGFIELD("II_DMUL") 1, false, false, 9, 2, 3, 1, 0, 0}, // #108
+ {DBGFIELD("II_POP") 1, false, false, 1, 2, 1, 1, 0, 0}, // #109
+ {DBGFIELD("II_DROTR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #110
+ {DBGFIELD("II_DROTR32") 1, false, false, 1, 2, 1, 1, 0, 0}, // #111
+ {DBGFIELD("II_DROTRV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #112
+ {DBGFIELD("II_DSBH") 1, false, false, 1, 2, 1, 1, 0, 0}, // #113
+ {DBGFIELD("II_DSHD") 1, false, false, 1, 2, 1, 1, 0, 0}, // #114
+ {DBGFIELD("II_DSLL") 1, false, false, 1, 2, 1, 1, 0, 0}, // #115
+ {DBGFIELD("II_DSLL32") 1, false, false, 1, 2, 1, 1, 0, 0}, // #116
+ {DBGFIELD("II_DSLLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #117
+ {DBGFIELD("II_DSRA") 1, false, false, 1, 2, 1, 1, 0, 0}, // #118
+ {DBGFIELD("II_DSRA32") 1, false, false, 1, 2, 1, 1, 0, 0}, // #119
+ {DBGFIELD("II_DSRAV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #120
+ {DBGFIELD("II_DSRL") 1, false, false, 1, 2, 1, 1, 0, 0}, // #121
+ {DBGFIELD("II_DSRL32") 1, false, false, 1, 2, 1, 1, 0, 0}, // #122
+ {DBGFIELD("II_DSRLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #123
+ {DBGFIELD("II_DSUB") 1, false, false, 1, 2, 1, 1, 0, 0}, // #124
+ {DBGFIELD("II_DSUBU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #125
+ {DBGFIELD("II_DVP") 1, false, false, 19, 2, 7, 1, 0, 0}, // #126
+ {DBGFIELD("II_DVPE") 1, false, false, 1, 2, 2, 1, 0, 0}, // #127
+ {DBGFIELD("II_EHB") 1, false, false, 19, 2, 7, 1, 0, 0}, // #128
+ {DBGFIELD("II_EI") 1, false, false, 19, 2, 7, 1, 0, 0}, // #129
+ {DBGFIELD("II_EMT") 1, false, false, 1, 2, 2, 1, 0, 0}, // #130
+ {DBGFIELD("II_ERET") 1, false, false, 3, 2, 1, 1, 0, 0}, // #131
+ {DBGFIELD("II_ERETNC") 1, false, false, 3, 2, 1, 1, 0, 0}, // #132
+ {DBGFIELD("II_EVP") 1, false, false, 19, 2, 7, 1, 0, 0}, // #133
+ {DBGFIELD("II_EVPE") 1, false, false, 1, 2, 2, 1, 0, 0}, // #134
+ {DBGFIELD("II_ABS") 1, false, false, 15, 2, 6, 1, 0, 0}, // #135
+ {DBGFIELD("II_SQRT_D") 1, false, false, 22, 2, 8, 1, 0, 0}, // #136
+ {DBGFIELD("II_ADD_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #137
+ {DBGFIELD("II_ADD_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #138
+ {DBGFIELD("II_DIV_D") 1, false, false, 22, 2, 9, 1, 0, 0}, // #139
+ {DBGFIELD("II_DIV_S") 1, false, false, 24, 2, 10, 1, 0, 0}, // #140
+ {DBGFIELD("II_FLOOR") 1, false, false, 7, 2, 3, 1, 0, 0}, // #141
+ {DBGFIELD("II_MOV_D") 1, false, false, 5, 2, 6, 1, 0, 0}, // #142
+ {DBGFIELD("II_MOV_S") 1, false, false, 5, 2, 6, 1, 0, 0}, // #143
+ {DBGFIELD("II_MUL_D") 1, false, false, 7, 2, 3, 1, 0, 0}, // #144
+ {DBGFIELD("II_MUL_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #145
+ {DBGFIELD("II_NEG") 1, false, false, 15, 2, 6, 1, 0, 0}, // #146
+ {DBGFIELD("II_FORK") 1, false, false, 19, 2, 1, 1, 0, 0}, // #147
+ {DBGFIELD("II_SQRT_S") 1, false, false, 24, 2, 10, 1, 0, 0}, // #148
+ {DBGFIELD("II_SUB_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #149
+ {DBGFIELD("II_SUB_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #150
+ {DBGFIELD("II_GINVI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #151
+ {DBGFIELD("II_GINVT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #152
+ {DBGFIELD("II_HYPCALL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #153
+ {DBGFIELD("II_JAL") 1, false, false, 3, 2, 2, 1, 0, 0}, // #154
+ {DBGFIELD("II_JALR_HB") 1, false, false, 3, 2, 2, 1, 0, 0}, // #155
+ {DBGFIELD("II_JALRC") 1, false, false, 3, 2, 2, 1, 0, 0}, // #156
+ {DBGFIELD("II_JALRS") 1, false, false, 3, 2, 2, 1, 0, 0}, // #157
+ {DBGFIELD("II_JALS") 1, false, false, 3, 2, 2, 1, 0, 0}, // #158
+ {DBGFIELD("II_JIALC") 1, false, false, 3, 2, 2, 1, 0, 0}, // #159
+ {DBGFIELD("II_JIC") 1, false, false, 3, 2, 1, 1, 0, 0}, // #160
+ {DBGFIELD("II_JRADDIUSP") 1, false, false, 3, 2, 1, 1, 0, 0}, // #161
+ {DBGFIELD("II_JRC") 1, false, false, 3, 2, 1, 1, 0, 0}, // #162
+ {DBGFIELD("II_JR_HB") 1, false, false, 3, 2, 1, 1, 0, 0}, // #163
+ {DBGFIELD("II_LB") 1, false, false, 17, 2, 2, 1, 0, 0}, // #164
+ {DBGFIELD("II_LBE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #165
+ {DBGFIELD("II_LBU") 1, false, false, 17, 2, 2, 1, 0, 0}, // #166
+ {DBGFIELD("II_LBUE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #167
+ {DBGFIELD("II_LD") 1, false, false, 17, 2, 2, 1, 0, 0}, // #168
+ {DBGFIELD("II_LDC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #169
+ {DBGFIELD("II_LDC2") 1, false, false, 17, 2, 2, 1, 0, 0}, // #170
+ {DBGFIELD("II_LDC3") 1, false, false, 17, 2, 2, 1, 0, 0}, // #171
+ {DBGFIELD("II_LDL") 1, false, false, 17, 2, 2, 1, 0, 0}, // #172
+ {DBGFIELD("II_LDPC") 1, false, false, 17, 2, 2, 1, 0, 0}, // #173
+ {DBGFIELD("II_LDR") 1, false, false, 17, 2, 2, 1, 0, 0}, // #174
+ {DBGFIELD("II_LDXC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #175
+ {DBGFIELD("II_LH") 1, false, false, 17, 2, 2, 1, 0, 0}, // #176
+ {DBGFIELD("II_LHE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #177
+ {DBGFIELD("II_LHU") 1, false, false, 17, 2, 2, 1, 0, 0}, // #178
+ {DBGFIELD("II_LHUE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #179
+ {DBGFIELD("II_LI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #180
+ {DBGFIELD("II_LL") 1, false, false, 17, 2, 2, 1, 0, 0}, // #181
+ {DBGFIELD("II_LLD") 1, false, false, 17, 2, 2, 1, 0, 0}, // #182
+ {DBGFIELD("II_LLE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #183
+ {DBGFIELD("II_LSA") 1, false, false, 1, 2, 1, 1, 0, 0}, // #184
+ {DBGFIELD("II_LUI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #185
+ {DBGFIELD("II_LUXC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #186
+ {DBGFIELD("II_LW") 1, false, false, 17, 2, 2, 1, 0, 0}, // #187
+ {DBGFIELD("II_LWC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #188
+ {DBGFIELD("II_LWC2") 1, false, false, 17, 2, 2, 1, 0, 0}, // #189
+ {DBGFIELD("II_LWC3") 1, false, false, 17, 2, 2, 1, 0, 0}, // #190
+ {DBGFIELD("II_LWE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #191
+ {DBGFIELD("II_LWL") 1, false, false, 17, 2, 2, 1, 0, 0}, // #192
+ {DBGFIELD("II_LWLE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #193
+ {DBGFIELD("II_LWM") 1, false, false, 17, 2, 2, 1, 0, 0}, // #194
+ {DBGFIELD("II_LWPC") 1, false, false, 17, 2, 2, 1, 0, 0}, // #195
+ {DBGFIELD("II_LWP") 1, false, false, 17, 2, 2, 1, 0, 0}, // #196
+ {DBGFIELD("II_LWR") 1, false, false, 17, 2, 2, 1, 0, 0}, // #197
+ {DBGFIELD("II_LWRE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #198
+ {DBGFIELD("II_LWUPC") 1, false, false, 17, 2, 2, 1, 0, 0}, // #199
+ {DBGFIELD("II_LWU") 1, false, false, 17, 2, 2, 1, 0, 0}, // #200
+ {DBGFIELD("II_LWXC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #201
+ {DBGFIELD("II_LWXS") 1, false, false, 17, 2, 2, 1, 0, 0}, // #202
+ {DBGFIELD("II_MADDF_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #203
+ {DBGFIELD("II_MADDF_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #204
+ {DBGFIELD("II_MADD_D") 1, false, false, 7, 2, 3, 1, 0, 0}, // #205
+ {DBGFIELD("II_MADD_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #206
+ {DBGFIELD("II_MAX_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #207
+ {DBGFIELD("II_MAXA_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #208
+ {DBGFIELD("II_MAX_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #209
+ {DBGFIELD("II_MAXA_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #210
+ {DBGFIELD("II_MFC0") 1, false, false, 19, 2, 2, 1, 0, 0}, // #211
+ {DBGFIELD("II_MFC2") 1, false, false, 21, 1, 1, 1, 0, 0}, // #212
+ {DBGFIELD("II_MFGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #213
+ {DBGFIELD("II_MFHC0") 1, false, false, 19, 2, 2, 1, 0, 0}, // #214
+ {DBGFIELD("II_MFHC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #215
+ {DBGFIELD("II_MFHGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #216
+ {DBGFIELD("II_MFTR") 1, false, false, 1, 2, 2, 1, 0, 0}, // #217
+ {DBGFIELD("II_MIN_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #218
+ {DBGFIELD("II_MINA_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #219
+ {DBGFIELD("II_MIN_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #220
+ {DBGFIELD("II_MINA_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #221
+ {DBGFIELD("II_MOD") 1, false, false, 11, 2, 4, 1, 0, 0}, // #222
+ {DBGFIELD("II_MODU") 1, false, false, 11, 2, 4, 1, 0, 0}, // #223
+ {DBGFIELD("II_MOVE") 1, false, false, 1, 2, 1, 1, 0, 0}, // #224
+ {DBGFIELD("II_MOVF_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #225
+ {DBGFIELD("II_MOVF") 1, false, false, 5, 2, 6, 1, 0, 0}, // #226
+ {DBGFIELD("II_MOVF_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #227
+ {DBGFIELD("II_MOVN_D") 1, false, false, 5, 2, 6, 1, 0, 0}, // #228
+ {DBGFIELD("II_MOVN") 1, false, false, 1, 2, 1, 1, 0, 0}, // #229
+ {DBGFIELD("II_MOVN_S") 1, false, false, 5, 2, 6, 1, 0, 0}, // #230
+ {DBGFIELD("II_MOVT_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #231
+ {DBGFIELD("II_MOVT") 1, false, false, 5, 2, 6, 1, 0, 0}, // #232
+ {DBGFIELD("II_MOVT_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #233
+ {DBGFIELD("II_MOVZ_D") 1, false, false, 5, 2, 6, 1, 0, 0}, // #234
+ {DBGFIELD("II_MOVZ") 1, false, false, 1, 2, 1, 1, 0, 0}, // #235
+ {DBGFIELD("II_MOVZ_S") 1, false, false, 5, 2, 6, 1, 0, 0}, // #236
+ {DBGFIELD("II_MSUBF_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #237
+ {DBGFIELD("II_MSUBF_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #238
+ {DBGFIELD("II_MSUB_D") 1, false, false, 7, 2, 3, 1, 0, 0}, // #239
+ {DBGFIELD("II_MSUB_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #240
+ {DBGFIELD("II_MTC0") 1, false, false, 19, 2, 7, 1, 0, 0}, // #241
+ {DBGFIELD("II_MTC2") 1, false, false, 21, 1, 1, 1, 0, 0}, // #242
+ {DBGFIELD("II_MTGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #243
+ {DBGFIELD("II_MTHC0") 1, false, false, 19, 2, 7, 1, 0, 0}, // #244
+ {DBGFIELD("II_MTHC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #245
+ {DBGFIELD("II_MTHGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #246
+ {DBGFIELD("II_MTTR") 1, false, false, 1, 2, 2, 1, 0, 0}, // #247
+ {DBGFIELD("II_MUH") 1, false, false, 9, 2, 6, 1, 0, 0}, // #248
+ {DBGFIELD("II_MUHU") 1, false, false, 9, 2, 6, 1, 0, 0}, // #249
+ {DBGFIELD("II_MUL") 1, false, false, 9, 2, 3, 1, 0, 0}, // #250
+ {DBGFIELD("II_MULU") 1, false, false, 9, 2, 6, 1, 0, 0}, // #251
+ {DBGFIELD("II_NMADD_D") 1, false, false, 7, 2, 3, 1, 0, 0}, // #252
+ {DBGFIELD("II_NMADD_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #253
+ {DBGFIELD("II_NMSUB_D") 1, false, false, 7, 2, 3, 1, 0, 0}, // #254
+ {DBGFIELD("II_NMSUB_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #255
+ {DBGFIELD("II_NOR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #256
+ {DBGFIELD("II_NOT") 1, false, false, 1, 2, 1, 1, 0, 0}, // #257
+ {DBGFIELD("II_OR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #258
+ {DBGFIELD("II_ORI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #259
+ {DBGFIELD("II_PAUSE") 1, false, false, 19, 2, 7, 1, 0, 0}, // #260
+ {DBGFIELD("II_PREF") 1, false, false, 17, 2, 1, 1, 0, 0}, // #261
+ {DBGFIELD("II_PREFE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #262
+ {DBGFIELD("II_RDHWR") 1, false, false, 1, 2, 2, 1, 0, 0}, // #263
+ {DBGFIELD("II_RDPGPR") 1, false, false, 19, 2, 7, 1, 0, 0}, // #264
+ {DBGFIELD("II_RECIP_D") 1, false, false, 28, 2, 11, 1, 0, 0}, // #265
+ {DBGFIELD("II_RECIP_S") 1, false, false, 30, 2, 12, 1, 0, 0}, // #266
+ {DBGFIELD("II_RINT_D") 1, false, false, 7, 2, 3, 1, 0, 0}, // #267
+ {DBGFIELD("II_RINT_S") 1, false, false, 7, 2, 3, 1, 0, 0}, // #268
+ {DBGFIELD("II_ROTR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #269
+ {DBGFIELD("II_ROTRV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #270
+ {DBGFIELD("II_ROUND") 1, false, false, 7, 2, 3, 1, 0, 0}, // #271
+ {DBGFIELD("II_RSQRT_D") 1, false, false, 28, 2, 11, 1, 0, 0}, // #272
+ {DBGFIELD("II_RSQRT_S") 1, false, false, 30, 2, 12, 1, 0, 0}, // #273
+ {DBGFIELD("II_RESTORE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #274
+ {DBGFIELD("II_SB") 1, false, false, 17, 2, 1, 1, 0, 0}, // #275
+ {DBGFIELD("II_SBE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #276
+ {DBGFIELD("II_SC") 1, false, false, 17, 2, 2, 1, 0, 0}, // #277
+ {DBGFIELD("II_SCD") 1, false, false, 17, 2, 1, 1, 0, 0}, // #278
+ {DBGFIELD("II_SCE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #279
+ {DBGFIELD("II_SD") 1, false, false, 17, 2, 1, 1, 0, 0}, // #280
+ {DBGFIELD("II_SDBBP") 1, false, false, 3, 2, 1, 1, 0, 0}, // #281
+ {DBGFIELD("II_SDC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #282
+ {DBGFIELD("II_SDC2") 1, false, false, 17, 2, 1, 1, 0, 0}, // #283
+ {DBGFIELD("II_SDC3") 1, false, false, 17, 2, 1, 1, 0, 0}, // #284
+ {DBGFIELD("II_SDL") 1, false, false, 17, 2, 1, 1, 0, 0}, // #285
+ {DBGFIELD("II_SDR") 1, false, false, 17, 2, 1, 1, 0, 0}, // #286
+ {DBGFIELD("II_SDXC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #287
+ {DBGFIELD("II_SEB") 1, false, false, 1, 2, 1, 1, 0, 0}, // #288
+ {DBGFIELD("II_SEH") 1, false, false, 1, 2, 1, 1, 0, 0}, // #289
+ {DBGFIELD("II_SELCCZ") 1, false, false, 1, 2, 1, 1, 0, 0}, // #290
+ {DBGFIELD("II_SELCCZ_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #291
+ {DBGFIELD("II_SELCCZ_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #292
+ {DBGFIELD("II_SEL_D") 1, false, false, 15, 2, 2, 1, 0, 0}, // #293
+ {DBGFIELD("II_SEL_S") 1, false, false, 15, 2, 2, 1, 0, 0}, // #294
+ {DBGFIELD("II_SEQ_SNE") 1, false, false, 1, 2, 1, 1, 0, 0}, // #295
+ {DBGFIELD("II_SEQI_SNEI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #296
+ {DBGFIELD("II_SH") 1, false, false, 17, 2, 1, 1, 0, 0}, // #297
+ {DBGFIELD("II_SHE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #298
+ {DBGFIELD("II_SLL") 1, false, false, 1, 2, 1, 1, 0, 0}, // #299
+ {DBGFIELD("II_SLLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #300
+ {DBGFIELD("II_SLT_SLTU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #301
+ {DBGFIELD("II_SLTI_SLTIU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #302
+ {DBGFIELD("II_SRA") 1, false, false, 1, 2, 1, 1, 0, 0}, // #303
+ {DBGFIELD("II_SRAV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #304
+ {DBGFIELD("II_SRL") 1, false, false, 1, 2, 1, 1, 0, 0}, // #305
+ {DBGFIELD("II_SRLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #306
+ {DBGFIELD("II_SSNOP") 1, false, false, 1, 2, 1, 1, 0, 0}, // #307
+ {DBGFIELD("II_SUB") 1, false, false, 1, 2, 1, 1, 0, 0}, // #308
+ {DBGFIELD("II_SUBU") 1, false, false, 1, 2, 1, 1, 0, 0}, // #309
+ {DBGFIELD("II_SUXC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #310
+ {DBGFIELD("II_SW") 1, false, false, 17, 2, 1, 1, 0, 0}, // #311
+ {DBGFIELD("II_SWC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #312
+ {DBGFIELD("II_SWC2") 1, false, false, 17, 2, 1, 1, 0, 0}, // #313
+ {DBGFIELD("II_SWC3") 1, false, false, 17, 2, 1, 1, 0, 0}, // #314
+ {DBGFIELD("II_SWE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #315
+ {DBGFIELD("II_SWL") 1, false, false, 17, 2, 1, 1, 0, 0}, // #316
+ {DBGFIELD("II_SWLE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #317
+ {DBGFIELD("II_SWM") 1, false, false, 17, 2, 1, 1, 0, 0}, // #318
+ {DBGFIELD("II_SWP") 1, false, false, 17, 2, 1, 1, 0, 0}, // #319
+ {DBGFIELD("II_SWR") 1, false, false, 17, 2, 1, 1, 0, 0}, // #320
+ {DBGFIELD("II_SWRE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #321
+ {DBGFIELD("II_SWXC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #322
+ {DBGFIELD("II_SYNC") 1, false, false, 17, 2, 1, 1, 0, 0}, // #323
+ {DBGFIELD("II_SYNCI") 1, false, false, 17, 2, 1, 1, 0, 0}, // #324
+ {DBGFIELD("II_SYSCALL") 1, false, false, 3, 2, 1, 1, 0, 0}, // #325
+ {DBGFIELD("II_SAVE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #326
+ {DBGFIELD("II_TEQ") 1, false, false, 3, 2, 1, 1, 0, 0}, // #327
+ {DBGFIELD("II_TEQI") 1, false, false, 3, 2, 1, 1, 0, 0}, // #328
+ {DBGFIELD("II_TGE") 1, false, false, 3, 2, 1, 1, 0, 0}, // #329
+ {DBGFIELD("II_TGEI") 1, false, false, 3, 2, 1, 1, 0, 0}, // #330
+ {DBGFIELD("II_TGEIU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #331
+ {DBGFIELD("II_TGEU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #332
+ {DBGFIELD("II_TLBGINV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #333
+ {DBGFIELD("II_TLBGINVF") 0, false, false, 0, 0, 0, 0, 0, 0}, // #334
+ {DBGFIELD("II_TLBGP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #335
+ {DBGFIELD("II_TLBGR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #336
+ {DBGFIELD("II_TLBGWI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #337
+ {DBGFIELD("II_TLBGWR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #338
+ {DBGFIELD("II_TLBINV") 1, false, false, 19, 2, 6, 1, 0, 0}, // #339
+ {DBGFIELD("II_TLBINVF") 1, false, false, 19, 2, 6, 1, 0, 0}, // #340
+ {DBGFIELD("II_TLBP") 1, false, false, 19, 2, 6, 1, 0, 0}, // #341
+ {DBGFIELD("II_TLBR") 1, false, false, 19, 2, 6, 1, 0, 0}, // #342
+ {DBGFIELD("II_TLBWI") 1, false, false, 19, 2, 6, 1, 0, 0}, // #343
+ {DBGFIELD("II_TLBWR") 1, false, false, 19, 2, 6, 1, 0, 0}, // #344
+ {DBGFIELD("II_TLT") 1, false, false, 3, 2, 1, 1, 0, 0}, // #345
+ {DBGFIELD("II_TLTI") 1, false, false, 3, 2, 1, 1, 0, 0}, // #346
+ {DBGFIELD("II_TTLTIU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #347
+ {DBGFIELD("II_TLTU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #348
+ {DBGFIELD("II_TNE") 1, false, false, 3, 2, 1, 1, 0, 0}, // #349
+ {DBGFIELD("II_TNEI") 1, false, false, 3, 2, 1, 1, 0, 0}, // #350
+ {DBGFIELD("II_TRUNC") 1, false, false, 7, 2, 3, 1, 0, 0}, // #351
+ {DBGFIELD("II_WAIT") 1, false, false, 19, 2, 7, 1, 0, 0}, // #352
+ {DBGFIELD("II_WRPGPR") 1, false, false, 19, 2, 7, 1, 0, 0}, // #353
+ {DBGFIELD("II_WSBH") 1, false, false, 1, 2, 1, 1, 0, 0}, // #354
+ {DBGFIELD("II_XOR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #355
+ {DBGFIELD("II_XORI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #356
+ {DBGFIELD("II_YIELD") 1, false, false, 19, 2, 3, 1, 0, 0}, // #357
+ {DBGFIELD("AND") 1, false, false, 1, 2, 1, 1, 0, 0}, // #358
+ {DBGFIELD("LUi") 1, false, false, 1, 2, 1, 1, 0, 0}, // #359
+ {DBGFIELD("NOR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #360
+ {DBGFIELD("OR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #361
+ {DBGFIELD("SLTi_SLTiu") 1, false, false, 1, 2, 1, 1, 0, 0}, // #362
+ {DBGFIELD("SUB") 1, false, false, 1, 2, 1, 1, 0, 0}, // #363
+ {DBGFIELD("SUBu") 1, false, false, 1, 2, 1, 1, 0, 0}, // #364
+ {DBGFIELD("XOR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #365
+ {DBGFIELD("B") 1, false, false, 3, 2, 1, 1, 0, 0}, // #366
+ {DBGFIELD("BAL") 1, false, false, 3, 2, 1, 1, 0, 0}, // #367
+ {DBGFIELD("BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL") 1, false, false, 3, 2, 1, 1, 0, 0}, // #368
+ {DBGFIELD("BEQ_BEQL_BNE_BNEL") 1, false, false, 3, 2, 1, 1, 0, 0}, // #369
+ {DBGFIELD("BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL") 1, false, false, 3, 2, 1, 1, 0, 0}, // #370
+ {DBGFIELD("BREAK") 1, false, false, 3, 2, 1, 1, 0, 0}, // #371
+ {DBGFIELD("DERET") 1, false, false, 3, 2, 1, 1, 0, 0}, // #372
+ {DBGFIELD("ERET") 1, false, false, 3, 2, 1, 1, 0, 0}, // #373
+ {DBGFIELD("ERETNC") 1, false, false, 3, 2, 1, 1, 0, 0}, // #374
+ {DBGFIELD("J_TAILCALL") 1, false, false, 3, 2, 1, 1, 0, 0}, // #375
+ {DBGFIELD("JR_TAILCALLREG_TAILCALLREGHB") 1, false, false, 3, 2, 1, 1, 0, 0}, // #376
+ {DBGFIELD("JR_HB") 1, false, false, 3, 2, 1, 1, 0, 0}, // #377
+ {DBGFIELD("PseudoIndirectBranch_PseudoIndirectHazardBranch") 0, false, false, 0, 0, 0, 0, 0, 0}, // #378
+ {DBGFIELD("PseudoReturn") 0, false, false, 0, 0, 0, 0, 0, 0}, // #379
+ {DBGFIELD("SDBBP") 1, false, false, 3, 2, 1, 1, 0, 0}, // #380
+ {DBGFIELD("SSNOP") 1, false, false, 1, 2, 1, 1, 0, 0}, // #381
+ {DBGFIELD("SYSCALL") 1, false, false, 3, 2, 1, 1, 0, 0}, // #382
+ {DBGFIELD("TEQ") 1, false, false, 3, 2, 1, 1, 0, 0}, // #383
+ {DBGFIELD("TEQI") 1, false, false, 3, 2, 1, 1, 0, 0}, // #384
+ {DBGFIELD("TGE") 1, false, false, 3, 2, 1, 1, 0, 0}, // #385
+ {DBGFIELD("TGEI") 1, false, false, 3, 2, 1, 1, 0, 0}, // #386
+ {DBGFIELD("TGEIU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #387
+ {DBGFIELD("TGEU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #388
+ {DBGFIELD("TLT") 1, false, false, 3, 2, 1, 1, 0, 0}, // #389
+ {DBGFIELD("TLTI") 1, false, false, 3, 2, 1, 1, 0, 0}, // #390
+ {DBGFIELD("TLTU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #391
+ {DBGFIELD("TNE") 1, false, false, 3, 2, 1, 1, 0, 0}, // #392
+ {DBGFIELD("TNEI") 1, false, false, 3, 2, 1, 1, 0, 0}, // #393
+ {DBGFIELD("TRAP") 1, false, false, 3, 2, 1, 1, 0, 0}, // #394
+ {DBGFIELD("TTLTIU") 1, false, false, 3, 2, 1, 1, 0, 0}, // #395
+ {DBGFIELD("WAIT") 1, false, false, 19, 2, 7, 1, 0, 0}, // #396
+ {DBGFIELD("PAUSE") 1, false, false, 19, 2, 7, 1, 0, 0}, // #397
+ {DBGFIELD("JAL") 1, false, false, 3, 2, 2, 1, 0, 0}, // #398
+ {DBGFIELD("JALR_JALRHBPseudo_JALRPseudo") 1, false, false, 3, 2, 2, 1, 0, 0}, // #399
+ {DBGFIELD("JALR_HB") 1, false, false, 3, 2, 2, 1, 0, 0}, // #400
+ {DBGFIELD("JALX") 1, false, false, 3, 2, 2, 1, 0, 0}, // #401
+ {DBGFIELD("TLBINV") 1, false, false, 19, 2, 6, 1, 0, 0}, // #402
+ {DBGFIELD("TLBINVF") 1, false, false, 19, 2, 6, 1, 0, 0}, // #403
+ {DBGFIELD("TLBP") 1, false, false, 19, 2, 6, 1, 0, 0}, // #404
+ {DBGFIELD("TLBR") 1, false, false, 19, 2, 6, 1, 0, 0}, // #405
+ {DBGFIELD("TLBWI") 1, false, false, 19, 2, 6, 1, 0, 0}, // #406
+ {DBGFIELD("TLBWR") 1, false, false, 19, 2, 6, 1, 0, 0}, // #407
+ {DBGFIELD("MFC0") 1, false, false, 19, 2, 2, 1, 0, 0}, // #408
+ {DBGFIELD("MTC0") 1, false, false, 19, 2, 7, 1, 0, 0}, // #409
+ {DBGFIELD("MFC2") 1, false, false, 21, 1, 1, 1, 0, 0}, // #410
+ {DBGFIELD("MTC2") 1, false, false, 21, 1, 1, 1, 0, 0}, // #411
+ {DBGFIELD("LB") 1, false, false, 17, 2, 2, 1, 0, 0}, // #412
+ {DBGFIELD("LBu") 1, false, false, 17, 2, 2, 1, 0, 0}, // #413
+ {DBGFIELD("LH") 1, false, false, 17, 2, 2, 1, 0, 0}, // #414
+ {DBGFIELD("LHu") 1, false, false, 17, 2, 2, 1, 0, 0}, // #415
+ {DBGFIELD("LW") 1, false, false, 17, 2, 2, 1, 0, 0}, // #416
+ {DBGFIELD("LL") 1, false, false, 17, 2, 2, 1, 0, 0}, // #417
+ {DBGFIELD("LWC2") 1, false, false, 17, 2, 2, 1, 0, 0}, // #418
+ {DBGFIELD("LWC3") 1, false, false, 17, 2, 2, 1, 0, 0}, // #419
+ {DBGFIELD("LDC2") 1, false, false, 17, 2, 2, 1, 0, 0}, // #420
+ {DBGFIELD("LDC3") 1, false, false, 17, 2, 2, 1, 0, 0}, // #421
+ {DBGFIELD("LBE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #422
+ {DBGFIELD("LBuE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #423
+ {DBGFIELD("LHE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #424
+ {DBGFIELD("LHuE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #425
+ {DBGFIELD("LWE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #426
+ {DBGFIELD("LLE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #427
+ {DBGFIELD("LWPC") 1, false, false, 17, 2, 2, 1, 0, 0}, // #428
+ {DBGFIELD("LWL") 1, false, false, 17, 2, 2, 1, 0, 0}, // #429
+ {DBGFIELD("LWR") 1, false, false, 17, 2, 2, 1, 0, 0}, // #430
+ {DBGFIELD("LWLE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #431
+ {DBGFIELD("LWRE") 1, false, false, 17, 2, 2, 1, 0, 0}, // #432
+ {DBGFIELD("SB") 1, false, false, 17, 2, 1, 1, 0, 0}, // #433
+ {DBGFIELD("SH") 1, false, false, 17, 2, 1, 1, 0, 0}, // #434
+ {DBGFIELD("SW") 1, false, false, 17, 2, 1, 1, 0, 0}, // #435
+ {DBGFIELD("SWC2") 1, false, false, 17, 2, 1, 1, 0, 0}, // #436
+ {DBGFIELD("SWC3") 1, false, false, 17, 2, 1, 1, 0, 0}, // #437
+ {DBGFIELD("SDC2") 1, false, false, 17, 2, 1, 1, 0, 0}, // #438
+ {DBGFIELD("SDC3") 1, false, false, 17, 2, 1, 1, 0, 0}, // #439
+ {DBGFIELD("SC") 1, false, false, 17, 2, 2, 1, 0, 0}, // #440
+ {DBGFIELD("SBE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #441
+ {DBGFIELD("SHE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #442
+ {DBGFIELD("SWE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #443
+ {DBGFIELD("SCE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #444
+ {DBGFIELD("SWL") 1, false, false, 17, 2, 1, 1, 0, 0}, // #445
+ {DBGFIELD("SWR") 1, false, false, 17, 2, 1, 1, 0, 0}, // #446
+ {DBGFIELD("SWLE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #447
+ {DBGFIELD("SWRE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #448
+ {DBGFIELD("PREF") 1, false, false, 17, 2, 1, 1, 0, 0}, // #449
+ {DBGFIELD("PREFE") 1, false, false, 17, 2, 1, 1, 0, 0}, // #450
+ {DBGFIELD("CACHE") 1, false, false, 17, 2, 3, 1, 0, 0}, // #451
+ {DBGFIELD("CACHEE") 1, false, false, 17, 2, 3, 1, 0, 0}, // #452
+ {DBGFIELD("SYNC") 1, false, false, 17, 2, 1, 1, 0, 0}, // #453
+ {DBGFIELD("SYNCI") 1, false, false, 17, 2, 1, 1, 0, 0}, // #454
+ {DBGFIELD("CLO") 1, false, false, 1, 2, 1, 1, 0, 0}, // #455
+ {DBGFIELD("CLZ") 1, false, false, 1, 2, 1, 1, 0, 0}, // #456
+ {DBGFIELD("DI") 1, false, false, 19, 2, 7, 1, 0, 0}, // #457
+ {DBGFIELD("EI") 1, false, false, 19, 2, 7, 1, 0, 0}, // #458
+ {DBGFIELD("MFHI_MFLO_PseudoMFHI_PseudoMFLO") 1, false, false, 1, 2, 3, 1, 0, 0}, // #459
+ {DBGFIELD("EHB") 1, false, false, 19, 2, 7, 1, 0, 0}, // #460
+ {DBGFIELD("RDHWR") 1, false, false, 1, 2, 2, 1, 0, 0}, // #461
+ {DBGFIELD("WSBH") 1, false, false, 1, 2, 1, 1, 0, 0}, // #462
+ {DBGFIELD("MOVN_I_I") 1, false, false, 1, 2, 1, 1, 0, 0}, // #463
+ {DBGFIELD("MOVZ_I_I") 1, false, false, 1, 2, 1, 1, 0, 0}, // #464
+ {DBGFIELD("DIV_PseudoSDIV_SDIV") 1, false, false, 11, 2, 4, 1, 0, 0}, // #465
+ {DBGFIELD("DIVU_PseudoUDIV_UDIV") 1, false, false, 13, 2, 5, 1, 0, 0}, // #466
+ {DBGFIELD("MUL") 1, false, false, 9, 2, 3, 1, 0, 0}, // #467
+ {DBGFIELD("MULT_PseudoMULT") 1, false, false, 1, 2, 1, 1, 0, 0}, // #468
+ {DBGFIELD("MULTu_PseudoMULTu") 1, false, false, 1, 2, 1, 1, 0, 0}, // #469
+ {DBGFIELD("MADD_PseudoMADD") 1, false, false, 9, 2, 1, 1, 0, 0}, // #470
+ {DBGFIELD("MADDU_PseudoMADDU") 1, false, false, 9, 2, 1, 1, 0, 0}, // #471
+ {DBGFIELD("MSUB_PseudoMSUB") 1, false, false, 9, 2, 1, 1, 0, 0}, // #472
+ {DBGFIELD("MSUBU_PseudoMSUBU") 1, false, false, 9, 2, 1, 1, 0, 0}, // #473
+ {DBGFIELD("MTHI_MTLO_PseudoMTLOHI") 1, false, false, 1, 2, 2, 1, 0, 0}, // #474
+ {DBGFIELD("EXT") 1, false, false, 1, 2, 1, 1, 0, 0}, // #475
+ {DBGFIELD("INS") 1, false, false, 1, 2, 1, 1, 0, 0}, // #476
+ {DBGFIELD("ADD") 1, false, false, 1, 2, 1, 1, 0, 0}, // #477
+ {DBGFIELD("ADDi") 1, false, false, 1, 2, 1, 1, 0, 0}, // #478
+ {DBGFIELD("ADDiu") 1, false, false, 1, 2, 1, 1, 0, 0}, // #479
+ {DBGFIELD("ANDi") 1, false, false, 1, 2, 1, 1, 0, 0}, // #480
+ {DBGFIELD("ORi") 1, false, false, 1, 2, 1, 1, 0, 0}, // #481
+ {DBGFIELD("ROTR") 1, false, false, 1, 2, 1, 1, 0, 0}, // #482
+ {DBGFIELD("SEB") 1, false, false, 1, 2, 1, 1, 0, 0}, // #483
+ {DBGFIELD("SEH") 1, false, false, 1, 2, 1, 1, 0, 0}, // #484
+ {DBGFIELD("SLT_SLTu") 1, false, false, 1, 2, 1, 1, 0, 0}, // #485
+ {DBGFIELD("SLL") 1, false, false, 1, 2, 1, 1, 0, 0}, // #486
+ {DBGFIELD("SRA") 1, false, false, 1, 2, 1, 1, 0, 0}, // #487
+ {DBGFIELD("SRL") 1, false, false, 1, 2, 1, 1, 0, 0}, // #488
+ {DBGFIELD("XORi") 1, false, false, 1, 2, 1, 1, 0, 0}, // #489
+ {DBGFIELD("ADDu") 1, false, false, 1, 2, 1, 1, 0, 0}, // #490
+ {DBGFIELD("SLLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #491
+ {DBGFIELD("SRAV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #492
+ {DBGFIELD("SRLV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #493
+ {DBGFIELD("LSA") 1, false, false, 1, 2, 1, 1, 0, 0}, // #494
+ {DBGFIELD("COPY") 1, false, false, 1, 2, 1, 1, 0, 0}, // #495
+ {DBGFIELD("VSHF_B_VSHF_D_VSHF_H_VSHF_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #496
+ {DBGFIELD("BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #497
+ {DBGFIELD("BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #498
+ {DBGFIELD("INSERT_B_INSERT_D_INSERT_H_INSERT_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #499
+ {DBGFIELD("SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #500
+ {DBGFIELD("BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #501
+ {DBGFIELD("BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #502
+ {DBGFIELD("BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #503
+ {DBGFIELD("BSELI_B_BSEL_V") 1, false, false, 15, 2, 2, 1, 0, 0}, // #504
+ {DBGFIELD("BMNZI_B_BMNZ_V_BMZI_B_BMZ_V") 1, false, false, 15, 2, 2, 1, 0, 0}, // #505
+ {DBGFIELD("PCNT_B_PCNT_D_PCNT_H_PCNT_W") 1, false, false, 15, 2, 7, 1, 0, 0}, // #506
+ {DBGFIELD("SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W") 1, false, false, 15, 2, 7, 1, 0, 0}, // #507
+ {DBGFIELD("BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #508
+ {DBGFIELD("CFCMSA_CTCMSA") 1, false, false, 15, 2, 1, 1, 0, 0}, // #509
+ {DBGFIELD("FABS_S_FABS_D32_FABS_D64") 1, false, false, 15, 2, 6, 1, 0, 0}, // #510
+ {DBGFIELD("MOVF_D32_MOVF_D64") 1, false, false, 15, 2, 6, 1, 0, 0}, // #511
+ {DBGFIELD("MOVF_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #512
+ {DBGFIELD("MOVT_D32_MOVT_D64") 1, false, false, 15, 2, 6, 1, 0, 0}, // #513
+ {DBGFIELD("MOVT_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #514
+ {DBGFIELD("FMOV_D32_FMOV_D64") 1, false, false, 5, 2, 6, 1, 0, 0}, // #515
+ {DBGFIELD("FMOV_S") 1, false, false, 5, 2, 6, 1, 0, 0}, // #516
+ {DBGFIELD("FNEG_S_FNEG_D32_FNEG_D64") 1, false, false, 15, 2, 6, 1, 0, 0}, // #517
+ {DBGFIELD("ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #518
+ {DBGFIELD("ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #519
+ {DBGFIELD("ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #520
+ {DBGFIELD("ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #521
+ {DBGFIELD("AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #522
+ {DBGFIELD("SHF_B_SHF_H_SHF_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #523
+ {DBGFIELD("FILL_B_FILL_D_FILL_H_FILL_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #524
+ {DBGFIELD("SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #525
+ {DBGFIELD("MOVE_V") 1, false, false, 15, 2, 1, 1, 0, 0}, // #526
+ {DBGFIELD("LDI_B_LDI_D_LDI_H_LDI_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #527
+ {DBGFIELD("AND_V_NOR_V_OR_V_XOR_V") 1, false, false, 15, 2, 1, 1, 0, 0}, // #528
+ {DBGFIELD("ANDI_B_NORI_B_ORI_B_XORI_B") 1, false, false, 15, 2, 1, 1, 0, 0}, // #529
+ {DBGFIELD("FEXP2_D_FEXP2_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #530
+ {DBGFIELD("CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #531
+ {DBGFIELD("CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #532
+ {DBGFIELD("CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #533
+ {DBGFIELD("CMP_UN_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #534
+ {DBGFIELD("CMP_UN_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #535
+ {DBGFIELD("CMP_UEQ_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #536
+ {DBGFIELD("CMP_UEQ_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #537
+ {DBGFIELD("CMP_EQ_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #538
+ {DBGFIELD("CMP_EQ_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #539
+ {DBGFIELD("CMP_LT_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #540
+ {DBGFIELD("CMP_LT_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #541
+ {DBGFIELD("CMP_ULT_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #542
+ {DBGFIELD("CMP_ULT_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #543
+ {DBGFIELD("CMP_LE_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #544
+ {DBGFIELD("CMP_LE_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #545
+ {DBGFIELD("CMP_ULE_D") 1, false, false, 15, 2, 6, 1, 0, 0}, // #546
+ {DBGFIELD("CMP_ULE_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #547
+ {DBGFIELD("FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #548
+ {DBGFIELD("FSUEQ_D_FSUEQ_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #549
+ {DBGFIELD("FSULE_D_FSULE_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #550
+ {DBGFIELD("FSULT_D_FSULT_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #551
+ {DBGFIELD("FSUNE_D_FSUNE_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #552
+ {DBGFIELD("FSUN_D_FSUN_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #553
+ {DBGFIELD("FCAF_D_FCAF_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #554
+ {DBGFIELD("FCEQ_D_FCEQ_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #555
+ {DBGFIELD("FCLE_D_FCLE_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #556
+ {DBGFIELD("FCLT_D_FCLT_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #557
+ {DBGFIELD("FCNE_D_FCNE_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #558
+ {DBGFIELD("FCOR_D_FCOR_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #559
+ {DBGFIELD("FCUEQ_D_FCUEQ_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #560
+ {DBGFIELD("FCULE_D_FCULE_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #561
+ {DBGFIELD("FCULT_D_FCULT_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #562
+ {DBGFIELD("FCUNE_D_FCUNE_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #563
+ {DBGFIELD("FCUN_D_FCUN_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #564
+ {DBGFIELD("FABS_D_FABS_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #565
+ {DBGFIELD("FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #566
+ {DBGFIELD("FFQL_D_FFQL_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #567
+ {DBGFIELD("FFQR_D_FFQR_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #568
+ {DBGFIELD("FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #569
+ {DBGFIELD("FRINT_D_FRINT_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #570
+ {DBGFIELD("FTQ_H_FTQ_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #571
+ {DBGFIELD("FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #572
+ {DBGFIELD("FEXDO_H_FEXDO_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #573
+ {DBGFIELD("FEXUPL_D_FEXUPL_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #574
+ {DBGFIELD("FEXUPR_D_FEXUPR_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #575
+ {DBGFIELD("FCLASS_D_FCLASS_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #576
+ {DBGFIELD("FMAX_A_D_FMAX_A_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #577
+ {DBGFIELD("FMAX_D_FMAX_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #578
+ {DBGFIELD("FMIN_A_D_FMIN_A_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #579
+ {DBGFIELD("FMIN_D_FMIN_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #580
+ {DBGFIELD("FLOG2_D_FLOG2_W") 1, false, false, 15, 2, 6, 1, 0, 0}, // #581
+ {DBGFIELD("ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #582
+ {DBGFIELD("ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #583
+ {DBGFIELD("INSVE_B_INSVE_D_INSVE_H_INSVE_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #584
+ {DBGFIELD("SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #585
+ {DBGFIELD("SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #586
+ {DBGFIELD("SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #587
+ {DBGFIELD("SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #588
+ {DBGFIELD("SUBV_B_SUBV_D_SUBV_H_SUBV_W") 1, false, false, 15, 2, 2, 1, 0, 0}, // #589
+ {DBGFIELD("MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W") 1, false, false, 34, 1, 4, 1, 0, 0}, // #590
+ {DBGFIELD("DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W") 1, false, false, 34, 1, 4, 1, 0, 0}, // #591
+ {DBGFIELD("HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #592
+ {DBGFIELD("HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #593
+ {DBGFIELD("MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #594
+ {DBGFIELD("MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #595
+ {DBGFIELD("MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #596
+ {DBGFIELD("MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #597
+ {DBGFIELD("SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #598
+ {DBGFIELD("SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #599
+ {DBGFIELD("SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #600
+ {DBGFIELD("SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #601
+ {DBGFIELD("SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #602
+ {DBGFIELD("PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #603
+ {DBGFIELD("NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W") 1, false, false, 15, 2, 1, 1, 0, 0}, // #604
+ {DBGFIELD("FADD_D32_FADD_D64") 1, false, false, 15, 2, 6, 1, 0, 0}, // #605
+ {DBGFIELD("FADD_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #606
+ {DBGFIELD("FMUL_D32_FMUL_D64") 1, false, false, 7, 2, 3, 1, 0, 0}, // #607
+ {DBGFIELD("FMUL_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #608
+ {DBGFIELD("FSUB_D32_FSUB_D64") 1, false, false, 15, 2, 6, 1, 0, 0}, // #609
+ {DBGFIELD("FSUB_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #610
+ {DBGFIELD("TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S") 1, false, false, 7, 2, 3, 1, 0, 0}, // #611
+ {DBGFIELD("CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S") 1, false, false, 7, 2, 3, 1, 0, 0}, // #612
+ {DBGFIELD("C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64") 1, false, false, 15, 2, 2, 1, 0, 0}, // #613
+ {DBGFIELD("C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S") 1, false, false, 15, 2, 2, 1, 0, 0}, // #614
+ {DBGFIELD("FCMP_D32_FCMP_D64") 1, false, false, 15, 2, 2, 1, 0, 0}, // #615
+ {DBGFIELD("FCMP_S32") 1, false, false, 15, 2, 2, 1, 0, 0}, // #616
+ {DBGFIELD("PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #617
+ {DBGFIELD("FDIV_S") 1, false, false, 24, 2, 10, 1, 0, 0}, // #618
+ {DBGFIELD("FDIV_D32_FDIV_D64") 1, false, false, 22, 2, 9, 1, 0, 0}, // #619
+ {DBGFIELD("FSQRT_S") 1, false, false, 24, 2, 10, 1, 0, 0}, // #620
+ {DBGFIELD("FSQRT_D32_FSQRT_D64") 1, false, false, 22, 2, 8, 1, 0, 0}, // #621
+ {DBGFIELD("FRCP_D_FRCP_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #622
+ {DBGFIELD("FRSQRT_D_FRSQRT_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #623
+ {DBGFIELD("RECIP_D32_RECIP_D64") 1, false, false, 28, 2, 11, 1, 0, 0}, // #624
+ {DBGFIELD("RSQRT_D32_RSQRT_D64") 1, false, false, 28, 2, 11, 1, 0, 0}, // #625
+ {DBGFIELD("RECIP_S") 1, false, false, 30, 2, 12, 1, 0, 0}, // #626
+ {DBGFIELD("RSQRT_S") 1, false, false, 30, 2, 12, 1, 0, 0}, // #627
+ {DBGFIELD("FMADD_D_FMADD_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #628
+ {DBGFIELD("FMSUB_D_FMSUB_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #629
+ {DBGFIELD("FDIV_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #630
+ {DBGFIELD("FDIV_D") 1, false, false, 7, 2, 3, 1, 0, 0}, // #631
+ {DBGFIELD("FSQRT_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #632
+ {DBGFIELD("FSQRT_D") 1, false, false, 7, 2, 3, 1, 0, 0}, // #633
+ {DBGFIELD("FMUL_D_FMUL_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #634
+ {DBGFIELD("FADD_D_FADD_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #635
+ {DBGFIELD("FSUB_D_FSUB_W") 1, false, false, 7, 2, 3, 1, 0, 0}, // #636
+ {DBGFIELD("DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #637
+ {DBGFIELD("DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #638
+ {DBGFIELD("DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #639
+ {DBGFIELD("MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #640
+ {DBGFIELD("MADDV_B_MADDV_D_MADDV_H_MADDV_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #641
+ {DBGFIELD("MULV_B_MULV_D_MULV_H_MULV_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #642
+ {DBGFIELD("MADDR_Q_H_MADDR_Q_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #643
+ {DBGFIELD("MADD_Q_H_MADD_Q_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #644
+ {DBGFIELD("MSUBR_Q_H_MSUBR_Q_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #645
+ {DBGFIELD("MSUB_Q_H_MSUB_Q_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #646
+ {DBGFIELD("MULR_Q_H_MULR_Q_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #647
+ {DBGFIELD("MUL_Q_H_MUL_Q_W") 1, false, false, 15, 2, 3, 1, 0, 0}, // #648
+ {DBGFIELD("MADD_D32_MADD_D64") 1, false, false, 7, 2, 3, 1, 0, 0}, // #649
+ {DBGFIELD("MADD_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #650
+ {DBGFIELD("MSUB_D32_MSUB_D64") 1, false, false, 7, 2, 3, 1, 0, 0}, // #651
+ {DBGFIELD("MSUB_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #652
+ {DBGFIELD("NMADD_D32_NMADD_D64") 1, false, false, 7, 2, 3, 1, 0, 0}, // #653
+ {DBGFIELD("NMADD_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #654
+ {DBGFIELD("NMSUB_D32_NMSUB_D64") 1, false, false, 7, 2, 3, 1, 0, 0}, // #655
+ {DBGFIELD("NMSUB_S") 1, false, false, 15, 2, 6, 1, 0, 0}, // #656
+ {DBGFIELD("CTC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #657
+ {DBGFIELD("MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64") 1, false, false, 5, 2, 2, 1, 0, 0}, // #658
+ {DBGFIELD("MTHC1_D32_MTHC1_D64") 1, false, false, 5, 2, 2, 1, 0, 0}, // #659
+ {DBGFIELD("COPY_U_B_COPY_U_H_COPY_U_W") 1, false, false, 5, 2, 2, 1, 0, 0}, // #660
+ {DBGFIELD("COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W") 1, false, false, 5, 2, 2, 1, 0, 0}, // #661
+ {DBGFIELD("BC1F") 1, false, false, 15, 2, 2, 1, 0, 0}, // #662
+ {DBGFIELD("BC1FL") 1, false, false, 15, 2, 2, 1, 0, 0}, // #663
+ {DBGFIELD("BC1T") 1, false, false, 15, 2, 2, 1, 0, 0}, // #664
+ {DBGFIELD("BC1TL") 1, false, false, 15, 2, 2, 1, 0, 0}, // #665
+ {DBGFIELD("CFC1") 1, false, false, 5, 2, 2, 1, 0, 0}, // #666
+ {DBGFIELD("MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64") 1, false, false, 5, 2, 2, 1, 0, 0}, // #667
+ {DBGFIELD("MFHC1_D32_MFHC1_D64") 1, false, false, 5, 2, 2, 1, 0, 0}, // #668
+ {DBGFIELD("MOVF_I") 1, false, false, 5, 2, 6, 1, 0, 0}, // #669
+ {DBGFIELD("MOVT_I") 1, false, false, 5, 2, 6, 1, 0, 0}, // #670
+ {DBGFIELD("SDC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #671
+ {DBGFIELD("SDXC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #672
+ {DBGFIELD("SUXC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #673
+ {DBGFIELD("SWC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #674
+ {DBGFIELD("SWXC1") 1, false, false, 32, 2, 1, 1, 0, 0}, // #675
+ {DBGFIELD("ST_B_ST_D_ST_H_ST_W") 1, false, false, 32, 2, 1, 1, 0, 0}, // #676
+ {DBGFIELD("MOVN_I_D32_MOVN_I_D64") 1, false, false, 5, 2, 6, 1, 0, 0}, // #677
+ {DBGFIELD("MOVN_I_S") 1, false, false, 5, 2, 6, 1, 0, 0}, // #678
+ {DBGFIELD("MOVZ_I_D32_MOVZ_I_D64") 1, false, false, 5, 2, 6, 1, 0, 0}, // #679
+ {DBGFIELD("MOVZ_I_S") 1, false, false, 5, 2, 6, 1, 0, 0}, // #680
+ {DBGFIELD("LDC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #681
+ {DBGFIELD("LDXC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #682
+ {DBGFIELD("LWC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #683
+ {DBGFIELD("LWXC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #684
+ {DBGFIELD("LUXC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #685
+ {DBGFIELD("LD_B_LD_D_LD_H_LD_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #686
+ {DBGFIELD("CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S") 1, false, false, 7, 2, 3, 1, 0, 0}, // #687
+ {DBGFIELD("FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S") 1, false, false, 7, 2, 3, 1, 0, 0}, // #688
+ {DBGFIELD("ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S") 1, false, false, 7, 2, 3, 1, 0, 0}, // #689
+ {DBGFIELD("ROTRV") 1, false, false, 1, 2, 1, 1, 0, 0}, // #690
+ {DBGFIELD("EXTRV_RS_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #691
+ {DBGFIELD("EXTRV_R_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #692
+ {DBGFIELD("EXTRV_S_H") 1, false, false, 35, 1, 13, 1, 0, 0}, // #693
+ {DBGFIELD("EXTRV_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #694
+ {DBGFIELD("EXTR_RS_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #695
+ {DBGFIELD("EXTR_R_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #696
+ {DBGFIELD("EXTR_S_H") 1, false, false, 35, 1, 13, 1, 0, 0}, // #697
+ {DBGFIELD("EXTR_W") 1, false, false, 35, 1, 13, 1, 0, 0}, // #698
+ {DBGFIELD("INSV") 1, false, false, 35, 1, 13, 1, 0, 0}, // #699
+ {DBGFIELD("MTHLIP") 1, false, false, 35, 1, 3, 1, 0, 0}, // #700
+ {DBGFIELD("MTHI_DSP") 1, false, false, 35, 1, 3, 1, 0, 0}, // #701
+ {DBGFIELD("MTLO_DSP") 1, false, false, 35, 1, 3, 1, 0, 0}, // #702
+ {DBGFIELD("ABSQ_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #703
+ {DBGFIELD("ABSQ_S_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #704
+ {DBGFIELD("ADDQ_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #705
+ {DBGFIELD("ADDQ_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #706
+ {DBGFIELD("ADDQ_S_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #707
+ {DBGFIELD("ADDSC") 1, false, false, 35, 1, 2, 1, 0, 0}, // #708
+ {DBGFIELD("ADDU_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #709
+ {DBGFIELD("ADDU_S_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #710
+ {DBGFIELD("ADDWC") 1, false, false, 35, 1, 2, 1, 0, 0}, // #711
+ {DBGFIELD("BITREV") 1, false, false, 35, 1, 2, 1, 0, 0}, // #712
+ {DBGFIELD("BPOSGE32") 1, false, false, 35, 1, 2, 1, 0, 0}, // #713
+ {DBGFIELD("CMPGU_EQ_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #714
+ {DBGFIELD("CMPGU_LE_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #715
+ {DBGFIELD("CMPGU_LT_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #716
+ {DBGFIELD("CMPU_EQ_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #717
+ {DBGFIELD("CMPU_LE_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #718
+ {DBGFIELD("CMPU_LT_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #719
+ {DBGFIELD("CMP_EQ_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #720
+ {DBGFIELD("CMP_LE_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #721
+ {DBGFIELD("CMP_LT_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #722
+ {DBGFIELD("DPAQ_SA_L_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #723
+ {DBGFIELD("DPAQ_S_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #724
+ {DBGFIELD("DPAU_H_QBL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #725
+ {DBGFIELD("DPAU_H_QBR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #726
+ {DBGFIELD("DPSQ_SA_L_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #727
+ {DBGFIELD("DPSQ_S_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #728
+ {DBGFIELD("DPSU_H_QBL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #729
+ {DBGFIELD("DPSU_H_QBR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #730
+ {DBGFIELD("EXTPDPV") 1, false, false, 35, 1, 2, 1, 0, 0}, // #731
+ {DBGFIELD("EXTPDP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #732
+ {DBGFIELD("EXTPV") 1, false, false, 35, 1, 2, 1, 0, 0}, // #733
+ {DBGFIELD("EXTP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #734
+ {DBGFIELD("LBUX") 1, false, false, 35, 1, 2, 1, 0, 0}, // #735
+ {DBGFIELD("LHX") 1, false, false, 35, 1, 2, 1, 0, 0}, // #736
+ {DBGFIELD("LWX") 1, false, false, 35, 1, 2, 1, 0, 0}, // #737
+ {DBGFIELD("MADDU_DSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #738
+ {DBGFIELD("MADD_DSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #739
+ {DBGFIELD("MAQ_SA_W_PHL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #740
+ {DBGFIELD("MAQ_SA_W_PHR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #741
+ {DBGFIELD("MAQ_S_W_PHL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #742
+ {DBGFIELD("MAQ_S_W_PHR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #743
+ {DBGFIELD("MFHI_DSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #744
+ {DBGFIELD("MFLO_DSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #745
+ {DBGFIELD("MODSUB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #746
+ {DBGFIELD("MSUBU_DSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #747
+ {DBGFIELD("MSUB_DSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #748
+ {DBGFIELD("MULEQ_S_W_PHL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #749
+ {DBGFIELD("MULEQ_S_W_PHR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #750
+ {DBGFIELD("MULEU_S_PH_QBL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #751
+ {DBGFIELD("MULEU_S_PH_QBR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #752
+ {DBGFIELD("MULQ_RS_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #753
+ {DBGFIELD("MULSAQ_S_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #754
+ {DBGFIELD("MULTU_DSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #755
+ {DBGFIELD("MULT_DSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #756
+ {DBGFIELD("PACKRL_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #757
+ {DBGFIELD("PICK_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #758
+ {DBGFIELD("PICK_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #759
+ {DBGFIELD("PRECEQU_PH_QBLA") 1, false, false, 35, 1, 2, 1, 0, 0}, // #760
+ {DBGFIELD("PRECEQU_PH_QBL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #761
+ {DBGFIELD("PRECEQU_PH_QBRA") 1, false, false, 35, 1, 2, 1, 0, 0}, // #762
+ {DBGFIELD("PRECEQU_PH_QBR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #763
+ {DBGFIELD("PRECEQ_W_PHL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #764
+ {DBGFIELD("PRECEQ_W_PHR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #765
+ {DBGFIELD("PRECEU_PH_QBLA") 1, false, false, 35, 1, 2, 1, 0, 0}, // #766
+ {DBGFIELD("PRECEU_PH_QBL") 1, false, false, 35, 1, 2, 1, 0, 0}, // #767
+ {DBGFIELD("PRECEU_PH_QBRA") 1, false, false, 35, 1, 2, 1, 0, 0}, // #768
+ {DBGFIELD("PRECEU_PH_QBR") 1, false, false, 35, 1, 2, 1, 0, 0}, // #769
+ {DBGFIELD("PRECRQU_S_QB_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #770
+ {DBGFIELD("PRECRQ_PH_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #771
+ {DBGFIELD("PRECRQ_QB_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #772
+ {DBGFIELD("PRECRQ_RS_PH_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #773
+ {DBGFIELD("RADDU_W_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #774
+ {DBGFIELD("RDDSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #775
+ {DBGFIELD("REPLV_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #776
+ {DBGFIELD("REPLV_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #777
+ {DBGFIELD("REPL_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #778
+ {DBGFIELD("REPL_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #779
+ {DBGFIELD("SHILOV") 1, false, false, 35, 1, 2, 1, 0, 0}, // #780
+ {DBGFIELD("SHILO") 1, false, false, 35, 1, 2, 1, 0, 0}, // #781
+ {DBGFIELD("SHLLV_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #782
+ {DBGFIELD("SHLLV_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #783
+ {DBGFIELD("SHLLV_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #784
+ {DBGFIELD("SHLLV_S_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #785
+ {DBGFIELD("SHLL_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #786
+ {DBGFIELD("SHLL_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #787
+ {DBGFIELD("SHLL_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #788
+ {DBGFIELD("SHLL_S_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #789
+ {DBGFIELD("SHRAV_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #790
+ {DBGFIELD("SHRAV_R_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #791
+ {DBGFIELD("SHRAV_R_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #792
+ {DBGFIELD("SHRA_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #793
+ {DBGFIELD("SHRA_R_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #794
+ {DBGFIELD("SHRA_R_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #795
+ {DBGFIELD("SHRLV_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #796
+ {DBGFIELD("SHRL_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #797
+ {DBGFIELD("SUBQ_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #798
+ {DBGFIELD("SUBQ_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #799
+ {DBGFIELD("SUBQ_S_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #800
+ {DBGFIELD("SUBU_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #801
+ {DBGFIELD("SUBU_S_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #802
+ {DBGFIELD("WRDSP") 1, false, false, 35, 1, 2, 1, 0, 0}, // #803
+ {DBGFIELD("ABSQ_S_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #804
+ {DBGFIELD("ADDQH_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #805
+ {DBGFIELD("ADDQH_R_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #806
+ {DBGFIELD("ADDQH_R_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #807
+ {DBGFIELD("ADDQH_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #808
+ {DBGFIELD("ADDUH_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #809
+ {DBGFIELD("ADDUH_R_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #810
+ {DBGFIELD("ADDU_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #811
+ {DBGFIELD("ADDU_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #812
+ {DBGFIELD("APPEND") 1, false, false, 35, 1, 2, 1, 0, 0}, // #813
+ {DBGFIELD("BALIGN") 1, false, false, 35, 1, 2, 1, 0, 0}, // #814
+ {DBGFIELD("CMPGDU_EQ_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #815
+ {DBGFIELD("CMPGDU_LE_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #816
+ {DBGFIELD("CMPGDU_LT_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #817
+ {DBGFIELD("DPA_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #818
+ {DBGFIELD("DPAQX_SA_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #819
+ {DBGFIELD("DPAQX_S_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #820
+ {DBGFIELD("DPAX_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #821
+ {DBGFIELD("DPS_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #822
+ {DBGFIELD("DPSQX_S_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #823
+ {DBGFIELD("DPSQX_SA_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #824
+ {DBGFIELD("DPSX_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #825
+ {DBGFIELD("MUL_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #826
+ {DBGFIELD("MUL_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #827
+ {DBGFIELD("MULQ_RS_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #828
+ {DBGFIELD("MULQ_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #829
+ {DBGFIELD("MULQ_S_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #830
+ {DBGFIELD("MULSA_W_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #831
+ {DBGFIELD("PRECR_QB_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #832
+ {DBGFIELD("PRECR_SRA_PH_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #833
+ {DBGFIELD("PRECR_SRA_R_PH_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #834
+ {DBGFIELD("PREPEND") 1, false, false, 35, 1, 2, 1, 0, 0}, // #835
+ {DBGFIELD("SHRA_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #836
+ {DBGFIELD("SHRA_R_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #837
+ {DBGFIELD("SHRAV_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #838
+ {DBGFIELD("SHRAV_R_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #839
+ {DBGFIELD("SHRL_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #840
+ {DBGFIELD("SHRLV_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #841
+ {DBGFIELD("SUBQH_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #842
+ {DBGFIELD("SUBQH_R_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #843
+ {DBGFIELD("SUBQH_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #844
+ {DBGFIELD("SUBQH_R_W") 1, false, false, 35, 1, 2, 1, 0, 0}, // #845
+ {DBGFIELD("SUBU_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #846
+ {DBGFIELD("SUBU_S_PH") 1, false, false, 35, 1, 2, 1, 0, 0}, // #847
+ {DBGFIELD("SUBUH_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #848
+ {DBGFIELD("SUBUH_R_QB") 1, false, false, 35, 1, 2, 1, 0, 0}, // #849
+ {DBGFIELD("ABSQ_S_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #850
+ {DBGFIELD("ABSQ_S_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #851
+ {DBGFIELD("ADDQ_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #852
+ {DBGFIELD("ADDQ_S_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #853
+ {DBGFIELD("ADDQ_S_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #854
+ {DBGFIELD("ADDSC_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #855
+ {DBGFIELD("ADDU_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #856
+ {DBGFIELD("ADDU_S_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #857
+ {DBGFIELD("ADDWC_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #858
+ {DBGFIELD("BITREV_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #859
+ {DBGFIELD("BPOSGE32_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #860
+ {DBGFIELD("CMPGU_EQ_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #861
+ {DBGFIELD("CMPGU_LE_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #862
+ {DBGFIELD("CMPGU_LT_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #863
+ {DBGFIELD("CMPU_EQ_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #864
+ {DBGFIELD("CMPU_LE_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #865
+ {DBGFIELD("CMPU_LT_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #866
+ {DBGFIELD("CMP_EQ_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #867
+ {DBGFIELD("CMP_LE_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #868
+ {DBGFIELD("CMP_LT_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #869
+ {DBGFIELD("DPAQ_SA_L_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #870
+ {DBGFIELD("DPAQ_S_W_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #871
+ {DBGFIELD("DPAU_H_QBL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #872
+ {DBGFIELD("DPAU_H_QBR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #873
+ {DBGFIELD("DPSQ_SA_L_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #874
+ {DBGFIELD("DPSQ_S_W_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #875
+ {DBGFIELD("DPSU_H_QBL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #876
+ {DBGFIELD("DPSU_H_QBR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #877
+ {DBGFIELD("EXTPDPV_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #878
+ {DBGFIELD("EXTPDP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #879
+ {DBGFIELD("EXTPV_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #880
+ {DBGFIELD("EXTP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #881
+ {DBGFIELD("EXTRV_RS_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #882
+ {DBGFIELD("EXTRV_R_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #883
+ {DBGFIELD("EXTRV_S_H_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #884
+ {DBGFIELD("EXTRV_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #885
+ {DBGFIELD("EXTR_RS_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #886
+ {DBGFIELD("EXTR_R_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #887
+ {DBGFIELD("EXTR_S_H_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #888
+ {DBGFIELD("EXTR_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #889
+ {DBGFIELD("INSV_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #890
+ {DBGFIELD("LBUX_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #891
+ {DBGFIELD("LHX_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #892
+ {DBGFIELD("LWX_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #893
+ {DBGFIELD("MADDU_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #894
+ {DBGFIELD("MADD_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #895
+ {DBGFIELD("MAQ_SA_W_PHL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #896
+ {DBGFIELD("MAQ_SA_W_PHR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #897
+ {DBGFIELD("MAQ_S_W_PHL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #898
+ {DBGFIELD("MAQ_S_W_PHR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #899
+ {DBGFIELD("MFHI_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #900
+ {DBGFIELD("MFLO_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #901
+ {DBGFIELD("MODSUB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #902
+ {DBGFIELD("MOVEP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #903
+ {DBGFIELD("MOVEP_MMR6") 1, false, false, 35, 1, 2, 1, 0, 0}, // #904
+ {DBGFIELD("MOVN_I_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #905
+ {DBGFIELD("MOVZ_I_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #906
+ {DBGFIELD("MSUBU_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #907
+ {DBGFIELD("MSUB_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #908
+ {DBGFIELD("MTHI_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #909
+ {DBGFIELD("MTHLIP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #910
+ {DBGFIELD("MTLO_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #911
+ {DBGFIELD("MULEQ_S_W_PHL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #912
+ {DBGFIELD("MULEQ_S_W_PHR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #913
+ {DBGFIELD("MULEU_S_PH_QBL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #914
+ {DBGFIELD("MULEU_S_PH_QBR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #915
+ {DBGFIELD("MULQ_RS_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #916
+ {DBGFIELD("MULSAQ_S_W_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #917
+ {DBGFIELD("MULTU_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #918
+ {DBGFIELD("MULT_DSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #919
+ {DBGFIELD("PACKRL_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #920
+ {DBGFIELD("PICK_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #921
+ {DBGFIELD("PICK_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #922
+ {DBGFIELD("PRECEQU_PH_QBLA_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #923
+ {DBGFIELD("PRECEQU_PH_QBL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #924
+ {DBGFIELD("PRECEQU_PH_QBRA_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #925
+ {DBGFIELD("PRECEQU_PH_QBR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #926
+ {DBGFIELD("PRECEQ_W_PHL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #927
+ {DBGFIELD("PRECEQ_W_PHR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #928
+ {DBGFIELD("PRECEU_PH_QBLA_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #929
+ {DBGFIELD("PRECEU_PH_QBL_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #930
+ {DBGFIELD("PRECEU_PH_QBRA_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #931
+ {DBGFIELD("PRECEU_PH_QBR_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #932
+ {DBGFIELD("PRECRQU_S_QB_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #933
+ {DBGFIELD("PRECRQ_PH_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #934
+ {DBGFIELD("PRECRQ_QB_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #935
+ {DBGFIELD("PRECRQ_RS_PH_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #936
+ {DBGFIELD("RADDU_W_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #937
+ {DBGFIELD("RDDSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #938
+ {DBGFIELD("REPLV_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #939
+ {DBGFIELD("REPLV_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #940
+ {DBGFIELD("REPL_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #941
+ {DBGFIELD("REPL_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #942
+ {DBGFIELD("SHILOV_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #943
+ {DBGFIELD("SHILO_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #944
+ {DBGFIELD("SHLLV_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #945
+ {DBGFIELD("SHLLV_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #946
+ {DBGFIELD("SHLLV_S_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #947
+ {DBGFIELD("SHLLV_S_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #948
+ {DBGFIELD("SHLL_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #949
+ {DBGFIELD("SHLL_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #950
+ {DBGFIELD("SHLL_S_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #951
+ {DBGFIELD("SHLL_S_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #952
+ {DBGFIELD("SHRAV_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #953
+ {DBGFIELD("SHRAV_R_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #954
+ {DBGFIELD("SHRAV_R_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #955
+ {DBGFIELD("SHRA_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #956
+ {DBGFIELD("SHRA_R_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #957
+ {DBGFIELD("SHRA_R_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #958
+ {DBGFIELD("SHRLV_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #959
+ {DBGFIELD("SHRL_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #960
+ {DBGFIELD("SUBQ_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #961
+ {DBGFIELD("SUBQ_S_PH_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #962
+ {DBGFIELD("SUBQ_S_W_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #963
+ {DBGFIELD("SUBU_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #964
+ {DBGFIELD("SUBU_S_QB_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #965
+ {DBGFIELD("WRDSP_MM") 1, false, false, 35, 1, 2, 1, 0, 0}, // #966
+ {DBGFIELD("ABSQ_S_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #967
+ {DBGFIELD("ADDQH_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #968
+ {DBGFIELD("ADDQH_R_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #969
+ {DBGFIELD("ADDQH_R_W_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #970
+ {DBGFIELD("ADDQH_W_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #971
+ {DBGFIELD("ADDUH_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #972
+ {DBGFIELD("ADDUH_R_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #973
+ {DBGFIELD("ADDU_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #974
+ {DBGFIELD("ADDU_S_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #975
+ {DBGFIELD("APPEND_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #976
+ {DBGFIELD("BALIGN_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #977
+ {DBGFIELD("CMPGDU_EQ_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #978
+ {DBGFIELD("CMPGDU_LE_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #979
+ {DBGFIELD("CMPGDU_LT_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #980
+ {DBGFIELD("DPA_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #981
+ {DBGFIELD("DPAQX_SA_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #982
+ {DBGFIELD("DPAQX_S_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #983
+ {DBGFIELD("DPAX_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #984
+ {DBGFIELD("DPS_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #985
+ {DBGFIELD("DPSQX_S_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #986
+ {DBGFIELD("DPSQX_SA_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #987
+ {DBGFIELD("DPSX_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #988
+ {DBGFIELD("MUL_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #989
+ {DBGFIELD("MUL_S_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #990
+ {DBGFIELD("MULQ_RS_W_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #991
+ {DBGFIELD("MULQ_S_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #992
+ {DBGFIELD("MULQ_S_W_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #993
+ {DBGFIELD("MULSA_W_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #994
+ {DBGFIELD("PRECR_QB_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #995
+ {DBGFIELD("PRECR_SRA_PH_W_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #996
+ {DBGFIELD("PRECR_SRA_R_PH_W_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #997
+ {DBGFIELD("PREPEND_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #998
+ {DBGFIELD("SHRA_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #999
+ {DBGFIELD("SHRA_R_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1000
+ {DBGFIELD("SHRAV_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1001
+ {DBGFIELD("SHRAV_R_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1002
+ {DBGFIELD("SHRL_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1003
+ {DBGFIELD("SHRLV_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1004
+ {DBGFIELD("SUBQH_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1005
+ {DBGFIELD("SUBQH_R_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1006
+ {DBGFIELD("SUBQH_W_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1007
+ {DBGFIELD("SUBQH_R_W_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1008
+ {DBGFIELD("SUBU_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1009
+ {DBGFIELD("SUBU_S_PH_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1010
+ {DBGFIELD("SUBUH_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1011
+ {DBGFIELD("SUBUH_R_QB_MMR2") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1012
+ {DBGFIELD("BPOSGE32C_MMR3") 1, false, false, 35, 1, 2, 1, 0, 0}, // #1013
+ {DBGFIELD("P5600WriteALU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1014
+ {DBGFIELD("P5600WriteAL2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1015
+}; // MipsGenericModelSchedClasses
+
+// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
+static const llvm::MCSchedClassDesc MipsP5600ModelSchedClasses[] = {
+ {DBGFIELD("InvalidSchedClass") 16383, false, false, 0, 0, 0, 0, 0, 0},
+ {DBGFIELD("IIPseudo") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1
+ {DBGFIELD("II_B") 0, false, false, 0, 0, 0, 0, 0, 0}, // #2
+ {DBGFIELD("II_BCCZAL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #3
+ {DBGFIELD("II_MTC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #4
+ {DBGFIELD("II_MFC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #5
+ {DBGFIELD("II_JALR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #6
+ {DBGFIELD("II_CVT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #7
+ {DBGFIELD("II_DMULT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #8
+ {DBGFIELD("II_DMULTU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #9
+ {DBGFIELD("II_DDIV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #10
+ {DBGFIELD("II_DDIVU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #11
+ {DBGFIELD("II_IndirectBranchPseudo") 0, false, false, 0, 0, 0, 0, 0, 0}, // #12
+ {DBGFIELD("II_MADD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #13
+ {DBGFIELD("II_MADDU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #14
+ {DBGFIELD("II_MFHI_MFLO") 0, false, false, 0, 0, 0, 0, 0, 0}, // #15
+ {DBGFIELD("II_MSUB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #16
+ {DBGFIELD("II_MSUBU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #17
+ {DBGFIELD("II_MTHI_MTLO") 0, false, false, 0, 0, 0, 0, 0, 0}, // #18
+ {DBGFIELD("II_MULT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #19
+ {DBGFIELD("II_MULTU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #20
+ {DBGFIELD("II_ReturnPseudo") 0, false, false, 0, 0, 0, 0, 0, 0}, // #21
+ {DBGFIELD("II_DIV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #22
+ {DBGFIELD("II_DIVU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #23
+ {DBGFIELD("II_J") 0, false, false, 0, 0, 0, 0, 0, 0}, // #24
+ {DBGFIELD("II_JR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #25
+ {DBGFIELD("II_TRAP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #26
+ {DBGFIELD("II_ADD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #27
+ {DBGFIELD("II_ADDIUPC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #28
+ {DBGFIELD("II_ADDIU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #29
+ {DBGFIELD("II_ADDU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #30
+ {DBGFIELD("II_ADDI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #31
+ {DBGFIELD("II_ALIGN") 0, false, false, 0, 0, 0, 0, 0, 0}, // #32
+ {DBGFIELD("II_ALUIPC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #33
+ {DBGFIELD("II_AND") 0, false, false, 0, 0, 0, 0, 0, 0}, // #34
+ {DBGFIELD("II_ANDI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #35
+ {DBGFIELD("II_AUI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #36
+ {DBGFIELD("II_AUIPC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #37
+ {DBGFIELD("IIM16Alu") 0, false, false, 0, 0, 0, 0, 0, 0}, // #38
+ {DBGFIELD("II_BADDU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #39
+ {DBGFIELD("II_BC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #40
+ {DBGFIELD("II_BALC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #41
+ {DBGFIELD("II_BBIT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #42
+ {DBGFIELD("II_BC1CCZ") 0, false, false, 0, 0, 0, 0, 0, 0}, // #43
+ {DBGFIELD("II_BC1F") 0, false, false, 0, 0, 0, 0, 0, 0}, // #44
+ {DBGFIELD("II_BC1FL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #45
+ {DBGFIELD("II_BC1T") 0, false, false, 0, 0, 0, 0, 0, 0}, // #46
+ {DBGFIELD("II_BC1TL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #47
+ {DBGFIELD("II_BC2CCZ") 0, false, false, 0, 0, 0, 0, 0, 0}, // #48
+ {DBGFIELD("II_BCC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #49
+ {DBGFIELD("II_BCCC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #50
+ {DBGFIELD("II_BCCZ") 0, false, false, 0, 0, 0, 0, 0, 0}, // #51
+ {DBGFIELD("II_BCCZC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #52
+ {DBGFIELD("II_BCCZALS") 0, false, false, 0, 0, 0, 0, 0, 0}, // #53
+ {DBGFIELD("II_BITSWAP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #54
+ {DBGFIELD("II_BREAK") 0, false, false, 0, 0, 0, 0, 0, 0}, // #55
+ {DBGFIELD("II_CACHE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #56
+ {DBGFIELD("II_CACHEE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #57
+ {DBGFIELD("II_CEIL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #58
+ {DBGFIELD("II_CFC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #59
+ {DBGFIELD("II_CFC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #60
+ {DBGFIELD("II_INS") 0, false, false, 0, 0, 0, 0, 0, 0}, // #61
+ {DBGFIELD("II_CLASS_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #62
+ {DBGFIELD("II_CLASS_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #63
+ {DBGFIELD("II_CLO") 0, false, false, 0, 0, 0, 0, 0, 0}, // #64
+ {DBGFIELD("II_CLZ") 0, false, false, 0, 0, 0, 0, 0, 0}, // #65
+ {DBGFIELD("II_CMP_CC_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #66
+ {DBGFIELD("II_CMP_CC_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #67
+ {DBGFIELD("II_CRC32B") 0, false, false, 0, 0, 0, 0, 0, 0}, // #68
+ {DBGFIELD("II_CRC32CB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #69
+ {DBGFIELD("II_CRC32CD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #70
+ {DBGFIELD("II_CRC32CH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #71
+ {DBGFIELD("II_CRC32CW") 0, false, false, 0, 0, 0, 0, 0, 0}, // #72
+ {DBGFIELD("II_CRC32D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #73
+ {DBGFIELD("II_CRC32H") 0, false, false, 0, 0, 0, 0, 0, 0}, // #74
+ {DBGFIELD("II_CRC32W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #75
+ {DBGFIELD("II_CTC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #76
+ {DBGFIELD("II_CTC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #77
+ {DBGFIELD("II_C_CC_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #78
+ {DBGFIELD("II_C_CC_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #79
+ {DBGFIELD("II_DADD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #80
+ {DBGFIELD("II_DADDI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #81
+ {DBGFIELD("II_DADDIU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #82
+ {DBGFIELD("II_DADDU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #83
+ {DBGFIELD("II_DAHI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #84
+ {DBGFIELD("II_DALIGN") 0, false, false, 0, 0, 0, 0, 0, 0}, // #85
+ {DBGFIELD("II_DATI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #86
+ {DBGFIELD("II_DAUI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #87
+ {DBGFIELD("II_DBITSWAP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #88
+ {DBGFIELD("II_DCLO") 0, false, false, 0, 0, 0, 0, 0, 0}, // #89
+ {DBGFIELD("II_DCLZ") 0, false, false, 0, 0, 0, 0, 0, 0}, // #90
+ {DBGFIELD("II_DERET") 0, false, false, 0, 0, 0, 0, 0, 0}, // #91
+ {DBGFIELD("II_EXT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #92
+ {DBGFIELD("II_DI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #93
+ {DBGFIELD("II_DLSA") 0, false, false, 0, 0, 0, 0, 0, 0}, // #94
+ {DBGFIELD("II_DMFC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #95
+ {DBGFIELD("II_DMFC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #96
+ {DBGFIELD("II_DMFC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #97
+ {DBGFIELD("II_DMFGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #98
+ {DBGFIELD("II_DMOD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #99
+ {DBGFIELD("II_DMODU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #100
+ {DBGFIELD("II_DMT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #101
+ {DBGFIELD("II_DMTC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #102
+ {DBGFIELD("II_DMTC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #103
+ {DBGFIELD("II_DMTC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #104
+ {DBGFIELD("II_DMTGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #105
+ {DBGFIELD("II_DMUH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #106
+ {DBGFIELD("II_DMUHU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #107
+ {DBGFIELD("II_DMUL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #108
+ {DBGFIELD("II_POP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #109
+ {DBGFIELD("II_DROTR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #110
+ {DBGFIELD("II_DROTR32") 0, false, false, 0, 0, 0, 0, 0, 0}, // #111
+ {DBGFIELD("II_DROTRV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #112
+ {DBGFIELD("II_DSBH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #113
+ {DBGFIELD("II_DSHD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #114
+ {DBGFIELD("II_DSLL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #115
+ {DBGFIELD("II_DSLL32") 0, false, false, 0, 0, 0, 0, 0, 0}, // #116
+ {DBGFIELD("II_DSLLV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #117
+ {DBGFIELD("II_DSRA") 0, false, false, 0, 0, 0, 0, 0, 0}, // #118
+ {DBGFIELD("II_DSRA32") 0, false, false, 0, 0, 0, 0, 0, 0}, // #119
+ {DBGFIELD("II_DSRAV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #120
+ {DBGFIELD("II_DSRL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #121
+ {DBGFIELD("II_DSRL32") 0, false, false, 0, 0, 0, 0, 0, 0}, // #122
+ {DBGFIELD("II_DSRLV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #123
+ {DBGFIELD("II_DSUB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #124
+ {DBGFIELD("II_DSUBU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #125
+ {DBGFIELD("II_DVP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #126
+ {DBGFIELD("II_DVPE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #127
+ {DBGFIELD("II_EHB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #128
+ {DBGFIELD("II_EI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #129
+ {DBGFIELD("II_EMT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #130
+ {DBGFIELD("II_ERET") 0, false, false, 0, 0, 0, 0, 0, 0}, // #131
+ {DBGFIELD("II_ERETNC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #132
+ {DBGFIELD("II_EVP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #133
+ {DBGFIELD("II_EVPE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #134
+ {DBGFIELD("II_ABS") 0, false, false, 0, 0, 0, 0, 0, 0}, // #135
+ {DBGFIELD("II_SQRT_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #136
+ {DBGFIELD("II_ADD_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #137
+ {DBGFIELD("II_ADD_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #138
+ {DBGFIELD("II_DIV_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #139
+ {DBGFIELD("II_DIV_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #140
+ {DBGFIELD("II_FLOOR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #141
+ {DBGFIELD("II_MOV_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #142
+ {DBGFIELD("II_MOV_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #143
+ {DBGFIELD("II_MUL_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #144
+ {DBGFIELD("II_MUL_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #145
+ {DBGFIELD("II_NEG") 0, false, false, 0, 0, 0, 0, 0, 0}, // #146
+ {DBGFIELD("II_FORK") 0, false, false, 0, 0, 0, 0, 0, 0}, // #147
+ {DBGFIELD("II_SQRT_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #148
+ {DBGFIELD("II_SUB_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #149
+ {DBGFIELD("II_SUB_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #150
+ {DBGFIELD("II_GINVI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #151
+ {DBGFIELD("II_GINVT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #152
+ {DBGFIELD("II_HYPCALL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #153
+ {DBGFIELD("II_JAL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #154
+ {DBGFIELD("II_JALR_HB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #155
+ {DBGFIELD("II_JALRC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #156
+ {DBGFIELD("II_JALRS") 0, false, false, 0, 0, 0, 0, 0, 0}, // #157
+ {DBGFIELD("II_JALS") 0, false, false, 0, 0, 0, 0, 0, 0}, // #158
+ {DBGFIELD("II_JIALC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #159
+ {DBGFIELD("II_JIC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #160
+ {DBGFIELD("II_JRADDIUSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #161
+ {DBGFIELD("II_JRC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #162
+ {DBGFIELD("II_JR_HB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #163
+ {DBGFIELD("II_LB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #164
+ {DBGFIELD("II_LBE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #165
+ {DBGFIELD("II_LBU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #166
+ {DBGFIELD("II_LBUE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #167
+ {DBGFIELD("II_LD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #168
+ {DBGFIELD("II_LDC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #169
+ {DBGFIELD("II_LDC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #170
+ {DBGFIELD("II_LDC3") 0, false, false, 0, 0, 0, 0, 0, 0}, // #171
+ {DBGFIELD("II_LDL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #172
+ {DBGFIELD("II_LDPC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #173
+ {DBGFIELD("II_LDR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #174
+ {DBGFIELD("II_LDXC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #175
+ {DBGFIELD("II_LH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #176
+ {DBGFIELD("II_LHE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #177
+ {DBGFIELD("II_LHU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #178
+ {DBGFIELD("II_LHUE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #179
+ {DBGFIELD("II_LI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #180
+ {DBGFIELD("II_LL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #181
+ {DBGFIELD("II_LLD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #182
+ {DBGFIELD("II_LLE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #183
+ {DBGFIELD("II_LSA") 0, false, false, 0, 0, 0, 0, 0, 0}, // #184
+ {DBGFIELD("II_LUI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #185
+ {DBGFIELD("II_LUXC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #186
+ {DBGFIELD("II_LW") 0, false, false, 0, 0, 0, 0, 0, 0}, // #187
+ {DBGFIELD("II_LWC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #188
+ {DBGFIELD("II_LWC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #189
+ {DBGFIELD("II_LWC3") 0, false, false, 0, 0, 0, 0, 0, 0}, // #190
+ {DBGFIELD("II_LWE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #191
+ {DBGFIELD("II_LWL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #192
+ {DBGFIELD("II_LWLE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #193
+ {DBGFIELD("II_LWM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #194
+ {DBGFIELD("II_LWPC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #195
+ {DBGFIELD("II_LWP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #196
+ {DBGFIELD("II_LWR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #197
+ {DBGFIELD("II_LWRE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #198
+ {DBGFIELD("II_LWUPC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #199
+ {DBGFIELD("II_LWU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #200
+ {DBGFIELD("II_LWXC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #201
+ {DBGFIELD("II_LWXS") 0, false, false, 0, 0, 0, 0, 0, 0}, // #202
+ {DBGFIELD("II_MADDF_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #203
+ {DBGFIELD("II_MADDF_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #204
+ {DBGFIELD("II_MADD_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #205
+ {DBGFIELD("II_MADD_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #206
+ {DBGFIELD("II_MAX_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #207
+ {DBGFIELD("II_MAXA_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #208
+ {DBGFIELD("II_MAX_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #209
+ {DBGFIELD("II_MAXA_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #210
+ {DBGFIELD("II_MFC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #211
+ {DBGFIELD("II_MFC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #212
+ {DBGFIELD("II_MFGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #213
+ {DBGFIELD("II_MFHC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #214
+ {DBGFIELD("II_MFHC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #215
+ {DBGFIELD("II_MFHGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #216
+ {DBGFIELD("II_MFTR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #217
+ {DBGFIELD("II_MIN_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #218
+ {DBGFIELD("II_MINA_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #219
+ {DBGFIELD("II_MIN_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #220
+ {DBGFIELD("II_MINA_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #221
+ {DBGFIELD("II_MOD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #222
+ {DBGFIELD("II_MODU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #223
+ {DBGFIELD("II_MOVE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #224
+ {DBGFIELD("II_MOVF_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #225
+ {DBGFIELD("II_MOVF") 0, false, false, 0, 0, 0, 0, 0, 0}, // #226
+ {DBGFIELD("II_MOVF_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #227
+ {DBGFIELD("II_MOVN_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #228
+ {DBGFIELD("II_MOVN") 0, false, false, 0, 0, 0, 0, 0, 0}, // #229
+ {DBGFIELD("II_MOVN_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #230
+ {DBGFIELD("II_MOVT_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #231
+ {DBGFIELD("II_MOVT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #232
+ {DBGFIELD("II_MOVT_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #233
+ {DBGFIELD("II_MOVZ_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #234
+ {DBGFIELD("II_MOVZ") 0, false, false, 0, 0, 0, 0, 0, 0}, // #235
+ {DBGFIELD("II_MOVZ_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #236
+ {DBGFIELD("II_MSUBF_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #237
+ {DBGFIELD("II_MSUBF_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #238
+ {DBGFIELD("II_MSUB_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #239
+ {DBGFIELD("II_MSUB_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #240
+ {DBGFIELD("II_MTC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #241
+ {DBGFIELD("II_MTC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #242
+ {DBGFIELD("II_MTGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #243
+ {DBGFIELD("II_MTHC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #244
+ {DBGFIELD("II_MTHC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #245
+ {DBGFIELD("II_MTHGC0") 0, false, false, 0, 0, 0, 0, 0, 0}, // #246
+ {DBGFIELD("II_MTTR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #247
+ {DBGFIELD("II_MUH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #248
+ {DBGFIELD("II_MUHU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #249
+ {DBGFIELD("II_MUL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #250
+ {DBGFIELD("II_MULU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #251
+ {DBGFIELD("II_NMADD_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #252
+ {DBGFIELD("II_NMADD_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #253
+ {DBGFIELD("II_NMSUB_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #254
+ {DBGFIELD("II_NMSUB_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #255
+ {DBGFIELD("II_NOR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #256
+ {DBGFIELD("II_NOT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #257
+ {DBGFIELD("II_OR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #258
+ {DBGFIELD("II_ORI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #259
+ {DBGFIELD("II_PAUSE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #260
+ {DBGFIELD("II_PREF") 0, false, false, 0, 0, 0, 0, 0, 0}, // #261
+ {DBGFIELD("II_PREFE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #262
+ {DBGFIELD("II_RDHWR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #263
+ {DBGFIELD("II_RDPGPR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #264
+ {DBGFIELD("II_RECIP_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #265
+ {DBGFIELD("II_RECIP_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #266
+ {DBGFIELD("II_RINT_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #267
+ {DBGFIELD("II_RINT_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #268
+ {DBGFIELD("II_ROTR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #269
+ {DBGFIELD("II_ROTRV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #270
+ {DBGFIELD("II_ROUND") 0, false, false, 0, 0, 0, 0, 0, 0}, // #271
+ {DBGFIELD("II_RSQRT_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #272
+ {DBGFIELD("II_RSQRT_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #273
+ {DBGFIELD("II_RESTORE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #274
+ {DBGFIELD("II_SB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #275
+ {DBGFIELD("II_SBE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #276
+ {DBGFIELD("II_SC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #277
+ {DBGFIELD("II_SCD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #278
+ {DBGFIELD("II_SCE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #279
+ {DBGFIELD("II_SD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #280
+ {DBGFIELD("II_SDBBP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #281
+ {DBGFIELD("II_SDC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #282
+ {DBGFIELD("II_SDC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #283
+ {DBGFIELD("II_SDC3") 0, false, false, 0, 0, 0, 0, 0, 0}, // #284
+ {DBGFIELD("II_SDL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #285
+ {DBGFIELD("II_SDR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #286
+ {DBGFIELD("II_SDXC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #287
+ {DBGFIELD("II_SEB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #288
+ {DBGFIELD("II_SEH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #289
+ {DBGFIELD("II_SELCCZ") 0, false, false, 0, 0, 0, 0, 0, 0}, // #290
+ {DBGFIELD("II_SELCCZ_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #291
+ {DBGFIELD("II_SELCCZ_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #292
+ {DBGFIELD("II_SEL_D") 0, false, false, 0, 0, 0, 0, 0, 0}, // #293
+ {DBGFIELD("II_SEL_S") 0, false, false, 0, 0, 0, 0, 0, 0}, // #294
+ {DBGFIELD("II_SEQ_SNE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #295
+ {DBGFIELD("II_SEQI_SNEI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #296
+ {DBGFIELD("II_SH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #297
+ {DBGFIELD("II_SHE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #298
+ {DBGFIELD("II_SLL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #299
+ {DBGFIELD("II_SLLV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #300
+ {DBGFIELD("II_SLT_SLTU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #301
+ {DBGFIELD("II_SLTI_SLTIU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #302
+ {DBGFIELD("II_SRA") 0, false, false, 0, 0, 0, 0, 0, 0}, // #303
+ {DBGFIELD("II_SRAV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #304
+ {DBGFIELD("II_SRL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #305
+ {DBGFIELD("II_SRLV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #306
+ {DBGFIELD("II_SSNOP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #307
+ {DBGFIELD("II_SUB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #308
+ {DBGFIELD("II_SUBU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #309
+ {DBGFIELD("II_SUXC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #310
+ {DBGFIELD("II_SW") 0, false, false, 0, 0, 0, 0, 0, 0}, // #311
+ {DBGFIELD("II_SWC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #312
+ {DBGFIELD("II_SWC2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #313
+ {DBGFIELD("II_SWC3") 0, false, false, 0, 0, 0, 0, 0, 0}, // #314
+ {DBGFIELD("II_SWE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #315
+ {DBGFIELD("II_SWL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #316
+ {DBGFIELD("II_SWLE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #317
+ {DBGFIELD("II_SWM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #318
+ {DBGFIELD("II_SWP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #319
+ {DBGFIELD("II_SWR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #320
+ {DBGFIELD("II_SWRE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #321
+ {DBGFIELD("II_SWXC1") 0, false, false, 0, 0, 0, 0, 0, 0}, // #322
+ {DBGFIELD("II_SYNC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #323
+ {DBGFIELD("II_SYNCI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #324
+ {DBGFIELD("II_SYSCALL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #325
+ {DBGFIELD("II_SAVE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #326
+ {DBGFIELD("II_TEQ") 0, false, false, 0, 0, 0, 0, 0, 0}, // #327
+ {DBGFIELD("II_TEQI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #328
+ {DBGFIELD("II_TGE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #329
+ {DBGFIELD("II_TGEI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #330
+ {DBGFIELD("II_TGEIU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #331
+ {DBGFIELD("II_TGEU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #332
+ {DBGFIELD("II_TLBGINV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #333
+ {DBGFIELD("II_TLBGINVF") 0, false, false, 0, 0, 0, 0, 0, 0}, // #334
+ {DBGFIELD("II_TLBGP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #335
+ {DBGFIELD("II_TLBGR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #336
+ {DBGFIELD("II_TLBGWI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #337
+ {DBGFIELD("II_TLBGWR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #338
+ {DBGFIELD("II_TLBINV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #339
+ {DBGFIELD("II_TLBINVF") 0, false, false, 0, 0, 0, 0, 0, 0}, // #340
+ {DBGFIELD("II_TLBP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #341
+ {DBGFIELD("II_TLBR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #342
+ {DBGFIELD("II_TLBWI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #343
+ {DBGFIELD("II_TLBWR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #344
+ {DBGFIELD("II_TLT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #345
+ {DBGFIELD("II_TLTI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #346
+ {DBGFIELD("II_TTLTIU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #347
+ {DBGFIELD("II_TLTU") 0, false, false, 0, 0, 0, 0, 0, 0}, // #348
+ {DBGFIELD("II_TNE") 0, false, false, 0, 0, 0, 0, 0, 0}, // #349
+ {DBGFIELD("II_TNEI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #350
+ {DBGFIELD("II_TRUNC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #351
+ {DBGFIELD("II_WAIT") 0, false, false, 0, 0, 0, 0, 0, 0}, // #352
+ {DBGFIELD("II_WRPGPR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #353
+ {DBGFIELD("II_WSBH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #354
+ {DBGFIELD("II_XOR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #355
+ {DBGFIELD("II_XORI") 0, false, false, 0, 0, 0, 0, 0, 0}, // #356
+ {DBGFIELD("II_YIELD") 0, false, false, 0, 0, 0, 0, 0, 0}, // #357
+ {DBGFIELD("AND") 1, false, false, 36, 2, 1, 1, 0, 0}, // #358
+ {DBGFIELD("LUi") 1, false, false, 36, 2, 1, 1, 0, 0}, // #359
+ {DBGFIELD("NOR") 1, false, false, 36, 2, 1, 1, 0, 0}, // #360
+ {DBGFIELD("OR") 1, false, false, 36, 2, 1, 1, 0, 0}, // #361
+ {DBGFIELD("SLTi_SLTiu") 1, false, false, 36, 2, 1, 1, 0, 0}, // #362
+ {DBGFIELD("SUB") 1, false, false, 36, 2, 1, 1, 0, 0}, // #363
+ {DBGFIELD("SUBu") 1, false, false, 36, 2, 1, 1, 0, 0}, // #364
+ {DBGFIELD("XOR") 1, false, false, 36, 2, 1, 1, 0, 0}, // #365
+ {DBGFIELD("B") 1, false, false, 38, 3, 1, 1, 0, 0}, // #366
+ {DBGFIELD("BAL") 1, false, false, 38, 3, 1, 1, 0, 0}, // #367
+ {DBGFIELD("BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL") 1, false, false, 38, 3, 1, 1, 0, 0}, // #368
+ {DBGFIELD("BEQ_BEQL_BNE_BNEL") 1, false, false, 38, 3, 1, 1, 0, 0}, // #369
+ {DBGFIELD("BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL") 1, false, false, 38, 3, 1, 1, 0, 0}, // #370
+ {DBGFIELD("BREAK") 1, false, false, 38, 3, 1, 1, 0, 0}, // #371
+ {DBGFIELD("DERET") 1, false, false, 38, 3, 1, 1, 0, 0}, // #372
+ {DBGFIELD("ERET") 1, false, false, 38, 3, 1, 1, 0, 0}, // #373
+ {DBGFIELD("ERETNC") 1, false, false, 38, 3, 1, 1, 0, 0}, // #374
+ {DBGFIELD("J_TAILCALL") 1, false, false, 38, 3, 1, 1, 0, 0}, // #375
+ {DBGFIELD("JR_TAILCALLREG_TAILCALLREGHB") 1, false, false, 38, 3, 1, 1, 0, 0}, // #376
+ {DBGFIELD("JR_HB") 1, false, false, 38, 3, 1, 1, 0, 0}, // #377
+ {DBGFIELD("PseudoIndirectBranch_PseudoIndirectHazardBranch") 1, false, false, 38, 3, 1, 1, 0, 0}, // #378
+ {DBGFIELD("PseudoReturn") 1, false, false, 38, 3, 1, 1, 0, 0}, // #379
+ {DBGFIELD("SDBBP") 1, false, false, 38, 3, 1, 1, 0, 0}, // #380
+ {DBGFIELD("SSNOP") 1, false, false, 38, 3, 1, 1, 0, 0}, // #381
+ {DBGFIELD("SYSCALL") 1, false, false, 38, 3, 1, 1, 0, 0}, // #382
+ {DBGFIELD("TEQ") 1, false, false, 38, 3, 1, 1, 0, 0}, // #383
+ {DBGFIELD("TEQI") 1, false, false, 38, 3, 1, 1, 0, 0}, // #384
+ {DBGFIELD("TGE") 1, false, false, 38, 3, 1, 1, 0, 0}, // #385
+ {DBGFIELD("TGEI") 1, false, false, 38, 3, 1, 1, 0, 0}, // #386
+ {DBGFIELD("TGEIU") 1, false, false, 38, 3, 1, 1, 0, 0}, // #387
+ {DBGFIELD("TGEU") 1, false, false, 38, 3, 1, 1, 0, 0}, // #388
+ {DBGFIELD("TLT") 1, false, false, 38, 3, 1, 1, 0, 0}, // #389
+ {DBGFIELD("TLTI") 1, false, false, 38, 3, 1, 1, 0, 0}, // #390
+ {DBGFIELD("TLTU") 1, false, false, 38, 3, 1, 1, 0, 0}, // #391
+ {DBGFIELD("TNE") 1, false, false, 38, 3, 1, 1, 0, 0}, // #392
+ {DBGFIELD("TNEI") 1, false, false, 38, 3, 1, 1, 0, 0}, // #393
+ {DBGFIELD("TRAP") 1, false, false, 38, 3, 1, 1, 0, 0}, // #394
+ {DBGFIELD("TTLTIU") 1, false, false, 38, 3, 1, 1, 0, 0}, // #395
+ {DBGFIELD("WAIT") 1, false, false, 38, 3, 1, 1, 0, 0}, // #396
+ {DBGFIELD("PAUSE") 1, false, false, 38, 3, 1, 1, 0, 0}, // #397
+ {DBGFIELD("JAL") 1, false, false, 38, 3, 2, 1, 0, 0}, // #398
+ {DBGFIELD("JALR_JALRHBPseudo_JALRPseudo") 1, false, false, 38, 3, 2, 1, 0, 0}, // #399
+ {DBGFIELD("JALR_HB") 1, false, false, 38, 3, 2, 1, 0, 0}, // #400
+ {DBGFIELD("JALX") 1, false, false, 38, 3, 2, 1, 0, 0}, // #401
+ {DBGFIELD("TLBINV") 1, false, false, 38, 3, 1, 1, 0, 0}, // #402
+ {DBGFIELD("TLBINVF") 1, false, false, 38, 3, 1, 1, 0, 0}, // #403
+ {DBGFIELD("TLBP") 1, false, false, 38, 3, 1, 1, 0, 0}, // #404
+ {DBGFIELD("TLBR") 1, false, false, 38, 3, 1, 1, 0, 0}, // #405
+ {DBGFIELD("TLBWI") 1, false, false, 38, 3, 1, 1, 0, 0}, // #406
+ {DBGFIELD("TLBWR") 1, false, false, 38, 3, 1, 1, 0, 0}, // #407
+ {DBGFIELD("MFC0") 1, false, false, 38, 3, 1, 1, 0, 0}, // #408
+ {DBGFIELD("MTC0") 1, false, false, 38, 3, 1, 1, 0, 0}, // #409
+ {DBGFIELD("MFC2") 1, false, false, 38, 3, 1, 1, 0, 0}, // #410
+ {DBGFIELD("MTC2") 1, false, false, 38, 3, 1, 1, 0, 0}, // #411
+ {DBGFIELD("LB") 1, false, false, 41, 2, 6, 1, 0, 0}, // #412
+ {DBGFIELD("LBu") 1, false, false, 41, 2, 6, 1, 0, 0}, // #413
+ {DBGFIELD("LH") 1, false, false, 41, 2, 6, 1, 0, 0}, // #414
+ {DBGFIELD("LHu") 1, false, false, 41, 2, 6, 1, 0, 0}, // #415
+ {DBGFIELD("LW") 1, false, false, 41, 2, 6, 1, 0, 0}, // #416
+ {DBGFIELD("LL") 1, false, false, 41, 2, 6, 1, 0, 0}, // #417
+ {DBGFIELD("LWC2") 1, false, false, 41, 2, 6, 1, 0, 0}, // #418
+ {DBGFIELD("LWC3") 1, false, false, 41, 2, 6, 1, 0, 0}, // #419
+ {DBGFIELD("LDC2") 1, false, false, 41, 2, 6, 1, 0, 0}, // #420
+ {DBGFIELD("LDC3") 1, false, false, 41, 2, 6, 1, 0, 0}, // #421
+ {DBGFIELD("LBE") 1, false, false, 41, 2, 6, 1, 0, 0}, // #422
+ {DBGFIELD("LBuE") 1, false, false, 41, 2, 6, 1, 0, 0}, // #423
+ {DBGFIELD("LHE") 1, false, false, 41, 2, 6, 1, 0, 0}, // #424
+ {DBGFIELD("LHuE") 1, false, false, 41, 2, 6, 1, 0, 0}, // #425
+ {DBGFIELD("LWE") 1, false, false, 41, 2, 6, 1, 0, 0}, // #426
+ {DBGFIELD("LLE") 1, false, false, 41, 2, 6, 1, 0, 0}, // #427
+ {DBGFIELD("LWPC") 1, false, false, 41, 2, 6, 1, 0, 0}, // #428
+ {DBGFIELD("LWL") 1, false, false, 43, 3, 6, 1, 0, 0}, // #429
+ {DBGFIELD("LWR") 1, false, false, 43, 3, 6, 1, 0, 0}, // #430
+ {DBGFIELD("LWLE") 1, false, false, 43, 3, 6, 1, 0, 0}, // #431
+ {DBGFIELD("LWRE") 1, false, false, 43, 3, 6, 1, 0, 0}, // #432
+ {DBGFIELD("SB") 1, false, false, 46, 3, 1, 1, 0, 0}, // #433
+ {DBGFIELD("SH") 1, false, false, 46, 3, 1, 1, 0, 0}, // #434
+ {DBGFIELD("SW") 1, false, false, 46, 3, 1, 1, 0, 0}, // #435
+ {DBGFIELD("SWC2") 1, false, false, 46, 3, 1, 1, 0, 0}, // #436
+ {DBGFIELD("SWC3") 1, false, false, 46, 3, 1, 1, 0, 0}, // #437
+ {DBGFIELD("SDC2") 1, false, false, 46, 3, 1, 1, 0, 0}, // #438
+ {DBGFIELD("SDC3") 1, false, false, 46, 3, 1, 1, 0, 0}, // #439
+ {DBGFIELD("SC") 1, false, false, 46, 3, 1, 1, 0, 0}, // #440
+ {DBGFIELD("SBE") 1, false, false, 46, 3, 1, 1, 0, 0}, // #441
+ {DBGFIELD("SHE") 1, false, false, 46, 3, 1, 1, 0, 0}, // #442
+ {DBGFIELD("SWE") 1, false, false, 46, 3, 1, 1, 0, 0}, // #443
+ {DBGFIELD("SCE") 1, false, false, 46, 3, 1, 1, 0, 0}, // #444
+ {DBGFIELD("SWL") 1, false, false, 46, 3, 1, 1, 0, 0}, // #445
+ {DBGFIELD("SWR") 1, false, false, 46, 3, 1, 1, 0, 0}, // #446
+ {DBGFIELD("SWLE") 1, false, false, 46, 3, 1, 1, 0, 0}, // #447
+ {DBGFIELD("SWRE") 1, false, false, 46, 3, 1, 1, 0, 0}, // #448
+ {DBGFIELD("PREF") 1, false, false, 41, 2, 1, 1, 0, 0}, // #449
+ {DBGFIELD("PREFE") 1, false, false, 41, 2, 1, 1, 0, 0}, // #450
+ {DBGFIELD("CACHE") 1, false, false, 41, 2, 1, 1, 0, 0}, // #451
+ {DBGFIELD("CACHEE") 1, false, false, 41, 2, 1, 1, 0, 0}, // #452
+ {DBGFIELD("SYNC") 1, false, false, 41, 2, 1, 1, 0, 0}, // #453
+ {DBGFIELD("SYNCI") 1, false, false, 41, 2, 1, 1, 0, 0}, // #454
+ {DBGFIELD("CLO") 1, false, false, 1, 2, 1, 1, 0, 0}, // #455
+ {DBGFIELD("CLZ") 1, false, false, 1, 2, 1, 1, 0, 0}, // #456
+ {DBGFIELD("DI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #457
+ {DBGFIELD("EI") 1, false, false, 1, 2, 1, 1, 0, 0}, // #458
+ {DBGFIELD("MFHI_MFLO_PseudoMFHI_PseudoMFLO") 1, false, false, 1, 2, 1, 1, 0, 0}, // #459
+ {DBGFIELD("EHB") 1, false, false, 1, 2, 2, 1, 0, 0}, // #460
+ {DBGFIELD("RDHWR") 1, false, false, 1, 2, 2, 1, 0, 0}, // #461
+ {DBGFIELD("WSBH") 1, false, false, 1, 2, 2, 1, 0, 0}, // #462
+ {DBGFIELD("MOVN_I_I") 1, false, false, 49, 3, 2, 1, 0, 0}, // #463
+ {DBGFIELD("MOVZ_I_I") 1, false, false, 49, 3, 2, 1, 0, 0}, // #464
+ {DBGFIELD("DIV_PseudoSDIV_SDIV") 1, false, false, 52, 3, 14, 1, 0, 0}, // #465
+ {DBGFIELD("DIVU_PseudoUDIV_UDIV") 1, false, false, 52, 3, 14, 1, 0, 0}, // #466
+ {DBGFIELD("MUL") 1, false, false, 1, 2, 7, 1, 0, 0}, // #467
+ {DBGFIELD("MULT_PseudoMULT") 1, false, false, 1, 2, 3, 1, 0, 0}, // #468
+ {DBGFIELD("MULTu_PseudoMULTu") 1, false, false, 1, 2, 3, 1, 0, 0}, // #469
+ {DBGFIELD("MADD_PseudoMADD") 1, false, false, 49, 3, 3, 1, 0, 0}, // #470
+ {DBGFIELD("MADDU_PseudoMADDU") 1, false, false, 49, 3, 3, 1, 0, 0}, // #471
+ {DBGFIELD("MSUB_PseudoMSUB") 1, false, false, 49, 3, 3, 1, 0, 0}, // #472
+ {DBGFIELD("MSUBU_PseudoMSUBU") 1, false, false, 49, 3, 3, 1, 0, 0}, // #473
+ {DBGFIELD("MTHI_MTLO_PseudoMTLOHI") 1, false, false, 49, 3, 3, 1, 0, 0}, // #474
+ {DBGFIELD("EXT") 1, false, false, 1, 2, 2, 1, 0, 0}, // #475
+ {DBGFIELD("INS") 1, false, false, 1, 2, 2, 1, 0, 0}, // #476
+ {DBGFIELD("ADD") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #477
+ {DBGFIELD("ADDi") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #478
+ {DBGFIELD("ADDiu") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #479
+ {DBGFIELD("ANDi") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #480
+ {DBGFIELD("ORi") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #481
+ {DBGFIELD("ROTR") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #482
+ {DBGFIELD("SEB") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #483
+ {DBGFIELD("SEH") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #484
+ {DBGFIELD("SLT_SLTu") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #485
+ {DBGFIELD("SLL") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #486
+ {DBGFIELD("SRA") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #487
+ {DBGFIELD("SRL") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #488
+ {DBGFIELD("XORi") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #489
+ {DBGFIELD("ADDu") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #490
+ {DBGFIELD("SLLV") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #491
+ {DBGFIELD("SRAV") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #492
+ {DBGFIELD("SRLV") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #493
+ {DBGFIELD("LSA") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #494
+ {DBGFIELD("COPY") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #495
+ {DBGFIELD("VSHF_B_VSHF_D_VSHF_H_VSHF_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #496
+ {DBGFIELD("BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #497
+ {DBGFIELD("BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #498
+ {DBGFIELD("INSERT_B_INSERT_D_INSERT_H_INSERT_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #499
+ {DBGFIELD("SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #500
+ {DBGFIELD("BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #501
+ {DBGFIELD("BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #502
+ {DBGFIELD("BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #503
+ {DBGFIELD("BSELI_B_BSEL_V") 1, false, false, 26, 2, 2, 1, 0, 0}, // #504
+ {DBGFIELD("BMNZI_B_BMNZ_V_BMZI_B_BMZ_V") 1, false, false, 26, 2, 2, 1, 0, 0}, // #505
+ {DBGFIELD("PCNT_B_PCNT_D_PCNT_H_PCNT_W") 1, false, false, 26, 2, 7, 1, 0, 0}, // #506
+ {DBGFIELD("SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W") 1, false, false, 26, 2, 7, 1, 0, 0}, // #507
+ {DBGFIELD("BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #508
+ {DBGFIELD("CFCMSA_CTCMSA") 1, false, false, 26, 2, 1, 1, 0, 0}, // #509
+ {DBGFIELD("FABS_S_FABS_D32_FABS_D64") 1, false, false, 26, 2, 1, 1, 0, 0}, // #510
+ {DBGFIELD("MOVF_D32_MOVF_D64") 1, false, false, 26, 2, 1, 1, 0, 0}, // #511
+ {DBGFIELD("MOVF_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #512
+ {DBGFIELD("MOVT_D32_MOVT_D64") 1, false, false, 26, 2, 1, 1, 0, 0}, // #513
+ {DBGFIELD("MOVT_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #514
+ {DBGFIELD("FMOV_D32_FMOV_D64") 1, false, false, 26, 2, 1, 1, 0, 0}, // #515
+ {DBGFIELD("FMOV_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #516
+ {DBGFIELD("FNEG_S_FNEG_D32_FNEG_D64") 1, false, false, 26, 2, 1, 1, 0, 0}, // #517
+ {DBGFIELD("ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #518
+ {DBGFIELD("ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #519
+ {DBGFIELD("ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #520
+ {DBGFIELD("ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #521
+ {DBGFIELD("AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #522
+ {DBGFIELD("SHF_B_SHF_H_SHF_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #523
+ {DBGFIELD("FILL_B_FILL_D_FILL_H_FILL_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #524
+ {DBGFIELD("SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #525
+ {DBGFIELD("MOVE_V") 1, false, false, 26, 2, 1, 1, 0, 0}, // #526
+ {DBGFIELD("LDI_B_LDI_D_LDI_H_LDI_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #527
+ {DBGFIELD("AND_V_NOR_V_OR_V_XOR_V") 1, false, false, 26, 2, 1, 1, 0, 0}, // #528
+ {DBGFIELD("ANDI_B_NORI_B_ORI_B_XORI_B") 1, false, false, 26, 2, 1, 1, 0, 0}, // #529
+ {DBGFIELD("FEXP2_D_FEXP2_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #530
+ {DBGFIELD("CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #531
+ {DBGFIELD("CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #532
+ {DBGFIELD("CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #533
+ {DBGFIELD("CMP_UN_D") 1, false, false, 26, 2, 1, 1, 0, 0}, // #534
+ {DBGFIELD("CMP_UN_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #535
+ {DBGFIELD("CMP_UEQ_D") 1, false, false, 26, 2, 1, 1, 0, 0}, // #536
+ {DBGFIELD("CMP_UEQ_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #537
+ {DBGFIELD("CMP_EQ_D") 1, false, false, 26, 2, 1, 1, 0, 0}, // #538
+ {DBGFIELD("CMP_EQ_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #539
+ {DBGFIELD("CMP_LT_D") 1, false, false, 26, 2, 1, 1, 0, 0}, // #540
+ {DBGFIELD("CMP_LT_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #541
+ {DBGFIELD("CMP_ULT_D") 1, false, false, 26, 2, 1, 1, 0, 0}, // #542
+ {DBGFIELD("CMP_ULT_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #543
+ {DBGFIELD("CMP_LE_D") 1, false, false, 26, 2, 1, 1, 0, 0}, // #544
+ {DBGFIELD("CMP_LE_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #545
+ {DBGFIELD("CMP_ULE_D") 1, false, false, 26, 2, 1, 1, 0, 0}, // #546
+ {DBGFIELD("CMP_ULE_S") 1, false, false, 26, 2, 1, 1, 0, 0}, // #547
+ {DBGFIELD("FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #548
+ {DBGFIELD("FSUEQ_D_FSUEQ_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #549
+ {DBGFIELD("FSULE_D_FSULE_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #550
+ {DBGFIELD("FSULT_D_FSULT_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #551
+ {DBGFIELD("FSUNE_D_FSUNE_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #552
+ {DBGFIELD("FSUN_D_FSUN_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #553
+ {DBGFIELD("FCAF_D_FCAF_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #554
+ {DBGFIELD("FCEQ_D_FCEQ_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #555
+ {DBGFIELD("FCLE_D_FCLE_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #556
+ {DBGFIELD("FCLT_D_FCLT_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #557
+ {DBGFIELD("FCNE_D_FCNE_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #558
+ {DBGFIELD("FCOR_D_FCOR_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #559
+ {DBGFIELD("FCUEQ_D_FCUEQ_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #560
+ {DBGFIELD("FCULE_D_FCULE_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #561
+ {DBGFIELD("FCULT_D_FCULT_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #562
+ {DBGFIELD("FCUNE_D_FCUNE_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #563
+ {DBGFIELD("FCUN_D_FCUN_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #564
+ {DBGFIELD("FABS_D_FABS_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #565
+ {DBGFIELD("FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #566
+ {DBGFIELD("FFQL_D_FFQL_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #567
+ {DBGFIELD("FFQR_D_FFQR_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #568
+ {DBGFIELD("FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #569
+ {DBGFIELD("FRINT_D_FRINT_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #570
+ {DBGFIELD("FTQ_H_FTQ_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #571
+ {DBGFIELD("FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #572
+ {DBGFIELD("FEXDO_H_FEXDO_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #573
+ {DBGFIELD("FEXUPL_D_FEXUPL_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #574
+ {DBGFIELD("FEXUPR_D_FEXUPR_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #575
+ {DBGFIELD("FCLASS_D_FCLASS_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #576
+ {DBGFIELD("FMAX_A_D_FMAX_A_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #577
+ {DBGFIELD("FMAX_D_FMAX_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #578
+ {DBGFIELD("FMIN_A_D_FMIN_A_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #579
+ {DBGFIELD("FMIN_D_FMIN_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #580
+ {DBGFIELD("FLOG2_D_FLOG2_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #581
+ {DBGFIELD("ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #582
+ {DBGFIELD("ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #583
+ {DBGFIELD("INSVE_B_INSVE_D_INSVE_H_INSVE_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #584
+ {DBGFIELD("SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #585
+ {DBGFIELD("SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #586
+ {DBGFIELD("SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #587
+ {DBGFIELD("SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #588
+ {DBGFIELD("SUBV_B_SUBV_D_SUBV_H_SUBV_W") 1, false, false, 26, 2, 2, 1, 0, 0}, // #589
+ {DBGFIELD("MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W") 1, false, false, 55, 3, 15, 1, 0, 0}, // #590
+ {DBGFIELD("DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W") 1, false, false, 55, 3, 15, 1, 0, 0}, // #591
+ {DBGFIELD("HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #592
+ {DBGFIELD("HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #593
+ {DBGFIELD("MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #594
+ {DBGFIELD("MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #595
+ {DBGFIELD("MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #596
+ {DBGFIELD("MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #597
+ {DBGFIELD("SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #598
+ {DBGFIELD("SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #599
+ {DBGFIELD("SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #600
+ {DBGFIELD("SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #601
+ {DBGFIELD("SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #602
+ {DBGFIELD("PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #603
+ {DBGFIELD("NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W") 1, false, false, 26, 2, 1, 1, 0, 0}, // #604
+ {DBGFIELD("FADD_D32_FADD_D64") 1, false, false, 58, 2, 6, 1, 0, 0}, // #605
+ {DBGFIELD("FADD_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #606
+ {DBGFIELD("FMUL_D32_FMUL_D64") 1, false, false, 58, 2, 6, 1, 0, 0}, // #607
+ {DBGFIELD("FMUL_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #608
+ {DBGFIELD("FSUB_D32_FSUB_D64") 1, false, false, 58, 2, 6, 1, 0, 0}, // #609
+ {DBGFIELD("FSUB_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #610
+ {DBGFIELD("TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #611
+ {DBGFIELD("CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #612
+ {DBGFIELD("C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64") 1, false, false, 58, 2, 6, 1, 0, 0}, // #613
+ {DBGFIELD("C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #614
+ {DBGFIELD("FCMP_D32_FCMP_D64") 1, false, false, 58, 2, 6, 1, 0, 0}, // #615
+ {DBGFIELD("FCMP_S32") 1, false, false, 58, 2, 6, 1, 0, 0}, // #616
+ {DBGFIELD("PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W") 1, false, false, 58, 2, 6, 1, 0, 0}, // #617
+ {DBGFIELD("FDIV_S") 1, false, false, 55, 3, 15, 1, 0, 0}, // #618
+ {DBGFIELD("FDIV_D32_FDIV_D64") 1, false, false, 60, 3, 5, 1, 0, 0}, // #619
+ {DBGFIELD("FSQRT_S") 1, false, false, 63, 3, 16, 1, 0, 0}, // #620
+ {DBGFIELD("FSQRT_D32_FSQRT_D64") 1, false, false, 66, 3, 17, 1, 0, 0}, // #621
+ {DBGFIELD("FRCP_D_FRCP_W") 1, false, false, 63, 3, 16, 1, 0, 0}, // #622
+ {DBGFIELD("FRSQRT_D_FRSQRT_W") 1, false, false, 63, 3, 16, 1, 0, 0}, // #623
+ {DBGFIELD("RECIP_D32_RECIP_D64") 1, false, false, 63, 3, 16, 1, 0, 0}, // #624
+ {DBGFIELD("RSQRT_D32_RSQRT_D64") 1, false, false, 63, 3, 16, 1, 0, 0}, // #625
+ {DBGFIELD("RECIP_S") 1, false, false, 63, 3, 16, 1, 0, 0}, // #626
+ {DBGFIELD("RSQRT_S") 1, false, false, 63, 3, 16, 1, 0, 0}, // #627
+ {DBGFIELD("FMADD_D_FMADD_W") 1, false, false, 58, 2, 13, 1, 0, 0}, // #628
+ {DBGFIELD("FMSUB_D_FMSUB_W") 1, false, false, 58, 2, 13, 1, 0, 0}, // #629
+ {DBGFIELD("FDIV_W") 1, false, false, 55, 3, 15, 1, 0, 0}, // #630
+ {DBGFIELD("FDIV_D") 1, false, false, 60, 3, 5, 1, 0, 0}, // #631
+ {DBGFIELD("FSQRT_W") 1, false, false, 63, 3, 16, 1, 0, 0}, // #632
+ {DBGFIELD("FSQRT_D") 1, false, false, 66, 3, 17, 1, 0, 0}, // #633
+ {DBGFIELD("FMUL_D_FMUL_W") 1, false, false, 58, 2, 6, 1, 0, 0}, // #634
+ {DBGFIELD("FADD_D_FADD_W") 1, false, false, 58, 2, 6, 1, 0, 0}, // #635
+ {DBGFIELD("FSUB_D_FSUB_W") 1, false, false, 58, 2, 6, 1, 0, 0}, // #636
+ {DBGFIELD("DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #637
+ {DBGFIELD("DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #638
+ {DBGFIELD("DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #639
+ {DBGFIELD("MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #640
+ {DBGFIELD("MADDV_B_MADDV_D_MADDV_H_MADDV_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #641
+ {DBGFIELD("MULV_B_MULV_D_MULV_H_MULV_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #642
+ {DBGFIELD("MADDR_Q_H_MADDR_Q_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #643
+ {DBGFIELD("MADD_Q_H_MADD_Q_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #644
+ {DBGFIELD("MSUBR_Q_H_MSUBR_Q_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #645
+ {DBGFIELD("MSUB_Q_H_MSUB_Q_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #646
+ {DBGFIELD("MULR_Q_H_MULR_Q_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #647
+ {DBGFIELD("MUL_Q_H_MUL_Q_W") 1, false, false, 26, 2, 3, 1, 0, 0}, // #648
+ {DBGFIELD("MADD_D32_MADD_D64") 1, false, false, 58, 2, 13, 1, 1, 1}, // #649
+ {DBGFIELD("MADD_S") 1, false, false, 58, 2, 13, 1, 1, 1}, // #650
+ {DBGFIELD("MSUB_D32_MSUB_D64") 1, false, false, 58, 2, 13, 1, 1, 1}, // #651
+ {DBGFIELD("MSUB_S") 1, false, false, 58, 2, 13, 1, 1, 1}, // #652
+ {DBGFIELD("NMADD_D32_NMADD_D64") 1, false, false, 58, 2, 13, 1, 1, 1}, // #653
+ {DBGFIELD("NMADD_S") 1, false, false, 58, 2, 13, 1, 1, 1}, // #654
+ {DBGFIELD("NMSUB_D32_NMSUB_D64") 1, false, false, 58, 2, 13, 1, 1, 1}, // #655
+ {DBGFIELD("NMSUB_S") 1, false, false, 58, 2, 13, 1, 1, 1}, // #656
+ {DBGFIELD("CTC1") 2, false, false, 69, 4, 1, 1, 0, 0}, // #657
+ {DBGFIELD("MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64") 2, false, false, 69, 4, 1, 1, 0, 0}, // #658
+ {DBGFIELD("MTHC1_D32_MTHC1_D64") 2, false, false, 69, 4, 1, 1, 0, 0}, // #659
+ {DBGFIELD("COPY_U_B_COPY_U_H_COPY_U_W") 2, false, false, 69, 4, 2, 1, 0, 0}, // #660
+ {DBGFIELD("COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W") 2, false, false, 69, 4, 2, 1, 0, 0}, // #661
+ {DBGFIELD("BC1F") 2, false, false, 69, 4, 2, 1, 0, 0}, // #662
+ {DBGFIELD("BC1FL") 2, false, false, 69, 4, 2, 1, 0, 0}, // #663
+ {DBGFIELD("BC1T") 2, false, false, 69, 4, 2, 1, 0, 0}, // #664
+ {DBGFIELD("BC1TL") 2, false, false, 69, 4, 2, 1, 0, 0}, // #665
+ {DBGFIELD("CFC1") 2, false, false, 69, 4, 2, 1, 0, 0}, // #666
+ {DBGFIELD("MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64") 2, false, false, 69, 4, 2, 1, 0, 0}, // #667
+ {DBGFIELD("MFHC1_D32_MFHC1_D64") 2, false, false, 69, 4, 2, 1, 0, 0}, // #668
+ {DBGFIELD("MOVF_I") 2, false, false, 69, 4, 2, 1, 0, 0}, // #669
+ {DBGFIELD("MOVT_I") 2, false, false, 69, 4, 2, 1, 0, 0}, // #670
+ {DBGFIELD("SDC1") 2, false, false, 69, 4, 1, 1, 0, 0}, // #671
+ {DBGFIELD("SDXC1") 2, false, false, 69, 4, 1, 1, 0, 0}, // #672
+ {DBGFIELD("SUXC1") 2, false, false, 69, 4, 1, 1, 0, 0}, // #673
+ {DBGFIELD("SWC1") 2, false, false, 69, 4, 1, 1, 0, 0}, // #674
+ {DBGFIELD("SWXC1") 2, false, false, 69, 4, 1, 1, 0, 0}, // #675
+ {DBGFIELD("ST_B_ST_D_ST_H_ST_W") 2, false, false, 69, 4, 1, 1, 0, 0}, // #676
+ {DBGFIELD("MOVN_I_D32_MOVN_I_D64") 2, false, false, 73, 4, 2, 1, 0, 0}, // #677
+ {DBGFIELD("MOVN_I_S") 2, false, false, 73, 4, 2, 1, 0, 0}, // #678
+ {DBGFIELD("MOVZ_I_D32_MOVZ_I_D64") 2, false, false, 73, 4, 2, 1, 0, 0}, // #679
+ {DBGFIELD("MOVZ_I_S") 2, false, false, 73, 4, 2, 1, 0, 0}, // #680
+ {DBGFIELD("LDC1") 2, false, false, 77, 4, 6, 1, 0, 0}, // #681
+ {DBGFIELD("LDXC1") 2, false, false, 77, 4, 6, 1, 0, 0}, // #682
+ {DBGFIELD("LWC1") 2, false, false, 77, 4, 6, 1, 0, 0}, // #683
+ {DBGFIELD("LWXC1") 2, false, false, 77, 4, 6, 1, 0, 0}, // #684
+ {DBGFIELD("LUXC1") 2, false, false, 77, 4, 6, 1, 0, 0}, // #685
+ {DBGFIELD("LD_B_LD_D_LD_H_LD_W") 2, false, false, 77, 4, 6, 1, 0, 0}, // #686
+ {DBGFIELD("CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #687
+ {DBGFIELD("FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #688
+ {DBGFIELD("ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S") 1, false, false, 58, 2, 6, 1, 0, 0}, // #689
+ {DBGFIELD("ROTRV") 16382, false, false, 0, 0, 0, 0, 0, 0}, // #690
+ {DBGFIELD("EXTRV_RS_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #691
+ {DBGFIELD("EXTRV_R_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #692
+ {DBGFIELD("EXTRV_S_H") 0, false, false, 0, 0, 0, 0, 0, 0}, // #693
+ {DBGFIELD("EXTRV_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #694
+ {DBGFIELD("EXTR_RS_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #695
+ {DBGFIELD("EXTR_R_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #696
+ {DBGFIELD("EXTR_S_H") 0, false, false, 0, 0, 0, 0, 0, 0}, // #697
+ {DBGFIELD("EXTR_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #698
+ {DBGFIELD("INSV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #699
+ {DBGFIELD("MTHLIP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #700
+ {DBGFIELD("MTHI_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #701
+ {DBGFIELD("MTLO_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #702
+ {DBGFIELD("ABSQ_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #703
+ {DBGFIELD("ABSQ_S_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #704
+ {DBGFIELD("ADDQ_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #705
+ {DBGFIELD("ADDQ_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #706
+ {DBGFIELD("ADDQ_S_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #707
+ {DBGFIELD("ADDSC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #708
+ {DBGFIELD("ADDU_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #709
+ {DBGFIELD("ADDU_S_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #710
+ {DBGFIELD("ADDWC") 0, false, false, 0, 0, 0, 0, 0, 0}, // #711
+ {DBGFIELD("BITREV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #712
+ {DBGFIELD("BPOSGE32") 0, false, false, 0, 0, 0, 0, 0, 0}, // #713
+ {DBGFIELD("CMPGU_EQ_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #714
+ {DBGFIELD("CMPGU_LE_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #715
+ {DBGFIELD("CMPGU_LT_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #716
+ {DBGFIELD("CMPU_EQ_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #717
+ {DBGFIELD("CMPU_LE_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #718
+ {DBGFIELD("CMPU_LT_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #719
+ {DBGFIELD("CMP_EQ_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #720
+ {DBGFIELD("CMP_LE_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #721
+ {DBGFIELD("CMP_LT_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #722
+ {DBGFIELD("DPAQ_SA_L_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #723
+ {DBGFIELD("DPAQ_S_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #724
+ {DBGFIELD("DPAU_H_QBL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #725
+ {DBGFIELD("DPAU_H_QBR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #726
+ {DBGFIELD("DPSQ_SA_L_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #727
+ {DBGFIELD("DPSQ_S_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #728
+ {DBGFIELD("DPSU_H_QBL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #729
+ {DBGFIELD("DPSU_H_QBR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #730
+ {DBGFIELD("EXTPDPV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #731
+ {DBGFIELD("EXTPDP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #732
+ {DBGFIELD("EXTPV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #733
+ {DBGFIELD("EXTP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #734
+ {DBGFIELD("LBUX") 0, false, false, 0, 0, 0, 0, 0, 0}, // #735
+ {DBGFIELD("LHX") 0, false, false, 0, 0, 0, 0, 0, 0}, // #736
+ {DBGFIELD("LWX") 0, false, false, 0, 0, 0, 0, 0, 0}, // #737
+ {DBGFIELD("MADDU_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #738
+ {DBGFIELD("MADD_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #739
+ {DBGFIELD("MAQ_SA_W_PHL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #740
+ {DBGFIELD("MAQ_SA_W_PHR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #741
+ {DBGFIELD("MAQ_S_W_PHL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #742
+ {DBGFIELD("MAQ_S_W_PHR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #743
+ {DBGFIELD("MFHI_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #744
+ {DBGFIELD("MFLO_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #745
+ {DBGFIELD("MODSUB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #746
+ {DBGFIELD("MSUBU_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #747
+ {DBGFIELD("MSUB_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #748
+ {DBGFIELD("MULEQ_S_W_PHL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #749
+ {DBGFIELD("MULEQ_S_W_PHR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #750
+ {DBGFIELD("MULEU_S_PH_QBL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #751
+ {DBGFIELD("MULEU_S_PH_QBR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #752
+ {DBGFIELD("MULQ_RS_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #753
+ {DBGFIELD("MULSAQ_S_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #754
+ {DBGFIELD("MULTU_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #755
+ {DBGFIELD("MULT_DSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #756
+ {DBGFIELD("PACKRL_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #757
+ {DBGFIELD("PICK_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #758
+ {DBGFIELD("PICK_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #759
+ {DBGFIELD("PRECEQU_PH_QBLA") 0, false, false, 0, 0, 0, 0, 0, 0}, // #760
+ {DBGFIELD("PRECEQU_PH_QBL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #761
+ {DBGFIELD("PRECEQU_PH_QBRA") 0, false, false, 0, 0, 0, 0, 0, 0}, // #762
+ {DBGFIELD("PRECEQU_PH_QBR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #763
+ {DBGFIELD("PRECEQ_W_PHL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #764
+ {DBGFIELD("PRECEQ_W_PHR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #765
+ {DBGFIELD("PRECEU_PH_QBLA") 0, false, false, 0, 0, 0, 0, 0, 0}, // #766
+ {DBGFIELD("PRECEU_PH_QBL") 0, false, false, 0, 0, 0, 0, 0, 0}, // #767
+ {DBGFIELD("PRECEU_PH_QBRA") 0, false, false, 0, 0, 0, 0, 0, 0}, // #768
+ {DBGFIELD("PRECEU_PH_QBR") 0, false, false, 0, 0, 0, 0, 0, 0}, // #769
+ {DBGFIELD("PRECRQU_S_QB_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #770
+ {DBGFIELD("PRECRQ_PH_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #771
+ {DBGFIELD("PRECRQ_QB_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #772
+ {DBGFIELD("PRECRQ_RS_PH_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #773
+ {DBGFIELD("RADDU_W_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #774
+ {DBGFIELD("RDDSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #775
+ {DBGFIELD("REPLV_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #776
+ {DBGFIELD("REPLV_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #777
+ {DBGFIELD("REPL_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #778
+ {DBGFIELD("REPL_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #779
+ {DBGFIELD("SHILOV") 0, false, false, 0, 0, 0, 0, 0, 0}, // #780
+ {DBGFIELD("SHILO") 0, false, false, 0, 0, 0, 0, 0, 0}, // #781
+ {DBGFIELD("SHLLV_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #782
+ {DBGFIELD("SHLLV_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #783
+ {DBGFIELD("SHLLV_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #784
+ {DBGFIELD("SHLLV_S_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #785
+ {DBGFIELD("SHLL_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #786
+ {DBGFIELD("SHLL_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #787
+ {DBGFIELD("SHLL_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #788
+ {DBGFIELD("SHLL_S_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #789
+ {DBGFIELD("SHRAV_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #790
+ {DBGFIELD("SHRAV_R_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #791
+ {DBGFIELD("SHRAV_R_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #792
+ {DBGFIELD("SHRA_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #793
+ {DBGFIELD("SHRA_R_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #794
+ {DBGFIELD("SHRA_R_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #795
+ {DBGFIELD("SHRLV_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #796
+ {DBGFIELD("SHRL_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #797
+ {DBGFIELD("SUBQ_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #798
+ {DBGFIELD("SUBQ_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #799
+ {DBGFIELD("SUBQ_S_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #800
+ {DBGFIELD("SUBU_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #801
+ {DBGFIELD("SUBU_S_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #802
+ {DBGFIELD("WRDSP") 0, false, false, 0, 0, 0, 0, 0, 0}, // #803
+ {DBGFIELD("ABSQ_S_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #804
+ {DBGFIELD("ADDQH_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #805
+ {DBGFIELD("ADDQH_R_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #806
+ {DBGFIELD("ADDQH_R_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #807
+ {DBGFIELD("ADDQH_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #808
+ {DBGFIELD("ADDUH_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #809
+ {DBGFIELD("ADDUH_R_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #810
+ {DBGFIELD("ADDU_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #811
+ {DBGFIELD("ADDU_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #812
+ {DBGFIELD("APPEND") 0, false, false, 0, 0, 0, 0, 0, 0}, // #813
+ {DBGFIELD("BALIGN") 0, false, false, 0, 0, 0, 0, 0, 0}, // #814
+ {DBGFIELD("CMPGDU_EQ_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #815
+ {DBGFIELD("CMPGDU_LE_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #816
+ {DBGFIELD("CMPGDU_LT_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #817
+ {DBGFIELD("DPA_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #818
+ {DBGFIELD("DPAQX_SA_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #819
+ {DBGFIELD("DPAQX_S_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #820
+ {DBGFIELD("DPAX_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #821
+ {DBGFIELD("DPS_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #822
+ {DBGFIELD("DPSQX_S_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #823
+ {DBGFIELD("DPSQX_SA_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #824
+ {DBGFIELD("DPSX_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #825
+ {DBGFIELD("MUL_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #826
+ {DBGFIELD("MUL_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #827
+ {DBGFIELD("MULQ_RS_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #828
+ {DBGFIELD("MULQ_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #829
+ {DBGFIELD("MULQ_S_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #830
+ {DBGFIELD("MULSA_W_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #831
+ {DBGFIELD("PRECR_QB_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #832
+ {DBGFIELD("PRECR_SRA_PH_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #833
+ {DBGFIELD("PRECR_SRA_R_PH_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #834
+ {DBGFIELD("PREPEND") 0, false, false, 0, 0, 0, 0, 0, 0}, // #835
+ {DBGFIELD("SHRA_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #836
+ {DBGFIELD("SHRA_R_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #837
+ {DBGFIELD("SHRAV_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #838
+ {DBGFIELD("SHRAV_R_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #839
+ {DBGFIELD("SHRL_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #840
+ {DBGFIELD("SHRLV_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #841
+ {DBGFIELD("SUBQH_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #842
+ {DBGFIELD("SUBQH_R_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #843
+ {DBGFIELD("SUBQH_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #844
+ {DBGFIELD("SUBQH_R_W") 0, false, false, 0, 0, 0, 0, 0, 0}, // #845
+ {DBGFIELD("SUBU_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #846
+ {DBGFIELD("SUBU_S_PH") 0, false, false, 0, 0, 0, 0, 0, 0}, // #847
+ {DBGFIELD("SUBUH_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #848
+ {DBGFIELD("SUBUH_R_QB") 0, false, false, 0, 0, 0, 0, 0, 0}, // #849
+ {DBGFIELD("ABSQ_S_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #850
+ {DBGFIELD("ABSQ_S_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #851
+ {DBGFIELD("ADDQ_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #852
+ {DBGFIELD("ADDQ_S_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #853
+ {DBGFIELD("ADDQ_S_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #854
+ {DBGFIELD("ADDSC_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #855
+ {DBGFIELD("ADDU_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #856
+ {DBGFIELD("ADDU_S_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #857
+ {DBGFIELD("ADDWC_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #858
+ {DBGFIELD("BITREV_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #859
+ {DBGFIELD("BPOSGE32_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #860
+ {DBGFIELD("CMPGU_EQ_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #861
+ {DBGFIELD("CMPGU_LE_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #862
+ {DBGFIELD("CMPGU_LT_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #863
+ {DBGFIELD("CMPU_EQ_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #864
+ {DBGFIELD("CMPU_LE_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #865
+ {DBGFIELD("CMPU_LT_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #866
+ {DBGFIELD("CMP_EQ_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #867
+ {DBGFIELD("CMP_LE_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #868
+ {DBGFIELD("CMP_LT_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #869
+ {DBGFIELD("DPAQ_SA_L_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #870
+ {DBGFIELD("DPAQ_S_W_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #871
+ {DBGFIELD("DPAU_H_QBL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #872
+ {DBGFIELD("DPAU_H_QBR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #873
+ {DBGFIELD("DPSQ_SA_L_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #874
+ {DBGFIELD("DPSQ_S_W_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #875
+ {DBGFIELD("DPSU_H_QBL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #876
+ {DBGFIELD("DPSU_H_QBR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #877
+ {DBGFIELD("EXTPDPV_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #878
+ {DBGFIELD("EXTPDP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #879
+ {DBGFIELD("EXTPV_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #880
+ {DBGFIELD("EXTP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #881
+ {DBGFIELD("EXTRV_RS_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #882
+ {DBGFIELD("EXTRV_R_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #883
+ {DBGFIELD("EXTRV_S_H_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #884
+ {DBGFIELD("EXTRV_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #885
+ {DBGFIELD("EXTR_RS_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #886
+ {DBGFIELD("EXTR_R_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #887
+ {DBGFIELD("EXTR_S_H_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #888
+ {DBGFIELD("EXTR_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #889
+ {DBGFIELD("INSV_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #890
+ {DBGFIELD("LBUX_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #891
+ {DBGFIELD("LHX_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #892
+ {DBGFIELD("LWX_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #893
+ {DBGFIELD("MADDU_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #894
+ {DBGFIELD("MADD_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #895
+ {DBGFIELD("MAQ_SA_W_PHL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #896
+ {DBGFIELD("MAQ_SA_W_PHR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #897
+ {DBGFIELD("MAQ_S_W_PHL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #898
+ {DBGFIELD("MAQ_S_W_PHR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #899
+ {DBGFIELD("MFHI_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #900
+ {DBGFIELD("MFLO_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #901
+ {DBGFIELD("MODSUB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #902
+ {DBGFIELD("MOVEP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #903
+ {DBGFIELD("MOVEP_MMR6") 0, false, false, 0, 0, 0, 0, 0, 0}, // #904
+ {DBGFIELD("MOVN_I_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #905
+ {DBGFIELD("MOVZ_I_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #906
+ {DBGFIELD("MSUBU_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #907
+ {DBGFIELD("MSUB_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #908
+ {DBGFIELD("MTHI_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #909
+ {DBGFIELD("MTHLIP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #910
+ {DBGFIELD("MTLO_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #911
+ {DBGFIELD("MULEQ_S_W_PHL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #912
+ {DBGFIELD("MULEQ_S_W_PHR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #913
+ {DBGFIELD("MULEU_S_PH_QBL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #914
+ {DBGFIELD("MULEU_S_PH_QBR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #915
+ {DBGFIELD("MULQ_RS_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #916
+ {DBGFIELD("MULSAQ_S_W_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #917
+ {DBGFIELD("MULTU_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #918
+ {DBGFIELD("MULT_DSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #919
+ {DBGFIELD("PACKRL_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #920
+ {DBGFIELD("PICK_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #921
+ {DBGFIELD("PICK_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #922
+ {DBGFIELD("PRECEQU_PH_QBLA_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #923
+ {DBGFIELD("PRECEQU_PH_QBL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #924
+ {DBGFIELD("PRECEQU_PH_QBRA_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #925
+ {DBGFIELD("PRECEQU_PH_QBR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #926
+ {DBGFIELD("PRECEQ_W_PHL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #927
+ {DBGFIELD("PRECEQ_W_PHR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #928
+ {DBGFIELD("PRECEU_PH_QBLA_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #929
+ {DBGFIELD("PRECEU_PH_QBL_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #930
+ {DBGFIELD("PRECEU_PH_QBRA_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #931
+ {DBGFIELD("PRECEU_PH_QBR_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #932
+ {DBGFIELD("PRECRQU_S_QB_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #933
+ {DBGFIELD("PRECRQ_PH_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #934
+ {DBGFIELD("PRECRQ_QB_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #935
+ {DBGFIELD("PRECRQ_RS_PH_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #936
+ {DBGFIELD("RADDU_W_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #937
+ {DBGFIELD("RDDSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #938
+ {DBGFIELD("REPLV_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #939
+ {DBGFIELD("REPLV_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #940
+ {DBGFIELD("REPL_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #941
+ {DBGFIELD("REPL_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #942
+ {DBGFIELD("SHILOV_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #943
+ {DBGFIELD("SHILO_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #944
+ {DBGFIELD("SHLLV_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #945
+ {DBGFIELD("SHLLV_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #946
+ {DBGFIELD("SHLLV_S_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #947
+ {DBGFIELD("SHLLV_S_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #948
+ {DBGFIELD("SHLL_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #949
+ {DBGFIELD("SHLL_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #950
+ {DBGFIELD("SHLL_S_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #951
+ {DBGFIELD("SHLL_S_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #952
+ {DBGFIELD("SHRAV_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #953
+ {DBGFIELD("SHRAV_R_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #954
+ {DBGFIELD("SHRAV_R_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #955
+ {DBGFIELD("SHRA_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #956
+ {DBGFIELD("SHRA_R_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #957
+ {DBGFIELD("SHRA_R_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #958
+ {DBGFIELD("SHRLV_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #959
+ {DBGFIELD("SHRL_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #960
+ {DBGFIELD("SUBQ_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #961
+ {DBGFIELD("SUBQ_S_PH_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #962
+ {DBGFIELD("SUBQ_S_W_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #963
+ {DBGFIELD("SUBU_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #964
+ {DBGFIELD("SUBU_S_QB_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #965
+ {DBGFIELD("WRDSP_MM") 0, false, false, 0, 0, 0, 0, 0, 0}, // #966
+ {DBGFIELD("ABSQ_S_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #967
+ {DBGFIELD("ADDQH_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #968
+ {DBGFIELD("ADDQH_R_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #969
+ {DBGFIELD("ADDQH_R_W_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #970
+ {DBGFIELD("ADDQH_W_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #971
+ {DBGFIELD("ADDUH_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #972
+ {DBGFIELD("ADDUH_R_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #973
+ {DBGFIELD("ADDU_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #974
+ {DBGFIELD("ADDU_S_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #975
+ {DBGFIELD("APPEND_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #976
+ {DBGFIELD("BALIGN_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #977
+ {DBGFIELD("CMPGDU_EQ_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #978
+ {DBGFIELD("CMPGDU_LE_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #979
+ {DBGFIELD("CMPGDU_LT_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #980
+ {DBGFIELD("DPA_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #981
+ {DBGFIELD("DPAQX_SA_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #982
+ {DBGFIELD("DPAQX_S_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #983
+ {DBGFIELD("DPAX_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #984
+ {DBGFIELD("DPS_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #985
+ {DBGFIELD("DPSQX_S_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #986
+ {DBGFIELD("DPSQX_SA_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #987
+ {DBGFIELD("DPSX_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #988
+ {DBGFIELD("MUL_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #989
+ {DBGFIELD("MUL_S_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #990
+ {DBGFIELD("MULQ_RS_W_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #991
+ {DBGFIELD("MULQ_S_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #992
+ {DBGFIELD("MULQ_S_W_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #993
+ {DBGFIELD("MULSA_W_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #994
+ {DBGFIELD("PRECR_QB_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #995
+ {DBGFIELD("PRECR_SRA_PH_W_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #996
+ {DBGFIELD("PRECR_SRA_R_PH_W_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #997
+ {DBGFIELD("PREPEND_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #998
+ {DBGFIELD("SHRA_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #999
+ {DBGFIELD("SHRA_R_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1000
+ {DBGFIELD("SHRAV_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1001
+ {DBGFIELD("SHRAV_R_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1002
+ {DBGFIELD("SHRL_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1003
+ {DBGFIELD("SHRLV_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1004
+ {DBGFIELD("SUBQH_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1005
+ {DBGFIELD("SUBQH_R_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1006
+ {DBGFIELD("SUBQH_W_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1007
+ {DBGFIELD("SUBQH_R_W_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1008
+ {DBGFIELD("SUBU_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1009
+ {DBGFIELD("SUBU_S_PH_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1010
+ {DBGFIELD("SUBUH_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1011
+ {DBGFIELD("SUBUH_R_QB_MMR2") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1012
+ {DBGFIELD("BPOSGE32C_MMR3") 0, false, false, 0, 0, 0, 0, 0, 0}, // #1013
+ {DBGFIELD("P5600WriteALU") 1, false, false, 36, 2, 1, 1, 0, 0}, // #1014
+ {DBGFIELD("P5600WriteAL2") 1, false, false, 1, 2, 1, 1, 0, 0}, // #1015
+}; // MipsP5600ModelSchedClasses
+
+static const llvm::MCSchedModel NoSchedModel = {
+ MCSchedModel::DefaultIssueWidth,
+ MCSchedModel::DefaultMicroOpBufferSize,
+ MCSchedModel::DefaultLoopMicroOpBufferSize,
+ MCSchedModel::DefaultLoadLatency,
+ MCSchedModel::DefaultHighLatency,
+ MCSchedModel::DefaultMispredictPenalty,
+ false, // PostRAScheduler
+ false, // CompleteModel
+ 0, // Processor ID
+ nullptr, nullptr, 0, 0, // No instruction-level machine model.
+ nullptr, // No Itinerary
+ nullptr // No extra processor descriptor
+};
+
+static const unsigned MipsGenericModelProcResourceSubUnits[] = {
+ 0, // Invalid
+};
+
+// {Name, NumUnits, SuperIdx, IsBuffered, SubUnitsIdxBegin}
+static const llvm::MCProcResourceDesc MipsGenericModelProcResources[] = {
+ {"InvalidUnit", 0, 0, 0, 0},
+ {"GenericALU", 1, 0, 1, nullptr}, // #1
+ {"GenericCOP0", 1, 0, 1, nullptr}, // #2
+ {"GenericCOP2", 1, 0, 1, nullptr}, // #3
+ {"GenericDSP", 1, 0, 1, nullptr}, // #4
+ {"GenericFPQ", 1, 0, 1, nullptr}, // #5
+ {"GenericFPUDivSqrt", 1, 5, -1, nullptr}, // #6, Super=GenericFPQ
+ {"GenericIssueALU", 1, 1, -1, nullptr}, // #7, Super=GenericALU
+ {"GenericIssueCOP0", 1, 2, -1, nullptr}, // #8, Super=GenericCOP0
+ {"GenericIssueCTISTD", 1, 1, -1, nullptr}, // #9, Super=GenericALU
+ {"GenericIssueDIV", 1, 19, -1, nullptr}, // #10, Super=GenericMDU
+ {"GenericIssueFPUL", 1, 5, -1, nullptr}, // #11, Super=GenericFPQ
+ {"GenericIssueFPULoad", 1, 5, -1, nullptr}, // #12, Super=GenericFPQ
+ {"GenericIssueFPUMove", 1, 5, -1, nullptr}, // #13, Super=GenericFPQ
+ {"GenericIssueFPUS", 1, 5, -1, nullptr}, // #14, Super=GenericFPQ
+ {"GenericIssueFPUStore", 1, 5, -1, nullptr}, // #15, Super=GenericFPQ
+ {"GenericIssueLDST", 1, 18, -1, nullptr}, // #16, Super=GenericLDST
+ {"GenericIssueMDU", 1, 1, -1, nullptr}, // #17, Super=GenericALU
+ {"GenericLDST", 1, 0, 1, nullptr}, // #18
+ {"GenericMDU", 1, 0, 1, nullptr}, // #19
+};
+
+static const llvm::MCSchedModel MipsGenericModel = {
+ 1, // IssueWidth
+ 0, // MicroOpBufferSize
+ MCSchedModel::DefaultLoopMicroOpBufferSize,
+ 2, // LoadLatency
+ 37, // HighLatency
+ 4, // MispredictPenalty
+ true, // PostRAScheduler
+ false, // CompleteModel
+ 1, // Processor ID
+ MipsGenericModelProcResources,
+ MipsGenericModelSchedClasses,
+ 20,
+ 1016,
+ nullptr, // No Itinerary
+ nullptr // No extra processor descriptor
+};
+
+static const unsigned MipsP5600ModelProcResourceSubUnits[] = {
+ 0, // Invalid
+};
+
+// {Name, NumUnits, SuperIdx, IsBuffered, SubUnitsIdxBegin}
+static const llvm::MCProcResourceDesc MipsP5600ModelProcResources[] = {
+ {"InvalidUnit", 0, 0, 0, 0},
+ {"P5600AGQ", 3, 0, 16, nullptr}, // #1
+ {"P5600AL2Div", 1, 0, -1, nullptr}, // #2
+ {"P5600ALQ", 1, 0, 16, nullptr}, // #3
+ {"P5600CTISTD", 1, 0, -1, nullptr}, // #4
+ {"P5600FPQ", 3, 0, 16, nullptr}, // #5
+ {"P5600FPUDivSqrt", 2, 0, -1, nullptr}, // #6
+ {"P5600IssueAL2", 1, 1, -1, nullptr}, // #7, Super=P5600AGQ
+ {"P5600IssueALU", 1, 3, -1, nullptr}, // #8, Super=P5600ALQ
+ {"P5600IssueCTISTD", 1, 1, -1, nullptr}, // #9, Super=P5600AGQ
+ {"P5600IssueFPUL", 1, 5, -1, nullptr}, // #10, Super=P5600FPQ
+ {"P5600IssueFPULoad", 1, 5, -1, nullptr}, // #11, Super=P5600FPQ
+ {"P5600IssueFPUS", 1, 5, -1, nullptr}, // #12, Super=P5600FPQ
+ {"P5600IssueLDST", 1, 1, -1, nullptr}, // #13, Super=P5600AGQ
+};
+
+static const llvm::MCSchedModel MipsP5600Model = {
+ 2, // IssueWidth
+ 48, // MicroOpBufferSize
+ MCSchedModel::DefaultLoopMicroOpBufferSize,
+ 4, // LoadLatency
+ MCSchedModel::DefaultHighLatency,
+ 8, // MispredictPenalty
+ false, // PostRAScheduler
+ false, // CompleteModel
+ 2, // Processor ID
+ MipsP5600ModelProcResources,
+ MipsP5600ModelSchedClasses,
+ 14,
+ 1016,
+ nullptr, // No Itinerary
+ nullptr // No extra processor descriptor
+};
+
+// Sorted (by key) array of itineraries for CPU subtype.
+extern const llvm::SubtargetInfoKV MipsProcSchedKV[] = {
+ { "mips1", (const void *)&MipsGenericModel },
+ { "mips2", (const void *)&MipsGenericModel },
+ { "mips3", (const void *)&MipsGenericModel },
+ { "mips32", (const void *)&MipsGenericModel },
+ { "mips32r2", (const void *)&MipsGenericModel },
+ { "mips32r3", (const void *)&MipsGenericModel },
+ { "mips32r5", (const void *)&MipsGenericModel },
+ { "mips32r6", (const void *)&MipsGenericModel },
+ { "mips4", (const void *)&MipsGenericModel },
+ { "mips5", (const void *)&MipsGenericModel },
+ { "mips64", (const void *)&MipsGenericModel },
+ { "mips64r2", (const void *)&MipsGenericModel },
+ { "mips64r3", (const void *)&MipsGenericModel },
+ { "mips64r5", (const void *)&MipsGenericModel },
+ { "mips64r6", (const void *)&MipsGenericModel },
+ { "octeon", (const void *)&MipsGenericModel },
+ { "p5600", (const void *)&MipsP5600Model },
+};
+
+#undef DBGFIELD
+namespace Mips_MC {
+unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
+ const MCInst *MI, unsigned CPUID) {
+ // Don't know how to resolve this scheduling class.
+ return 0;
+}
+} // end of namespace Mips_MC
+
+struct MipsGenMCSubtargetInfo : public MCSubtargetInfo {
+ MipsGenMCSubtargetInfo(const Triple &TT,
+ StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
+ ArrayRef<SubtargetFeatureKV> PD,
+ const SubtargetInfoKV *ProcSched,
+ const MCWriteProcResEntry *WPR,
+ const MCWriteLatencyEntry *WL,
+ const MCReadAdvanceEntry *RA, const InstrStage *IS,
+ const unsigned *OC, const unsigned *FP) :
+ MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,
+ WPR, WL, RA, IS, OC, FP) { }
+
+ unsigned resolveVariantSchedClass(unsigned SchedClass,
+ const MCInst *MI, unsigned CPUID) const override {
+ return Mips_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
+ }
+};
+
+static inline MCSubtargetInfo *createMipsMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
+ return new MipsGenMCSubtargetInfo(TT, CPU, FS, MipsFeatureKV, MipsSubTypeKV,
+ MipsProcSchedKV, MipsWriteProcResTable, MipsWriteLatencyTable, MipsReadAdvanceTable,
+ nullptr, nullptr, nullptr);
+}
+
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_MC_DESC
+
+
+#ifdef GET_SUBTARGETINFO_TARGET_DESC
+#undef GET_SUBTARGETINFO_TARGET_DESC
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+// ParseSubtargetFeatures - Parses features string setting specified
+// subtarget options.
+void llvm::MipsSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
+ LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
+ LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
+ InitMCProcessorInfo(CPU, FS);
+ const FeatureBitset& Bits = getFeatureBits();
+ if (Bits[Mips::FeatureCRC]) HasCRC = true;
+ if (Bits[Mips::FeatureCnMips]) HasCnMips = true;
+ if (Bits[Mips::FeatureDSP]) HasDSP = true;
+ if (Bits[Mips::FeatureDSPR2]) HasDSPR2 = true;
+ if (Bits[Mips::FeatureDSPR3]) HasDSPR3 = true;
+ if (Bits[Mips::FeatureEVA]) HasEVA = true;
+ if (Bits[Mips::FeatureFP64Bit]) IsFP64bit = true;
+ if (Bits[Mips::FeatureFPXX]) IsFPXX = true;
+ if (Bits[Mips::FeatureGINV]) HasGINV = true;
+ if (Bits[Mips::FeatureGP64Bit]) IsGP64bit = true;
+ if (Bits[Mips::FeatureLongCalls]) UseLongCalls = true;
+ if (Bits[Mips::FeatureMSA]) HasMSA = true;
+ if (Bits[Mips::FeatureMT]) HasMT = true;
+ if (Bits[Mips::FeatureMadd4]) DisableMadd4 = true;
+ if (Bits[Mips::FeatureMicroMips]) InMicroMipsMode = true;
+ if (Bits[Mips::FeatureMips1] && MipsArchVersion < Mips1) MipsArchVersion = Mips1;
+ if (Bits[Mips::FeatureMips2] && MipsArchVersion < Mips2) MipsArchVersion = Mips2;
+ if (Bits[Mips::FeatureMips3] && MipsArchVersion < Mips3) MipsArchVersion = Mips3;
+ if (Bits[Mips::FeatureMips3_32]) HasMips3_32 = true;
+ if (Bits[Mips::FeatureMips3_32r2]) HasMips3_32r2 = true;
+ if (Bits[Mips::FeatureMips4] && MipsArchVersion < Mips4) MipsArchVersion = Mips4;
+ if (Bits[Mips::FeatureMips4_32]) HasMips4_32 = true;
+ if (Bits[Mips::FeatureMips4_32r2]) HasMips4_32r2 = true;
+ if (Bits[Mips::FeatureMips5] && MipsArchVersion < Mips5) MipsArchVersion = Mips5;
+ if (Bits[Mips::FeatureMips5_32r2]) HasMips5_32r2 = true;
+ if (Bits[Mips::FeatureMips16]) InMips16Mode = true;
+ if (Bits[Mips::FeatureMips32] && MipsArchVersion < Mips32) MipsArchVersion = Mips32;
+ if (Bits[Mips::FeatureMips32r2] && MipsArchVersion < Mips32r2) MipsArchVersion = Mips32r2;
+ if (Bits[Mips::FeatureMips32r3] && MipsArchVersion < Mips32r3) MipsArchVersion = Mips32r3;
+ if (Bits[Mips::FeatureMips32r5] && MipsArchVersion < Mips32r5) MipsArchVersion = Mips32r5;
+ if (Bits[Mips::FeatureMips32r6] && MipsArchVersion < Mips32r6) MipsArchVersion = Mips32r6;
+ if (Bits[Mips::FeatureMips64] && MipsArchVersion < Mips64) MipsArchVersion = Mips64;
+ if (Bits[Mips::FeatureMips64r2] && MipsArchVersion < Mips64r2) MipsArchVersion = Mips64r2;
+ if (Bits[Mips::FeatureMips64r3] && MipsArchVersion < Mips64r3) MipsArchVersion = Mips64r3;
+ if (Bits[Mips::FeatureMips64r5] && MipsArchVersion < Mips64r5) MipsArchVersion = Mips64r5;
+ if (Bits[Mips::FeatureMips64r6] && MipsArchVersion < Mips64r6) MipsArchVersion = Mips64r6;
+ if (Bits[Mips::FeatureNaN2008]) IsNaN2008bit = true;
+ if (Bits[Mips::FeatureNoABICalls]) NoABICalls = true;
+ if (Bits[Mips::FeatureNoOddSPReg]) UseOddSPReg = false;
+ if (Bits[Mips::FeaturePTR64Bit]) IsPTR64bit = true;
+ if (Bits[Mips::FeatureSingleFloat]) IsSingleFloat = true;
+ if (Bits[Mips::FeatureSoftFloat]) IsSoftFloat = true;
+ if (Bits[Mips::FeatureSym32]) HasSym32 = true;
+ if (Bits[Mips::FeatureUseIndirectJumpsHazard]) UseIndirectJumpsHazard = true;
+ if (Bits[Mips::FeatureUseTCCInDIV]) UseTCCInDIV = false;
+ if (Bits[Mips::FeatureVFPU]) HasVFPU = true;
+ if (Bits[Mips::FeatureVirt]) HasVirt = true;
+ if (Bits[Mips::ImplP5600] && ProcImpl < MipsSubtarget::CPU::P5600) ProcImpl = MipsSubtarget::CPU::P5600;
+}
+#endif // GET_SUBTARGETINFO_TARGET_DESC
+
+
+#ifdef GET_SUBTARGETINFO_HEADER
+#undef GET_SUBTARGETINFO_HEADER
+
+namespace llvm {
+class DFAPacketizer;
+namespace Mips_MC {
+unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
+}
+
+struct MipsGenSubtargetInfo : public TargetSubtargetInfo {
+ explicit MipsGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
+public:
+ unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
+ unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
+ DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
+};
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_HEADER
+
+
+#ifdef GET_SUBTARGETINFO_CTOR
+#undef GET_SUBTARGETINFO_CTOR
+
+#include "llvm/CodeGen/TargetSchedule.h"
+
+namespace llvm {
+extern const llvm::SubtargetFeatureKV MipsFeatureKV[];
+extern const llvm::SubtargetFeatureKV MipsSubTypeKV[];
+extern const llvm::SubtargetInfoKV MipsProcSchedKV[];
+extern const llvm::MCWriteProcResEntry MipsWriteProcResTable[];
+extern const llvm::MCWriteLatencyEntry MipsWriteLatencyTable[];
+extern const llvm::MCReadAdvanceEntry MipsReadAdvanceTable[];
+MipsGenSubtargetInfo::MipsGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
+ : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(MipsFeatureKV, 48), makeArrayRef(MipsSubTypeKV, 17),
+ MipsProcSchedKV, MipsWriteProcResTable, MipsWriteLatencyTable, MipsReadAdvanceTable,
+ nullptr, nullptr, nullptr) {}
+
+unsigned MipsGenSubtargetInfo
+::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
+ switch (SchedClass) {
+ case 477: // ADD
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 478: // ADDi
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 479: // ADDiu
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 480: // ANDi
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 481: // ORi
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 482: // ROTR
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 483: // SEB
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 484: // SEH
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 485: // SLT_SLTu
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 486: // SLL
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 487: // SRA
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 488: // SRL
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 489: // XORi
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 490: // ADDu
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 491: // SLLV
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 492: // SRAV
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 493: // SRLV
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 494: // LSA
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 495: // COPY
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ case 690: // ROTRV
+ if (SchedModel->getProcessorID() == 2) { // MipsP5600Model
+ if ((1))
+ return 1014; // P5600WriteALU
+ if ((0))
+ return 1015; // P5600WriteAL2
+ }
+ break;
+ };
+ report_fatal_error("Expected a variant SchedClass");
+} // MipsGenSubtargetInfo::resolveSchedClass
+
+unsigned MipsGenSubtargetInfo
+::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
+ return Mips_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
+} // MipsGenSubtargetInfo::resolveVariantSchedClass
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_CTOR
+
diff --git a/third_party/llvm-7.0/configs/linux/include/llvm/Config/AsmParsers.def b/third_party/llvm-7.0/configs/linux/include/llvm/Config/AsmParsers.def
index d9f2476..49d8e31 100644
--- a/third_party/llvm-7.0/configs/linux/include/llvm/Config/AsmParsers.def
+++ b/third_party/llvm-7.0/configs/linux/include/llvm/Config/AsmParsers.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_ASM_PARSER(X86)
#endif
+#if defined(__mips__)
+LLVM_ASM_PARSER(Mips)
+#endif
#undef LLVM_ASM_PARSER
diff --git a/third_party/llvm-7.0/configs/linux/include/llvm/Config/AsmPrinters.def b/third_party/llvm-7.0/configs/linux/include/llvm/Config/AsmPrinters.def
index e742776..84a2c42 100644
--- a/third_party/llvm-7.0/configs/linux/include/llvm/Config/AsmPrinters.def
+++ b/third_party/llvm-7.0/configs/linux/include/llvm/Config/AsmPrinters.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_ASM_PRINTER(X86)
#endif
+#if defined(__mips__)
+LLVM_ASM_PRINTER(Mips)
+#endif
#undef LLVM_ASM_PRINTER
diff --git a/third_party/llvm-7.0/configs/linux/include/llvm/Config/Disassemblers.def b/third_party/llvm-7.0/configs/linux/include/llvm/Config/Disassemblers.def
index e863f92..e3bb9ce 100644
--- a/third_party/llvm-7.0/configs/linux/include/llvm/Config/Disassemblers.def
+++ b/third_party/llvm-7.0/configs/linux/include/llvm/Config/Disassemblers.def
@@ -33,6 +33,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_DISASSEMBLER(X86)
#endif
+#if defined(__mips__)
+LLVM_DISASSEMBLER(Mips)
+#endif
#undef LLVM_DISASSEMBLER
diff --git a/third_party/llvm-7.0/configs/linux/include/llvm/Config/Targets.def b/third_party/llvm-7.0/configs/linux/include/llvm/Config/Targets.def
index 6968ed1..aaf9378 100644
--- a/third_party/llvm-7.0/configs/linux/include/llvm/Config/Targets.def
+++ b/third_party/llvm-7.0/configs/linux/include/llvm/Config/Targets.def
@@ -32,6 +32,9 @@
#if defined(__i386__) || defined(__x86_64__)
LLVM_TARGET(X86)
#endif
+#if defined(__mips__)
+LLVM_TARGET(Mips)
+#endif
#undef LLVM_TARGET
diff --git a/third_party/llvm-7.0/configs/linux/include/llvm/Config/config.h b/third_party/llvm-7.0/configs/linux/include/llvm/Config/config.h
index 3b70fa7..bedb306 100644
--- a/third_party/llvm-7.0/configs/linux/include/llvm/Config/config.h
+++ b/third_party/llvm-7.0/configs/linux/include/llvm/Config/config.h
@@ -299,6 +299,8 @@
#define LLVM_DEFAULT_TARGET_TRIPLE "armv7-linux-gnueabihf"
#elif defined(__aarch64__)
#define LLVM_DEFAULT_TARGET_TRIPLE "aarch64-linux-gnu"
+#elif defined(__mips__)
+#define LLVM_DEFAULT_TARGET_TRIPLE "mipsel-linux-gnu"
#else
#error "unknown architecture"
#endif
diff --git a/third_party/llvm-7.0/configs/linux/include/llvm/Config/llvm-config.h b/third_party/llvm-7.0/configs/linux/include/llvm/Config/llvm-config.h
index 64dbd67..174aca9 100644
--- a/third_party/llvm-7.0/configs/linux/include/llvm/Config/llvm-config.h
+++ b/third_party/llvm-7.0/configs/linux/include/llvm/Config/llvm-config.h
@@ -29,6 +29,8 @@
#define LLVM_DEFAULT_TARGET_TRIPLE "armv7-linux-gnueabihf"
#elif defined(__aarch64__)
#define LLVM_DEFAULT_TARGET_TRIPLE "aarch64-linux-gnu"
+#elif defined(__mips__)
+#define LLVM_DEFAULT_TARGET_TRIPLE "mipsel-linux-gnu"
#else
#error "unknown architecture"
#endif
@@ -48,6 +50,8 @@
#define LLVM_HOST_TRIPLE "armv7-linux-gnueabihf"
#elif defined(__aarch64__)
#define LLVM_HOST_TRIPLE "aarch64-linux-gnu"
+#elif defined(__mips__)
+#define LLVM_HOST_TRIPLE "mipsel-linux-gnu"
#else
#error "unknown architecture"
#endif
@@ -59,6 +63,8 @@
#define LLVM_NATIVE_ARCH ARM
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ARCH X86
+#elif defined(__mips__)
+#define LLVM_NATIVE_ARCH Mips
#else
#error "unknown architecture"
#endif
@@ -70,6 +76,8 @@
#define LLVM_NATIVE_ASMPARSER LLVMInitializeARMAsmParser
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
+#elif defined(__mips__)
+#define LLVM_NATIVE_ASMPARSER LLVMInitializeMipsAsmParser
#else
#error "unknown architecture"
#endif
@@ -81,6 +89,8 @@
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeARMAsmPrinter
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
+#elif defined(__mips__)
+#define LLVM_NATIVE_ASMPRINTER LLVMInitializeMipsAsmPrinter
#else
#error "unknown architecture"
#endif
@@ -92,6 +102,8 @@
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeARMDisassembler
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeX86Disassembler
+#elif defined(__mips__)
+#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeMipsDisassembler
#else
#error "unknown architecture"
#endif
@@ -103,6 +115,8 @@
#define LLVM_NATIVE_TARGET LLVMInitializeARMTarget
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGET LLVMInitializeX86Target
+#elif defined(__mips__)
+#define LLVM_NATIVE_TARGET LLVMInitializeMipsTarget
#else
#error "unknown architecture"
#endif
@@ -114,6 +128,8 @@
#define LLVM_NATIVE_TARGETINFO LLVMInitializeARMTargetInfo
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo
+#elif defined(__mips__)
+#define LLVM_NATIVE_TARGETINFO LLVMInitializeMipsTargetInfo
#else
#error "unknown architecture"
#endif
@@ -125,6 +141,8 @@
#define LLVM_NATIVE_TARGETMC LLVMInitializeARMTargetMC
#elif defined(__i386__) || defined(__x86_64__)
#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC
+#elif defined(__mips__)
+#define LLVM_NATIVE_TARGETMC LLVMInitializeMipsTargetMC
#else
#error "unknown architecture"
#endif
