[SubZero] Fix code generation for vector type The patch fixes legalizeToReg issues in vector code generation. The patch also generates JALR for pointer to function and corrects encoding of FP conditional move instruction. R=stichnot@chromium.org Review URL: https://codereview.chromium.org/2468133002 . Patch from Jaydeep Patil <jaydeep.patil@imgtec.com>.
diff --git a/src/IceAssemblerMIPS32.cpp b/src/IceAssemblerMIPS32.cpp index ca8a631..c35dff0 100644 --- a/src/IceAssemblerMIPS32.cpp +++ b/src/IceAssemblerMIPS32.cpp
@@ -645,6 +645,17 @@ nop(); } +void AssemblerMIPS32::jalr(const Operand *OpRs, const Operand *OpRd) { + IValueT Opcode = 0x00000009; + const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); + const IValueT Rd = + (OpRd == nullptr) ? 31 : encodeGPRegister(OpRd, "Rd", "jalr"); + Opcode |= Rd << 16; + Opcode |= Rs << 21; + emitInst(Opcode); + nop(); +} + void AssemblerMIPS32::lui(const Operand *OpRt, const Operand *OpImm, const RelocOp Reloc) { IValueT Opcode = 0x3C000000; @@ -833,13 +844,13 @@ void AssemblerMIPS32::movn_d(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt) { static constexpr IValueT Opcode = 0x44000013; - emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.d"); + emitCOP1FmtRtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.d"); } void AssemblerMIPS32::movn_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt) { static constexpr IValueT Opcode = 0x44000013; - emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s"); + emitCOP1FmtRtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s"); } void AssemblerMIPS32::movt(const Operand *OpRd, const Operand *OpRs,
diff --git a/src/IceAssemblerMIPS32.h b/src/IceAssemblerMIPS32.h index a444b06..dd70790 100644 --- a/src/IceAssemblerMIPS32.h +++ b/src/IceAssemblerMIPS32.h
@@ -188,6 +188,8 @@ void jal(const ConstantRelocatable *Target); + void jalr(const Operand *OpRs, const Operand *OpRd); + void lui(const Operand *OpRt, const Operand *OpImm, const RelocOp Reloc); void ldc1(const Operand *OpRt, const Operand *OpBase, const Operand *OpOff,
diff --git a/src/IceInstMIPS32.cpp b/src/IceInstMIPS32.cpp index 8cf5593..b627a20 100644 --- a/src/IceInstMIPS32.cpp +++ b/src/IceInstMIPS32.cpp
@@ -552,7 +552,7 @@ CallTarget->emitWithoutPrefix(Func->getTarget()); } else { Str << "\t" - "jal" + "jalr" "\t"; getCallTarget()->emit(Func); } @@ -561,11 +561,14 @@ void InstMIPS32Call::emitIAS(const Cfg *Func) const { assert(getSrcSize() == 1); auto *Asm = Func->getAssembler<MIPS32::AssemblerMIPS32>(); - if (const auto *CallTarget = - llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) { + if (llvm::isa<ConstantInteger32>(getCallTarget())) { + llvm::report_fatal_error("MIPS32Call to ConstantInteger32"); + } else if (const auto *CallTarget = + llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) { Asm->jal(CallTarget); } else { - llvm::report_fatal_error("MIPS32Call: Invalid operand"); + const Operand *ImplicitRA = nullptr; + Asm->jalr(getCallTarget(), ImplicitRA); } }
diff --git a/src/IceTargetLoweringMIPS32.cpp b/src/IceTargetLoweringMIPS32.cpp index a9e59e2..9957112 100644 --- a/src/IceTargetLoweringMIPS32.cpp +++ b/src/IceTargetLoweringMIPS32.cpp
@@ -3247,12 +3247,15 @@ if (ReturnReg) { if (RetVecFloat) { auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest); + auto *TBase = legalizeToReg(RetVecFloat); for (SizeT i = 0; i < DestVecOn32->ContainersPerVector; ++i) { auto *Var = DestVecOn32->getContainers()[i]; + auto *TVar = makeReg(IceType_i32); OperandMIPS32Mem *Mem = OperandMIPS32Mem::create( - Func, IceType_i32, RetVecFloat, + Func, IceType_i32, TBase, llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(i * 4))); - _lw(Var, Mem); + _lw(TVar, Mem); + _mov(Var, TVar); } } else if (auto *RetVec = llvm::dyn_cast<VariableVecOn32>(ReturnReg)) { auto *DestVecOn32 = llvm::cast<VariableVecOn32>(Dest); @@ -3538,7 +3541,8 @@ // Number of elements in each container uint32_t ElemPerCont = typeNumElements(Src0->getType()) / Src0R->ContainersPerVector; - auto *SrcE = Src0R->getContainers()[Index / ElemPerCont]; + auto *Src = Src0R->getContainers()[Index / ElemPerCont]; + auto *SrcE = legalizeToReg(Src); // Position of the element in the container uint32_t PosInCont = Index % ElemPerCont; if (ElemPerCont == 1) { @@ -4050,7 +4054,10 @@ uint32_t ElemPerCont = typeNumElements(Src0->getType()) / Src0R->ContainersPerVector; // Source Element - auto *SrcE = Src0R->getContainers()[Index / ElemPerCont]; + auto *Src = Src0R->getContainers()[Index / ElemPerCont]; + auto *SrcE = Src; + if (ElemPerCont > 1) + SrcE = legalizeToReg(Src); // Dest is a vector auto *VDest = llvm::dyn_cast<VariableVecOn32>(Dest); VDest->initVecElement(Func); @@ -4067,6 +4074,7 @@ auto *TReg3 = makeReg(Src1R->getType()); auto *TReg4 = makeReg(Src1R->getType()); auto *TReg5 = makeReg(Src1R->getType()); + auto *TDReg = makeReg(Src1R->getType()); // Position of the element in the container uint32_t PosInCont = Index % ElemPerCont; // Load source vector in a temporary vector @@ -4089,13 +4097,15 @@ _andi(TReg1, Src1R, 0xffff); // Clear upper 16-bits of source _srl(TReg2, SrcE, 16); _sll(TReg3, TReg2, 16); // Clear lower 16-bits of element - _or(DstE, TReg1, TReg3); + _or(TDReg, TReg1, TReg3); + _mov(DstE, TDReg); break; case 1: _sll(TReg1, Src1R, 16); // Clear lower 16-bits of source _sll(TReg2, SrcE, 16); _srl(TReg3, TReg2, 16); // Clear upper 16-bits of element - _or(DstE, TReg1, TReg3); + _or(TDReg, TReg1, TReg3); + _mov(DstE, TDReg); break; default: llvm::report_fatal_error("InsertElement: Invalid PosInCont"); @@ -4107,7 +4117,8 @@ _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source _srl(TReg2, SrcE, 8); _sll(TReg3, TReg2, 8); // Clear bits[7:0] of element - _or(DstE, TReg1, TReg3); + _or(TDReg, TReg1, TReg3); + _mov(DstE, TDReg); break; case 1: _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source @@ -4115,7 +4126,8 @@ _lui(TReg2, Ctx->getConstantInt32(0xffff)); _ori(TReg3, TReg2, 0x00ff); _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element - _or(DstE, TReg5, TReg4); + _or(TDReg, TReg5, TReg4); + _mov(DstE, TDReg); break; case 2: _andi(TReg1, Src1R, 0xff); // Clear bits[31:8] of source @@ -4123,13 +4135,15 @@ _lui(TReg2, Ctx->getConstantInt32(0xff00)); _ori(TReg3, TReg2, 0xffff); _and(TReg4, SrcE, TReg3); // Clear bits[15:8] of element - _or(DstE, TReg5, TReg4); + _or(TDReg, TReg5, TReg4); + _mov(DstE, TDReg); break; case 3: _srl(TReg1, Src1R, 24); // Position in the destination _sll(TReg2, SrcE, 8); _srl(TReg3, TReg2, 8); // Clear bits[31:24] of element - _or(DstE, TReg1, TReg3); + _or(TDReg, TReg1, TReg3); + _mov(DstE, TDReg); break; default: llvm::report_fatal_error("InsertElement: Invalid PosInCont"); @@ -4746,7 +4760,7 @@ case IceType_v16i8: case IceType_v8i16: case IceType_v4i32: { - auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0); + auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); Variable *V0 = legalizeToReg(SrcVec->getContainers()[0], RegMIPS32::Reg_V0); Variable *V1 = @@ -4762,7 +4776,7 @@ break; } case IceType_v4f32: { - auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(Src0); + auto *SrcVec = llvm::dyn_cast<VariableVecOn32>(legalizeUndef(Src0)); Reg = getImplicitRet(); auto *RegT = legalizeToReg(Reg); // Return the vector through buffer in implicit argument a0 @@ -4806,13 +4820,13 @@ if (DestTy == IceType_i64) { DestR = llvm::cast<Variable>(loOperand(Dest)); DestHiR = llvm::cast<Variable>(hiOperand(Dest)); - SrcTR = legalizeToReg(loOperand(Instr->getTrueOperand())); - SrcTHiR = legalizeToReg(hiOperand(Instr->getTrueOperand())); - SrcFR = legalizeToReg(loOperand(Instr->getFalseOperand())); - SrcFHiR = legalizeToReg(hiOperand(Instr->getFalseOperand())); + SrcTR = legalizeToReg(loOperand(legalizeUndef(Instr->getTrueOperand()))); + SrcTHiR = legalizeToReg(hiOperand(legalizeUndef(Instr->getTrueOperand()))); + SrcFR = legalizeToReg(loOperand(legalizeUndef(Instr->getFalseOperand()))); + SrcFHiR = legalizeToReg(hiOperand(legalizeUndef(Instr->getFalseOperand()))); } else { - SrcTR = legalizeToReg(Instr->getTrueOperand()); - SrcFR = legalizeToReg(Instr->getFalseOperand()); + SrcTR = legalizeToReg(legalizeUndef(Instr->getTrueOperand())); + SrcFR = legalizeToReg(legalizeUndef(Instr->getFalseOperand())); } Variable *ConditionR = legalizeToReg(Instr->getCondition());
diff --git a/tests_lit/llvm2ice_tests/vector-arg.ll b/tests_lit/llvm2ice_tests/vector-arg.ll index 64698d6..e625f48 100644 --- a/tests_lit/llvm2ice_tests/vector-arg.ll +++ b/tests_lit/llvm2ice_tests/vector-arg.ll
@@ -560,18 +560,19 @@ ; MIPS32: sw a3,{{.*}}(sp) ; MIPS32: move a2,v0 ; MIPS32: move a3,a1 -; MIPS32: jal 0 <test_returning_arg0> 494: R_MIPS_26 VectorReturn +; MIPS32: jal 0 <test_returning_arg0> {{.*}} R_MIPS_26 VectorReturn ; MIPS32: nop ; MIPS32: lw v0,0(s0) ; MIPS32: lw v1,4(s0) -; MIPS32: lw a1,8(s0) +; MIPS32: lw a0,8(s0) +; MIPS32: move a1,a0 ; MIPS32: lw s0,12(s0) ; MIPS32: addiu a0,sp,32 ; MIPS32: sw a1,{{.*}}(sp) ; MIPS32: sw s0,{{.*}}(sp) ; MIPS32: move a2,v0 ; MIPS32: move a3,v1 -; MIPS32: jal 0 <test_returning_arg0> 4c0: R_MIPS_26 VectorReturn +; MIPS32: jal 0 <test_returning_arg0> {{.*}} R_MIPS_26 VectorReturn ; MIPS32: nop ; MIPS32: move sp,s8 ; MIPS32: lw s0,{{.*}}(sp)
diff --git a/tests_lit/llvm2ice_tests/vector-cast.ll b/tests_lit/llvm2ice_tests/vector-cast.ll index a987d8c..a23a1cd 100644 --- a/tests_lit/llvm2ice_tests/vector-cast.ll +++ b/tests_lit/llvm2ice_tests/vector-cast.ll
@@ -33,7 +33,8 @@ ; X8632: pcmpgtb ; ARM32: vshl.s8 ; ARM32-NEXT: vshr.s8 -; MIPS32: andi t2,a0,0xff +; MIPS32: move t2,a0 +; MIPS32: andi t2,t2,0xff ; MIPS32: andi t2,t2,0x1 ; MIPS32: sll t2,t2,0x1f ; MIPS32: sra t2,t2,0x1f @@ -41,7 +42,8 @@ ; MIPS32: srl v0,v0,0x8 ; MIPS32: sll v0,v0,0x8 ; MIPS32: or t2,t2,v0 -; MIPS32: srl v0,a0,0x8 +; MIPS32: move v0,a0 +; MIPS32: srl v0,v0,0x8 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f @@ -52,7 +54,8 @@ ; MIPS32: ori t3,t3,0xff ; MIPS32: and t2,t2,t3 ; MIPS32: or v0,v0,t2 -; MIPS32: srl t2,a0,0x10 +; MIPS32: move t2,a0 +; MIPS32: srl t2,t2,0x10 ; MIPS32: andi t2,t2,0xff ; MIPS32: andi t2,t2,0x1 ; MIPS32: sll t2,t2,0x1f @@ -71,7 +74,8 @@ ; MIPS32: sll t2,t2,0x8 ; MIPS32: srl t2,t2,0x8 ; MIPS32: or a0,a0,t2 -; MIPS32: andi v0,a1,0xff +; MIPS32: move v0,a1 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f ; MIPS32: sra v0,v0,0x1f @@ -79,7 +83,8 @@ ; MIPS32: srl v1,v1,0x8 ; MIPS32: sll v1,v1,0x8 ; MIPS32: or v0,v0,v1 -; MIPS32: srl v1,a1,0x8 +; MIPS32: move v1,a1 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0x1 ; MIPS32: sll v1,v1,0x1f @@ -90,7 +95,8 @@ ; MIPS32: ori t2,t2,0xff ; MIPS32: and v0,v0,t2 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a1,0x10 +; MIPS32: move v0,a1 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f @@ -109,7 +115,8 @@ ; MIPS32: sll v0,v0,0x8 ; MIPS32: srl v0,v0,0x8 ; MIPS32: or a1,a1,v0 -; MIPS32: andi v0,a2,0xff +; MIPS32: move v0,a2 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f ; MIPS32: sra v0,v0,0x1f @@ -117,7 +124,8 @@ ; MIPS32: srl t0,t0,0x8 ; MIPS32: sll t0,t0,0x8 ; MIPS32: or v0,v0,t0 -; MIPS32: srl v1,a2,0x8 +; MIPS32: move v1,a2 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0x1 ; MIPS32: sll v1,v1,0x1f @@ -128,7 +136,8 @@ ; MIPS32: ori t0,t0,0xff ; MIPS32: and v0,v0,t0 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a2,0x10 +; MIPS32: move v0,a2 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f @@ -147,7 +156,8 @@ ; MIPS32: sll v0,v0,0x8 ; MIPS32: srl v0,v0,0x8 ; MIPS32: or a2,a2,v0 -; MIPS32: andi v0,a3,0xff +; MIPS32: move v0,a3 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f ; MIPS32: sra v0,v0,0x1f @@ -155,7 +165,8 @@ ; MIPS32: srl t1,t1,0x8 ; MIPS32: sll t1,t1,0x8 ; MIPS32: or v0,v0,t1 -; MIPS32: srl v1,a3,0x8 +; MIPS32: move v1,a3 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0x1 ; MIPS32: sll v1,v1,0x1f @@ -166,7 +177,8 @@ ; MIPS32: ori t0,t0,0xff ; MIPS32: and v0,v0,t0 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a3,0x10 +; MIPS32: move v0,a3 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f @@ -201,7 +213,8 @@ ; MIPS32: move v1,zero ; MIPS32: move t0,zero ; MIPS32: move t1,zero -; MIPS32: andi t2,a0,0xffff +; MIPS32: move t2,a0 +; MIPS32: andi t2,t2,0xffff ; MIPS32: andi t2,t2,0x1 ; MIPS32: sll t2,t2,0x1f ; MIPS32: sra t2,t2,0x1f @@ -217,7 +230,8 @@ ; MIPS32: sll t2,t2,0x10 ; MIPS32: srl t2,t2,0x10 ; MIPS32: or a0,a0,t2 -; MIPS32: andi v0,a1,0xffff +; MIPS32: move v0,a1 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f ; MIPS32: sra v0,v0,0x1f @@ -233,7 +247,8 @@ ; MIPS32: sll v0,v0,0x10 ; MIPS32: srl v0,v0,0x10 ; MIPS32: or a1,a1,v0 -; MIPS32: andi v0,a2,0xffff +; MIPS32: move v0,a2 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f ; MIPS32: sra v0,v0,0x1f @@ -249,7 +264,8 @@ ; MIPS32: sll v0,v0,0x10 ; MIPS32: srl v0,v0,0x10 ; MIPS32: or a2,a2,v0 -; MIPS32: andi v0,a3,0xffff +; MIPS32: move v0,a3 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0x1 ; MIPS32: sll v0,v0,0x1f ; MIPS32: sra v0,v0,0x1f @@ -305,14 +321,16 @@ ; X8632: pand ; ARM32: vmov.i8 [[S:.*]], #1 ; ARM32-NEXT: vand {{.*}}, [[S]] -; MIPS32: andi t2,a0,0xff +; MIPS32: move t2,a0 +; MIPS32: andi t2,t2,0xff ; MIPS32: andi t2,t2,0x1 ; MIPS32: andi t2,t2,0x1 ; MIPS32: andi t2,t2,0xff ; MIPS32: srl v0,v0,0x8 ; MIPS32: sll v0,v0,0x8 ; MIPS32: or t2,t2,v0 -; MIPS32: srl v0,a0,0x8 +; MIPS32: move v0,a0 +; MIPS32: srl v0,v0,0x8 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 @@ -322,7 +340,8 @@ ; MIPS32: ori t3,t3,0xff ; MIPS32: and t2,t2,t3 ; MIPS32: or v0,v0,t2 -; MIPS32: srl t2,a0,0x10 +; MIPS32: move t2,a0 +; MIPS32: srl t2,t2,0x10 ; MIPS32: andi t2,t2,0xff ; MIPS32: andi t2,t2,0x1 ; MIPS32: andi t2,t2,0x1 @@ -339,14 +358,16 @@ ; MIPS32: sll t2,t2,0x8 ; MIPS32: srl t2,t2,0x8 ; MIPS32: or a0,a0,t2 -; MIPS32: andi v0,a1,0xff +; MIPS32: move v0,a1 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0xff ; MIPS32: srl v1,v1,0x8 ; MIPS32: sll v1,v1,0x8 ; MIPS32: or v0,v0,v1 -; MIPS32: srl v1,a1,0x8 +; MIPS32: move v1,a1 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0x1 ; MIPS32: andi v1,v1,0x1 @@ -356,7 +377,8 @@ ; MIPS32: ori t2,t2,0xff ; MIPS32: and v0,v0,t2 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a1,0x10 +; MIPS32: move v0,a1 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 @@ -373,14 +395,16 @@ ; MIPS32: sll v0,v0,0x8 ; MIPS32: srl v0,v0,0x8 ; MIPS32: or a1,a1,v0 -; MIPS32: andi v0,a2,0xff +; MIPS32: move v0,a2 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0xff ; MIPS32: srl t0,t0,0x8 ; MIPS32: sll t0,t0,0x8 ; MIPS32: or v0,v0,t0 -; MIPS32: srl v1,a2,0x8 +; MIPS32: move v1,a2 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0x1 ; MIPS32: andi v1,v1,0x1 @@ -390,7 +414,8 @@ ; MIPS32: ori t0,t0,0xff ; MIPS32: and v0,v0,t0 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a2,0x10 +; MIPS32: move v0,a2 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 @@ -407,14 +432,16 @@ ; MIPS32: sll v0,v0,0x8 ; MIPS32: srl v0,v0,0x8 ; MIPS32: or a2,a2,v0 -; MIPS32: andi v0,a3,0xff +; MIPS32: move v0,a3 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0xff ; MIPS32: srl t1,t1,0x8 ; MIPS32: sll t1,t1,0x8 ; MIPS32: or v0,v0,t1 -; MIPS32: srl v1,a3,0x8 +; MIPS32: move v1,a3 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0x1 ; MIPS32: andi v1,v1,0x1 @@ -424,7 +451,8 @@ ; MIPS32: ori t0,t0,0xff ; MIPS32: and v0,v0,t0 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a3,0x10 +; MIPS32: move v0,a3 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 @@ -455,7 +483,8 @@ ; X8632: pand ; ARM32: vmov.i16 [[S:.*]], #1 ; ARM32-NEXT: vand {{.*}}, [[S]] -; MIPS32: andi t2,a0,0xffff +; MIPS32: move t2,a0 +; MIPS32: andi t2,t2,0xffff ; MIPS32: andi t2,t2,0x1 ; MIPS32: andi t2,t2,0x1 ; MIPS32: andi t2,t2,0xffff @@ -469,7 +498,8 @@ ; MIPS32: sll t2,t2,0x10 ; MIPS32: srl t2,t2,0x10 ; MIPS32: or a0,a0,t2 -; MIPS32: andi v0,a1,0xffff +; MIPS32: move v0,a1 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0xffff @@ -483,7 +513,8 @@ ; MIPS32: sll v0,v0,0x10 ; MIPS32: srl v0,v0,0x10 ; MIPS32: or a1,a1,v0 -; MIPS32: andi v0,a2,0xffff +; MIPS32: move v0,a2 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0xffff @@ -497,7 +528,8 @@ ; MIPS32: sll v0,v0,0x10 ; MIPS32: srl v0,v0,0x10 ; MIPS32: or a2,a2,v0 -; MIPS32: andi v0,a3,0xffff +; MIPS32: move v0,a3 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0x1 ; MIPS32: andi v0,v0,0xffff @@ -547,12 +579,14 @@ ; X8632: pcmpeqb ; X8632: psubb ; X8632: pand -; MIPS32: andi t2,a0,0xff +; MIPS32: move t2,a0 +; MIPS32: andi t2,t2,0xff ; MIPS32: andi t2,t2,0xff ; MIPS32: srl v0,v0,0x8 ; MIPS32: sll v0,v0,0x8 ; MIPS32: or t2,t2,v0 -; MIPS32: srl v0,a0,0x8 +; MIPS32: move v0,a0 +; MIPS32: srl v0,v0,0x8 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0xff ; MIPS32: sll v0,v0,0x8 @@ -560,7 +594,8 @@ ; MIPS32: ori t3,t3,0xff ; MIPS32: and t2,t2,t3 ; MIPS32: or v0,v0,t2 -; MIPS32: srl t2,a0,0x10 +; MIPS32: move t2,a0 +; MIPS32: srl t2,t2,0x10 ; MIPS32: andi t2,t2,0xff ; MIPS32: andi t2,t2,0xff ; MIPS32: sll t2,t2,0x10 @@ -573,12 +608,14 @@ ; MIPS32: sll t2,t2,0x8 ; MIPS32: srl t2,t2,0x8 ; MIPS32: or a0,a0,t2 -; MIPS32: andi v0,a1,0xff +; MIPS32: move v0,a1 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0xff ; MIPS32: srl v1,v1,0x8 ; MIPS32: sll v1,v1,0x8 ; MIPS32: or v0,v0,v1 -; MIPS32: srl v1,a1,0x8 +; MIPS32: move v1,a1 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0xff ; MIPS32: sll v1,v1,0x8 @@ -586,7 +623,8 @@ ; MIPS32: ori t2,t2,0xff ; MIPS32: and v0,v0,t2 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a1,0x10 +; MIPS32: move v0,a1 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0xff ; MIPS32: sll v0,v0,0x10 @@ -599,12 +637,14 @@ ; MIPS32: sll v0,v0,0x8 ; MIPS32: srl v0,v0,0x8 ; MIPS32: or a1,a1,v0 -; MIPS32: andi v0,a2,0xff +; MIPS32: move v0,a2 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0xff ; MIPS32: srl t0,t0,0x8 ; MIPS32: sll t0,t0,0x8 ; MIPS32: or v0,v0,t0 -; MIPS32: srl v1,a2,0x8 +; MIPS32: move v1,a2 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0xff ; MIPS32: sll v1,v1,0x8 @@ -612,7 +652,8 @@ ; MIPS32: ori t0,t0,0xff ; MIPS32: and v0,v0,t0 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a2,0x10 +; MIPS32: move v0,a2 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0xff ; MIPS32: sll v0,v0,0x10 @@ -625,12 +666,14 @@ ; MIPS32: sll v0,v0,0x8 ; MIPS32: srl v0,v0,0x8 ; MIPS32: or a2,a2,v0 -; MIPS32: andi v0,a3,0xff +; MIPS32: move v0,a3 +; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0xff ; MIPS32: srl t1,t1,0x8 ; MIPS32: sll t1,t1,0x8 ; MIPS32: or v0,v0,t1 -; MIPS32: srl v1,a3,0x8 +; MIPS32: move v1,a3 +; MIPS32: srl v1,v1,0x8 ; MIPS32: andi v1,v1,0xff ; MIPS32: andi v1,v1,0xff ; MIPS32: sll v1,v1,0x8 @@ -638,7 +681,8 @@ ; MIPS32: ori t0,t0,0xff ; MIPS32: and v0,v0,t0 ; MIPS32: or v1,v1,v0 -; MIPS32: srl v0,a3,0x10 +; MIPS32: move v0,a3 +; MIPS32: srl v0,v0,0x10 ; MIPS32: andi v0,v0,0xff ; MIPS32: andi v0,v0,0xff ; MIPS32: sll v0,v0,0x10 @@ -663,7 +707,8 @@ ; X8632: pcmpeqw ; X8632: psubw ; X8632: pand -; MIPS32: andi t2,a0,0xffff +; MIPS32: move t2,a0 +; MIPS32: andi t2,t2,0xffff ; MIPS32: andi t2,t2,0xffff ; MIPS32: srl v0,v0,0x10 ; MIPS32: sll v0,v0,0x10 @@ -673,7 +718,8 @@ ; MIPS32: sll t2,t2,0x10 ; MIPS32: srl t2,t2,0x10 ; MIPS32: or a0,a0,t2 -; MIPS32: andi v0,a1,0xffff +; MIPS32: move v0,a1 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0xffff ; MIPS32: srl v1,v1,0x10 ; MIPS32: sll v1,v1,0x10 @@ -683,7 +729,8 @@ ; MIPS32: sll v0,v0,0x10 ; MIPS32: srl v0,v0,0x10 ; MIPS32: or a1,a1,v0 -; MIPS32: andi v0,a2,0xffff +; MIPS32: move v0,a2 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0xffff ; MIPS32: srl t0,t0,0x10 ; MIPS32: sll t0,t0,0x10 @@ -693,7 +740,8 @@ ; MIPS32: sll v0,v0,0x10 ; MIPS32: srl v0,v0,0x10 ; MIPS32: or a2,a2,v0 -; MIPS32: andi v0,a3,0xffff +; MIPS32: move v0,a3 +; MIPS32: andi v0,v0,0xffff ; MIPS32: andi v0,v0,0xffff ; MIPS32: srl t1,t1,0x10 ; MIPS32: sll t1,t1,0x10
diff --git a/tests_lit/llvm2ice_tests/vector-icmp.ll b/tests_lit/llvm2ice_tests/vector-icmp.ll index 6059b1d..95c0961 100644 --- a/tests_lit/llvm2ice_tests/vector-icmp.ll +++ b/tests_lit/llvm2ice_tests/vector-icmp.ll
@@ -23,34 +23,34 @@ ; CHECK-NOT: pslld ; MIPS32-LABEL: test_sext_elimination -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]] -; MIPS32: sltiu [[R_E0]],[[R_E0]],1 -; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]] -; MIPS32: sltiu [[R_E1]],[[R_E1]],1 -; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]] -; MIPS32: sltiu [[R_E2]],[[R_E2]],1 -; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]] -; MIPS32: sltiu [[R_E3]],[[R_E3]],1 -; MIPS32: andi [[R_E0]],[[R_E0]],0x1 -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: sra [[R_E0]],[[R_E0]],0x1f -; MIPS32: andi [[R_E1]],[[R_E1]],0x1 -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: sra [[R_E1]],[[R_E1]],0x1f -; MIPS32: andi [[R_E2]],[[R_E2]],0x1 -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: sra [[R_E2]],[[R_E2]],0x1f -; MIPS32: andi [[R_E3]],[[R_E3]],0x1 -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: sra [[R_E3]],[[R_E3]],0x1f -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: xor [[T4:.*]],a0,[[T0]] +; MIPS32: sltiu [[T4]],[[T4]],1 +; MIPS32: xor [[T5:.*]],a1,[[T1]] +; MIPS32: sltiu [[T5]],[[T5]],1 +; MIPS32: xor [[T6:.*]],a2,[[T2]] +; MIPS32: sltiu [[T6]],[[T6]],1 +; MIPS32: xor [[T7:.*]],a3,[[T3]] +; MIPS32: sltiu [[T7]],[[T7]],1 +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sra [[T4]],[[T4]],0x1f +; MIPS32: andi [[T5]],[[T5]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sra [[T5]],[[T5]],0x1f +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sra [[T6]],[[T6]],0x1f +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sra [[T7]],[[T7]],0x1f +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i32_eq(<4 x i32> %a, <4 x i32> %b) { @@ -61,22 +61,22 @@ ; CHECK: pcmpeqd ; MIPS32-LABEL: test_icmp_v4i32_eq -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]] -; MIPS32: sltiu [[R_E0]],[[R_E0]],1 -; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]] -; MIPS32: sltiu [[R_E1]],[[R_E1]],1 -; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]] -; MIPS32: sltiu [[R_E2]],[[R_E2]],1 -; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]] -; MIPS32: sltiu [[R_E3]],[[R_E3]],1 -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: xor [[T4:.*]],a0,[[T0]] +; MIPS32: sltiu [[T4]],[[T4]],1 +; MIPS32: xor [[T5:.*]],a1,[[T1]] +; MIPS32: sltiu [[T5]],[[T5]],1 +; MIPS32: xor [[T6:.*]],a2,[[T2]] +; MIPS32: sltiu [[T6]],[[T6]],1 +; MIPS32: xor [[T7:.*]],a3,[[T3]] +; MIPS32: sltiu [[T7]],[[T7]],1 +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i32_ne(<4 x i32> %a, <4 x i32> %b) { @@ -88,22 +88,22 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v4i32_ne -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: xor [[R_E0:.*]],a0,[[B_E0]] -; MIPS32: sltu [[R_E0]],zero,[[R_E0]] -; MIPS32: xor [[R_E1:.*]],a1,[[B_E1]] -; MIPS32: sltu [[R_E1]],zero,[[R_E1]] -; MIPS32: xor [[R_E2:.*]],a2,[[B_E2]] -; MIPS32: sltu [[R_E2]],zero,[[R_E2]] -; MIPS32: xor [[R_E3:.*]],a3,[[B_E3]] -; MIPS32: sltu [[R_E3]],zero,[[R_E3]] -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: xor [[T4:.*]],a0,[[T0]] +; MIPS32: sltu [[T4]],zero,[[T4]] +; MIPS32: xor [[T5:.*]],a1,[[T1]] +; MIPS32: sltu [[T5]],zero,[[T5]] +; MIPS32: xor [[T6:.*]],a2,[[T2]] +; MIPS32: sltu [[T6]],zero,[[T6]] +; MIPS32: xor [[T7:.*]],a3,[[T3]] +; MIPS32: sltu [[T7]],zero,[[T7]] +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i32_sgt(<4 x i32> %a, <4 x i32> %b) { @@ -113,14 +113,16 @@ ; CHECK: pcmpgtd ; MIPS32-LABEL: test_icmp_v4i32_sgt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: slt [[R_E0:.*]],[[B_E0]],a0 -; MIPS32: slt [[R_E1:.*]],[[B_E1]],a1 -; MIPS32: slt [[R_E2:.*]],[[B_E2]],a2 -; MIPS32: slt [[R_E3:.*]],[[B_E3]],a3 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: slt v0,[[T0]],[[T4:.*]] +; MIPS32: slt v1,[[T1]],[[T5:.*]] +; MIPS32: slt [[T2]],[[T2]],[[T6:.*]] +; MIPS32: slt [[T3]],[[T3]],[[T7:.*]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <4 x i1> @test_icmp_v4i32_sle(<4 x i32> %a, <4 x i32> %b) { @@ -132,18 +134,20 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v4i32_sle -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: slt [[R_E0:.*]],[[B_E0]],a0 -; MIPS32: xori [[R_E0]],[[R_E0]],0x1 -; MIPS32: slt [[R_E1:.*]],[[B_E1]],a1 -; MIPS32: xori [[R_E1]],[[R_E1]],0x1 -; MIPS32: slt [[R_E2:.*]],[[B_E2]],a2 -; MIPS32: xori [[R_E2]],[[R_E2]],0x1 -; MIPS32: slt [[R_E3:.*]],[[B_E3]],a3 -; MIPS32: xori [[R_E3]],[[R_E3]],0x1 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: slt [[T0]],[[T0]],[[T4:.*]] +; MIPS32: xori v0,[[T0]],0x1 +; MIPS32: slt [[T1]],[[T1]],[[T5:.*]] +; MIPS32: xori v1,[[T1]],0x1 +; MIPS32: slt [[T2]],[[T2]],[[T6:.*]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: slt [[T3]],[[T3]],[[T7:.*]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <4 x i1> @test_icmp_v4i32_slt(<4 x i32> %a, <4 x i32> %b) { @@ -154,14 +158,18 @@ ; CHECK: pcmpgtd ; MIPS32-LABEL: test_icmp_v4i32_slt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: slt [[R_E0:.*]],a0,[[B_E0]] -; MIPS32: slt [[R_E1:.*]],a1,[[B_E1]] -; MIPS32: slt [[R_E2:.*]],a2,[[B_E2]] -; MIPS32: slt [[R_E3:.*]],a3,[[B_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: slt [[T4:.*]],a0,[[T0]] +; MIPS32: slt [[T5:.*]],a1,[[T1]] +; MIPS32: slt [[T6:.*]],a2,[[T2]] +; MIPS32: slt [[T7:.*]],a3,[[T3]] +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i32_uge(<4 x i32> %a, <4 x i32> %b) { @@ -174,18 +182,22 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v4i32_uge -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: sltu [[R_E0:.*]],a0,[[B_E0]] -; MIPS32: xori [[R_E0]],[[R_E0]],0x1 -; MIPS32: sltu [[R_E1:.*]],a1,[[B_E1]] -; MIPS32: xori [[R_E1]],[[R_E1]],0x1 -; MIPS32: sltu [[R_E2:.*]],a2,[[B_E2]] -; MIPS32: xori [[R_E2]],[[R_E2]],0x1 -; MIPS32: sltu [[R_E3:.*]],a3,[[B_E3]] -; MIPS32: xori [[R_E3]],[[R_E3]],0x1 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: sltu [[T4:.*]],a0,[[T0]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: sltu [[T5:.*]],a1,[[T1]] +; MIPS32: xori [[T5]],[[T5]],0x1 +; MIPS32: sltu [[T6:.*]],a2,[[T2]] +; MIPS32: xori [[T6]],[[T6]],0x1 +; MIPS32: sltu [[T7:.*]],a3,[[T3]] +; MIPS32: xori [[T7]],[[T7]],0x1 +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i32_ugt(<4 x i32> %a, <4 x i32> %b) { @@ -197,14 +209,16 @@ ; CHECK: pcmpgtd ; MIPS32-LABEL: test_icmp_v4i32_ugt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: sltu [[R_E0:.*]],[[B_E0]],a0 -; MIPS32: sltu [[R_E1:.*]],[[B_E1]],a1 -; MIPS32: sltu [[R_E2:.*]],[[B_E2]],a2 -; MIPS32: sltu [[R_E3:.*]],[[B_E3]],a3 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: sltu v0,[[T0]],[[T4:.*]] +; MIPS32: sltu v1,[[T1]],[[T5:.*]] +; MIPS32: sltu [[T2]],[[T2]],[[T6:.*]] +; MIPS32: sltu [[T3]],[[T3]],[[T7:.*]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <4 x i1> @test_icmp_v4i32_ule(<4 x i32> %a, <4 x i32> %b) { @@ -217,18 +231,20 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v4i32_ule -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: sltu [[R_E0:.*]],[[B_E0]],a0 -; MIPS32: xori [[R_E0]],[[R_E0]],0x1 -; MIPS32: sltu [[R_E1:.*]],[[B_E1]],a1 -; MIPS32: xori [[R_E1]],[[R_E1]],0x1 -; MIPS32: sltu [[R_E2:.*]],[[B_E2]],a2 -; MIPS32: xori [[R_E2]],[[R_E2]],0x1 -; MIPS32: sltu [[R_E3:.*]],[[B_E3]],a3 -; MIPS32: xori [[R_E3]],[[R_E3]],0x1 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: sltu [[T0]],[[T0]],[[T4:.*]] +; MIPS32: xori v0,[[T0]],0x1 +; MIPS32: sltu [[T1]],[[T1]],[[T5:.*]] +; MIPS32: xori v1,[[T1]],0x1 +; MIPS32: sltu [[T2]],[[T2]],[[T6:.*]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: sltu [[T3]],[[T3]],[[T7:.*]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <4 x i1> @test_icmp_v4i32_ult(<4 x i32> %a, <4 x i32> %b) { @@ -240,14 +256,18 @@ ; CHECK: pcmpgtd ; MIPS32-LABEL: test_icmp_v4i32_ult -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: sltu [[R_E0:.*]],a0,[[B_E0]] -; MIPS32: sltu [[R_E1:.*]],a1,[[B_E1]] -; MIPS32: sltu [[R_E2:.*]],a2,[[B_E2]] -; MIPS32: sltu [[R_E3:.*]],a3,[[B_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: sltu [[T4:.*]],a0,[[T0]] +; MIPS32: sltu [[T5:.*]],a1,[[T1]] +; MIPS32: sltu [[T6:.*]],a2,[[T2]] +; MIPS32: sltu [[T7:.*]],a3,[[T3]] +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i1_eq(<4 x i1> %a, <4 x i1> %b) { @@ -258,38 +278,38 @@ ; CHECK: pcmpeqd ; MIPS32-LABEL: test_icmp_v4i1_eq -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[R_E0:.*]],a0,0x1 -; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: xor [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: sltiu [[R_E0]],[[R_E0]],1 -; MIPS32: andi [[R_E1:.*]],a1,0x1 -; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: xor [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: sltiu [[R_E1]],[[R_E1]],1 -; MIPS32: andi [[R_E2:.*]],a2,0x1 -; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: xor [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: sltiu [[R_E2]],[[R_E2]],1 -; MIPS32: andi [[R_E3:.*]],a3,0x1 -; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: xor [[R_E3]],[[R_E3]],[[T_E3]] -; MIPS32: sltiu [[R_E3]],[[R_E3]],1 -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: xor [[T4]],[[T4]],[[T0]] +; MIPS32: sltiu [[T4]],[[T4]],1 +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T5]],[[T5]],[[T1]] +; MIPS32: sltiu [[T5]],[[T5]],1 +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: xor [[T6]],[[T6]],[[T2]] +; MIPS32: sltiu [[T6]],[[T6]],1 +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: xor [[T7]],[[T7]],[[T3]] +; MIPS32: sltiu [[T7]],[[T7]],1 +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i1_ne(<4 x i1> %a, <4 x i1> %b) { @@ -301,38 +321,38 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v4i1_ne -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[R_E0:.*]],a0,0x1 -; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: xor [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: sltu [[R_E0]],zero,[[R_E0]] -; MIPS32: andi [[R_E1:.*]],a1,0x1 -; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: xor [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: sltu [[R_E1]],zero,[[R_E1]] -; MIPS32: andi [[R_E2:.*]],a2,0x1 -; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: xor [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: sltu [[R_E2]],zero,[[R_E2]] -; MIPS32: andi [[R_E3:.*]],a3,0x1 -; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: xor [[R_E3]],[[R_E3]],[[T_E3]] -; MIPS32: sltu [[R_E3]],zero,[[R_E3]] -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: xor [[T4]],[[T4]],[[T0]] +; MIPS32: sltu [[T4]],zero,[[T4]] +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T5]],[[T5]],[[T1]] +; MIPS32: sltu [[T5]],zero,[[T5]] +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: xor [[T6]],[[T6]],[[T2]] +; MIPS32: sltu [[T6]],zero,[[T6]] +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: xor [[T7]],[[T7]],[[T3]] +; MIPS32: sltu [[T7]],zero,[[T7]] +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i1_sgt(<4 x i1> %a, <4 x i1> %b) { @@ -343,30 +363,32 @@ ; CHECK: pcmpgtd ; MIPS32-LABEL: test_icmp_v4i1_sgt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[T_E0:.*]],a0,0x1 -; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: andi [[T_E1:.*]],a1,0x1 -; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: andi [[T_E2:.*]],a2,0x1 -; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: andi [[T_E3:.*]],a3,0x1 -; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: slt v0,[[T0]],[[T4]] +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt v1,[[T1]],[[T5]] +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T2]],[[T2]],[[T6]] +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: slt [[T3]],[[T3]],[[T7]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <4 x i1> @test_icmp_v4i1_sle(<4 x i1> %a, <4 x i1> %b) { @@ -378,34 +400,36 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v4i1_sle -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[T_E0:.*]],a0,0x1 -; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: xori [[R_E0]],[[R_E0]],0x1 -; MIPS32: andi [[T_E1:.*]],a1,0x1 -; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: xori [[R_E1]],[[R_E1]],0x1 -; MIPS32: andi [[T_E2:.*]],a2,0x1 -; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: xori [[R_E2]],[[R_E2]],0x1 -; MIPS32: andi [[T_E3:.*]],a3,0x1 -; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]] -; MIPS32: xori [[R_E3]],[[R_E3]],0x1 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T4]] +; MIPS32: xori v0,[[T0]],0x1 +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt [[T1]],[[T1]],[[T5]] +; MIPS32: xori v1,[[T1]],0x1 +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T2]],[[T2]],[[T6]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: slt [[T3]],[[T3]],[[T7]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <4 x i1> @test_icmp_v4i1_slt(<4 x i1> %a, <4 x i1> %b) { @@ -416,34 +440,34 @@ ; CHECK: pcmpgtd ; MIPS32-LABEL: test_icmp_v4i1_slt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[R_E0:.*]],a0,0x1 -; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: slt [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: andi [[R_E1:.*]],a1,0x1 -; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: slt [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: andi [[R_E2:.*]],a2,0x1 -; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: slt [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: andi [[R_E3:.*]],a3,0x1 -; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: slt [[R_E3]],[[R_E3]],[[T_E3]] -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: slt [[T4]],[[T4]],[[T0]] +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt [[T5]],[[T5]],[[T1]] +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T6]],[[T6]],[[T2]] +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: slt [[T7]],[[T7]],[[T3]] +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i1_uge(<4 x i1> %a, <4 x i1> %b) { @@ -456,38 +480,38 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v4i1_uge -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[R_E0:.*]],a0,0x1 -; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: xori [[R_E0]],[[R_E0]],0x1 -; MIPS32: andi [[R_E1:.*]],a1,0x1 -; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: xori [[R_E1]],[[R_E1]],0x1 -; MIPS32: andi [[R_E2:.*]],a2,0x1 -; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: xori [[R_E2]],[[R_E2]],0x1 -; MIPS32: andi [[R_E3:.*]],a3,0x1 -; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]] -; MIPS32: xori [[R_E3]],[[R_E3]],0x1 -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T0]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T5]],[[T5]],[[T1]] +; MIPS32: xori [[T5]],[[T5]],0x1 +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T6]],[[T6]],[[T2]] +; MIPS32: xori [[T6]],[[T6]],0x1 +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T7]],[[T7]],[[T3]] +; MIPS32: xori [[T7]],[[T7]],0x1 +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <4 x i1> @test_icmp_v4i1_ugt(<4 x i1> %a, <4 x i1> %b) { @@ -499,30 +523,32 @@ ; CHECK: pcmpgtd ; MIPS32-LABEL: test_icmp_v4i1_ugt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[T_E0:.*]],a0,0x1 -; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: andi [[T_E1:.*]],a1,0x1 -; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: andi [[T_E2:.*]],a2,0x1 -; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: andi [[T_E3:.*]],a3,0x1 -; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu v0,[[T0]],[[T4]] +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu v1,[[T1]],[[T5]] +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T2]],[[T2]],[[T6]] +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T3]],[[T3]],[[T7]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <4 x i1> @test_icmp_v4i1_ule(<4 x i1> %a, <4 x i1> %b) { @@ -535,34 +561,36 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v4i1_ule -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[T_E0:.*]],a0,0x1 -; MIPS32: andi [[R_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: xori [[R_E0]],[[R_E0]],0x1 -; MIPS32: andi [[T_E1:.*]],a1,0x1 -; MIPS32: andi [[R_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: xori [[R_E1]],[[R_E1]],0x1 -; MIPS32: andi [[T_E2:.*]],a2,0x1 -; MIPS32: andi [[R_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: xori [[R_E2]],[[R_E2]],0x1 -; MIPS32: andi [[T_E3:.*]],a3,0x1 -; MIPS32: andi [[R_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]] -; MIPS32: xori [[R_E3]],[[R_E3]],0x1 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: xori v0,[[T0]],0x1 +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T1]],[[T1]],[[T5]] +; MIPS32: xori v1,[[T1]],0x1 +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T2]],[[T2]],[[T6]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T3]],[[T3]],[[T7]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <4 x i1> @test_icmp_v4i1_ult(<4 x i1> %a, <4 x i1> %b) { @@ -574,34 +602,34 @@ ; CHECK: pcmpgtd ; MIPS32-LABEL: test_icmp_v4i1_ult -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: andi [[R_E0:.*]],a0,0x1 -; MIPS32: andi [[T_E0:.*]],[[B_E0]],0x1 -; MIPS32: sll [[R_E0]],[[R_E0]],0x1f -; MIPS32: sll [[T_E0]],[[T_E0]],0x1f -; MIPS32: sltu [[R_E0]],[[R_E0]],[[T_E0]] -; MIPS32: andi [[R_E1:.*]],a1,0x1 -; MIPS32: andi [[T_E1:.*]],[[B_E1]],0x1 -; MIPS32: sll [[R_E1]],[[R_E1]],0x1f -; MIPS32: sll [[T_E1]],[[T_E1]],0x1f -; MIPS32: sltu [[R_E1]],[[R_E1]],[[T_E1]] -; MIPS32: andi [[R_E2:.*]],a2,0x1 -; MIPS32: andi [[T_E2:.*]],[[B_E2]],0x1 -; MIPS32: sll [[R_E2]],[[R_E2]],0x1f -; MIPS32: sll [[T_E2]],[[T_E2]],0x1f -; MIPS32: sltu [[R_E2]],[[R_E2]],[[T_E2]] -; MIPS32: andi [[R_E3:.*]],a3,0x1 -; MIPS32: andi [[T_E3:.*]],[[B_E3]],0x1 -; MIPS32: sll [[R_E3]],[[R_E3]],0x1f -; MIPS32: sll [[T_E3]],[[T_E3]],0x1f -; MIPS32: sltu [[R_E3]],[[R_E3]],[[T_E3]] -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: andi [[T4:.*]],a0,0x1 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T0]] +; MIPS32: andi [[T5:.*]],a1,0x1 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T5]],[[T5]],[[T1]] +; MIPS32: andi [[T6:.*]],a2,0x1 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T6]],[[T6]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T6]],[[T6]],[[T2]] +; MIPS32: andi [[T7:.*]],a3,0x1 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T7]],[[T7]],[[T3]] +; MIPS32: move v0,[[T4]] +; MIPS32: move v1,[[T5]] +; MIPS32: move a0,[[T6]] +; MIPS32: move a1,[[T7]] } define internal <8 x i1> @test_icmp_v8i16_eq(<8 x i16> %a, <8 x i16> %b) { @@ -612,107 +640,106 @@ ; CHECK: pcmpeqw ; MIPS32-LABEL: test_icmp_v8i16_eq -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; *** icmp a[0] and b[0] *** -; MIPS32: andi [[T2:.*]],a0,0xffff -; MIPS32: andi [[T3:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: xor [[T2]],[[T2]],[[T3]] -; MIPS32: sltiu [[T2]],[[T2]],1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T4:.*]],[[T1_E0]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltiu [[T8]],[[T8]],1 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T4]] -; *** icmp a[1] and b[1] *** -; MIPS32: srl [[R_E0:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 -; MIPS32: sll [[R_E0]],[[R_E0]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: xor [[R_E0]],[[R_E0]],[[T5]] -; MIPS32: sltiu [[R_E0]],[[R_E0]],1 -; MIPS32: sll [[R_E0]],[[R_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E0]],[[R_E0]],[[T2]] -; *** icmp a[2] and b[2] *** -; MIPS32: andi [[T2:.*]],a1,0xffff -; MIPS32: andi [[T3:.*]],[[B_E1]],0xffff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: xor [[T2]],[[T2]],[[T3]] -; MIPS32: sltiu [[T2]],[[T2]],1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T4:.*]],[[T1_E1]],0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: xor [[T10]],[[T10]],[[T0]] +; MIPS32: sltiu [[T10]],[[T10]],1 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T4]] -; *** icmp a[3] and b[3] *** -; MIPS32: srl [[R_E1:.*]],a1,0x10 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 -; MIPS32: sll [[R_E1]],[[R_E1]],0x10 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 ; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: xor [[R_E1]],[[R_E1]],[[T5]] -; MIPS32: sltiu [[R_E1]],[[R_E1]],1 -; MIPS32: sll [[R_E1]],[[R_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E1]],[[R_E1]],[[T2]] -; *** icmp a[4] and b[4] *** -; MIPS32: andi [[T2:.*]],a2,0xffff -; MIPS32: andi [[T3:.*]],[[B_E2]],0xffff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: xor [[T2]],[[T2]],[[T3]] -; MIPS32: sltiu [[T2]],[[T2]],1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T4:.*]],[[T1_E2]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T4]] -; *** icmp a[5] and b[5] *** -; MIPS32: srl [[R_E2:.*]],a2,0x10 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: sll [[R_E2]],[[R_E2]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: xor [[R_E2]],[[R_E2]],[[T5]] -; MIPS32: sltiu [[R_E2]],[[R_E2]],1 -; MIPS32: sll [[R_E2]],[[R_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E2]],[[R_E2]],[[T2]] -; *** icmp a[6] and b[6] *** -; MIPS32: andi [[T2:.*]],a3,0xffff -; MIPS32: andi [[T3:.*]],[[B_E3]],0xffff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: xor [[T2]],[[T2]],[[T3]] -; MIPS32: sltiu [[T2]],[[T2]],1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T5:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; *** icmp a[7] and b[7] *** -; MIPS32: srl [[R_E3:.*]],a3,0x10 -; MIPS32: srl [[T6:.*]],[[B_E3]],0x10 -; MIPS32: sll [[R_E3]],[[R_E3]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: xor [[T11]],[[T11]],[[T1]] +; MIPS32: sltiu [[T11]],[[T11]],1 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 ; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: xor [[R_E3]],[[R_E3]],[[T6]] -; MIPS32: sltiu [[R_E3]],[[R_E3]],1 -; MIPS32: sll [[R_E3]],[[R_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 ; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E3]],[[R_E3]],[[T2]] -; *** move result to $2:$3:$4:$5 *** -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: xor [[T12]],[[T12]],[[T2]] +; MIPS32: sltiu [[T12]],[[T12]],1 +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: xor [[T13]],[[T13]],[[T3]] +; MIPS32: sltiu [[T13]],[[T13]],1 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i16_ne(<8 x i16> %a, <8 x i16> %b) { @@ -724,107 +751,106 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v8i16_ne -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; *** icmp a[0] and b[0] *** -; MIPS32: andi [[T2:.*]],a0,0xffff -; MIPS32: andi [[T3:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: xor [[T2]],[[T2]],[[T3]] -; MIPS32: sltu [[T2]],zero,[[T2]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T4:.*]],[[T1_E0]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltu [[T8]],zero,[[T8]] +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T4]] -; *** icmp a[1] and b[1] *** -; MIPS32: srl [[R_E0:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 -; MIPS32: sll [[R_E0]],[[R_E0]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: xor [[R_E0]],[[R_E0]],[[T5]] -; MIPS32: sltu [[R_E0]],zero,[[R_E0]] -; MIPS32: sll [[R_E0]],[[R_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E0]],[[R_E0]],[[T2]] -; *** icmp a[2] and b[2] *** -; MIPS32: andi [[T2:.*]],a1,0xffff -; MIPS32: andi [[T3:.*]],[[B_E1]],0xffff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: xor [[T2]],[[T2]],[[T3]] -; MIPS32: sltu [[T2]],zero,[[T2]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T4:.*]],[[T1_E1]],0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: xor [[T10]],[[T10]],[[T0]] +; MIPS32: sltu [[T10]],zero,[[T10]] +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T4]] -; *** icmp a[3] and b[3] *** -; MIPS32: srl [[R_E1:.*]],a1,0x10 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 -; MIPS32: sll [[R_E1]],[[R_E1]],0x10 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 ; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: xor [[R_E1]],[[R_E1]],[[T5]] -; MIPS32: sltu [[R_E1]],zero,[[R_E1]] -; MIPS32: sll [[R_E1]],[[R_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E1]],[[R_E1]],[[T2]] -; *** icmp a[4] and b[4] *** -; MIPS32: andi [[T2:.*]],a2,0xffff -; MIPS32: andi [[T3:.*]],[[B_E2]],0xffff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: xor [[T2]],[[T2]],[[T3]] -; MIPS32: sltu [[T2]],zero,[[T2]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T4:.*]],[[T1_E2]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T4]] -; *** icmp a[5] and b[5] *** -; MIPS32: srl [[R_E2:.*]],a2,0x10 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: sll [[R_E2]],[[R_E2]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: xor [[R_E2]],[[R_E2]],[[T5]] -; MIPS32: sltu [[R_E2]],zero,[[R_E2]] -; MIPS32: sll [[R_E2]],[[R_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E2]],[[R_E2]],[[T2]] -; *** icmp a[6] and b[6] *** -; MIPS32: andi [[T2:.*]],a3,0xffff -; MIPS32: andi [[T3:.*]],[[B_E3]],0xffff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: xor [[T2]],[[T2]],[[T3]] -; MIPS32: sltu [[T2]],zero,[[T2]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T5:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; *** icmp a[7] and b[7] *** -; MIPS32: srl [[R_E3:.*]],a3,0x10 -; MIPS32: srl [[T6:.*]],[[B_E3]],0x10 -; MIPS32: sll [[R_E3]],[[R_E3]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: xor [[T11]],[[T11]],[[T1]] +; MIPS32: sltu [[T11]],zero,[[T11]] +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 ; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: xor [[R_E3]],[[R_E3]],[[T6]] -; MIPS32: sltu [[R_E3]],zero,[[R_E3]] -; MIPS32: sll [[R_E3]],[[R_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 ; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E3]],[[R_E3]],[[T2]] -; *** move result to $2:$3:$4:$5 *** -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: xor [[T12]],[[T12]],[[T2]] +; MIPS32: sltu [[T12]],zero,[[T12]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: xor [[T13]],[[T13]],[[T3]] +; MIPS32: sltu [[T13]],zero,[[T13]] +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i16_sgt(<8 x i16> %a, <8 x i16> %b) { @@ -835,86 +861,96 @@ ; CHECK: pcmpgtw ; MIPS32-LABEL: test_icmp_v8i16_sgt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: slt [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: slt [[T5]],[[T5]],[[T4]] -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]] -; MIPS32: andi [[T4]],a1,0xffff -; MIPS32: andi [[T3]],[[B_E1]],0xffff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: slt [[T3]],[[T3]],[[T4]] -; MIPS32: andi [[T3]],[[T3]],0xffff -; MIPS32: srl [[T6:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: or [[T3]],[[T3]],[[T6]] -; MIPS32: srl [[T7:.*]],a1,0x10 -; MIPS32: srl [[T8:.*]],[[B_E1]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff ; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: slt [[T8]],[[T8]],[[T7]] -; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: srl [[T3]],[[T3]],0x10 -; MIPS32: or [[R_E1:.*]],[[T8]],[[T3]] -; MIPS32: andi [[T4]],a2,0xffff -; MIPS32: andi [[T7]],[[B_E2]],0xffff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 -; MIPS32: slt [[T7]],[[T7]],[[T4]] -; MIPS32: andi [[T7]],[[T7]],0xffff -; MIPS32: srl [[T9:.*]],[[T1_E2]],0x10 ; MIPS32: sll [[T9]],[[T9]],0x10 -; MIPS32: or [[T7]],[[T7]],[[T9]] -; MIPS32: srl [[T10:.*]],a2,0x10 -; MIPS32: srl [[T11:.*]],[[B_E2]],0x10 +; MIPS32: slt [[T9]],[[T9]],[[T8]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T10]] +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: slt [[T1]],[[T1]],[[T11]] +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xffff ; MIPS32: sll [[T10]],[[T10]],0x10 ; MIPS32: sll [[T11]],[[T11]],0x10 ; MIPS32: slt [[T11]],[[T11]],[[T10]] -; MIPS32: sll [[T11]],[[T11]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 -; MIPS32: srl [[T7]],[[T7]],0x10 -; MIPS32: or [[R_E2:.*]],[[T11]],[[T7]] -; MIPS32: andi [[T4]],a3,0xffff -; MIPS32: andi [[T7]],[[B_E3]],0xffff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 -; MIPS32: slt [[T7]],[[T7]],[[T4]] -; MIPS32: andi [[T7]],[[T7]],0xffff -; MIPS32: srl [[T12:.*]],[[T1_E3]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: srl [[T2]],[[T2]],0x10 ; MIPS32: sll [[T12]],[[T12]],0x10 -; MIPS32: or [[T7]],[[T7]],[[T12]] -; MIPS32: srl [[T13:.*]],a3,0x10 -; MIPS32: srl [[T14:.*]],[[B_E3]],0x10 -; MIPS32: sll [[T13]],[[T13]],0x10 -; MIPS32: sll [[T14]],[[T14]],0x10 -; MIPS32: slt [[T14]],[[T14]],[[T13]] -; MIPS32: sll [[T14]],[[T14]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: slt [[T2]],[[T2]],[[T12]] +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xffff ; MIPS32: srl [[T7]],[[T7]],0x10 -; MIPS32: or [[R_E3:.*]],[[T14]],[[T7]] +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: slt [[T3]],[[T3]],[[T13]] +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <8 x i1> @test_icmp_v8i16_sle(<8 x i16> %a, <8 x i16> %b) { @@ -926,94 +962,104 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v8i16_sle -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: slt [[T2]],[[T2]],[[T1]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: slt [[T5]],[[T5]],[[T4]] -; MIPS32: xori [[T5]],[[T5]],0x1 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]] -; MIPS32: andi [[T4]],a1,0xffff -; MIPS32: andi [[T3]],[[B_E1]],0xffff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: slt [[T3]],[[T3]],[[T4]] -; MIPS32: xori [[T3]],[[T3]],0x1 -; MIPS32: andi [[T3]],[[T3]],0xffff -; MIPS32: srl [[T6:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: or [[T3]],[[T3]],[[T6]] -; MIPS32: srl [[T7:.*]],a1,0x10 -; MIPS32: srl [[T8:.*]],[[B_E1]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff ; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: slt [[T8]],[[T8]],[[T7]] -; MIPS32: xori [[T8]],[[T8]],0x1 -; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: srl [[T3]],[[T3]],0x10 -; MIPS32: or [[R_E1:.*]],[[T8]],[[T3]] -; MIPS32: andi [[T4]],a2,0xffff -; MIPS32: andi [[T7]],[[B_E2]],0xffff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 -; MIPS32: slt [[T7]],[[T7]],[[T4]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: andi [[T7]],[[T7]],0xffff -; MIPS32: srl [[T9:.*]],[[T1_E2]],0x10 ; MIPS32: sll [[T9]],[[T9]],0x10 -; MIPS32: or [[T7]],[[T7]],[[T9]] -; MIPS32: srl [[T10:.*]],a2,0x10 -; MIPS32: srl [[T11:.*]],[[B_E2]],0x10 +; MIPS32: slt [[T9]],[[T9]],[[T8]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T10]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: slt [[T1]],[[T1]],[[T11]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xffff ; MIPS32: sll [[T10]],[[T10]],0x10 ; MIPS32: sll [[T11]],[[T11]],0x10 ; MIPS32: slt [[T11]],[[T11]],[[T10]] ; MIPS32: xori [[T11]],[[T11]],0x1 -; MIPS32: sll [[T11]],[[T11]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 -; MIPS32: srl [[T7]],[[T7]],0x10 -; MIPS32: or [[R_E2:.*]],[[T11]],[[T7]] -; MIPS32: andi [[T4]],a3,0xffff -; MIPS32: andi [[T7]],[[B_E3]],0xffff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 -; MIPS32: slt [[T7]],[[T7]],[[T4]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: andi [[T7]],[[T7]],0xffff -; MIPS32: srl [[T12:.*]],[[T1_E3]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: srl [[T2]],[[T2]],0x10 ; MIPS32: sll [[T12]],[[T12]],0x10 -; MIPS32: or [[T7]],[[T7]],[[T12]] -; MIPS32: srl [[T13:.*]],a3,0x10 -; MIPS32: srl [[T14:.*]],[[B_E3]],0x10 -; MIPS32: sll [[T13]],[[T13]],0x10 -; MIPS32: sll [[T14]],[[T14]],0x10 -; MIPS32: slt [[T14]],[[T14]],[[T13]] -; MIPS32: xori [[T14]],[[T14]],0x1 -; MIPS32: sll [[T14]],[[T14]],0x10 -; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: slt [[T2]],[[T2]],[[T12]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xffff ; MIPS32: srl [[T7]],[[T7]],0x10 -; MIPS32: or [[R_E3:.*]],[[T14]],[[T7]] +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: slt [[T3]],[[T3]],[[T13]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <8 x i1> @test_icmp_v8i16_slt(<8 x i16> %a, <8 x i16> %b) { @@ -1024,86 +1070,98 @@ ; CHECK: pcmpgtw ; MIPS32-LABEL: test_icmp_v8i16_slt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: slt [[T1]],[[T1]],[[T2]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: slt [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: slt [[T10]],[[T10]],[[T0]] +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 ; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: slt [[T4]],[[T4]],[[T5]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a1,0xffff -; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff +; MIPS32: sll [[T11]],[[T11]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: slt [[T1]],[[T1]],[[T2]] +; MIPS32: slt [[T11]],[[T11]],[[T1]] +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T2]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a1,0x10 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: slt [[T4]],[[T4]],[[T5]] -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a2,0xffff -; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: sll [[T12]],[[T12]],0x10 ; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: slt [[T1]],[[T1]],[[T2]] +; MIPS32: slt [[T12]],[[T12]],[[T2]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T3]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 ; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a2,0x10 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: slt [[T4]],[[T4]],[[T5]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a3,0xffff -; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: slt [[T1]],[[T1]],[[T2]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a3,0x10 -; MIPS32: srl [[T5:.*]],[[B_E3]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: slt [[T4]],[[T4]],[[T5]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]] +; MIPS32: slt [[T13]],[[T13]],[[T3]] +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i16_uge(<8 x i16> %a, <8 x i16> %b) { @@ -1116,98 +1174,106 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v8i16_uge -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sltu [[T10]],[[T10]],[[T0]] +; MIPS32: xori [[T10]],[[T10]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 ; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T4]],[[T4]],[[T5]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a1,0xffff -; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff +; MIPS32: sll [[T11]],[[T11]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: sltu [[T11]],[[T11]],[[T1]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T2]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a1,0x10 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T4]],[[T4]],[[T5]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a2,0xffff -; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: sll [[T12]],[[T12]],0x10 ; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: sltu [[T12]],[[T12]],[[T2]] +; MIPS32: xori [[T12]],[[T12]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T3]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 ; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a2,0x10 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T4]],[[T4]],[[T5]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a3,0xffff -; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a3,0x10 -; MIPS32: srl [[T5:.*]],[[B_E3]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T4]],[[T4]],[[T5]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]] -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: sltu [[T13]],[[T13]],[[T3]] +; MIPS32: xori [[T13]],[[T13]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i16_ugt(<8 x i16> %a, <8 x i16> %b) { @@ -1219,87 +1285,96 @@ ; CHECK: pcmpgtw ; MIPS32-LABEL: test_icmp_v8i16_ugt -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: sltu [[T9]],[[T9]],[[T8]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T5]],[[T5]],[[T4]] -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]] -; MIPS32: andi [[T1:.*]],a1,0xffff -; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a1,0x10 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T10]] +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 ; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T5]],[[T5]],[[T4]] -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E1:.*]],[[T5]],[[T2]] -; MIPS32: andi [[T1:.*]],a2,0xffff -; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a2,0x10 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T5]],[[T5]],[[T4]] -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E2:.*]],[[T5]],[[T2]] -; MIPS32: andi [[T1:.*]],a3,0xffff -; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff +; MIPS32: sltu [[T1]],[[T1]],[[T11]] ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a3,0x10 -; MIPS32: srl [[T5:.*]],[[B_E3]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T5]],[[T5]],[[T4]] -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 ; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E3:.*]],[[T5]],[[T2]] - +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sltu [[T2]],[[T2]],[[T12]] +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sltu [[T3]],[[T3]],[[T13]] +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <8 x i1> @test_icmp_v8i16_ule(<8 x i16> %a, <8 x i16> %b) { @@ -1312,94 +1387,104 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v8i16_ule -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: sltu [[T9]],[[T9]],[[T8]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T5]],[[T5]],[[T4]] -; MIPS32: xori [[T5]],[[T5]],0x1 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E0:.*]],[[T5]],[[T2]] -; MIPS32: andi [[T1:.*]],a1,0xffff -; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a1,0x10 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T10]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 ; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T5]],[[T5]],[[T4]] -; MIPS32: xori [[T5]],[[T5]],0x1 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E1:.*]],[[T5]],[[T2]] -; MIPS32: andi [[T1:.*]],a2,0xffff -; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a2,0x10 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T5]],[[T5]],[[T4]] -; MIPS32: xori [[T5]],[[T5]],0x1 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E2:.*]],[[T5]],[[T2]] -; MIPS32: andi [[T1:.*]],a3,0xffff -; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff +; MIPS32: sltu [[T1]],[[T1]],[[T11]] +; MIPS32: xori [[T1]],[[T1]],0x1 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T2]],[[T2]],[[T3]] -; MIPS32: srl [[T4:.*]],a3,0x10 -; MIPS32: srl [[T5:.*]],[[B_E3]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T5]],[[T5]],[[T4]] -; MIPS32: xori [[T5]],[[T5]],0x1 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 ; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: or [[R_E3:.*]],[[T5]],[[T2]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sltu [[T2]],[[T2]],[[T12]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sltu [[T3]],[[T3]],[[T13]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <8 x i1> @test_icmp_v8i16_ult(<8 x i16> %a, <8 x i16> %b) { @@ -1411,90 +1496,98 @@ ; CHECK: pcmpgtw ; MIPS32-LABEL: test_icmp_v8i16_ult -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sltu [[T10]],[[T10]],[[T0]] +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 ; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T4]],[[T4]],[[T5]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a1,0xffff -; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff +; MIPS32: sll [[T11]],[[T11]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] +; MIPS32: sltu [[T11]],[[T11]],[[T1]] +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T2]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a1,0x10 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T4]],[[T4]],[[T5]] -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a2,0xffff -; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: sll [[T12]],[[T12]],0x10 ; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] +; MIPS32: sltu [[T12]],[[T12]],[[T2]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: move [[T1]],[[T3]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: sll [[T13]],[[T13]],0x10 ; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a2,0x10 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T4]],[[T4]],[[T5]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a3,0xffff -; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a3,0x10 -; MIPS32: srl [[T5:.*]],[[B_E3]],0x10 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sltu [[T4]],[[T4]],[[T5]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]] -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: sltu [[T13]],[[T13]],[[T3]] +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i1_eq(<8 x i1> %a, <8 x i1> %b) { @@ -1505,114 +1598,122 @@ ; CHECK: pcmpeqw ; MIPS32-LABEL: test_icmp_v8i1_eq -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T1]],[[T1]],[[T2]] -; MIPS32: sltiu [[T1]],[[T1]],1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T5]] -; MIPS32: sltiu [[T4]],[[T4]],1 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltiu [[T8]],[[T8]],1 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a1,0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T1]],[[T1]],[[T2]] -; MIPS32: sltiu [[T1]],[[T1]],1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a1,0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: xor [[T10]],[[T10]],[[T0]] +; MIPS32: sltiu [[T10]],[[T10]],1 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T5]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a2,0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff -; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T1]],[[T1]],[[T2]] -; MIPS32: sltiu [[T1]],[[T1]],1 +; MIPS32: xor [[T11]],[[T11]],[[T1]] +; MIPS32: sltiu [[T11]],[[T11]],1 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T5]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a3,0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff -; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f ; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T1]],[[T1]],[[T2]] -; MIPS32: sltiu [[T1]],[[T1]],1 +; MIPS32: xor [[T12]],[[T12]],[[T2]] +; MIPS32: sltiu [[T12]],[[T12]],1 +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T3]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5:.*]],[[B_E3]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T5]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]] -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: xor [[T13]],[[T13]],[[T3]] +; MIPS32: sltiu [[T13]],[[T13]],1 +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i1_ne(<8 x i1> %a, <8 x i1> %b) { @@ -1624,114 +1725,122 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v8i1_ne -; MIPS32: lw [[B_E0:.*]], -; MIPS32: lw [[B_E1:.*]], -; MIPS32: lw [[B_E2:.*]], -; MIPS32: lw [[B_E3:.*]], -; MIPS32: move [[T1_E0:.*]],zero -; MIPS32: move [[T1_E1:.*]],zero -; MIPS32: move [[T1_E2:.*]],zero -; MIPS32: move [[T1_E3:.*]],zero -; MIPS32: andi [[T1:.*]],a0,0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T2:.*]],[[B_E0]],0xffff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T1]],[[T1]],[[T2]] -; MIPS32: sltu [[T1]],zero,[[T1]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E0]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a0,0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5:.*]],[[B_E0]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T5]] -; MIPS32: sltu [[T4]],zero,[[T4]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltu [[T8]],zero,[[T8]] +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a1,0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T2:.*]],[[B_E1]],0xffff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T1]],[[T1]],[[T2]] -; MIPS32: sltu [[T1]],zero,[[T1]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E1]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a1,0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: xor [[T10]],[[T10]],[[T0]] +; MIPS32: sltu [[T10]],zero,[[T10]] +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5:.*]],[[B_E1]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T5]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a2,0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T2:.*]],[[B_E2]],0xffff -; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T1]],[[T1]],[[T2]] -; MIPS32: sltu [[T1]],zero,[[T1]] +; MIPS32: xor [[T11]],[[T11]],[[T1]] +; MIPS32: sltu [[T11]],zero,[[T11]] +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E2]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5:.*]],[[B_E2]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T5]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T1:.*]],a3,0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T2:.*]],[[B_E3]],0xffff -; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f ; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T1]],[[T1]],[[T2]] -; MIPS32: sltu [[T1]],zero,[[T1]] +; MIPS32: xor [[T12]],[[T12]],[[T2]] +; MIPS32: sltu [[T12]],zero,[[T12]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T3]] ; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T3:.*]],[[T1_E3]],0x10 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T3]] -; MIPS32: srl [[T4:.*]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5:.*]],[[B_E3]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T5]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[R_E3:.*]],[[T4]],[[T1]] -; MIPS32: move v0,[[R_E0]] -; MIPS32: move v1,[[R_E1]] -; MIPS32: move a0,[[R_E2]] -; MIPS32: move a1,[[R_E3]] +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: xor [[T13]],[[T13]],[[T3]] +; MIPS32: sltu [[T13]],zero,[[T13]] +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i1_sgt(<8 x i1> %a, <8 x i1> %b) { @@ -1742,102 +1851,112 @@ ; CHECK: pcmpgtw ; MIPS32-LABEL: test_icmp_v8i1_sgt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T9]],[[T9]],[[T8]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a1,0xffff +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T10]] +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: slt [[T1]],[[T1]],[[T11]] ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T2]],[[T2]],[[T12]] +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: slt [[T3]],[[T3]],[[T13]] +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <8 x i1> @test_icmp_v8i1_sle(<8 x i1> %a, <8 x i1> %b) { @@ -1849,110 +1968,120 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v8i1_sle -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] -; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T9]],[[T9]],[[T8]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a1,0xffff +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T10]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] +; MIPS32: slt [[T4]],[[T4]],[[T10]] ; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] +; MIPS32: slt [[T1]],[[T1]],[[T11]] ; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] -; MIPS32: xori [[T4]],[[T4]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T2]],[[T2]],[[T12]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: slt [[T3]],[[T3]],[[T13]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <8 x i1> @test_icmp_v8i1_slt(<8 x i1> %a, <8 x i1> %b) { @@ -1963,102 +2092,114 @@ ; CHECK: pcmpgtw ; MIPS32-LABEL: test_icmp_v8i1_slt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xffff +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: slt [[T10]],[[T10]],[[T0]] +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T1]] +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 ; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: slt [[T0]],[[T0]],[[T1]] ; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T3]],[[T3]],[[T4]] -; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T12]],[[T12]],[[T2]] +; MIPS32: sll [[T12]],[[T12]],0x10 ; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a1,0xffff +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 ; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: slt [[T0]],[[T0]],[[T1]] ; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a1,0x10 +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 ; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f ; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T3]],[[T3]],[[T4]] -; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: slt [[T13]],[[T13]],[[T3]] +; MIPS32: sll [[T13]],[[T13]],0x10 ; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T3]],[[T3]],[[T4]] -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T3]],[[T3]],[[T4]] -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]] +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i1_uge(<8 x i1> %a, <8 x i1> %b) { @@ -2071,110 +2212,122 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v8i1_uge -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xffff +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T10]],[[T10]],[[T0]] +; MIPS32: xori [[T10]],[[T10]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T1]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 ; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sltu [[T0]],[[T0]],[[T1]] ; MIPS32: xori [[T0]],[[T0]],0x1 ; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: xori [[T3]],[[T3]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T12]],[[T12]],[[T2]] +; MIPS32: xori [[T12]],[[T12]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x10 ; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a1,0xffff +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 ; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sltu [[T0]],[[T0]],[[T1]] ; MIPS32: xori [[T0]],[[T0]],0x1 ; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a1,0x10 +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 ; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f ; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: xori [[T3]],[[T3]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sltu [[T13]],[[T13]],[[T3]] +; MIPS32: xori [[T13]],[[T13]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x10 ; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: xori [[T3]],[[T3]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: xori [[T3]],[[T3]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]] +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <8 x i1> @test_icmp_v8i1_ugt(<8 x i1> %a, <8 x i1> %b) { @@ -2186,102 +2339,112 @@ ; CHECK: pcmpgtw ; MIPS32-LABEL: test_icmp_v8i1_ugt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T9]],[[T9]],[[T8]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a1,0xffff +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T10]] +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sltu [[T1]],[[T1]],[[T11]] ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T2]],[[T2]],[[T12]] +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T3]],[[T3]],[[T13]] +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <8 x i1> @test_icmp_v8i1_ule(<8 x i1> %a, <8 x i1> %b) { @@ -2294,110 +2457,120 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v8i1_ule -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] -; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T9]],[[T9]],[[T8]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a1,0xffff +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T10]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] +; MIPS32: sltu [[T4]],[[T4]],[[T10]] ; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 ; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] +; MIPS32: sltu [[T1]],[[T1]],[[T11]] ; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x10 ; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T0:.*]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T3:.*]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] -; MIPS32: xori [[T4]],[[T4]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T2]],[[T2]],[[T12]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: sll [[T2]],[[T2]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xffff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xffff +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T3]],[[T3]],[[T13]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <8 x i1> @test_icmp_v8i1_ult(<8 x i1> %a, <8 x i1> %b) { @@ -2409,102 +2582,114 @@ ; CHECK: pcmpgtw ; MIPS32-LABEL: test_icmp_v8i1_ult -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xffff +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xffff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x10 ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xffff +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T10]],[[T10]],[[T0]] +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xffff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T1]] +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xffff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 ; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sltu [[T0]],[[T0]],[[T1]] ; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: sll [[T6]],[[T6]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: srl [[T12:.*]],a2,0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T12]],[[T12]],[[T2]] +; MIPS32: sll [[T12]],[[T12]],0x10 ; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a1,0xffff +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xffff ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E1]],0xffff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xffff ; MIPS32: andi [[T1]],[[T1]],0x1 ; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sltu [[T0]],[[T0]],[[T1]] ; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E1]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a1,0x10 +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: sll [[T7]],[[T7]],0x10 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: srl [[T13:.*]],a3,0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x10 ; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E1]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f ; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: sll [[T3]],[[T3]],0x10 +; MIPS32: sltu [[T13]],[[T13]],[[T3]] +; MIPS32: sll [[T13]],[[T13]],0x10 ; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E2]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E2]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E2]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T0:.*]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E3]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xffff -; MIPS32: srl [[T2:.*]],[[TV_E3]],0x10 -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E3]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: sll [[T3]],[[T3]],0x10 -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T3]],[[T0]] +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i8_eq(<16 x i8> %a, <16 x i8> %b) { @@ -2515,206 +2700,234 @@ ; CHECK: pcmpeqb ; MIPS32-LABEL: test_icmp_v16i8_eq -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: xor [[T0]],[[T0]],[[T1]] -; MIPS32: sltiu [[T0]],[[T0]],1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: xor [[T2]],[[T2]],[[T1]] -; MIPS32: sltiu [[T2]],[[T2]],1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: xor [[T0]],[[T0]],[[T1]] -; MIPS32: sltiu [[T0]],[[T0]],1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltiu [[T8]],[[T8]],1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: xor [[T3]],[[T3]],[[T4]] -; MIPS32: sltiu [[T3]],[[T3]],1 -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T2]] +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: xor [[T4]],[[T4]],[[T9]] ; MIPS32: sltiu [[T4]],[[T4]],1 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: xor [[T2]],[[T2]],[[T5]] -; MIPS32: sltiu [[T2]],[[T2]],1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltiu [[T8]],[[T8]],1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: xor [[T10]],[[T10]],[[T0]] +; MIPS32: sltiu [[T10]],[[T10]],1 +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T1]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 ; MIPS32: xor [[T4]],[[T4]],[[T5]] ; MIPS32: sltiu [[T4]],[[T4]],1 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T5]],[[T5]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T5]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: xor [[T6]],[[T6]],[[T7]] -; MIPS32: sltiu [[T6]],[[T6]],1 -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: xor [[T11]],[[T11]],[[T1]] +; MIPS32: sltiu [[T11]],[[T11]],1 +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T7]],[[BV_E2]],0xff +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T1]],[[T1]],0x18 ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T7]] -; MIPS32: sltiu [[T4]],[[T4]],1 +; MIPS32: xor [[T1]],[[T1]],[[T4]] +; MIPS32: sltiu [[T1]],[[T1]],1 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: xor [[T7]],[[T7]],[[T2]] -; MIPS32: sltiu [[T7]],[[T7]],1 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T2]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: xor [[T9]],[[T9]],[[T10]] -; MIPS32: sltiu [[T9]],[[T9]],1 -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T7]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: xor [[T7]],[[T7]],[[T10]] -; MIPS32: sltiu [[T7]],[[T7]],1 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T10]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 ; MIPS32: sll [[T12]],[[T12]],0x18 -; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: xor [[T12]],[[T12]],[[T13]] +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: xor [[T12]],[[T12]],[[T2]] ; MIPS32: sltiu [[T12]],[[T12]],1 ; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: xor [[T1]],[[T1]],[[T2]] +; MIPS32: sltiu [[T1]],[[T1]],1 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T2]],0xffff +; MIPS32: ori [[T2]],[[T2]],0xff +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T2]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T2]],0xff00 +; MIPS32: ori [[T2]],[[T2]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T13]],[[T13]],0x18 +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: xor [[T13]],[[T13]],[[T3]] +; MIPS32: sltiu [[T13]],[[T13]],1 +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) { @@ -2726,206 +2939,234 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v16i8_ne -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: xor [[T0]],[[T0]],[[T1]] -; MIPS32: sltu [[T0]],zero,[[T0]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: xor [[T2]],[[T2]],[[T1]] -; MIPS32: sltu [[T2]],zero,[[T2]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: xor [[T0]],[[T0]],[[T1]] -; MIPS32: sltu [[T0]],zero,[[T0]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltu [[T8]],zero,[[T8]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: xor [[T3]],[[T3]],[[T4]] -; MIPS32: sltu [[T3]],zero,[[T3]] -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T2]] +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: xor [[T4]],[[T4]],[[T9]] ; MIPS32: sltu [[T4]],zero,[[T4]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: xor [[T2]],[[T2]],[[T5]] -; MIPS32: sltu [[T2]],zero,[[T2]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltu [[T8]],zero,[[T8]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: xor [[T10]],[[T10]],[[T0]] +; MIPS32: sltu [[T10]],zero,[[T10]] +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T1]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 ; MIPS32: xor [[T4]],[[T4]],[[T5]] ; MIPS32: sltu [[T4]],zero,[[T4]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T5]],[[T5]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T5]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: xor [[T6]],[[T6]],[[T7]] -; MIPS32: sltu [[T6]],zero,[[T6]] -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: xor [[T11]],[[T11]],[[T1]] +; MIPS32: sltu [[T11]],zero,[[T11]] +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T7]],[[BV_E2]],0xff +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T1]],[[T1]],0x18 ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T7]] -; MIPS32: sltu [[T4]],zero,[[T4]] +; MIPS32: xor [[T1]],[[T1]],[[T4]] +; MIPS32: sltu [[T1]],zero,[[T1]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: xor [[T7]],[[T7]],[[T2]] -; MIPS32: sltu [[T7]],zero,[[T7]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T2]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: xor [[T9]],[[T9]],[[T10]] -; MIPS32: sltu [[T9]],zero,[[T9]] -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T7]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: xor [[T7]],[[T7]],[[T10]] -; MIPS32: sltu [[T7]],zero,[[T7]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: xor [[T4]],[[T4]],[[T10]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 ; MIPS32: sll [[T12]],[[T12]],0x18 -; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: xor [[T12]],[[T12]],[[T13]] +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: xor [[T12]],[[T12]],[[T2]] ; MIPS32: sltu [[T12]],zero,[[T12]] ; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: xor [[T1]],[[T1]],[[T2]] +; MIPS32: sltu [[T1]],zero,[[T1]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T2]],0xffff +; MIPS32: ori [[T2]],[[T2]],0xff +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: xor [[T0]],[[T0]],[[T2]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T2]],0xff00 +; MIPS32: ori [[T2]],[[T2]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T13]],[[T13]],0x18 +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: xor [[T13]],[[T13]],[[T3]] +; MIPS32: sltu [[T13]],zero,[[T13]] +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) { @@ -2936,190 +3177,216 @@ ; CHECK: pcmpgtb ; MIPS32-LABEL: test_icmp_v16i8_sgt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T0]],[[BV_E0]],0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: slt [[T0]],[[T0]],[[T2]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T1]],[[T1]],[[T2]] -; MIPS32: or [[T0]],[[T0]],[[T1]] -; MIPS32: srl [[T2]],a0,0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: slt [[T1]],[[T1]],[[T2]] -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T0]],[[T0]],[[T2]] -; MIPS32: or [[T1]],[[T1]],[[T0]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: slt [[T9]],[[T9]],[[T8]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T8]],[[T0]] +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: andi [[T8]],[[T8]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: slt [[T4]],[[T4]],[[T3]] -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x8 -; MIPS32: srl [[T1]],[[T1]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T3]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T3]],a1,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: slt [[T8]],[[T8]],[[T4]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T9]],[[T9]],[[T4]] +; MIPS32: or [[T8]],[[T8]],[[T9]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: slt [[T9]],[[T9]],[[T4]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T8]],[[T8]],[[T4]] +; MIPS32: or [[T9]],[[T9]],[[T8]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: slt [[T0]],[[T0]],[[T10]] +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x8 +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: slt [[T5]],[[T5]],[[T3]] +; MIPS32: slt [[T5]],[[T5]],[[T10]] ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T5]],[[T5]],[[T2]] -; MIPS32: srl [[T3]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T2]],[[BV_E1]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T5]],[[T5]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: slt [[T7]],[[T7]],[[T6]] -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: srl [[T2]],[[T2]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]] -; MIPS32: andi [[T3]],a2,0xff -; MIPS32: andi [[T6]],[[BV_E2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T8]] -; MIPS32: srl [[T3]],a2,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T6]] -; MIPS32: srl [[T3]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T6]],[[BV_E2]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T2]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T5]],[[T5]],[[T4]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: slt [[T10]],[[T10]],[[T9]] -; MIPS32: srl [[T10]],[[T10]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T5]],[[T5]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: slt [[T1]],[[T1]],[[T11]] +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff ; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]] -; MIPS32: andi [[T3]],a3,0xff -; MIPS32: andi [[T6]],[[BV_E3]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T11]] -; MIPS32: srl [[T3]],a3,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T9]],[[BV_E3]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: slt [[T9]],[[T9]],[[T3]] -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T9]],[[T9]],[[T6]] -; MIPS32: srl [[T3]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T6]],[[BV_E3]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T9]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T11]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T4]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 ; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: slt [[T2]],[[T2]],[[T12]] +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T12]],[[T3]] +; MIPS32: srl [[T12]],[[T12]],0x8 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: slt [[T12]],[[T12]],[[T10]] +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T12]],[[T12]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T12]],[[T12]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T12]],[[T12]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T12]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 ; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: slt [[T13]],[[T13]],[[T12]] -; MIPS32: srl [[T13]],[[T13]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 -; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]] +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: slt [[T3]],[[T3]],[[T13]] +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) { @@ -3131,206 +3398,232 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v16i8_sle -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T0]],[[BV_E0]],0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: slt [[T0]],[[T0]],[[T2]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T1]],[[T1]],[[T2]] -; MIPS32: or [[T0]],[[T0]],[[T1]] -; MIPS32: srl [[T2]],a0,0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: slt [[T1]],[[T1]],[[T2]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T0]],[[T0]],[[T2]] -; MIPS32: or [[T1]],[[T1]],[[T0]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: slt [[T9]],[[T9]],[[T8]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T8]],[[T0]] +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: andi [[T8]],[[T8]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: slt [[T4]],[[T4]],[[T3]] +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: slt [[T8]],[[T8]],[[T4]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T9]],[[T9]],[[T4]] +; MIPS32: or [[T8]],[[T8]],[[T9]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: slt [[T9]],[[T9]],[[T4]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T8]],[[T8]],[[T4]] +; MIPS32: or [[T9]],[[T9]],[[T8]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: slt [[T0]],[[T0]],[[T10]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x8 +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T4]],[[T4]],[[T10]] ; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x8 -; MIPS32: srl [[T1]],[[T1]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T3]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T3]],a1,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: slt [[T5]],[[T5]],[[T3]] +; MIPS32: slt [[T5]],[[T5]],[[T10]] ; MIPS32: xori [[T5]],[[T5]],0x1 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T5]],[[T5]],[[T2]] -; MIPS32: srl [[T3]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T2]],[[BV_E1]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T5]],[[T5]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: slt [[T7]],[[T7]],[[T6]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: srl [[T2]],[[T2]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]] -; MIPS32: andi [[T3]],a2,0xff -; MIPS32: andi [[T6]],[[BV_E2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T8]] -; MIPS32: srl [[T3]],a2,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T6]] -; MIPS32: srl [[T3]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T6]],[[BV_E2]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T2]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T5]],[[T5]],[[T4]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: slt [[T10]],[[T10]],[[T9]] -; MIPS32: xori [[T10]],[[T10]],0x1 -; MIPS32: srl [[T10]],[[T10]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T5]],[[T5]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: slt [[T1]],[[T1]],[[T11]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff ; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]] -; MIPS32: andi [[T3]],a3,0xff -; MIPS32: andi [[T6]],[[BV_E3]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T11]] -; MIPS32: srl [[T3]],a3,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T9]],[[BV_E3]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: slt [[T9]],[[T9]],[[T3]] -; MIPS32: xori [[T9]],[[T9]],0x1 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T9]],[[T9]],[[T6]] -; MIPS32: srl [[T3]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T6]],[[BV_E3]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T9]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T11]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T4]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 ; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: slt [[T2]],[[T2]],[[T12]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T12]],[[T3]] +; MIPS32: srl [[T12]],[[T12]],0x8 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: slt [[T12]],[[T12]],[[T10]] +; MIPS32: xori [[T12]],[[T12]],0x1 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T12]],[[T12]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T12]],[[T12]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T12]],[[T12]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T12]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 ; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: slt [[T13]],[[T13]],[[T12]] -; MIPS32: xori [[T13]],[[T13]],0x1 -; MIPS32: srl [[T13]],[[T13]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 -; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]] +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: slt [[T3]],[[T3]],[[T13]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) { @@ -3341,190 +3634,218 @@ ; CHECK: pcmpgtb ; MIPS32-LABEL: test_icmp_v16i8_slt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: slt [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: slt [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: slt [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: slt [[T3]],[[T3]],[[T4]] -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T4]],[[T4]],[[T2]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: slt [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: slt [[T2]],[[T2]],[[T5]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: slt [[T4]],[[T4]],[[T9]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: slt [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: slt [[T10]],[[T10]],[[T0]] +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 ; MIPS32: slt [[T4]],[[T4]],[[T5]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T5]],[[T5]],0x18 +; MIPS32: slt [[T0]],[[T0]],[[T5]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: slt [[T6]],[[T6]],[[T7]] -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: slt [[T11]],[[T11]],[[T1]] +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: slt [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T7]],[[BV_E2]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: slt [[T4]],[[T4]],[[T7]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T1]],[[T1]],[[T4]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: slt [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T12]],[[T12]],0x18 ; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T7]],[[T7]],[[T2]] -; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: slt [[T12]],[[T12]],[[T2]] +; MIPS32: srl [[T12]],[[T12]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: slt [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 ; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: slt [[T1]],[[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 ; MIPS32: lui [[T2]],0xffff ; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x10 +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 ; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 ; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: slt [[T4]],[[T4]],[[T2]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T2]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T2]],0xff00 ; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: slt [[T9]],[[T9]],[[T10]] -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: slt [[T4]],[[T4]],[[T7]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: slt [[T7]],[[T7]],[[T10]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: slt [[T4]],[[T4]],[[T10]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 ; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: slt [[T12]],[[T12]],[[T13]] -; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: slt [[T13]],[[T13]],[[T3]] +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) { @@ -3537,206 +3858,234 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v16i8_uge -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: xori [[T3]],[[T3]],0x1 -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T2]] +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T4]],[[T4]],[[T9]] ; MIPS32: xori [[T4]],[[T4]],0x1 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T5]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sltu [[T10]],[[T10]],[[T0]] +; MIPS32: xori [[T10]],[[T10]],0x1 +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T1]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 ; MIPS32: sltu [[T4]],[[T4]],[[T5]] ; MIPS32: xori [[T4]],[[T4]],0x1 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T5]],[[T5]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T5]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T7]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T1]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T7]],[[BV_E2]],0xff +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T1]],[[T1]],0x18 ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T7]] -; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: sltu [[T1]],[[T1]],[[T4]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T7]],[[T7]],[[T2]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T2]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: sltu [[T9]],[[T9]],[[T10]] -; MIPS32: xori [[T9]],[[T9]],0x1 -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T7]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: sltu [[T7]],[[T7]],[[T10]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T10]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 ; MIPS32: sll [[T12]],[[T12]],0x18 -; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: sltu [[T12]],[[T12]],[[T13]] +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: sltu [[T12]],[[T12]],[[T2]] ; MIPS32: xori [[T12]],[[T12]],0x1 ; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: sltu [[T1]],[[T1]],[[T2]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T2]],0xffff +; MIPS32: ori [[T2]],[[T2]],0xff +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T2]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T2]],0xff00 +; MIPS32: ori [[T2]],[[T2]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T13]],[[T13]],0x18 +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: sltu [[T13]],[[T13]],[[T3]] +; MIPS32: xori [[T13]],[[T13]],0x1 +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) { @@ -3748,190 +4097,216 @@ ; CHECK: pcmpgtb ; MIPS32-LABEL: test_icmp_v16i8_ugt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T0]],[[BV_E0]],0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sltu [[T0]],[[T0]],[[T2]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T1]],[[T1]],[[T2]] -; MIPS32: or [[T0]],[[T0]],[[T1]] -; MIPS32: srl [[T2]],a0,0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T0]],[[T0]],[[T2]] -; MIPS32: or [[T1]],[[T1]],[[T0]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T9]],[[T9]],[[T8]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T8]],[[T0]] +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: andi [[T8]],[[T8]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T3]] -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x8 -; MIPS32: srl [[T1]],[[T1]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T3]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T3]],a1,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sltu [[T8]],[[T8]],[[T4]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T9]],[[T9]],[[T4]] +; MIPS32: or [[T8]],[[T8]],[[T9]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T9]],[[T9]],[[T4]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T8]],[[T8]],[[T4]] +; MIPS32: or [[T9]],[[T9]],[[T8]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T10]] +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x8 +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: sltu [[T5]],[[T5]],[[T3]] +; MIPS32: sltu [[T5]],[[T5]],[[T10]] ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T5]],[[T5]],[[T2]] -; MIPS32: srl [[T3]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T2]],[[BV_E1]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T5]],[[T5]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sltu [[T7]],[[T7]],[[T6]] -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: srl [[T2]],[[T2]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]] -; MIPS32: andi [[T3]],a2,0xff -; MIPS32: andi [[T6]],[[BV_E2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T8]] -; MIPS32: srl [[T3]],a2,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T6]] -; MIPS32: srl [[T3]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T6]],[[BV_E2]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T2]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T5]],[[T5]],[[T4]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: sltu [[T10]],[[T10]],[[T9]] -; MIPS32: srl [[T10]],[[T10]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T5]],[[T5]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sltu [[T1]],[[T1]],[[T11]] +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff ; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]] -; MIPS32: andi [[T3]],a3,0xff -; MIPS32: andi [[T6]],[[BV_E3]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T11]] -; MIPS32: srl [[T3]],a3,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T9]],[[BV_E3]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: sltu [[T9]],[[T9]],[[T3]] -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T9]],[[T9]],[[T6]] -; MIPS32: srl [[T3]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T6]],[[BV_E3]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T9]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T11]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T4]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 ; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: sltu [[T2]],[[T2]],[[T12]] +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T12]],[[T3]] +; MIPS32: srl [[T12]],[[T12]],0x8 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: sltu [[T12]],[[T12]],[[T10]] +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T12]],[[T12]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T12]],[[T12]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T12]],[[T12]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T12]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 ; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: sltu [[T13]],[[T13]],[[T12]] -; MIPS32: srl [[T13]],[[T13]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 -; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]] +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: sltu [[T3]],[[T3]],[[T13]] +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) { @@ -3944,206 +4319,232 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v16i8_ule -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T0]],[[BV_E0]],0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sltu [[T0]],[[T0]],[[T2]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T1]],[[T1]],[[T2]] -; MIPS32: or [[T0]],[[T0]],[[T1]] -; MIPS32: srl [[T2]],a0,0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T0]],[[T0]],[[T2]] -; MIPS32: or [[T1]],[[T1]],[[T0]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T9]],[[T9]],[[T8]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T8]],[[T0]] +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: andi [[T8]],[[T8]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T3]] +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sltu [[T8]],[[T8]],[[T4]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T9]],[[T9]],[[T4]] +; MIPS32: or [[T8]],[[T8]],[[T9]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T9]],[[T9]],[[T4]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T8]],[[T8]],[[T4]] +; MIPS32: or [[T9]],[[T9]],[[T8]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T10]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x8 +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] ; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x8 -; MIPS32: srl [[T1]],[[T1]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T3]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T3]],a1,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: sltu [[T5]],[[T5]],[[T3]] +; MIPS32: sltu [[T5]],[[T5]],[[T10]] ; MIPS32: xori [[T5]],[[T5]],0x1 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T5]],[[T5]],[[T2]] -; MIPS32: srl [[T3]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T2]],[[BV_E1]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T5]],[[T5]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sltu [[T7]],[[T7]],[[T6]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: srl [[T2]],[[T2]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]] -; MIPS32: andi [[T3]],a2,0xff -; MIPS32: andi [[T6]],[[BV_E2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T8]] -; MIPS32: srl [[T3]],a2,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T6]] -; MIPS32: srl [[T3]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T6]],[[BV_E2]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T2]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T5]],[[T5]],[[T4]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: sltu [[T10]],[[T10]],[[T9]] -; MIPS32: xori [[T10]],[[T10]],0x1 -; MIPS32: srl [[T10]],[[T10]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T5]],[[T5]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sltu [[T1]],[[T1]],[[T11]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff ; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]] -; MIPS32: andi [[T3]],a3,0xff -; MIPS32: andi [[T6]],[[BV_E3]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T11]] -; MIPS32: srl [[T3]],a3,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T9]],[[BV_E3]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: sltu [[T9]],[[T9]],[[T3]] -; MIPS32: xori [[T9]],[[T9]],0x1 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T9]],[[T9]],[[T6]] -; MIPS32: srl [[T3]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: srl [[T6]],[[BV_E3]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T9]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T11]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T2]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T4]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 ; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: sltu [[T2]],[[T2]],[[T12]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T12]],[[T3]] +; MIPS32: srl [[T12]],[[T12]],0x8 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: sltu [[T12]],[[T12]],[[T10]] +; MIPS32: xori [[T12]],[[T12]],0x1 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T12]],[[T12]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T12]],[[T12]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: move [[T11]],[[T3]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T12]],[[T12]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T12]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 ; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: sltu [[T13]],[[T13]],[[T12]] -; MIPS32: xori [[T13]],[[T13]],0x1 -; MIPS32: srl [[T13]],[[T13]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 -; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]] +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: sltu [[T3]],[[T3]],[[T13]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) { @@ -4155,190 +4556,218 @@ ; CHECK: pcmpgtb ; MIPS32-LABEL: test_icmp_v16i8_ult -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[TV_E0]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T0]],[[T0]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x18 -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: sll [[T3]],[[T3]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T2]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[TV_E1]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sll [[T5]],[[T5]],0x18 -; MIPS32: sltu [[T2]],[[T2]],[[T5]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T4]],[[T4]],[[T9]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T8]],[[T8]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x18 +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T10]],[[T10]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sltu [[T10]],[[T10]],[[T0]] +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T4]],[[T4]],0x18 ; MIPS32: sll [[T5]],[[T5]],0x18 ; MIPS32: sltu [[T4]],[[T4]],[[T5]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T5]],[[T5]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T5]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sltu [[T6]],[[T6]],[[T7]] -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sltu [[T11]],[[T11]],[[T1]] +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T7]],[[BV_E2]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T7]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[TV_E2]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T1]],[[T1]],[[T4]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T12]],[[T12]],0x18 ; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T7]],[[T7]],[[T2]] -; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: sltu [[T12]],[[T12]],[[T2]] +; MIPS32: srl [[T12]],[[T12]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T0]],[[T0]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 ; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T1]],[[T1]],0x18 +; MIPS32: sll [[T2]],[[T2]],0x18 +; MIPS32: sltu [[T1]],[[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 ; MIPS32: lui [[T2]],0xffff ; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T2]],[[BV_E2]],0x10 +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 ; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x18 ; MIPS32: sll [[T2]],[[T2]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T2]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T2]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T2]],0xff00 ; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: sll [[T9]],[[T9]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: sltu [[T9]],[[T9]],[[T10]] -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T7]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[TV_E3]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T7]],[[T7]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: sltu [[T7]],[[T7]],[[T10]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: sll [[T4]],[[T4]],0x18 -; MIPS32: sll [[T10]],[[T10]],0x18 -; MIPS32: sltu [[T4]],[[T4]],[[T10]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: sll [[T12]],[[T12]],0x18 +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: srl [[T3]],[[T3]],0x18 ; MIPS32: sll [[T13]],[[T13]],0x18 -; MIPS32: sltu [[T12]],[[T12]],[[T13]] -; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T3]],[[T3]],0x18 +; MIPS32: sltu [[T13]],[[T13]],[[T3]] +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) { @@ -4349,102 +4778,96 @@ ; CHECK: pcmpeqb ; MIPS32-LABEL: test_icmp_v16i1_eq -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: xor [[T0]],[[T0]],[[T1]] -; MIPS32: sltiu [[T0]],[[T0]],1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: xor [[T2]],[[T2]],[[T1]] -; MIPS32: sltiu [[T2]],[[T2]],1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: xor [[T0]],[[T0]],[[T1]] -; MIPS32: sltiu [[T0]],[[T0]],1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltiu [[T8]],[[T8]],1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: xor [[T3]],[[T3]],[[T4]] -; MIPS32: sltiu [[T3]],[[T3]],1 -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T2]] +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: xor [[T4]],[[T4]],[[T9]] ; MIPS32: sltiu [[T4]],[[T4]],1 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T2]],[[T2]],[[T5]] -; MIPS32: sltiu [[T2]],[[T2]],1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltiu [[T8]],[[T8]],1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: xor [[T10]],[[T10]],[[T0]] +; MIPS32: sltiu [[T10]],[[T10]],1 +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f @@ -4452,135 +4875,169 @@ ; MIPS32: xor [[T4]],[[T4]],[[T5]] ; MIPS32: sltiu [[T4]],[[T4]],1 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: andi [[T5]],[[T5]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T5]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: xor [[T6]],[[T6]],[[T7]] -; MIPS32: sltiu [[T6]],[[T6]],1 -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T11]],[[T11]],[[T1]] +; MIPS32: sltiu [[T11]],[[T11]],1 +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E2]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T7]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T7]],[[T7]],[[T2]] -; MIPS32: sltiu [[T7]],[[T7]],1 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T2]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: xor [[T9]],[[T9]],[[T10]] -; MIPS32: sltiu [[T9]],[[T9]],1 -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T7]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: xor [[T7]],[[T7]],[[T10]] -; MIPS32: sltiu [[T7]],[[T7]],1 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 +; MIPS32: xor [[T1]],[[T1]],[[T4]] +; MIPS32: sltiu [[T1]],[[T1]],1 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T10]] -; MIPS32: sltiu [[T4]],[[T4]],1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 ; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 ; MIPS32: sll [[T12]],[[T12]],0x1f -; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: xor [[T12]],[[T12]],[[T13]] +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: xor [[T12]],[[T12]],[[T2]] ; MIPS32: sltiu [[T12]],[[T12]],1 ; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: xor [[T1]],[[T1]],[[T2]] +; MIPS32: sltiu [[T1]],[[T1]],1 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T2]],0xffff +; MIPS32: ori [[T2]],[[T2]],0xff +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T2]] +; MIPS32: sltiu [[T0]],[[T0]],1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T2]],0xff00 +; MIPS32: ori [[T2]],[[T2]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: xor [[T13]],[[T13]],[[T3]] +; MIPS32: sltiu [[T13]],[[T13]],1 +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) { @@ -4592,102 +5049,96 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v16i1_ne -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: xor [[T0]],[[T0]],[[T1]] -; MIPS32: sltu [[T0]],zero,[[T0]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: xor [[T2]],[[T2]],[[T1]] -; MIPS32: sltu [[T2]],zero,[[T2]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: xor [[T0]],[[T0]],[[T1]] -; MIPS32: sltu [[T0]],zero,[[T0]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltu [[T8]],zero,[[T8]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: xor [[T3]],[[T3]],[[T4]] -; MIPS32: sltu [[T3]],zero,[[T3]] -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T2]] +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: xor [[T4]],[[T4]],[[T9]] ; MIPS32: sltu [[T4]],zero,[[T4]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: xor [[T2]],[[T2]],[[T5]] -; MIPS32: sltu [[T2]],zero,[[T2]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: xor [[T8]],[[T8]],[[T9]] +; MIPS32: sltu [[T8]],zero,[[T8]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: xor [[T10]],[[T10]],[[T0]] +; MIPS32: sltu [[T10]],zero,[[T10]] +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f @@ -4695,135 +5146,169 @@ ; MIPS32: xor [[T4]],[[T4]],[[T5]] ; MIPS32: sltu [[T4]],zero,[[T4]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: andi [[T5]],[[T5]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T5]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: xor [[T6]],[[T6]],[[T7]] -; MIPS32: sltu [[T6]],zero,[[T6]] -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T11]],[[T11]],[[T1]] +; MIPS32: sltu [[T11]],zero,[[T11]] +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E2]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T7]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T7]],[[T7]],[[T2]] -; MIPS32: sltu [[T7]],zero,[[T7]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T2]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: xor [[T9]],[[T9]],[[T10]] -; MIPS32: sltu [[T9]],zero,[[T9]] -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T7]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: xor [[T7]],[[T7]],[[T10]] -; MIPS32: sltu [[T7]],zero,[[T7]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 +; MIPS32: xor [[T1]],[[T1]],[[T4]] +; MIPS32: sltu [[T1]],zero,[[T1]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: xor [[T4]],[[T4]],[[T10]] -; MIPS32: sltu [[T4]],zero,[[T4]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 +; MIPS32: xor [[T0]],[[T0]],[[T4]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 ; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 ; MIPS32: sll [[T12]],[[T12]],0x1f -; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: xor [[T12]],[[T12]],[[T13]] +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: xor [[T12]],[[T12]],[[T2]] ; MIPS32: sltu [[T12]],zero,[[T12]] ; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T1]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: xor [[T1]],[[T1]],[[T2]] +; MIPS32: sltu [[T1]],zero,[[T1]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T2]],0xffff +; MIPS32: ori [[T2]],[[T2]],0xff +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: xor [[T0]],[[T0]],[[T2]] +; MIPS32: sltu [[T0]],zero,[[T0]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T2]],0xff00 +; MIPS32: ori [[T2]],[[T2]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: xor [[T13]],[[T13]],[[T3]] +; MIPS32: sltu [[T13]],zero,[[T13]] +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) { @@ -4834,222 +5319,248 @@ ; CHECK: pcmpgtb ; MIPS32-LABEL: test_icmp_v16i1_sgt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T0]],[[BV_E0]],0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: slt [[T0]],[[T0]],[[T2]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T1]],[[T1]],[[T2]] -; MIPS32: or [[T0]],[[T0]],[[T1]] -; MIPS32: srl [[T2]],a0,0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T2]] -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T0]],[[T0]],[[T2]] -; MIPS32: or [[T1]],[[T1]],[[T0]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T9]],[[T9]],[[T8]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: move [[T8]],[[T0]] +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x8 -; MIPS32: srl [[T1]],[[T1]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T3]],a1,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: slt [[T8]],[[T8]],[[T4]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T9]],[[T9]],[[T4]] +; MIPS32: or [[T8]],[[T8]],[[T9]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T9]],[[T9]],[[T4]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T8]],[[T8]],[[T4]] +; MIPS32: or [[T9]],[[T9]],[[T8]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T10]] +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x8 +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T3]],a1,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: slt [[T5]],[[T5]],[[T3]] +; MIPS32: slt [[T5]],[[T5]],[[T10]] ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T5]],[[T5]],[[T2]] -; MIPS32: srl [[T3]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T2]],[[BV_E1]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T5]],[[T5]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: slt [[T7]],[[T7]],[[T6]] -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: srl [[T2]],[[T2]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]] -; MIPS32: andi [[T3]],a2,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T6]],[[BV_E2]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T8]] -; MIPS32: srl [[T3]],a2,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T6]] -; MIPS32: srl [[T3]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T6]],[[BV_E2]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T2]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T5]],[[T5]],[[T4]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff ; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: move [[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 ; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: slt [[T10]],[[T10]],[[T9]] -; MIPS32: srl [[T10]],[[T10]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T5]],[[T5]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt [[T1]],[[T1]],[[T11]] +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff ; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]] -; MIPS32: andi [[T3]],a3,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T6]],[[BV_E3]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T11]] -; MIPS32: srl [[T3]],a3,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T9]],[[BV_E3]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: slt [[T9]],[[T9]],[[T3]] -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T9]],[[T9]],[[T6]] -; MIPS32: srl [[T3]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T6]],[[BV_E3]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T9]] -; MIPS32: srl [[T12:.*]],a3,0x18 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T11]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T4]] +; MIPS32: srl [[T12:.*]],a2,0x18 ; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 ; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T2]],[[T2]],[[T12]] +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T12]],[[T3]] +; MIPS32: srl [[T12]],[[T12]],0x8 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: slt [[T12]],[[T12]],[[T10]] +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T12]],[[T12]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T12]],[[T12]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T12]],[[T12]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T12]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 ; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: slt [[T13]],[[T13]],[[T12]] -; MIPS32: srl [[T13]],[[T13]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 -; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]] +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: slt [[T3]],[[T3]],[[T13]] +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) { @@ -5061,238 +5572,264 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v16i1_sle -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T0]],[[BV_E0]],0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: slt [[T0]],[[T0]],[[T2]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T1]],[[T1]],[[T2]] -; MIPS32: or [[T0]],[[T0]],[[T1]] -; MIPS32: srl [[T2]],a0,0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T1]],[[T1]],[[T2]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T0]],[[T0]],[[T2]] -; MIPS32: or [[T1]],[[T1]],[[T0]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T9]],[[T9]],[[T8]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: move [[T8]],[[T0]] +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T3]] +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: slt [[T8]],[[T8]],[[T4]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T9]],[[T9]],[[T4]] +; MIPS32: or [[T8]],[[T8]],[[T9]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T9]],[[T9]],[[T4]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T8]],[[T8]],[[T4]] +; MIPS32: or [[T9]],[[T9]],[[T8]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T10]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x8 +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T4]],[[T4]],[[T10]] ; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x8 -; MIPS32: srl [[T1]],[[T1]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T3]],a1,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T3]],a1,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: slt [[T5]],[[T5]],[[T3]] +; MIPS32: slt [[T5]],[[T5]],[[T10]] ; MIPS32: xori [[T5]],[[T5]],0x1 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T5]],[[T5]],[[T2]] -; MIPS32: srl [[T3]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T2]],[[BV_E1]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T5]],[[T5]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: slt [[T7]],[[T7]],[[T6]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: srl [[T2]],[[T2]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]] -; MIPS32: andi [[T3]],a2,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T6]],[[BV_E2]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T8]] -; MIPS32: srl [[T3]],a2,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T6]] -; MIPS32: srl [[T3]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T6]],[[BV_E2]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T2]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T5]],[[T5]],[[T4]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff ; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: move [[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 ; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: slt [[T10]],[[T10]],[[T9]] -; MIPS32: xori [[T10]],[[T10]],0x1 -; MIPS32: srl [[T10]],[[T10]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T5]],[[T5]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt [[T1]],[[T1]],[[T11]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff ; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]] -; MIPS32: andi [[T3]],a3,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T6]],[[BV_E3]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T11]] -; MIPS32: srl [[T3]],a3,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T9]],[[BV_E3]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: slt [[T9]],[[T9]],[[T3]] -; MIPS32: xori [[T9]],[[T9]],0x1 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T9]],[[T9]],[[T6]] -; MIPS32: srl [[T3]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T6]],[[BV_E3]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T9]] -; MIPS32: srl [[T12:.*]],a3,0x18 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T11]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T4]] +; MIPS32: srl [[T12:.*]],a2,0x18 ; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 ; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T2]],[[T2]],[[T12]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T12]],[[T3]] +; MIPS32: srl [[T12]],[[T12]],0x8 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: slt [[T12]],[[T12]],[[T10]] +; MIPS32: xori [[T12]],[[T12]],0x1 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T12]],[[T12]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T12]],[[T12]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T12]],[[T12]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T12]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 ; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: slt [[T13]],[[T13]],[[T12]] -; MIPS32: xori [[T13]],[[T13]],0x1 -; MIPS32: srl [[T13]],[[T13]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 -; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]] +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: slt [[T3]],[[T3]],[[T13]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) { @@ -5303,222 +5840,250 @@ ; CHECK: pcmpgtb ; MIPS32-LABEL: test_icmp_v16i1_slt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: slt [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: slt [[T3]],[[T3]],[[T4]] -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T2]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T4]],[[T4]],[[T9]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: slt [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: slt [[T10]],[[T10]],[[T0]] +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: slt [[T2]],[[T2]],[[T5]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f ; MIPS32: sll [[T5]],[[T5]],0x1f ; MIPS32: slt [[T4]],[[T4]],[[T5]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: andi [[T5]],[[T5]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T5]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: slt [[T6]],[[T6]],[[T7]] -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt [[T11]],[[T11]],[[T1]] +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E2]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T7]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T1]],[[T1]],[[T4]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: slt [[T12]],[[T12]],[[T2]] +; MIPS32: srl [[T12]],[[T12]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: slt [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 ; MIPS32: andi [[T2]],[[T2]],0xff ; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T7]],[[T7]],[[T2]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: slt [[T1]],[[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 ; MIPS32: lui [[T2]],0xffff ; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x10 +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 ; MIPS32: andi [[T2]],[[T2]],0xff ; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T2]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: slt [[T0]],[[T0]],[[T2]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T2]],0xff00 ; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: slt [[T9]],[[T9]],[[T10]] -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T7]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: slt [[T7]],[[T7]],[[T10]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: slt [[T4]],[[T4]],[[T10]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 ; MIPS32: andi [[T13]],[[T13]],0x1 -; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 ; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: slt [[T12]],[[T12]],[[T13]] -; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: slt [[T13]],[[T13]],[[T3]] +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) { @@ -5531,102 +6096,96 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v16i1_uge -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: xori [[T3]],[[T3]],0x1 -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T2]] +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T9]] ; MIPS32: xori [[T4]],[[T4]],0x1 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 -; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T5]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T10]],[[T10]],[[T0]] +; MIPS32: xori [[T10]],[[T10]],0x1 +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f @@ -5634,135 +6193,169 @@ ; MIPS32: sltu [[T4]],[[T4]],[[T5]] ; MIPS32: xori [[T4]],[[T4]],0x1 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: andi [[T5]],[[T5]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T5]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T7]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T1]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E2]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T7]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T7]],[[T7]],[[T2]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T2]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: sltu [[T9]],[[T9]],[[T10]] -; MIPS32: xori [[T9]],[[T9]],0x1 -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T7]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: sltu [[T7]],[[T7]],[[T10]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 +; MIPS32: sltu [[T1]],[[T1]],[[T4]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T10]] -; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 ; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 ; MIPS32: sll [[T12]],[[T12]],0x1f -; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: sltu [[T12]],[[T12]],[[T13]] +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T12]],[[T12]],[[T2]] ; MIPS32: xori [[T12]],[[T12]],0x1 ; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T1]],[[T1]],[[T2]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T2]],0xffff +; MIPS32: ori [[T2]],[[T2]],0xff +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T2]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T2]],0xff00 +; MIPS32: ori [[T2]],[[T2]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T13]],[[T13]],0x1f +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T13]],[[T13]],[[T3]] +; MIPS32: xori [[T13]],[[T13]],0x1 +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] } define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) { @@ -5774,222 +6367,248 @@ ; CHECK: pcmpgtb ; MIPS32-LABEL: test_icmp_v16i1_ugt -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T0]],[[BV_E0]],0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T2]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T1]],[[T1]],[[T2]] -; MIPS32: or [[T0]],[[T0]],[[T1]] -; MIPS32: srl [[T2]],a0,0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T0]],[[T0]],[[T2]] -; MIPS32: or [[T1]],[[T1]],[[T0]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T9]],[[T9]],[[T8]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: move [[T8]],[[T0]] +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x8 -; MIPS32: srl [[T1]],[[T1]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T3]],a1,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sltu [[T8]],[[T8]],[[T4]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T9]],[[T9]],[[T4]] +; MIPS32: or [[T8]],[[T8]],[[T9]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T9]],[[T9]],[[T4]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T8]],[[T8]],[[T4]] +; MIPS32: or [[T9]],[[T9]],[[T8]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T10]] +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x8 +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T3]],a1,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: sltu [[T5]],[[T5]],[[T3]] +; MIPS32: sltu [[T5]],[[T5]],[[T10]] ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T5]],[[T5]],[[T2]] -; MIPS32: srl [[T3]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T2]],[[BV_E1]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T5]],[[T5]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sltu [[T7]],[[T7]],[[T6]] -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: srl [[T2]],[[T2]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]] -; MIPS32: andi [[T3]],a2,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T6]],[[BV_E2]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T8]] -; MIPS32: srl [[T3]],a2,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T6]] -; MIPS32: srl [[T3]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T6]],[[BV_E2]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T2]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T5]],[[T5]],[[T4]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff ; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: move [[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 ; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: sltu [[T10]],[[T10]],[[T9]] -; MIPS32: srl [[T10]],[[T10]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T5]],[[T5]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T1]],[[T1]],[[T11]] +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff ; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]] -; MIPS32: andi [[T3]],a3,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T6]],[[BV_E3]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T11]] -; MIPS32: srl [[T3]],a3,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T9]],[[BV_E3]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: sltu [[T9]],[[T9]],[[T3]] -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T9]],[[T9]],[[T6]] -; MIPS32: srl [[T3]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T6]],[[BV_E3]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T9]] -; MIPS32: srl [[T12:.*]],a3,0x18 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T11]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T4]] +; MIPS32: srl [[T12:.*]],a2,0x18 ; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 ; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T2]],[[T2]],[[T12]] +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T12]],[[T3]] +; MIPS32: srl [[T12]],[[T12]],0x8 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sltu [[T12]],[[T12]],[[T10]] +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T12]],[[T12]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T12]],[[T12]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T12]],[[T12]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T12]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 ; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: sltu [[T13]],[[T13]],[[T12]] -; MIPS32: srl [[T13]],[[T13]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 -; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]] +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T3]],[[T3]],[[T13]] +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) { @@ -6002,238 +6621,264 @@ ; CHECK: pxor ; MIPS32-LABEL: test_icmp_v16i1_ule -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T0]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T1]],[[T1]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T0]],[[BV_E0]],0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T2]] -; MIPS32: xori [[T0]],[[T0]],0x1 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: lui [[T2]],0xffff -; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T1]],[[T1]],[[T2]] -; MIPS32: or [[T0]],[[T0]],[[T1]] -; MIPS32: srl [[T2]],a0,0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T1]],[[T1]],[[T2]] -; MIPS32: xori [[T1]],[[T1]],0x1 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: sll [[T1]],[[T1]],0x10 -; MIPS32: lui [[T2]],0xff00 -; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T0]],[[T0]],[[T2]] -; MIPS32: or [[T1]],[[T1]],[[T0]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T9]],[[T9]],[[T8]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T9]],[[T9]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: move [[T8]],[[T0]] +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T3]] +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sltu [[T8]],[[T8]],[[T4]] +; MIPS32: xori [[T8]],[[T8]],0x1 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T9]],[[T9]],[[T4]] +; MIPS32: or [[T8]],[[T8]],[[T9]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T9]],[[T9]],[[T4]] +; MIPS32: xori [[T9]],[[T9]],0x1 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: sll [[T9]],[[T9]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T8]],[[T8]],[[T4]] +; MIPS32: or [[T9]],[[T9]],[[T8]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T10]] +; MIPS32: xori [[T0]],[[T0]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: sll [[T9]],[[T9]],0x8 +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: or v0,[[T0]],[[T9]] +; MIPS32: move [[T10]],a1 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T10]] ; MIPS32: xori [[T4]],[[T4]],0x1 -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T1]],[[T1]],0x8 -; MIPS32: srl [[T1]],[[T1]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T1]] -; MIPS32: andi [[T3]],a1,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T3]],a1,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sll [[T10]],[[T10]],0x1f ; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: sltu [[T5]],[[T5]],[[T3]] +; MIPS32: sltu [[T5]],[[T5]],[[T10]] ; MIPS32: xori [[T5]],[[T5]],0x1 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T5]],[[T5]],[[T2]] -; MIPS32: srl [[T3]],a1,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T2]],[[BV_E1]],0x10 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T5]],[[T5]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T5]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sltu [[T7]],[[T7]],[[T6]] -; MIPS32: xori [[T7]],[[T7]],0x1 -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: srl [[T2]],[[T2]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T7]],[[T2]] -; MIPS32: andi [[T3]],a2,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T6]],[[BV_E2]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T8]] -; MIPS32: srl [[T3]],a2,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T3]] -; MIPS32: xori [[T2]],[[T2]],0x1 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T2]],[[T2]],[[T6]] -; MIPS32: srl [[T3]],a2,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T6]],[[BV_E2]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T2]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T5]],[[T5]],[[T4]] +; MIPS32: move [[T10]],a1 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff ; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: move [[T4]],[[T1]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 ; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: sltu [[T10]],[[T10]],[[T9]] -; MIPS32: xori [[T10]],[[T10]],0x1 -; MIPS32: srl [[T10]],[[T10]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T5]],[[T5]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T5]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T1]],[[T1]],[[T11]] +; MIPS32: xori [[T1]],[[T1]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: or v1,[[T1]],[[T4]] +; MIPS32: move [[T10]],a2 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff ; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T10]],[[T6]] -; MIPS32: andi [[T3]],a3,0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: andi [[T6]],[[BV_E3]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T6]],[[T6]],[[T11]] -; MIPS32: srl [[T3]],a3,0x8 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T9]],[[BV_E3]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: sltu [[T9]],[[T9]],[[T3]] -; MIPS32: xori [[T9]],[[T9]],0x1 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T3]],0xffff -; MIPS32: ori [[T3]],[[T3]],0xff -; MIPS32: and [[T6]],[[T6]],[[T3]] -; MIPS32: or [[T9]],[[T9]],[[T6]] -; MIPS32: srl [[T3]],a3,0x10 -; MIPS32: andi [[T3]],[[T3]],0xff -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T6]],[[BV_E3]],0x10 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T3]] -; MIPS32: xori [[T6]],[[T6]],0x1 -; MIPS32: andi [[T6]],[[T6]],0xff -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: lui [[T3]],0xff00 -; MIPS32: ori [[T3]],[[T3]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T3]] -; MIPS32: or [[T6]],[[T6]],[[T9]] -; MIPS32: srl [[T12:.*]],a3,0x18 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T6]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T10]] +; MIPS32: xori [[T4]],[[T4]],0x1 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T4]],[[T4]],[[T11]] +; MIPS32: move [[T10]],a2 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T2]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T4]] +; MIPS32: srl [[T12:.*]],a2,0x18 ; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 -; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 ; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T2]],[[T2]],[[T12]] +; MIPS32: xori [[T2]],[[T2]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T2]],[[T2]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T7]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x8 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T12]],[[T3]] +; MIPS32: srl [[T12]],[[T12]],0x8 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sltu [[T12]],[[T12]],[[T10]] +; MIPS32: xori [[T12]],[[T12]],0x1 +; MIPS32: andi [[T12]],[[T12]],0xff +; MIPS32: sll [[T12]],[[T12]],0x8 +; MIPS32: lui [[T10]],0xffff +; MIPS32: ori [[T10]],[[T10]],0xff +; MIPS32: and [[T11]],[[T11]],[[T10]] +; MIPS32: or [[T12]],[[T12]],[[T11]] +; MIPS32: move [[T10]],a3 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0xff +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: move [[T11]],[[T3]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T10]] +; MIPS32: xori [[T11]],[[T11]],0x1 +; MIPS32: andi [[T11]],[[T11]],0xff +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: lui [[T10]],0xff00 +; MIPS32: ori [[T10]],[[T10]],0xffff +; MIPS32: and [[T12]],[[T12]],[[T10]] +; MIPS32: or [[T11]],[[T11]],[[T12]] +; MIPS32: srl [[T13:.*]],a3,0x18 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 ; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: sltu [[T13]],[[T13]],[[T12]] -; MIPS32: xori [[T13]],[[T13]],0x1 -; MIPS32: srl [[T13]],[[T13]],0x18 -; MIPS32: sll [[T6]],[[T6]],0x8 -; MIPS32: srl [[T6]],[[T6]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T13]],[[T6]] +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T3]],[[T3]],[[T13]] +; MIPS32: xori [[T3]],[[T3]],0x1 +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: sll [[T11]],[[T11]],0x8 +; MIPS32: srl [[T11]],[[T11]],0x8 +; MIPS32: or [[T3]],[[T3]],[[T11]] +; MIPS32: move a0,[[T2]] +; MIPS32: move a1,[[T3]] } define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) { @@ -6245,220 +6890,248 @@ ; CHECK: pcmpgtb ; MIPS32-LABEL: test_icmp_v16i1_ult -; MIPS32: lw [[BV_E0:.*]], -; MIPS32: lw [[BV_E1:.*]], -; MIPS32: lw [[BV_E2:.*]], -; MIPS32: lw [[BV_E3:.*]], -; MIPS32: move [[TV_E0:.*]],zero -; MIPS32: move [[TV_E1:.*]],zero -; MIPS32: move [[TV_E2:.*]],zero -; MIPS32: move [[TV_E3:.*]],zero -; MIPS32: andi [[T0:.*]],a0,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1:.*]],[[BV_E0]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: srl [[T2:.*]],[[TV_E0]],0x8 -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T2]],a0,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T1]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T1]],0xffff -; MIPS32: ori [[T1]],[[T1]],0xff -; MIPS32: and [[T0]],[[T0]],[[T1]] -; MIPS32: or [[T2]],[[T2]],[[T0]] -; MIPS32: srl [[T0]],a0,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[BV_E0]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: sll [[T0]],[[T0]],0x1f -; MIPS32: sll [[T1]],[[T1]],0x1f -; MIPS32: sltu [[T0]],[[T0]],[[T1]] -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: sll [[T0]],[[T0]],0x10 -; MIPS32: lui [[T1]],0xff00 -; MIPS32: ori [[T1]],[[T1]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T1]] -; MIPS32: or [[T0]],[[T0]],[[T2]] -; MIPS32: srl [[T3:.*]],a0,0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 -; MIPS32: srl [[T4:.*]],[[BV_E0]],0x18 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: sll [[T3]],[[T3]],0x1f -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sltu [[T3]],[[T3]],[[T4]] -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: sll [[T0]],[[T0]],0x8 -; MIPS32: srl [[T0]],[[T0]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T3]],[[T0]] -; MIPS32: andi [[T4]],a1,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T2]],[[BV_E1]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T2]] +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: move [[T4:.*]],zero +; MIPS32: move [[T5:.*]],zero +; MIPS32: move [[T6:.*]],zero +; MIPS32: move [[T7:.*]],zero +; MIPS32: move [[T8:.*]],a0 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9:.*]],[[T0]] +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: move [[T4]],a0 +; MIPS32: srl [[T4]],[[T4]],0x8 ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T5:.*]],[[TV_E1]],0x8 +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x8 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T4]],[[T4]],[[T9]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T9]],0xffff +; MIPS32: ori [[T9]],[[T9]],0xff +; MIPS32: and [[T8]],[[T8]],[[T9]] +; MIPS32: or [[T4]],[[T4]],[[T8]] +; MIPS32: move [[T8]],a0 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: move [[T9]],[[T0]] +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0xff +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: sll [[T8]],[[T8]],0x1f +; MIPS32: sll [[T9]],[[T9]],0x1f +; MIPS32: sltu [[T8]],[[T8]],[[T9]] +; MIPS32: andi [[T8]],[[T8]],0xff +; MIPS32: sll [[T8]],[[T8]],0x10 +; MIPS32: lui [[T9]],0xff00 +; MIPS32: ori [[T9]],[[T9]],0xffff +; MIPS32: and [[T4]],[[T4]],[[T9]] +; MIPS32: or [[T8]],[[T8]],[[T4]] +; MIPS32: srl [[T10:.*]],a0,0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: srl [[T0]],[[T0]],0x18 +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: sll [[T10]],[[T10]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sltu [[T10]],[[T10]],[[T0]] +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T8]],[[T8]],0x8 +; MIPS32: srl [[T8]],[[T8]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T8]] +; MIPS32: move [[T0]],a1 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T1]] +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: sll [[T5]],[[T5]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T5]] -; MIPS32: srl [[T2]],a1,0x8 -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x8 -; MIPS32: andi [[T5]],[[T5]],0xff -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sll [[T5]],[[T5]],0x1f -; MIPS32: sltu [[T2]],[[T2]],[[T5]] -; MIPS32: andi [[T2]],[[T2]],0xff -; MIPS32: sll [[T2]],[[T2]],0x8 -; MIPS32: lui [[T5]],0xffff -; MIPS32: ori [[T5]],[[T5]],0xff -; MIPS32: and [[T4]],[[T4]],[[T5]] -; MIPS32: or [[T2]],[[T2]],[[T4]] -; MIPS32: srl [[T4]],a1,0x10 +; MIPS32: or [[T0]],[[T0]],[[T5]] +; MIPS32: move [[T4]],a1 +; MIPS32: srl [[T4]],[[T4]],0x8 ; MIPS32: andi [[T4]],[[T4]],0xff ; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T5]],[[BV_E1]],0x10 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x8 ; MIPS32: andi [[T5]],[[T5]],0xff ; MIPS32: andi [[T5]],[[T5]],0x1 ; MIPS32: sll [[T4]],[[T4]],0x1f ; MIPS32: sll [[T5]],[[T5]],0x1f ; MIPS32: sltu [[T4]],[[T4]],[[T5]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: lui [[T5]],0xffff +; MIPS32: ori [[T5]],[[T5]],0xff +; MIPS32: and [[T0]],[[T0]],[[T5]] +; MIPS32: or [[T4]],[[T4]],[[T0]] +; MIPS32: move [[T0]],a1 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T5]],[[T1]] +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: andi [[T5]],[[T5]],0xff +; MIPS32: andi [[T5]],[[T5]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T5]],[[T5]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T5]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T5]],0xff00 ; MIPS32: ori [[T5]],[[T5]],0xffff -; MIPS32: and [[T2]],[[T2]],[[T5]] -; MIPS32: or [[T4]],[[T4]],[[T2]] -; MIPS32: srl [[T6:.*]],a1,0x18 -; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: srl [[T7:.*]],[[BV_E1]],0x18 -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T6]],[[T6]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sltu [[T6]],[[T6]],[[T7]] -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: and [[T4]],[[T4]],[[T5]] +; MIPS32: or [[T0]],[[T0]],[[T4]] +; MIPS32: srl [[T11:.*]],a1,0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: srl [[T1]],[[T1]],0x18 +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T11]],[[T11]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T11]],[[T11]],[[T1]] +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: sll [[T6]],[[T6]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T6]] +; MIPS32: move [[T1]],a2 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T4]],[[T2]] ; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T6]],[[T4]] -; MIPS32: andi [[T4]],a2,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E2]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T7]] ; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T8:.*]],[[TV_E2]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T8]] -; MIPS32: srl [[T7]],a2,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x8 +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T1]],[[T1]],[[T4]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: lui [[T4]],0xffff +; MIPS32: ori [[T4]],[[T4]],0xff +; MIPS32: and [[T0]],[[T0]],[[T4]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a2 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T4]],[[T2]] +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: andi [[T4]],[[T4]],0xff +; MIPS32: andi [[T4]],[[T4]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T4]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 +; MIPS32: lui [[T4]],0xff00 +; MIPS32: ori [[T4]],[[T4]],0xffff +; MIPS32: and [[T1]],[[T1]],[[T4]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T12:.*]],a2,0x18 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: sll [[T2]],[[T2]],0x1f +; MIPS32: sltu [[T12]],[[T12]],[[T2]] +; MIPS32: srl [[T12]],[[T12]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T1]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: sll [[T0]],[[T0]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f +; MIPS32: sltu [[T0]],[[T0]],[[T1]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: or [[T0]],[[T0]],[[T7]] +; MIPS32: move [[T1]],a3 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x8 ; MIPS32: andi [[T2]],[[T2]],0xff ; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f +; MIPS32: sll [[T1]],[[T1]],0x1f ; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T7]],[[T7]],[[T2]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 +; MIPS32: sltu [[T1]],[[T1]],[[T2]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x8 ; MIPS32: lui [[T2]],0xffff ; MIPS32: ori [[T2]],[[T2]],0xff -; MIPS32: and [[T4]],[[T4]],[[T2]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a2,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T2]],[[BV_E2]],0x10 +; MIPS32: and [[T0]],[[T0]],[[T2]] +; MIPS32: or [[T1]],[[T1]],[[T0]] +; MIPS32: move [[T0]],a3 +; MIPS32: srl [[T0]],[[T0]],0x10 +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: andi [[T0]],[[T0]],0x1 +; MIPS32: move [[T2]],[[T3]] +; MIPS32: srl [[T2]],[[T2]],0x10 ; MIPS32: andi [[T2]],[[T2]],0xff ; MIPS32: andi [[T2]],[[T2]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f +; MIPS32: sll [[T0]],[[T0]],0x1f ; MIPS32: sll [[T2]],[[T2]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T2]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: sltu [[T0]],[[T0]],[[T2]] +; MIPS32: andi [[T0]],[[T0]],0xff +; MIPS32: sll [[T0]],[[T0]],0x10 ; MIPS32: lui [[T2]],0xff00 ; MIPS32: ori [[T2]],[[T2]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T2]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T9:.*]],a2,0x18 -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: srl [[T10:.*]],[[BV_E2]],0x18 -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T9]],[[T9]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: sltu [[T9]],[[T9]],[[T10]] -; MIPS32: srl [[T9]],[[T9]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T9]],[[T4]] -; MIPS32: andi [[T4]],a3,0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: andi [[T7]],[[BV_E3]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T7]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: srl [[T11:.*]],[[TV_E3]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T4]],[[T4]],[[T11]] -; MIPS32: srl [[T7]],a3,0x8 -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x8 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T7]],[[T7]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: sltu [[T7]],[[T7]],[[T10]] -; MIPS32: andi [[T7]],[[T7]],0xff -; MIPS32: sll [[T7]],[[T7]],0x8 -; MIPS32: lui [[T10]],0xffff -; MIPS32: ori [[T10]],[[T10]],0xff -; MIPS32: and [[T4]],[[T4]],[[T10]] -; MIPS32: or [[T7]],[[T7]],[[T4]] -; MIPS32: srl [[T4]],a3,0x10 -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: srl [[T10]],[[BV_E3]],0x10 -; MIPS32: andi [[T10]],[[T10]],0xff -; MIPS32: andi [[T10]],[[T10]],0x1 -; MIPS32: sll [[T4]],[[T4]],0x1f -; MIPS32: sll [[T10]],[[T10]],0x1f -; MIPS32: sltu [[T4]],[[T4]],[[T10]] -; MIPS32: andi [[T4]],[[T4]],0xff -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: lui [[T10]],0xff00 -; MIPS32: ori [[T10]],[[T10]],0xffff -; MIPS32: and [[T7]],[[T7]],[[T10]] -; MIPS32: or [[T4]],[[T4]],[[T7]] -; MIPS32: srl [[T12:.*]],a3,0x18 -; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13:.*]],[[BV_E3]],0x18 +; MIPS32: and [[T1]],[[T1]],[[T2]] +; MIPS32: or [[T0]],[[T0]],[[T1]] +; MIPS32: srl [[T13:.*]],a3,0x18 ; MIPS32: andi [[T13]],[[T13]],0x1 -; MIPS32: sll [[T12]],[[T12]],0x1f +; MIPS32: srl [[T3]],[[T3]],0x18 +; MIPS32: andi [[T3]],[[T3]],0x1 ; MIPS32: sll [[T13]],[[T13]],0x1f -; MIPS32: sltu [[T12]],[[T12]],[[T13]] -; MIPS32: srl [[T12]],[[T12]],0x18 -; MIPS32: sll [[T4]],[[T4]],0x8 -; MIPS32: srl [[T4]],[[T4]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T12]],[[T4]] +; MIPS32: sll [[T3]],[[T3]],0x1f +; MIPS32: sltu [[T13]],[[T13]],[[T3]] +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T0]],[[T0]],0x8 +; MIPS32: srl [[T0]],[[T0]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T0]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] }
diff --git a/tests_lit/llvm2ice_tests/vector-select.ll b/tests_lit/llvm2ice_tests/vector-select.ll index d073938..0555ddf 100644 --- a/tests_lit/llvm2ice_tests/vector-select.ll +++ b/tests_lit/llvm2ice_tests/vector-select.ll
@@ -29,202 +29,254 @@ ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} ; MIPS32-LABEL: test_select_v16i8 -; MIPS32: lw [[T0:.*]],36(sp) -; MIPS32: lw [[T1:.*]],40(sp) -; MIPS32: lw [[T2:.*]],44(sp) -; MIPS32: lw [[T3:.*]],48(sp) -; MIPS32: lw [[T4:.*]],52(sp) -; MIPS32: lw [[T5:.*]],56(sp) -; MIPS32: lw [[T6:.*]],60(sp) -; MIPS32: lw [[T7:.*]],64(sp) -; MIPS32: move [[T8:.*]],zero -; MIPS32: move [[T9:.*]],zero -; MIPS32: move [[T10:.*]],zero -; MIPS32: move [[T11:.*]],zero -; MIPS32: andi [[T12:.*]],a0,0xff -; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: andi [[T13:.*]],[[T0]],0xff -; MIPS32: andi [[T14:.*]],[[T4]],0xff -; MIPS32: movn [[T14]],[[T13]],[[T12]] +; MIPS32: addiu [[T0:.*]],sp,-20 +; MIPS32: sw [[T1:.*]], +; MIPS32: sw [[T2:.*]], +; MIPS32: sw [[T3:.*]], +; MIPS32: sw [[T4:.*]], +; MIPS32: sw [[T5:.*]], +; MIPS32: lw [[T6:.*]], +; MIPS32: lw [[T7:.*]], +; MIPS32: lw [[T8:.*]], +; MIPS32: lw [[T9:.*]], +; MIPS32: lw [[T10:.*]], +; MIPS32: lw [[T11:.*]], +; MIPS32: lw [[T12:.*]], +; MIPS32: lw [[T13:.*]], +; MIPS32: move [[T14:.*]],zero +; MIPS32: move [[T15:.*]],zero +; MIPS32: move [[T5]],zero +; MIPS32: move [[T4]],zero +; MIPS32: move [[T3]],a0 +; MIPS32: andi [[T3]],[[T3]],0xff +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: move [[T2]],[[T6]] +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: move [[T1]],[[T10]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: movn [[T1]],[[T2]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: srl [[T14]],[[T14]],0x8 +; MIPS32: sll [[T14]],[[T14]],0x8 +; MIPS32: or [[T1]],[[T1]],[[T14]] +; MIPS32: move [[T14]],a0 +; MIPS32: srl [[T14]],[[T14]],0x8 ; MIPS32: andi [[T14]],[[T14]],0xff -; MIPS32: srl [[T8]],[[T8]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T14]],[[T14]],[[T8]] -; MIPS32: srl [[T8]],a0,0x8 -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: andi [[T8]],[[T8]],0x1 -; MIPS32: srl [[T12]],[[T0]],0x8 -; MIPS32: andi [[T12]],[[T12]],0xff -; MIPS32: srl [[T13]],[[T4]],0x8 -; MIPS32: andi [[T13]],[[T13]],0xff -; MIPS32: movn [[T13]],[[T12]],[[T8]] -; MIPS32: andi [[T13]],[[T13]],0xff -; MIPS32: sll [[T13]],[[T13]],0x8 -; MIPS32: lui [[T8]],0xffff -; MIPS32: ori [[T8]],[[T8]],0xff -; MIPS32: and [[T14]],[[T14]],[[T8]] -; MIPS32: or [[T13]],[[T13]],[[T14]] -; MIPS32: srl [[T8]],a0,0x10 -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: andi [[T8]],[[T8]],0x1 -; MIPS32: srl [[T12]],[[T0]],0x10 -; MIPS32: andi [[T12]],[[T12]],0xff -; MIPS32: srl [[T14]],[[T4]],0x10 +; MIPS32: andi [[T14]],[[T14]],0x1 +; MIPS32: move [[T3]],[[T6]] +; MIPS32: srl [[T3]],[[T3]],0x8 +; MIPS32: andi [[T3]],[[T3]],0xff +; MIPS32: move [[T2]],[[T10]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: movn [[T2]],[[T3]],[[T14]] +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T2]],[[T2]],0x8 +; MIPS32: lui [[T14]],0xffff +; MIPS32: ori [[T14]],[[T14]],0xff +; MIPS32: and [[T1]],[[T1]],[[T14]] +; MIPS32: or [[T2]],[[T2]],[[T1]] +; MIPS32: move [[T14]],a0 +; MIPS32: srl [[T14]],[[T14]],0x10 ; MIPS32: andi [[T14]],[[T14]],0xff -; MIPS32: movn [[T14]],[[T12]],[[T8]] +; MIPS32: andi [[T14]],[[T14]],0x1 +; MIPS32: move [[T3]],[[T6]] +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: andi [[T3]],[[T3]],0xff +; MIPS32: move [[T1]],[[T10]] +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: movn [[T1]],[[T3]],[[T14]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: lui [[T14]],0xff00 +; MIPS32: ori [[T14]],[[T14]],0xffff +; MIPS32: and [[T2]],[[T2]],[[T14]] +; MIPS32: or [[T1]],[[T1]],[[T2]] +; MIPS32: srl [[T16:.*]],a0,0x18 +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: srl [[T6]],[[T6]],0x18 +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: movn [[T10]],[[T6]],[[T16]] +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T1]] +; MIPS32: move [[T6]],a1 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T16]],[[T7]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: move [[T14]],[[T11]] +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: movn [[T14]],[[T16]],[[T6]] +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: srl [[T15]],[[T15]],0x8 +; MIPS32: sll [[T15]],[[T15]],0x8 +; MIPS32: or [[T14]],[[T14]],[[T15]] +; MIPS32: move [[T6]],a1 +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T16]],[[T7]] +; MIPS32: srl [[T16]],[[T16]],0x8 +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: move [[T15]],[[T11]] +; MIPS32: srl [[T15]],[[T15]],0x8 +; MIPS32: andi [[T15]],[[T15]],0xff +; MIPS32: movn [[T15]],[[T16]],[[T6]] +; MIPS32: andi [[T15]],[[T15]],0xff +; MIPS32: sll [[T15]],[[T15]],0x8 +; MIPS32: lui [[T6]],0xffff +; MIPS32: ori [[T6]],[[T6]],0xff +; MIPS32: and [[T14]],[[T14]],[[T6]] +; MIPS32: or [[T15]],[[T15]],[[T14]] +; MIPS32: move [[T6]],a1 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T16]],[[T7]] +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: move [[T14]],[[T11]] +; MIPS32: srl [[T14]],[[T14]],0x10 +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: movn [[T14]],[[T16]],[[T6]] ; MIPS32: andi [[T14]],[[T14]],0xff ; MIPS32: sll [[T14]],[[T14]],0x10 -; MIPS32: lui [[T8]],0xff00 -; MIPS32: ori [[T8]],[[T8]],0xffff -; MIPS32: and [[T13]],[[T13]],[[T8]] -; MIPS32: or [[T14]],[[T14]],[[T13]] -; MIPS32: srl [[T15:.*]],a0,0x18 -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: srl [[T0]],[[T0]],0x18 -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: movn [[T4]],[[T0]],[[T15]] -; MIPS32: srl [[T4]],[[T4]],0x18 +; MIPS32: lui [[T6]],0xff00 +; MIPS32: ori [[T6]],[[T6]],0xffff +; MIPS32: and [[T15]],[[T15]],[[T6]] +; MIPS32: or [[T14]],[[T14]],[[T15]] +; MIPS32: srl [[T17:.*]],a1,0x18 +; MIPS32: andi [[T17]],[[T17]],0x1 +; MIPS32: srl [[T7]],[[T7]],0x18 +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: movn [[T11]],[[T7]],[[T17]] +; MIPS32: srl [[T11]],[[T11]],0x18 ; MIPS32: sll [[T14]],[[T14]],0x8 ; MIPS32: srl [[T14]],[[T14]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] -; MIPS32: andi [[T0]],a1,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T15]],[[T1]],0xff -; MIPS32: andi [[T8]],[[T5]],0xff -; MIPS32: movn [[T8]],[[T15]],[[T0]] -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: srl [[T9]],[[T9]],0x8 -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: or [[T8]],[[T8]],[[T9]] -; MIPS32: srl [[T0]],a1,0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T15]],[[T1]],0x8 -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: srl [[T9]],[[T5]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: movn [[T9]],[[T15]],[[T0]] -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T0]],0xffff -; MIPS32: ori [[T0]],[[T0]],0xff -; MIPS32: and [[T8]],[[T8]],[[T0]] -; MIPS32: or [[T9]],[[T9]],[[T8]] -; MIPS32: srl [[T0]],a1,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T15]],[[T1]],0x10 -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: srl [[T8]],[[T5]],0x10 -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: movn [[T8]],[[T15]],[[T0]] -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: lui [[T0]],0xff00 -; MIPS32: ori [[T0]],[[T0]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T0]] -; MIPS32: or [[T8]],[[T8]],[[T9]] -; MIPS32: srl [[T16:.*]],a1,0x18 -; MIPS32: andi [[T16]],[[T16]],0x1 -; MIPS32: srl [[T1]],[[T1]],0x18 -; MIPS32: srl [[T5]],[[T5]],0x18 -; MIPS32: movn [[T5]],[[T1]],[[T16]] -; MIPS32: srl [[T5]],[[T5]],0x18 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: srl [[T8]],[[T8]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] -; MIPS32: andi [[T0]],a2,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1]],[[T2]],0xff -; MIPS32: andi [[T15]],[[T6]],0xff -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: srl [[T10]],[[T10]],0x8 -; MIPS32: sll [[T10]],[[T10]],0x8 -; MIPS32: or [[T15]],[[T15]],[[T10]] -; MIPS32: srl [[T0]],a2,0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[T2]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T16]],[[T6]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T14]] +; MIPS32: move [[T6]],a2 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T8]] +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: move [[T16]],[[T12]] ; MIPS32: andi [[T16]],[[T16]],0xff -; MIPS32: movn [[T16]],[[T1]],[[T0]] +; MIPS32: movn [[T16]],[[T7]],[[T6]] ; MIPS32: andi [[T16]],[[T16]],0xff -; MIPS32: sll [[T16]],[[T16]],0x8 -; MIPS32: lui [[T0]],0xffff -; MIPS32: ori [[T0]],[[T0]],0xff -; MIPS32: and [[T15]],[[T15]],[[T0]] -; MIPS32: or [[T16]],[[T16]],[[T15]] -; MIPS32: srl [[T0]],a2,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[T2]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T15]],[[T6]],0x10 -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: sll [[T15]],[[T15]],0x10 -; MIPS32: lui [[T0]],0xff00 -; MIPS32: ori [[T0]],[[T0]],0xffff -; MIPS32: and [[T16]],[[T16]],[[T0]] -; MIPS32: or [[T15]],[[T15]],[[T16]] -; MIPS32: srl [[T17:.*]],a2,0x18 -; MIPS32: andi [[T17]],[[T17]],0x1 -; MIPS32: srl [[T2]],[[T2]],0x18 -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: movn [[T6]],[[T2]],[[T17]] -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T15]],[[T15]],0x8 -; MIPS32: srl [[T15]],[[T15]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] -; MIPS32: andi [[T0]],a3,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1]],[[T3]],0xff -; MIPS32: andi [[T15]],[[T7]],0xff -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: srl [[T11]],[[T11]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T15]],[[T15]],[[T11]] -; MIPS32: srl [[T0]],a3,0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[T3]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T16]],[[T7]],0x8 +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T16]],[[T16]],[[T5]] +; MIPS32: move [[T6]],a2 +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T8]] +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: move [[T17]],[[T12]] +; MIPS32: srl [[T17]],[[T17]],0x8 +; MIPS32: andi [[T17]],[[T17]],0xff +; MIPS32: movn [[T17]],[[T7]],[[T6]] +; MIPS32: andi [[T17]],[[T17]],0xff +; MIPS32: sll [[T17]],[[T17]],0x8 +; MIPS32: lui [[T6]],0xffff +; MIPS32: ori [[T6]],[[T6]],0xff +; MIPS32: and [[T16]],[[T16]],[[T6]] +; MIPS32: or [[T17]],[[T17]],[[T16]] +; MIPS32: move [[T6]],a2 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T8]] +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: move [[T16]],[[T12]] +; MIPS32: srl [[T16]],[[T16]],0x10 ; MIPS32: andi [[T16]],[[T16]],0xff -; MIPS32: movn [[T16]],[[T1]],[[T0]] +; MIPS32: movn [[T16]],[[T7]],[[T6]] ; MIPS32: andi [[T16]],[[T16]],0xff -; MIPS32: sll [[T16]],[[T16]],0x8 -; MIPS32: lui [[T0]],0xffff -; MIPS32: ori [[T0]],[[T0]],0xff -; MIPS32: and [[T15]],[[T15]],[[T0]] -; MIPS32: or [[T16]],[[T16]],[[T15]] -; MIPS32: srl [[T0]],a3,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[T3]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: srl [[T15]],[[T7]],0x10 -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: sll [[T15]],[[T15]],0x10 -; MIPS32: lui [[T0]],0xff00 -; MIPS32: ori [[T0]],[[T0]],0xffff -; MIPS32: and [[T16]],[[T16]],[[T0]] -; MIPS32: or [[T15]],[[T15]],[[T16]] -; MIPS32: srl [[T18:.*]],a3,0x18 +; MIPS32: sll [[T16]],[[T16]],0x10 +; MIPS32: lui [[T6]],0xff00 +; MIPS32: ori [[T6]],[[T6]],0xffff +; MIPS32: and [[T17]],[[T17]],[[T6]] +; MIPS32: or [[T16]],[[T16]],[[T17]] +; MIPS32: srl [[T18:.*]],a2,0x18 ; MIPS32: andi [[T18]],[[T18]],0x1 -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: movn [[T7]],[[T3]],[[T18]] -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T15]],[[T15]],0x8 -; MIPS32: srl [[T15]],[[T15]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] +; MIPS32: srl [[T8]],[[T8]],0x18 +; MIPS32: srl [[T12]],[[T12]],0x18 +; MIPS32: movn [[T12]],[[T8]],[[T18]] +; MIPS32: srl [[T12]],[[T12]],0x18 +; MIPS32: sll [[T16]],[[T16]],0x8 +; MIPS32: srl [[T16]],[[T16]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T16]] +; MIPS32: move [[T6]],a3 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T9]] +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: move [[T16]],[[T13]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T16]],[[T16]],[[T4]] +; MIPS32: move [[T6]],a3 +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T9]] +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: move [[T17]],[[T13]] +; MIPS32: srl [[T17]],[[T17]],0x8 +; MIPS32: andi [[T17]],[[T17]],0xff +; MIPS32: movn [[T17]],[[T7]],[[T6]] +; MIPS32: andi [[T17]],[[T17]],0xff +; MIPS32: sll [[T17]],[[T17]],0x8 +; MIPS32: lui [[T6]],0xffff +; MIPS32: ori [[T6]],[[T6]],0xff +; MIPS32: and [[T16]],[[T16]],[[T6]] +; MIPS32: or [[T17]],[[T17]],[[T16]] +; MIPS32: move [[T6]],a3 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T9]] +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: move [[T16]],[[T13]] +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: sll [[T16]],[[T16]],0x10 +; MIPS32: lui [[T6]],0xff00 +; MIPS32: ori [[T6]],[[T6]],0xffff +; MIPS32: and [[T17]],[[T17]],[[T6]] +; MIPS32: or [[T16]],[[T16]],[[T17]] +; MIPS32: srl [[T19:.*]],a3,0x18 +; MIPS32: andi [[T19]],[[T19]],0x1 +; MIPS32: srl [[T9]],[[T9]],0x18 +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: movn [[T13]],[[T9]],[[T19]] +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T16]],[[T16]],0x8 +; MIPS32: srl [[T16]],[[T16]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T16]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] +; MIPS32: lw [[T5]], +; MIPS32: lw [[T4]], +; MIPS32: lw [[T3]], +; MIPS32: lw [[T2]], +; MIPS32: lw [[T1]], +; MIPS32: addiu [[T0]],sp,20 } define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1, @@ -241,234 +293,286 @@ ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} ; MIPS32-LABEL: test_select_v16i1 -; MIPS32: lw [[T0:.*]],36(sp) -; MIPS32: lw [[T1:.*]],40(sp) -; MIPS32: lw [[T2:.*]],44(sp) -; MIPS32: lw [[T3:.*]],48(sp) -; MIPS32: lw [[T4:.*]],52(sp) -; MIPS32: lw [[T5:.*]],56(sp) -; MIPS32: lw [[T6:.*]],60(sp) -; MIPS32: lw [[T7:.*]],64(sp) -; MIPS32: move [[T8:.*]],zero -; MIPS32: move [[T9:.*]],zero -; MIPS32: move [[T10:.*]],zero -; MIPS32: move [[T11:.*]],zero -; MIPS32: andi [[T12:.*]],a0,0xff -; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: andi [[T13:.*]],[[T0]],0xff -; MIPS32: andi [[T13]],[[T13]],0x1 -; MIPS32: andi [[T14:.*]],[[T4]],0xff -; MIPS32: andi [[T14]],[[T14]],0x1 -; MIPS32: movn [[T14]],[[T13]],[[T12]] -; MIPS32: andi [[T14]],[[T14]],0xff -; MIPS32: srl [[T8]],[[T8]],0x8 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: or [[T14]],[[T14]],[[T8]] -; MIPS32: srl [[T8]],a0,0x8 -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: andi [[T8]],[[T8]],0x1 -; MIPS32: srl [[T12]],[[T0]],0x8 -; MIPS32: andi [[T12]],[[T12]],0xff -; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T13]],[[T4]],0x8 -; MIPS32: andi [[T13]],[[T13]],0xff -; MIPS32: andi [[T13]],[[T13]],0x1 -; MIPS32: movn [[T13]],[[T12]],[[T8]] -; MIPS32: andi [[T13]],[[T13]],0xff -; MIPS32: sll [[T13]],[[T13]],0x8 -; MIPS32: lui [[T8]],0xffff -; MIPS32: ori [[T8]],[[T8]],0xff -; MIPS32: and [[T14]],[[T14]],[[T8]] -; MIPS32: or [[T13]],[[T13]],[[T14]] -; MIPS32: srl [[T8]],a0,0x10 -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: andi [[T8]],[[T8]],0x1 -; MIPS32: srl [[T12]],[[T0]],0x10 -; MIPS32: andi [[T12]],[[T12]],0xff -; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: srl [[T14]],[[T4]],0x10 -; MIPS32: andi [[T14]],[[T14]],0xff -; MIPS32: andi [[T14]],[[T14]],0x1 -; MIPS32: movn [[T14]],[[T12]],[[T8]] -; MIPS32: andi [[T14]],[[T14]],0xff -; MIPS32: sll [[T14]],[[T14]],0x10 -; MIPS32: lui [[T8]],0xff00 -; MIPS32: ori [[T8]],[[T8]],0xffff -; MIPS32: and [[T13]],[[T13]],[[T8]] -; MIPS32: or [[T14]],[[T14]],[[T13]] -; MIPS32: srl [[T15:.*]],a0,0x18 -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: srl [[T0]],[[T0]],0x18 -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: movn [[T4]],[[T0]],[[T15]] -; MIPS32: srl [[T4]],[[T4]],0x18 -; MIPS32: sll [[T14]],[[T14]],0x8 -; MIPS32: srl [[T14]],[[T14]],0x8 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] -; MIPS32: andi [[T0]],a1,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T15]],[[T1]],0xff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: andi [[T8]],[[T5]],0xff -; MIPS32: andi [[T8]],[[T8]],0x1 -; MIPS32: movn [[T8]],[[T15]],[[T0]] -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: srl [[T9]],[[T9]],0x8 -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: or [[T8]],[[T8]],[[T9]] -; MIPS32: srl [[T0]],a1,0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T15]],[[T1]],0x8 -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: srl [[T9]],[[T5]],0x8 -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: andi [[T9]],[[T9]],0x1 -; MIPS32: movn [[T9]],[[T15]],[[T0]] -; MIPS32: andi [[T9]],[[T9]],0xff -; MIPS32: sll [[T9]],[[T9]],0x8 -; MIPS32: lui [[T0]],0xffff -; MIPS32: ori [[T0]],[[T0]],0xff -; MIPS32: and [[T8]],[[T8]],[[T0]] -; MIPS32: or [[T9]],[[T9]],[[T8]] -; MIPS32: srl [[T0]],a1,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T15]],[[T1]],0x10 -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: srl [[T8]],[[T5]],0x10 -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: andi [[T8]],[[T8]],0x1 -; MIPS32: movn [[T8]],[[T15]],[[T0]] -; MIPS32: andi [[T8]],[[T8]],0xff -; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: lui [[T0]],0xff00 -; MIPS32: ori [[T0]],[[T0]],0xffff -; MIPS32: and [[T9]],[[T9]],[[T0]] -; MIPS32: or [[T8]],[[T8]],[[T9]] -; MIPS32: srl [[T16:.*]],a1,0x18 -; MIPS32: andi [[T16]],[[T16]],0x1 -; MIPS32: srl [[T1]],[[T1]],0x18 -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: srl [[T5]],[[T5]],0x18 -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: movn [[T5]],[[T1]],[[T16]] -; MIPS32: srl [[T5]],[[T5]],0x18 -; MIPS32: sll [[T8]],[[T8]],0x8 -; MIPS32: srl [[T8]],[[T8]],0x8 -; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] -; MIPS32: andi [[T0]],a2,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1]],[[T2]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T15]],[[T6]],0xff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: srl [[T10]],[[T10]],0x8 -; MIPS32: sll [[T10]],[[T10]],0x8 -; MIPS32: or [[T15]],[[T15]],[[T10]] -; MIPS32: srl [[T0]],a2,0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[T2]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: srl [[T16]],[[T6]],0x8 -; MIPS32: andi [[T16]],[[T16]],0xff -; MIPS32: andi [[T16]],[[T16]],0x1 -; MIPS32: movn [[T16]],[[T1]],[[T0]] -; MIPS32: andi [[T16]],[[T16]],0xff -; MIPS32: sll [[T16]],[[T16]],0x8 -; MIPS32: lui [[T0]],0xffff -; MIPS32: ori [[T0]],[[T0]],0xff -; MIPS32: and [[T15]],[[T15]],[[T0]] -; MIPS32: or [[T16]],[[T16]],[[T15]] -; MIPS32: srl [[T0]],a2,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[T2]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: srl [[T15]],[[T6]],0x10 -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: sll [[T15]],[[T15]],0x10 -; MIPS32: lui [[T0]],0xff00 -; MIPS32: ori [[T0]],[[T0]],0xffff -; MIPS32: and [[T16]],[[T16]],[[T0]] -; MIPS32: or [[T15]],[[T15]],[[T16]] -; MIPS32: srl [[T17:.*]],a2,0x18 -; MIPS32: andi [[T17]],[[T17]],0x1 -; MIPS32: srl [[T2]],[[T2]],0x18 +; MIPS32: addiu [[T0:.*]],sp,-20 +; MIPS32: sw [[T1:.*]], +; MIPS32: sw [[T2:.*]], +; MIPS32: sw [[T3:.*]], +; MIPS32: sw [[T4:.*]], +; MIPS32: sw [[T5:.*]], +; MIPS32: lw [[T6:.*]], +; MIPS32: lw [[T7:.*]], +; MIPS32: lw [[T8:.*]], +; MIPS32: lw [[T9:.*]], +; MIPS32: lw [[T10:.*]], +; MIPS32: lw [[T11:.*]], +; MIPS32: lw [[T12:.*]], +; MIPS32: lw [[T13:.*]], +; MIPS32: move [[T14:.*]],zero +; MIPS32: move [[T15:.*]],zero +; MIPS32: move [[T5]],zero +; MIPS32: move [[T4]],zero +; MIPS32: move [[T3]],a0 +; MIPS32: andi [[T3]],[[T3]],0xff +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: move [[T2]],[[T6]] +; MIPS32: andi [[T2]],[[T2]],0xff ; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: move [[T1]],[[T10]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: movn [[T1]],[[T2]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: srl [[T14]],[[T14]],0x8 +; MIPS32: sll [[T14]],[[T14]],0x8 +; MIPS32: or [[T1]],[[T1]],[[T14]] +; MIPS32: move [[T14]],a0 +; MIPS32: srl [[T14]],[[T14]],0x8 +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: andi [[T14]],[[T14]],0x1 +; MIPS32: move [[T3]],[[T6]] +; MIPS32: srl [[T3]],[[T3]],0x8 +; MIPS32: andi [[T3]],[[T3]],0xff +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: move [[T2]],[[T10]] +; MIPS32: srl [[T2]],[[T2]],0x8 +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: movn [[T2]],[[T3]],[[T14]] +; MIPS32: andi [[T2]],[[T2]],0xff +; MIPS32: sll [[T2]],[[T2]],0x8 +; MIPS32: lui [[T14]],0xffff +; MIPS32: ori [[T14]],[[T14]],0xff +; MIPS32: and [[T1]],[[T1]],[[T14]] +; MIPS32: or [[T2]],[[T2]],[[T1]] +; MIPS32: move [[T14]],a0 +; MIPS32: srl [[T14]],[[T14]],0x10 +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: andi [[T14]],[[T14]],0x1 +; MIPS32: move [[T3]],[[T6]] +; MIPS32: srl [[T3]],[[T3]],0x10 +; MIPS32: andi [[T3]],[[T3]],0xff +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: move [[T1]],[[T10]] +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: movn [[T1]],[[T3]],[[T14]] +; MIPS32: andi [[T1]],[[T1]],0xff +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: lui [[T14]],0xff00 +; MIPS32: ori [[T14]],[[T14]],0xffff +; MIPS32: and [[T2]],[[T2]],[[T14]] +; MIPS32: or [[T1]],[[T1]],[[T2]] +; MIPS32: srl [[T16:.*]],a0,0x18 +; MIPS32: andi [[T16]],[[T16]],0x1 ; MIPS32: srl [[T6]],[[T6]],0x18 ; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: movn [[T6]],[[T2]],[[T17]] -; MIPS32: srl [[T6]],[[T6]],0x18 -; MIPS32: sll [[T15]],[[T15]],0x8 -; MIPS32: srl [[T15]],[[T15]],0x8 -; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] -; MIPS32: andi [[T0]],a3,0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1]],[[T3]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T15]],[[T7]],0xff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: srl [[T11]],[[T11]],0x8 -; MIPS32: sll [[T11]],[[T11]],0x8 -; MIPS32: or [[T15]],[[T15]],[[T11]] -; MIPS32: srl [[T0]],a3,0x8 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[T3]],0x8 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: srl [[T16]],[[T7]],0x8 +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: movn [[T10]],[[T6]],[[T16]] +; MIPS32: srl [[T10]],[[T10]],0x18 +; MIPS32: sll [[T1]],[[T1]],0x8 +; MIPS32: srl [[T1]],[[T1]],0x8 +; MIPS32: or [[T10]],[[T10]],[[T1]] +; MIPS32: move [[T6]],a1 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T16]],[[T7]] ; MIPS32: andi [[T16]],[[T16]],0xff ; MIPS32: andi [[T16]],[[T16]],0x1 -; MIPS32: movn [[T16]],[[T1]],[[T0]] +; MIPS32: move [[T14]],[[T11]] +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: andi [[T14]],[[T14]],0x1 +; MIPS32: movn [[T14]],[[T16]],[[T6]] +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: srl [[T15]],[[T15]],0x8 +; MIPS32: sll [[T15]],[[T15]],0x8 +; MIPS32: or [[T14]],[[T14]],[[T15]] +; MIPS32: move [[T6]],a1 +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T16]],[[T7]] +; MIPS32: srl [[T16]],[[T16]],0x8 ; MIPS32: andi [[T16]],[[T16]],0xff -; MIPS32: sll [[T16]],[[T16]],0x8 -; MIPS32: lui [[T0]],0xffff -; MIPS32: ori [[T0]],[[T0]],0xff -; MIPS32: and [[T15]],[[T15]],[[T0]] -; MIPS32: or [[T16]],[[T16]],[[T15]] -; MIPS32: srl [[T0]],a3,0x10 -; MIPS32: andi [[T0]],[[T0]],0xff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T1]],[[T3]],0x10 -; MIPS32: andi [[T1]],[[T1]],0xff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: srl [[T15]],[[T7]],0x10 +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: move [[T15]],[[T11]] +; MIPS32: srl [[T15]],[[T15]],0x8 ; MIPS32: andi [[T15]],[[T15]],0xff ; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: movn [[T15]],[[T1]],[[T0]] +; MIPS32: movn [[T15]],[[T16]],[[T6]] ; MIPS32: andi [[T15]],[[T15]],0xff -; MIPS32: sll [[T15]],[[T15]],0x10 -; MIPS32: lui [[T0]],0xff00 -; MIPS32: ori [[T0]],[[T0]],0xffff -; MIPS32: and [[T16]],[[T16]],[[T0]] -; MIPS32: or [[T15]],[[T15]],[[T16]] -; MIPS32: srl [[T18:.*]],a3,0x18 -; MIPS32: andi [[T18]],[[T18]],0x1 -; MIPS32: srl [[T3]],[[T3]],0x18 -; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T15]],[[T15]],0x8 +; MIPS32: lui [[T6]],0xffff +; MIPS32: ori [[T6]],[[T6]],0xff +; MIPS32: and [[T14]],[[T14]],[[T6]] +; MIPS32: or [[T15]],[[T15]],[[T14]] +; MIPS32: move [[T6]],a1 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T16]],[[T7]] +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: move [[T14]],[[T11]] +; MIPS32: srl [[T14]],[[T14]],0x10 +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: andi [[T14]],[[T14]],0x1 +; MIPS32: movn [[T14]],[[T16]],[[T6]] +; MIPS32: andi [[T14]],[[T14]],0xff +; MIPS32: sll [[T14]],[[T14]],0x10 +; MIPS32: lui [[T6]],0xff00 +; MIPS32: ori [[T6]],[[T6]],0xffff +; MIPS32: and [[T15]],[[T15]],[[T6]] +; MIPS32: or [[T14]],[[T14]],[[T15]] +; MIPS32: srl [[T17:.*]],a1,0x18 +; MIPS32: andi [[T17]],[[T17]],0x1 ; MIPS32: srl [[T7]],[[T7]],0x18 ; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: movn [[T7]],[[T3]],[[T18]] -; MIPS32: srl [[T7]],[[T7]],0x18 -; MIPS32: sll [[T15]],[[T15]],0x8 -; MIPS32: srl [[T15]],[[T15]],0x8 -; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: movn [[T11]],[[T7]],[[T17]] +; MIPS32: srl [[T11]],[[T11]],0x18 +; MIPS32: sll [[T14]],[[T14]],0x8 +; MIPS32: srl [[T14]],[[T14]],0x8 +; MIPS32: or [[T11]],[[T11]],[[T14]] +; MIPS32: move [[T6]],a2 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T8]] +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: move [[T16]],[[T12]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: srl [[T5]],[[T5]],0x8 +; MIPS32: sll [[T5]],[[T5]],0x8 +; MIPS32: or [[T16]],[[T16]],[[T5]] +; MIPS32: move [[T6]],a2 +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T8]] +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: move [[T17]],[[T12]] +; MIPS32: srl [[T17]],[[T17]],0x8 +; MIPS32: andi [[T17]],[[T17]],0xff +; MIPS32: andi [[T17]],[[T17]],0x1 +; MIPS32: movn [[T17]],[[T7]],[[T6]] +; MIPS32: andi [[T17]],[[T17]],0xff +; MIPS32: sll [[T17]],[[T17]],0x8 +; MIPS32: lui [[T6]],0xffff +; MIPS32: ori [[T6]],[[T6]],0xff +; MIPS32: and [[T16]],[[T16]],[[T6]] +; MIPS32: or [[T17]],[[T17]],[[T16]] +; MIPS32: move [[T6]],a2 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T8]] +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: move [[T16]],[[T12]] +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: sll [[T16]],[[T16]],0x10 +; MIPS32: lui [[T6]],0xff00 +; MIPS32: ori [[T6]],[[T6]],0xffff +; MIPS32: and [[T17]],[[T17]],[[T6]] +; MIPS32: or [[T16]],[[T16]],[[T17]] +; MIPS32: srl [[T18:.*]],a2,0x18 +; MIPS32: andi [[T18]],[[T18]],0x1 +; MIPS32: srl [[T8]],[[T8]],0x18 +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: srl [[T12]],[[T12]],0x18 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: movn [[T12]],[[T8]],[[T18]] +; MIPS32: srl [[T12]],[[T12]],0x18 +; MIPS32: sll [[T16]],[[T16]],0x8 +; MIPS32: srl [[T16]],[[T16]],0x8 +; MIPS32: or [[T12]],[[T12]],[[T16]] +; MIPS32: move [[T6]],a3 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T9]] +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: move [[T16]],[[T13]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: srl [[T4]],[[T4]],0x8 +; MIPS32: sll [[T4]],[[T4]],0x8 +; MIPS32: or [[T16]],[[T16]],[[T4]] +; MIPS32: move [[T6]],a3 +; MIPS32: srl [[T6]],[[T6]],0x8 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T9]] +; MIPS32: srl [[T7]],[[T7]],0x8 +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: move [[T17]],[[T13]] +; MIPS32: srl [[T17]],[[T17]],0x8 +; MIPS32: andi [[T17]],[[T17]],0xff +; MIPS32: andi [[T17]],[[T17]],0x1 +; MIPS32: movn [[T17]],[[T7]],[[T6]] +; MIPS32: andi [[T17]],[[T17]],0xff +; MIPS32: sll [[T17]],[[T17]],0x8 +; MIPS32: lui [[T6]],0xffff +; MIPS32: ori [[T6]],[[T6]],0xff +; MIPS32: and [[T16]],[[T16]],[[T6]] +; MIPS32: or [[T17]],[[T17]],[[T16]] +; MIPS32: move [[T6]],a3 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: andi [[T6]],[[T6]],0xff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T9]] +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: andi [[T7]],[[T7]],0xff +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: move [[T16]],[[T13]] +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xff +; MIPS32: sll [[T16]],[[T16]],0x10 +; MIPS32: lui [[T6]],0xff00 +; MIPS32: ori [[T6]],[[T6]],0xffff +; MIPS32: and [[T17]],[[T17]],[[T6]] +; MIPS32: or [[T16]],[[T16]],[[T17]] +; MIPS32: srl [[T19:.*]],a3,0x18 +; MIPS32: andi [[T19]],[[T19]],0x1 +; MIPS32: srl [[T9]],[[T9]],0x18 +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: movn [[T13]],[[T9]],[[T19]] +; MIPS32: srl [[T13]],[[T13]],0x18 +; MIPS32: sll [[T16]],[[T16]],0x8 +; MIPS32: srl [[T16]],[[T16]],0x8 +; MIPS32: or [[T13]],[[T13]],[[T16]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] +; MIPS32: lw [[T5]], +; MIPS32: lw [[T4]], +; MIPS32: lw [[T3]], +; MIPS32: lw [[T2]], +; MIPS32: lw [[T1]], +; MIPS32: addiu [[T0]],sp,20 } define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1, @@ -485,90 +589,118 @@ ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} ; MIPS32-LABEL: test_select_v8i16 -; MIPS32: lw [[T0:.*]],36(sp) -; MIPS32: lw [[T1:.*]],40(sp) -; MIPS32: lw [[T2:.*]],44(sp) -; MIPS32: lw [[T3:.*]],48(sp) -; MIPS32: lw [[T4:.*]],52(sp) -; MIPS32: lw [[T5:.*]],56(sp) -; MIPS32: lw [[T6:.*]],60(sp) -; MIPS32: lw [[T7:.*]],64(sp) -; MIPS32: move [[T8:.*]],zero -; MIPS32: move [[T9:.*]],zero -; MIPS32: move [[T10:.*]],zero -; MIPS32: move [[T11:.*]],zero -; MIPS32: andi [[T12:.*]],a0,0xffff -; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: andi [[T13:.*]],[[T0]],0xffff -; MIPS32: andi [[T14:.*]],[[T4]],0xffff -; MIPS32: movn [[T14]],[[T13]],[[T12]] +; MIPS32: addiu [[T0:.*]],sp,-20 +; MIPS32: sw [[T1:.*]], +; MIPS32: sw [[T2:.*]], +; MIPS32: sw [[T3:.*]], +; MIPS32: sw [[T4:.*]], +; MIPS32: sw [[T5:.*]], +; MIPS32: lw [[T6:.*]], +; MIPS32: lw [[T7:.*]], +; MIPS32: lw [[T8:.*]], +; MIPS32: lw [[T9:.*]], +; MIPS32: lw [[T10:.*]], +; MIPS32: lw [[T11:.*]], +; MIPS32: lw [[T12:.*]], +; MIPS32: lw [[T13:.*]], +; MIPS32: move [[T14:.*]],zero +; MIPS32: move [[T15:.*]],zero +; MIPS32: move [[T5]],zero +; MIPS32: move [[T4]],zero +; MIPS32: move [[T3]],a0 +; MIPS32: andi [[T3]],[[T3]],0xffff +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: move [[T2]],[[T6]] +; MIPS32: andi [[T2]],[[T2]],0xffff +; MIPS32: move [[T1]],[[T10]] +; MIPS32: andi [[T1]],[[T1]],0xffff +; MIPS32: movn [[T1]],[[T2]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xffff +; MIPS32: srl [[T14]],[[T14]],0x10 +; MIPS32: sll [[T14]],[[T14]],0x10 +; MIPS32: or [[T1]],[[T1]],[[T14]] +; MIPS32: srl [[T16:.*]],a0,0x10 +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: srl [[T6]],[[T6]],0x10 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: movn [[T10]],[[T6]],[[T16]] +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T1]] +; MIPS32: move [[T6]],a1 +; MIPS32: andi [[T6]],[[T6]],0xffff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T16]],[[T7]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: move [[T14]],[[T11]] ; MIPS32: andi [[T14]],[[T14]],0xffff -; MIPS32: srl [[T8]],[[T8]],0x10 -; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: or [[T14]],[[T14]],[[T8]] -; MIPS32: srl [[T15:.*]],a0,0x10 -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: srl [[T4]],[[T4]],0x10 -; MIPS32: movn [[T4]],[[T0]],[[T15]] -; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: movn [[T14]],[[T16]],[[T6]] +; MIPS32: andi [[T14]],[[T14]],0xffff +; MIPS32: srl [[T15]],[[T15]],0x10 +; MIPS32: sll [[T15]],[[T15]],0x10 +; MIPS32: or [[T14]],[[T14]],[[T15]] +; MIPS32: srl [[T17:.*]],a1,0x10 +; MIPS32: andi [[T17]],[[T17]],0x1 +; MIPS32: srl [[T7]],[[T7]],0x10 +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: movn [[T11]],[[T7]],[[T17]] +; MIPS32: sll [[T11]],[[T11]],0x10 ; MIPS32: sll [[T14]],[[T14]],0x10 ; MIPS32: srl [[T14]],[[T14]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] -; MIPS32: andi [[T0]],a1,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T15]],[[T1]],0xffff -; MIPS32: andi [[T8]],[[T5]],0xffff -; MIPS32: movn [[T8]],[[T15]],[[T0]] -; MIPS32: andi [[T8]],[[T8]],0xffff -; MIPS32: srl [[T9]],[[T9]],0x10 -; MIPS32: sll [[T9]],[[T9]],0x10 -; MIPS32: or [[T8]],[[T8]],[[T9]] -; MIPS32: srl [[T16:.*]],a1,0x10 -; MIPS32: andi [[T16]],[[T16]],0x1 -; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T14]] +; MIPS32: move [[T6]],a2 +; MIPS32: andi [[T6]],[[T6]],0xffff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T8]] +; MIPS32: andi [[T7]],[[T7]],0xffff +; MIPS32: move [[T16]],[[T12]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xffff ; MIPS32: srl [[T5]],[[T5]],0x10 -; MIPS32: movn [[T5]],[[T1]],[[T16]] ; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: srl [[T8]],[[T8]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] -; MIPS32: andi [[T0]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1]],[[T2]],0xffff -; MIPS32: andi [[T15]],[[T6]],0xffff -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xffff -; MIPS32: srl [[T10]],[[T10]],0x10 -; MIPS32: sll [[T10]],[[T10]],0x10 -; MIPS32: or [[T15]],[[T15]],[[T10]] -; MIPS32: srl [[T17:.*]],a2,0x10 -; MIPS32: andi [[T17]],[[T17]],0x1 -; MIPS32: srl [[T2]],[[T2]],0x10 -; MIPS32: srl [[T6]],[[T6]],0x10 -; MIPS32: movn [[T6]],[[T2]],[[T17]] -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: sll [[T15]],[[T15]],0x10 -; MIPS32: srl [[T15]],[[T15]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] -; MIPS32: andi [[T0]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1]],[[T3]],0xffff -; MIPS32: andi [[T15]],[[T7]],0xffff -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xffff -; MIPS32: srl [[T11]],[[T11]],0x10 -; MIPS32: sll [[T11]],[[T11]],0x10 -; MIPS32: or [[T15]],[[T15]],[[T11]] -; MIPS32: srl [[T18:.*]],a3,0x10 +; MIPS32: or [[T16]],[[T16]],[[T5]] +; MIPS32: srl [[T18:.*]],a2,0x10 ; MIPS32: andi [[T18]],[[T18]],0x1 -; MIPS32: srl [[T3]],[[T3]],0x10 -; MIPS32: srl [[T7]],[[T7]],0x10 -; MIPS32: movn [[T7]],[[T3]],[[T18]] -; MIPS32: sll [[T7]],[[T7]],0x10 -; MIPS32: sll [[T15]],[[T15]],0x10 -; MIPS32: srl [[T15]],[[T15]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: srl [[T12]],[[T12]],0x10 +; MIPS32: movn [[T12]],[[T8]],[[T18]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T16]],[[T16]],0x10 +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T16]] +; MIPS32: move [[T6]],a3 +; MIPS32: andi [[T6]],[[T6]],0xffff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T9]] +; MIPS32: andi [[T7]],[[T7]],0xffff +; MIPS32: move [[T16]],[[T13]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T16]],[[T16]],[[T4]] +; MIPS32: srl [[T19:.*]],a3,0x10 +; MIPS32: andi [[T19]],[[T19]],0x1 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: srl [[T13]],[[T13]],0x10 +; MIPS32: movn [[T13]],[[T9]],[[T19]] +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T16]],[[T16]],0x10 +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T16]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] +; MIPS32: lw [[T5]], +; MIPS32: lw [[T4]], +; MIPS32: lw [[T3]], +; MIPS32: lw [[T2]], +; MIPS32: lw [[T1]], +; MIPS32: addiu [[T0]],sp,20 } define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1, @@ -585,106 +717,134 @@ ; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} ; MIPS32-LABEL: test_select_v8i1 -; MIPS32: lw [[T0:.*]],36(sp) -; MIPS32: lw [[T1:.*]],40(sp) -; MIPS32: lw [[T2:.*]],44(sp) -; MIPS32: lw [[T3:.*]],48(sp) -; MIPS32: lw [[T4:.*]],52(sp) -; MIPS32: lw [[T5:.*]],56(sp) -; MIPS32: lw [[T6:.*]],60(sp) -; MIPS32: lw [[T7:.*]],64(sp) -; MIPS32: move [[T8:.*]],zero -; MIPS32: move [[T9:.*]],zero -; MIPS32: move [[T10:.*]],zero -; MIPS32: move [[T11:.*]],zero -; MIPS32: andi [[T12:.*]],a0,0xffff -; MIPS32: andi [[T12]],[[T12]],0x1 -; MIPS32: andi [[T13:.*]],[[T0]],0xffff -; MIPS32: andi [[T13]],[[T13]],0x1 -; MIPS32: andi [[T14:.*]],[[T4]],0xffff -; MIPS32: andi [[T14]],[[T14]],0x1 -; MIPS32: movn [[T14]],[[T13]],[[T12]] -; MIPS32: andi [[T14]],[[T14]],0xffff -; MIPS32: srl [[T8]],[[T8]],0x10 -; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: or [[T14]],[[T14]],[[T8]] -; MIPS32: srl [[T15:.*]],a0,0x10 -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: srl [[T0]],[[T0]],0x10 -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: srl [[T4]],[[T4]],0x10 -; MIPS32: andi [[T4]],[[T4]],0x1 -; MIPS32: movn [[T4]],[[T0]],[[T15]] -; MIPS32: sll [[T4]],[[T4]],0x10 -; MIPS32: sll [[T14]],[[T14]],0x10 -; MIPS32: srl [[T14]],[[T14]],0x10 -; MIPS32: or [[RV_E0:.*]],[[T4]],[[T14]] -; MIPS32: andi [[T0]],a1,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T15]],[[T1]],0xffff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: andi [[T8]],[[T5]],0xffff -; MIPS32: andi [[T8]],[[T8]],0x1 -; MIPS32: movn [[T8]],[[T15]],[[T0]] -; MIPS32: andi [[T8]],[[T8]],0xffff -; MIPS32: srl [[T9]],[[T9]],0x10 -; MIPS32: sll [[T9]],[[T9]],0x10 -; MIPS32: or [[T8]],[[T8]],[[T9]] -; MIPS32: srl [[T16:.*]],a1,0x10 -; MIPS32: andi [[T16]],[[T16]],0x1 -; MIPS32: srl [[T1]],[[T1]],0x10 -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: srl [[T5]],[[T5]],0x10 -; MIPS32: andi [[T5]],[[T5]],0x1 -; MIPS32: movn [[T5]],[[T1]],[[T16]] -; MIPS32: sll [[T5]],[[T5]],0x10 -; MIPS32: sll [[T8]],[[T8]],0x10 -; MIPS32: srl [[T8]],[[T8]],0x10 -; MIPS32: or [[RV_E1:.*]],[[T5]],[[T8]] -; MIPS32: andi [[T0]],a2,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1]],[[T2]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T15]],[[T6]],0xffff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xffff -; MIPS32: srl [[T10]],[[T10]],0x10 -; MIPS32: sll [[T10]],[[T10]],0x10 -; MIPS32: or [[T15]],[[T15]],[[T10]] -; MIPS32: srl [[T17:.*]],a2,0x10 -; MIPS32: andi [[T17]],[[T17]],0x1 -; MIPS32: srl [[T2]],[[T2]],0x10 +; MIPS32: addiu [[T0:.*]],sp,-20 +; MIPS32: sw [[T1:.*]], +; MIPS32: sw [[T2:.*]], +; MIPS32: sw [[T3:.*]], +; MIPS32: sw [[T4:.*]], +; MIPS32: sw [[T5:.*]], +; MIPS32: lw [[T6:.*]], +; MIPS32: lw [[T7:.*]], +; MIPS32: lw [[T8:.*]], +; MIPS32: lw [[T9:.*]], +; MIPS32: lw [[T10:.*]], +; MIPS32: lw [[T11:.*]], +; MIPS32: lw [[T12:.*]], +; MIPS32: lw [[T13:.*]], +; MIPS32: move [[T14:.*]],zero +; MIPS32: move [[T15:.*]],zero +; MIPS32: move [[T5]],zero +; MIPS32: move [[T4]],zero +; MIPS32: move [[T3]],a0 +; MIPS32: andi [[T3]],[[T3]],0xffff +; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: move [[T2]],[[T6]] +; MIPS32: andi [[T2]],[[T2]],0xffff ; MIPS32: andi [[T2]],[[T2]],0x1 +; MIPS32: move [[T1]],[[T10]] +; MIPS32: andi [[T1]],[[T1]],0xffff +; MIPS32: andi [[T1]],[[T1]],0x1 +; MIPS32: movn [[T1]],[[T2]],[[T3]] +; MIPS32: andi [[T1]],[[T1]],0xffff +; MIPS32: srl [[T14]],[[T14]],0x10 +; MIPS32: sll [[T14]],[[T14]],0x10 +; MIPS32: or [[T1]],[[T1]],[[T14]] +; MIPS32: srl [[T16:.*]],a0,0x10 +; MIPS32: andi [[T16]],[[T16]],0x1 ; MIPS32: srl [[T6]],[[T6]],0x10 ; MIPS32: andi [[T6]],[[T6]],0x1 -; MIPS32: movn [[T6]],[[T2]],[[T17]] -; MIPS32: sll [[T6]],[[T6]],0x10 -; MIPS32: sll [[T15]],[[T15]],0x10 +; MIPS32: srl [[T10]],[[T10]],0x10 +; MIPS32: andi [[T10]],[[T10]],0x1 +; MIPS32: movn [[T10]],[[T6]],[[T16]] +; MIPS32: sll [[T10]],[[T10]],0x10 +; MIPS32: sll [[T1]],[[T1]],0x10 +; MIPS32: srl [[T1]],[[T1]],0x10 +; MIPS32: or [[T10]],[[T10]],[[T1]] +; MIPS32: move [[T6]],a1 +; MIPS32: andi [[T6]],[[T6]],0xffff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T16]],[[T7]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: move [[T14]],[[T11]] +; MIPS32: andi [[T14]],[[T14]],0xffff +; MIPS32: andi [[T14]],[[T14]],0x1 +; MIPS32: movn [[T14]],[[T16]],[[T6]] +; MIPS32: andi [[T14]],[[T14]],0xffff ; MIPS32: srl [[T15]],[[T15]],0x10 -; MIPS32: or [[RV_E2:.*]],[[T6]],[[T15]] -; MIPS32: andi [[T0]],a3,0xffff -; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: andi [[T1]],[[T3]],0xffff -; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: andi [[T15]],[[T7]],0xffff -; MIPS32: andi [[T15]],[[T15]],0x1 -; MIPS32: movn [[T15]],[[T1]],[[T0]] -; MIPS32: andi [[T15]],[[T15]],0xffff -; MIPS32: srl [[T11]],[[T11]],0x10 -; MIPS32: sll [[T11]],[[T11]],0x10 -; MIPS32: or [[T15]],[[T15]],[[T11]] -; MIPS32: srl [[T18:.*]],a3,0x10 -; MIPS32: andi [[T18]],[[T18]],0x1 -; MIPS32: srl [[T3]],[[T3]],0x10 -; MIPS32: andi [[T3]],[[T3]],0x1 +; MIPS32: sll [[T15]],[[T15]],0x10 +; MIPS32: or [[T14]],[[T14]],[[T15]] +; MIPS32: srl [[T17:.*]],a1,0x10 +; MIPS32: andi [[T17]],[[T17]],0x1 ; MIPS32: srl [[T7]],[[T7]],0x10 ; MIPS32: andi [[T7]],[[T7]],0x1 -; MIPS32: movn [[T7]],[[T3]],[[T18]] -; MIPS32: sll [[T7]],[[T7]],0x10 -; MIPS32: sll [[T15]],[[T15]],0x10 -; MIPS32: srl [[T15]],[[T15]],0x10 -; MIPS32: or [[RV_E3:.*]],[[T7]],[[T15]] +; MIPS32: srl [[T11]],[[T11]],0x10 +; MIPS32: andi [[T11]],[[T11]],0x1 +; MIPS32: movn [[T11]],[[T7]],[[T17]] +; MIPS32: sll [[T11]],[[T11]],0x10 +; MIPS32: sll [[T14]],[[T14]],0x10 +; MIPS32: srl [[T14]],[[T14]],0x10 +; MIPS32: or [[T11]],[[T11]],[[T14]] +; MIPS32: move [[T6]],a2 +; MIPS32: andi [[T6]],[[T6]],0xffff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T8]] +; MIPS32: andi [[T7]],[[T7]],0xffff +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: move [[T16]],[[T12]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: srl [[T5]],[[T5]],0x10 +; MIPS32: sll [[T5]],[[T5]],0x10 +; MIPS32: or [[T16]],[[T16]],[[T5]] +; MIPS32: srl [[T18:.*]],a2,0x10 +; MIPS32: andi [[T18]],[[T18]],0x1 +; MIPS32: srl [[T8]],[[T8]],0x10 +; MIPS32: andi [[T8]],[[T8]],0x1 +; MIPS32: srl [[T12]],[[T12]],0x10 +; MIPS32: andi [[T12]],[[T12]],0x1 +; MIPS32: movn [[T12]],[[T8]],[[T18]] +; MIPS32: sll [[T12]],[[T12]],0x10 +; MIPS32: sll [[T16]],[[T16]],0x10 +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: or [[T12]],[[T12]],[[T16]] +; MIPS32: move [[T6]],a3 +; MIPS32: andi [[T6]],[[T6]],0xffff +; MIPS32: andi [[T6]],[[T6]],0x1 +; MIPS32: move [[T7]],[[T9]] +; MIPS32: andi [[T7]],[[T7]],0xffff +; MIPS32: andi [[T7]],[[T7]],0x1 +; MIPS32: move [[T16]],[[T13]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: andi [[T16]],[[T16]],0x1 +; MIPS32: movn [[T16]],[[T7]],[[T6]] +; MIPS32: andi [[T16]],[[T16]],0xffff +; MIPS32: srl [[T4]],[[T4]],0x10 +; MIPS32: sll [[T4]],[[T4]],0x10 +; MIPS32: or [[T16]],[[T16]],[[T4]] +; MIPS32: srl [[T19:.*]],a3,0x10 +; MIPS32: andi [[T19]],[[T19]],0x1 +; MIPS32: srl [[T9]],[[T9]],0x10 +; MIPS32: andi [[T9]],[[T9]],0x1 +; MIPS32: srl [[T13]],[[T13]],0x10 +; MIPS32: andi [[T13]],[[T13]],0x1 +; MIPS32: movn [[T13]],[[T9]],[[T19]] +; MIPS32: sll [[T13]],[[T13]],0x10 +; MIPS32: sll [[T16]],[[T16]],0x10 +; MIPS32: srl [[T16]],[[T16]],0x10 +; MIPS32: or [[T13]],[[T13]],[[T16]] +; MIPS32: move v0,[[T10]] +; MIPS32: move v1,[[T11]] +; MIPS32: move a0,[[T12]] +; MIPS32: move a1,[[T13]] +; MIPS32: lw [[T5]], +; MIPS32: lw [[T4]], +; MIPS32: lw [[T3]], +; MIPS32: lw [[T2]], +; MIPS32: lw [[T1]], +; MIPS32: addiu [[T0]],sp,20 } define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1, @@ -702,14 +862,14 @@ ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} ; MIPS32-LABEL: test_select_v4i32 -; MIPS32: lw [[T0:.*]],16(sp) -; MIPS32: lw [[T1:.*]],20(sp) -; MIPS32: lw [[T2:.*]],24(sp) -; MIPS32: lw [[T3:.*]],28(sp) -; MIPS32: lw [[T4:.*]],32(sp) -; MIPS32: lw [[T5:.*]],36(sp) -; MIPS32: lw [[T6:.*]],40(sp) -; MIPS32: lw [[T7:.*]],44(sp) +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: lw [[T4:.*]], +; MIPS32: lw [[T5:.*]], +; MIPS32: lw [[T6:.*]], +; MIPS32: lw [[T7:.*]], ; MIPS32: andi [[T8:.*]],a0,0x1 ; MIPS32: movn [[T4]],[[T0]],[[T8]] ; MIPS32: andi [[T9:.*]],a1,0x1 @@ -739,41 +899,41 @@ ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} ; MIPS32-LABEL: test_select_v4f32 -; MIPS32: lw [[T0:.*]],16(sp) -; MIPS32: lw [[T1:.*]],20(sp) -; MIPS32: lw [[T2:.*]],24(sp) -; MIPS32: lw [[T3:.*]],28(sp) -; MIPS32: lw [[T4:.*]],32(sp) -; MIPS32: lw [[T5:.*]],36(sp) -; MIPS32: lw [[T6:.*]],40(sp) -; MIPS32: lw [[T7:.*]],44(sp) -; MIPS32: lw [[T8:.*]],48(sp) -; MIPS32: lw [[T9:.*]],52(sp) +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: lw [[T4:.*]], +; MIPS32: lw [[T5:.*]], +; MIPS32: lw [[T6:.*]], +; MIPS32: lw [[T7:.*]], +; MIPS32: lw [[T8:.*]], +; MIPS32: lw [[T9:.*]], ; MIPS32: andi [[T10:.*]],a2,0x1 -; MIPS32: mtc1 [[T2]],[[F0:.*]] -; MIPS32: mtc1 [[T6]],[[F1:.*]] -; MIPS32: movn.s [[T11:.*]],[[F0]],[[T10]] -; MIPS32: mfc1 v0,[[T11]] +; MIPS32: mtc1 [[T2]],$f0 +; MIPS32: mtc1 [[T6]],$f1 +; MIPS32: movn.s [[T11:.*]],$f0,[[T10]] +; MIPS32: mfc1 [[T2]],[[T11]] ; MIPS32: andi [[T12:.*]],a3,0x1 -; MIPS32: mtc1 [[T3]],[[F0]] +; MIPS32: mtc1 [[T3]],$f0 ; MIPS32: mtc1 [[T7]],[[T11]] -; MIPS32: movn.s [[T11]],[[F0]],[[T12]] -; MIPS32: mfc1 v1,[[T11]] +; MIPS32: movn.s [[T11]],$f0,[[T12]] +; MIPS32: mfc1 [[T3]],[[T11]] ; MIPS32: andi [[T0]],[[T0]],0x1 -; MIPS32: mtc1 [[T4]],[[F0]] +; MIPS32: mtc1 [[T4]],$f0 ; MIPS32: mtc1 [[T8]],[[T11]] -; MIPS32: movn.s [[T11]],[[F0]],[[T0]] -; MIPS32: mfc1 a1,[[T11]] +; MIPS32: movn.s [[T11]],$f0,[[T0]] +; MIPS32: mfc1 [[T4]],[[T11]] ; MIPS32: andi [[T1]],[[T1]],0x1 -; MIPS32: mtc1 [[T5]],[[F0]] +; MIPS32: mtc1 [[T5]],$f0 ; MIPS32: mtc1 [[T9]],[[T11]] -; MIPS32: movn.s [[T11]],[[F0]],[[T1]] -; MIPS32: mfc1 a2,[[T11]] -; MIPS32: move [[RET:.*]],a0 -; MIPS32: sw v0,0([[RET]]) -; MIPS32: sw v1,4([[RET]]) -; MIPS32: sw a1,8([[RET]]) -; MIPS32: sw a2,12([[RET]]) +; MIPS32: movn.s [[T11]],$f0,[[T1]] +; MIPS32: mfc1 [[T10]],[[T11]] +; MIPS32: move [[T12]],a0 +; MIPS32: sw [[T2]],0(a3) +; MIPS32: sw v1,4(a3) +; MIPS32: sw a1,8(a3) +; MIPS32: sw [[T10]],12(a3) ; MIPS32: move v0,a0 } @@ -792,14 +952,14 @@ ; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}} ; MIPS32-LABEL: test_select_v4i1 -; MIPS32: lw [[T0:.*]],16(sp) -; MIPS32: lw [[T1:.*]],20(sp) -; MIPS32: lw [[T2:.*]],24(sp) -; MIPS32: lw [[T3:.*]],28(sp) -; MIPS32: lw [[T4:.*]],32(sp) -; MIPS32: lw [[T5:.*]],36(sp) -; MIPS32: lw [[T6:.*]],40(sp) -; MIPS32: lw [[T7:.*]],44(sp) +; MIPS32: lw [[T0:.*]], +; MIPS32: lw [[T1:.*]], +; MIPS32: lw [[T2:.*]], +; MIPS32: lw [[T3:.*]], +; MIPS32: lw [[T4:.*]], +; MIPS32: lw [[T5:.*]], +; MIPS32: lw [[T6:.*]], +; MIPS32: lw [[T7:.*]], ; MIPS32: andi [[T8:.*]],a0,0x1 ; MIPS32: andi [[T0]],[[T0]],0x1 ; MIPS32: andi [[T4]],[[T4]],0x1