llvm-10.0: add configs/common and configs/linux for riscv64
Bug: b/217573066
Signed-off-by: Rebecca Chang Swee Fun <rebecca.chang@starfivetech.com>
Change-Id: Ice4e65ca943f8dd98cb858d67725d88996937d9a
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/64670
Kokoro-Result: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
Reviewed-by: Ben Clayton <bclayton@google.com>
Tested-by: Nicolas Capens <nicolascapens@google.com>
diff --git a/third_party/llvm-10.0/BUILD.gn b/third_party/llvm-10.0/BUILD.gn
index 94dbaa2..6c40b2c 100644
--- a/third_party/llvm-10.0/BUILD.gn
+++ b/third_party/llvm-10.0/BUILD.gn
@@ -87,6 +87,7 @@
"llvm/lib/Target/ARM/",
"llvm/lib/Target/Mips/",
"llvm/lib/Target/PowerPC/",
+ "llvm/lib/Target/RISCV/",
"llvm/lib/Target/X86/",
"configs/common/include/",
"configs/common/lib/IR/",
@@ -94,6 +95,7 @@
"configs/common/lib/Target/ARM/",
"configs/common/lib/Target/Mips/",
"configs/common/lib/Target/PowerPC/",
+ "configs/common/lib/Target/RISCV/",
"configs/common/lib/Target/X86/",
"configs/common/lib/Transforms/InstCombine/",
]
@@ -152,6 +154,8 @@
deps += [ ":swiftshader_llvm_mips" ]
} else if (current_cpu == "ppc64") {
deps += [ ":swiftshader_llvm_ppc" ]
+ } else if (current_cpu == "riscv64") {
+ deps += [ ":swiftshader_llvm_riscv64" ]
} else if (current_cpu == "x86" || current_cpu == "x64") {
deps += [ ":swiftshader_llvm_x86" ]
} else {
@@ -1314,3 +1318,39 @@
"llvm/lib/Target/X86/X86WinEHState.cpp",
]
}
+
+swiftshader_llvm_source_set("swiftshader_llvm_riscv64") {
+ sources = [
+ "llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp",
+ "llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp",
+ "llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp",
+ "llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp",
+ "llvm/lib/Target/RISCV/RISCVCallLowering.cpp",
+ "llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp",
+ "llvm/lib/Target/RISCV/RISCVFrameLowering.cpp",
+ "llvm/lib/Target/RISCV/RISCVInstrInfo.cpp",
+ "llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp",
+ "llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp",
+ "llvm/lib/Target/RISCV/RISCVISelLowering.cpp",
+ "llvm/lib/Target/RISCV/RISCVLegalizerInfo.cpp",
+ "llvm/lib/Target/RISCV/RISCVMCInstLower.cpp",
+ "llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp",
+ "llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp",
+ "llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp",
+ "llvm/lib/Target/RISCV/RISCVSubtarget.cpp",
+ "llvm/lib/Target/RISCV/RISCVTargetMachine.cpp",
+ "llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp",
+ "llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp",
+ "llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp",
+ "llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp",
+ "llvm/lib/Target/RISCV/Utils/RISCVMatInt.cpp",
+ ]
+}
diff --git a/third_party/llvm-10.0/CMakeLists.txt b/third_party/llvm-10.0/CMakeLists.txt
index 4da7922..30e4d90 100644
--- a/third_party/llvm-10.0/CMakeLists.txt
+++ b/third_party/llvm-10.0/CMakeLists.txt
@@ -1126,6 +1126,40 @@
${LLVM_DIR}/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
${LLVM_DIR}/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
)
+elseif(ARCH STREQUAL "riscv64")
+ list(APPEND LLVM_LIST
+ ${LLVM_DIR}/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVAsmPrinter.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVCallLowering.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVFrameLowering.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVInstrInfo.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVInstructionSelector.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVISelLowering.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVLegalizerInfo.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVMCInstLower.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVRegisterInfo.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVSubtarget.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVTargetMachine.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVTargetObjectFile.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
+ ${LLVM_DIR}/lib/Target/RISCV/Utils/RISCVMatInt.cpp
+ )
endif()
if(REACTOR_EMIT_DEBUG_INFO)
@@ -1157,6 +1191,7 @@
${LLVM_DIR}/lib/Target/ARM
${LLVM_DIR}/lib/Target/Mips
${LLVM_DIR}/lib/Target/PowerPC
+ ${LLVM_DIR}/lib/Target/RISCV
${LLVM_DIR}/lib/Target/X86
${LLVM_CONFIG_DIR}/common/include
${LLVM_CONFIG_DIR}/common/lib/IR
@@ -1164,6 +1199,7 @@
${LLVM_CONFIG_DIR}/common/lib/Target/ARM
${LLVM_CONFIG_DIR}/common/lib/Target/Mips
${LLVM_CONFIG_DIR}/common/lib/Target/PowerPC
+ ${LLVM_CONFIG_DIR}/common/lib/Target/RISCV
${LLVM_CONFIG_DIR}/common/lib/Target/X86
${LLVM_CONFIG_DIR}/common/lib/Transforms/InstCombine
)
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenAsmMatcher.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenAsmMatcher.inc
new file mode 100644
index 0000000..086c441
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenAsmMatcher.inc
@@ -0,0 +1,2861 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Assembly Matcher Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_ASSEMBLER_HEADER
+#undef GET_ASSEMBLER_HEADER
+ // This should be included into the middle of the declaration of
+ // your subclasses implementation of MCTargetAsmParser.
+ FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const;
+ void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
+ const OperandVector &Operands);
+ void convertToMapAndConstraints(unsigned Kind,
+ const OperandVector &Operands) override;
+ unsigned MatchInstructionImpl(const OperandVector &Operands,
+ MCInst &Inst,
+ uint64_t &ErrorInfo,
+ FeatureBitset &MissingFeatures,
+ bool matchingInlineAsm,
+ unsigned VariantID = 0);
+ unsigned MatchInstructionImpl(const OperandVector &Operands,
+ MCInst &Inst,
+ uint64_t &ErrorInfo,
+ bool matchingInlineAsm,
+ unsigned VariantID = 0) {
+ FeatureBitset MissingFeatures;
+ return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
+ matchingInlineAsm, VariantID);
+ }
+
+ OperandMatchResultTy MatchOperandParserImpl(
+ OperandVector &Operands,
+ StringRef Mnemonic,
+ bool ParseForAllFeatures = false);
+ OperandMatchResultTy tryCustomParseOperand(
+ OperandVector &Operands,
+ unsigned MCK);
+
+#endif // GET_ASSEMBLER_HEADER_INFO
+
+
+#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
+#undef GET_OPERAND_DIAGNOSTIC_TYPES
+
+ Match_InvalidBareSymbol,
+ Match_InvalidCLUIImm,
+ Match_InvalidCSRSystemRegister,
+ Match_InvalidCallSymbol,
+ Match_InvalidFRMArg,
+ Match_InvalidFenceArg,
+ Match_InvalidImmXLenLI,
+ Match_InvalidImmZero,
+ Match_InvalidSImm10Lsb0000NonZero,
+ Match_InvalidSImm12,
+ Match_InvalidSImm12Lsb0,
+ Match_InvalidSImm13Lsb0,
+ Match_InvalidSImm21Lsb0JAL,
+ Match_InvalidSImm6,
+ Match_InvalidSImm6NonZero,
+ Match_InvalidSImm9Lsb0,
+ Match_InvalidTPRelAddSymbol,
+ Match_InvalidUImm10Lsb00NonZero,
+ Match_InvalidUImm20AUIPC,
+ Match_InvalidUImm20LUI,
+ Match_InvalidUImm5,
+ Match_InvalidUImm7Lsb00,
+ Match_InvalidUImm8Lsb00,
+ Match_InvalidUImm8Lsb000,
+ Match_InvalidUImm9Lsb000,
+ Match_InvalidUImmLog2XLen,
+ Match_InvalidUImmLog2XLenNonZero,
+ END_OPERAND_DIAGNOSTIC_TYPES
+#endif // GET_OPERAND_DIAGNOSTIC_TYPES
+
+
+#ifdef GET_REGISTER_MATCHER
+#undef GET_REGISTER_MATCHER
+
+// Bits for subtarget features that participate in instruction matching.
+enum SubtargetFeatureBits : uint8_t {
+ Feature_HasStdExtMBit = 5,
+ Feature_HasStdExtABit = 1,
+ Feature_HasStdExtFBit = 4,
+ Feature_HasStdExtDBit = 3,
+ Feature_HasStdExtCBit = 2,
+ Feature_HasRVCHintsBit = 0,
+ Feature_IsRV64Bit = 8,
+ Feature_IsRV32Bit = 6,
+ Feature_IsRV32EBit = 7,
+};
+
+static unsigned MatchRegisterName(StringRef Name) {
+ switch (Name.size()) {
+ default: break;
+ case 2: // 30 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'f': // 20 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 33; // "f0"
+ case '1': // 2 strings to match.
+ return 34; // "f1"
+ case '2': // 2 strings to match.
+ return 35; // "f2"
+ case '3': // 2 strings to match.
+ return 36; // "f3"
+ case '4': // 2 strings to match.
+ return 37; // "f4"
+ case '5': // 2 strings to match.
+ return 38; // "f5"
+ case '6': // 2 strings to match.
+ return 39; // "f6"
+ case '7': // 2 strings to match.
+ return 40; // "f7"
+ case '8': // 2 strings to match.
+ return 41; // "f8"
+ case '9': // 2 strings to match.
+ return 42; // "f9"
+ }
+ break;
+ case 'x': // 10 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 1; // "x0"
+ case '1': // 1 string to match.
+ return 2; // "x1"
+ case '2': // 1 string to match.
+ return 3; // "x2"
+ case '3': // 1 string to match.
+ return 4; // "x3"
+ case '4': // 1 string to match.
+ return 5; // "x4"
+ case '5': // 1 string to match.
+ return 6; // "x5"
+ case '6': // 1 string to match.
+ return 7; // "x6"
+ case '7': // 1 string to match.
+ return 8; // "x7"
+ case '8': // 1 string to match.
+ return 9; // "x8"
+ case '9': // 1 string to match.
+ return 10; // "x9"
+ }
+ break;
+ }
+ break;
+ case 3: // 66 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'f': // 44 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '1': // 20 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 43; // "f10"
+ case '1': // 2 strings to match.
+ return 44; // "f11"
+ case '2': // 2 strings to match.
+ return 45; // "f12"
+ case '3': // 2 strings to match.
+ return 46; // "f13"
+ case '4': // 2 strings to match.
+ return 47; // "f14"
+ case '5': // 2 strings to match.
+ return 48; // "f15"
+ case '6': // 2 strings to match.
+ return 49; // "f16"
+ case '7': // 2 strings to match.
+ return 50; // "f17"
+ case '8': // 2 strings to match.
+ return 51; // "f18"
+ case '9': // 2 strings to match.
+ return 52; // "f19"
+ }
+ break;
+ case '2': // 20 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 53; // "f20"
+ case '1': // 2 strings to match.
+ return 54; // "f21"
+ case '2': // 2 strings to match.
+ return 55; // "f22"
+ case '3': // 2 strings to match.
+ return 56; // "f23"
+ case '4': // 2 strings to match.
+ return 57; // "f24"
+ case '5': // 2 strings to match.
+ return 58; // "f25"
+ case '6': // 2 strings to match.
+ return 59; // "f26"
+ case '7': // 2 strings to match.
+ return 60; // "f27"
+ case '8': // 2 strings to match.
+ return 61; // "f28"
+ case '9': // 2 strings to match.
+ return 62; // "f29"
+ }
+ break;
+ case '3': // 4 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 63; // "f30"
+ case '1': // 2 strings to match.
+ return 64; // "f31"
+ }
+ break;
+ }
+ break;
+ case 'x': // 22 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '1': // 10 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 11; // "x10"
+ case '1': // 1 string to match.
+ return 12; // "x11"
+ case '2': // 1 string to match.
+ return 13; // "x12"
+ case '3': // 1 string to match.
+ return 14; // "x13"
+ case '4': // 1 string to match.
+ return 15; // "x14"
+ case '5': // 1 string to match.
+ return 16; // "x15"
+ case '6': // 1 string to match.
+ return 17; // "x16"
+ case '7': // 1 string to match.
+ return 18; // "x17"
+ case '8': // 1 string to match.
+ return 19; // "x18"
+ case '9': // 1 string to match.
+ return 20; // "x19"
+ }
+ break;
+ case '2': // 10 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 21; // "x20"
+ case '1': // 1 string to match.
+ return 22; // "x21"
+ case '2': // 1 string to match.
+ return 23; // "x22"
+ case '3': // 1 string to match.
+ return 24; // "x23"
+ case '4': // 1 string to match.
+ return 25; // "x24"
+ case '5': // 1 string to match.
+ return 26; // "x25"
+ case '6': // 1 string to match.
+ return 27; // "x26"
+ case '7': // 1 string to match.
+ return 28; // "x27"
+ case '8': // 1 string to match.
+ return 29; // "x28"
+ case '9': // 1 string to match.
+ return 30; // "x29"
+ }
+ break;
+ case '3': // 2 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 31; // "x30"
+ case '1': // 1 string to match.
+ return 32; // "x31"
+ }
+ break;
+ }
+ break;
+ }
+ break;
+ }
+ return 0;
+}
+
+static unsigned MatchRegisterAltName(StringRef Name) {
+ switch (Name.size()) {
+ default: break;
+ case 2: // 30 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'a': // 8 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 11; // "a0"
+ case '1': // 1 string to match.
+ return 12; // "a1"
+ case '2': // 1 string to match.
+ return 13; // "a2"
+ case '3': // 1 string to match.
+ return 14; // "a3"
+ case '4': // 1 string to match.
+ return 15; // "a4"
+ case '5': // 1 string to match.
+ return 16; // "a5"
+ case '6': // 1 string to match.
+ return 17; // "a6"
+ case '7': // 1 string to match.
+ return 18; // "a7"
+ }
+ break;
+ case 'f': // 1 string to match.
+ if (Name[1] != 'p')
+ break;
+ return 9; // "fp"
+ case 'g': // 1 string to match.
+ if (Name[1] != 'p')
+ break;
+ return 4; // "gp"
+ case 'r': // 1 string to match.
+ if (Name[1] != 'a')
+ break;
+ return 2; // "ra"
+ case 's': // 11 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 9; // "s0"
+ case '1': // 1 string to match.
+ return 10; // "s1"
+ case '2': // 1 string to match.
+ return 19; // "s2"
+ case '3': // 1 string to match.
+ return 20; // "s3"
+ case '4': // 1 string to match.
+ return 21; // "s4"
+ case '5': // 1 string to match.
+ return 22; // "s5"
+ case '6': // 1 string to match.
+ return 23; // "s6"
+ case '7': // 1 string to match.
+ return 24; // "s7"
+ case '8': // 1 string to match.
+ return 25; // "s8"
+ case '9': // 1 string to match.
+ return 26; // "s9"
+ case 'p': // 1 string to match.
+ return 3; // "sp"
+ }
+ break;
+ case 't': // 8 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 6; // "t0"
+ case '1': // 1 string to match.
+ return 7; // "t1"
+ case '2': // 1 string to match.
+ return 8; // "t2"
+ case '3': // 1 string to match.
+ return 29; // "t3"
+ case '4': // 1 string to match.
+ return 30; // "t4"
+ case '5': // 1 string to match.
+ return 31; // "t5"
+ case '6': // 1 string to match.
+ return 32; // "t6"
+ case 'p': // 1 string to match.
+ return 5; // "tp"
+ }
+ break;
+ }
+ break;
+ case 3: // 58 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'f': // 56 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 'a': // 16 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 43; // "fa0"
+ case '1': // 2 strings to match.
+ return 44; // "fa1"
+ case '2': // 2 strings to match.
+ return 45; // "fa2"
+ case '3': // 2 strings to match.
+ return 46; // "fa3"
+ case '4': // 2 strings to match.
+ return 47; // "fa4"
+ case '5': // 2 strings to match.
+ return 48; // "fa5"
+ case '6': // 2 strings to match.
+ return 49; // "fa6"
+ case '7': // 2 strings to match.
+ return 50; // "fa7"
+ }
+ break;
+ case 's': // 20 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 41; // "fs0"
+ case '1': // 2 strings to match.
+ return 42; // "fs1"
+ case '2': // 2 strings to match.
+ return 51; // "fs2"
+ case '3': // 2 strings to match.
+ return 52; // "fs3"
+ case '4': // 2 strings to match.
+ return 53; // "fs4"
+ case '5': // 2 strings to match.
+ return 54; // "fs5"
+ case '6': // 2 strings to match.
+ return 55; // "fs6"
+ case '7': // 2 strings to match.
+ return 56; // "fs7"
+ case '8': // 2 strings to match.
+ return 57; // "fs8"
+ case '9': // 2 strings to match.
+ return 58; // "fs9"
+ }
+ break;
+ case 't': // 20 strings to match.
+ switch (Name[2]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 33; // "ft0"
+ case '1': // 2 strings to match.
+ return 34; // "ft1"
+ case '2': // 2 strings to match.
+ return 35; // "ft2"
+ case '3': // 2 strings to match.
+ return 36; // "ft3"
+ case '4': // 2 strings to match.
+ return 37; // "ft4"
+ case '5': // 2 strings to match.
+ return 38; // "ft5"
+ case '6': // 2 strings to match.
+ return 39; // "ft6"
+ case '7': // 2 strings to match.
+ return 40; // "ft7"
+ case '8': // 2 strings to match.
+ return 61; // "ft8"
+ case '9': // 2 strings to match.
+ return 62; // "ft9"
+ }
+ break;
+ }
+ break;
+ case 's': // 2 strings to match.
+ if (Name[1] != '1')
+ break;
+ switch (Name[2]) {
+ default: break;
+ case '0': // 1 string to match.
+ return 27; // "s10"
+ case '1': // 1 string to match.
+ return 28; // "s11"
+ }
+ break;
+ }
+ break;
+ case 4: // 9 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case 'f': // 8 strings to match.
+ switch (Name[1]) {
+ default: break;
+ case 's': // 4 strings to match.
+ if (Name[2] != '1')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 59; // "fs10"
+ case '1': // 2 strings to match.
+ return 60; // "fs11"
+ }
+ break;
+ case 't': // 4 strings to match.
+ if (Name[2] != '1')
+ break;
+ switch (Name[3]) {
+ default: break;
+ case '0': // 2 strings to match.
+ return 63; // "ft10"
+ case '1': // 2 strings to match.
+ return 64; // "ft11"
+ }
+ break;
+ }
+ break;
+ case 'z': // 1 string to match.
+ if (memcmp(Name.data()+1, "ero", 3) != 0)
+ break;
+ return 1; // "zero"
+ }
+ break;
+ }
+ return 0;
+}
+
+#endif // GET_REGISTER_MATCHER
+
+
+#ifdef GET_SUBTARGET_FEATURE_NAME
+#undef GET_SUBTARGET_FEATURE_NAME
+
+// User-level names for subtarget features that participate in
+// instruction matching.
+static const char *getSubtargetFeatureName(uint64_t Val) {
+ switch(Val) {
+ case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)";
+ case Feature_HasStdExtABit: return "'A' (Atomic Instructions)";
+ case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)";
+ case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)";
+ case Feature_HasStdExtCBit: return "'C' (Compressed Instructions)";
+ case Feature_HasRVCHintsBit: return "RVC Hint Instructions";
+ case Feature_IsRV64Bit: return "RV64I Base Instruction Set";
+ case Feature_IsRV32Bit: return "RV32I Base Instruction Set";
+ case Feature_IsRV32EBit: return "";
+ default: return "(unknown)";
+ }
+}
+
+#endif // GET_SUBTARGET_FEATURE_NAME
+
+
+#ifdef GET_MATCHER_IMPLEMENTATION
+#undef GET_MATCHER_IMPLEMENTATION
+
+static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
+ switch (VariantID) {
+ case 0:
+ switch (Mnemonic.size()) {
+ default: break;
+ case 4: // 1 string to match.
+ if (memcmp(Mnemonic.data()+0, "move", 4) != 0)
+ break;
+ Mnemonic = "mv"; // "move"
+ return;
+ case 5: // 1 string to match.
+ if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
+ break;
+ Mnemonic = "ecall"; // "scall"
+ return;
+ case 6: // 1 string to match.
+ if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0)
+ break;
+ Mnemonic = "ebreak"; // "sbreak"
+ return;
+ case 7: // 2 strings to match.
+ if (memcmp(Mnemonic.data()+0, "fmv.", 4) != 0)
+ break;
+ switch (Mnemonic[4]) {
+ default: break;
+ case 's': // 1 string to match.
+ if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
+ break;
+ if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x"
+ Mnemonic = "fmv.w.x";
+ return;
+ case 'x': // 1 string to match.
+ if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
+ break;
+ if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s"
+ Mnemonic = "fmv.x.w";
+ return;
+ }
+ break;
+ }
+ break;
+ }
+ switch (Mnemonic.size()) {
+ default: break;
+ case 4: // 1 string to match.
+ if (memcmp(Mnemonic.data()+0, "move", 4) != 0)
+ break;
+ Mnemonic = "mv"; // "move"
+ return;
+ case 5: // 1 string to match.
+ if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
+ break;
+ Mnemonic = "ecall"; // "scall"
+ return;
+ case 6: // 1 string to match.
+ if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0)
+ break;
+ Mnemonic = "ebreak"; // "sbreak"
+ return;
+ case 7: // 2 strings to match.
+ if (memcmp(Mnemonic.data()+0, "fmv.", 4) != 0)
+ break;
+ switch (Mnemonic[4]) {
+ default: break;
+ case 's': // 1 string to match.
+ if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
+ break;
+ if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x"
+ Mnemonic = "fmv.w.x";
+ return;
+ case 'x': // 1 string to match.
+ if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
+ break;
+ if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s"
+ Mnemonic = "fmv.x.w";
+ return;
+ }
+ break;
+ }
+}
+
+enum {
+ Tie0_1_1,
+};
+
+static const uint8_t TiedAsmOperandTable[][3] = {
+ /* Tie0_1_1 */ { 0, 1, 1 },
+};
+
+namespace {
+enum OperatorConversionKind {
+ CVT_Done,
+ CVT_Reg,
+ CVT_Tied,
+ CVT_95_Reg,
+ CVT_95_addImmOperands,
+ CVT_95_addRegOperands,
+ CVT_regX0,
+ CVT_imm_95_0,
+ CVT_95_addCSRSystemRegisterOperands,
+ CVT_imm_95_7,
+ CVT_95_addFRMArgOperands,
+ CVT_imm_95_15,
+ CVT_95_addFenceArgOperands,
+ CVT_imm_95_3,
+ CVT_imm_95_1,
+ CVT_imm_95_2,
+ CVT_regX1,
+ CVT_imm_95__MINUS_1,
+ CVT_imm_95_3072,
+ CVT_imm_95_3200,
+ CVT_imm_95_3074,
+ CVT_imm_95_3202,
+ CVT_imm_95_3073,
+ CVT_imm_95_3201,
+ CVT_NUM_CONVERTERS
+};
+
+enum InstructionConversionKind {
+ Convert__Reg1_0__Reg1_1__Reg1_2,
+ Convert__Reg1_0__Reg1_1__SImm121_2,
+ Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3,
+ Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1,
+ Convert__Reg1_0__UImm20AUIPC1_1,
+ Convert__Reg1_0__Reg1_1__SImm13Lsb01_2,
+ Convert__Reg1_0__regX0__SImm13Lsb01_1,
+ Convert__Reg1_1__Reg1_0__SImm13Lsb01_2,
+ Convert__regX0__Reg1_0__SImm13Lsb01_1,
+ Convert__Reg1_0__Tie0_1_1__Reg1_1,
+ Convert__Reg1_0__Tie0_1_1__ImmZero1_1,
+ Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1,
+ Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1,
+ Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2,
+ Convert__Reg1_0__Tie0_1_1__SImm61_1,
+ Convert__Reg1_0__SImm9Lsb01_1,
+ Convert_NoOperands,
+ Convert__Reg1_0__Reg1_2__imm_95_0,
+ Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1,
+ Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1,
+ Convert__Reg1_0__Reg1_3__UImm7Lsb001_1,
+ Convert__Reg1_0__Reg1_3__UImm8Lsb001_1,
+ Convert__SImm12Lsb01_0,
+ Convert__Reg1_0,
+ Convert__Reg1_0__SImm61_1,
+ Convert__Reg1_0__CLUIImm1_1,
+ Convert__Reg1_0__Reg1_1,
+ Convert__SImm6NonZero1_0,
+ Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1,
+ Convert__Reg1_0__Tie0_1_1,
+ Convert__CallSymbol1_0,
+ Convert__Reg1_0__CallSymbol1_1,
+ Convert__regX0__CSRSystemRegister1_0__Reg1_1,
+ Convert__regX0__CSRSystemRegister1_0__UImm51_1,
+ Convert__Reg1_0__CSRSystemRegister1_1__regX0,
+ Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2,
+ Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2,
+ Convert__Reg1_0__Reg1_1__Reg1_1,
+ Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7,
+ Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3,
+ Convert__Reg1_0__Reg1_1__imm_95_7,
+ Convert__Reg1_0__Reg1_1__FRMArg1_2,
+ Convert__imm_95_15__imm_95_15,
+ Convert__FenceArg1_0__FenceArg1_1,
+ Convert__Reg1_0__Reg1_2__Reg1_1,
+ Convert__Reg1_0__Reg1_2__BareSymbol1_1,
+ Convert__Reg1_0__Reg1_3__SImm121_1,
+ Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7,
+ Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4,
+ Convert__Reg1_0__imm_95_3__regX0,
+ Convert__Reg1_0__imm_95_1__regX0,
+ Convert__Reg1_0__imm_95_2__regX0,
+ Convert__regX0__imm_95_3__Reg1_0,
+ Convert__Reg1_0__imm_95_3__Reg1_1,
+ Convert__regX0__imm_95_1__Reg1_0,
+ Convert__Reg1_0__imm_95_1__Reg1_1,
+ Convert__regX0__imm_95_1__UImm51_0,
+ Convert__Reg1_0__imm_95_1__UImm51_1,
+ Convert__regX0__imm_95_2__Reg1_0,
+ Convert__Reg1_0__imm_95_2__Reg1_1,
+ Convert__regX0__imm_95_2__UImm51_0,
+ Convert__Reg1_0__imm_95_2__UImm51_1,
+ Convert__regX0__SImm21Lsb0JAL1_0,
+ Convert__regX1__SImm21Lsb0JAL1_0,
+ Convert__Reg1_0__SImm21Lsb0JAL1_1,
+ Convert__regX1__Reg1_0__imm_95_0,
+ Convert__Reg1_0__Reg1_1__imm_95_0,
+ Convert__regX1__Reg1_0__SImm121_1,
+ Convert__regX1__Reg1_2__SImm121_0,
+ Convert__regX0__Reg1_0__imm_95_0,
+ Convert__regX0__Reg1_0__SImm121_1,
+ Convert__regX0__Reg1_2__SImm121_0,
+ Convert__Reg1_0__BareSymbol1_1,
+ Convert__Reg1_0__ImmXLenLI1_1,
+ Convert__Reg1_0__AtomicMemOpOperand1_1,
+ Convert__Reg1_0__UImm20LUI1_1,
+ Convert__imm_95_0__imm_95_0,
+ Convert__Reg1_0__regX0__Reg1_1,
+ Convert__regX0__regX0__imm_95_0,
+ Convert__Reg1_0__Reg1_1__imm_95__MINUS_1,
+ Convert__Reg1_0__imm_95_3072__regX0,
+ Convert__Reg1_0__imm_95_3200__regX0,
+ Convert__Reg1_0__imm_95_3074__regX0,
+ Convert__Reg1_0__imm_95_3202__regX0,
+ Convert__Reg1_0__imm_95_3073__regX0,
+ Convert__Reg1_0__imm_95_3201__regX0,
+ Convert__regX0__regX1__imm_95_0,
+ Convert__Reg1_0__Reg1_1__imm_95_1,
+ Convert__regX0__regX0,
+ Convert__Reg1_0__regX0,
+ Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2,
+ Convert__Reg1_0__Reg1_1__UImm51_2,
+ Convert__Reg1_0__Reg1_1__regX0,
+ CVT_NUM_SIGNATURES
+};
+
+} // end anonymous namespace
+
+static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
+ // Convert__Reg1_0__Reg1_1__Reg1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm121_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
+ // Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1
+ { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_Reg, 2, CVT_Done },
+ // Convert__Reg1_0__UImm20AUIPC1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__SImm13Lsb01_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__regX0__SImm13Lsb01_1
+ { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_1__Reg1_0__SImm13Lsb01_2
+ { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__regX0__Reg1_0__SImm13Lsb01_1
+ { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__Reg1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__ImmZero1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__SImm61_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__SImm9Lsb01_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert_NoOperands
+ { CVT_Done },
+ // Convert__Reg1_0__Reg1_2__imm_95_0
+ { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_3__UImm7Lsb001_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_3__UImm8Lsb001_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__SImm12Lsb01_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0
+ { CVT_95_Reg, 1, CVT_Done },
+ // Convert__Reg1_0__SImm61_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__CLUIImm1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
+ // Convert__SImm6NonZero1_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Tie0_1_1
+ { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
+ // Convert__CallSymbol1_0
+ { CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__CallSymbol1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__regX0__CSRSystemRegister1_0__Reg1_1
+ { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
+ // Convert__regX0__CSRSystemRegister1_0__UImm51_1
+ { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__CSRSystemRegister1_1__regX0
+ { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2
+ { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done },
+ // Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2
+ { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_7, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands, 4, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__imm_95_7
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__FRMArg1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
+ // Convert__imm_95_15__imm_95_15
+ { CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done },
+ // Convert__FenceArg1_0__FenceArg1_1
+ { CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_2__Reg1_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_2__BareSymbol1_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_3__SImm121_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_7, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands, 5, CVT_Done },
+ // Convert__Reg1_0__imm_95_3__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__imm_95_1__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__imm_95_2__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__regX0__imm_95_3__Reg1_0
+ { CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
+ // Convert__Reg1_0__imm_95_3__Reg1_1
+ { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
+ // Convert__regX0__imm_95_1__Reg1_0
+ { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
+ // Convert__Reg1_0__imm_95_1__Reg1_1
+ { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
+ // Convert__regX0__imm_95_1__UImm51_0
+ { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__imm_95_1__UImm51_1
+ { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__regX0__imm_95_2__Reg1_0
+ { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
+ // Convert__Reg1_0__imm_95_2__Reg1_1
+ { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
+ // Convert__regX0__imm_95_2__UImm51_0
+ { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__imm_95_2__UImm51_1
+ { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__regX0__SImm21Lsb0JAL1_0
+ { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__regX1__SImm21Lsb0JAL1_0
+ { CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__SImm21Lsb0JAL1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__regX1__Reg1_0__imm_95_0
+ { CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__imm_95_0
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__regX1__Reg1_0__SImm121_1
+ { CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__regX1__Reg1_2__SImm121_0
+ { CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__regX0__Reg1_0__imm_95_0
+ { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__regX0__Reg1_0__SImm121_1
+ { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__regX0__Reg1_2__SImm121_0
+ { CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
+ // Convert__Reg1_0__BareSymbol1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__ImmXLenLI1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__Reg1_0__AtomicMemOpOperand1_1
+ { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
+ // Convert__Reg1_0__UImm20LUI1_1
+ { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
+ // Convert__imm_95_0__imm_95_0
+ { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__Reg1_0__regX0__Reg1_1
+ { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
+ // Convert__regX0__regX0__imm_95_0
+ { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done },
+ // Convert__Reg1_0__imm_95_3072__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__imm_95_3200__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__imm_95_3074__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__imm_95_3202__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__imm_95_3073__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__imm_95_3201__regX0
+ { CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__regX0__regX1__imm_95_0
+ { CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__imm_95_1
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
+ // Convert__regX0__regX0
+ { CVT_regX0, 0, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__regX0
+ { CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__UImm51_2
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
+ // Convert__Reg1_0__Reg1_1__regX0
+ { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
+};
+
+void RISCVAsmParser::
+convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
+ const OperandVector &Operands) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ const uint8_t *Converter = ConversionTable[Kind];
+ unsigned OpIdx;
+ Inst.setOpcode(Opcode);
+ for (const uint8_t *p = Converter; *p; p+= 2) {
+ OpIdx = *(p + 1);
+ switch (*p) {
+ default: llvm_unreachable("invalid conversion entry!");
+ case CVT_Reg:
+ static_cast<RISCVOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
+ break;
+ case CVT_Tied: {
+ assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
+ std::begin(TiedAsmOperandTable)) &&
+ "Tied operand not found");
+ unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
+ if (TiedResOpnd != (uint8_t) -1)
+ Inst.addOperand(Inst.getOperand(TiedResOpnd));
+ break;
+ }
+ case CVT_95_Reg:
+ static_cast<RISCVOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
+ break;
+ case CVT_95_addImmOperands:
+ static_cast<RISCVOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
+ break;
+ case CVT_95_addRegOperands:
+ static_cast<RISCVOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
+ break;
+ case CVT_regX0:
+ Inst.addOperand(MCOperand::createReg(RISCV::X0));
+ break;
+ case CVT_imm_95_0:
+ Inst.addOperand(MCOperand::createImm(0));
+ break;
+ case CVT_95_addCSRSystemRegisterOperands:
+ static_cast<RISCVOperand&>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1);
+ break;
+ case CVT_imm_95_7:
+ Inst.addOperand(MCOperand::createImm(7));
+ break;
+ case CVT_95_addFRMArgOperands:
+ static_cast<RISCVOperand&>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
+ break;
+ case CVT_imm_95_15:
+ Inst.addOperand(MCOperand::createImm(15));
+ break;
+ case CVT_95_addFenceArgOperands:
+ static_cast<RISCVOperand&>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1);
+ break;
+ case CVT_imm_95_3:
+ Inst.addOperand(MCOperand::createImm(3));
+ break;
+ case CVT_imm_95_1:
+ Inst.addOperand(MCOperand::createImm(1));
+ break;
+ case CVT_imm_95_2:
+ Inst.addOperand(MCOperand::createImm(2));
+ break;
+ case CVT_regX1:
+ Inst.addOperand(MCOperand::createReg(RISCV::X1));
+ break;
+ case CVT_imm_95__MINUS_1:
+ Inst.addOperand(MCOperand::createImm(-1));
+ break;
+ case CVT_imm_95_3072:
+ Inst.addOperand(MCOperand::createImm(3072));
+ break;
+ case CVT_imm_95_3200:
+ Inst.addOperand(MCOperand::createImm(3200));
+ break;
+ case CVT_imm_95_3074:
+ Inst.addOperand(MCOperand::createImm(3074));
+ break;
+ case CVT_imm_95_3202:
+ Inst.addOperand(MCOperand::createImm(3202));
+ break;
+ case CVT_imm_95_3073:
+ Inst.addOperand(MCOperand::createImm(3073));
+ break;
+ case CVT_imm_95_3201:
+ Inst.addOperand(MCOperand::createImm(3201));
+ break;
+ }
+ }
+}
+
+void RISCVAsmParser::
+convertToMapAndConstraints(unsigned Kind,
+ const OperandVector &Operands) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ unsigned NumMCOperands = 0;
+ const uint8_t *Converter = ConversionTable[Kind];
+ for (const uint8_t *p = Converter; *p; p+= 2) {
+ switch (*p) {
+ default: llvm_unreachable("invalid conversion entry!");
+ case CVT_Reg:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("r");
+ ++NumMCOperands;
+ break;
+ case CVT_Tied:
+ ++NumMCOperands;
+ break;
+ case CVT_95_Reg:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("r");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addImmOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_95_addRegOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_regX0:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_0:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addCSRSystemRegisterOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_imm_95_7:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addFRMArgOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_imm_95_15:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_95_addFenceArgOperands:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ NumMCOperands += 1;
+ break;
+ case CVT_imm_95_3:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_1:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_2:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_regX1:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("m");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95__MINUS_1:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_3072:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_3200:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_3074:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_3202:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_3073:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ case CVT_imm_95_3201:
+ Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
+ Operands[*(p + 1)]->setConstraint("");
+ ++NumMCOperands;
+ break;
+ }
+ }
+}
+
+namespace {
+
+/// MatchClassKind - The kinds of classes which participate in
+/// instruction matching.
+enum MatchClassKind {
+ InvalidMatchClass = 0,
+ OptionalMatchClass = 1,
+ MCK__40_, // '('
+ MCK__41_, // ')'
+ MCK_LAST_TOKEN = MCK__41_,
+ MCK_GPRX0, // register class 'GPRX0'
+ MCK_SP, // register class 'SP'
+ MCK_Reg7, // derived register class
+ MCK_FPR32C, // register class 'FPR32C'
+ MCK_FPR64C, // register class 'FPR64C'
+ MCK_GPRC, // register class 'GPRC'
+ MCK_GPRTC, // register class 'GPRTC'
+ MCK_GPRNoX0X2, // register class 'GPRNoX0X2'
+ MCK_GPRNoX0, // register class 'GPRNoX0'
+ MCK_FPR32, // register class 'FPR32'
+ MCK_FPR64, // register class 'FPR64'
+ MCK_GPR, // register class 'GPR'
+ MCK_LAST_REGISTER = MCK_GPR,
+ MCK_AtomicMemOpOperand, // user defined class 'AtomicMemOpOperand'
+ MCK_BareSymbol, // user defined class 'BareSymbol'
+ MCK_CLUIImm, // user defined class 'CLUIImmAsmOperand'
+ MCK_CSRSystemRegister, // user defined class 'CSRSystemRegister'
+ MCK_CallSymbol, // user defined class 'CallSymbol'
+ MCK_FRMArg, // user defined class 'FRMArg'
+ MCK_FenceArg, // user defined class 'FenceArg'
+ MCK_Imm, // user defined class 'ImmAsmOperand'
+ MCK_ImmZero, // user defined class 'ImmZeroAsmOperand'
+ MCK_SImm21Lsb0JAL, // user defined class 'Simm21Lsb0JALAsmOperand'
+ MCK_TPRelAddSymbol, // user defined class 'TPRelAddSymbol'
+ MCK_UImmLog2XLen, // user defined class 'UImmLog2XLenAsmOperand'
+ MCK_UImmLog2XLenNonZero, // user defined class 'UImmLog2XLenNonZeroAsmOperand'
+ MCK_UImm5, // user defined class 'anonymous_2450'
+ MCK_SImm12, // user defined class 'anonymous_2451'
+ MCK_SImm13Lsb0, // user defined class 'anonymous_2452'
+ MCK_UImm20LUI, // user defined class 'anonymous_2453'
+ MCK_UImm20AUIPC, // user defined class 'anonymous_2454'
+ MCK_ImmXLenLI, // user defined class 'anonymous_2455'
+ MCK_SImm6, // user defined class 'anonymous_3109'
+ MCK_SImm6NonZero, // user defined class 'anonymous_3110'
+ MCK_UImm7Lsb00, // user defined class 'anonymous_3111'
+ MCK_UImm8Lsb00, // user defined class 'anonymous_3112'
+ MCK_UImm8Lsb000, // user defined class 'anonymous_3113'
+ MCK_SImm9Lsb0, // user defined class 'anonymous_3114'
+ MCK_UImm9Lsb000, // user defined class 'anonymous_3115'
+ MCK_UImm10Lsb00NonZero, // user defined class 'anonymous_3116'
+ MCK_SImm10Lsb0000NonZero, // user defined class 'anonymous_3117'
+ MCK_SImm12Lsb0, // user defined class 'anonymous_3118'
+ NumMatchClassKinds
+};
+
+} // end anonymous namespace
+
+static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
+ return MCTargetAsmParser::Match_InvalidOperand;
+}
+
+static MatchClassKind matchTokenString(StringRef Name) {
+ switch (Name.size()) {
+ default: break;
+ case 1: // 2 strings to match.
+ switch (Name[0]) {
+ default: break;
+ case '(': // 1 string to match.
+ return MCK__40_; // "("
+ case ')': // 1 string to match.
+ return MCK__41_; // ")"
+ }
+ break;
+ }
+ return InvalidMatchClass;
+}
+
+/// isSubclass - Compute whether \p A is a subclass of \p B.
+static bool isSubclass(MatchClassKind A, MatchClassKind B) {
+ if (A == B)
+ return true;
+
+ switch (A) {
+ default:
+ return false;
+
+ case MCK_GPRX0:
+ return B == MCK_GPR;
+
+ case MCK_SP:
+ switch (B) {
+ default: return false;
+ case MCK_GPRNoX0: return true;
+ case MCK_GPR: return true;
+ }
+
+ case MCK_Reg7:
+ switch (B) {
+ default: return false;
+ case MCK_GPRC: return true;
+ case MCK_GPRTC: return true;
+ case MCK_GPRNoX0X2: return true;
+ case MCK_GPRNoX0: return true;
+ case MCK_GPR: return true;
+ }
+
+ case MCK_FPR32C:
+ return B == MCK_FPR32;
+
+ case MCK_FPR64C:
+ return B == MCK_FPR64;
+
+ case MCK_GPRC:
+ switch (B) {
+ default: return false;
+ case MCK_GPRNoX0X2: return true;
+ case MCK_GPRNoX0: return true;
+ case MCK_GPR: return true;
+ }
+
+ case MCK_GPRTC:
+ switch (B) {
+ default: return false;
+ case MCK_GPRNoX0X2: return true;
+ case MCK_GPRNoX0: return true;
+ case MCK_GPR: return true;
+ }
+
+ case MCK_GPRNoX0X2:
+ switch (B) {
+ default: return false;
+ case MCK_GPRNoX0: return true;
+ case MCK_GPR: return true;
+ }
+
+ case MCK_GPRNoX0:
+ return B == MCK_GPR;
+ }
+}
+
+static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
+ RISCVOperand &Operand = (RISCVOperand&)GOp;
+ if (Kind == InvalidMatchClass)
+ return MCTargetAsmParser::Match_InvalidOperand;
+
+ if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
+ return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
+ MCTargetAsmParser::Match_Success :
+ MCTargetAsmParser::Match_InvalidOperand;
+
+ switch (Kind) {
+ default: break;
+ // 'AtomicMemOpOperand' class
+ case MCK_AtomicMemOpOperand: {
+ DiagnosticPredicate DP(Operand.isGPR());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'BareSymbol' class
+ case MCK_BareSymbol: {
+ DiagnosticPredicate DP(Operand.isBareSymbol());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidBareSymbol;
+ break;
+ }
+ // 'CLUIImm' class
+ case MCK_CLUIImm: {
+ DiagnosticPredicate DP(Operand.isCLUIImm());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidCLUIImm;
+ break;
+ }
+ // 'CSRSystemRegister' class
+ case MCK_CSRSystemRegister: {
+ DiagnosticPredicate DP(Operand.isCSRSystemRegister());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidCSRSystemRegister;
+ break;
+ }
+ // 'CallSymbol' class
+ case MCK_CallSymbol: {
+ DiagnosticPredicate DP(Operand.isCallSymbol());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidCallSymbol;
+ break;
+ }
+ // 'FRMArg' class
+ case MCK_FRMArg: {
+ DiagnosticPredicate DP(Operand.isFRMArg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidFRMArg;
+ break;
+ }
+ // 'FenceArg' class
+ case MCK_FenceArg: {
+ DiagnosticPredicate DP(Operand.isFenceArg());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidFenceArg;
+ break;
+ }
+ // 'Imm' class
+ case MCK_Imm: {
+ DiagnosticPredicate DP(Operand.isImm());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ break;
+ }
+ // 'ImmZero' class
+ case MCK_ImmZero: {
+ DiagnosticPredicate DP(Operand.isImmZero());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidImmZero;
+ break;
+ }
+ // 'SImm21Lsb0JAL' class
+ case MCK_SImm21Lsb0JAL: {
+ DiagnosticPredicate DP(Operand.isSImm21Lsb0JAL());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidSImm21Lsb0JAL;
+ break;
+ }
+ // 'TPRelAddSymbol' class
+ case MCK_TPRelAddSymbol: {
+ DiagnosticPredicate DP(Operand.isTPRelAddSymbol());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidTPRelAddSymbol;
+ break;
+ }
+ // 'UImmLog2XLen' class
+ case MCK_UImmLog2XLen: {
+ DiagnosticPredicate DP(Operand.isUImmLog2XLen());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImmLog2XLen;
+ break;
+ }
+ // 'UImmLog2XLenNonZero' class
+ case MCK_UImmLog2XLenNonZero: {
+ DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero;
+ break;
+ }
+ // 'UImm5' class
+ case MCK_UImm5: {
+ DiagnosticPredicate DP(Operand.isUImm5());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImm5;
+ break;
+ }
+ // 'SImm12' class
+ case MCK_SImm12: {
+ DiagnosticPredicate DP(Operand.isSImm12());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidSImm12;
+ break;
+ }
+ // 'SImm13Lsb0' class
+ case MCK_SImm13Lsb0: {
+ DiagnosticPredicate DP(Operand.isSImm13Lsb0());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidSImm13Lsb0;
+ break;
+ }
+ // 'UImm20LUI' class
+ case MCK_UImm20LUI: {
+ DiagnosticPredicate DP(Operand.isUImm20LUI());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImm20LUI;
+ break;
+ }
+ // 'UImm20AUIPC' class
+ case MCK_UImm20AUIPC: {
+ DiagnosticPredicate DP(Operand.isUImm20AUIPC());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImm20AUIPC;
+ break;
+ }
+ // 'ImmXLenLI' class
+ case MCK_ImmXLenLI: {
+ DiagnosticPredicate DP(Operand.isImmXLenLI());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidImmXLenLI;
+ break;
+ }
+ // 'SImm6' class
+ case MCK_SImm6: {
+ DiagnosticPredicate DP(Operand.isSImm6());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidSImm6;
+ break;
+ }
+ // 'SImm6NonZero' class
+ case MCK_SImm6NonZero: {
+ DiagnosticPredicate DP(Operand.isSImm6NonZero());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidSImm6NonZero;
+ break;
+ }
+ // 'UImm7Lsb00' class
+ case MCK_UImm7Lsb00: {
+ DiagnosticPredicate DP(Operand.isUImm7Lsb00());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImm7Lsb00;
+ break;
+ }
+ // 'UImm8Lsb00' class
+ case MCK_UImm8Lsb00: {
+ DiagnosticPredicate DP(Operand.isUImm8Lsb00());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImm8Lsb00;
+ break;
+ }
+ // 'UImm8Lsb000' class
+ case MCK_UImm8Lsb000: {
+ DiagnosticPredicate DP(Operand.isUImm8Lsb000());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImm8Lsb000;
+ break;
+ }
+ // 'SImm9Lsb0' class
+ case MCK_SImm9Lsb0: {
+ DiagnosticPredicate DP(Operand.isSImm9Lsb0());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidSImm9Lsb0;
+ break;
+ }
+ // 'UImm9Lsb000' class
+ case MCK_UImm9Lsb000: {
+ DiagnosticPredicate DP(Operand.isUImm9Lsb000());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImm9Lsb000;
+ break;
+ }
+ // 'UImm10Lsb00NonZero' class
+ case MCK_UImm10Lsb00NonZero: {
+ DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero;
+ break;
+ }
+ // 'SImm10Lsb0000NonZero' class
+ case MCK_SImm10Lsb0000NonZero: {
+ DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero;
+ break;
+ }
+ // 'SImm12Lsb0' class
+ case MCK_SImm12Lsb0: {
+ DiagnosticPredicate DP(Operand.isSImm12Lsb0());
+ if (DP.isMatch())
+ return MCTargetAsmParser::Match_Success;
+ if (DP.isNearMatch())
+ return RISCVAsmParser::Match_InvalidSImm12Lsb0;
+ break;
+ }
+ } // end switch (Kind)
+
+ if (Operand.isReg()) {
+ MatchClassKind OpKind;
+ switch (Operand.getReg()) {
+ default: OpKind = InvalidMatchClass; break;
+ case RISCV::X0: OpKind = MCK_GPRX0; break;
+ case RISCV::X1: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X2: OpKind = MCK_SP; break;
+ case RISCV::X3: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X4: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X5: OpKind = MCK_GPRTC; break;
+ case RISCV::X6: OpKind = MCK_GPRTC; break;
+ case RISCV::X7: OpKind = MCK_GPRTC; break;
+ case RISCV::X8: OpKind = MCK_GPRC; break;
+ case RISCV::X9: OpKind = MCK_GPRC; break;
+ case RISCV::X10: OpKind = MCK_Reg7; break;
+ case RISCV::X11: OpKind = MCK_Reg7; break;
+ case RISCV::X12: OpKind = MCK_Reg7; break;
+ case RISCV::X13: OpKind = MCK_Reg7; break;
+ case RISCV::X14: OpKind = MCK_Reg7; break;
+ case RISCV::X15: OpKind = MCK_Reg7; break;
+ case RISCV::X16: OpKind = MCK_GPRTC; break;
+ case RISCV::X17: OpKind = MCK_GPRTC; break;
+ case RISCV::X18: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X19: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X20: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X21: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X22: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X23: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X24: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X25: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X26: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X27: OpKind = MCK_GPRNoX0X2; break;
+ case RISCV::X28: OpKind = MCK_GPRTC; break;
+ case RISCV::X29: OpKind = MCK_GPRTC; break;
+ case RISCV::X30: OpKind = MCK_GPRTC; break;
+ case RISCV::X31: OpKind = MCK_GPRTC; break;
+ case RISCV::F0_F: OpKind = MCK_FPR32; break;
+ case RISCV::F1_F: OpKind = MCK_FPR32; break;
+ case RISCV::F2_F: OpKind = MCK_FPR32; break;
+ case RISCV::F3_F: OpKind = MCK_FPR32; break;
+ case RISCV::F4_F: OpKind = MCK_FPR32; break;
+ case RISCV::F5_F: OpKind = MCK_FPR32; break;
+ case RISCV::F6_F: OpKind = MCK_FPR32; break;
+ case RISCV::F7_F: OpKind = MCK_FPR32; break;
+ case RISCV::F8_F: OpKind = MCK_FPR32C; break;
+ case RISCV::F9_F: OpKind = MCK_FPR32C; break;
+ case RISCV::F10_F: OpKind = MCK_FPR32C; break;
+ case RISCV::F11_F: OpKind = MCK_FPR32C; break;
+ case RISCV::F12_F: OpKind = MCK_FPR32C; break;
+ case RISCV::F13_F: OpKind = MCK_FPR32C; break;
+ case RISCV::F14_F: OpKind = MCK_FPR32C; break;
+ case RISCV::F15_F: OpKind = MCK_FPR32C; break;
+ case RISCV::F16_F: OpKind = MCK_FPR32; break;
+ case RISCV::F17_F: OpKind = MCK_FPR32; break;
+ case RISCV::F18_F: OpKind = MCK_FPR32; break;
+ case RISCV::F19_F: OpKind = MCK_FPR32; break;
+ case RISCV::F20_F: OpKind = MCK_FPR32; break;
+ case RISCV::F21_F: OpKind = MCK_FPR32; break;
+ case RISCV::F22_F: OpKind = MCK_FPR32; break;
+ case RISCV::F23_F: OpKind = MCK_FPR32; break;
+ case RISCV::F24_F: OpKind = MCK_FPR32; break;
+ case RISCV::F25_F: OpKind = MCK_FPR32; break;
+ case RISCV::F26_F: OpKind = MCK_FPR32; break;
+ case RISCV::F27_F: OpKind = MCK_FPR32; break;
+ case RISCV::F28_F: OpKind = MCK_FPR32; break;
+ case RISCV::F29_F: OpKind = MCK_FPR32; break;
+ case RISCV::F30_F: OpKind = MCK_FPR32; break;
+ case RISCV::F31_F: OpKind = MCK_FPR32; break;
+ case RISCV::F0_D: OpKind = MCK_FPR64; break;
+ case RISCV::F1_D: OpKind = MCK_FPR64; break;
+ case RISCV::F2_D: OpKind = MCK_FPR64; break;
+ case RISCV::F3_D: OpKind = MCK_FPR64; break;
+ case RISCV::F4_D: OpKind = MCK_FPR64; break;
+ case RISCV::F5_D: OpKind = MCK_FPR64; break;
+ case RISCV::F6_D: OpKind = MCK_FPR64; break;
+ case RISCV::F7_D: OpKind = MCK_FPR64; break;
+ case RISCV::F8_D: OpKind = MCK_FPR64C; break;
+ case RISCV::F9_D: OpKind = MCK_FPR64C; break;
+ case RISCV::F10_D: OpKind = MCK_FPR64C; break;
+ case RISCV::F11_D: OpKind = MCK_FPR64C; break;
+ case RISCV::F12_D: OpKind = MCK_FPR64C; break;
+ case RISCV::F13_D: OpKind = MCK_FPR64C; break;
+ case RISCV::F14_D: OpKind = MCK_FPR64C; break;
+ case RISCV::F15_D: OpKind = MCK_FPR64C; break;
+ case RISCV::F16_D: OpKind = MCK_FPR64; break;
+ case RISCV::F17_D: OpKind = MCK_FPR64; break;
+ case RISCV::F18_D: OpKind = MCK_FPR64; break;
+ case RISCV::F19_D: OpKind = MCK_FPR64; break;
+ case RISCV::F20_D: OpKind = MCK_FPR64; break;
+ case RISCV::F21_D: OpKind = MCK_FPR64; break;
+ case RISCV::F22_D: OpKind = MCK_FPR64; break;
+ case RISCV::F23_D: OpKind = MCK_FPR64; break;
+ case RISCV::F24_D: OpKind = MCK_FPR64; break;
+ case RISCV::F25_D: OpKind = MCK_FPR64; break;
+ case RISCV::F26_D: OpKind = MCK_FPR64; break;
+ case RISCV::F27_D: OpKind = MCK_FPR64; break;
+ case RISCV::F28_D: OpKind = MCK_FPR64; break;
+ case RISCV::F29_D: OpKind = MCK_FPR64; break;
+ case RISCV::F30_D: OpKind = MCK_FPR64; break;
+ case RISCV::F31_D: OpKind = MCK_FPR64; break;
+ }
+ return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
+ getDiagKindFromRegisterClass(Kind);
+ }
+
+ if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
+ return getDiagKindFromRegisterClass(Kind);
+
+ return MCTargetAsmParser::Match_InvalidOperand;
+}
+
+#ifndef NDEBUG
+const char *getMatchClassName(MatchClassKind Kind) {
+ switch (Kind) {
+ case InvalidMatchClass: return "InvalidMatchClass";
+ case OptionalMatchClass: return "OptionalMatchClass";
+ case MCK__40_: return "MCK__40_";
+ case MCK__41_: return "MCK__41_";
+ case MCK_GPRX0: return "MCK_GPRX0";
+ case MCK_SP: return "MCK_SP";
+ case MCK_Reg7: return "MCK_Reg7";
+ case MCK_FPR32C: return "MCK_FPR32C";
+ case MCK_FPR64C: return "MCK_FPR64C";
+ case MCK_GPRC: return "MCK_GPRC";
+ case MCK_GPRTC: return "MCK_GPRTC";
+ case MCK_GPRNoX0X2: return "MCK_GPRNoX0X2";
+ case MCK_GPRNoX0: return "MCK_GPRNoX0";
+ case MCK_FPR32: return "MCK_FPR32";
+ case MCK_FPR64: return "MCK_FPR64";
+ case MCK_GPR: return "MCK_GPR";
+ case MCK_AtomicMemOpOperand: return "MCK_AtomicMemOpOperand";
+ case MCK_BareSymbol: return "MCK_BareSymbol";
+ case MCK_CLUIImm: return "MCK_CLUIImm";
+ case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister";
+ case MCK_CallSymbol: return "MCK_CallSymbol";
+ case MCK_FRMArg: return "MCK_FRMArg";
+ case MCK_FenceArg: return "MCK_FenceArg";
+ case MCK_Imm: return "MCK_Imm";
+ case MCK_ImmZero: return "MCK_ImmZero";
+ case MCK_SImm21Lsb0JAL: return "MCK_SImm21Lsb0JAL";
+ case MCK_TPRelAddSymbol: return "MCK_TPRelAddSymbol";
+ case MCK_UImmLog2XLen: return "MCK_UImmLog2XLen";
+ case MCK_UImmLog2XLenNonZero: return "MCK_UImmLog2XLenNonZero";
+ case MCK_UImm5: return "MCK_UImm5";
+ case MCK_SImm12: return "MCK_SImm12";
+ case MCK_SImm13Lsb0: return "MCK_SImm13Lsb0";
+ case MCK_UImm20LUI: return "MCK_UImm20LUI";
+ case MCK_UImm20AUIPC: return "MCK_UImm20AUIPC";
+ case MCK_ImmXLenLI: return "MCK_ImmXLenLI";
+ case MCK_SImm6: return "MCK_SImm6";
+ case MCK_SImm6NonZero: return "MCK_SImm6NonZero";
+ case MCK_UImm7Lsb00: return "MCK_UImm7Lsb00";
+ case MCK_UImm8Lsb00: return "MCK_UImm8Lsb00";
+ case MCK_UImm8Lsb000: return "MCK_UImm8Lsb000";
+ case MCK_SImm9Lsb0: return "MCK_SImm9Lsb0";
+ case MCK_UImm9Lsb000: return "MCK_UImm9Lsb000";
+ case MCK_UImm10Lsb00NonZero: return "MCK_UImm10Lsb00NonZero";
+ case MCK_SImm10Lsb0000NonZero: return "MCK_SImm10Lsb0000NonZero";
+ case MCK_SImm12Lsb0: return "MCK_SImm12Lsb0";
+ case NumMatchClassKinds: return "NumMatchClassKinds";
+ }
+ llvm_unreachable("unhandled MatchClassKind!");
+}
+
+#endif // NDEBUG
+FeatureBitset RISCVAsmParser::
+ComputeAvailableFeatures(const FeatureBitset& FB) const {
+ FeatureBitset Features;
+ if ((FB[RISCV::FeatureStdExtM]))
+ Features.set(Feature_HasStdExtMBit);
+ if ((FB[RISCV::FeatureStdExtA]))
+ Features.set(Feature_HasStdExtABit);
+ if ((FB[RISCV::FeatureStdExtF]))
+ Features.set(Feature_HasStdExtFBit);
+ if ((FB[RISCV::FeatureStdExtD]))
+ Features.set(Feature_HasStdExtDBit);
+ if ((FB[RISCV::FeatureStdExtC]))
+ Features.set(Feature_HasStdExtCBit);
+ if ((FB[RISCV::FeatureRVCHints]))
+ Features.set(Feature_HasRVCHintsBit);
+ if ((FB[RISCV::Feature64Bit]))
+ Features.set(Feature_IsRV64Bit);
+ if ((!FB[RISCV::Feature64Bit]))
+ Features.set(Feature_IsRV32Bit);
+ if ((FB[RISCV::FeatureRV32E]))
+ Features.set(Feature_IsRV32EBit);
+ return Features;
+}
+
+static bool checkAsmTiedOperandConstraints(const RISCVAsmParser&AsmParser,
+ unsigned Kind,
+ const OperandVector &Operands,
+ uint64_t &ErrorInfo) {
+ assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
+ const uint8_t *Converter = ConversionTable[Kind];
+ for (const uint8_t *p = Converter; *p; p+= 2) {
+ switch (*p) {
+ case CVT_Tied: {
+ unsigned OpIdx = *(p+1);
+ assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
+ std::begin(TiedAsmOperandTable)) &&
+ "Tied operand not found");
+ unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
+ unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
+ if (OpndNum1 != OpndNum2) {
+ auto &SrcOp1 = Operands[OpndNum1];
+ auto &SrcOp2 = Operands[OpndNum2];
+ if (SrcOp1->isReg() && SrcOp2->isReg()) {
+ if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {
+ ErrorInfo = OpndNum2;
+ return false;
+ }
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ return true;
+}
+
+static const char *const MnemonicTable =
+ "\003add\004addi\005addiw\004addw\010amoadd.d\013amoadd.d.aq\015amoadd.d"
+ ".aqrl\013amoadd.d.rl\010amoadd.w\013amoadd.w.aq\015amoadd.w.aqrl\013amo"
+ "add.w.rl\010amoand.d\013amoand.d.aq\015amoand.d.aqrl\013amoand.d.rl\010"
+ "amoand.w\013amoand.w.aq\015amoand.w.aqrl\013amoand.w.rl\010amomax.d\013"
+ "amomax.d.aq\015amomax.d.aqrl\013amomax.d.rl\010amomax.w\013amomax.w.aq\015"
+ "amomax.w.aqrl\013amomax.w.rl\tamomaxu.d\014amomaxu.d.aq\016amomaxu.d.aq"
+ "rl\014amomaxu.d.rl\tamomaxu.w\014amomaxu.w.aq\016amomaxu.w.aqrl\014amom"
+ "axu.w.rl\010amomin.d\013amomin.d.aq\015amomin.d.aqrl\013amomin.d.rl\010"
+ "amomin.w\013amomin.w.aq\015amomin.w.aqrl\013amomin.w.rl\tamominu.d\014a"
+ "mominu.d.aq\016amominu.d.aqrl\014amominu.d.rl\tamominu.w\014amominu.w.a"
+ "q\016amominu.w.aqrl\014amominu.w.rl\007amoor.d\namoor.d.aq\014amoor.d.a"
+ "qrl\namoor.d.rl\007amoor.w\namoor.w.aq\014amoor.w.aqrl\namoor.w.rl\tamo"
+ "swap.d\014amoswap.d.aq\016amoswap.d.aqrl\014amoswap.d.rl\tamoswap.w\014"
+ "amoswap.w.aq\016amoswap.w.aqrl\014amoswap.w.rl\010amoxor.d\013amoxor.d."
+ "aq\015amoxor.d.aqrl\013amoxor.d.rl\010amoxor.w\013amoxor.w.aq\015amoxor"
+ ".w.aqrl\013amoxor.w.rl\003and\004andi\005auipc\003beq\004beqz\003bge\004"
+ "bgeu\004bgez\003bgt\004bgtu\004bgtz\003ble\004bleu\004blez\003blt\004bl"
+ "tu\004bltz\003bne\004bnez\005c.add\006c.addi\nc.addi16sp\nc.addi4spn\007"
+ "c.addiw\006c.addw\005c.and\006c.andi\006c.beqz\006c.bnez\010c.ebreak\005"
+ "c.fld\007c.fldsp\005c.flw\007c.flwsp\005c.fsd\007c.fsdsp\005c.fsw\007c."
+ "fswsp\003c.j\005c.jal\006c.jalr\004c.jr\004c.ld\006c.ldsp\004c.li\005c."
+ "lui\004c.lw\006c.lwsp\004c.mv\005c.nop\004c.or\004c.sd\006c.sdsp\006c.s"
+ "lli\010c.slli64\006c.srai\010c.srai64\006c.srli\010c.srli64\005c.sub\006"
+ "c.subw\004c.sw\006c.swsp\007c.unimp\005c.xor\004call\004csrc\005csrci\004"
+ "csrr\005csrrc\006csrrci\005csrrs\006csrrsi\005csrrw\006csrrwi\004csrs\005"
+ "csrsi\004csrw\005csrwi\003div\004divu\005divuw\004divw\006ebreak\005eca"
+ "ll\006fabs.d\006fabs.s\006fadd.d\006fadd.s\010fclass.d\010fclass.s\010f"
+ "cvt.d.l\tfcvt.d.lu\010fcvt.d.s\010fcvt.d.w\tfcvt.d.wu\010fcvt.l.d\010fc"
+ "vt.l.s\tfcvt.lu.d\tfcvt.lu.s\010fcvt.s.d\010fcvt.s.l\tfcvt.s.lu\010fcvt"
+ ".s.w\tfcvt.s.wu\010fcvt.w.d\010fcvt.w.s\tfcvt.wu.d\tfcvt.wu.s\006fdiv.d"
+ "\006fdiv.s\005fence\007fence.i\tfence.tso\005feq.d\005feq.s\005fge.d\005"
+ "fge.s\005fgt.d\005fgt.s\003fld\005fle.d\005fle.s\005flt.d\005flt.s\003f"
+ "lw\007fmadd.d\007fmadd.s\006fmax.d\006fmax.s\006fmin.d\006fmin.s\007fms"
+ "ub.d\007fmsub.s\006fmul.d\006fmul.s\005fmv.d\007fmv.d.x\005fmv.s\007fmv"
+ ".w.x\007fmv.x.d\007fmv.x.w\006fneg.d\006fneg.s\010fnmadd.d\010fnmadd.s\010"
+ "fnmsub.d\010fnmsub.s\005frcsr\007frflags\004frrm\004frsr\005fscsr\003fs"
+ "d\007fsflags\010fsflagsi\007fsgnj.d\007fsgnj.s\010fsgnjn.d\010fsgnjn.s\010"
+ "fsgnjx.d\010fsgnjx.s\007fsqrt.d\007fsqrt.s\004fsrm\005fsrmi\004fssr\006"
+ "fsub.d\006fsub.s\003fsw\001j\003jal\004jalr\002jr\002la\tla.tls.gd\tla."
+ "tls.ie\002lb\003lbu\002ld\002lh\003lhu\002li\003lla\004lr.d\007lr.d.aq\t"
+ "lr.d.aqrl\007lr.d.rl\004lr.w\007lr.w.aq\tlr.w.aqrl\007lr.w.rl\003lui\002"
+ "lw\003lwu\004mret\003mul\004mulh\006mulhsu\005mulhu\004mulw\002mv\003ne"
+ "g\004negw\003nop\003not\002or\003ori\007rdcycle\010rdcycleh\trdinstret\n"
+ "rdinstreth\006rdtime\007rdtimeh\003rem\004remu\005remuw\004remw\003ret\002"
+ "sb\004sc.d\007sc.d.aq\tsc.d.aqrl\007sc.d.rl\004sc.w\007sc.w.aq\tsc.w.aq"
+ "rl\007sc.w.rl\002sd\004seqz\006sext.w\nsfence.vma\003sgt\004sgtu\004sgt"
+ "z\002sh\003sll\004slli\005slliw\004sllw\003slt\004slti\005sltiu\004sltu"
+ "\004sltz\004snez\003sra\004srai\005sraiw\004sraw\004sret\003srl\004srli"
+ "\005srliw\004srlw\003sub\004subw\002sw\004tail\005unimp\004uret\003wfi\003"
+ "xor\004xori";
+
+// Feature bitsets.
+enum : uint8_t {
+ AMFBS_None,
+ AMFBS_HasStdExtA,
+ AMFBS_HasStdExtC,
+ AMFBS_HasStdExtD,
+ AMFBS_HasStdExtF,
+ AMFBS_HasStdExtM,
+ AMFBS_IsRV32,
+ AMFBS_IsRV64,
+ AMFBS_HasStdExtA_IsRV64,
+ AMFBS_HasStdExtC_HasRVCHints,
+ AMFBS_HasStdExtC_HasStdExtD,
+ AMFBS_HasStdExtC_IsRV32,
+ AMFBS_HasStdExtC_IsRV64,
+ AMFBS_HasStdExtD_IsRV64,
+ AMFBS_HasStdExtF_IsRV64,
+ AMFBS_HasStdExtM_IsRV64,
+ AMFBS_HasStdExtC_HasStdExtF_IsRV32,
+};
+
+static constexpr FeatureBitset FeatureBitsets[] = {
+ {}, // AMFBS_None
+ {Feature_HasStdExtABit, },
+ {Feature_HasStdExtCBit, },
+ {Feature_HasStdExtDBit, },
+ {Feature_HasStdExtFBit, },
+ {Feature_HasStdExtMBit, },
+ {Feature_IsRV32Bit, },
+ {Feature_IsRV64Bit, },
+ {Feature_HasStdExtABit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtCBit, Feature_HasRVCHintsBit, },
+ {Feature_HasStdExtCBit, Feature_HasStdExtDBit, },
+ {Feature_HasStdExtCBit, Feature_IsRV32Bit, },
+ {Feature_HasStdExtCBit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtDBit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtFBit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtMBit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtCBit, Feature_HasStdExtFBit, Feature_IsRV32Bit, },
+};
+
+namespace {
+ struct MatchEntry {
+ uint16_t Mnemonic;
+ uint16_t Opcode;
+ uint8_t ConvertFn;
+ uint8_t RequiredFeaturesIdx;
+ uint8_t Classes[5];
+ StringRef getMnemonic() const {
+ return StringRef(MnemonicTable + Mnemonic + 1,
+ MnemonicTable[Mnemonic]);
+ }
+ };
+
+ // Predicate for searching for an opcode.
+ struct LessOpcode {
+ bool operator()(const MatchEntry &LHS, StringRef RHS) {
+ return LHS.getMnemonic() < RHS;
+ }
+ bool operator()(StringRef LHS, const MatchEntry &RHS) {
+ return LHS < RHS.getMnemonic();
+ }
+ bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
+ return LHS.getMnemonic() < RHS.getMnemonic();
+ }
+ };
+} // end anonymous namespace
+
+static const MatchEntry MatchTable0[] = {
+ { 0 /* add */, RISCV::ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 0 /* add */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 0 /* add */, RISCV::PseudoAddTPRel, Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_TPRelAddSymbol }, },
+ { 4 /* addi */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 9 /* addiw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 15 /* addw */, RISCV::ADDW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 15 /* addw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 20 /* amoadd.d */, RISCV::AMOADD_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 29 /* amoadd.d.aq */, RISCV::AMOADD_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 41 /* amoadd.d.aqrl */, RISCV::AMOADD_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 55 /* amoadd.d.rl */, RISCV::AMOADD_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 67 /* amoadd.w */, RISCV::AMOADD_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 76 /* amoadd.w.aq */, RISCV::AMOADD_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 88 /* amoadd.w.aqrl */, RISCV::AMOADD_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 102 /* amoadd.w.rl */, RISCV::AMOADD_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 114 /* amoand.d */, RISCV::AMOAND_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 123 /* amoand.d.aq */, RISCV::AMOAND_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 135 /* amoand.d.aqrl */, RISCV::AMOAND_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 149 /* amoand.d.rl */, RISCV::AMOAND_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 161 /* amoand.w */, RISCV::AMOAND_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 170 /* amoand.w.aq */, RISCV::AMOAND_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 182 /* amoand.w.aqrl */, RISCV::AMOAND_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 196 /* amoand.w.rl */, RISCV::AMOAND_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 208 /* amomax.d */, RISCV::AMOMAX_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 217 /* amomax.d.aq */, RISCV::AMOMAX_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 229 /* amomax.d.aqrl */, RISCV::AMOMAX_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 243 /* amomax.d.rl */, RISCV::AMOMAX_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 255 /* amomax.w */, RISCV::AMOMAX_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 264 /* amomax.w.aq */, RISCV::AMOMAX_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 276 /* amomax.w.aqrl */, RISCV::AMOMAX_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 290 /* amomax.w.rl */, RISCV::AMOMAX_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 302 /* amomaxu.d */, RISCV::AMOMAXU_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 312 /* amomaxu.d.aq */, RISCV::AMOMAXU_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 325 /* amomaxu.d.aqrl */, RISCV::AMOMAXU_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 340 /* amomaxu.d.rl */, RISCV::AMOMAXU_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 353 /* amomaxu.w */, RISCV::AMOMAXU_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 363 /* amomaxu.w.aq */, RISCV::AMOMAXU_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 376 /* amomaxu.w.aqrl */, RISCV::AMOMAXU_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 391 /* amomaxu.w.rl */, RISCV::AMOMAXU_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 404 /* amomin.d */, RISCV::AMOMIN_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 413 /* amomin.d.aq */, RISCV::AMOMIN_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 425 /* amomin.d.aqrl */, RISCV::AMOMIN_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 439 /* amomin.d.rl */, RISCV::AMOMIN_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 451 /* amomin.w */, RISCV::AMOMIN_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 460 /* amomin.w.aq */, RISCV::AMOMIN_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 472 /* amomin.w.aqrl */, RISCV::AMOMIN_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 486 /* amomin.w.rl */, RISCV::AMOMIN_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 498 /* amominu.d */, RISCV::AMOMINU_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 508 /* amominu.d.aq */, RISCV::AMOMINU_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 521 /* amominu.d.aqrl */, RISCV::AMOMINU_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 536 /* amominu.d.rl */, RISCV::AMOMINU_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 549 /* amominu.w */, RISCV::AMOMINU_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 559 /* amominu.w.aq */, RISCV::AMOMINU_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 572 /* amominu.w.aqrl */, RISCV::AMOMINU_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 587 /* amominu.w.rl */, RISCV::AMOMINU_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 600 /* amoor.d */, RISCV::AMOOR_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 608 /* amoor.d.aq */, RISCV::AMOOR_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 619 /* amoor.d.aqrl */, RISCV::AMOOR_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 632 /* amoor.d.rl */, RISCV::AMOOR_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 643 /* amoor.w */, RISCV::AMOOR_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 651 /* amoor.w.aq */, RISCV::AMOOR_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 662 /* amoor.w.aqrl */, RISCV::AMOOR_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 675 /* amoor.w.rl */, RISCV::AMOOR_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 686 /* amoswap.d */, RISCV::AMOSWAP_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 696 /* amoswap.d.aq */, RISCV::AMOSWAP_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 709 /* amoswap.d.aqrl */, RISCV::AMOSWAP_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 724 /* amoswap.d.rl */, RISCV::AMOSWAP_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 737 /* amoswap.w */, RISCV::AMOSWAP_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 747 /* amoswap.w.aq */, RISCV::AMOSWAP_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 760 /* amoswap.w.aqrl */, RISCV::AMOSWAP_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 775 /* amoswap.w.rl */, RISCV::AMOSWAP_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 788 /* amoxor.d */, RISCV::AMOXOR_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 797 /* amoxor.d.aq */, RISCV::AMOXOR_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 809 /* amoxor.d.aqrl */, RISCV::AMOXOR_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 823 /* amoxor.d.rl */, RISCV::AMOXOR_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 835 /* amoxor.w */, RISCV::AMOXOR_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 844 /* amoxor.w.aq */, RISCV::AMOXOR_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 856 /* amoxor.w.aqrl */, RISCV::AMOXOR_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 870 /* amoxor.w.rl */, RISCV::AMOXOR_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 882 /* and */, RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 882 /* and */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 886 /* andi */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 891 /* auipc */, RISCV::AUIPC, Convert__Reg1_0__UImm20AUIPC1_1, AMFBS_None, { MCK_GPR, MCK_UImm20AUIPC }, },
+ { 897 /* beq */, RISCV::BEQ, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 901 /* beqz */, RISCV::BEQ, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 906 /* bge */, RISCV::BGE, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 910 /* bgeu */, RISCV::BGEU, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 915 /* bgez */, RISCV::BGE, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 920 /* bgt */, RISCV::BLT, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 924 /* bgtu */, RISCV::BLTU, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 929 /* bgtz */, RISCV::BLT, Convert__regX0__Reg1_0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 934 /* ble */, RISCV::BGE, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 938 /* bleu */, RISCV::BGEU, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 943 /* blez */, RISCV::BGE, Convert__regX0__Reg1_0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 948 /* blt */, RISCV::BLT, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 952 /* bltu */, RISCV::BLTU, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 957 /* bltz */, RISCV::BLT, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 962 /* bne */, RISCV::BNE, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 966 /* bnez */, RISCV::BNE, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, },
+ { 971 /* c.add */, RISCV::C_ADD_HINT, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_GPRNoX0 }, },
+ { 971 /* c.add */, RISCV::C_ADD, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
+ { 977 /* c.addi */, RISCV::C_ADDI_NOP, Convert__Reg1_0__Tie0_1_1__ImmZero1_1, AMFBS_HasStdExtC, { MCK_GPRX0, MCK_ImmZero }, },
+ { 977 /* c.addi */, RISCV::C_ADDI_HINT_X0, Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_SImm6NonZero }, },
+ { 977 /* c.addi */, RISCV::C_ADDI_HINT_IMM_ZERO, Convert__Reg1_0__Tie0_1_1__ImmZero1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRNoX0, MCK_ImmZero }, },
+ { 977 /* c.addi */, RISCV::C_ADDI, Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_SImm6NonZero }, },
+ { 984 /* c.addi16sp */, RISCV::C_ADDI16SP, Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, AMFBS_HasStdExtC, { MCK_SP, MCK_SImm10Lsb0000NonZero }, },
+ { 995 /* c.addi4spn */, RISCV::C_ADDI4SPN, Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, AMFBS_HasStdExtC, { MCK_GPRC, MCK_SP, MCK_UImm10Lsb00NonZero }, },
+ { 1006 /* c.addiw */, RISCV::C_ADDIW, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRNoX0, MCK_SImm6 }, },
+ { 1014 /* c.addw */, RISCV::C_ADDW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK_GPRC }, },
+ { 1021 /* c.and */, RISCV::C_AND, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_GPRC }, },
+ { 1027 /* c.andi */, RISCV::C_ANDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_SImm6 }, },
+ { 1034 /* c.beqz */, RISCV::C_BEQZ, Convert__Reg1_0__SImm9Lsb01_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_SImm9Lsb0 }, },
+ { 1041 /* c.bnez */, RISCV::C_BNEZ, Convert__Reg1_0__SImm9Lsb01_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_SImm9Lsb0 }, },
+ { 1048 /* c.ebreak */, RISCV::C_EBREAK, Convert_NoOperands, AMFBS_HasStdExtC, { }, },
+ { 1057 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1057 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1063 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1063 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1071 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1071 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1077 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1077 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1085 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1085 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1091 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1091 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1099 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1099 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1105 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1105 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1113 /* c.j */, RISCV::C_J, Convert__SImm12Lsb01_0, AMFBS_HasStdExtC, { MCK_SImm12Lsb0 }, },
+ { 1117 /* c.jal */, RISCV::C_JAL, Convert__SImm12Lsb01_0, AMFBS_HasStdExtC_IsRV32, { MCK_SImm12Lsb0 }, },
+ { 1123 /* c.jalr */, RISCV::C_JALR, Convert__Reg1_0, AMFBS_HasStdExtC, { MCK_GPRNoX0 }, },
+ { 1130 /* c.jr */, RISCV::C_JR, Convert__Reg1_0, AMFBS_HasStdExtC, { MCK_GPRNoX0 }, },
+ { 1135 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1135 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1140 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1140 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRNoX0, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1147 /* c.li */, RISCV::C_LI_HINT, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_SImm6 }, },
+ { 1147 /* c.li */, RISCV::C_LI, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_SImm6 }, },
+ { 1152 /* c.lui */, RISCV::C_LUI_HINT, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_CLUIImm }, },
+ { 1152 /* c.lui */, RISCV::C_LUI, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0X2, MCK_CLUIImm }, },
+ { 1158 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1158 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1163 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1163 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1170 /* c.mv */, RISCV::C_MV_HINT, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_GPRNoX0 }, },
+ { 1170 /* c.mv */, RISCV::C_MV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_GPRNoX0 }, },
+ { 1175 /* c.nop */, RISCV::C_NOP, Convert_NoOperands, AMFBS_HasStdExtC, { }, },
+ { 1175 /* c.nop */, RISCV::C_NOP_HINT, Convert__SImm6NonZero1_0, AMFBS_HasStdExtC_HasRVCHints, { MCK_SImm6NonZero }, },
+ { 1181 /* c.or */, RISCV::C_OR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_GPRC }, },
+ { 1186 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1186 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1191 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1191 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPR, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1198 /* c.slli */, RISCV::C_SLLI_HINT, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_UImmLog2XLenNonZero }, },
+ { 1198 /* c.slli */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_UImmLog2XLenNonZero }, },
+ { 1205 /* c.slli64 */, RISCV::C_SLLI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPR }, },
+ { 1214 /* c.srai */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
+ { 1221 /* c.srai64 */, RISCV::C_SRAI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRC }, },
+ { 1230 /* c.srli */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, },
+ { 1237 /* c.srli64 */, RISCV::C_SRLI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRC }, },
+ { 1246 /* c.sub */, RISCV::C_SUB, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_GPRC }, },
+ { 1252 /* c.subw */, RISCV::C_SUBW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK_GPRC }, },
+ { 1259 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1259 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, },
+ { 1264 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1264 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtC, { MCK_GPR, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, },
+ { 1271 /* c.unimp */, RISCV::C_UNIMP, Convert_NoOperands, AMFBS_HasStdExtC, { }, },
+ { 1279 /* c.xor */, RISCV::C_XOR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_GPRC }, },
+ { 1285 /* call */, RISCV::PseudoCALL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
+ { 1285 /* call */, RISCV::PseudoCALLReg, Convert__Reg1_0__CallSymbol1_1, AMFBS_None, { MCK_GPR, MCK_CallSymbol }, },
+ { 1290 /* csrc */, RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
+ { 1290 /* csrc */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1295 /* csrci */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1301 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, },
+ { 1306 /* csrrc */, RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
+ { 1306 /* csrrc */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1312 /* csrrci */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1319 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
+ { 1319 /* csrrs */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1325 /* csrrsi */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1332 /* csrrw */, RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, },
+ { 1332 /* csrrw */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1338 /* csrrwi */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1345 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
+ { 1345 /* csrs */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1350 /* csrsi */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1356 /* csrw */, RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, },
+ { 1356 /* csrw */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1361 /* csrwi */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, },
+ { 1367 /* div */, RISCV::DIV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 1371 /* divu */, RISCV::DIVU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 1376 /* divuw */, RISCV::DIVUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 1382 /* divw */, RISCV::DIVW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 1387 /* ebreak */, RISCV::EBREAK, Convert_NoOperands, AMFBS_None, { }, },
+ { 1394 /* ecall */, RISCV::ECALL, Convert_NoOperands, AMFBS_None, { }, },
+ { 1400 /* fabs.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1407 /* fabs.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1414 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1414 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 1421 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1421 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 1428 /* fclass.d */, RISCV::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, },
+ { 1437 /* fclass.s */, RISCV::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
+ { 1446 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, },
+ { 1446 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
+ { 1455 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, },
+ { 1455 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, },
+ { 1465 /* fcvt.d.s */, RISCV::FCVT_D_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR32 }, },
+ { 1474 /* fcvt.d.w */, RISCV::FCVT_D_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR }, },
+ { 1483 /* fcvt.d.wu */, RISCV::FCVT_D_WU, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR }, },
+ { 1493 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, },
+ { 1493 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
+ { 1502 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32 }, },
+ { 1502 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
+ { 1511 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, },
+ { 1511 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
+ { 1521 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32 }, },
+ { 1521 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
+ { 1531 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64 }, },
+ { 1531 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64, MCK_FRMArg }, },
+ { 1540 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR }, },
+ { 1540 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
+ { 1549 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR }, },
+ { 1549 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
+ { 1559 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, },
+ { 1559 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
+ { 1568 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, },
+ { 1568 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, },
+ { 1578 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, },
+ { 1578 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
+ { 1587 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
+ { 1587 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
+ { 1596 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, },
+ { 1596 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, },
+ { 1606 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
+ { 1606 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, },
+ { 1616 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1616 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 1623 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1623 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 1630 /* fence */, RISCV::FENCE, Convert__imm_95_15__imm_95_15, AMFBS_None, { }, },
+ { 1630 /* fence */, RISCV::FENCE, Convert__FenceArg1_0__FenceArg1_1, AMFBS_None, { MCK_FenceArg, MCK_FenceArg }, },
+ { 1636 /* fence.i */, RISCV::FENCE_I, Convert_NoOperands, AMFBS_None, { }, },
+ { 1644 /* fence.tso */, RISCV::FENCE_TSO, Convert_NoOperands, AMFBS_None, { }, },
+ { 1654 /* feq.d */, RISCV::FEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
+ { 1660 /* feq.s */, RISCV::FEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
+ { 1666 /* fge.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
+ { 1672 /* fge.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
+ { 1678 /* fgt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
+ { 1684 /* fgt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
+ { 1690 /* fld */, RISCV::PseudoFLD, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
+ { 1690 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 1690 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 1694 /* fle.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
+ { 1700 /* fle.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
+ { 1706 /* flt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, },
+ { 1712 /* flt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, },
+ { 1718 /* flw */, RISCV::PseudoFLW, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
+ { 1718 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 1718 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 1722 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1722 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 1730 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1730 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 1738 /* fmax.d */, RISCV::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1745 /* fmax.s */, RISCV::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1752 /* fmin.d */, RISCV::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1759 /* fmin.s */, RISCV::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1766 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1766 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 1774 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1774 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 1782 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1782 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 1789 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1789 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 1796 /* fmv.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1802 /* fmv.d.x */, RISCV::FMV_D_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, },
+ { 1810 /* fmv.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1816 /* fmv.w.x */, RISCV::FMV_W_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, },
+ { 1824 /* fmv.x.d */, RISCV::FMV_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, },
+ { 1832 /* fmv.x.w */, RISCV::FMV_X_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, },
+ { 1840 /* fneg.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1847 /* fneg.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
+ { 1854 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1854 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 1863 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1863 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 1872 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1872 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 1881 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1881 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 1890 /* frcsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtF, { MCK_GPR }, },
+ { 1896 /* frflags */, RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtF, { MCK_GPR }, },
+ { 1904 /* frrm */, RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtF, { MCK_GPR }, },
+ { 1909 /* frsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtF, { MCK_GPR }, },
+ { 1914 /* fscsr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, },
+ { 1914 /* fscsr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, },
+ { 1920 /* fsd */, RISCV::PseudoFSD, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, },
+ { 1920 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 1920 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 1924 /* fsflags */, RISCV::CSRRW, Convert__regX0__imm_95_1__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, },
+ { 1924 /* fsflags */, RISCV::CSRRW, Convert__Reg1_0__imm_95_1__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, },
+ { 1932 /* fsflagsi */, RISCV::CSRRWI, Convert__regX0__imm_95_1__UImm51_0, AMFBS_HasStdExtF, { MCK_UImm5 }, },
+ { 1932 /* fsflagsi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_1__UImm51_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_UImm5 }, },
+ { 1941 /* fsgnj.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1949 /* fsgnj.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1957 /* fsgnjn.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1966 /* fsgnjn.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1975 /* fsgnjx.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 1984 /* fsgnjx.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 1993 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, },
+ { 1993 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 2001 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, },
+ { 2001 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 2009 /* fsrm */, RISCV::CSRRW, Convert__regX0__imm_95_2__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, },
+ { 2009 /* fsrm */, RISCV::CSRRW, Convert__Reg1_0__imm_95_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, },
+ { 2014 /* fsrmi */, RISCV::CSRRWI, Convert__regX0__imm_95_2__UImm51_0, AMFBS_HasStdExtF, { MCK_UImm5 }, },
+ { 2014 /* fsrmi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_2__UImm51_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_UImm5 }, },
+ { 2020 /* fssr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, },
+ { 2020 /* fssr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, },
+ { 2025 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, },
+ { 2025 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, },
+ { 2032 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, },
+ { 2032 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, },
+ { 2039 /* fsw */, RISCV::PseudoFSW, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, },
+ { 2039 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2039 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2043 /* j */, RISCV::JAL, Convert__regX0__SImm21Lsb0JAL1_0, AMFBS_None, { MCK_SImm21Lsb0JAL }, },
+ { 2045 /* jal */, RISCV::JAL, Convert__regX1__SImm21Lsb0JAL1_0, AMFBS_None, { MCK_SImm21Lsb0JAL }, },
+ { 2045 /* jal */, RISCV::JAL, Convert__Reg1_0__SImm21Lsb0JAL1_1, AMFBS_None, { MCK_GPR, MCK_SImm21Lsb0JAL }, },
+ { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
+ { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, },
+ { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, },
+ { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, },
+ { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2057 /* la */, RISCV::PseudoLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2060 /* la.tls.gd */, RISCV::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2070 /* la.tls.ie */, RISCV::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2080 /* lb */, RISCV::PseudoLB, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2080 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2080 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2083 /* lbu */, RISCV::PseudoLBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2083 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2083 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2087 /* ld */, RISCV::PseudoLD, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
+ { 2087 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2087 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2090 /* lh */, RISCV::PseudoLH, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2090 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2090 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2093 /* lhu */, RISCV::PseudoLHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2093 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2093 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2097 /* li */, RISCV::PseudoLI, Convert__Reg1_0__ImmXLenLI1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI }, },
+ { 2100 /* lla */, RISCV::PseudoLLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2104 /* lr.d */, RISCV::LR_D, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2109 /* lr.d.aq */, RISCV::LR_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2117 /* lr.d.aqrl */, RISCV::LR_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2127 /* lr.d.rl */, RISCV::LR_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2135 /* lr.w */, RISCV::LR_W, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2140 /* lr.w.aq */, RISCV::LR_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2148 /* lr.w.aqrl */, RISCV::LR_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2158 /* lr.w.rl */, RISCV::LR_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2166 /* lui */, RISCV::LUI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_None, { MCK_GPR, MCK_UImm20LUI }, },
+ { 2170 /* lw */, RISCV::PseudoLW, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, },
+ { 2170 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2170 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2173 /* lwu */, RISCV::PseudoLWU, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, },
+ { 2173 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2173 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2177 /* mret */, RISCV::MRET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, },
+ { 2182 /* mul */, RISCV::MUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2186 /* mulh */, RISCV::MULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2191 /* mulhsu */, RISCV::MULHSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2198 /* mulhu */, RISCV::MULHU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2204 /* mulw */, RISCV::MULW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2209 /* mv */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2212 /* neg */, RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2216 /* negw */, RISCV::SUBW, Convert__Reg1_0__regX0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
+ { 2221 /* nop */, RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, },
+ { 2225 /* not */, RISCV::XORI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2229 /* or */, RISCV::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2229 /* or */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 2232 /* ori */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 2236 /* rdcycle */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, },
+ { 2244 /* rdcycleh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, },
+ { 2253 /* rdinstret */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, },
+ { 2263 /* rdinstreth */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, },
+ { 2274 /* rdtime */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, },
+ { 2281 /* rdtimeh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, },
+ { 2289 /* rem */, RISCV::REM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2293 /* remu */, RISCV::REMU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2298 /* remuw */, RISCV::REMUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2304 /* remw */, RISCV::REMW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2309 /* ret */, RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, { }, },
+ { 2313 /* sb */, RISCV::PseudoSB, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
+ { 2313 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2313 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2316 /* sc.d */, RISCV::SC_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2321 /* sc.d.aq */, RISCV::SC_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2329 /* sc.d.aqrl */, RISCV::SC_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2339 /* sc.d.rl */, RISCV::SC_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2347 /* sc.w */, RISCV::SC_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2352 /* sc.w.aq */, RISCV::SC_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2360 /* sc.w.aqrl */, RISCV::SC_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2370 /* sc.w.rl */, RISCV::SC_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, },
+ { 2378 /* sd */, RISCV::PseudoSD, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
+ { 2378 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2378 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2381 /* seqz */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2386 /* sext.w */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, },
+ { 2393 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__regX0__regX0, AMFBS_None, { }, },
+ { 2393 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, },
+ { 2393 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2404 /* sgt */, RISCV::SLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2408 /* sgtu */, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2413 /* sgtz */, RISCV::SLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2418 /* sh */, RISCV::PseudoSH, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
+ { 2418 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2418 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2421 /* sll */, RISCV::SLL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2421 /* sll */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
+ { 2425 /* slli */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
+ { 2430 /* slliw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 2436 /* sllw */, RISCV::SLLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2436 /* sllw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 2441 /* slt */, RISCV::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2441 /* slt */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 2445 /* slti */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 2450 /* sltiu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 2456 /* sltu */, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2456 /* sltu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 2461 /* sltz */, RISCV::SLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2466 /* snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, },
+ { 2471 /* sra */, RISCV::SRA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2471 /* sra */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
+ { 2475 /* srai */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
+ { 2480 /* sraiw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 2486 /* sraw */, RISCV::SRAW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2486 /* sraw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 2491 /* sret */, RISCV::SRET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, },
+ { 2496 /* srl */, RISCV::SRL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2496 /* srl */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
+ { 2500 /* srli */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, },
+ { 2505 /* srliw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 2511 /* srlw */, RISCV::SRLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2511 /* srlw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, },
+ { 2516 /* sub */, RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2520 /* subw */, RISCV::SUBW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2525 /* sw */, RISCV::PseudoSW, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, },
+ { 2525 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2525 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, },
+ { 2528 /* tail */, RISCV::PseudoTAIL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, },
+ { 2533 /* unimp */, RISCV::UNIMP, Convert_NoOperands, AMFBS_None, { }, },
+ { 2539 /* uret */, RISCV::URET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, },
+ { 2544 /* wfi */, RISCV::WFI, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, },
+ { 2548 /* xor */, RISCV::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, },
+ { 2548 /* xor */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+ { 2552 /* xori */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, },
+};
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Format.h"
+
+unsigned RISCVAsmParser::
+MatchInstructionImpl(const OperandVector &Operands,
+ MCInst &Inst,
+ uint64_t &ErrorInfo,
+ FeatureBitset &MissingFeatures,
+ bool matchingInlineAsm, unsigned VariantID) {
+ // Eliminate obvious mismatches.
+ if (Operands.size() > 6) {
+ ErrorInfo = 6;
+ return Match_InvalidOperand;
+ }
+
+ // Get the current feature set.
+ const FeatureBitset &AvailableFeatures = getAvailableFeatures();
+
+ // Get the instruction mnemonic, which is the first token.
+ StringRef Mnemonic = ((RISCVOperand&)*Operands[0]).getToken();
+
+ // Process all MnemonicAliases to remap the mnemonic.
+ applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
+
+ // Some state to try to produce better error messages.
+ bool HadMatchOtherThanFeatures = false;
+ bool HadMatchOtherThanPredicate = false;
+ unsigned RetCode = Match_InvalidOperand;
+ MissingFeatures.set();
+ // Set ErrorInfo to the operand that mismatches if it is
+ // wrong for all instances of the instruction.
+ ErrorInfo = ~0ULL;
+ // Find the appropriate table for this asm variant.
+ const MatchEntry *Start, *End;
+ switch (VariantID) {
+ default: llvm_unreachable("invalid variant!");
+ case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
+ }
+ // Search the table.
+ auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
+
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
+ std::distance(MnemonicRange.first, MnemonicRange.second) <<
+ " encodings with mnemonic '" << Mnemonic << "'\n");
+
+ // Return a more specific error code if no mnemonics match.
+ if (MnemonicRange.first == MnemonicRange.second)
+ return Match_MnemonicFail;
+
+ for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
+ it != ie; ++it) {
+ const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
+ bool HasRequiredFeatures =
+ (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
+ << MII.getName(it->Opcode) << "\n");
+ // equal_range guarantees that instruction mnemonic matches.
+ assert(Mnemonic == it->getMnemonic());
+ bool OperandsValid = true;
+ for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 5; ++FormalIdx) {
+ auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << " Matching formal operand class " << getMatchClassName(Formal)
+ << " against actual operand at index " << ActualIdx);
+ if (ActualIdx < Operands.size())
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
+ Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
+ else
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
+ if (ActualIdx >= Operands.size()) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range ");
+ OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
+ if (!OperandsValid) ErrorInfo = ActualIdx;
+ break;
+ }
+ MCParsedAsmOperand &Actual = *Operands[ActualIdx];
+ unsigned Diag = validateOperandClass(Actual, Formal);
+ if (Diag == Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "match success using generic matcher\n");
+ ++ActualIdx;
+ continue;
+ }
+ // If the generic handler indicates an invalid operand
+ // failure, check for a special case.
+ if (Diag != Match_Success) {
+ unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
+ if (TargetDiag == Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "match success using target matcher\n");
+ ++ActualIdx;
+ continue;
+ }
+ // If the target matcher returned a specific error code use
+ // that, else use the one from the generic matcher.
+ if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
+ Diag = TargetDiag;
+ }
+ // If current formal operand wasn't matched and it is optional
+ // then try to match next formal operand
+ if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
+ continue;
+ }
+ // If this operand is broken for all of the instances of this
+ // mnemonic, keep track of it so we can report loc info.
+ // If we already had a match that only failed due to a
+ // target predicate, that diagnostic is preferred.
+ if (!HadMatchOtherThanPredicate &&
+ (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
+ if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
+ RetCode = Diag;
+ ErrorInfo = ActualIdx;
+ }
+ // Otherwise, just reject this instance of the mnemonic.
+ OperandsValid = false;
+ break;
+ }
+
+ if (!OperandsValid) {
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
+ "operand mismatches, ignoring "
+ "this opcode\n");
+ continue;
+ }
+ if (!HasRequiredFeatures) {
+ HadMatchOtherThanFeatures = true;
+ FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
+ DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
+ for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
+ if (NewMissingFeatures[I])
+ dbgs() << ' ' << I;
+ dbgs() << "\n");
+ if (NewMissingFeatures.count() <=
+ MissingFeatures.count())
+ MissingFeatures = NewMissingFeatures;
+ continue;
+ }
+
+ Inst.clear();
+
+ Inst.setOpcode(it->Opcode);
+ // We have a potential match but have not rendered the operands.
+ // Check the target predicate to handle any context sensitive
+ // constraints.
+ // For example, Ties that are referenced multiple times must be
+ // checked here to ensure the input is the same for each match
+ // constraints. If we leave it any later the ties will have been
+ // canonicalized
+ unsigned MatchResult;
+ if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
+ Inst.clear();
+ DEBUG_WITH_TYPE(
+ "asm-matcher",
+ dbgs() << "Early target match predicate failed with diag code "
+ << MatchResult << "\n");
+ RetCode = MatchResult;
+ HadMatchOtherThanPredicate = true;
+ continue;
+ }
+
+ if (matchingInlineAsm) {
+ convertToMapAndConstraints(it->ConvertFn, Operands);
+ if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
+ return Match_InvalidTiedOperand;
+
+ return Match_Success;
+ }
+
+ // We have selected a definite instruction, convert the parsed
+ // operands into the appropriate MCInst.
+ convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
+
+ // We have a potential match. Check the target predicate to
+ // handle any context sensitive constraints.
+ if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
+ DEBUG_WITH_TYPE("asm-matcher",
+ dbgs() << "Target match predicate failed with diag code "
+ << MatchResult << "\n");
+ Inst.clear();
+ RetCode = MatchResult;
+ HadMatchOtherThanPredicate = true;
+ continue;
+ }
+
+ if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
+ return Match_InvalidTiedOperand;
+
+ DEBUG_WITH_TYPE(
+ "asm-matcher",
+ dbgs() << "Opcode result: complete match, selecting this opcode\n");
+ return Match_Success;
+ }
+
+ // Okay, we had no match. Try to return a useful error code.
+ if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
+ return RetCode;
+
+ ErrorInfo = 0;
+ return Match_MissingFeature;
+}
+
+namespace {
+ struct OperandMatchEntry {
+ uint16_t Mnemonic;
+ uint8_t OperandMask;
+ uint8_t Class;
+ uint8_t RequiredFeaturesIdx;
+
+ StringRef getMnemonic() const {
+ return StringRef(MnemonicTable + Mnemonic + 1,
+ MnemonicTable[Mnemonic]);
+ }
+ };
+
+ // Predicate for searching for an opcode.
+ struct LessOpcodeOperand {
+ bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
+ return LHS.getMnemonic() < RHS;
+ }
+ bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
+ return LHS < RHS.getMnemonic();
+ }
+ bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
+ return LHS.getMnemonic() < RHS.getMnemonic();
+ }
+ };
+} // end anonymous namespace
+
+static const OperandMatchEntry OperandMatchTable[133] = {
+ /* Operand List Mnemonic, Mask, Operand Class, Features */
+ { 0 /* add */, 8 /* 3 */, MCK_TPRelAddSymbol, AMFBS_None },
+ { 20 /* amoadd.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 29 /* amoadd.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 41 /* amoadd.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 55 /* amoadd.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 67 /* amoadd.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 76 /* amoadd.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 88 /* amoadd.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 102 /* amoadd.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 114 /* amoand.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 123 /* amoand.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 135 /* amoand.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 149 /* amoand.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 161 /* amoand.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 170 /* amoand.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 182 /* amoand.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 196 /* amoand.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 208 /* amomax.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 217 /* amomax.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 229 /* amomax.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 243 /* amomax.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 255 /* amomax.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 264 /* amomax.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 276 /* amomax.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 290 /* amomax.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 302 /* amomaxu.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 312 /* amomaxu.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 325 /* amomaxu.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 340 /* amomaxu.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 353 /* amomaxu.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 363 /* amomaxu.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 376 /* amomaxu.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 391 /* amomaxu.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 404 /* amomin.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 413 /* amomin.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 425 /* amomin.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 439 /* amomin.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 451 /* amomin.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 460 /* amomin.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 472 /* amomin.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 486 /* amomin.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 498 /* amominu.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 508 /* amominu.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 521 /* amominu.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 536 /* amominu.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 549 /* amominu.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 559 /* amominu.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 572 /* amominu.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 587 /* amominu.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 600 /* amoor.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 608 /* amoor.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 619 /* amoor.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 632 /* amoor.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 643 /* amoor.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 651 /* amoor.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 662 /* amoor.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 675 /* amoor.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 686 /* amoswap.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 696 /* amoswap.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 709 /* amoswap.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 724 /* amoswap.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 737 /* amoswap.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 747 /* amoswap.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 760 /* amoswap.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 775 /* amoswap.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 788 /* amoxor.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 797 /* amoxor.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 809 /* amoxor.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 823 /* amoxor.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 835 /* amoxor.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 844 /* amoxor.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 856 /* amoxor.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 870 /* amoxor.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 1285 /* call */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
+ { 1285 /* call */, 2 /* 1 */, MCK_CallSymbol, AMFBS_None },
+ { 1290 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1290 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1295 /* csrci */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1301 /* csrr */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1306 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1306 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1312 /* csrrci */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1319 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1319 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1325 /* csrrsi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1332 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1332 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1338 /* csrrwi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1345 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1345 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1350 /* csrsi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1356 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1356 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1361 /* csrwi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None },
+ { 1690 /* fld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
+ { 1718 /* flw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
+ { 1920 /* fsd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD },
+ { 2039 /* fsw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF },
+ { 2043 /* j */, 1 /* 0 */, MCK_SImm21Lsb0JAL, AMFBS_None },
+ { 2045 /* jal */, 1 /* 0 */, MCK_SImm21Lsb0JAL, AMFBS_None },
+ { 2045 /* jal */, 2 /* 1 */, MCK_SImm21Lsb0JAL, AMFBS_None },
+ { 2057 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2060 /* la.tls.gd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2070 /* la.tls.ie */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2080 /* lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2083 /* lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2087 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
+ { 2090 /* lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2093 /* lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2100 /* lla */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2104 /* lr.d */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 2109 /* lr.d.aq */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 2117 /* lr.d.aqrl */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 2127 /* lr.d.rl */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 2135 /* lr.w */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 2140 /* lr.w.aq */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 2148 /* lr.w.aqrl */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 2158 /* lr.w.rl */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 2170 /* lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2173 /* lwu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
+ { 2313 /* sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2316 /* sc.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 2321 /* sc.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 2329 /* sc.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 2339 /* sc.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 },
+ { 2347 /* sc.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 2352 /* sc.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 2360 /* sc.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 2370 /* sc.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA },
+ { 2378 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 },
+ { 2418 /* sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2525 /* sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None },
+ { 2528 /* tail */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None },
+};
+
+OperandMatchResultTy RISCVAsmParser::
+tryCustomParseOperand(OperandVector &Operands,
+ unsigned MCK) {
+
+ switch(MCK) {
+ case MCK_AtomicMemOpOperand:
+ return parseAtomicMemOp(Operands);
+ case MCK_BareSymbol:
+ return parseBareSymbol(Operands);
+ case MCK_CSRSystemRegister:
+ return parseCSRSystemRegister(Operands);
+ case MCK_CallSymbol:
+ return parseCallSymbol(Operands);
+ case MCK_SImm21Lsb0JAL:
+ return parseJALOffset(Operands);
+ case MCK_TPRelAddSymbol:
+ return parseOperandWithModifier(Operands);
+ default:
+ return MatchOperand_NoMatch;
+ }
+ return MatchOperand_NoMatch;
+}
+
+OperandMatchResultTy RISCVAsmParser::
+MatchOperandParserImpl(OperandVector &Operands,
+ StringRef Mnemonic,
+ bool ParseForAllFeatures) {
+ // Get the current feature set.
+ const FeatureBitset &AvailableFeatures = getAvailableFeatures();
+
+ // Get the next operand index.
+ unsigned NextOpNum = Operands.size() - 1;
+ // Search the table.
+ auto MnemonicRange =
+ std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
+ Mnemonic, LessOpcodeOperand());
+
+ if (MnemonicRange.first == MnemonicRange.second)
+ return MatchOperand_NoMatch;
+
+ for (const OperandMatchEntry *it = MnemonicRange.first,
+ *ie = MnemonicRange.second; it != ie; ++it) {
+ // equal_range guarantees that instruction mnemonic matches.
+ assert(Mnemonic == it->getMnemonic());
+
+ // check if the available features match
+ const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
+ if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
+ continue;
+
+ // check if the operand in question has a custom parser.
+ if (!(it->OperandMask & (1 << NextOpNum)))
+ continue;
+
+ // call custom parse method to handle the operand
+ OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
+ if (Result != MatchOperand_NoMatch)
+ return Result;
+ }
+
+ // Okay, we had no match.
+ return MatchOperand_NoMatch;
+}
+
+#endif // GET_MATCHER_IMPLEMENTATION
+
+
+#ifdef GET_MNEMONIC_SPELL_CHECKER
+#undef GET_MNEMONIC_SPELL_CHECKER
+
+static std::string RISCVMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
+ const unsigned MaxEditDist = 2;
+ std::vector<StringRef> Candidates;
+ StringRef Prev = "";
+
+ // Find the appropriate table for this asm variant.
+ const MatchEntry *Start, *End;
+ switch (VariantID) {
+ default: llvm_unreachable("invalid variant!");
+ case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
+ }
+
+ for (auto I = Start; I < End; I++) {
+ // Ignore unsupported instructions.
+ const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
+ if ((FBS & RequiredFeatures) != RequiredFeatures)
+ continue;
+
+ StringRef T = I->getMnemonic();
+ // Avoid recomputing the edit distance for the same string.
+ if (T.equals(Prev))
+ continue;
+
+ Prev = T;
+ unsigned Dist = S.edit_distance(T, false, MaxEditDist);
+ if (Dist <= MaxEditDist)
+ Candidates.push_back(T);
+ }
+
+ if (Candidates.empty())
+ return "";
+
+ std::string Res = ", did you mean: ";
+ unsigned i = 0;
+ for( ; i < Candidates.size() - 1; i++)
+ Res += Candidates[i].str() + ", ";
+ return Res + Candidates[i].str() + "?";
+}
+
+#endif // GET_MNEMONIC_SPELL_CHECKER
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenAsmWriter.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenAsmWriter.inc
new file mode 100644
index 0000000..841f5c0
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenAsmWriter.inc
@@ -0,0 +1,2475 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Assembly Writer Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+void RISCVInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
+ static const char AsmStrs[] = {
+ /* 0 */ 'c', '.', 's', 'r', 'a', 'i', '6', '4', 9, 0,
+ /* 10 */ 'c', '.', 's', 'l', 'l', 'i', '6', '4', 9, 0,
+ /* 20 */ 'c', '.', 's', 'r', 'l', 'i', '6', '4', 9, 0,
+ /* 30 */ 'l', 'l', 'a', 9, 0,
+ /* 35 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0,
+ /* 47 */ 's', 'r', 'a', 9, 0,
+ /* 52 */ 'l', 'b', 9, 0,
+ /* 56 */ 's', 'b', 9, 0,
+ /* 60 */ 'c', '.', 's', 'u', 'b', 9, 0,
+ /* 67 */ 'a', 'u', 'i', 'p', 'c', 9, 0,
+ /* 74 */ 'c', 's', 'r', 'r', 'c', 9, 0,
+ /* 81 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 89 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 98 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0,
+ /* 108 */ 's', 'c', '.', 'd', 9, 0,
+ /* 114 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 122 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 131 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 141 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0,
+ /* 151 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0,
+ /* 161 */ 'f', 'l', 'e', '.', 'd', 9, 0,
+ /* 168 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0,
+ /* 177 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0,
+ /* 187 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0,
+ /* 195 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0,
+ /* 203 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0,
+ /* 213 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0,
+ /* 223 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0,
+ /* 234 */ 'f', 'e', 'q', '.', 'd', 9, 0,
+ /* 241 */ 'l', 'r', '.', 'd', 9, 0,
+ /* 247 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0,
+ /* 256 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0,
+ /* 266 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0,
+ /* 276 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0,
+ /* 286 */ 'f', 'l', 't', '.', 'd', 9, 0,
+ /* 293 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0,
+ /* 302 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0,
+ /* 313 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0,
+ /* 324 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0,
+ /* 335 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0,
+ /* 346 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0,
+ /* 354 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0,
+ /* 364 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0,
+ /* 373 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0,
+ /* 381 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0,
+ /* 391 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0,
+ /* 401 */ 'c', '.', 'a', 'd', 'd', 9, 0,
+ /* 408 */ 'l', 'a', '.', 't', 'l', 's', '.', 'g', 'd', 9, 0,
+ /* 419 */ 'c', '.', 'l', 'd', 9, 0,
+ /* 425 */ 'c', '.', 'f', 'l', 'd', 9, 0,
+ /* 432 */ 'c', '.', 'a', 'n', 'd', 9, 0,
+ /* 439 */ 'c', '.', 's', 'd', 9, 0,
+ /* 445 */ 'c', '.', 'f', 's', 'd', 9, 0,
+ /* 452 */ 'f', 'e', 'n', 'c', 'e', 9, 0,
+ /* 459 */ 'b', 'g', 'e', 9, 0,
+ /* 464 */ 'l', 'a', '.', 't', 'l', 's', '.', 'i', 'e', 9, 0,
+ /* 475 */ 'b', 'n', 'e', 9, 0,
+ /* 480 */ 'm', 'u', 'l', 'h', 9, 0,
+ /* 486 */ 's', 'h', 9, 0,
+ /* 490 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0,
+ /* 499 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0,
+ /* 507 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0,
+ /* 515 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0,
+ /* 523 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0,
+ /* 531 */ 'w', 'f', 'i', 9, 0,
+ /* 536 */ 'c', '.', 'l', 'i', 9, 0,
+ /* 542 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0,
+ /* 550 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0,
+ /* 558 */ 'x', 'o', 'r', 'i', 9, 0,
+ /* 564 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0,
+ /* 572 */ 's', 'l', 't', 'i', 9, 0,
+ /* 578 */ 'c', '.', 'l', 'u', 'i', 9, 0,
+ /* 585 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0,
+ /* 593 */ 'c', '.', 'j', 9, 0,
+ /* 598 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0,
+ /* 608 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0,
+ /* 618 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0,
+ /* 628 */ 'c', '.', 'j', 'a', 'l', 9, 0,
+ /* 635 */ 't', 'a', 'i', 'l', 9, 0,
+ /* 641 */ 'e', 'c', 'a', 'l', 'l', 9, 0,
+ /* 648 */ 's', 'l', 'l', 9, 0,
+ /* 653 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 662 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 675 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 688 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 701 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 715 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 724 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 736 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 749 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 763 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 777 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0,
+ /* 790 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 799 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 812 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 825 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 838 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 852 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 861 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 873 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 886 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 900 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 914 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0,
+ /* 927 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 938 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 953 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 968 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 983 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 999 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1010 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1024 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1039 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1055 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1071 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1086 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1097 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1112 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1127 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1142 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1158 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1169 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1183 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1198 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1214 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1230 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0,
+ /* 1245 */ 's', 'r', 'l', 9, 0,
+ /* 1250 */ 'm', 'u', 'l', 9, 0,
+ /* 1255 */ 'r', 'e', 'm', 9, 0,
+ /* 1260 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0,
+ /* 1272 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0,
+ /* 1283 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0,
+ /* 1292 */ 'c', '.', 'n', 'o', 'p', 9, 0,
+ /* 1299 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0,
+ /* 1311 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0,
+ /* 1319 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0,
+ /* 1328 */ 'c', '.', 's', 'd', 's', 'p', 9, 0,
+ /* 1336 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0,
+ /* 1345 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0,
+ /* 1353 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0,
+ /* 1362 */ 'c', '.', 's', 'w', 's', 'p', 9, 0,
+ /* 1370 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0,
+ /* 1379 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1388 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1401 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1414 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1427 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1441 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1450 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1462 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1475 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1489 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1503 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0,
+ /* 1516 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1525 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1538 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1551 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1564 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1578 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1587 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1599 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1612 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1626 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1640 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0,
+ /* 1653 */ 'b', 'e', 'q', 9, 0,
+ /* 1658 */ 'c', '.', 'j', 'r', 9, 0,
+ /* 1664 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0,
+ /* 1672 */ 'c', '.', 'o', 'r', 9, 0,
+ /* 1678 */ 'c', '.', 'x', 'o', 'r', 9, 0,
+ /* 1685 */ 'f', 's', 'u', 'b', '.', 's', 9, 0,
+ /* 1693 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0,
+ /* 1702 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0,
+ /* 1712 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0,
+ /* 1722 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0,
+ /* 1730 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0,
+ /* 1739 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0,
+ /* 1749 */ 'f', 'l', 'e', '.', 's', 9, 0,
+ /* 1756 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0,
+ /* 1765 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0,
+ /* 1775 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0,
+ /* 1783 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0,
+ /* 1791 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0,
+ /* 1801 */ 'f', 'e', 'q', '.', 's', 9, 0,
+ /* 1808 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0,
+ /* 1818 */ 'f', 'l', 't', '.', 's', 9, 0,
+ /* 1825 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0,
+ /* 1834 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0,
+ /* 1845 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0,
+ /* 1856 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0,
+ /* 1864 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0,
+ /* 1874 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0,
+ /* 1882 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0,
+ /* 1892 */ 'c', 's', 'r', 'r', 's', 9, 0,
+ /* 1899 */ 'm', 'r', 'e', 't', 9, 0,
+ /* 1905 */ 's', 'r', 'e', 't', 9, 0,
+ /* 1911 */ 'u', 'r', 'e', 't', 9, 0,
+ /* 1917 */ 'b', 'l', 't', 9, 0,
+ /* 1922 */ 's', 'l', 't', 9, 0,
+ /* 1927 */ 'l', 'b', 'u', 9, 0,
+ /* 1932 */ 'b', 'g', 'e', 'u', 9, 0,
+ /* 1938 */ 'm', 'u', 'l', 'h', 'u', 9, 0,
+ /* 1945 */ 's', 'l', 't', 'i', 'u', 9, 0,
+ /* 1952 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0,
+ /* 1963 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0,
+ /* 1974 */ 'r', 'e', 'm', 'u', 9, 0,
+ /* 1980 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0,
+ /* 1988 */ 'b', 'l', 't', 'u', 9, 0,
+ /* 1994 */ 's', 'l', 't', 'u', 9, 0,
+ /* 2000 */ 'd', 'i', 'v', 'u', 9, 0,
+ /* 2006 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0,
+ /* 2017 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0,
+ /* 2028 */ 'l', 'w', 'u', 9, 0,
+ /* 2033 */ 'd', 'i', 'v', 9, 0,
+ /* 2038 */ 'c', '.', 'm', 'v', 9, 0,
+ /* 2044 */ 's', 'c', '.', 'w', 9, 0,
+ /* 2050 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0,
+ /* 2060 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0,
+ /* 2070 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0,
+ /* 2080 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0,
+ /* 2090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0,
+ /* 2101 */ 'l', 'r', '.', 'w', 9, 0,
+ /* 2107 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0,
+ /* 2116 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0,
+ /* 2126 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0,
+ /* 2136 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0,
+ /* 2147 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0,
+ /* 2158 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0,
+ /* 2167 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0,
+ /* 2177 */ 's', 'r', 'a', 'w', 9, 0,
+ /* 2183 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0,
+ /* 2191 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0,
+ /* 2199 */ 's', 'r', 'a', 'i', 'w', 9, 0,
+ /* 2206 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0,
+ /* 2215 */ 's', 'l', 'l', 'i', 'w', 9, 0,
+ /* 2222 */ 's', 'r', 'l', 'i', 'w', 9, 0,
+ /* 2229 */ 'c', '.', 'l', 'w', 9, 0,
+ /* 2235 */ 'c', '.', 'f', 'l', 'w', 9, 0,
+ /* 2242 */ 's', 'l', 'l', 'w', 9, 0,
+ /* 2248 */ 's', 'r', 'l', 'w', 9, 0,
+ /* 2254 */ 'm', 'u', 'l', 'w', 9, 0,
+ /* 2260 */ 'r', 'e', 'm', 'w', 9, 0,
+ /* 2266 */ 'c', 's', 'r', 'r', 'w', 9, 0,
+ /* 2273 */ 'c', '.', 's', 'w', 9, 0,
+ /* 2279 */ 'c', '.', 'f', 's', 'w', 9, 0,
+ /* 2286 */ 'r', 'e', 'm', 'u', 'w', 9, 0,
+ /* 2293 */ 'd', 'i', 'v', 'u', 'w', 9, 0,
+ /* 2300 */ 'd', 'i', 'v', 'w', 9, 0,
+ /* 2306 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0,
+ /* 2315 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0,
+ /* 2324 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0,
+ /* 2332 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0,
+ /* 2340 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0,
+ /* 2371 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
+ /* 2395 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
+ /* 2420 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0,
+ /* 2443 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0,
+ /* 2466 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0,
+ /* 2488 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+ /* 2501 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+ /* 2508 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 2518 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 2528 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 2543 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0,
+ };
+
+ static const uint16_t OpInfo0[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // INLINEASM_BR
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // ANNOTATION_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 2509U, // DBG_VALUE
+ 2519U, // DBG_LABEL
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 2502U, // BUNDLE
+ 2529U, // LIFETIME_START
+ 2489U, // LIFETIME_END
+ 0U, // STACKMAP
+ 2544U, // FENTRY_CALL
+ 0U, // PATCHPOINT
+ 0U, // LOAD_STACK_GUARD
+ 0U, // STATEPOINT
+ 0U, // LOCAL_ESCAPE
+ 0U, // FAULTING_OP
+ 0U, // PATCHABLE_OP
+ 2421U, // PATCHABLE_FUNCTION_ENTER
+ 2341U, // PATCHABLE_RET
+ 2467U, // PATCHABLE_FUNCTION_EXIT
+ 2444U, // PATCHABLE_TAIL_CALL
+ 2396U, // PATCHABLE_EVENT_CALL
+ 2372U, // PATCHABLE_TYPED_EVENT_CALL
+ 0U, // ICALL_BRANCH_FUNNEL
+ 0U, // G_ADD
+ 0U, // G_SUB
+ 0U, // G_MUL
+ 0U, // G_SDIV
+ 0U, // G_UDIV
+ 0U, // G_SREM
+ 0U, // G_UREM
+ 0U, // G_AND
+ 0U, // G_OR
+ 0U, // G_XOR
+ 0U, // G_IMPLICIT_DEF
+ 0U, // G_PHI
+ 0U, // G_FRAME_INDEX
+ 0U, // G_GLOBAL_VALUE
+ 0U, // G_EXTRACT
+ 0U, // G_UNMERGE_VALUES
+ 0U, // G_INSERT
+ 0U, // G_MERGE_VALUES
+ 0U, // G_BUILD_VECTOR
+ 0U, // G_BUILD_VECTOR_TRUNC
+ 0U, // G_CONCAT_VECTORS
+ 0U, // G_PTRTOINT
+ 0U, // G_INTTOPTR
+ 0U, // G_BITCAST
+ 0U, // G_INTRINSIC_TRUNC
+ 0U, // G_INTRINSIC_ROUND
+ 0U, // G_READCYCLECOUNTER
+ 0U, // G_LOAD
+ 0U, // G_SEXTLOAD
+ 0U, // G_ZEXTLOAD
+ 0U, // G_INDEXED_LOAD
+ 0U, // G_INDEXED_SEXTLOAD
+ 0U, // G_INDEXED_ZEXTLOAD
+ 0U, // G_STORE
+ 0U, // G_INDEXED_STORE
+ 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ 0U, // G_ATOMIC_CMPXCHG
+ 0U, // G_ATOMICRMW_XCHG
+ 0U, // G_ATOMICRMW_ADD
+ 0U, // G_ATOMICRMW_SUB
+ 0U, // G_ATOMICRMW_AND
+ 0U, // G_ATOMICRMW_NAND
+ 0U, // G_ATOMICRMW_OR
+ 0U, // G_ATOMICRMW_XOR
+ 0U, // G_ATOMICRMW_MAX
+ 0U, // G_ATOMICRMW_MIN
+ 0U, // G_ATOMICRMW_UMAX
+ 0U, // G_ATOMICRMW_UMIN
+ 0U, // G_ATOMICRMW_FADD
+ 0U, // G_ATOMICRMW_FSUB
+ 0U, // G_FENCE
+ 0U, // G_BRCOND
+ 0U, // G_BRINDIRECT
+ 0U, // G_INTRINSIC
+ 0U, // G_INTRINSIC_W_SIDE_EFFECTS
+ 0U, // G_ANYEXT
+ 0U, // G_TRUNC
+ 0U, // G_CONSTANT
+ 0U, // G_FCONSTANT
+ 0U, // G_VASTART
+ 0U, // G_VAARG
+ 0U, // G_SEXT
+ 0U, // G_SEXT_INREG
+ 0U, // G_ZEXT
+ 0U, // G_SHL
+ 0U, // G_LSHR
+ 0U, // G_ASHR
+ 0U, // G_ICMP
+ 0U, // G_FCMP
+ 0U, // G_SELECT
+ 0U, // G_UADDO
+ 0U, // G_UADDE
+ 0U, // G_USUBO
+ 0U, // G_USUBE
+ 0U, // G_SADDO
+ 0U, // G_SADDE
+ 0U, // G_SSUBO
+ 0U, // G_SSUBE
+ 0U, // G_UMULO
+ 0U, // G_SMULO
+ 0U, // G_UMULH
+ 0U, // G_SMULH
+ 0U, // G_FADD
+ 0U, // G_FSUB
+ 0U, // G_FMUL
+ 0U, // G_FMA
+ 0U, // G_FMAD
+ 0U, // G_FDIV
+ 0U, // G_FREM
+ 0U, // G_FPOW
+ 0U, // G_FEXP
+ 0U, // G_FEXP2
+ 0U, // G_FLOG
+ 0U, // G_FLOG2
+ 0U, // G_FLOG10
+ 0U, // G_FNEG
+ 0U, // G_FPEXT
+ 0U, // G_FPTRUNC
+ 0U, // G_FPTOSI
+ 0U, // G_FPTOUI
+ 0U, // G_SITOFP
+ 0U, // G_UITOFP
+ 0U, // G_FABS
+ 0U, // G_FCOPYSIGN
+ 0U, // G_FCANONICALIZE
+ 0U, // G_FMINNUM
+ 0U, // G_FMAXNUM
+ 0U, // G_FMINNUM_IEEE
+ 0U, // G_FMAXNUM_IEEE
+ 0U, // G_FMINIMUM
+ 0U, // G_FMAXIMUM
+ 0U, // G_PTR_ADD
+ 0U, // G_PTR_MASK
+ 0U, // G_SMIN
+ 0U, // G_SMAX
+ 0U, // G_UMIN
+ 0U, // G_UMAX
+ 0U, // G_BR
+ 0U, // G_BRJT
+ 0U, // G_INSERT_VECTOR_ELT
+ 0U, // G_EXTRACT_VECTOR_ELT
+ 0U, // G_SHUFFLE_VECTOR
+ 0U, // G_CTTZ
+ 0U, // G_CTTZ_ZERO_UNDEF
+ 0U, // G_CTLZ
+ 0U, // G_CTLZ_ZERO_UNDEF
+ 0U, // G_CTPOP
+ 0U, // G_BSWAP
+ 0U, // G_BITREVERSE
+ 0U, // G_FCEIL
+ 0U, // G_FCOS
+ 0U, // G_FSIN
+ 0U, // G_FSQRT
+ 0U, // G_FFLOOR
+ 0U, // G_FRINT
+ 0U, // G_FNEARBYINT
+ 0U, // G_ADDRSPACE_CAST
+ 0U, // G_BLOCK_ADDR
+ 0U, // G_JUMP_TABLE
+ 0U, // G_DYN_STACKALLOC
+ 0U, // G_READ_REGISTER
+ 0U, // G_WRITE_REGISTER
+ 9U, // ADJCALLSTACKDOWN
+ 9U, // ADJCALLSTACKUP
+ 9U, // BuildPairF64Pseudo
+ 4500U, // PseudoAddTPRel
+ 9U, // PseudoAtomicLoadNand32
+ 9U, // PseudoAtomicLoadNand64
+ 9U, // PseudoBR
+ 9U, // PseudoBRIND
+ 21123U, // PseudoCALL
+ 9U, // PseudoCALLIndirect
+ 4739U, // PseudoCALLReg
+ 9U, // PseudoCmpXchg32
+ 9U, // PseudoCmpXchg64
+ 37292U, // PseudoFLD
+ 39102U, // PseudoFLW
+ 37312U, // PseudoFSD
+ 39146U, // PseudoFSW
+ 4128U, // PseudoLA
+ 4505U, // PseudoLA_TLS_GD
+ 4561U, // PseudoLA_TLS_IE
+ 4149U, // PseudoLB
+ 6024U, // PseudoLBU
+ 4518U, // PseudoLD
+ 4579U, // PseudoLH
+ 6037U, // PseudoLHU
+ 4635U, // PseudoLI
+ 4127U, // PseudoLLA
+ 6328U, // PseudoLW
+ 6125U, // PseudoLWU
+ 9U, // PseudoMaskedAtomicLoadAdd32
+ 9U, // PseudoMaskedAtomicLoadMax32
+ 9U, // PseudoMaskedAtomicLoadMin32
+ 9U, // PseudoMaskedAtomicLoadNand32
+ 9U, // PseudoMaskedAtomicLoadSub32
+ 9U, // PseudoMaskedAtomicLoadUMax32
+ 9U, // PseudoMaskedAtomicLoadUMin32
+ 9U, // PseudoMaskedAtomicSwap32
+ 9U, // PseudoMaskedCmpXchg32
+ 9U, // PseudoRET
+ 36921U, // PseudoSB
+ 37306U, // PseudoSD
+ 37351U, // PseudoSH
+ 39140U, // PseudoSW
+ 21116U, // PseudoTAIL
+ 9U, // PseudoTAILIndirect
+ 9U, // ReadCycleWide
+ 9U, // Select_FPR32_Using_CC_GPR
+ 9U, // Select_FPR64_Using_CC_GPR
+ 9U, // Select_GPR_Using_CC_GPR
+ 9U, // SplitF64Pseudo
+ 4500U, // ADD
+ 4614U, // ADDI
+ 6305U, // ADDIW
+ 6290U, // ADDW
+ 37006U, // AMOADD_D
+ 38253U, // AMOADD_D_AQ
+ 37803U, // AMOADD_D_AQ_RL
+ 37527U, // AMOADD_D_RL
+ 38925U, // AMOADD_W
+ 38390U, // AMOADD_W_AQ
+ 37962U, // AMOADD_W_AQ_RL
+ 37664U, // AMOADD_W_RL
+ 37016U, // AMOAND_D
+ 38266U, // AMOAND_D_AQ
+ 37818U, // AMOAND_D_AQ_RL
+ 37540U, // AMOAND_D_RL
+ 38935U, // AMOAND_W
+ 38403U, // AMOAND_W_AQ
+ 37977U, // AMOAND_W_AQ_RL
+ 37677U, // AMOAND_W_RL
+ 37200U, // AMOMAXU_D
+ 38354U, // AMOMAXU_D_AQ
+ 37920U, // AMOMAXU_D_AQ_RL
+ 37628U, // AMOMAXU_D_RL
+ 39012U, // AMOMAXU_W
+ 38491U, // AMOMAXU_W_AQ
+ 38079U, // AMOMAXU_W_AQ_RL
+ 37765U, // AMOMAXU_W_RL
+ 37246U, // AMOMAX_D
+ 38368U, // AMOMAX_D_AQ
+ 37936U, // AMOMAX_D_AQ_RL
+ 37642U, // AMOMAX_D_RL
+ 39032U, // AMOMAX_W
+ 38505U, // AMOMAX_W_AQ
+ 38095U, // AMOMAX_W_AQ_RL
+ 37779U, // AMOMAX_W_RL
+ 37178U, // AMOMINU_D
+ 38340U, // AMOMINU_D_AQ
+ 37904U, // AMOMINU_D_AQ_RL
+ 37614U, // AMOMINU_D_RL
+ 39001U, // AMOMINU_W
+ 38477U, // AMOMINU_W_AQ
+ 38063U, // AMOMINU_W_AQ_RL
+ 37751U, // AMOMINU_W_RL
+ 37068U, // AMOMIN_D
+ 38279U, // AMOMIN_D_AQ
+ 37833U, // AMOMIN_D_AQ_RL
+ 37553U, // AMOMIN_D_RL
+ 38945U, // AMOMIN_W
+ 38416U, // AMOMIN_W_AQ
+ 37992U, // AMOMIN_W_AQ_RL
+ 37690U, // AMOMIN_W_RL
+ 37112U, // AMOOR_D
+ 38315U, // AMOOR_D_AQ
+ 37875U, // AMOOR_D_AQ_RL
+ 37589U, // AMOOR_D_RL
+ 38972U, // AMOOR_W
+ 38452U, // AMOOR_W_AQ
+ 38034U, // AMOOR_W_AQ_RL
+ 37726U, // AMOOR_W_RL
+ 37088U, // AMOSWAP_D
+ 38292U, // AMOSWAP_D_AQ
+ 37848U, // AMOSWAP_D_AQ_RL
+ 37566U, // AMOSWAP_D_RL
+ 38955U, // AMOSWAP_W
+ 38429U, // AMOSWAP_W_AQ
+ 38007U, // AMOSWAP_W_AQ_RL
+ 37703U, // AMOSWAP_W_RL
+ 37121U, // AMOXOR_D
+ 38327U, // AMOXOR_D_AQ
+ 37889U, // AMOXOR_D_AQ_RL
+ 37601U, // AMOXOR_D_RL
+ 38981U, // AMOXOR_W
+ 38464U, // AMOXOR_W_AQ
+ 38048U, // AMOXOR_W_AQ_RL
+ 37738U, // AMOXOR_W_RL
+ 4531U, // AND
+ 4622U, // ANDI
+ 4164U, // AUIPC
+ 5750U, // BEQ
+ 4556U, // BGE
+ 6029U, // BGEU
+ 6014U, // BLT
+ 6085U, // BLTU
+ 4572U, // BNE
+ 4171U, // CSRRC
+ 4604U, // CSRRCI
+ 5989U, // CSRRS
+ 4661U, // CSRRSI
+ 6363U, // CSRRW
+ 4682U, // CSRRWI
+ 41362U, // C_ADD
+ 41476U, // C_ADDI
+ 42260U, // C_ADDI16SP
+ 5357U, // C_ADDI4SPN
+ 43167U, // C_ADDIW
+ 41476U, // C_ADDI_HINT_IMM_ZERO
+ 41476U, // C_ADDI_HINT_X0
+ 41476U, // C_ADDI_NOP
+ 43152U, // C_ADDW
+ 41362U, // C_ADD_HINT
+ 41393U, // C_AND
+ 41484U, // C_ANDI
+ 6429U, // C_BEQZ
+ 6421U, // C_BNEZ
+ 599U, // C_EBREAK
+ 37290U, // C_FLD
+ 38184U, // C_FLDSP
+ 39100U, // C_FLW
+ 38218U, // C_FLWSP
+ 37310U, // C_FSD
+ 38201U, // C_FSDSP
+ 39144U, // C_FSW
+ 38235U, // C_FSWSP
+ 21074U, // C_J
+ 21109U, // C_JAL
+ 22145U, // C_JALR
+ 22139U, // C_JR
+ 37284U, // C_LD
+ 38176U, // C_LDSP
+ 4633U, // C_LI
+ 4633U, // C_LI_HINT
+ 4675U, // C_LUI
+ 4675U, // C_LUI_HINT
+ 39094U, // C_LW
+ 38210U, // C_LWSP
+ 6135U, // C_MV
+ 6135U, // C_MV_HINT
+ 1293U, // C_NOP
+ 21773U, // C_NOP_HINT
+ 42633U, // C_OR
+ 37304U, // C_SD
+ 38193U, // C_SDSP
+ 41503U, // C_SLLI
+ 24587U, // C_SLLI64_HINT
+ 41503U, // C_SLLI_HINT
+ 41460U, // C_SRAI
+ 24577U, // C_SRAI64_HINT
+ 41511U, // C_SRLI
+ 24597U, // C_SRLI64_HINT
+ 41021U, // C_SUB
+ 43144U, // C_SUBW
+ 39138U, // C_SW
+ 38227U, // C_SWSP
+ 1284U, // C_UNIMP
+ 42639U, // C_XOR
+ 6130U, // DIV
+ 6097U, // DIVU
+ 6390U, // DIVUW
+ 6397U, // DIVW
+ 601U, // EBREAK
+ 642U, // ECALL
+ 4211U, // FADD_D
+ 5819U, // FADD_S
+ 4373U, // FCLASS_D
+ 5905U, // FCLASS_S
+ 4705U, // FCVT_D_L
+ 6049U, // FCVT_D_LU
+ 5809U, // FCVT_D_S
+ 6147U, // FCVT_D_W
+ 6103U, // FCVT_D_WU
+ 4399U, // FCVT_LU_D
+ 5931U, // FCVT_LU_S
+ 4274U, // FCVT_L_D
+ 5862U, // FCVT_L_S
+ 4363U, // FCVT_S_D
+ 4715U, // FCVT_S_L
+ 6060U, // FCVT_S_LU
+ 6223U, // FCVT_S_W
+ 6114U, // FCVT_S_WU
+ 4421U, // FCVT_WU_D
+ 5942U, // FCVT_WU_S
+ 4451U, // FCVT_W_D
+ 5961U, // FCVT_W_S
+ 4443U, // FDIV_D
+ 5953U, // FDIV_S
+ 12741U, // FENCE
+ 491U, // FENCE_I
+ 1273U, // FENCE_TSO
+ 4331U, // FEQ_D
+ 5898U, // FEQ_S
+ 37292U, // FLD
+ 4258U, // FLE_D
+ 5846U, // FLE_S
+ 4383U, // FLT_D
+ 5915U, // FLT_S
+ 39102U, // FLW
+ 4219U, // FMADD_D
+ 5827U, // FMADD_S
+ 4470U, // FMAX_D
+ 5971U, // FMAX_S
+ 4292U, // FMIN_D
+ 5880U, // FMIN_S
+ 4186U, // FMSUB_D
+ 5790U, // FMSUB_S
+ 4284U, // FMUL_D
+ 5872U, // FMUL_S
+ 6403U, // FMV_D_X
+ 6412U, // FMV_W_X
+ 4461U, // FMV_X_D
+ 6255U, // FMV_X_W
+ 4228U, // FNMADD_D
+ 5836U, // FNMADD_S
+ 4195U, // FNMSUB_D
+ 5799U, // FNMSUB_S
+ 37312U, // FSD
+ 4310U, // FSGNJN_D
+ 5888U, // FSGNJN_S
+ 4488U, // FSGNJX_D
+ 5979U, // FSGNJX_S
+ 4265U, // FSGNJ_D
+ 5853U, // FSGNJ_S
+ 4390U, // FSQRT_D
+ 5922U, // FSQRT_S
+ 4178U, // FSUB_D
+ 5782U, // FSUB_S
+ 39146U, // FSW
+ 4727U, // JAL
+ 38531U, // JALR
+ 36917U, // LB
+ 38792U, // LBU
+ 37286U, // LD
+ 37347U, // LH
+ 38805U, // LHU
+ 37106U, // LR_D
+ 38306U, // LR_D_AQ
+ 37864U, // LR_D_AQ_RL
+ 37580U, // LR_D_RL
+ 38966U, // LR_W
+ 38443U, // LR_W_AQ
+ 38023U, // LR_W_AQ_RL
+ 37717U, // LR_W_RL
+ 4677U, // LUI
+ 39096U, // LW
+ 38893U, // LWU
+ 1900U, // MRET
+ 5347U, // MUL
+ 4577U, // MULH
+ 6077U, // MULHSU
+ 6035U, // MULHU
+ 6351U, // MULW
+ 5771U, // OR
+ 4656U, // ORI
+ 5352U, // REM
+ 6071U, // REMU
+ 6383U, // REMUW
+ 6357U, // REMW
+ 36921U, // SB
+ 36973U, // SC_D
+ 38244U, // SC_D_AQ
+ 37792U, // SC_D_AQ_RL
+ 37518U, // SC_D_RL
+ 38909U, // SC_W
+ 38381U, // SC_W_AQ
+ 37951U, // SC_W_AQ_RL
+ 37655U, // SC_W_RL
+ 37306U, // SD
+ 4132U, // SFENCE_VMA
+ 37351U, // SH
+ 4745U, // SLL
+ 4641U, // SLLI
+ 6312U, // SLLIW
+ 6339U, // SLLW
+ 6019U, // SLT
+ 4669U, // SLTI
+ 6042U, // SLTIU
+ 6091U, // SLTU
+ 4144U, // SRA
+ 4598U, // SRAI
+ 6296U, // SRAIW
+ 6274U, // SRAW
+ 1906U, // SRET
+ 5342U, // SRL
+ 4649U, // SRLI
+ 6319U, // SRLIW
+ 6345U, // SRLW
+ 4159U, // SUB
+ 6282U, // SUBW
+ 39140U, // SW
+ 1286U, // UNIMP
+ 1912U, // URET
+ 532U, // WFI
+ 5777U, // XOR
+ 4655U, // XORI
+ };
+
+ static const uint8_t OpInfo1[] = {
+ 0U, // PHI
+ 0U, // INLINEASM
+ 0U, // INLINEASM_BR
+ 0U, // CFI_INSTRUCTION
+ 0U, // EH_LABEL
+ 0U, // GC_LABEL
+ 0U, // ANNOTATION_LABEL
+ 0U, // KILL
+ 0U, // EXTRACT_SUBREG
+ 0U, // INSERT_SUBREG
+ 0U, // IMPLICIT_DEF
+ 0U, // SUBREG_TO_REG
+ 0U, // COPY_TO_REGCLASS
+ 0U, // DBG_VALUE
+ 0U, // DBG_LABEL
+ 0U, // REG_SEQUENCE
+ 0U, // COPY
+ 0U, // BUNDLE
+ 0U, // LIFETIME_START
+ 0U, // LIFETIME_END
+ 0U, // STACKMAP
+ 0U, // FENTRY_CALL
+ 0U, // PATCHPOINT
+ 0U, // LOAD_STACK_GUARD
+ 0U, // STATEPOINT
+ 0U, // LOCAL_ESCAPE
+ 0U, // FAULTING_OP
+ 0U, // PATCHABLE_OP
+ 0U, // PATCHABLE_FUNCTION_ENTER
+ 0U, // PATCHABLE_RET
+ 0U, // PATCHABLE_FUNCTION_EXIT
+ 0U, // PATCHABLE_TAIL_CALL
+ 0U, // PATCHABLE_EVENT_CALL
+ 0U, // PATCHABLE_TYPED_EVENT_CALL
+ 0U, // ICALL_BRANCH_FUNNEL
+ 0U, // G_ADD
+ 0U, // G_SUB
+ 0U, // G_MUL
+ 0U, // G_SDIV
+ 0U, // G_UDIV
+ 0U, // G_SREM
+ 0U, // G_UREM
+ 0U, // G_AND
+ 0U, // G_OR
+ 0U, // G_XOR
+ 0U, // G_IMPLICIT_DEF
+ 0U, // G_PHI
+ 0U, // G_FRAME_INDEX
+ 0U, // G_GLOBAL_VALUE
+ 0U, // G_EXTRACT
+ 0U, // G_UNMERGE_VALUES
+ 0U, // G_INSERT
+ 0U, // G_MERGE_VALUES
+ 0U, // G_BUILD_VECTOR
+ 0U, // G_BUILD_VECTOR_TRUNC
+ 0U, // G_CONCAT_VECTORS
+ 0U, // G_PTRTOINT
+ 0U, // G_INTTOPTR
+ 0U, // G_BITCAST
+ 0U, // G_INTRINSIC_TRUNC
+ 0U, // G_INTRINSIC_ROUND
+ 0U, // G_READCYCLECOUNTER
+ 0U, // G_LOAD
+ 0U, // G_SEXTLOAD
+ 0U, // G_ZEXTLOAD
+ 0U, // G_INDEXED_LOAD
+ 0U, // G_INDEXED_SEXTLOAD
+ 0U, // G_INDEXED_ZEXTLOAD
+ 0U, // G_STORE
+ 0U, // G_INDEXED_STORE
+ 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ 0U, // G_ATOMIC_CMPXCHG
+ 0U, // G_ATOMICRMW_XCHG
+ 0U, // G_ATOMICRMW_ADD
+ 0U, // G_ATOMICRMW_SUB
+ 0U, // G_ATOMICRMW_AND
+ 0U, // G_ATOMICRMW_NAND
+ 0U, // G_ATOMICRMW_OR
+ 0U, // G_ATOMICRMW_XOR
+ 0U, // G_ATOMICRMW_MAX
+ 0U, // G_ATOMICRMW_MIN
+ 0U, // G_ATOMICRMW_UMAX
+ 0U, // G_ATOMICRMW_UMIN
+ 0U, // G_ATOMICRMW_FADD
+ 0U, // G_ATOMICRMW_FSUB
+ 0U, // G_FENCE
+ 0U, // G_BRCOND
+ 0U, // G_BRINDIRECT
+ 0U, // G_INTRINSIC
+ 0U, // G_INTRINSIC_W_SIDE_EFFECTS
+ 0U, // G_ANYEXT
+ 0U, // G_TRUNC
+ 0U, // G_CONSTANT
+ 0U, // G_FCONSTANT
+ 0U, // G_VASTART
+ 0U, // G_VAARG
+ 0U, // G_SEXT
+ 0U, // G_SEXT_INREG
+ 0U, // G_ZEXT
+ 0U, // G_SHL
+ 0U, // G_LSHR
+ 0U, // G_ASHR
+ 0U, // G_ICMP
+ 0U, // G_FCMP
+ 0U, // G_SELECT
+ 0U, // G_UADDO
+ 0U, // G_UADDE
+ 0U, // G_USUBO
+ 0U, // G_USUBE
+ 0U, // G_SADDO
+ 0U, // G_SADDE
+ 0U, // G_SSUBO
+ 0U, // G_SSUBE
+ 0U, // G_UMULO
+ 0U, // G_SMULO
+ 0U, // G_UMULH
+ 0U, // G_SMULH
+ 0U, // G_FADD
+ 0U, // G_FSUB
+ 0U, // G_FMUL
+ 0U, // G_FMA
+ 0U, // G_FMAD
+ 0U, // G_FDIV
+ 0U, // G_FREM
+ 0U, // G_FPOW
+ 0U, // G_FEXP
+ 0U, // G_FEXP2
+ 0U, // G_FLOG
+ 0U, // G_FLOG2
+ 0U, // G_FLOG10
+ 0U, // G_FNEG
+ 0U, // G_FPEXT
+ 0U, // G_FPTRUNC
+ 0U, // G_FPTOSI
+ 0U, // G_FPTOUI
+ 0U, // G_SITOFP
+ 0U, // G_UITOFP
+ 0U, // G_FABS
+ 0U, // G_FCOPYSIGN
+ 0U, // G_FCANONICALIZE
+ 0U, // G_FMINNUM
+ 0U, // G_FMAXNUM
+ 0U, // G_FMINNUM_IEEE
+ 0U, // G_FMAXNUM_IEEE
+ 0U, // G_FMINIMUM
+ 0U, // G_FMAXIMUM
+ 0U, // G_PTR_ADD
+ 0U, // G_PTR_MASK
+ 0U, // G_SMIN
+ 0U, // G_SMAX
+ 0U, // G_UMIN
+ 0U, // G_UMAX
+ 0U, // G_BR
+ 0U, // G_BRJT
+ 0U, // G_INSERT_VECTOR_ELT
+ 0U, // G_EXTRACT_VECTOR_ELT
+ 0U, // G_SHUFFLE_VECTOR
+ 0U, // G_CTTZ
+ 0U, // G_CTTZ_ZERO_UNDEF
+ 0U, // G_CTLZ
+ 0U, // G_CTLZ_ZERO_UNDEF
+ 0U, // G_CTPOP
+ 0U, // G_BSWAP
+ 0U, // G_BITREVERSE
+ 0U, // G_FCEIL
+ 0U, // G_FCOS
+ 0U, // G_FSIN
+ 0U, // G_FSQRT
+ 0U, // G_FFLOOR
+ 0U, // G_FRINT
+ 0U, // G_FNEARBYINT
+ 0U, // G_ADDRSPACE_CAST
+ 0U, // G_BLOCK_ADDR
+ 0U, // G_JUMP_TABLE
+ 0U, // G_DYN_STACKALLOC
+ 0U, // G_READ_REGISTER
+ 0U, // G_WRITE_REGISTER
+ 0U, // ADJCALLSTACKDOWN
+ 0U, // ADJCALLSTACKUP
+ 0U, // BuildPairF64Pseudo
+ 0U, // PseudoAddTPRel
+ 0U, // PseudoAtomicLoadNand32
+ 0U, // PseudoAtomicLoadNand64
+ 0U, // PseudoBR
+ 0U, // PseudoBRIND
+ 0U, // PseudoCALL
+ 0U, // PseudoCALLIndirect
+ 2U, // PseudoCALLReg
+ 0U, // PseudoCmpXchg32
+ 0U, // PseudoCmpXchg64
+ 8U, // PseudoFLD
+ 8U, // PseudoFLW
+ 8U, // PseudoFSD
+ 8U, // PseudoFSW
+ 2U, // PseudoLA
+ 2U, // PseudoLA_TLS_GD
+ 2U, // PseudoLA_TLS_IE
+ 2U, // PseudoLB
+ 2U, // PseudoLBU
+ 2U, // PseudoLD
+ 2U, // PseudoLH
+ 2U, // PseudoLHU
+ 2U, // PseudoLI
+ 2U, // PseudoLLA
+ 2U, // PseudoLW
+ 2U, // PseudoLWU
+ 0U, // PseudoMaskedAtomicLoadAdd32
+ 0U, // PseudoMaskedAtomicLoadMax32
+ 0U, // PseudoMaskedAtomicLoadMin32
+ 0U, // PseudoMaskedAtomicLoadNand32
+ 0U, // PseudoMaskedAtomicLoadSub32
+ 0U, // PseudoMaskedAtomicLoadUMax32
+ 0U, // PseudoMaskedAtomicLoadUMin32
+ 0U, // PseudoMaskedAtomicSwap32
+ 0U, // PseudoMaskedCmpXchg32
+ 0U, // PseudoRET
+ 8U, // PseudoSB
+ 8U, // PseudoSD
+ 8U, // PseudoSH
+ 8U, // PseudoSW
+ 0U, // PseudoTAIL
+ 0U, // PseudoTAILIndirect
+ 0U, // ReadCycleWide
+ 0U, // Select_FPR32_Using_CC_GPR
+ 0U, // Select_FPR64_Using_CC_GPR
+ 0U, // Select_GPR_Using_CC_GPR
+ 0U, // SplitF64Pseudo
+ 32U, // ADD
+ 32U, // ADDI
+ 32U, // ADDIW
+ 32U, // ADDW
+ 16U, // AMOADD_D
+ 16U, // AMOADD_D_AQ
+ 16U, // AMOADD_D_AQ_RL
+ 16U, // AMOADD_D_RL
+ 16U, // AMOADD_W
+ 16U, // AMOADD_W_AQ
+ 16U, // AMOADD_W_AQ_RL
+ 16U, // AMOADD_W_RL
+ 16U, // AMOAND_D
+ 16U, // AMOAND_D_AQ
+ 16U, // AMOAND_D_AQ_RL
+ 16U, // AMOAND_D_RL
+ 16U, // AMOAND_W
+ 16U, // AMOAND_W_AQ
+ 16U, // AMOAND_W_AQ_RL
+ 16U, // AMOAND_W_RL
+ 16U, // AMOMAXU_D
+ 16U, // AMOMAXU_D_AQ
+ 16U, // AMOMAXU_D_AQ_RL
+ 16U, // AMOMAXU_D_RL
+ 16U, // AMOMAXU_W
+ 16U, // AMOMAXU_W_AQ
+ 16U, // AMOMAXU_W_AQ_RL
+ 16U, // AMOMAXU_W_RL
+ 16U, // AMOMAX_D
+ 16U, // AMOMAX_D_AQ
+ 16U, // AMOMAX_D_AQ_RL
+ 16U, // AMOMAX_D_RL
+ 16U, // AMOMAX_W
+ 16U, // AMOMAX_W_AQ
+ 16U, // AMOMAX_W_AQ_RL
+ 16U, // AMOMAX_W_RL
+ 16U, // AMOMINU_D
+ 16U, // AMOMINU_D_AQ
+ 16U, // AMOMINU_D_AQ_RL
+ 16U, // AMOMINU_D_RL
+ 16U, // AMOMINU_W
+ 16U, // AMOMINU_W_AQ
+ 16U, // AMOMINU_W_AQ_RL
+ 16U, // AMOMINU_W_RL
+ 16U, // AMOMIN_D
+ 16U, // AMOMIN_D_AQ
+ 16U, // AMOMIN_D_AQ_RL
+ 16U, // AMOMIN_D_RL
+ 16U, // AMOMIN_W
+ 16U, // AMOMIN_W_AQ
+ 16U, // AMOMIN_W_AQ_RL
+ 16U, // AMOMIN_W_RL
+ 16U, // AMOOR_D
+ 16U, // AMOOR_D_AQ
+ 16U, // AMOOR_D_AQ_RL
+ 16U, // AMOOR_D_RL
+ 16U, // AMOOR_W
+ 16U, // AMOOR_W_AQ
+ 16U, // AMOOR_W_AQ_RL
+ 16U, // AMOOR_W_RL
+ 16U, // AMOSWAP_D
+ 16U, // AMOSWAP_D_AQ
+ 16U, // AMOSWAP_D_AQ_RL
+ 16U, // AMOSWAP_D_RL
+ 16U, // AMOSWAP_W
+ 16U, // AMOSWAP_W_AQ
+ 16U, // AMOSWAP_W_AQ_RL
+ 16U, // AMOSWAP_W_RL
+ 16U, // AMOXOR_D
+ 16U, // AMOXOR_D_AQ
+ 16U, // AMOXOR_D_AQ_RL
+ 16U, // AMOXOR_D_RL
+ 16U, // AMOXOR_W
+ 16U, // AMOXOR_W_AQ
+ 16U, // AMOXOR_W_AQ_RL
+ 16U, // AMOXOR_W_RL
+ 32U, // AND
+ 32U, // ANDI
+ 2U, // AUIPC
+ 32U, // BEQ
+ 32U, // BGE
+ 32U, // BGEU
+ 32U, // BLT
+ 32U, // BLTU
+ 32U, // BNE
+ 1U, // CSRRC
+ 1U, // CSRRCI
+ 1U, // CSRRS
+ 1U, // CSRRSI
+ 1U, // CSRRW
+ 1U, // CSRRWI
+ 2U, // C_ADD
+ 2U, // C_ADDI
+ 2U, // C_ADDI16SP
+ 32U, // C_ADDI4SPN
+ 2U, // C_ADDIW
+ 2U, // C_ADDI_HINT_IMM_ZERO
+ 2U, // C_ADDI_HINT_X0
+ 2U, // C_ADDI_NOP
+ 2U, // C_ADDW
+ 2U, // C_ADD_HINT
+ 2U, // C_AND
+ 2U, // C_ANDI
+ 2U, // C_BEQZ
+ 2U, // C_BNEZ
+ 0U, // C_EBREAK
+ 4U, // C_FLD
+ 4U, // C_FLDSP
+ 4U, // C_FLW
+ 4U, // C_FLWSP
+ 4U, // C_FSD
+ 4U, // C_FSDSP
+ 4U, // C_FSW
+ 4U, // C_FSWSP
+ 0U, // C_J
+ 0U, // C_JAL
+ 0U, // C_JALR
+ 0U, // C_JR
+ 4U, // C_LD
+ 4U, // C_LDSP
+ 2U, // C_LI
+ 2U, // C_LI_HINT
+ 2U, // C_LUI
+ 2U, // C_LUI_HINT
+ 4U, // C_LW
+ 4U, // C_LWSP
+ 2U, // C_MV
+ 2U, // C_MV_HINT
+ 0U, // C_NOP
+ 0U, // C_NOP_HINT
+ 2U, // C_OR
+ 4U, // C_SD
+ 4U, // C_SDSP
+ 2U, // C_SLLI
+ 0U, // C_SLLI64_HINT
+ 2U, // C_SLLI_HINT
+ 2U, // C_SRAI
+ 0U, // C_SRAI64_HINT
+ 2U, // C_SRLI
+ 0U, // C_SRLI64_HINT
+ 2U, // C_SUB
+ 2U, // C_SUBW
+ 4U, // C_SW
+ 4U, // C_SWSP
+ 0U, // C_UNIMP
+ 2U, // C_XOR
+ 32U, // DIV
+ 32U, // DIVU
+ 32U, // DIVUW
+ 32U, // DIVW
+ 0U, // EBREAK
+ 0U, // ECALL
+ 64U, // FADD_D
+ 64U, // FADD_S
+ 2U, // FCLASS_D
+ 2U, // FCLASS_S
+ 24U, // FCVT_D_L
+ 24U, // FCVT_D_LU
+ 2U, // FCVT_D_S
+ 2U, // FCVT_D_W
+ 2U, // FCVT_D_WU
+ 24U, // FCVT_LU_D
+ 24U, // FCVT_LU_S
+ 24U, // FCVT_L_D
+ 24U, // FCVT_L_S
+ 24U, // FCVT_S_D
+ 24U, // FCVT_S_L
+ 24U, // FCVT_S_LU
+ 24U, // FCVT_S_W
+ 24U, // FCVT_S_WU
+ 24U, // FCVT_WU_D
+ 24U, // FCVT_WU_S
+ 24U, // FCVT_W_D
+ 24U, // FCVT_W_S
+ 64U, // FDIV_D
+ 64U, // FDIV_S
+ 0U, // FENCE
+ 0U, // FENCE_I
+ 0U, // FENCE_TSO
+ 32U, // FEQ_D
+ 32U, // FEQ_S
+ 4U, // FLD
+ 32U, // FLE_D
+ 32U, // FLE_S
+ 32U, // FLT_D
+ 32U, // FLT_S
+ 4U, // FLW
+ 128U, // FMADD_D
+ 128U, // FMADD_S
+ 32U, // FMAX_D
+ 32U, // FMAX_S
+ 32U, // FMIN_D
+ 32U, // FMIN_S
+ 128U, // FMSUB_D
+ 128U, // FMSUB_S
+ 64U, // FMUL_D
+ 64U, // FMUL_S
+ 2U, // FMV_D_X
+ 2U, // FMV_W_X
+ 2U, // FMV_X_D
+ 2U, // FMV_X_W
+ 128U, // FNMADD_D
+ 128U, // FNMADD_S
+ 128U, // FNMSUB_D
+ 128U, // FNMSUB_S
+ 4U, // FSD
+ 32U, // FSGNJN_D
+ 32U, // FSGNJN_S
+ 32U, // FSGNJX_D
+ 32U, // FSGNJX_S
+ 32U, // FSGNJ_D
+ 32U, // FSGNJ_S
+ 24U, // FSQRT_D
+ 24U, // FSQRT_S
+ 64U, // FSUB_D
+ 64U, // FSUB_S
+ 4U, // FSW
+ 2U, // JAL
+ 4U, // JALR
+ 4U, // LB
+ 4U, // LBU
+ 4U, // LD
+ 4U, // LH
+ 4U, // LHU
+ 1U, // LR_D
+ 1U, // LR_D_AQ
+ 1U, // LR_D_AQ_RL
+ 1U, // LR_D_RL
+ 1U, // LR_W
+ 1U, // LR_W_AQ
+ 1U, // LR_W_AQ_RL
+ 1U, // LR_W_RL
+ 2U, // LUI
+ 4U, // LW
+ 4U, // LWU
+ 0U, // MRET
+ 32U, // MUL
+ 32U, // MULH
+ 32U, // MULHSU
+ 32U, // MULHU
+ 32U, // MULW
+ 32U, // OR
+ 32U, // ORI
+ 32U, // REM
+ 32U, // REMU
+ 32U, // REMUW
+ 32U, // REMW
+ 4U, // SB
+ 16U, // SC_D
+ 16U, // SC_D_AQ
+ 16U, // SC_D_AQ_RL
+ 16U, // SC_D_RL
+ 16U, // SC_W
+ 16U, // SC_W_AQ
+ 16U, // SC_W_AQ_RL
+ 16U, // SC_W_RL
+ 4U, // SD
+ 2U, // SFENCE_VMA
+ 4U, // SH
+ 32U, // SLL
+ 32U, // SLLI
+ 32U, // SLLIW
+ 32U, // SLLW
+ 32U, // SLT
+ 32U, // SLTI
+ 32U, // SLTIU
+ 32U, // SLTU
+ 32U, // SRA
+ 32U, // SRAI
+ 32U, // SRAIW
+ 32U, // SRAW
+ 0U, // SRET
+ 32U, // SRL
+ 32U, // SRLI
+ 32U, // SRLIW
+ 32U, // SRLW
+ 32U, // SUB
+ 32U, // SUBW
+ 4U, // SW
+ 0U, // UNIMP
+ 0U, // URET
+ 0U, // WFI
+ 32U, // XOR
+ 32U, // XORI
+ };
+
+ O << "\t";
+
+ // Emit the opcode for the instruction.
+ uint32_t Bits = 0;
+ Bits |= OpInfo0[MI->getOpcode()] << 0;
+ Bits |= OpInfo1[MI->getOpcode()] << 16;
+ assert(Bits != 0 && "Cannot print this instruction.");
+ O << AsmStrs+(Bits & 4095)-1;
+
+
+ // Fragment 0 encoded into 2 bits for 4 unique commands.
+ switch ((Bits >> 12) & 3) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL...
+ return;
+ break;
+ case 1:
+ // PseudoAddTPRel, PseudoCALL, PseudoCALLReg, PseudoFLD, PseudoFLW, Pseud...
+ printOperand(MI, 0, STI, O);
+ break;
+ case 2:
+ // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDI_HINT_IMM_ZERO, C_ADDI_HINT_...
+ printOperand(MI, 1, STI, O);
+ break;
+ case 3:
+ // FENCE
+ printFenceArg(MI, 0, STI, O);
+ O << ", ";
+ printFenceArg(MI, 1, STI, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 1 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 14) & 1) {
+ // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR, C_NOP_HINT, C_SLLI64...
+ return;
+ } else {
+ // PseudoAddTPRel, PseudoCALLReg, PseudoFLD, PseudoFLW, PseudoFSD, Pseudo...
+ O << ", ";
+ }
+
+
+ // Fragment 2 encoded into 2 bits for 4 unique commands.
+ switch ((Bits >> 15) & 3) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // PseudoAddTPRel, PseudoCALLReg, PseudoLA, PseudoLA_TLS_GD, PseudoLA_TLS...
+ printOperand(MI, 1, STI, O);
+ break;
+ case 1:
+ // PseudoFLD, PseudoFLW, PseudoFSD, PseudoFSW, PseudoSB, PseudoSD, Pseudo...
+ printOperand(MI, 2, STI, O);
+ break;
+ case 2:
+ // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI
+ printCSRSystemRegister(MI, 1, STI, O);
+ O << ", ";
+ printOperand(MI, 2, STI, O);
+ return;
+ break;
+ case 3:
+ // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL
+ printAtomicMemOp(MI, 1, STI, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 3 encoded into 2 bits for 3 unique commands.
+ switch ((Bits >> 17) & 3) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // PseudoAddTPRel, PseudoFLD, PseudoFLW, PseudoFSD, PseudoFSW, PseudoSB, ...
+ O << ", ";
+ break;
+ case 1:
+ // PseudoCALLReg, PseudoLA, PseudoLA_TLS_GD, PseudoLA_TLS_IE, PseudoLB, P...
+ return;
+ break;
+ case 2:
+ // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ...
+ O << '(';
+ printOperand(MI, 1, STI, O);
+ O << ')';
+ return;
+ break;
+ }
+
+
+ // Fragment 4 encoded into 2 bits for 4 unique commands.
+ switch ((Bits >> 19) & 3) {
+ default: llvm_unreachable("Invalid command number.");
+ case 0:
+ // PseudoAddTPRel, ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT...
+ printOperand(MI, 2, STI, O);
+ break;
+ case 1:
+ // PseudoFLD, PseudoFLW, PseudoFSD, PseudoFSW, PseudoSB, PseudoSD, Pseudo...
+ printOperand(MI, 1, STI, O);
+ return;
+ break;
+ case 2:
+ // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W...
+ printAtomicMemOp(MI, 1, STI, O);
+ return;
+ break;
+ case 3:
+ // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_...
+ printFRMArg(MI, 2, STI, O);
+ return;
+ break;
+ }
+
+
+ // Fragment 5 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 21) & 1) {
+ // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A...
+ return;
+ } else {
+ // PseudoAddTPRel, FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSU...
+ O << ", ";
+ }
+
+
+ // Fragment 6 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 22) & 1) {
+ // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S
+ printFRMArg(MI, 3, STI, O);
+ return;
+ } else {
+ // PseudoAddTPRel, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S...
+ printOperand(MI, 3, STI, O);
+ }
+
+
+ // Fragment 7 encoded into 1 bits for 2 unique commands.
+ if ((Bits >> 23) & 1) {
+ // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS...
+ O << ", ";
+ printFRMArg(MI, 4, STI, O);
+ return;
+ } else {
+ // PseudoAddTPRel
+ return;
+ }
+
+}
+
+
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description. This returns the assembler name
+/// for the specified register.
+const char *RISCVInstPrinter::
+getRegisterName(unsigned RegNo, unsigned AltIdx) {
+ assert(RegNo && RegNo < 97 && "Invalid register number!");
+
+ static const char AsmStrsABIRegAltName[] = {
+ /* 0 */ 'f', 's', '1', '0', 0,
+ /* 5 */ 'f', 't', '1', '0', 0,
+ /* 10 */ 'f', 'a', '0', 0,
+ /* 14 */ 'f', 's', '0', 0,
+ /* 18 */ 'f', 't', '0', 0,
+ /* 22 */ 'f', 's', '1', '1', 0,
+ /* 27 */ 'f', 't', '1', '1', 0,
+ /* 32 */ 'f', 'a', '1', 0,
+ /* 36 */ 'f', 's', '1', 0,
+ /* 40 */ 'f', 't', '1', 0,
+ /* 44 */ 'f', 'a', '2', 0,
+ /* 48 */ 'f', 's', '2', 0,
+ /* 52 */ 'f', 't', '2', 0,
+ /* 56 */ 'f', 'a', '3', 0,
+ /* 60 */ 'f', 's', '3', 0,
+ /* 64 */ 'f', 't', '3', 0,
+ /* 68 */ 'f', 'a', '4', 0,
+ /* 72 */ 'f', 's', '4', 0,
+ /* 76 */ 'f', 't', '4', 0,
+ /* 80 */ 'f', 'a', '5', 0,
+ /* 84 */ 'f', 's', '5', 0,
+ /* 88 */ 'f', 't', '5', 0,
+ /* 92 */ 'f', 'a', '6', 0,
+ /* 96 */ 'f', 's', '6', 0,
+ /* 100 */ 'f', 't', '6', 0,
+ /* 104 */ 'f', 'a', '7', 0,
+ /* 108 */ 'f', 's', '7', 0,
+ /* 112 */ 'f', 't', '7', 0,
+ /* 116 */ 'f', 's', '8', 0,
+ /* 120 */ 'f', 't', '8', 0,
+ /* 124 */ 'f', 's', '9', 0,
+ /* 128 */ 'f', 't', '9', 0,
+ /* 132 */ 'r', 'a', 0,
+ /* 135 */ 'z', 'e', 'r', 'o', 0,
+ /* 140 */ 'g', 'p', 0,
+ /* 143 */ 's', 'p', 0,
+ /* 146 */ 't', 'p', 0,
+ };
+
+ static const uint8_t RegAsmOffsetABIRegAltName[] = {
+ 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57,
+ 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23,
+ 65, 77, 89, 101, 18, 40, 52, 64, 76, 88, 100, 112, 14, 36,
+ 10, 32, 44, 56, 68, 80, 92, 104, 48, 60, 72, 84, 96, 108,
+ 116, 124, 0, 22, 120, 128, 5, 27, 18, 40, 52, 64, 76, 88,
+ 100, 112, 14, 36, 10, 32, 44, 56, 68, 80, 92, 104, 48, 60,
+ 72, 84, 96, 108, 116, 124, 0, 22, 120, 128, 5, 27,
+ };
+
+ static const char AsmStrsNoRegAltName[] = {
+ /* 0 */ 'f', '1', '0', 0,
+ /* 4 */ 'x', '1', '0', 0,
+ /* 8 */ 'f', '2', '0', 0,
+ /* 12 */ 'x', '2', '0', 0,
+ /* 16 */ 'f', '3', '0', 0,
+ /* 20 */ 'x', '3', '0', 0,
+ /* 24 */ 'f', '0', 0,
+ /* 27 */ 'x', '0', 0,
+ /* 30 */ 'f', '1', '1', 0,
+ /* 34 */ 'x', '1', '1', 0,
+ /* 38 */ 'f', '2', '1', 0,
+ /* 42 */ 'x', '2', '1', 0,
+ /* 46 */ 'f', '3', '1', 0,
+ /* 50 */ 'x', '3', '1', 0,
+ /* 54 */ 'f', '1', 0,
+ /* 57 */ 'x', '1', 0,
+ /* 60 */ 'f', '1', '2', 0,
+ /* 64 */ 'x', '1', '2', 0,
+ /* 68 */ 'f', '2', '2', 0,
+ /* 72 */ 'x', '2', '2', 0,
+ /* 76 */ 'f', '2', 0,
+ /* 79 */ 'x', '2', 0,
+ /* 82 */ 'f', '1', '3', 0,
+ /* 86 */ 'x', '1', '3', 0,
+ /* 90 */ 'f', '2', '3', 0,
+ /* 94 */ 'x', '2', '3', 0,
+ /* 98 */ 'f', '3', 0,
+ /* 101 */ 'x', '3', 0,
+ /* 104 */ 'f', '1', '4', 0,
+ /* 108 */ 'x', '1', '4', 0,
+ /* 112 */ 'f', '2', '4', 0,
+ /* 116 */ 'x', '2', '4', 0,
+ /* 120 */ 'f', '4', 0,
+ /* 123 */ 'x', '4', 0,
+ /* 126 */ 'f', '1', '5', 0,
+ /* 130 */ 'x', '1', '5', 0,
+ /* 134 */ 'f', '2', '5', 0,
+ /* 138 */ 'x', '2', '5', 0,
+ /* 142 */ 'f', '5', 0,
+ /* 145 */ 'x', '5', 0,
+ /* 148 */ 'f', '1', '6', 0,
+ /* 152 */ 'x', '1', '6', 0,
+ /* 156 */ 'f', '2', '6', 0,
+ /* 160 */ 'x', '2', '6', 0,
+ /* 164 */ 'f', '6', 0,
+ /* 167 */ 'x', '6', 0,
+ /* 170 */ 'f', '1', '7', 0,
+ /* 174 */ 'x', '1', '7', 0,
+ /* 178 */ 'f', '2', '7', 0,
+ /* 182 */ 'x', '2', '7', 0,
+ /* 186 */ 'f', '7', 0,
+ /* 189 */ 'x', '7', 0,
+ /* 192 */ 'f', '1', '8', 0,
+ /* 196 */ 'x', '1', '8', 0,
+ /* 200 */ 'f', '2', '8', 0,
+ /* 204 */ 'x', '2', '8', 0,
+ /* 208 */ 'f', '8', 0,
+ /* 211 */ 'x', '8', 0,
+ /* 214 */ 'f', '1', '9', 0,
+ /* 218 */ 'x', '1', '9', 0,
+ /* 222 */ 'f', '2', '9', 0,
+ /* 226 */ 'x', '2', '9', 0,
+ /* 230 */ 'f', '9', 0,
+ /* 233 */ 'x', '9', 0,
+ };
+
+ static const uint8_t RegAsmOffsetNoRegAltName[] = {
+ 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86,
+ 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182,
+ 204, 226, 20, 50, 24, 54, 76, 98, 120, 142, 164, 186, 208, 230,
+ 0, 30, 60, 82, 104, 126, 148, 170, 192, 214, 8, 38, 68, 90,
+ 112, 134, 156, 178, 200, 222, 16, 46, 24, 54, 76, 98, 120, 142,
+ 164, 186, 208, 230, 0, 30, 60, 82, 104, 126, 148, 170, 192, 214,
+ 8, 38, 68, 90, 112, 134, 156, 178, 200, 222, 16, 46,
+ };
+
+ switch(AltIdx) {
+ default: llvm_unreachable("Invalid register alt name index!");
+ case RISCV::ABIRegAltName:
+ assert(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) &&
+ "Invalid alt name index for register!");
+ return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1];
+ case RISCV::NoRegAltName:
+ assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
+ "Invalid alt name index for register!");
+ return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
+ }
+}
+
+#ifdef PRINT_ALIAS_INSTR
+#undef PRINT_ALIAS_INSTR
+
+static bool RISCVInstPrinterValidateMCOperand(const MCOperand &MCOp,
+ const MCSubtargetInfo &STI,
+ unsigned PredicateIndex);
+bool RISCVInstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) {
+ static const PatternsForOpcode OpToPatterns[] = {
+ {RISCV::ADDI, 0, 2 },
+ {RISCV::ADDIW, 2, 1 },
+ {RISCV::BEQ, 3, 1 },
+ {RISCV::BGE, 4, 2 },
+ {RISCV::BLT, 6, 2 },
+ {RISCV::BNE, 8, 1 },
+ {RISCV::CSRRC, 9, 1 },
+ {RISCV::CSRRCI, 10, 1 },
+ {RISCV::CSRRS, 11, 11 },
+ {RISCV::CSRRSI, 22, 1 },
+ {RISCV::CSRRW, 23, 7 },
+ {RISCV::CSRRWI, 30, 5 },
+ {RISCV::FADD_D, 35, 1 },
+ {RISCV::FADD_S, 36, 1 },
+ {RISCV::FCVT_D_L, 37, 1 },
+ {RISCV::FCVT_D_LU, 38, 1 },
+ {RISCV::FCVT_LU_D, 39, 1 },
+ {RISCV::FCVT_LU_S, 40, 1 },
+ {RISCV::FCVT_L_D, 41, 1 },
+ {RISCV::FCVT_L_S, 42, 1 },
+ {RISCV::FCVT_S_D, 43, 1 },
+ {RISCV::FCVT_S_L, 44, 1 },
+ {RISCV::FCVT_S_LU, 45, 1 },
+ {RISCV::FCVT_S_W, 46, 1 },
+ {RISCV::FCVT_S_WU, 47, 1 },
+ {RISCV::FCVT_WU_D, 48, 1 },
+ {RISCV::FCVT_WU_S, 49, 1 },
+ {RISCV::FCVT_W_D, 50, 1 },
+ {RISCV::FCVT_W_S, 51, 1 },
+ {RISCV::FDIV_D, 52, 1 },
+ {RISCV::FDIV_S, 53, 1 },
+ {RISCV::FENCE, 54, 1 },
+ {RISCV::FMADD_D, 55, 1 },
+ {RISCV::FMADD_S, 56, 1 },
+ {RISCV::FMSUB_D, 57, 1 },
+ {RISCV::FMSUB_S, 58, 1 },
+ {RISCV::FMUL_D, 59, 1 },
+ {RISCV::FMUL_S, 60, 1 },
+ {RISCV::FNMADD_D, 61, 1 },
+ {RISCV::FNMADD_S, 62, 1 },
+ {RISCV::FNMSUB_D, 63, 1 },
+ {RISCV::FNMSUB_S, 64, 1 },
+ {RISCV::FSGNJN_D, 65, 1 },
+ {RISCV::FSGNJN_S, 66, 1 },
+ {RISCV::FSGNJX_D, 67, 1 },
+ {RISCV::FSGNJX_S, 68, 1 },
+ {RISCV::FSGNJ_D, 69, 1 },
+ {RISCV::FSGNJ_S, 70, 1 },
+ {RISCV::FSQRT_D, 71, 1 },
+ {RISCV::FSQRT_S, 72, 1 },
+ {RISCV::FSUB_D, 73, 1 },
+ {RISCV::FSUB_S, 74, 1 },
+ {RISCV::JAL, 75, 2 },
+ {RISCV::JALR, 77, 6 },
+ {RISCV::SFENCE_VMA, 83, 2 },
+ {RISCV::SLT, 85, 2 },
+ {RISCV::SLTIU, 87, 1 },
+ {RISCV::SLTU, 88, 1 },
+ {RISCV::SUB, 89, 1 },
+ {RISCV::SUBW, 90, 1 },
+ {RISCV::XORI, 91, 1 },
+ };
+
+ static const AliasPattern Patterns[] = {
+ // RISCV::ADDI - 0
+ {0, 0, 3, 3 },
+ {4, 3, 3, 3 },
+ // RISCV::ADDIW - 2
+ {14, 6, 3, 4 },
+ // RISCV::BEQ - 3
+ {28, 10, 3, 3 },
+ // RISCV::BGE - 4
+ {40, 13, 3, 3 },
+ {52, 16, 3, 3 },
+ // RISCV::BLT - 6
+ {64, 19, 3, 3 },
+ {76, 22, 3, 3 },
+ // RISCV::BNE - 8
+ {88, 25, 3, 3 },
+ // RISCV::CSRRC - 9
+ {100, 28, 3, 3 },
+ // RISCV::CSRRCI - 10
+ {114, 31, 3, 2 },
+ // RISCV::CSRRS - 11
+ {129, 33, 3, 4 },
+ {138, 37, 3, 4 },
+ {146, 41, 3, 4 },
+ {157, 45, 3, 3 },
+ {170, 48, 3, 3 },
+ {181, 51, 3, 3 },
+ {191, 54, 3, 4 },
+ {205, 58, 3, 4 },
+ {217, 62, 3, 4 },
+ {228, 66, 3, 3 },
+ {242, 69, 3, 3 },
+ // RISCV::CSRRSI - 22
+ {256, 72, 3, 2 },
+ // RISCV::CSRRW - 23
+ {271, 74, 3, 4 },
+ {280, 78, 3, 4 },
+ {288, 82, 3, 4 },
+ {299, 86, 3, 3 },
+ {313, 89, 3, 4 },
+ {326, 93, 3, 4 },
+ {338, 97, 3, 4 },
+ // RISCV::CSRRWI - 30
+ {353, 101, 3, 3 },
+ {362, 104, 3, 3 },
+ {374, 107, 3, 2 },
+ {389, 109, 3, 3 },
+ {402, 112, 3, 3 },
+ // RISCV::FADD_D - 35
+ {418, 115, 4, 5 },
+ // RISCV::FADD_S - 36
+ {436, 120, 4, 5 },
+ // RISCV::FCVT_D_L - 37
+ {454, 125, 3, 5 },
+ // RISCV::FCVT_D_LU - 38
+ {470, 130, 3, 5 },
+ // RISCV::FCVT_LU_D - 39
+ {487, 135, 3, 5 },
+ // RISCV::FCVT_LU_S - 40
+ {504, 140, 3, 5 },
+ // RISCV::FCVT_L_D - 41
+ {521, 145, 3, 5 },
+ // RISCV::FCVT_L_S - 42
+ {537, 150, 3, 5 },
+ // RISCV::FCVT_S_D - 43
+ {553, 155, 3, 4 },
+ // RISCV::FCVT_S_L - 44
+ {569, 159, 3, 5 },
+ // RISCV::FCVT_S_LU - 45
+ {585, 164, 3, 5 },
+ // RISCV::FCVT_S_W - 46
+ {602, 169, 3, 4 },
+ // RISCV::FCVT_S_WU - 47
+ {618, 173, 3, 4 },
+ // RISCV::FCVT_WU_D - 48
+ {635, 177, 3, 4 },
+ // RISCV::FCVT_WU_S - 49
+ {652, 181, 3, 4 },
+ // RISCV::FCVT_W_D - 50
+ {669, 185, 3, 4 },
+ // RISCV::FCVT_W_S - 51
+ {685, 189, 3, 4 },
+ // RISCV::FDIV_D - 52
+ {701, 193, 4, 5 },
+ // RISCV::FDIV_S - 53
+ {719, 198, 4, 5 },
+ // RISCV::FENCE - 54
+ {737, 203, 2, 2 },
+ // RISCV::FMADD_D - 55
+ {743, 205, 5, 6 },
+ // RISCV::FMADD_S - 56
+ {766, 211, 5, 6 },
+ // RISCV::FMSUB_D - 57
+ {789, 217, 5, 6 },
+ // RISCV::FMSUB_S - 58
+ {812, 223, 5, 6 },
+ // RISCV::FMUL_D - 59
+ {835, 229, 4, 5 },
+ // RISCV::FMUL_S - 60
+ {853, 234, 4, 5 },
+ // RISCV::FNMADD_D - 61
+ {871, 239, 5, 6 },
+ // RISCV::FNMADD_S - 62
+ {895, 245, 5, 6 },
+ // RISCV::FNMSUB_D - 63
+ {919, 251, 5, 6 },
+ // RISCV::FNMSUB_S - 64
+ {943, 257, 5, 6 },
+ // RISCV::FSGNJN_D - 65
+ {967, 263, 3, 4 },
+ // RISCV::FSGNJN_S - 66
+ {981, 267, 3, 4 },
+ // RISCV::FSGNJX_D - 67
+ {995, 271, 3, 4 },
+ // RISCV::FSGNJX_S - 68
+ {1009, 275, 3, 4 },
+ // RISCV::FSGNJ_D - 69
+ {1023, 279, 3, 4 },
+ // RISCV::FSGNJ_S - 70
+ {1036, 283, 3, 4 },
+ // RISCV::FSQRT_D - 71
+ {1049, 287, 3, 4 },
+ // RISCV::FSQRT_S - 72
+ {1064, 291, 3, 4 },
+ // RISCV::FSUB_D - 73
+ {1079, 295, 4, 5 },
+ // RISCV::FSUB_S - 74
+ {1097, 300, 4, 5 },
+ // RISCV::JAL - 75
+ {1115, 305, 2, 2 },
+ {1120, 307, 2, 2 },
+ // RISCV::JALR - 77
+ {1127, 309, 3, 3 },
+ {1131, 312, 3, 3 },
+ {1137, 315, 3, 3 },
+ {1145, 318, 3, 3 },
+ {1157, 321, 3, 3 },
+ {1167, 324, 3, 3 },
+ // RISCV::SFENCE_VMA - 83
+ {1179, 327, 2, 2 },
+ {1190, 329, 2, 2 },
+ // RISCV::SLT - 85
+ {1204, 331, 3, 3 },
+ {1216, 334, 3, 3 },
+ // RISCV::SLTIU - 87
+ {1228, 337, 3, 3 },
+ // RISCV::SLTU - 88
+ {1240, 340, 3, 3 },
+ // RISCV::SUB - 89
+ {1252, 343, 3, 3 },
+ // RISCV::SUBW - 90
+ {1263, 346, 3, 4 },
+ // RISCV::XORI - 91
+ {1275, 350, 3, 3 },
+ };
+
+ static const AliasPatternCond Conds[] = {
+ // (ADDI X0, X0, 0) - 0
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (ADDI GPR:$rd, GPR:$rs, 0) - 3
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (ADDIW GPR:$rd, GPR:$rs, 0) - 6
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) - 10
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Custom, 1},
+ // (BGE X0, GPR:$rs, simm13_lsb0:$offset) - 13
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Custom, 1},
+ // (BGE GPR:$rs, X0, simm13_lsb0:$offset) - 16
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Custom, 1},
+ // (BLT GPR:$rs, X0, simm13_lsb0:$offset) - 19
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Custom, 1},
+ // (BLT X0, GPR:$rs, simm13_lsb0:$offset) - 22
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Custom, 1},
+ // (BNE GPR:$rs, X0, simm13_lsb0:$offset) - 25
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Custom, 1},
+ // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) - 28
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Ignore, 0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm) - 31
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Ignore, 0},
+ // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, X0) - 33
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(3)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, X0) - 37
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(2)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, X0) - 41
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(1)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, X0) - 45
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(3074)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, X0) - 48
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(3072)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, X0) - 51
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(3073)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0 }, X0) - 54
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(3202)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_NegFeature, RISCV::Feature64Bit},
+ // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 }, X0) - 58
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(3200)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_NegFeature, RISCV::Feature64Bit},
+ // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1 }, X0) - 62
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(3201)},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_NegFeature, RISCV::Feature64Bit},
+ // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) - 66
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Ignore, 0},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) - 69
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Ignore, 0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm) - 72
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Ignore, 0},
+ // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, GPR:$rs) - 74
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Imm, uint32_t(3)},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, GPR:$rs) - 78
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Imm, uint32_t(2)},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, GPR:$rs) - 82
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Imm, uint32_t(1)},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) - 86
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Ignore, 0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, GPR:$rs) - 89
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(3)},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, GPR:$rs) - 93
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(2)},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, GPR:$rs) - 97
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(1)},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRWI X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, uimm5:$imm) - 101
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Imm, uint32_t(2)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRWI X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, uimm5:$imm) - 104
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Imm, uint32_t(1)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm) - 107
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Ignore, 0},
+ // (CSRRWI GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, uimm5:$imm) - 109
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(2)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (CSRRWI GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, uimm5:$imm) - 112
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(1)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 115
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 120
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) - 125
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) - 130
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 135
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 140
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 145
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 150
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) - 155
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 159
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 164
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 169
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 173
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 177
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 181
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 185
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 189
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 193
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 198
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FENCE 15, 15) - 203
+ {AliasPatternCond::K_Imm, uint32_t(15)},
+ {AliasPatternCond::K_Imm, uint32_t(15)},
+ // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - 205
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - 211
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - 217
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - 223
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 229
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 234
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - 239
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - 245
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - 251
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - 257
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 263
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_TiedReg, 1},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 267
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_TiedReg, 1},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 271
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_TiedReg, 1},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 275
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_TiedReg, 1},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 279
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_TiedReg, 1},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 283
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_TiedReg, 1},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) - 287
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) - 291
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 295
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD},
+ // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 300
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(7)},
+ {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF},
+ // (JAL X0, simm21_lsb0_jal:$offset) - 305
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Custom, 2},
+ // (JAL X1, simm21_lsb0_jal:$offset) - 307
+ {AliasPatternCond::K_Reg, RISCV::X1},
+ {AliasPatternCond::K_Custom, 2},
+ // (JALR X0, X1, 0) - 309
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Reg, RISCV::X1},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (JALR X0, GPR:$rs, 0) - 312
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (JALR X1, GPR:$rs, 0) - 315
+ {AliasPatternCond::K_Reg, RISCV::X1},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (JALR GPR:$rd, GPR:$rs, 0) - 318
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(0)},
+ // (JALR X0, GPR:$rs, simm12:$offset) - 321
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Custom, 3},
+ // (JALR X1, GPR:$rs, simm12:$offset) - 324
+ {AliasPatternCond::K_Reg, RISCV::X1},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Custom, 3},
+ // (SFENCE_VMA X0, X0) - 327
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ // (SFENCE_VMA GPR:$rs, X0) - 329
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ // (SLT GPR:$rd, GPR:$rs, X0) - 331
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ // (SLT GPR:$rd, X0, GPR:$rs) - 334
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ // (SLTIU GPR:$rd, GPR:$rs, 1) - 337
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(1)},
+ // (SLTU GPR:$rd, X0, GPR:$rs) - 340
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ // (SUB GPR:$rd, X0, GPR:$rs) - 343
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ // (SUBW GPR:$rd, X0, GPR:$rs) - 346
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Reg, RISCV::X0},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Feature, RISCV::Feature64Bit},
+ // (XORI GPR:$rd, GPR:$rs, -1) - 350
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID},
+ {AliasPatternCond::K_Imm, uint32_t(-1)},
+ };
+
+ static const char AsmStrings[] =
+ /* 0 */ "nop\0"
+ /* 4 */ "mv $\x01, $\x02\0"
+ /* 14 */ "sext.w $\x01, $\x02\0"
+ /* 28 */ "beqz $\x01, $\x03\0"
+ /* 40 */ "blez $\x02, $\x03\0"
+ /* 52 */ "bgez $\x01, $\x03\0"
+ /* 64 */ "bltz $\x01, $\x03\0"
+ /* 76 */ "bgtz $\x02, $\x03\0"
+ /* 88 */ "bnez $\x01, $\x03\0"
+ /* 100 */ "csrc $\xFF\x02\x01, $\x03\0"
+ /* 114 */ "csrci $\xFF\x02\x01, $\x03\0"
+ /* 129 */ "frcsr $\x01\0"
+ /* 138 */ "frrm $\x01\0"
+ /* 146 */ "frflags $\x01\0"
+ /* 157 */ "rdinstret $\x01\0"
+ /* 170 */ "rdcycle $\x01\0"
+ /* 181 */ "rdtime $\x01\0"
+ /* 191 */ "rdinstreth $\x01\0"
+ /* 205 */ "rdcycleh $\x01\0"
+ /* 217 */ "rdtimeh $\x01\0"
+ /* 228 */ "csrr $\x01, $\xFF\x02\x01\0"
+ /* 242 */ "csrs $\xFF\x02\x01, $\x03\0"
+ /* 256 */ "csrsi $\xFF\x02\x01, $\x03\0"
+ /* 271 */ "fscsr $\x03\0"
+ /* 280 */ "fsrm $\x03\0"
+ /* 288 */ "fsflags $\x03\0"
+ /* 299 */ "csrw $\xFF\x02\x01, $\x03\0"
+ /* 313 */ "fscsr $\x01, $\x03\0"
+ /* 326 */ "fsrm $\x01, $\x03\0"
+ /* 338 */ "fsflags $\x01, $\x03\0"
+ /* 353 */ "fsrmi $\x03\0"
+ /* 362 */ "fsflagsi $\x03\0"
+ /* 374 */ "csrwi $\xFF\x02\x01, $\x03\0"
+ /* 389 */ "fsrmi $\x01, $\x03\0"
+ /* 402 */ "fsflagsi $\x01, $\x03\0"
+ /* 418 */ "fadd.d $\x01, $\x02, $\x03\0"
+ /* 436 */ "fadd.s $\x01, $\x02, $\x03\0"
+ /* 454 */ "fcvt.d.l $\x01, $\x02\0"
+ /* 470 */ "fcvt.d.lu $\x01, $\x02\0"
+ /* 487 */ "fcvt.lu.d $\x01, $\x02\0"
+ /* 504 */ "fcvt.lu.s $\x01, $\x02\0"
+ /* 521 */ "fcvt.l.d $\x01, $\x02\0"
+ /* 537 */ "fcvt.l.s $\x01, $\x02\0"
+ /* 553 */ "fcvt.s.d $\x01, $\x02\0"
+ /* 569 */ "fcvt.s.l $\x01, $\x02\0"
+ /* 585 */ "fcvt.s.lu $\x01, $\x02\0"
+ /* 602 */ "fcvt.s.w $\x01, $\x02\0"
+ /* 618 */ "fcvt.s.wu $\x01, $\x02\0"
+ /* 635 */ "fcvt.wu.d $\x01, $\x02\0"
+ /* 652 */ "fcvt.wu.s $\x01, $\x02\0"
+ /* 669 */ "fcvt.w.d $\x01, $\x02\0"
+ /* 685 */ "fcvt.w.s $\x01, $\x02\0"
+ /* 701 */ "fdiv.d $\x01, $\x02, $\x03\0"
+ /* 719 */ "fdiv.s $\x01, $\x02, $\x03\0"
+ /* 737 */ "fence\0"
+ /* 743 */ "fmadd.d $\x01, $\x02, $\x03, $\x04\0"
+ /* 766 */ "fmadd.s $\x01, $\x02, $\x03, $\x04\0"
+ /* 789 */ "fmsub.d $\x01, $\x02, $\x03, $\x04\0"
+ /* 812 */ "fmsub.s $\x01, $\x02, $\x03, $\x04\0"
+ /* 835 */ "fmul.d $\x01, $\x02, $\x03\0"
+ /* 853 */ "fmul.s $\x01, $\x02, $\x03\0"
+ /* 871 */ "fnmadd.d $\x01, $\x02, $\x03, $\x04\0"
+ /* 895 */ "fnmadd.s $\x01, $\x02, $\x03, $\x04\0"
+ /* 919 */ "fnmsub.d $\x01, $\x02, $\x03, $\x04\0"
+ /* 943 */ "fnmsub.s $\x01, $\x02, $\x03, $\x04\0"
+ /* 967 */ "fneg.d $\x01, $\x02\0"
+ /* 981 */ "fneg.s $\x01, $\x02\0"
+ /* 995 */ "fabs.d $\x01, $\x02\0"
+ /* 1009 */ "fabs.s $\x01, $\x02\0"
+ /* 1023 */ "fmv.d $\x01, $\x02\0"
+ /* 1036 */ "fmv.s $\x01, $\x02\0"
+ /* 1049 */ "fsqrt.d $\x01, $\x02\0"
+ /* 1064 */ "fsqrt.s $\x01, $\x02\0"
+ /* 1079 */ "fsub.d $\x01, $\x02, $\x03\0"
+ /* 1097 */ "fsub.s $\x01, $\x02, $\x03\0"
+ /* 1115 */ "j $\x02\0"
+ /* 1120 */ "jal $\x02\0"
+ /* 1127 */ "ret\0"
+ /* 1131 */ "jr $\x02\0"
+ /* 1137 */ "jalr $\x02\0"
+ /* 1145 */ "jalr $\x01, $\x02\0"
+ /* 1157 */ "jr $\x03($\x02)\0"
+ /* 1167 */ "jalr $\x03($\x02)\0"
+ /* 1179 */ "sfence.vma\0"
+ /* 1190 */ "sfence.vma $\x01\0"
+ /* 1204 */ "sltz $\x01, $\x02\0"
+ /* 1216 */ "sgtz $\x01, $\x03\0"
+ /* 1228 */ "seqz $\x01, $\x02\0"
+ /* 1240 */ "snez $\x01, $\x03\0"
+ /* 1252 */ "neg $\x01, $\x03\0"
+ /* 1263 */ "negw $\x01, $\x03\0"
+ /* 1275 */ "not $\x01, $\x02\0"
+ ;
+
+#ifndef NDEBUG
+ static struct SortCheck {
+ SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
+ assert(std::is_sorted(
+ OpToPatterns.begin(), OpToPatterns.end(),
+ [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
+ return L.Opcode < R.Opcode;
+ }) &&
+ "tablegen failed to sort opcode patterns");
+ }
+ } sortCheckVar(OpToPatterns);
+#endif
+
+ AliasMatchingData M {
+ makeArrayRef(OpToPatterns),
+ makeArrayRef(Patterns),
+ makeArrayRef(Conds),
+ StringRef(AsmStrings, array_lengthof(AsmStrings)),
+ &RISCVInstPrinterValidateMCOperand,
+ };
+ const char *AsmString = matchAliasPatterns(MI, &STI, M);
+ if (!AsmString) return false;
+
+ unsigned I = 0;
+ while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
+ AsmString[I] != '$' && AsmString[I] != '\0')
+ ++I;
+ OS << '\t' << StringRef(AsmString, I);
+ if (AsmString[I] != '\0') {
+ if (AsmString[I] == ' ' || AsmString[I] == '\t') {
+ OS << '\t';
+ ++I;
+ }
+ do {
+ if (AsmString[I] == '$') {
+ ++I;
+ if (AsmString[I] == (char)0xff) {
+ ++I;
+ int OpIdx = AsmString[I++] - 1;
+ int PrintMethodIdx = AsmString[I++] - 1;
+ printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, STI, OS);
+ } else
+ printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS);
+ } else {
+ OS << AsmString[I++];
+ }
+ } while (AsmString[I] != '\0');
+ }
+
+ return true;
+}
+
+void RISCVInstPrinter::printCustomAliasOperand(
+ const MCInst *MI, unsigned OpIdx,
+ unsigned PrintMethodIdx,
+ const MCSubtargetInfo &STI,
+ raw_ostream &OS) {
+ switch (PrintMethodIdx) {
+ default:
+ llvm_unreachable("Unknown PrintMethod kind");
+ break;
+ case 0:
+ printCSRSystemRegister(MI, OpIdx, STI, OS);
+ break;
+ }
+}
+
+static bool RISCVInstPrinterValidateMCOperand(const MCOperand &MCOp,
+ const MCSubtargetInfo &STI,
+ unsigned PredicateIndex) {
+ switch (PredicateIndex) {
+ default:
+ llvm_unreachable("Unknown MCOperandPredicate kind");
+ break;
+ case 1: {
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isShiftedInt<12, 1>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 2: {
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isShiftedInt<20, 1>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 3: {
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isInt<12>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ }
+}
+
+#endif // PRINT_ALIAS_INSTR
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc
new file mode 100644
index 0000000..88aee77
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc
@@ -0,0 +1,2609 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Compress instruction Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GEN_COMPRESS_INSTR
+#undef GEN_COMPRESS_INSTR
+
+static bool RISCVValidateMCOperand(const MCOperand &MCOp,
+ const MCSubtargetInfo &STI,
+ unsigned PredicateIndex) {
+ switch (PredicateIndex) {
+ default:
+ llvm_unreachable("Unknown MCOperandPredicate kind");
+ break;
+ case 1: {
+ // uimm10_lsb00nonzero
+
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
+
+ }
+ case 2: {
+ // simm6nonzero
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return (Imm != 0) && isInt<6>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 3: {
+ // simm6
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isInt<6>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 4: {
+ // simm10_lsb0000nonzero
+
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedInt<6, 4>(Imm) && (Imm != 0);
+
+ }
+ case 5: {
+ // simm9_lsb0
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isShiftedInt<8, 1>(Imm);
+ return MCOp.isBareSymbolRef();
+
+
+ }
+ case 6: {
+ // uimm8_lsb000
+
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedUInt<5, 3>(Imm);
+
+ }
+ case 7: {
+ // uimm9_lsb000
+
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedUInt<6, 3>(Imm);
+
+ }
+ case 8: {
+ // uimm7_lsb00
+
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedUInt<5, 2>(Imm);
+
+ }
+ case 9: {
+ // uimm8_lsb00
+
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isShiftedUInt<6, 2>(Imm);
+
+ }
+ case 10: {
+ // simm12_lsb0
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isShiftedInt<11, 1>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 11: {
+ // c_lui_imm
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return (Imm != 0) && (isUInt<5>(Imm) ||
+ (Imm >= 0xfffe0 && Imm <= 0xfffff));
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 12: {
+ // uimmlog2xlennonzero
+
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ if (STI.getTargetTriple().isArch64Bit())
+ return isUInt<6>(Imm) && (Imm != 0);
+ return isUInt<5>(Imm) && (Imm != 0);
+
+ }
+ }
+}
+
+static bool compressInst(MCInst& OutInst,
+ const MCInst &MI,
+ const MCSubtargetInfo &STI,
+ MCContext &Context) {
+ const MCRegisterInfo &MRI = *Context.getRegisterInfo();
+ switch (MI.getOpcode()) {
+ default: return false;
+ case RISCV::ADD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.mv $rs1, $rs2
+ OutInst.setOpcode(RISCV::C_MV);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.mv $rs1, $rs2
+ OutInst.setOpcode(RISCV::C_MV);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.add $rs1, $rs2
+ OutInst.setOpcode(RISCV::C_ADD);
+ // Operand: rs1_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.add $rs1, $rs2
+ OutInst.setOpcode(RISCV::C_ADD);
+ // Operand: rs1_wb
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case ADD
+ case RISCV::ADDI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // c.addi4spn $rd, $rs1, $imm
+ OutInst.setOpcode(RISCV::C_ADDI4SPN);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X0) &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(2).getImm() == 0)) {
+ // c.nop
+ OutInst.setOpcode(RISCV::C_NOP);
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 2)) {
+ // c.addi $rd, $imm
+ OutInst.setOpcode(RISCV::C_ADDI);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 3)) {
+ // c.li $rd, $imm
+ OutInst.setOpcode(RISCV::C_LI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X2) &&
+ (MI.getOperand(1).getReg() == RISCV::X2) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 4)) {
+ // c.addi16sp $rd, $imm
+ OutInst.setOpcode(RISCV::C_ADDI16SP);
+ // Operand: rd_wb
+ OutInst.addOperand(MCOperand::createReg(RISCV::X2));
+ // Operand: rd
+ OutInst.addOperand(MCOperand::createReg(RISCV::X2));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(2).getImm() == 0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.mv $rs1, $rs2
+ OutInst.setOpcode(RISCV::C_MV);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case ADDI
+ case RISCV::ADDIW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 3)) {
+ // c.addiw $rd, $imm
+ OutInst.setOpcode(RISCV::C_ADDIW);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 3)) {
+ // c.li $rd, $imm
+ OutInst.setOpcode(RISCV::C_LI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case ADDIW
+ case RISCV::ADDW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.addw $rd, $rs2
+ OutInst.setOpcode(RISCV::C_ADDW);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.addw $rd, $rs2
+ OutInst.setOpcode(RISCV::C_ADDW);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case ADDW
+ case RISCV::AND: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.and $rd, $rs2
+ OutInst.setOpcode(RISCV::C_AND);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.and $rd, $rs2
+ OutInst.setOpcode(RISCV::C_AND);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case AND
+ case RISCV::ANDI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 3)) {
+ // c.andi $rs1, $imm
+ OutInst.setOpcode(RISCV::C_ANDI);
+ // Operand: rs1_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case ANDI
+ case RISCV::BEQ: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) {
+ // c.beqz $rs1, $imm
+ OutInst.setOpcode(RISCV::C_BEQZ);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case BEQ
+ case RISCV::BNE: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) {
+ // c.bnez $rs1, $imm
+ OutInst.setOpcode(RISCV::C_BNEZ);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case BNE
+ case RISCV::EBREAK: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
+ // c.ebreak
+ OutInst.setOpcode(RISCV::C_EBREAK);
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case EBREAK
+ case RISCV::FLD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 6)) {
+ // c.fld $rd, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_FLD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 7)) {
+ // c.fldsp $rd, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_FLDSP);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case FLD
+ case RISCV::FLW: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 8)) {
+ // c.flw $rd, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_FLW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 9)) {
+ // c.flwsp $rd, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_FLWSP);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case FLW
+ case RISCV::FSD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 6)) {
+ // c.fsd $rs2, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_FSD);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 7)) {
+ // c.fsdsp $rs2, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_FSDSP);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case FSD
+ case RISCV::FSW: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 8)) {
+ // c.fsw $rs2, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_FSW);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 9)) {
+ // c.fswsp $rs2, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_FSWSP);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case FSW
+ case RISCV::JAL: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X1) &&
+ RISCVValidateMCOperand(MI.getOperand(1), STI, 10)) {
+ // c.jal $offset
+ OutInst.setOpcode(RISCV::C_JAL);
+ // Operand: offset
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X0) &&
+ RISCVValidateMCOperand(MI.getOperand(1), STI, 10)) {
+ // c.j $offset
+ OutInst.setOpcode(RISCV::C_J);
+ // Operand: offset
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case JAL
+ case RISCV::JALR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X0) &&
+ (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(2).getImm() == 0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.jr $rs1
+ OutInst.setOpcode(RISCV::C_JR);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X1) &&
+ (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(2).getImm() == 0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.jalr $rs1
+ OutInst.setOpcode(RISCV::C_JALR);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case JALR
+ case RISCV::LD: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 6)) {
+ // c.ld $rd, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_LD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 7)) {
+ // c.ldsp $rd, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_LDSP);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case LD
+ case RISCV::LUI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRNoX0X2RegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(1), STI, 11)) {
+ // c.lui $rd, $imm
+ OutInst.setOpcode(RISCV::C_LUI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case LUI
+ case RISCV::LW: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 8)) {
+ // c.lw $rd, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_LW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 9)) {
+ // c.lwsp $rd, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_LWSP);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case LW
+ case RISCV::OR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.or $rd, $rs2
+ OutInst.setOpcode(RISCV::C_OR);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.or $rd, $rs2
+ OutInst.setOpcode(RISCV::C_OR);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case OR
+ case RISCV::SD: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 6)) {
+ // c.sd $rs2, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_SD);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 7)) {
+ // c.sdsp $rs2, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_SDSP);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case SD
+ case RISCV::SLLI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 12)) {
+ // c.slli $rd, $imm
+ OutInst.setOpcode(RISCV::C_SLLI);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case SLLI
+ case RISCV::SRAI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 12)) {
+ // c.srai $rs1, $imm
+ OutInst.setOpcode(RISCV::C_SRAI);
+ // Operand: rs1_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case SRAI
+ case RISCV::SRLI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 12)) {
+ // c.srli $rs1, $imm
+ OutInst.setOpcode(RISCV::C_SRLI);
+ // Operand: rs1_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case SRLI
+ case RISCV::SUB: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.sub $rd, $rs2
+ OutInst.setOpcode(RISCV::C_SUB);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case SUB
+ case RISCV::SUBW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.subw $rd, $rs2
+ OutInst.setOpcode(RISCV::C_SUBW);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case SUBW
+ case RISCV::SW: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 8)) {
+ // c.sw $rs2, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_SW);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 9)) {
+ // c.swsp $rs2, ${imm}(${rs1})
+ OutInst.setOpcode(RISCV::C_SWSP);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case SW
+ case RISCV::UNIMP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
+ // c.unimp
+ OutInst.setOpcode(RISCV::C_UNIMP);
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case UNIMP
+ case RISCV::XOR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.xor $rd, $rs2
+ OutInst.setOpcode(RISCV::C_XOR);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.xor $rd, $rs2
+ OutInst.setOpcode(RISCV::C_XOR);
+ // Operand: rd_wb
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+
+ } // case XOR
+ } // switch
+ return false;
+}
+
+#endif //GEN_COMPRESS_INSTR
+
+#ifdef GEN_UNCOMPRESS_INSTR
+#undef GEN_UNCOMPRESS_INSTR
+
+static bool RISCVValidateMCOperand(const MCOperand &MCOp,
+ const MCSubtargetInfo &STI,
+ unsigned PredicateIndex) {
+ switch (PredicateIndex) {
+ default:
+ llvm_unreachable("Unknown MCOperandPredicate kind");
+ break;
+ case 1: {
+ // simm12
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isInt<12>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 2: {
+ // simm13_lsb0
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isShiftedInt<12, 1>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 3: {
+ // simm21_lsb0_jal
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isShiftedInt<20, 1>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 4: {
+ // uimm20_lui
+
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isUInt<20>(Imm);
+ return MCOp.isBareSymbolRef();
+
+ }
+ case 5: {
+ // uimmlog2xlen
+
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ if (STI.getTargetTriple().isArch64Bit())
+ return isUInt<6>(Imm);
+ return isUInt<5>(Imm);
+
+ }
+ }
+}
+
+static bool uncompressInst(MCInst& OutInst,
+ const MCInst &MI,
+ const MCRegisterInfo &MRI,
+ const MCSubtargetInfo &STI) {
+ switch (MI.getOpcode()) {
+ default: return false;
+ case RISCV::C_ADD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // add $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::ADD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) {
+ // add $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::ADD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_ADD
+ case RISCV::C_ADDI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // addi $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ADDI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_ADDI
+ case RISCV::C_ADDI16SP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X2) &&
+ (MI.getOperand(1).getReg() == RISCV::X2) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // addi $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ADDI);
+ // Operand: rd
+ OutInst.addOperand(MCOperand::createReg(RISCV::X2));
+ // Operand: rs1
+ OutInst.addOperand(MCOperand::createReg(RISCV::X2));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_ADDI16SP
+ case RISCV::C_ADDI4SPN: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // addi $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ADDI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_ADDI4SPN
+ case RISCV::C_ADDIW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // addiw $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ADDIW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_ADDIW
+ case RISCV::C_ADDW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // addw $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::ADDW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) {
+ // addw $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::ADDW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_ADDW
+ case RISCV::C_AND: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // and $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::AND);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) {
+ // and $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::AND);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_AND
+ case RISCV::C_ANDI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // andi $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ANDI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_ANDI
+ case RISCV::C_BEQZ: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(1), STI, 2)) {
+ // beq $rs1, $rs2, $imm12
+ OutInst.setOpcode(RISCV::BEQ);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_BEQZ
+ case RISCV::C_BNEZ: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(1), STI, 2)) {
+ // bne $rs1, $rs2, $imm12
+ OutInst.setOpcode(RISCV::BNE);
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_BNEZ
+ case RISCV::C_EBREAK: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
+ // ebreak
+ OutInst.setOpcode(RISCV::EBREAK);
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_EBREAK
+ case RISCV::C_FLD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // fld $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::FLD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_FLD
+ case RISCV::C_FLDSP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // fld $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::FLD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_FLDSP
+ case RISCV::C_FLW: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // flw $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::FLW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_FLW
+ case RISCV::C_FLWSP: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // flw $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::FLW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_FLWSP
+ case RISCV::C_FSD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // fsd $rs2, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::FSD);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_FSD
+ case RISCV::C_FSDSP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // fsd $rs2, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::FSD);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_FSDSP
+ case RISCV::C_FSW: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // fsw $rs2, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::FSW);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_FSW
+ case RISCV::C_FSWSP: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // fsw $rs2, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::FSW);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_FSWSP
+ case RISCV::C_J: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ RISCVValidateMCOperand(MI.getOperand(0), STI, 3)) {
+ // jal $rd, $imm20
+ OutInst.setOpcode(RISCV::JAL);
+ // Operand: rd
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: imm20
+ OutInst.addOperand(MI.getOperand(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_J
+ case RISCV::C_JAL: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ RISCVValidateMCOperand(MI.getOperand(0), STI, 3)) {
+ // jal $rd, $imm20
+ OutInst.setOpcode(RISCV::JAL);
+ // Operand: rd
+ OutInst.addOperand(MCOperand::createReg(RISCV::X1));
+ // Operand: imm20
+ OutInst.addOperand(MI.getOperand(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_JAL
+ case RISCV::C_JALR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MCOperand::createImm(0), STI, 1)) {
+ // jalr $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::JALR);
+ // Operand: rd
+ OutInst.addOperand(MCOperand::createReg(RISCV::X1));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm12
+ OutInst.addOperand(MCOperand::createImm(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_JALR
+ case RISCV::C_JR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MCOperand::createImm(0), STI, 1)) {
+ // jalr $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::JALR);
+ // Operand: rd
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm12
+ OutInst.addOperand(MCOperand::createImm(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_JR
+ case RISCV::C_LD: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // ld $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::LD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_LD
+ case RISCV::C_LDSP: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // ld $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::LD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_LDSP
+ case RISCV::C_LI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(1), STI, 1)) {
+ // addi $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ADDI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(1), STI, 1)) {
+ // addiw $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ADDIW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_LI
+ case RISCV::C_LUI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(1), STI, 4)) {
+ // lui $rd, $imm20
+ OutInst.setOpcode(RISCV::LUI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: imm20
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_LUI
+ case RISCV::C_LW: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // lw $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::LW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_LW
+ case RISCV::C_LWSP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // lw $rd, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::LW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_LWSP
+ case RISCV::C_MV: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // add $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::ADD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(1));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // add $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::ADD);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: rs2
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MCOperand::createImm(0), STI, 1)) {
+ // addi $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ADDI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MCOperand::createImm(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_MV
+ case RISCV::C_NOP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ RISCVValidateMCOperand(MCOperand::createImm(0), STI, 1)) {
+ // addi $rd, $rs1, $imm12
+ OutInst.setOpcode(RISCV::ADDI);
+ // Operand: rd
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: rs1
+ OutInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: imm12
+ OutInst.addOperand(MCOperand::createImm(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_NOP
+ case RISCV::C_OR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // or $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::OR);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) {
+ // or $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::OR);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_OR
+ case RISCV::C_SD: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // sd $rs2, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::SD);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SD
+ case RISCV::C_SDSP: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // sd $rs2, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::SD);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SDSP
+ case RISCV::C_SLLI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) {
+ // slli $rd, $rs1, $shamt
+ OutInst.setOpcode(RISCV::SLLI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: shamt
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SLLI
+ case RISCV::C_SRAI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) {
+ // srai $rd, $rs1, $shamt
+ OutInst.setOpcode(RISCV::SRAI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: shamt
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SRAI
+ case RISCV::C_SRLI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) {
+ // srli $rd, $rs1, $shamt
+ OutInst.setOpcode(RISCV::SRLI);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: shamt
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SRLI
+ case RISCV::C_SUB: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // sub $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::SUB);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SUB
+ case RISCV::C_SUBW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // subw $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::SUBW);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SUBW
+ case RISCV::C_SW: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // sw $rs2, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::SW);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SW
+ case RISCV::C_SWSP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) &&
+ RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) {
+ // sw $rs2, ${imm12}(${rs1})
+ OutInst.setOpcode(RISCV::SW);
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(1));
+ // Operand: imm12
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_SWSP
+ case RISCV::C_UNIMP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
+ // unimp
+ OutInst.setOpcode(RISCV::UNIMP);
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ break;
+ } // case C_UNIMP
+ case RISCV::C_XOR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // xor $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::XOR);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(2));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) {
+ // xor $rd, $rs1, $rs2
+ OutInst.setOpcode(RISCV::XOR);
+ // Operand: rd
+ OutInst.addOperand(MI.getOperand(0));
+ // Operand: rs1
+ OutInst.addOperand(MI.getOperand(2));
+ // Operand: rs2
+ OutInst.addOperand(MI.getOperand(0));
+ OutInst.setLoc(MI.getLoc());
+ return true;
+ } // if
+
+ } // case C_XOR
+ } // switch
+ return false;
+}
+
+#endif //GEN_UNCOMPRESS_INSTR
+
+
+#ifdef GEN_CHECK_COMPRESS_INSTR
+#undef GEN_CHECK_COMPRESS_INSTR
+
+static bool RISCVValidateMachineOperand(const MachineOperand &MO,
+ const RISCVSubtarget *Subtarget,
+ unsigned PredicateIndex) {
+ int64_t Imm = MO.getImm();
+ switch (PredicateIndex) {
+ default:
+ llvm_unreachable("Unknown ImmLeaf Predicate kind");
+ break;
+ case 1: {
+ // simm6nonzero
+ return (Imm != 0) && isInt<6>(Imm);
+ }
+ case 2: {
+ // simm10_lsb0000nonzero
+ return (Imm != 0) && isShiftedInt<6, 4>(Imm);
+ }
+ case 3: {
+ // uimm10_lsb00nonzero
+ return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
+ }
+ case 4: {
+ // simm6
+ return isInt<6>(Imm);
+ }
+ case 5: {
+ // simm9_lsb0
+ return isShiftedInt<8, 1>(Imm);
+ }
+ case 6: {
+ // uimm8_lsb000
+ return isShiftedUInt<5, 3>(Imm);
+ }
+ case 7: {
+ // uimm9_lsb000
+ return isShiftedUInt<6, 3>(Imm);
+ }
+ case 8: {
+ // uimm7_lsb00
+ return isShiftedUInt<5, 2>(Imm);
+ }
+ case 9: {
+ // uimm8_lsb00
+ return isShiftedUInt<6, 2>(Imm);
+ }
+ case 10: {
+ // simm12_lsb0
+ return isShiftedInt<11, 1>(Imm);
+ }
+ case 11: {
+ // c_lui_imm
+ return (Imm != 0) &&
+ (isUInt<5>(Imm) ||
+ (Imm >= 0xfffe0 && Imm <= 0xfffff));
+ }
+ case 12: {
+ // uimmlog2xlennonzero
+
+ if (Subtarget->is64Bit())
+ return isUInt<6>(Imm) && (Imm != 0);
+ return isUInt<5>(Imm) && (Imm != 0);
+
+ }
+ }
+}
+
+static bool isCompressibleInst(const MachineInstr& MI,
+ const RISCVSubtarget *Subtarget,
+ const MCRegisterInfo &MRI,
+ const MCSubtargetInfo &STI) {
+ switch (MI.getOpcode()) {
+ default: return false;
+ case RISCV::ADD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.add $rs1, $rs2
+ // Operand: rs1_wb
+ // Operand: rs1
+ // Operand: rs2
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.add $rs1, $rs2
+ // Operand: rs1_wb
+ // Operand: rs1
+ // Operand: rs2
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.mv $rs1, $rs2
+ // Operand: rs1
+ // Operand: rs2
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.mv $rs1, $rs2
+ // Operand: rs1
+ // Operand: rs2
+ return true;
+ } // if
+ break;
+ } // case ADD
+ case RISCV::ADDI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 1)) {
+ // c.addi $rd, $imm
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X2) &&
+ (MI.getOperand(1).getReg() == RISCV::X2) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 2)) {
+ // c.addi16sp $rd, $imm
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 3)) {
+ // c.addi4spn $rd, $rs1, $imm
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 4)) {
+ // c.li $rd, $imm
+ // Operand: rd
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(2).getImm() == 0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.mv $rs1, $rs2
+ // Operand: rs1
+ // Operand: rs2
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X0) &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(2).getImm() == 0)) {
+ // c.nop
+ return true;
+ } // if
+ break;
+ } // case ADDI
+ case RISCV::ADDIW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 4)) {
+ // c.addiw $rd, $imm
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 4)) {
+ // c.li $rd, $imm
+ // Operand: rd
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case ADDIW
+ case RISCV::ADDW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.addw $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.addw $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ break;
+ } // case ADDW
+ case RISCV::AND: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.and $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.and $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ break;
+ } // case AND
+ case RISCV::ANDI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 4)) {
+ // c.andi $rs1, $imm
+ // Operand: rs1_wb
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case ANDI
+ case RISCV::BEQ: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 5)) {
+ // c.beqz $rs1, $imm
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case BEQ
+ case RISCV::BNE: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == RISCV::X0) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 5)) {
+ // c.bnez $rs1, $imm
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case BNE
+ case RISCV::EBREAK: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
+ // c.ebreak
+ return true;
+ } // if
+ break;
+ } // case EBREAK
+ case RISCV::FLD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 6)) {
+ // c.fld $rd, ${imm}(${rs1})
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 7)) {
+ // c.fldsp $rd, ${imm}(${rs1})
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case FLD
+ case RISCV::FLW: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 8)) {
+ // c.flw $rd, ${imm}(${rs1})
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 9)) {
+ // c.flwsp $rd, ${imm}(${rs1})
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case FLW
+ case RISCV::FSD: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 6)) {
+ // c.fsd $rs2, ${imm}(${rs1})
+ // Operand: rs2
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
+ (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 7)) {
+ // c.fsdsp $rs2, ${imm}(${rs1})
+ // Operand: rs2
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case FSD
+ case RISCV::FSW: {
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 8)) {
+ // c.fsw $rs2, ${imm}(${rs1})
+ // Operand: rs2
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
+ (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 9)) {
+ // c.fswsp $rs2, ${imm}(${rs1})
+ // Operand: rs2
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case FSW
+ case RISCV::JAL: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X0) &&
+ MI.getOperand(1).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(1), Subtarget, 10)) {
+ // c.j $offset
+ // Operand: offset
+ return true;
+ } // if
+ if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X1) &&
+ MI.getOperand(1).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(1), Subtarget, 10)) {
+ // c.jal $offset
+ // Operand: offset
+ return true;
+ } // if
+ break;
+ } // case JAL
+ case RISCV::JALR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X1) &&
+ (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(2).getImm() == 0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.jalr $rs1
+ // Operand: rs1
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(0).getReg() == RISCV::X0) &&
+ (MI.getOperand(2).isImm()) &&
+ (MI.getOperand(2).getImm() == 0) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.jr $rs1
+ // Operand: rs1
+ return true;
+ } // if
+ break;
+ } // case JALR
+ case RISCV::LD: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 6)) {
+ // c.ld $rd, ${imm}(${rs1})
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 7)) {
+ // c.ldsp $rd, ${imm}(${rs1})
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case LD
+ case RISCV::LUI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRNoX0X2RegClassID).contains(MI.getOperand(0).getReg())) &&
+ MI.getOperand(1).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(1), Subtarget, 11)) {
+ // c.lui $rd, $imm
+ // Operand: rd
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case LUI
+ case RISCV::LW: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 8)) {
+ // c.lw $rd, ${imm}(${rs1})
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 9)) {
+ // c.lwsp $rd, ${imm}(${rs1})
+ // Operand: rd
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case LW
+ case RISCV::OR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.or $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.or $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ break;
+ } // case OR
+ case RISCV::SD: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 6)) {
+ // c.sd $rs2, ${imm}(${rs1})
+ // Operand: rs2
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 7)) {
+ // c.sdsp $rs2, ${imm}(${rs1})
+ // Operand: rs2
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case SD
+ case RISCV::SLLI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 12)) {
+ // c.slli $rd, $imm
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case SLLI
+ case RISCV::SRAI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 12)) {
+ // c.srai $rs1, $imm
+ // Operand: rs1_wb
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case SRAI
+ case RISCV::SRLI: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 12)) {
+ // c.srli $rs1, $imm
+ // Operand: rs1_wb
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case SRLI
+ case RISCV::SUB: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.sub $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ break;
+ } // case SUB
+ case RISCV::SUBW: {
+ if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
+ STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.subw $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ break;
+ } // case SUBW
+ case RISCV::SW: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 8)) {
+ // c.sw $rs2, ${imm}(${rs1})
+ // Operand: rs2
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) &&
+ (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) &&
+ MI.getOperand(2).isImm() &&
+ RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 9)) {
+ // c.swsp $rs2, ${imm}(${rs1})
+ // Operand: rs2
+ // Operand: rs1
+ // Operand: imm
+ return true;
+ } // if
+ break;
+ } // case SW
+ case RISCV::UNIMP: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
+ // c.unimp
+ return true;
+ } // if
+ break;
+ } // case UNIMP
+ case RISCV::XOR: {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) {
+ // c.xor $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC] &&
+ (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) &&
+ (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) {
+ // c.xor $rd, $rs2
+ // Operand: rd_wb
+ // Operand: rd
+ // Operand: rs2
+ return true;
+ } // if
+
+ } // case XOR
+ } // switch
+ return false;
+}
+
+#endif //GEN_CHECK_COMPRESS_INSTR
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenDAGISel.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenDAGISel.inc
new file mode 100644
index 0000000..aec8641
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenDAGISel.inc
@@ -0,0 +1,14257 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* DAG Instruction Selector for the RISCV target *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+// *** NOTE: This file is #included into the middle of the target
+// *** instruction selector class. These functions are really methods.
+
+// If GET_DAGISEL_DECL is #defined with any value, only function
+// declarations will be included when this file is included.
+// If GET_DAGISEL_BODY is #defined, its value should be the name of
+// the instruction selector class. Function bodies will be emitted
+// and each function's name will be qualified with the name of the
+// class.
+//
+// When neither of the GET_DAGISEL* macros is defined, the functions
+// are emitted inline.
+
+#if defined(GET_DAGISEL_DECL) && defined(GET_DAGISEL_BODY)
+#error GET_DAGISEL_DECL and GET_DAGISEL_BODY cannot be both defined, undef both for inline definitions
+#endif
+
+#ifdef GET_DAGISEL_BODY
+#define LOCAL_DAGISEL_STRINGIZE(X) LOCAL_DAGISEL_STRINGIZE_(X)
+#define LOCAL_DAGISEL_STRINGIZE_(X) #X
+static_assert(sizeof(LOCAL_DAGISEL_STRINGIZE(GET_DAGISEL_BODY)) > 1,
+ "GET_DAGISEL_BODY is empty: it should be defined with the class name");
+#undef LOCAL_DAGISEL_STRINGIZE_
+#undef LOCAL_DAGISEL_STRINGIZE
+#endif
+
+#if !defined(GET_DAGISEL_DECL) && !defined(GET_DAGISEL_BODY)
+#define DAGISEL_INLINE 1
+#else
+#define DAGISEL_INLINE 0
+#endif
+
+#if !DAGISEL_INLINE
+#define DAGISEL_CLASS_COLONCOLON GET_DAGISEL_BODY ::
+#else
+#define DAGISEL_CLASS_COLONCOLON
+#endif
+
+#ifdef GET_DAGISEL_DECL
+void SelectCode(SDNode *N);
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+void DAGISEL_CLASS_COLONCOLON SelectCode(SDNode *N)
+{
+ // Some target values are emitted as 2 bytes, TARGET_VAL handles
+ // this.
+ #define TARGET_VAL(X) X & 255, unsigned(X) >> 8
+ static const unsigned char MatcherTable[] = {
+/* 0*/ OPC_SwitchOpcode /*81 cases */, 12|128,5/*652*/, TARGET_VAL(ISD::AND),// ->657
+/* 5*/ OPC_Scope, 41|128,4/*553*/, /*->561*/ // 2 children in Scope
+/* 8*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 14*/ OPC_Scope, 75|128,3/*459*/, /*->476*/ // 2 children in Scope
+/* 17*/ OPC_MoveChild0,
+/* 18*/ OPC_SwitchOpcode /*2 cases */, 96|128,1/*224*/, TARGET_VAL(RISCVISD::DIVUW),// ->247
+/* 23*/ OPC_MoveChild0,
+/* 24*/ OPC_Scope, 110, /*->136*/ // 2 children in Scope
+/* 26*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 32*/ OPC_RecordChild0, // #0 = $rs1
+/* 33*/ OPC_MoveParent,
+/* 34*/ OPC_MoveChild1,
+/* 35*/ OPC_Scope, 49, /*->86*/ // 2 children in Scope
+/* 37*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 43*/ OPC_RecordChild0, // #1 = $rs2
+/* 44*/ OPC_MoveParent,
+/* 45*/ OPC_MoveParent,
+/* 46*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->73
+/* 49*/ OPC_Scope, 10, /*->61*/ // 2 children in Scope
+/* 51*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 53*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_divuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })), 4294967295:{ *:[i32] }) - Complexity = 27
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 61*/ /*Scope*/ 10, /*->72*/
+/* 62*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 64*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_divuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })), 4294967295:{ *:[i32] }) - Complexity = 27
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 72*/ 0, /*End of Scope*/
+/* 73*/ /*SwitchType*/ 10, MVT::i64,// ->85
+/* 75*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 77*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (riscv_divuw:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })), 4294967295:{ *:[i64] }) - Complexity = 27
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 85*/ 0, // EndSwitchType
+/* 86*/ /*Scope*/ 48, /*->135*/
+/* 87*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 90*/ OPC_RecordChild0, // #1 = $rs2
+/* 91*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 93*/ OPC_MoveParent,
+/* 94*/ OPC_MoveParent,
+/* 95*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->122
+/* 98*/ OPC_Scope, 10, /*->110*/ // 2 children in Scope
+/* 100*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 102*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_divuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i32] }) - Complexity = 23
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 110*/ /*Scope*/ 10, /*->121*/
+/* 111*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 113*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_divuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i32] }) - Complexity = 23
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 121*/ 0, /*End of Scope*/
+/* 122*/ /*SwitchType*/ 10, MVT::i64,// ->134
+/* 124*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 126*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (riscv_divuw:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i64] }) - Complexity = 23
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 134*/ 0, // EndSwitchType
+/* 135*/ 0, /*End of Scope*/
+/* 136*/ /*Scope*/ 109, /*->246*/
+/* 137*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 140*/ OPC_RecordChild0, // #0 = $rs1
+/* 141*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 143*/ OPC_MoveParent,
+/* 144*/ OPC_MoveChild1,
+/* 145*/ OPC_Scope, 49, /*->196*/ // 2 children in Scope
+/* 147*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 153*/ OPC_RecordChild0, // #1 = $rs2
+/* 154*/ OPC_MoveParent,
+/* 155*/ OPC_MoveParent,
+/* 156*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->183
+/* 159*/ OPC_Scope, 10, /*->171*/ // 2 children in Scope
+/* 161*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 163*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_divuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })), 4294967295:{ *:[i32] }) - Complexity = 23
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 171*/ /*Scope*/ 10, /*->182*/
+/* 172*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 174*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_divuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })), 4294967295:{ *:[i32] }) - Complexity = 23
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 182*/ 0, /*End of Scope*/
+/* 183*/ /*SwitchType*/ 10, MVT::i64,// ->195
+/* 185*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 187*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (riscv_divuw:{ *:[i64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })), 4294967295:{ *:[i64] }) - Complexity = 23
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 195*/ 0, // EndSwitchType
+/* 196*/ /*Scope*/ 48, /*->245*/
+/* 197*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 200*/ OPC_RecordChild0, // #1 = $rs2
+/* 201*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 203*/ OPC_MoveParent,
+/* 204*/ OPC_MoveParent,
+/* 205*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->232
+/* 208*/ OPC_Scope, 10, /*->220*/ // 2 children in Scope
+/* 210*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 212*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_divuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i32] }) - Complexity = 19
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 220*/ /*Scope*/ 10, /*->231*/
+/* 221*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 223*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_divuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i32] }) - Complexity = 19
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 231*/ 0, /*End of Scope*/
+/* 232*/ /*SwitchType*/ 10, MVT::i64,// ->244
+/* 234*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 236*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (riscv_divuw:{ *:[i64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i64] }) - Complexity = 19
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 244*/ 0, // EndSwitchType
+/* 245*/ 0, /*End of Scope*/
+/* 246*/ 0, /*End of Scope*/
+/* 247*/ /*SwitchOpcode*/ 96|128,1/*224*/, TARGET_VAL(RISCVISD::REMUW),// ->475
+/* 251*/ OPC_MoveChild0,
+/* 252*/ OPC_Scope, 110, /*->364*/ // 2 children in Scope
+/* 254*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 260*/ OPC_RecordChild0, // #0 = $rs1
+/* 261*/ OPC_MoveParent,
+/* 262*/ OPC_MoveChild1,
+/* 263*/ OPC_Scope, 49, /*->314*/ // 2 children in Scope
+/* 265*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 271*/ OPC_RecordChild0, // #1 = $rs2
+/* 272*/ OPC_MoveParent,
+/* 273*/ OPC_MoveParent,
+/* 274*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->301
+/* 277*/ OPC_Scope, 10, /*->289*/ // 2 children in Scope
+/* 279*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 281*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_remuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })), 4294967295:{ *:[i32] }) - Complexity = 27
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 289*/ /*Scope*/ 10, /*->300*/
+/* 290*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 292*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_remuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })), 4294967295:{ *:[i32] }) - Complexity = 27
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 300*/ 0, /*End of Scope*/
+/* 301*/ /*SwitchType*/ 10, MVT::i64,// ->313
+/* 303*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 305*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (riscv_remuw:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })), 4294967295:{ *:[i64] }) - Complexity = 27
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 313*/ 0, // EndSwitchType
+/* 314*/ /*Scope*/ 48, /*->363*/
+/* 315*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 318*/ OPC_RecordChild0, // #1 = $rs2
+/* 319*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 321*/ OPC_MoveParent,
+/* 322*/ OPC_MoveParent,
+/* 323*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->350
+/* 326*/ OPC_Scope, 10, /*->338*/ // 2 children in Scope
+/* 328*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 330*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_remuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i32] }) - Complexity = 23
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 338*/ /*Scope*/ 10, /*->349*/
+/* 339*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 341*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_remuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i32] }) - Complexity = 23
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 349*/ 0, /*End of Scope*/
+/* 350*/ /*SwitchType*/ 10, MVT::i64,// ->362
+/* 352*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 354*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (riscv_remuw:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i64] }) - Complexity = 23
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 362*/ 0, // EndSwitchType
+/* 363*/ 0, /*End of Scope*/
+/* 364*/ /*Scope*/ 109, /*->474*/
+/* 365*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 368*/ OPC_RecordChild0, // #0 = $rs1
+/* 369*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 371*/ OPC_MoveParent,
+/* 372*/ OPC_MoveChild1,
+/* 373*/ OPC_Scope, 49, /*->424*/ // 2 children in Scope
+/* 375*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 381*/ OPC_RecordChild0, // #1 = $rs2
+/* 382*/ OPC_MoveParent,
+/* 383*/ OPC_MoveParent,
+/* 384*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->411
+/* 387*/ OPC_Scope, 10, /*->399*/ // 2 children in Scope
+/* 389*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 391*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_remuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })), 4294967295:{ *:[i32] }) - Complexity = 23
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 399*/ /*Scope*/ 10, /*->410*/
+/* 400*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 402*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_remuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })), 4294967295:{ *:[i32] }) - Complexity = 23
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 410*/ 0, /*End of Scope*/
+/* 411*/ /*SwitchType*/ 10, MVT::i64,// ->423
+/* 413*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 415*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (riscv_remuw:{ *:[i64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })), 4294967295:{ *:[i64] }) - Complexity = 23
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 423*/ 0, // EndSwitchType
+/* 424*/ /*Scope*/ 48, /*->473*/
+/* 425*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 428*/ OPC_RecordChild0, // #1 = $rs2
+/* 429*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 431*/ OPC_MoveParent,
+/* 432*/ OPC_MoveParent,
+/* 433*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->460
+/* 436*/ OPC_Scope, 10, /*->448*/ // 2 children in Scope
+/* 438*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 440*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_remuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i32] }) - Complexity = 19
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 448*/ /*Scope*/ 10, /*->459*/
+/* 449*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 451*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } (riscv_remuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i32] }) - Complexity = 19
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 459*/ 0, /*End of Scope*/
+/* 460*/ /*SwitchType*/ 10, MVT::i64,// ->472
+/* 462*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 464*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } (riscv_remuw:{ *:[i64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertzexti32>>), 4294967295:{ *:[i64] }) - Complexity = 19
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 472*/ 0, // EndSwitchType
+/* 473*/ 0, /*End of Scope*/
+/* 474*/ 0, /*End of Scope*/
+/* 475*/ 0, // EndSwitchOpcode
+/* 476*/ /*Scope*/ 83, /*->560*/
+/* 477*/ OPC_RecordChild0, // #0 = $rs1
+/* 478*/ OPC_SwitchType /*2 cases */, 52, MVT::i32,// ->533
+/* 481*/ OPC_Scope, 24, /*->507*/ // 2 children in Scope
+/* 483*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 485*/ OPC_EmitInteger, MVT::i32, 32,
+/* 488*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLLI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 496*/ OPC_EmitInteger, MVT::i32, 32,
+/* 499*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }) - Complexity = 8
+ // Dst: (SRLI:{ *:[i32] } (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 32:{ *:[i32] }), 32:{ *:[i32] })
+/* 507*/ /*Scope*/ 24, /*->532*/
+/* 508*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 510*/ OPC_EmitInteger, MVT::i32, 32,
+/* 513*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLLI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 521*/ OPC_EmitInteger, MVT::i32, 32,
+/* 524*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }) - Complexity = 8
+ // Dst: (SRLI:{ *:[i32] } (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 32:{ *:[i32] }), 32:{ *:[i32] })
+/* 532*/ 0, /*End of Scope*/
+/* 533*/ /*SwitchType*/ 24, MVT::i64,// ->559
+/* 535*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 537*/ OPC_EmitInteger, MVT::i64, 32,
+/* 540*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLLI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #2
+/* 548*/ OPC_EmitInteger, MVT::i64, 32,
+/* 551*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLI), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }) - Complexity = 8
+ // Dst: (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), 32:{ *:[i64] })
+/* 559*/ 0, // EndSwitchType
+/* 560*/ 0, /*End of Scope*/
+/* 561*/ /*Scope*/ 94, /*->656*/
+/* 562*/ OPC_RecordChild0, // #0 = $rs1
+/* 563*/ OPC_RecordChild1, // #1 = $imm12
+/* 564*/ OPC_Scope, 51, /*->617*/ // 3 children in Scope
+/* 566*/ OPC_MoveChild1,
+/* 567*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 570*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 572*/ OPC_MoveParent,
+/* 573*/ OPC_SwitchType /*2 cases */, 26, MVT::i32,// ->602
+/* 576*/ OPC_Scope, 12, /*->590*/ // 2 children in Scope
+/* 578*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 580*/ OPC_EmitConvertToTarget, 1,
+/* 582*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ANDI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 590*/ /*Scope*/ 10, /*->601*/
+/* 591*/ OPC_EmitConvertToTarget, 1,
+/* 593*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ANDI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 601*/ 0, /*End of Scope*/
+/* 602*/ /*SwitchType*/ 12, MVT::i64,// ->616
+/* 604*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 606*/ OPC_EmitConvertToTarget, 1,
+/* 608*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ANDI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 616*/ 0, // EndSwitchType
+/* 617*/ /*Scope*/ 24, /*->642*/
+/* 618*/ OPC_CheckType, MVT::i32,
+/* 620*/ OPC_Scope, 10, /*->632*/ // 2 children in Scope
+/* 622*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 624*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 632*/ /*Scope*/ 8, /*->641*/
+/* 633*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 641*/ 0, /*End of Scope*/
+/* 642*/ /*Scope*/ 12, /*->655*/
+/* 643*/ OPC_CheckType, MVT::i64,
+/* 645*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 647*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (AND:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 655*/ 0, /*End of Scope*/
+/* 656*/ 0, /*End of Scope*/
+/* 657*/ /*SwitchOpcode*/ 91|128,3/*475*/, TARGET_VAL(ISD::AssertZext),// ->1136
+/* 661*/ OPC_MoveChild0,
+/* 662*/ OPC_SwitchOpcode /*2 cases */, 104|128,1/*232*/, TARGET_VAL(RISCVISD::DIVUW),// ->899
+/* 667*/ OPC_MoveChild0,
+/* 668*/ OPC_Scope, 114, /*->784*/ // 2 children in Scope
+/* 670*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 676*/ OPC_RecordChild0, // #0 = $rs1
+/* 677*/ OPC_MoveParent,
+/* 678*/ OPC_MoveChild1,
+/* 679*/ OPC_Scope, 51, /*->732*/ // 2 children in Scope
+/* 681*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 687*/ OPC_RecordChild0, // #1 = $rs2
+/* 688*/ OPC_MoveParent,
+/* 689*/ OPC_MoveParent,
+/* 690*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 692*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->719
+/* 695*/ OPC_Scope, 10, /*->707*/ // 2 children in Scope
+/* 697*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 699*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_divuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })))<<P:Predicate_assertzexti32>> - Complexity = 23
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 707*/ /*Scope*/ 10, /*->718*/
+/* 708*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 710*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_divuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })))<<P:Predicate_assertzexti32>> - Complexity = 23
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 718*/ 0, /*End of Scope*/
+/* 719*/ /*SwitchType*/ 10, MVT::i64,// ->731
+/* 721*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 723*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i64] } (riscv_divuw:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })))<<P:Predicate_assertzexti32>> - Complexity = 23
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 731*/ 0, // EndSwitchType
+/* 732*/ /*Scope*/ 50, /*->783*/
+/* 733*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 736*/ OPC_RecordChild0, // #1 = $rs2
+/* 737*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 739*/ OPC_MoveParent,
+/* 740*/ OPC_MoveParent,
+/* 741*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 743*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->770
+/* 746*/ OPC_Scope, 10, /*->758*/ // 2 children in Scope
+/* 748*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 750*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_divuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 758*/ /*Scope*/ 10, /*->769*/
+/* 759*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 761*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_divuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 769*/ 0, /*End of Scope*/
+/* 770*/ /*SwitchType*/ 10, MVT::i64,// ->782
+/* 772*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 774*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i64] } (riscv_divuw:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 782*/ 0, // EndSwitchType
+/* 783*/ 0, /*End of Scope*/
+/* 784*/ /*Scope*/ 113, /*->898*/
+/* 785*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 788*/ OPC_RecordChild0, // #0 = $rs1
+/* 789*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 791*/ OPC_MoveParent,
+/* 792*/ OPC_MoveChild1,
+/* 793*/ OPC_Scope, 51, /*->846*/ // 2 children in Scope
+/* 795*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 801*/ OPC_RecordChild0, // #1 = $rs2
+/* 802*/ OPC_MoveParent,
+/* 803*/ OPC_MoveParent,
+/* 804*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 806*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->833
+/* 809*/ OPC_Scope, 10, /*->821*/ // 2 children in Scope
+/* 811*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 813*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_divuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 821*/ /*Scope*/ 10, /*->832*/
+/* 822*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 824*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_divuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 832*/ 0, /*End of Scope*/
+/* 833*/ /*SwitchType*/ 10, MVT::i64,// ->845
+/* 835*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 837*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i64] } (riscv_divuw:{ *:[i64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 845*/ 0, // EndSwitchType
+/* 846*/ /*Scope*/ 50, /*->897*/
+/* 847*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 850*/ OPC_RecordChild0, // #1 = $rs2
+/* 851*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 853*/ OPC_MoveParent,
+/* 854*/ OPC_MoveParent,
+/* 855*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 857*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->884
+/* 860*/ OPC_Scope, 10, /*->872*/ // 2 children in Scope
+/* 862*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 864*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_divuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 15
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 872*/ /*Scope*/ 10, /*->883*/
+/* 873*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 875*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_divuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 15
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 883*/ 0, /*End of Scope*/
+/* 884*/ /*SwitchType*/ 10, MVT::i64,// ->896
+/* 886*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 888*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i64] } (riscv_divuw:{ *:[i64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 15
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 896*/ 0, // EndSwitchType
+/* 897*/ 0, /*End of Scope*/
+/* 898*/ 0, /*End of Scope*/
+/* 899*/ /*SwitchOpcode*/ 104|128,1/*232*/, TARGET_VAL(RISCVISD::REMUW),// ->1135
+/* 903*/ OPC_MoveChild0,
+/* 904*/ OPC_Scope, 114, /*->1020*/ // 2 children in Scope
+/* 906*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 912*/ OPC_RecordChild0, // #0 = $rs1
+/* 913*/ OPC_MoveParent,
+/* 914*/ OPC_MoveChild1,
+/* 915*/ OPC_Scope, 51, /*->968*/ // 2 children in Scope
+/* 917*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 923*/ OPC_RecordChild0, // #1 = $rs2
+/* 924*/ OPC_MoveParent,
+/* 925*/ OPC_MoveParent,
+/* 926*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 928*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->955
+/* 931*/ OPC_Scope, 10, /*->943*/ // 2 children in Scope
+/* 933*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 935*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_remuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })))<<P:Predicate_assertzexti32>> - Complexity = 23
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 943*/ /*Scope*/ 10, /*->954*/
+/* 944*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 946*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_remuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })))<<P:Predicate_assertzexti32>> - Complexity = 23
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 954*/ 0, /*End of Scope*/
+/* 955*/ /*SwitchType*/ 10, MVT::i64,// ->967
+/* 957*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 959*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i64] } (riscv_remuw:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })))<<P:Predicate_assertzexti32>> - Complexity = 23
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 967*/ 0, // EndSwitchType
+/* 968*/ /*Scope*/ 50, /*->1019*/
+/* 969*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 972*/ OPC_RecordChild0, // #1 = $rs2
+/* 973*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 975*/ OPC_MoveParent,
+/* 976*/ OPC_MoveParent,
+/* 977*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 979*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->1006
+/* 982*/ OPC_Scope, 10, /*->994*/ // 2 children in Scope
+/* 984*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 986*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_remuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 994*/ /*Scope*/ 10, /*->1005*/
+/* 995*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 997*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_remuw:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }), (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 1005*/ 0, /*End of Scope*/
+/* 1006*/ /*SwitchType*/ 10, MVT::i64,// ->1018
+/* 1008*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1010*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i64] } (riscv_remuw:{ *:[i64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }), (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 1018*/ 0, // EndSwitchType
+/* 1019*/ 0, /*End of Scope*/
+/* 1020*/ /*Scope*/ 113, /*->1134*/
+/* 1021*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 1024*/ OPC_RecordChild0, // #0 = $rs1
+/* 1025*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 1027*/ OPC_MoveParent,
+/* 1028*/ OPC_MoveChild1,
+/* 1029*/ OPC_Scope, 51, /*->1082*/ // 2 children in Scope
+/* 1031*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 1037*/ OPC_RecordChild0, // #1 = $rs2
+/* 1038*/ OPC_MoveParent,
+/* 1039*/ OPC_MoveParent,
+/* 1040*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 1042*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->1069
+/* 1045*/ OPC_Scope, 10, /*->1057*/ // 2 children in Scope
+/* 1047*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1049*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_remuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 1057*/ /*Scope*/ 10, /*->1068*/
+/* 1058*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 1060*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_remuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, 4294967295:{ *:[i32] })))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 1068*/ 0, /*End of Scope*/
+/* 1069*/ /*SwitchType*/ 10, MVT::i64,// ->1081
+/* 1071*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1073*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i64] } (riscv_remuw:{ *:[i64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, 4294967295:{ *:[i64] })))<<P:Predicate_assertzexti32>> - Complexity = 19
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 1081*/ 0, // EndSwitchType
+/* 1082*/ /*Scope*/ 50, /*->1133*/
+/* 1083*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 1086*/ OPC_RecordChild0, // #1 = $rs2
+/* 1087*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 1089*/ OPC_MoveParent,
+/* 1090*/ OPC_MoveParent,
+/* 1091*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 1093*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->1120
+/* 1096*/ OPC_Scope, 10, /*->1108*/ // 2 children in Scope
+/* 1098*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1100*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_remuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 15
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 1108*/ /*Scope*/ 10, /*->1119*/
+/* 1109*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 1111*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i32] } (riscv_remuw:{ *:[i32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 15
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 1119*/ 0, /*End of Scope*/
+/* 1120*/ /*SwitchType*/ 10, MVT::i64,// ->1132
+/* 1122*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1124*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (assertzext:{ *:[i64] } (riscv_remuw:{ *:[i64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>, (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertzexti32>>))<<P:Predicate_assertzexti32>> - Complexity = 15
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 1132*/ 0, // EndSwitchType
+/* 1133*/ 0, /*End of Scope*/
+/* 1134*/ 0, /*End of Scope*/
+/* 1135*/ 0, // EndSwitchOpcode
+/* 1136*/ /*SwitchOpcode*/ 80|128,30/*3920*/, TARGET_VAL(ISD::LOAD),// ->5060
+/* 1140*/ OPC_RecordMemRef,
+/* 1141*/ OPC_RecordNode, // #0 = 'ld' chained node
+/* 1142*/ OPC_Scope, 48|128,15/*1968*/, /*->3113*/ // 4 children in Scope
+/* 1145*/ OPC_MoveChild1,
+/* 1146*/ OPC_SwitchOpcode /*2 cases */, 57|128,5/*697*/, TARGET_VAL(ISD::OR),// ->1848
+/* 1151*/ OPC_RecordChild0, // #1 = $rs1
+/* 1152*/ OPC_RecordChild1, // #2 = $imm12
+/* 1153*/ OPC_MoveChild1,
+/* 1154*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 1157*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 1159*/ OPC_MoveParent,
+/* 1160*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 1162*/ OPC_SwitchType /*2 cases */, 59|128,3/*443*/, MVT::i32,// ->1609
+/* 1166*/ OPC_MoveParent,
+/* 1167*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 1169*/ OPC_CheckType, MVT::i32,
+/* 1171*/ OPC_Scope, 38, /*->1211*/ // 10 children in Scope
+/* 1173*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 1175*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 1177*/ OPC_Scope, 16, /*->1195*/ // 2 children in Scope
+/* 1179*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1181*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1184*/ OPC_EmitMergeInputChains1_0,
+/* 1185*/ OPC_EmitConvertToTarget, 2,
+/* 1187*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 18
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1195*/ /*Scope*/ 14, /*->1210*/
+/* 1196*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1199*/ OPC_EmitMergeInputChains1_0,
+/* 1200*/ OPC_EmitConvertToTarget, 2,
+/* 1202*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 18
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1210*/ 0, /*End of Scope*/
+/* 1211*/ /*Scope*/ 38, /*->1250*/
+/* 1212*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 1214*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 1216*/ OPC_Scope, 16, /*->1234*/ // 2 children in Scope
+/* 1218*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1220*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1223*/ OPC_EmitMergeInputChains1_0,
+/* 1224*/ OPC_EmitConvertToTarget, 2,
+/* 1226*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 18
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1234*/ /*Scope*/ 14, /*->1249*/
+/* 1235*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1238*/ OPC_EmitMergeInputChains1_0,
+/* 1239*/ OPC_EmitConvertToTarget, 2,
+/* 1241*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 18
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1249*/ 0, /*End of Scope*/
+/* 1250*/ /*Scope*/ 38, /*->1289*/
+/* 1251*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 1253*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 1255*/ OPC_Scope, 16, /*->1273*/ // 2 children in Scope
+/* 1257*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1259*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1262*/ OPC_EmitMergeInputChains1_0,
+/* 1263*/ OPC_EmitConvertToTarget, 2,
+/* 1265*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 18
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1273*/ /*Scope*/ 14, /*->1288*/
+/* 1274*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1277*/ OPC_EmitMergeInputChains1_0,
+/* 1278*/ OPC_EmitConvertToTarget, 2,
+/* 1280*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 18
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1288*/ 0, /*End of Scope*/
+/* 1289*/ /*Scope*/ 38, /*->1328*/
+/* 1290*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 1292*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 1294*/ OPC_Scope, 16, /*->1312*/ // 2 children in Scope
+/* 1296*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1298*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1301*/ OPC_EmitMergeInputChains1_0,
+/* 1302*/ OPC_EmitConvertToTarget, 2,
+/* 1304*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 18
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1312*/ /*Scope*/ 14, /*->1327*/
+/* 1313*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1316*/ OPC_EmitMergeInputChains1_0,
+/* 1317*/ OPC_EmitConvertToTarget, 2,
+/* 1319*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 18
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1327*/ 0, /*End of Scope*/
+/* 1328*/ /*Scope*/ 38, /*->1367*/
+/* 1329*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 1331*/ OPC_Scope, 16, /*->1349*/ // 2 children in Scope
+/* 1333*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1335*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1338*/ OPC_EmitMergeInputChains1_0,
+/* 1339*/ OPC_EmitConvertToTarget, 2,
+/* 1341*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1349*/ /*Scope*/ 16, /*->1366*/
+/* 1350*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 1352*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1355*/ OPC_EmitMergeInputChains1_0,
+/* 1356*/ OPC_EmitConvertToTarget, 2,
+/* 1358*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1366*/ 0, /*End of Scope*/
+/* 1367*/ /*Scope*/ 78, /*->1446*/
+/* 1368*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 1370*/ OPC_Scope, 36, /*->1408*/ // 2 children in Scope
+/* 1372*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 1374*/ OPC_Scope, 16, /*->1392*/ // 2 children in Scope
+/* 1376*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1378*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1381*/ OPC_EmitMergeInputChains1_0,
+/* 1382*/ OPC_EmitConvertToTarget, 2,
+/* 1384*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 18
+ // Dst: (LBU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1392*/ /*Scope*/ 14, /*->1407*/
+/* 1393*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1396*/ OPC_EmitMergeInputChains1_0,
+/* 1397*/ OPC_EmitConvertToTarget, 2,
+/* 1399*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 18
+ // Dst: (LBU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1407*/ 0, /*End of Scope*/
+/* 1408*/ /*Scope*/ 36, /*->1445*/
+/* 1409*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 1411*/ OPC_Scope, 16, /*->1429*/ // 2 children in Scope
+/* 1413*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1415*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1418*/ OPC_EmitMergeInputChains1_0,
+/* 1419*/ OPC_EmitConvertToTarget, 2,
+/* 1421*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 18
+ // Dst: (LHU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1429*/ /*Scope*/ 14, /*->1444*/
+/* 1430*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1433*/ OPC_EmitMergeInputChains1_0,
+/* 1434*/ OPC_EmitConvertToTarget, 2,
+/* 1436*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 18
+ // Dst: (LHU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1444*/ 0, /*End of Scope*/
+/* 1445*/ 0, /*End of Scope*/
+/* 1446*/ /*Scope*/ 40, /*->1487*/
+/* 1447*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 1449*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 1451*/ OPC_Scope, 16, /*->1469*/ // 2 children in Scope
+/* 1453*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1455*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1458*/ OPC_EmitMergeInputChains1_0,
+/* 1459*/ OPC_EmitConvertToTarget, 2,
+/* 1461*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 18
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1469*/ /*Scope*/ 16, /*->1486*/
+/* 1470*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 1472*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1475*/ OPC_EmitMergeInputChains1_0,
+/* 1476*/ OPC_EmitConvertToTarget, 2,
+/* 1478*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 18
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1486*/ 0, /*End of Scope*/
+/* 1487*/ /*Scope*/ 40, /*->1528*/
+/* 1488*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 1490*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 1492*/ OPC_Scope, 16, /*->1510*/ // 2 children in Scope
+/* 1494*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1496*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1499*/ OPC_EmitMergeInputChains1_0,
+/* 1500*/ OPC_EmitConvertToTarget, 2,
+/* 1502*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 18
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1510*/ /*Scope*/ 16, /*->1527*/
+/* 1511*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 1513*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1516*/ OPC_EmitMergeInputChains1_0,
+/* 1517*/ OPC_EmitConvertToTarget, 2,
+/* 1519*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 18
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1527*/ 0, /*End of Scope*/
+/* 1528*/ /*Scope*/ 40, /*->1569*/
+/* 1529*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 1531*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 1533*/ OPC_Scope, 16, /*->1551*/ // 2 children in Scope
+/* 1535*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1537*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1540*/ OPC_EmitMergeInputChains1_0,
+/* 1541*/ OPC_EmitConvertToTarget, 2,
+/* 1543*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 18
+ // Dst: (LWU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1551*/ /*Scope*/ 16, /*->1568*/
+/* 1552*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 1554*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1557*/ OPC_EmitMergeInputChains1_0,
+/* 1558*/ OPC_EmitConvertToTarget, 2,
+/* 1560*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 18
+ // Dst: (LWU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1568*/ 0, /*End of Scope*/
+/* 1569*/ /*Scope*/ 38, /*->1608*/
+/* 1570*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 1572*/ OPC_Scope, 16, /*->1590*/ // 2 children in Scope
+/* 1574*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1576*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1579*/ OPC_EmitMergeInputChains1_0,
+/* 1580*/ OPC_EmitConvertToTarget, 2,
+/* 1582*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1590*/ /*Scope*/ 16, /*->1607*/
+/* 1591*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 1593*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1596*/ OPC_EmitMergeInputChains1_0,
+/* 1597*/ OPC_EmitConvertToTarget, 2,
+/* 1599*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1607*/ 0, /*End of Scope*/
+/* 1608*/ 0, /*End of Scope*/
+/* 1609*/ /*SwitchType*/ 107|128,1/*235*/, MVT::i64,// ->1847
+/* 1612*/ OPC_MoveParent,
+/* 1613*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 1615*/ OPC_CheckType, MVT::i64,
+/* 1617*/ OPC_Scope, 20, /*->1639*/ // 10 children in Scope
+/* 1619*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 1621*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 1623*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1625*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1628*/ OPC_EmitMergeInputChains1_0,
+/* 1629*/ OPC_EmitConvertToTarget, 2,
+/* 1631*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 18
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1639*/ /*Scope*/ 20, /*->1660*/
+/* 1640*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 1642*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 1644*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1646*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1649*/ OPC_EmitMergeInputChains1_0,
+/* 1650*/ OPC_EmitConvertToTarget, 2,
+/* 1652*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 18
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1660*/ /*Scope*/ 20, /*->1681*/
+/* 1661*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 1663*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 1665*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1667*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1670*/ OPC_EmitMergeInputChains1_0,
+/* 1671*/ OPC_EmitConvertToTarget, 2,
+/* 1673*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 18
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1681*/ /*Scope*/ 20, /*->1702*/
+/* 1682*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 1684*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 1686*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1688*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1691*/ OPC_EmitMergeInputChains1_0,
+/* 1692*/ OPC_EmitConvertToTarget, 2,
+/* 1694*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 18
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1702*/ /*Scope*/ 18, /*->1721*/
+/* 1703*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 1705*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1707*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1710*/ OPC_EmitMergeInputChains1_0,
+/* 1711*/ OPC_EmitConvertToTarget, 2,
+/* 1713*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1721*/ /*Scope*/ 42, /*->1764*/
+/* 1722*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 1724*/ OPC_Scope, 18, /*->1744*/ // 2 children in Scope
+/* 1726*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 1728*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1730*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1733*/ OPC_EmitMergeInputChains1_0,
+/* 1734*/ OPC_EmitConvertToTarget, 2,
+/* 1736*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 18
+ // Dst: (LBU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1744*/ /*Scope*/ 18, /*->1763*/
+/* 1745*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 1747*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1749*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1752*/ OPC_EmitMergeInputChains1_0,
+/* 1753*/ OPC_EmitConvertToTarget, 2,
+/* 1755*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 18
+ // Dst: (LHU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1763*/ 0, /*End of Scope*/
+/* 1764*/ /*Scope*/ 20, /*->1785*/
+/* 1765*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 1767*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 1769*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1771*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1774*/ OPC_EmitMergeInputChains1_0,
+/* 1775*/ OPC_EmitConvertToTarget, 2,
+/* 1777*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 18
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1785*/ /*Scope*/ 20, /*->1806*/
+/* 1786*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 1788*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 1790*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1792*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1795*/ OPC_EmitMergeInputChains1_0,
+/* 1796*/ OPC_EmitConvertToTarget, 2,
+/* 1798*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 18
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1806*/ /*Scope*/ 20, /*->1827*/
+/* 1807*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 1809*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 1811*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1813*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1816*/ OPC_EmitMergeInputChains1_0,
+/* 1817*/ OPC_EmitConvertToTarget, 2,
+/* 1819*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 18
+ // Dst: (LWU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1827*/ /*Scope*/ 18, /*->1846*/
+/* 1828*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 1830*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 1832*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1835*/ OPC_EmitMergeInputChains1_0,
+/* 1836*/ OPC_EmitConvertToTarget, 2,
+/* 1838*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (LD:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 1846*/ 0, /*End of Scope*/
+/* 1847*/ 0, // EndSwitchType
+/* 1848*/ /*SwitchOpcode*/ 108|128,9/*1260*/, TARGET_VAL(ISD::ADD),// ->3112
+/* 1852*/ OPC_RecordChild0, // #1 = $rs1
+/* 1853*/ OPC_RecordChild1, // #2 = $imm12
+/* 1854*/ OPC_MoveChild1,
+/* 1855*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 1858*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 1860*/ OPC_MoveParent,
+/* 1861*/ OPC_SwitchType /*2 cases */, 45|128,6/*813*/, MVT::i32,// ->2678
+/* 1865*/ OPC_MoveParent,
+/* 1866*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 1868*/ OPC_CheckType, MVT::i32,
+/* 1870*/ OPC_Scope, 38, /*->1910*/ // 20 children in Scope
+/* 1872*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 1874*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 1876*/ OPC_Scope, 16, /*->1894*/ // 2 children in Scope
+/* 1878*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1880*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1883*/ OPC_EmitMergeInputChains1_0,
+/* 1884*/ OPC_EmitConvertToTarget, 2,
+/* 1886*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 17
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1894*/ /*Scope*/ 14, /*->1909*/
+/* 1895*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1898*/ OPC_EmitMergeInputChains1_0,
+/* 1899*/ OPC_EmitConvertToTarget, 2,
+/* 1901*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 17
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1909*/ 0, /*End of Scope*/
+/* 1910*/ /*Scope*/ 38, /*->1949*/
+/* 1911*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 1913*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 1915*/ OPC_Scope, 16, /*->1933*/ // 2 children in Scope
+/* 1917*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1919*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1922*/ OPC_EmitMergeInputChains1_0,
+/* 1923*/ OPC_EmitConvertToTarget, 2,
+/* 1925*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 17
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1933*/ /*Scope*/ 14, /*->1948*/
+/* 1934*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1937*/ OPC_EmitMergeInputChains1_0,
+/* 1938*/ OPC_EmitConvertToTarget, 2,
+/* 1940*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 17
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1948*/ 0, /*End of Scope*/
+/* 1949*/ /*Scope*/ 38, /*->1988*/
+/* 1950*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 1952*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 1954*/ OPC_Scope, 16, /*->1972*/ // 2 children in Scope
+/* 1956*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1958*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1961*/ OPC_EmitMergeInputChains1_0,
+/* 1962*/ OPC_EmitConvertToTarget, 2,
+/* 1964*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 17
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1972*/ /*Scope*/ 14, /*->1987*/
+/* 1973*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 1976*/ OPC_EmitMergeInputChains1_0,
+/* 1977*/ OPC_EmitConvertToTarget, 2,
+/* 1979*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 17
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 1987*/ 0, /*End of Scope*/
+/* 1988*/ /*Scope*/ 38, /*->2027*/
+/* 1989*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 1991*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 1993*/ OPC_Scope, 16, /*->2011*/ // 2 children in Scope
+/* 1995*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 1997*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2000*/ OPC_EmitMergeInputChains1_0,
+/* 2001*/ OPC_EmitConvertToTarget, 2,
+/* 2003*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 17
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2011*/ /*Scope*/ 14, /*->2026*/
+/* 2012*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2015*/ OPC_EmitMergeInputChains1_0,
+/* 2016*/ OPC_EmitConvertToTarget, 2,
+/* 2018*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 17
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2026*/ 0, /*End of Scope*/
+/* 2027*/ /*Scope*/ 38, /*->2066*/
+/* 2028*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 2030*/ OPC_Scope, 16, /*->2048*/ // 2 children in Scope
+/* 2032*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2034*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2037*/ OPC_EmitMergeInputChains1_0,
+/* 2038*/ OPC_EmitConvertToTarget, 2,
+/* 2040*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2048*/ /*Scope*/ 16, /*->2065*/
+/* 2049*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 2051*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2054*/ OPC_EmitMergeInputChains1_0,
+/* 2055*/ OPC_EmitConvertToTarget, 2,
+/* 2057*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2065*/ 0, /*End of Scope*/
+/* 2066*/ /*Scope*/ 78, /*->2145*/
+/* 2067*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 2069*/ OPC_Scope, 36, /*->2107*/ // 2 children in Scope
+/* 2071*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 2073*/ OPC_Scope, 16, /*->2091*/ // 2 children in Scope
+/* 2075*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2077*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2080*/ OPC_EmitMergeInputChains1_0,
+/* 2081*/ OPC_EmitConvertToTarget, 2,
+/* 2083*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 17
+ // Dst: (LBU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2091*/ /*Scope*/ 14, /*->2106*/
+/* 2092*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2095*/ OPC_EmitMergeInputChains1_0,
+/* 2096*/ OPC_EmitConvertToTarget, 2,
+/* 2098*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 17
+ // Dst: (LBU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2106*/ 0, /*End of Scope*/
+/* 2107*/ /*Scope*/ 36, /*->2144*/
+/* 2108*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 2110*/ OPC_Scope, 16, /*->2128*/ // 2 children in Scope
+/* 2112*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2114*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2117*/ OPC_EmitMergeInputChains1_0,
+/* 2118*/ OPC_EmitConvertToTarget, 2,
+/* 2120*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 17
+ // Dst: (LHU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2128*/ /*Scope*/ 14, /*->2143*/
+/* 2129*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2132*/ OPC_EmitMergeInputChains1_0,
+/* 2133*/ OPC_EmitConvertToTarget, 2,
+/* 2135*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 17
+ // Dst: (LHU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2143*/ 0, /*End of Scope*/
+/* 2144*/ 0, /*End of Scope*/
+/* 2145*/ /*Scope*/ 40, /*->2186*/
+/* 2146*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2148*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 2150*/ OPC_Scope, 16, /*->2168*/ // 2 children in Scope
+/* 2152*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2154*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2157*/ OPC_EmitMergeInputChains1_0,
+/* 2158*/ OPC_EmitConvertToTarget, 2,
+/* 2160*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 17
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2168*/ /*Scope*/ 16, /*->2185*/
+/* 2169*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 2171*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2174*/ OPC_EmitMergeInputChains1_0,
+/* 2175*/ OPC_EmitConvertToTarget, 2,
+/* 2177*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 17
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2185*/ 0, /*End of Scope*/
+/* 2186*/ /*Scope*/ 40, /*->2227*/
+/* 2187*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2189*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 2191*/ OPC_Scope, 16, /*->2209*/ // 2 children in Scope
+/* 2193*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2195*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2198*/ OPC_EmitMergeInputChains1_0,
+/* 2199*/ OPC_EmitConvertToTarget, 2,
+/* 2201*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 17
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2209*/ /*Scope*/ 16, /*->2226*/
+/* 2210*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 2212*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2215*/ OPC_EmitMergeInputChains1_0,
+/* 2216*/ OPC_EmitConvertToTarget, 2,
+/* 2218*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 17
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2226*/ 0, /*End of Scope*/
+/* 2227*/ /*Scope*/ 40, /*->2268*/
+/* 2228*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 2230*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 2232*/ OPC_Scope, 16, /*->2250*/ // 2 children in Scope
+/* 2234*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2236*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2239*/ OPC_EmitMergeInputChains1_0,
+/* 2240*/ OPC_EmitConvertToTarget, 2,
+/* 2242*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 17
+ // Dst: (LWU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2250*/ /*Scope*/ 16, /*->2267*/
+/* 2251*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 2253*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2256*/ OPC_EmitMergeInputChains1_0,
+/* 2257*/ OPC_EmitConvertToTarget, 2,
+/* 2259*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 17
+ // Dst: (LWU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2267*/ 0, /*End of Scope*/
+/* 2268*/ /*Scope*/ 38, /*->2307*/
+/* 2269*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 2271*/ OPC_Scope, 16, /*->2289*/ // 2 children in Scope
+/* 2273*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2275*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2278*/ OPC_EmitMergeInputChains1_0,
+/* 2279*/ OPC_EmitConvertToTarget, 2,
+/* 2281*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2289*/ /*Scope*/ 16, /*->2306*/
+/* 2290*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 2292*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2295*/ OPC_EmitMergeInputChains1_0,
+/* 2296*/ OPC_EmitConvertToTarget, 2,
+/* 2298*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2306*/ 0, /*End of Scope*/
+/* 2307*/ /*Scope*/ 32, /*->2340*/
+/* 2308*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2310*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 2312*/ OPC_Scope, 13, /*->2327*/ // 2 children in Scope
+/* 2314*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2316*/ OPC_EmitMergeInputChains1_0,
+/* 2317*/ OPC_EmitConvertToTarget, 2,
+/* 2319*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 11
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2327*/ /*Scope*/ 11, /*->2339*/
+/* 2328*/ OPC_EmitMergeInputChains1_0,
+/* 2329*/ OPC_EmitConvertToTarget, 2,
+/* 2331*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 11
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2339*/ 0, /*End of Scope*/
+/* 2340*/ /*Scope*/ 32, /*->2373*/
+/* 2341*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2343*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 2345*/ OPC_Scope, 13, /*->2360*/ // 2 children in Scope
+/* 2347*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2349*/ OPC_EmitMergeInputChains1_0,
+/* 2350*/ OPC_EmitConvertToTarget, 2,
+/* 2352*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 11
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2360*/ /*Scope*/ 11, /*->2372*/
+/* 2361*/ OPC_EmitMergeInputChains1_0,
+/* 2362*/ OPC_EmitConvertToTarget, 2,
+/* 2364*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 11
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2372*/ 0, /*End of Scope*/
+/* 2373*/ /*Scope*/ 32, /*->2406*/
+/* 2374*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2376*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 2378*/ OPC_Scope, 13, /*->2393*/ // 2 children in Scope
+/* 2380*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2382*/ OPC_EmitMergeInputChains1_0,
+/* 2383*/ OPC_EmitConvertToTarget, 2,
+/* 2385*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 11
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2393*/ /*Scope*/ 11, /*->2405*/
+/* 2394*/ OPC_EmitMergeInputChains1_0,
+/* 2395*/ OPC_EmitConvertToTarget, 2,
+/* 2397*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 11
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2405*/ 0, /*End of Scope*/
+/* 2406*/ /*Scope*/ 32, /*->2439*/
+/* 2407*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2409*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 2411*/ OPC_Scope, 13, /*->2426*/ // 2 children in Scope
+/* 2413*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2415*/ OPC_EmitMergeInputChains1_0,
+/* 2416*/ OPC_EmitConvertToTarget, 2,
+/* 2418*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 11
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2426*/ /*Scope*/ 11, /*->2438*/
+/* 2427*/ OPC_EmitMergeInputChains1_0,
+/* 2428*/ OPC_EmitConvertToTarget, 2,
+/* 2430*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 11
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2438*/ 0, /*End of Scope*/
+/* 2439*/ /*Scope*/ 32, /*->2472*/
+/* 2440*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 2442*/ OPC_Scope, 13, /*->2457*/ // 2 children in Scope
+/* 2444*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2446*/ OPC_EmitMergeInputChains1_0,
+/* 2447*/ OPC_EmitConvertToTarget, 2,
+/* 2449*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2457*/ /*Scope*/ 13, /*->2471*/
+/* 2458*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 2460*/ OPC_EmitMergeInputChains1_0,
+/* 2461*/ OPC_EmitConvertToTarget, 2,
+/* 2463*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2471*/ 0, /*End of Scope*/
+/* 2472*/ /*Scope*/ 66, /*->2539*/
+/* 2473*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 2475*/ OPC_Scope, 30, /*->2507*/ // 2 children in Scope
+/* 2477*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 2479*/ OPC_Scope, 13, /*->2494*/ // 2 children in Scope
+/* 2481*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2483*/ OPC_EmitMergeInputChains1_0,
+/* 2484*/ OPC_EmitConvertToTarget, 2,
+/* 2486*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 11
+ // Dst: (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2494*/ /*Scope*/ 11, /*->2506*/
+/* 2495*/ OPC_EmitMergeInputChains1_0,
+/* 2496*/ OPC_EmitConvertToTarget, 2,
+/* 2498*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 11
+ // Dst: (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2506*/ 0, /*End of Scope*/
+/* 2507*/ /*Scope*/ 30, /*->2538*/
+/* 2508*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 2510*/ OPC_Scope, 13, /*->2525*/ // 2 children in Scope
+/* 2512*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2514*/ OPC_EmitMergeInputChains1_0,
+/* 2515*/ OPC_EmitConvertToTarget, 2,
+/* 2517*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 11
+ // Dst: (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2525*/ /*Scope*/ 11, /*->2537*/
+/* 2526*/ OPC_EmitMergeInputChains1_0,
+/* 2527*/ OPC_EmitConvertToTarget, 2,
+/* 2529*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 11
+ // Dst: (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2537*/ 0, /*End of Scope*/
+/* 2538*/ 0, /*End of Scope*/
+/* 2539*/ /*Scope*/ 34, /*->2574*/
+/* 2540*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2542*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 2544*/ OPC_Scope, 13, /*->2559*/ // 2 children in Scope
+/* 2546*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2548*/ OPC_EmitMergeInputChains1_0,
+/* 2549*/ OPC_EmitConvertToTarget, 2,
+/* 2551*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 11
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2559*/ /*Scope*/ 13, /*->2573*/
+/* 2560*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 2562*/ OPC_EmitMergeInputChains1_0,
+/* 2563*/ OPC_EmitConvertToTarget, 2,
+/* 2565*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 11
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2573*/ 0, /*End of Scope*/
+/* 2574*/ /*Scope*/ 34, /*->2609*/
+/* 2575*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2577*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 2579*/ OPC_Scope, 13, /*->2594*/ // 2 children in Scope
+/* 2581*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2583*/ OPC_EmitMergeInputChains1_0,
+/* 2584*/ OPC_EmitConvertToTarget, 2,
+/* 2586*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 11
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2594*/ /*Scope*/ 13, /*->2608*/
+/* 2595*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 2597*/ OPC_EmitMergeInputChains1_0,
+/* 2598*/ OPC_EmitConvertToTarget, 2,
+/* 2600*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 11
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2608*/ 0, /*End of Scope*/
+/* 2609*/ /*Scope*/ 34, /*->2644*/
+/* 2610*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 2612*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 2614*/ OPC_Scope, 13, /*->2629*/ // 2 children in Scope
+/* 2616*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2618*/ OPC_EmitMergeInputChains1_0,
+/* 2619*/ OPC_EmitConvertToTarget, 2,
+/* 2621*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 11
+ // Dst: (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2629*/ /*Scope*/ 13, /*->2643*/
+/* 2630*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 2632*/ OPC_EmitMergeInputChains1_0,
+/* 2633*/ OPC_EmitConvertToTarget, 2,
+/* 2635*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 11
+ // Dst: (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2643*/ 0, /*End of Scope*/
+/* 2644*/ /*Scope*/ 32, /*->2677*/
+/* 2645*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 2647*/ OPC_Scope, 13, /*->2662*/ // 2 children in Scope
+/* 2649*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 2651*/ OPC_EmitMergeInputChains1_0,
+/* 2652*/ OPC_EmitConvertToTarget, 2,
+/* 2654*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2662*/ /*Scope*/ 13, /*->2676*/
+/* 2663*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 2665*/ OPC_EmitMergeInputChains1_0,
+/* 2666*/ OPC_EmitConvertToTarget, 2,
+/* 2668*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 2676*/ 0, /*End of Scope*/
+/* 2677*/ 0, /*End of Scope*/
+/* 2678*/ /*SwitchType*/ 46|128,3/*430*/, MVT::i64,// ->3111
+/* 2681*/ OPC_MoveParent,
+/* 2682*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 2684*/ OPC_CheckType, MVT::i64,
+/* 2686*/ OPC_Scope, 20, /*->2708*/ // 20 children in Scope
+/* 2688*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2690*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 2692*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2694*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2697*/ OPC_EmitMergeInputChains1_0,
+/* 2698*/ OPC_EmitConvertToTarget, 2,
+/* 2700*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 17
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2708*/ /*Scope*/ 20, /*->2729*/
+/* 2709*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2711*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 2713*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2715*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2718*/ OPC_EmitMergeInputChains1_0,
+/* 2719*/ OPC_EmitConvertToTarget, 2,
+/* 2721*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 17
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2729*/ /*Scope*/ 20, /*->2750*/
+/* 2730*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2732*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 2734*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2736*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2739*/ OPC_EmitMergeInputChains1_0,
+/* 2740*/ OPC_EmitConvertToTarget, 2,
+/* 2742*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 17
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2750*/ /*Scope*/ 20, /*->2771*/
+/* 2751*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2753*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 2755*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2757*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2760*/ OPC_EmitMergeInputChains1_0,
+/* 2761*/ OPC_EmitConvertToTarget, 2,
+/* 2763*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 17
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2771*/ /*Scope*/ 18, /*->2790*/
+/* 2772*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 2774*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2776*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2779*/ OPC_EmitMergeInputChains1_0,
+/* 2780*/ OPC_EmitConvertToTarget, 2,
+/* 2782*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2790*/ /*Scope*/ 42, /*->2833*/
+/* 2791*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 2793*/ OPC_Scope, 18, /*->2813*/ // 2 children in Scope
+/* 2795*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 2797*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2799*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2802*/ OPC_EmitMergeInputChains1_0,
+/* 2803*/ OPC_EmitConvertToTarget, 2,
+/* 2805*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 17
+ // Dst: (LBU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2813*/ /*Scope*/ 18, /*->2832*/
+/* 2814*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 2816*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2818*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2821*/ OPC_EmitMergeInputChains1_0,
+/* 2822*/ OPC_EmitConvertToTarget, 2,
+/* 2824*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 17
+ // Dst: (LHU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2832*/ 0, /*End of Scope*/
+/* 2833*/ /*Scope*/ 20, /*->2854*/
+/* 2834*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2836*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 2838*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2840*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2843*/ OPC_EmitMergeInputChains1_0,
+/* 2844*/ OPC_EmitConvertToTarget, 2,
+/* 2846*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 17
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2854*/ /*Scope*/ 20, /*->2875*/
+/* 2855*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2857*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 2859*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2861*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2864*/ OPC_EmitMergeInputChains1_0,
+/* 2865*/ OPC_EmitConvertToTarget, 2,
+/* 2867*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 17
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2875*/ /*Scope*/ 20, /*->2896*/
+/* 2876*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 2878*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 2880*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2882*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2885*/ OPC_EmitMergeInputChains1_0,
+/* 2886*/ OPC_EmitConvertToTarget, 2,
+/* 2888*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 17
+ // Dst: (LWU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2896*/ /*Scope*/ 18, /*->2915*/
+/* 2897*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 2899*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2901*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 2904*/ OPC_EmitMergeInputChains1_0,
+/* 2905*/ OPC_EmitConvertToTarget, 2,
+/* 2907*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (LD:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2915*/ /*Scope*/ 17, /*->2933*/
+/* 2916*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2918*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 2920*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2922*/ OPC_EmitMergeInputChains1_0,
+/* 2923*/ OPC_EmitConvertToTarget, 2,
+/* 2925*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 11
+ // Dst: (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2933*/ /*Scope*/ 17, /*->2951*/
+/* 2934*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2936*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 2938*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2940*/ OPC_EmitMergeInputChains1_0,
+/* 2941*/ OPC_EmitConvertToTarget, 2,
+/* 2943*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 11
+ // Dst: (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2951*/ /*Scope*/ 17, /*->2969*/
+/* 2952*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 2954*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 2956*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2958*/ OPC_EmitMergeInputChains1_0,
+/* 2959*/ OPC_EmitConvertToTarget, 2,
+/* 2961*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 11
+ // Dst: (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2969*/ /*Scope*/ 17, /*->2987*/
+/* 2970*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 2972*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 2974*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2976*/ OPC_EmitMergeInputChains1_0,
+/* 2977*/ OPC_EmitConvertToTarget, 2,
+/* 2979*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 11
+ // Dst: (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 2987*/ /*Scope*/ 15, /*->3003*/
+/* 2988*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 2990*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 2992*/ OPC_EmitMergeInputChains1_0,
+/* 2993*/ OPC_EmitConvertToTarget, 2,
+/* 2995*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 3003*/ /*Scope*/ 36, /*->3040*/
+/* 3004*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 3006*/ OPC_Scope, 15, /*->3023*/ // 2 children in Scope
+/* 3008*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 3010*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3012*/ OPC_EmitMergeInputChains1_0,
+/* 3013*/ OPC_EmitConvertToTarget, 2,
+/* 3015*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 11
+ // Dst: (LBU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 3023*/ /*Scope*/ 15, /*->3039*/
+/* 3024*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 3026*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3028*/ OPC_EmitMergeInputChains1_0,
+/* 3029*/ OPC_EmitConvertToTarget, 2,
+/* 3031*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 11
+ // Dst: (LHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 3039*/ 0, /*End of Scope*/
+/* 3040*/ /*Scope*/ 17, /*->3058*/
+/* 3041*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 3043*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 3045*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3047*/ OPC_EmitMergeInputChains1_0,
+/* 3048*/ OPC_EmitConvertToTarget, 2,
+/* 3050*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 11
+ // Dst: (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 3058*/ /*Scope*/ 17, /*->3076*/
+/* 3059*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 3061*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 3063*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3065*/ OPC_EmitMergeInputChains1_0,
+/* 3066*/ OPC_EmitConvertToTarget, 2,
+/* 3068*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 11
+ // Dst: (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 3076*/ /*Scope*/ 17, /*->3094*/
+/* 3077*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 3079*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 3081*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3083*/ OPC_EmitMergeInputChains1_0,
+/* 3084*/ OPC_EmitConvertToTarget, 2,
+/* 3086*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 11
+ // Dst: (LWU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 3094*/ /*Scope*/ 15, /*->3110*/
+/* 3095*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 3097*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3099*/ OPC_EmitMergeInputChains1_0,
+/* 3100*/ OPC_EmitConvertToTarget, 2,
+/* 3102*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 3110*/ 0, /*End of Scope*/
+/* 3111*/ 0, // EndSwitchType
+/* 3112*/ 0, // EndSwitchOpcode
+/* 3113*/ /*Scope*/ 51|128,10/*1331*/, /*->4446*/
+/* 3115*/ OPC_RecordChild1, // #1 = $rs1
+/* 3116*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 3118*/ OPC_Scope, 63, /*->3183*/ // 12 children in Scope
+/* 3120*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 3122*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 3124*/ OPC_SwitchType /*2 cases */, 36, MVT::i32,// ->3163
+/* 3127*/ OPC_Scope, 17, /*->3146*/ // 2 children in Scope
+/* 3129*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3131*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3134*/ OPC_EmitMergeInputChains1_0,
+/* 3135*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3138*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 10
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3146*/ /*Scope*/ 15, /*->3162*/
+/* 3147*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3150*/ OPC_EmitMergeInputChains1_0,
+/* 3151*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3154*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 10
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3162*/ 0, /*End of Scope*/
+/* 3163*/ /*SwitchType*/ 17, MVT::i64,// ->3182
+/* 3165*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3167*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3170*/ OPC_EmitMergeInputChains1_0,
+/* 3171*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3174*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 10
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3182*/ 0, // EndSwitchType
+/* 3183*/ /*Scope*/ 63, /*->3247*/
+/* 3184*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 3186*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 3188*/ OPC_SwitchType /*2 cases */, 36, MVT::i32,// ->3227
+/* 3191*/ OPC_Scope, 17, /*->3210*/ // 2 children in Scope
+/* 3193*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3195*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3198*/ OPC_EmitMergeInputChains1_0,
+/* 3199*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3202*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 10
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3210*/ /*Scope*/ 15, /*->3226*/
+/* 3211*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3214*/ OPC_EmitMergeInputChains1_0,
+/* 3215*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3218*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 10
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3226*/ 0, /*End of Scope*/
+/* 3227*/ /*SwitchType*/ 17, MVT::i64,// ->3246
+/* 3229*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3231*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3234*/ OPC_EmitMergeInputChains1_0,
+/* 3235*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3238*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 10
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3246*/ 0, // EndSwitchType
+/* 3247*/ /*Scope*/ 63, /*->3311*/
+/* 3248*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 3250*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 3252*/ OPC_SwitchType /*2 cases */, 36, MVT::i32,// ->3291
+/* 3255*/ OPC_Scope, 17, /*->3274*/ // 2 children in Scope
+/* 3257*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3259*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3262*/ OPC_EmitMergeInputChains1_0,
+/* 3263*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3266*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 10
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3274*/ /*Scope*/ 15, /*->3290*/
+/* 3275*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3278*/ OPC_EmitMergeInputChains1_0,
+/* 3279*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3282*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 10
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3290*/ 0, /*End of Scope*/
+/* 3291*/ /*SwitchType*/ 17, MVT::i64,// ->3310
+/* 3293*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3295*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3298*/ OPC_EmitMergeInputChains1_0,
+/* 3299*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3302*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 10
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3310*/ 0, // EndSwitchType
+/* 3311*/ /*Scope*/ 63, /*->3375*/
+/* 3312*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 3314*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 3316*/ OPC_SwitchType /*2 cases */, 36, MVT::i32,// ->3355
+/* 3319*/ OPC_Scope, 17, /*->3338*/ // 2 children in Scope
+/* 3321*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3323*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3326*/ OPC_EmitMergeInputChains1_0,
+/* 3327*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3330*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 10
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3338*/ /*Scope*/ 15, /*->3354*/
+/* 3339*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3342*/ OPC_EmitMergeInputChains1_0,
+/* 3343*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3346*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 10
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3354*/ 0, /*End of Scope*/
+/* 3355*/ /*SwitchType*/ 17, MVT::i64,// ->3374
+/* 3357*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3359*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3362*/ OPC_EmitMergeInputChains1_0,
+/* 3363*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3366*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 10
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3374*/ 0, // EndSwitchType
+/* 3375*/ /*Scope*/ 63, /*->3439*/
+/* 3376*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 3378*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->3419
+/* 3381*/ OPC_Scope, 17, /*->3400*/ // 2 children in Scope
+/* 3383*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3385*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3388*/ OPC_EmitMergeInputChains1_0,
+/* 3389*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3392*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3400*/ /*Scope*/ 17, /*->3418*/
+/* 3401*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 3403*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3406*/ OPC_EmitMergeInputChains1_0,
+/* 3407*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3410*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3418*/ 0, /*End of Scope*/
+/* 3419*/ /*SwitchType*/ 17, MVT::i64,// ->3438
+/* 3421*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3423*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3426*/ OPC_EmitMergeInputChains1_0,
+/* 3427*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3430*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3438*/ 0, // EndSwitchType
+/* 3439*/ /*Scope*/ 0|128,1/*128*/, /*->3569*/
+/* 3441*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 3443*/ OPC_Scope, 61, /*->3506*/ // 2 children in Scope
+/* 3445*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 3447*/ OPC_SwitchType /*2 cases */, 36, MVT::i32,// ->3486
+/* 3450*/ OPC_Scope, 17, /*->3469*/ // 2 children in Scope
+/* 3452*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3454*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3457*/ OPC_EmitMergeInputChains1_0,
+/* 3458*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3461*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 10
+ // Dst: (LBU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3469*/ /*Scope*/ 15, /*->3485*/
+/* 3470*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3473*/ OPC_EmitMergeInputChains1_0,
+/* 3474*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3477*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 10
+ // Dst: (LBU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3485*/ 0, /*End of Scope*/
+/* 3486*/ /*SwitchType*/ 17, MVT::i64,// ->3505
+/* 3488*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3490*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3493*/ OPC_EmitMergeInputChains1_0,
+/* 3494*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3497*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 10
+ // Dst: (LBU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3505*/ 0, // EndSwitchType
+/* 3506*/ /*Scope*/ 61, /*->3568*/
+/* 3507*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 3509*/ OPC_SwitchType /*2 cases */, 36, MVT::i32,// ->3548
+/* 3512*/ OPC_Scope, 17, /*->3531*/ // 2 children in Scope
+/* 3514*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3516*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3519*/ OPC_EmitMergeInputChains1_0,
+/* 3520*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3523*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 10
+ // Dst: (LHU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3531*/ /*Scope*/ 15, /*->3547*/
+/* 3532*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3535*/ OPC_EmitMergeInputChains1_0,
+/* 3536*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3539*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 10
+ // Dst: (LHU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3547*/ 0, /*End of Scope*/
+/* 3548*/ /*SwitchType*/ 17, MVT::i64,// ->3567
+/* 3550*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3552*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3555*/ OPC_EmitMergeInputChains1_0,
+/* 3556*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3559*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 10
+ // Dst: (LHU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3567*/ 0, // EndSwitchType
+/* 3568*/ 0, /*End of Scope*/
+/* 3569*/ /*Scope*/ 65, /*->3635*/
+/* 3570*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 3572*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 3574*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->3615
+/* 3577*/ OPC_Scope, 17, /*->3596*/ // 2 children in Scope
+/* 3579*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3581*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3584*/ OPC_EmitMergeInputChains1_0,
+/* 3585*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3588*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 10
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3596*/ /*Scope*/ 17, /*->3614*/
+/* 3597*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 3599*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3602*/ OPC_EmitMergeInputChains1_0,
+/* 3603*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3606*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 10
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3614*/ 0, /*End of Scope*/
+/* 3615*/ /*SwitchType*/ 17, MVT::i64,// ->3634
+/* 3617*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3619*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3622*/ OPC_EmitMergeInputChains1_0,
+/* 3623*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3626*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 10
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3634*/ 0, // EndSwitchType
+/* 3635*/ /*Scope*/ 65, /*->3701*/
+/* 3636*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 3638*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 3640*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->3681
+/* 3643*/ OPC_Scope, 17, /*->3662*/ // 2 children in Scope
+/* 3645*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3647*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3650*/ OPC_EmitMergeInputChains1_0,
+/* 3651*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3654*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 10
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3662*/ /*Scope*/ 17, /*->3680*/
+/* 3663*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 3665*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3668*/ OPC_EmitMergeInputChains1_0,
+/* 3669*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3672*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 10
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3680*/ 0, /*End of Scope*/
+/* 3681*/ /*SwitchType*/ 17, MVT::i64,// ->3700
+/* 3683*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3685*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3688*/ OPC_EmitMergeInputChains1_0,
+/* 3689*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3692*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 10
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3700*/ 0, // EndSwitchType
+/* 3701*/ /*Scope*/ 65, /*->3767*/
+/* 3702*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 3704*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 3706*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->3747
+/* 3709*/ OPC_Scope, 17, /*->3728*/ // 2 children in Scope
+/* 3711*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3713*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3716*/ OPC_EmitMergeInputChains1_0,
+/* 3717*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3720*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 10
+ // Dst: (LWU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3728*/ /*Scope*/ 17, /*->3746*/
+/* 3729*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 3731*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3734*/ OPC_EmitMergeInputChains1_0,
+/* 3735*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3738*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 10
+ // Dst: (LWU:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3746*/ 0, /*End of Scope*/
+/* 3747*/ /*SwitchType*/ 17, MVT::i64,// ->3766
+/* 3749*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3751*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3754*/ OPC_EmitMergeInputChains1_0,
+/* 3755*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3758*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 10
+ // Dst: (LWU:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3766*/ 0, // EndSwitchType
+/* 3767*/ /*Scope*/ 63, /*->3831*/
+/* 3768*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 3770*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->3811
+/* 3773*/ OPC_Scope, 17, /*->3792*/ // 2 children in Scope
+/* 3775*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3777*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3780*/ OPC_EmitMergeInputChains1_0,
+/* 3781*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3784*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3792*/ /*Scope*/ 17, /*->3810*/
+/* 3793*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 3795*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3798*/ OPC_EmitMergeInputChains1_0,
+/* 3799*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3802*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3810*/ 0, /*End of Scope*/
+/* 3811*/ /*SwitchType*/ 17, MVT::i64,// ->3830
+/* 3813*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 3815*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 3818*/ OPC_EmitMergeInputChains1_0,
+/* 3819*/ OPC_EmitInteger, MVT::i64, 0,
+/* 3822*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (LD:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 3830*/ 0, // EndSwitchType
+/* 3831*/ /*Scope*/ 14|128,3/*398*/, /*->4231*/
+/* 3833*/ OPC_CheckChild1Type, MVT::i32,
+/* 3835*/ OPC_CheckType, MVT::i32,
+/* 3837*/ OPC_Scope, 34, /*->3873*/ // 10 children in Scope
+/* 3839*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 3841*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 3843*/ OPC_Scope, 14, /*->3859*/ // 2 children in Scope
+/* 3845*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3847*/ OPC_EmitMergeInputChains1_0,
+/* 3848*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3851*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 4
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3859*/ /*Scope*/ 12, /*->3872*/
+/* 3860*/ OPC_EmitMergeInputChains1_0,
+/* 3861*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3864*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 4
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3872*/ 0, /*End of Scope*/
+/* 3873*/ /*Scope*/ 34, /*->3908*/
+/* 3874*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 3876*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 3878*/ OPC_Scope, 14, /*->3894*/ // 2 children in Scope
+/* 3880*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3882*/ OPC_EmitMergeInputChains1_0,
+/* 3883*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3886*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 4
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3894*/ /*Scope*/ 12, /*->3907*/
+/* 3895*/ OPC_EmitMergeInputChains1_0,
+/* 3896*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3899*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 4
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3907*/ 0, /*End of Scope*/
+/* 3908*/ /*Scope*/ 34, /*->3943*/
+/* 3909*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 3911*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 3913*/ OPC_Scope, 14, /*->3929*/ // 2 children in Scope
+/* 3915*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3917*/ OPC_EmitMergeInputChains1_0,
+/* 3918*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3921*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 4
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3929*/ /*Scope*/ 12, /*->3942*/
+/* 3930*/ OPC_EmitMergeInputChains1_0,
+/* 3931*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3934*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 4
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3942*/ 0, /*End of Scope*/
+/* 3943*/ /*Scope*/ 34, /*->3978*/
+/* 3944*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 3946*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 3948*/ OPC_Scope, 14, /*->3964*/ // 2 children in Scope
+/* 3950*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3952*/ OPC_EmitMergeInputChains1_0,
+/* 3953*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3956*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 4
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3964*/ /*Scope*/ 12, /*->3977*/
+/* 3965*/ OPC_EmitMergeInputChains1_0,
+/* 3966*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3969*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 4
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3977*/ 0, /*End of Scope*/
+/* 3978*/ /*Scope*/ 34, /*->4013*/
+/* 3979*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 3981*/ OPC_Scope, 14, /*->3997*/ // 2 children in Scope
+/* 3983*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 3985*/ OPC_EmitMergeInputChains1_0,
+/* 3986*/ OPC_EmitInteger, MVT::i32, 0,
+/* 3989*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 3997*/ /*Scope*/ 14, /*->4012*/
+/* 3998*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 4000*/ OPC_EmitMergeInputChains1_0,
+/* 4001*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4004*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4012*/ 0, /*End of Scope*/
+/* 4013*/ /*Scope*/ 70, /*->4084*/
+/* 4014*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 4016*/ OPC_Scope, 32, /*->4050*/ // 2 children in Scope
+/* 4018*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 4020*/ OPC_Scope, 14, /*->4036*/ // 2 children in Scope
+/* 4022*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4024*/ OPC_EmitMergeInputChains1_0,
+/* 4025*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4028*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 4
+ // Dst: (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4036*/ /*Scope*/ 12, /*->4049*/
+/* 4037*/ OPC_EmitMergeInputChains1_0,
+/* 4038*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4041*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 4
+ // Dst: (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4049*/ 0, /*End of Scope*/
+/* 4050*/ /*Scope*/ 32, /*->4083*/
+/* 4051*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 4053*/ OPC_Scope, 14, /*->4069*/ // 2 children in Scope
+/* 4055*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4057*/ OPC_EmitMergeInputChains1_0,
+/* 4058*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4061*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 4
+ // Dst: (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4069*/ /*Scope*/ 12, /*->4082*/
+/* 4070*/ OPC_EmitMergeInputChains1_0,
+/* 4071*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4074*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 4
+ // Dst: (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4082*/ 0, /*End of Scope*/
+/* 4083*/ 0, /*End of Scope*/
+/* 4084*/ /*Scope*/ 36, /*->4121*/
+/* 4085*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 4087*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 4089*/ OPC_Scope, 14, /*->4105*/ // 2 children in Scope
+/* 4091*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4093*/ OPC_EmitMergeInputChains1_0,
+/* 4094*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4097*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 4
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4105*/ /*Scope*/ 14, /*->4120*/
+/* 4106*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 4108*/ OPC_EmitMergeInputChains1_0,
+/* 4109*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4112*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 4
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4120*/ 0, /*End of Scope*/
+/* 4121*/ /*Scope*/ 36, /*->4158*/
+/* 4122*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 4124*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 4126*/ OPC_Scope, 14, /*->4142*/ // 2 children in Scope
+/* 4128*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4130*/ OPC_EmitMergeInputChains1_0,
+/* 4131*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4134*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 4
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4142*/ /*Scope*/ 14, /*->4157*/
+/* 4143*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 4145*/ OPC_EmitMergeInputChains1_0,
+/* 4146*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4149*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 4
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4157*/ 0, /*End of Scope*/
+/* 4158*/ /*Scope*/ 36, /*->4195*/
+/* 4159*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 4161*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 4163*/ OPC_Scope, 14, /*->4179*/ // 2 children in Scope
+/* 4165*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4167*/ OPC_EmitMergeInputChains1_0,
+/* 4168*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4171*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 4
+ // Dst: (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4179*/ /*Scope*/ 14, /*->4194*/
+/* 4180*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 4182*/ OPC_EmitMergeInputChains1_0,
+/* 4183*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4186*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 4
+ // Dst: (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4194*/ 0, /*End of Scope*/
+/* 4195*/ /*Scope*/ 34, /*->4230*/
+/* 4196*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 4198*/ OPC_Scope, 14, /*->4214*/ // 2 children in Scope
+/* 4200*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4202*/ OPC_EmitMergeInputChains1_0,
+/* 4203*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4206*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4214*/ /*Scope*/ 14, /*->4229*/
+/* 4215*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 4217*/ OPC_EmitMergeInputChains1_0,
+/* 4218*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4221*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4229*/ 0, /*End of Scope*/
+/* 4230*/ 0, /*End of Scope*/
+/* 4231*/ /*Scope*/ 84|128,1/*212*/, /*->4445*/
+/* 4233*/ OPC_CheckChild1Type, MVT::i64,
+/* 4235*/ OPC_CheckType, MVT::i64,
+/* 4237*/ OPC_Scope, 18, /*->4257*/ // 10 children in Scope
+/* 4239*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 4241*/ OPC_CheckPredicate, 5, // Predicate_sextloadi8
+/* 4243*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4245*/ OPC_EmitMergeInputChains1_0,
+/* 4246*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4249*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> - Complexity = 4
+ // Dst: (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4257*/ /*Scope*/ 18, /*->4276*/
+/* 4258*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 4260*/ OPC_CheckPredicate, 5, // Predicate_extloadi8
+/* 4262*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4264*/ OPC_EmitMergeInputChains1_0,
+/* 4265*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4268*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> - Complexity = 4
+ // Dst: (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4276*/ /*Scope*/ 18, /*->4295*/
+/* 4277*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 4279*/ OPC_CheckPredicate, 7, // Predicate_sextloadi16
+/* 4281*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4283*/ OPC_EmitMergeInputChains1_0,
+/* 4284*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4287*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> - Complexity = 4
+ // Dst: (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4295*/ /*Scope*/ 18, /*->4314*/
+/* 4296*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 4298*/ OPC_CheckPredicate, 7, // Predicate_extloadi16
+/* 4300*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4302*/ OPC_EmitMergeInputChains1_0,
+/* 4303*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4306*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> - Complexity = 4
+ // Dst: (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4314*/ /*Scope*/ 16, /*->4331*/
+/* 4315*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 4317*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4319*/ OPC_EmitMergeInputChains1_0,
+/* 4320*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4323*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4331*/ /*Scope*/ 38, /*->4370*/
+/* 4332*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 4334*/ OPC_Scope, 16, /*->4352*/ // 2 children in Scope
+/* 4336*/ OPC_CheckPredicate, 5, // Predicate_zextloadi8
+/* 4338*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4340*/ OPC_EmitMergeInputChains1_0,
+/* 4341*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4344*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LBU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> - Complexity = 4
+ // Dst: (LBU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4352*/ /*Scope*/ 16, /*->4369*/
+/* 4353*/ OPC_CheckPredicate, 7, // Predicate_zextloadi16
+/* 4355*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4357*/ OPC_EmitMergeInputChains1_0,
+/* 4358*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4361*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LHU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> - Complexity = 4
+ // Dst: (LHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4369*/ 0, /*End of Scope*/
+/* 4370*/ /*Scope*/ 18, /*->4389*/
+/* 4371*/ OPC_CheckPredicate, 4, // Predicate_sextload
+/* 4373*/ OPC_CheckPredicate, 10, // Predicate_sextloadi32
+/* 4375*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4377*/ OPC_EmitMergeInputChains1_0,
+/* 4378*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4381*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> - Complexity = 4
+ // Dst: (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4389*/ /*Scope*/ 18, /*->4408*/
+/* 4390*/ OPC_CheckPredicate, 6, // Predicate_extload
+/* 4392*/ OPC_CheckPredicate, 10, // Predicate_extloadi32
+/* 4394*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4396*/ OPC_EmitMergeInputChains1_0,
+/* 4397*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4400*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> - Complexity = 4
+ // Dst: (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4408*/ /*Scope*/ 18, /*->4427*/
+/* 4409*/ OPC_CheckPredicate, 9, // Predicate_zextload
+/* 4411*/ OPC_CheckPredicate, 10, // Predicate_zextloadi32
+/* 4413*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4415*/ OPC_EmitMergeInputChains1_0,
+/* 4416*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4419*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LWU), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> - Complexity = 4
+ // Dst: (LWU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4427*/ /*Scope*/ 16, /*->4444*/
+/* 4428*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 4430*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4432*/ OPC_EmitMergeInputChains1_0,
+/* 4433*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4436*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4444*/ 0, /*End of Scope*/
+/* 4445*/ 0, /*End of Scope*/
+/* 4446*/ /*Scope*/ 126|128,2/*382*/, /*->4830*/
+/* 4448*/ OPC_MoveChild1,
+/* 4449*/ OPC_SwitchOpcode /*2 cases */, 15|128,1/*143*/, TARGET_VAL(ISD::OR),// ->4597
+/* 4454*/ OPC_RecordChild0, // #1 = $rs1
+/* 4455*/ OPC_RecordChild1, // #2 = $imm12
+/* 4456*/ OPC_MoveChild1,
+/* 4457*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 4460*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 4462*/ OPC_MoveParent,
+/* 4463*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 4465*/ OPC_SwitchType /*2 cases */, 83, MVT::i32,// ->4551
+/* 4468*/ OPC_MoveParent,
+/* 4469*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 4471*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 4473*/ OPC_SwitchType /*2 cases */, 36, MVT::f32,// ->4512
+/* 4476*/ OPC_Scope, 16, /*->4494*/ // 2 children in Scope
+/* 4478*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4480*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4483*/ OPC_EmitMergeInputChains1_0,
+/* 4484*/ OPC_EmitConvertToTarget, 2,
+/* 4486*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4494*/ /*Scope*/ 16, /*->4511*/
+/* 4495*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 4497*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4500*/ OPC_EmitMergeInputChains1_0,
+/* 4501*/ OPC_EmitConvertToTarget, 2,
+/* 4503*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4511*/ 0, /*End of Scope*/
+/* 4512*/ /*SwitchType*/ 36, MVT::f64,// ->4550
+/* 4514*/ OPC_Scope, 16, /*->4532*/ // 2 children in Scope
+/* 4516*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4518*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4521*/ OPC_EmitMergeInputChains1_0,
+/* 4522*/ OPC_EmitConvertToTarget, 2,
+/* 4524*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f64] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4532*/ /*Scope*/ 16, /*->4549*/
+/* 4533*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 4535*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4538*/ OPC_EmitMergeInputChains1_0,
+/* 4539*/ OPC_EmitConvertToTarget, 2,
+/* 4541*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f64] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4549*/ 0, /*End of Scope*/
+/* 4550*/ 0, // EndSwitchType
+/* 4551*/ /*SwitchType*/ 43, MVT::i64,// ->4596
+/* 4553*/ OPC_MoveParent,
+/* 4554*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 4556*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 4558*/ OPC_SwitchType /*2 cases */, 16, MVT::f32,// ->4577
+/* 4561*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4563*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4566*/ OPC_EmitMergeInputChains1_0,
+/* 4567*/ OPC_EmitConvertToTarget, 2,
+/* 4569*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f32] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 4577*/ /*SwitchType*/ 16, MVT::f64,// ->4595
+/* 4579*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4581*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4584*/ OPC_EmitMergeInputChains1_0,
+/* 4585*/ OPC_EmitConvertToTarget, 2,
+/* 4587*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 18
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 4595*/ 0, // EndSwitchType
+/* 4596*/ 0, // EndSwitchType
+/* 4597*/ /*SwitchOpcode*/ 100|128,1/*228*/, TARGET_VAL(ISD::ADD),// ->4829
+/* 4601*/ OPC_RecordChild0, // #1 = $rs1
+/* 4602*/ OPC_RecordChild1, // #2 = $imm12
+/* 4603*/ OPC_MoveChild1,
+/* 4604*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 4607*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 4609*/ OPC_MoveParent,
+/* 4610*/ OPC_SwitchType /*2 cases */, 11|128,1/*139*/, MVT::i32,// ->4753
+/* 4614*/ OPC_MoveParent,
+/* 4615*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 4617*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 4619*/ OPC_SwitchType /*2 cases */, 64, MVT::f32,// ->4686
+/* 4622*/ OPC_Scope, 16, /*->4640*/ // 4 children in Scope
+/* 4624*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4626*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4629*/ OPC_EmitMergeInputChains1_0,
+/* 4630*/ OPC_EmitConvertToTarget, 2,
+/* 4632*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4640*/ /*Scope*/ 16, /*->4657*/
+/* 4641*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 4643*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4646*/ OPC_EmitMergeInputChains1_0,
+/* 4647*/ OPC_EmitConvertToTarget, 2,
+/* 4649*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4657*/ /*Scope*/ 13, /*->4671*/
+/* 4658*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4660*/ OPC_EmitMergeInputChains1_0,
+/* 4661*/ OPC_EmitConvertToTarget, 2,
+/* 4663*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[f32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4671*/ /*Scope*/ 13, /*->4685*/
+/* 4672*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 4674*/ OPC_EmitMergeInputChains1_0,
+/* 4675*/ OPC_EmitConvertToTarget, 2,
+/* 4677*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[f32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4685*/ 0, /*End of Scope*/
+/* 4686*/ /*SwitchType*/ 64, MVT::f64,// ->4752
+/* 4688*/ OPC_Scope, 16, /*->4706*/ // 4 children in Scope
+/* 4690*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4692*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4695*/ OPC_EmitMergeInputChains1_0,
+/* 4696*/ OPC_EmitConvertToTarget, 2,
+/* 4698*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f64] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4706*/ /*Scope*/ 16, /*->4723*/
+/* 4707*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 4709*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4712*/ OPC_EmitMergeInputChains1_0,
+/* 4713*/ OPC_EmitConvertToTarget, 2,
+/* 4715*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f64] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4723*/ /*Scope*/ 13, /*->4737*/
+/* 4724*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4726*/ OPC_EmitMergeInputChains1_0,
+/* 4727*/ OPC_EmitConvertToTarget, 2,
+/* 4729*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[f64] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4737*/ /*Scope*/ 13, /*->4751*/
+/* 4738*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 4740*/ OPC_EmitMergeInputChains1_0,
+/* 4741*/ OPC_EmitConvertToTarget, 2,
+/* 4743*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[f64] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 4751*/ 0, /*End of Scope*/
+/* 4752*/ 0, // EndSwitchType
+/* 4753*/ /*SwitchType*/ 73, MVT::i64,// ->4828
+/* 4755*/ OPC_MoveParent,
+/* 4756*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 4758*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 4760*/ OPC_SwitchType /*2 cases */, 31, MVT::f32,// ->4794
+/* 4763*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4765*/ OPC_Scope, 14, /*->4781*/ // 2 children in Scope
+/* 4767*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4770*/ OPC_EmitMergeInputChains1_0,
+/* 4771*/ OPC_EmitConvertToTarget, 2,
+/* 4773*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f32] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 4781*/ /*Scope*/ 11, /*->4793*/
+/* 4782*/ OPC_EmitMergeInputChains1_0,
+/* 4783*/ OPC_EmitConvertToTarget, 2,
+/* 4785*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[f32] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (FLW:{ *:[f32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 4793*/ 0, /*End of Scope*/
+/* 4794*/ /*SwitchType*/ 31, MVT::f64,// ->4827
+/* 4796*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4798*/ OPC_Scope, 14, /*->4814*/ // 2 children in Scope
+/* 4800*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 4803*/ OPC_EmitMergeInputChains1_0,
+/* 4804*/ OPC_EmitConvertToTarget, 2,
+/* 4806*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 3, 4,
+ // Src: (ld:{ *:[f64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 17
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 4814*/ /*Scope*/ 11, /*->4826*/
+/* 4815*/ OPC_EmitMergeInputChains1_0,
+/* 4816*/ OPC_EmitConvertToTarget, 2,
+/* 4818*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 1, 3,
+ // Src: (ld:{ *:[f64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 11
+ // Dst: (FLD:{ *:[f64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 4826*/ 0, /*End of Scope*/
+/* 4827*/ 0, // EndSwitchType
+/* 4828*/ 0, // EndSwitchType
+/* 4829*/ 0, // EndSwitchOpcode
+/* 4830*/ /*Scope*/ 99|128,1/*227*/, /*->5059*/
+/* 4832*/ OPC_RecordChild1, // #1 = $rs1
+/* 4833*/ OPC_CheckPredicate, 3, // Predicate_unindexedload
+/* 4835*/ OPC_CheckPredicate, 8, // Predicate_load
+/* 4837*/ OPC_SwitchType /*2 cases */, 108, MVT::f32,// ->4948
+/* 4840*/ OPC_Scope, 17, /*->4859*/ // 5 children in Scope
+/* 4842*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4844*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 4847*/ OPC_EmitMergeInputChains1_0,
+/* 4848*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4851*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4859*/ /*Scope*/ 17, /*->4877*/
+/* 4860*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4862*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 4865*/ OPC_EmitMergeInputChains1_0,
+/* 4866*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4869*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4877*/ /*Scope*/ 17, /*->4895*/
+/* 4878*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 4880*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 4883*/ OPC_EmitMergeInputChains1_0,
+/* 4884*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4887*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (FLW:{ *:[f32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4895*/ /*Scope*/ 34, /*->4930*/
+/* 4896*/ OPC_CheckChild1Type, MVT::i32,
+/* 4898*/ OPC_Scope, 14, /*->4914*/ // 2 children in Scope
+/* 4900*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4902*/ OPC_EmitMergeInputChains1_0,
+/* 4903*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4906*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4914*/ /*Scope*/ 14, /*->4929*/
+/* 4915*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 4917*/ OPC_EmitMergeInputChains1_0,
+/* 4918*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4921*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4929*/ 0, /*End of Scope*/
+/* 4930*/ /*Scope*/ 16, /*->4947*/
+/* 4931*/ OPC_CheckChild1Type, MVT::i64,
+/* 4933*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4935*/ OPC_EmitMergeInputChains1_0,
+/* 4936*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4939*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f32, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (FLW:{ *:[f32] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4947*/ 0, /*End of Scope*/
+/* 4948*/ /*SwitchType*/ 108, MVT::f64,// ->5058
+/* 4950*/ OPC_Scope, 17, /*->4969*/ // 5 children in Scope
+/* 4952*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 4954*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 4957*/ OPC_EmitMergeInputChains1_0,
+/* 4958*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4961*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 4969*/ /*Scope*/ 17, /*->4987*/
+/* 4970*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 4972*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 4975*/ OPC_EmitMergeInputChains1_0,
+/* 4976*/ OPC_EmitInteger, MVT::i64, 0,
+/* 4979*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 4987*/ /*Scope*/ 17, /*->5005*/
+/* 4988*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 4990*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 4993*/ OPC_EmitMergeInputChains1_0,
+/* 4994*/ OPC_EmitInteger, MVT::i32, 0,
+/* 4997*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 2, 3,
+ // Src: (ld:{ *:[f64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 10
+ // Dst: (FLD:{ *:[f64] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5005*/ /*Scope*/ 34, /*->5040*/
+/* 5006*/ OPC_CheckChild1Type, MVT::i32,
+/* 5008*/ OPC_Scope, 14, /*->5024*/ // 2 children in Scope
+/* 5010*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5012*/ OPC_EmitMergeInputChains1_0,
+/* 5013*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5016*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5024*/ /*Scope*/ 14, /*->5039*/
+/* 5025*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 5027*/ OPC_EmitMergeInputChains1_0,
+/* 5028*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5031*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5039*/ 0, /*End of Scope*/
+/* 5040*/ /*Scope*/ 16, /*->5057*/
+/* 5041*/ OPC_CheckChild1Type, MVT::i64,
+/* 5043*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 5045*/ OPC_EmitMergeInputChains1_0,
+/* 5046*/ OPC_EmitInteger, MVT::i64, 0,
+/* 5049*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::f64, 2/*#Ops*/, 1, 2,
+ // Src: (ld:{ *:[f64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
+ // Dst: (FLD:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 5057*/ 0, /*End of Scope*/
+/* 5058*/ 0, // EndSwitchType
+/* 5059*/ 0, /*End of Scope*/
+/* 5060*/ /*SwitchOpcode*/ 59|128,17/*2235*/, TARGET_VAL(ISD::STORE),// ->7299
+/* 5064*/ OPC_RecordMemRef,
+/* 5065*/ OPC_RecordNode, // #0 = 'st' chained node
+/* 5066*/ OPC_RecordChild1, // #1 = $rs2
+/* 5067*/ OPC_Scope, 118|128,7/*1014*/, /*->6084*/ // 4 children in Scope
+/* 5070*/ OPC_CheckChild1Type, MVT::i32,
+/* 5072*/ OPC_Scope, 97|128,4/*609*/, /*->5684*/ // 2 children in Scope
+/* 5075*/ OPC_MoveChild2,
+/* 5076*/ OPC_SwitchOpcode /*2 cases */, 88|128,1/*216*/, TARGET_VAL(ISD::OR),// ->5297
+/* 5081*/ OPC_RecordChild0, // #2 = $rs1
+/* 5082*/ OPC_RecordChild1, // #3 = $imm12
+/* 5083*/ OPC_MoveChild1,
+/* 5084*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5087*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 5089*/ OPC_MoveParent,
+/* 5090*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 5092*/ OPC_CheckType, MVT::i32,
+/* 5094*/ OPC_MoveParent,
+/* 5095*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 5097*/ OPC_Scope, 78, /*->5177*/ // 4 children in Scope
+/* 5099*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5101*/ OPC_Scope, 36, /*->5139*/ // 2 children in Scope
+/* 5103*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 5105*/ OPC_Scope, 16, /*->5123*/ // 2 children in Scope
+/* 5107*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5109*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5112*/ OPC_EmitMergeInputChains1_0,
+/* 5113*/ OPC_EmitConvertToTarget, 3,
+/* 5115*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 18
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5123*/ /*Scope*/ 14, /*->5138*/
+/* 5124*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5127*/ OPC_EmitMergeInputChains1_0,
+/* 5128*/ OPC_EmitConvertToTarget, 3,
+/* 5130*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 18
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5138*/ 0, /*End of Scope*/
+/* 5139*/ /*Scope*/ 36, /*->5176*/
+/* 5140*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 5142*/ OPC_Scope, 16, /*->5160*/ // 2 children in Scope
+/* 5144*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5146*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5149*/ OPC_EmitMergeInputChains1_0,
+/* 5150*/ OPC_EmitConvertToTarget, 3,
+/* 5152*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 18
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5160*/ /*Scope*/ 14, /*->5175*/
+/* 5161*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5164*/ OPC_EmitMergeInputChains1_0,
+/* 5165*/ OPC_EmitConvertToTarget, 3,
+/* 5167*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 18
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5175*/ 0, /*End of Scope*/
+/* 5176*/ 0, /*End of Scope*/
+/* 5177*/ /*Scope*/ 38, /*->5216*/
+/* 5178*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5180*/ OPC_Scope, 16, /*->5198*/ // 2 children in Scope
+/* 5182*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5184*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5187*/ OPC_EmitMergeInputChains1_0,
+/* 5188*/ OPC_EmitConvertToTarget, 3,
+/* 5190*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5198*/ /*Scope*/ 16, /*->5215*/
+/* 5199*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 5201*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5204*/ OPC_EmitMergeInputChains1_0,
+/* 5205*/ OPC_EmitConvertToTarget, 3,
+/* 5207*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5215*/ 0, /*End of Scope*/
+/* 5216*/ /*Scope*/ 40, /*->5257*/
+/* 5217*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5219*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 5221*/ OPC_Scope, 16, /*->5239*/ // 2 children in Scope
+/* 5223*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5225*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5228*/ OPC_EmitMergeInputChains1_0,
+/* 5229*/ OPC_EmitConvertToTarget, 3,
+/* 5231*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5239*/ /*Scope*/ 16, /*->5256*/
+/* 5240*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 5242*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5245*/ OPC_EmitMergeInputChains1_0,
+/* 5246*/ OPC_EmitConvertToTarget, 3,
+/* 5248*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5256*/ 0, /*End of Scope*/
+/* 5257*/ /*Scope*/ 38, /*->5296*/
+/* 5258*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5260*/ OPC_Scope, 16, /*->5278*/ // 2 children in Scope
+/* 5262*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5264*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5267*/ OPC_EmitMergeInputChains1_0,
+/* 5268*/ OPC_EmitConvertToTarget, 3,
+/* 5270*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5278*/ /*Scope*/ 16, /*->5295*/
+/* 5279*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 5281*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5284*/ OPC_EmitMergeInputChains1_0,
+/* 5285*/ OPC_EmitConvertToTarget, 3,
+/* 5287*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5295*/ 0, /*End of Scope*/
+/* 5296*/ 0, /*End of Scope*/
+/* 5297*/ /*SwitchOpcode*/ 126|128,2/*382*/, TARGET_VAL(ISD::ADD),// ->5683
+/* 5301*/ OPC_RecordChild0, // #2 = $rs1
+/* 5302*/ OPC_RecordChild1, // #3 = $imm12
+/* 5303*/ OPC_MoveChild1,
+/* 5304*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 5307*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 5309*/ OPC_MoveParent,
+/* 5310*/ OPC_CheckType, MVT::i32,
+/* 5312*/ OPC_MoveParent,
+/* 5313*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 5315*/ OPC_Scope, 78, /*->5395*/ // 8 children in Scope
+/* 5317*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5319*/ OPC_Scope, 36, /*->5357*/ // 2 children in Scope
+/* 5321*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 5323*/ OPC_Scope, 16, /*->5341*/ // 2 children in Scope
+/* 5325*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5327*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5330*/ OPC_EmitMergeInputChains1_0,
+/* 5331*/ OPC_EmitConvertToTarget, 3,
+/* 5333*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 17
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5341*/ /*Scope*/ 14, /*->5356*/
+/* 5342*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5345*/ OPC_EmitMergeInputChains1_0,
+/* 5346*/ OPC_EmitConvertToTarget, 3,
+/* 5348*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 17
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5356*/ 0, /*End of Scope*/
+/* 5357*/ /*Scope*/ 36, /*->5394*/
+/* 5358*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 5360*/ OPC_Scope, 16, /*->5378*/ // 2 children in Scope
+/* 5362*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5364*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5367*/ OPC_EmitMergeInputChains1_0,
+/* 5368*/ OPC_EmitConvertToTarget, 3,
+/* 5370*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 17
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5378*/ /*Scope*/ 14, /*->5393*/
+/* 5379*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5382*/ OPC_EmitMergeInputChains1_0,
+/* 5383*/ OPC_EmitConvertToTarget, 3,
+/* 5385*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 17
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5393*/ 0, /*End of Scope*/
+/* 5394*/ 0, /*End of Scope*/
+/* 5395*/ /*Scope*/ 38, /*->5434*/
+/* 5396*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5398*/ OPC_Scope, 16, /*->5416*/ // 2 children in Scope
+/* 5400*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5402*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5405*/ OPC_EmitMergeInputChains1_0,
+/* 5406*/ OPC_EmitConvertToTarget, 3,
+/* 5408*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5416*/ /*Scope*/ 16, /*->5433*/
+/* 5417*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 5419*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5422*/ OPC_EmitMergeInputChains1_0,
+/* 5423*/ OPC_EmitConvertToTarget, 3,
+/* 5425*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5433*/ 0, /*End of Scope*/
+/* 5434*/ /*Scope*/ 40, /*->5475*/
+/* 5435*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5437*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 5439*/ OPC_Scope, 16, /*->5457*/ // 2 children in Scope
+/* 5441*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5443*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5446*/ OPC_EmitMergeInputChains1_0,
+/* 5447*/ OPC_EmitConvertToTarget, 3,
+/* 5449*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5457*/ /*Scope*/ 16, /*->5474*/
+/* 5458*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 5460*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5463*/ OPC_EmitMergeInputChains1_0,
+/* 5464*/ OPC_EmitConvertToTarget, 3,
+/* 5466*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5474*/ 0, /*End of Scope*/
+/* 5475*/ /*Scope*/ 38, /*->5514*/
+/* 5476*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5478*/ OPC_Scope, 16, /*->5496*/ // 2 children in Scope
+/* 5480*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5482*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5485*/ OPC_EmitMergeInputChains1_0,
+/* 5486*/ OPC_EmitConvertToTarget, 3,
+/* 5488*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5496*/ /*Scope*/ 16, /*->5513*/
+/* 5497*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 5499*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 5502*/ OPC_EmitMergeInputChains1_0,
+/* 5503*/ OPC_EmitConvertToTarget, 3,
+/* 5505*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5513*/ 0, /*End of Scope*/
+/* 5514*/ /*Scope*/ 66, /*->5581*/
+/* 5515*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5517*/ OPC_Scope, 30, /*->5549*/ // 2 children in Scope
+/* 5519*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 5521*/ OPC_Scope, 13, /*->5536*/ // 2 children in Scope
+/* 5523*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5525*/ OPC_EmitMergeInputChains1_0,
+/* 5526*/ OPC_EmitConvertToTarget, 3,
+/* 5528*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 11
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5536*/ /*Scope*/ 11, /*->5548*/
+/* 5537*/ OPC_EmitMergeInputChains1_0,
+/* 5538*/ OPC_EmitConvertToTarget, 3,
+/* 5540*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 11
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5548*/ 0, /*End of Scope*/
+/* 5549*/ /*Scope*/ 30, /*->5580*/
+/* 5550*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 5552*/ OPC_Scope, 13, /*->5567*/ // 2 children in Scope
+/* 5554*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5556*/ OPC_EmitMergeInputChains1_0,
+/* 5557*/ OPC_EmitConvertToTarget, 3,
+/* 5559*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 11
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5567*/ /*Scope*/ 11, /*->5579*/
+/* 5568*/ OPC_EmitMergeInputChains1_0,
+/* 5569*/ OPC_EmitConvertToTarget, 3,
+/* 5571*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 11
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5579*/ 0, /*End of Scope*/
+/* 5580*/ 0, /*End of Scope*/
+/* 5581*/ /*Scope*/ 32, /*->5614*/
+/* 5582*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5584*/ OPC_Scope, 13, /*->5599*/ // 2 children in Scope
+/* 5586*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5588*/ OPC_EmitMergeInputChains1_0,
+/* 5589*/ OPC_EmitConvertToTarget, 3,
+/* 5591*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5599*/ /*Scope*/ 13, /*->5613*/
+/* 5600*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 5602*/ OPC_EmitMergeInputChains1_0,
+/* 5603*/ OPC_EmitConvertToTarget, 3,
+/* 5605*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5613*/ 0, /*End of Scope*/
+/* 5614*/ /*Scope*/ 34, /*->5649*/
+/* 5615*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5617*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 5619*/ OPC_Scope, 13, /*->5634*/ // 2 children in Scope
+/* 5621*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5623*/ OPC_EmitMergeInputChains1_0,
+/* 5624*/ OPC_EmitConvertToTarget, 3,
+/* 5626*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5634*/ /*Scope*/ 13, /*->5648*/
+/* 5635*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 5637*/ OPC_EmitMergeInputChains1_0,
+/* 5638*/ OPC_EmitConvertToTarget, 3,
+/* 5640*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5648*/ 0, /*End of Scope*/
+/* 5649*/ /*Scope*/ 32, /*->5682*/
+/* 5650*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5652*/ OPC_Scope, 13, /*->5667*/ // 2 children in Scope
+/* 5654*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5656*/ OPC_EmitMergeInputChains1_0,
+/* 5657*/ OPC_EmitConvertToTarget, 3,
+/* 5659*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5667*/ /*Scope*/ 13, /*->5681*/
+/* 5668*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 5670*/ OPC_EmitMergeInputChains1_0,
+/* 5671*/ OPC_EmitConvertToTarget, 3,
+/* 5673*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 5681*/ 0, /*End of Scope*/
+/* 5682*/ 0, /*End of Scope*/
+/* 5683*/ 0, // EndSwitchOpcode
+/* 5684*/ /*Scope*/ 13|128,3/*397*/, /*->6083*/
+/* 5686*/ OPC_RecordChild2, // #2 = $rs1
+/* 5687*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 5689*/ OPC_Scope, 82, /*->5773*/ // 5 children in Scope
+/* 5691*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5693*/ OPC_Scope, 38, /*->5733*/ // 2 children in Scope
+/* 5695*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 5697*/ OPC_Scope, 17, /*->5716*/ // 2 children in Scope
+/* 5699*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5701*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5704*/ OPC_EmitMergeInputChains1_0,
+/* 5705*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5708*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 10
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5716*/ /*Scope*/ 15, /*->5732*/
+/* 5717*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5720*/ OPC_EmitMergeInputChains1_0,
+/* 5721*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5724*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 10
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5732*/ 0, /*End of Scope*/
+/* 5733*/ /*Scope*/ 38, /*->5772*/
+/* 5734*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 5736*/ OPC_Scope, 17, /*->5755*/ // 2 children in Scope
+/* 5738*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5740*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5743*/ OPC_EmitMergeInputChains1_0,
+/* 5744*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5747*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 10
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5755*/ /*Scope*/ 15, /*->5771*/
+/* 5756*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5759*/ OPC_EmitMergeInputChains1_0,
+/* 5760*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5763*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 10
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5771*/ 0, /*End of Scope*/
+/* 5772*/ 0, /*End of Scope*/
+/* 5773*/ /*Scope*/ 40, /*->5814*/
+/* 5774*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5776*/ OPC_Scope, 17, /*->5795*/ // 2 children in Scope
+/* 5778*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5780*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5783*/ OPC_EmitMergeInputChains1_0,
+/* 5784*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5787*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5795*/ /*Scope*/ 17, /*->5813*/
+/* 5796*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 5798*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5801*/ OPC_EmitMergeInputChains1_0,
+/* 5802*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5805*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5813*/ 0, /*End of Scope*/
+/* 5814*/ /*Scope*/ 42, /*->5857*/
+/* 5815*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5817*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 5819*/ OPC_Scope, 17, /*->5838*/ // 2 children in Scope
+/* 5821*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5823*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5826*/ OPC_EmitMergeInputChains1_0,
+/* 5827*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5830*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5838*/ /*Scope*/ 17, /*->5856*/
+/* 5839*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 5841*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5844*/ OPC_EmitMergeInputChains1_0,
+/* 5845*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5848*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5856*/ 0, /*End of Scope*/
+/* 5857*/ /*Scope*/ 40, /*->5898*/
+/* 5858*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5860*/ OPC_Scope, 17, /*->5879*/ // 2 children in Scope
+/* 5862*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5864*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5867*/ OPC_EmitMergeInputChains1_0,
+/* 5868*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5871*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5879*/ /*Scope*/ 17, /*->5897*/
+/* 5880*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 5882*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 5885*/ OPC_EmitMergeInputChains1_0,
+/* 5886*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5889*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5897*/ 0, /*End of Scope*/
+/* 5898*/ /*Scope*/ 54|128,1/*182*/, /*->6082*/
+/* 5900*/ OPC_CheckChild2Type, MVT::i32,
+/* 5902*/ OPC_Scope, 70, /*->5974*/ // 4 children in Scope
+/* 5904*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 5906*/ OPC_Scope, 32, /*->5940*/ // 2 children in Scope
+/* 5908*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 5910*/ OPC_Scope, 14, /*->5926*/ // 2 children in Scope
+/* 5912*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5914*/ OPC_EmitMergeInputChains1_0,
+/* 5915*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5918*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 4
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5926*/ /*Scope*/ 12, /*->5939*/
+/* 5927*/ OPC_EmitMergeInputChains1_0,
+/* 5928*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5931*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 4
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5939*/ 0, /*End of Scope*/
+/* 5940*/ /*Scope*/ 32, /*->5973*/
+/* 5941*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 5943*/ OPC_Scope, 14, /*->5959*/ // 2 children in Scope
+/* 5945*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5947*/ OPC_EmitMergeInputChains1_0,
+/* 5948*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5951*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 4
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5959*/ /*Scope*/ 12, /*->5972*/
+/* 5960*/ OPC_EmitMergeInputChains1_0,
+/* 5961*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5964*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 4
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5972*/ 0, /*End of Scope*/
+/* 5973*/ 0, /*End of Scope*/
+/* 5974*/ /*Scope*/ 34, /*->6009*/
+/* 5975*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 5977*/ OPC_Scope, 14, /*->5993*/ // 2 children in Scope
+/* 5979*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 5981*/ OPC_EmitMergeInputChains1_0,
+/* 5982*/ OPC_EmitInteger, MVT::i32, 0,
+/* 5985*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 5993*/ /*Scope*/ 14, /*->6008*/
+/* 5994*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 5996*/ OPC_EmitMergeInputChains1_0,
+/* 5997*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6000*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6008*/ 0, /*End of Scope*/
+/* 6009*/ /*Scope*/ 36, /*->6046*/
+/* 6010*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6012*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 6014*/ OPC_Scope, 14, /*->6030*/ // 2 children in Scope
+/* 6016*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 6018*/ OPC_EmitMergeInputChains1_0,
+/* 6019*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6022*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6030*/ /*Scope*/ 14, /*->6045*/
+/* 6031*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 6033*/ OPC_EmitMergeInputChains1_0,
+/* 6034*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6037*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6045*/ 0, /*End of Scope*/
+/* 6046*/ /*Scope*/ 34, /*->6081*/
+/* 6047*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6049*/ OPC_Scope, 14, /*->6065*/ // 2 children in Scope
+/* 6051*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 6053*/ OPC_EmitMergeInputChains1_0,
+/* 6054*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6057*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6065*/ /*Scope*/ 14, /*->6080*/
+/* 6066*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 6068*/ OPC_EmitMergeInputChains1_0,
+/* 6069*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6072*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6080*/ 0, /*End of Scope*/
+/* 6081*/ 0, /*End of Scope*/
+/* 6082*/ 0, /*End of Scope*/
+/* 6083*/ 0, /*End of Scope*/
+/* 6084*/ /*Scope*/ 40|128,4/*552*/, /*->6638*/
+/* 6086*/ OPC_CheckChild1Type, MVT::i64,
+/* 6088*/ OPC_Scope, 79|128,2/*335*/, /*->6426*/ // 2 children in Scope
+/* 6091*/ OPC_MoveChild2,
+/* 6092*/ OPC_SwitchOpcode /*2 cases */, 120, TARGET_VAL(ISD::OR),// ->6216
+/* 6096*/ OPC_RecordChild0, // #2 = $rs1
+/* 6097*/ OPC_RecordChild1, // #3 = $imm12
+/* 6098*/ OPC_MoveChild1,
+/* 6099*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 6102*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 6104*/ OPC_MoveParent,
+/* 6105*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 6107*/ OPC_CheckType, MVT::i64,
+/* 6109*/ OPC_MoveParent,
+/* 6110*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6112*/ OPC_Scope, 42, /*->6156*/ // 4 children in Scope
+/* 6114*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6116*/ OPC_Scope, 18, /*->6136*/ // 2 children in Scope
+/* 6118*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 6120*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6122*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6125*/ OPC_EmitMergeInputChains1_0,
+/* 6126*/ OPC_EmitConvertToTarget, 3,
+/* 6128*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 18
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6136*/ /*Scope*/ 18, /*->6155*/
+/* 6137*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 6139*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6141*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6144*/ OPC_EmitMergeInputChains1_0,
+/* 6145*/ OPC_EmitConvertToTarget, 3,
+/* 6147*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 18
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6155*/ 0, /*End of Scope*/
+/* 6156*/ /*Scope*/ 18, /*->6175*/
+/* 6157*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6159*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6161*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6164*/ OPC_EmitMergeInputChains1_0,
+/* 6165*/ OPC_EmitConvertToTarget, 3,
+/* 6167*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6175*/ /*Scope*/ 20, /*->6196*/
+/* 6176*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6178*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 6180*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6182*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6185*/ OPC_EmitMergeInputChains1_0,
+/* 6186*/ OPC_EmitConvertToTarget, 3,
+/* 6188*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6196*/ /*Scope*/ 18, /*->6215*/
+/* 6197*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6199*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6201*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6204*/ OPC_EmitMergeInputChains1_0,
+/* 6205*/ OPC_EmitConvertToTarget, 3,
+/* 6207*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6215*/ 0, /*End of Scope*/
+/* 6216*/ /*SwitchOpcode*/ 77|128,1/*205*/, TARGET_VAL(ISD::ADD),// ->6425
+/* 6220*/ OPC_RecordChild0, // #2 = $rs1
+/* 6221*/ OPC_RecordChild1, // #3 = $imm12
+/* 6222*/ OPC_MoveChild1,
+/* 6223*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 6226*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 6228*/ OPC_MoveParent,
+/* 6229*/ OPC_CheckType, MVT::i64,
+/* 6231*/ OPC_MoveParent,
+/* 6232*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6234*/ OPC_Scope, 42, /*->6278*/ // 8 children in Scope
+/* 6236*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6238*/ OPC_Scope, 18, /*->6258*/ // 2 children in Scope
+/* 6240*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 6242*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6244*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6247*/ OPC_EmitMergeInputChains1_0,
+/* 6248*/ OPC_EmitConvertToTarget, 3,
+/* 6250*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 17
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6258*/ /*Scope*/ 18, /*->6277*/
+/* 6259*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 6261*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6263*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6266*/ OPC_EmitMergeInputChains1_0,
+/* 6267*/ OPC_EmitConvertToTarget, 3,
+/* 6269*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 17
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6277*/ 0, /*End of Scope*/
+/* 6278*/ /*Scope*/ 18, /*->6297*/
+/* 6279*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6281*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6283*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6286*/ OPC_EmitMergeInputChains1_0,
+/* 6287*/ OPC_EmitConvertToTarget, 3,
+/* 6289*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6297*/ /*Scope*/ 20, /*->6318*/
+/* 6298*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6300*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 6302*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6304*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6307*/ OPC_EmitMergeInputChains1_0,
+/* 6308*/ OPC_EmitConvertToTarget, 3,
+/* 6310*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6318*/ /*Scope*/ 18, /*->6337*/
+/* 6319*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6321*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 6323*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6326*/ OPC_EmitMergeInputChains1_0,
+/* 6327*/ OPC_EmitConvertToTarget, 3,
+/* 6329*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6337*/ /*Scope*/ 36, /*->6374*/
+/* 6338*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6340*/ OPC_Scope, 15, /*->6357*/ // 2 children in Scope
+/* 6342*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 6344*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6346*/ OPC_EmitMergeInputChains1_0,
+/* 6347*/ OPC_EmitConvertToTarget, 3,
+/* 6349*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 11
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6357*/ /*Scope*/ 15, /*->6373*/
+/* 6358*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 6360*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6362*/ OPC_EmitMergeInputChains1_0,
+/* 6363*/ OPC_EmitConvertToTarget, 3,
+/* 6365*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 11
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6373*/ 0, /*End of Scope*/
+/* 6374*/ /*Scope*/ 15, /*->6390*/
+/* 6375*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6377*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6379*/ OPC_EmitMergeInputChains1_0,
+/* 6380*/ OPC_EmitConvertToTarget, 3,
+/* 6382*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6390*/ /*Scope*/ 17, /*->6408*/
+/* 6391*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6393*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 6395*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6397*/ OPC_EmitMergeInputChains1_0,
+/* 6398*/ OPC_EmitConvertToTarget, 3,
+/* 6400*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6408*/ /*Scope*/ 15, /*->6424*/
+/* 6409*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6411*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6413*/ OPC_EmitMergeInputChains1_0,
+/* 6414*/ OPC_EmitConvertToTarget, 3,
+/* 6416*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6424*/ 0, /*End of Scope*/
+/* 6425*/ 0, // EndSwitchOpcode
+/* 6426*/ /*Scope*/ 81|128,1/*209*/, /*->6637*/
+/* 6428*/ OPC_RecordChild2, // #2 = $rs1
+/* 6429*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6431*/ OPC_Scope, 44, /*->6477*/ // 5 children in Scope
+/* 6433*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6435*/ OPC_Scope, 19, /*->6456*/ // 2 children in Scope
+/* 6437*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 6439*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6441*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 6444*/ OPC_EmitMergeInputChains1_0,
+/* 6445*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6448*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 10
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6456*/ /*Scope*/ 19, /*->6476*/
+/* 6457*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 6459*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6461*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 6464*/ OPC_EmitMergeInputChains1_0,
+/* 6465*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6468*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 10
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6476*/ 0, /*End of Scope*/
+/* 6477*/ /*Scope*/ 19, /*->6497*/
+/* 6478*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6480*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6482*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 6485*/ OPC_EmitMergeInputChains1_0,
+/* 6486*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6489*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6497*/ /*Scope*/ 21, /*->6519*/
+/* 6498*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6500*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 6502*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6504*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 6507*/ OPC_EmitMergeInputChains1_0,
+/* 6508*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6511*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6519*/ /*Scope*/ 19, /*->6539*/
+/* 6520*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6522*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6524*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 6527*/ OPC_EmitMergeInputChains1_0,
+/* 6528*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6531*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6539*/ /*Scope*/ 96, /*->6636*/
+/* 6540*/ OPC_CheckChild2Type, MVT::i64,
+/* 6542*/ OPC_Scope, 38, /*->6582*/ // 4 children in Scope
+/* 6544*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6546*/ OPC_Scope, 16, /*->6564*/ // 2 children in Scope
+/* 6548*/ OPC_CheckPredicate, 5, // Predicate_truncstorei8
+/* 6550*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6552*/ OPC_EmitMergeInputChains1_0,
+/* 6553*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6556*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>> - Complexity = 4
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6564*/ /*Scope*/ 16, /*->6581*/
+/* 6565*/ OPC_CheckPredicate, 7, // Predicate_truncstorei16
+/* 6567*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6569*/ OPC_EmitMergeInputChains1_0,
+/* 6570*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6573*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>> - Complexity = 4
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6581*/ 0, /*End of Scope*/
+/* 6582*/ /*Scope*/ 16, /*->6599*/
+/* 6583*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6585*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6587*/ OPC_EmitMergeInputChains1_0,
+/* 6588*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6591*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6599*/ /*Scope*/ 18, /*->6618*/
+/* 6600*/ OPC_CheckPredicate, 12, // Predicate_truncstore
+/* 6602*/ OPC_CheckPredicate, 10, // Predicate_truncstorei32
+/* 6604*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6606*/ OPC_EmitMergeInputChains1_0,
+/* 6607*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6610*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6618*/ /*Scope*/ 16, /*->6635*/
+/* 6619*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6621*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6623*/ OPC_EmitMergeInputChains1_0,
+/* 6624*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6627*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6635*/ 0, /*End of Scope*/
+/* 6636*/ 0, /*End of Scope*/
+/* 6637*/ 0, /*End of Scope*/
+/* 6638*/ /*Scope*/ 72|128,2/*328*/, /*->6968*/
+/* 6640*/ OPC_CheckChild1Type, MVT::f32,
+/* 6642*/ OPC_Scope, 80|128,1/*208*/, /*->6853*/ // 2 children in Scope
+/* 6645*/ OPC_MoveChild2,
+/* 6646*/ OPC_SwitchOpcode /*2 cases */, 79, TARGET_VAL(ISD::OR),// ->6729
+/* 6650*/ OPC_RecordChild0, // #2 = $rs1
+/* 6651*/ OPC_RecordChild1, // #3 = $imm12
+/* 6652*/ OPC_MoveChild1,
+/* 6653*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 6656*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 6658*/ OPC_MoveParent,
+/* 6659*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 6661*/ OPC_SwitchType /*2 cases */, 41, MVT::i32,// ->6705
+/* 6664*/ OPC_MoveParent,
+/* 6665*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6667*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6669*/ OPC_Scope, 16, /*->6687*/ // 2 children in Scope
+/* 6671*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 6673*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6676*/ OPC_EmitMergeInputChains1_0,
+/* 6677*/ OPC_EmitConvertToTarget, 3,
+/* 6679*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 6687*/ /*Scope*/ 16, /*->6704*/
+/* 6688*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 6690*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6693*/ OPC_EmitMergeInputChains1_0,
+/* 6694*/ OPC_EmitConvertToTarget, 3,
+/* 6696*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 6704*/ 0, /*End of Scope*/
+/* 6705*/ /*SwitchType*/ 21, MVT::i64,// ->6728
+/* 6707*/ OPC_MoveParent,
+/* 6708*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6710*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6712*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6714*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6717*/ OPC_EmitMergeInputChains1_0,
+/* 6718*/ OPC_EmitConvertToTarget, 3,
+/* 6720*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6728*/ 0, // EndSwitchType
+/* 6729*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::ADD),// ->6852
+/* 6732*/ OPC_RecordChild0, // #2 = $rs1
+/* 6733*/ OPC_RecordChild1, // #3 = $imm12
+/* 6734*/ OPC_MoveChild1,
+/* 6735*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 6738*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 6740*/ OPC_MoveParent,
+/* 6741*/ OPC_SwitchType /*2 cases */, 69, MVT::i32,// ->6813
+/* 6744*/ OPC_MoveParent,
+/* 6745*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6747*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6749*/ OPC_Scope, 16, /*->6767*/ // 4 children in Scope
+/* 6751*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 6753*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6756*/ OPC_EmitMergeInputChains1_0,
+/* 6757*/ OPC_EmitConvertToTarget, 3,
+/* 6759*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 6767*/ /*Scope*/ 16, /*->6784*/
+/* 6768*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 6770*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6773*/ OPC_EmitMergeInputChains1_0,
+/* 6774*/ OPC_EmitConvertToTarget, 3,
+/* 6776*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 6784*/ /*Scope*/ 13, /*->6798*/
+/* 6785*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 6787*/ OPC_EmitMergeInputChains1_0,
+/* 6788*/ OPC_EmitConvertToTarget, 3,
+/* 6790*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 6798*/ /*Scope*/ 13, /*->6812*/
+/* 6799*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 6801*/ OPC_EmitMergeInputChains1_0,
+/* 6802*/ OPC_EmitConvertToTarget, 3,
+/* 6804*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 6812*/ 0, /*End of Scope*/
+/* 6813*/ /*SwitchType*/ 36, MVT::i64,// ->6851
+/* 6815*/ OPC_MoveParent,
+/* 6816*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6818*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6820*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 6822*/ OPC_Scope, 14, /*->6838*/ // 2 children in Scope
+/* 6824*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 6827*/ OPC_EmitMergeInputChains1_0,
+/* 6828*/ OPC_EmitConvertToTarget, 3,
+/* 6830*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6838*/ /*Scope*/ 11, /*->6850*/
+/* 6839*/ OPC_EmitMergeInputChains1_0,
+/* 6840*/ OPC_EmitConvertToTarget, 3,
+/* 6842*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 6850*/ 0, /*End of Scope*/
+/* 6851*/ 0, // EndSwitchType
+/* 6852*/ 0, // EndSwitchOpcode
+/* 6853*/ /*Scope*/ 113, /*->6967*/
+/* 6854*/ OPC_RecordChild2, // #2 = $rs1
+/* 6855*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6857*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6859*/ OPC_Scope, 17, /*->6878*/ // 5 children in Scope
+/* 6861*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 6863*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 6866*/ OPC_EmitMergeInputChains1_0,
+/* 6867*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6870*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6878*/ /*Scope*/ 17, /*->6896*/
+/* 6879*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6881*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 6884*/ OPC_EmitMergeInputChains1_0,
+/* 6885*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6888*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6896*/ /*Scope*/ 17, /*->6914*/
+/* 6897*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 6899*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 6902*/ OPC_EmitMergeInputChains1_0,
+/* 6903*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6906*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6914*/ /*Scope*/ 34, /*->6949*/
+/* 6915*/ OPC_CheckChild2Type, MVT::i32,
+/* 6917*/ OPC_Scope, 14, /*->6933*/ // 2 children in Scope
+/* 6919*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 6921*/ OPC_EmitMergeInputChains1_0,
+/* 6922*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6925*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6933*/ /*Scope*/ 14, /*->6948*/
+/* 6934*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 6936*/ OPC_EmitMergeInputChains1_0,
+/* 6937*/ OPC_EmitInteger, MVT::i32, 0,
+/* 6940*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 6948*/ 0, /*End of Scope*/
+/* 6949*/ /*Scope*/ 16, /*->6966*/
+/* 6950*/ OPC_CheckChild2Type, MVT::i64,
+/* 6952*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 6954*/ OPC_EmitMergeInputChains1_0,
+/* 6955*/ OPC_EmitInteger, MVT::i64, 0,
+/* 6958*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 6966*/ 0, /*End of Scope*/
+/* 6967*/ 0, /*End of Scope*/
+/* 6968*/ /*Scope*/ 72|128,2/*328*/, /*->7298*/
+/* 6970*/ OPC_CheckChild1Type, MVT::f64,
+/* 6972*/ OPC_Scope, 80|128,1/*208*/, /*->7183*/ // 2 children in Scope
+/* 6975*/ OPC_MoveChild2,
+/* 6976*/ OPC_SwitchOpcode /*2 cases */, 79, TARGET_VAL(ISD::OR),// ->7059
+/* 6980*/ OPC_RecordChild0, // #2 = $rs1
+/* 6981*/ OPC_RecordChild1, // #3 = $imm12
+/* 6982*/ OPC_MoveChild1,
+/* 6983*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 6986*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 6988*/ OPC_MoveParent,
+/* 6989*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 6991*/ OPC_SwitchType /*2 cases */, 41, MVT::i32,// ->7035
+/* 6994*/ OPC_MoveParent,
+/* 6995*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 6997*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 6999*/ OPC_Scope, 16, /*->7017*/ // 2 children in Scope
+/* 7001*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7003*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 7006*/ OPC_EmitMergeInputChains1_0,
+/* 7007*/ OPC_EmitConvertToTarget, 3,
+/* 7009*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7017*/ /*Scope*/ 16, /*->7034*/
+/* 7018*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 7020*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 7023*/ OPC_EmitMergeInputChains1_0,
+/* 7024*/ OPC_EmitConvertToTarget, 3,
+/* 7026*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7034*/ 0, /*End of Scope*/
+/* 7035*/ /*SwitchType*/ 21, MVT::i64,// ->7058
+/* 7037*/ OPC_MoveParent,
+/* 7038*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 7040*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 7042*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7044*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 7047*/ OPC_EmitMergeInputChains1_0,
+/* 7048*/ OPC_EmitConvertToTarget, 3,
+/* 7050*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 18
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7058*/ 0, // EndSwitchType
+/* 7059*/ /*SwitchOpcode*/ 120, TARGET_VAL(ISD::ADD),// ->7182
+/* 7062*/ OPC_RecordChild0, // #2 = $rs1
+/* 7063*/ OPC_RecordChild1, // #3 = $imm12
+/* 7064*/ OPC_MoveChild1,
+/* 7065*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 7068*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 7070*/ OPC_MoveParent,
+/* 7071*/ OPC_SwitchType /*2 cases */, 69, MVT::i32,// ->7143
+/* 7074*/ OPC_MoveParent,
+/* 7075*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 7077*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 7079*/ OPC_Scope, 16, /*->7097*/ // 4 children in Scope
+/* 7081*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7083*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 7086*/ OPC_EmitMergeInputChains1_0,
+/* 7087*/ OPC_EmitConvertToTarget, 3,
+/* 7089*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7097*/ /*Scope*/ 16, /*->7114*/
+/* 7098*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 7100*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 7103*/ OPC_EmitMergeInputChains1_0,
+/* 7104*/ OPC_EmitConvertToTarget, 3,
+/* 7106*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7114*/ /*Scope*/ 13, /*->7128*/
+/* 7115*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7117*/ OPC_EmitMergeInputChains1_0,
+/* 7118*/ OPC_EmitConvertToTarget, 3,
+/* 7120*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7128*/ /*Scope*/ 13, /*->7142*/
+/* 7129*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 7131*/ OPC_EmitMergeInputChains1_0,
+/* 7132*/ OPC_EmitConvertToTarget, 3,
+/* 7134*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7142*/ 0, /*End of Scope*/
+/* 7143*/ /*SwitchType*/ 36, MVT::i64,// ->7181
+/* 7145*/ OPC_MoveParent,
+/* 7146*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 7148*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 7150*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7152*/ OPC_Scope, 14, /*->7168*/ // 2 children in Scope
+/* 7154*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #4
+/* 7157*/ OPC_EmitMergeInputChains1_0,
+/* 7158*/ OPC_EmitConvertToTarget, 3,
+/* 7160*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 4, 5,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 17
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7168*/ /*Scope*/ 11, /*->7180*/
+/* 7169*/ OPC_EmitMergeInputChains1_0,
+/* 7170*/ OPC_EmitConvertToTarget, 3,
+/* 7172*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 4,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 11
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7180*/ 0, /*End of Scope*/
+/* 7181*/ 0, // EndSwitchType
+/* 7182*/ 0, // EndSwitchOpcode
+/* 7183*/ /*Scope*/ 113, /*->7297*/
+/* 7184*/ OPC_RecordChild2, // #2 = $rs1
+/* 7185*/ OPC_CheckPredicate, 11, // Predicate_unindexedstore
+/* 7187*/ OPC_CheckPredicate, 13, // Predicate_store
+/* 7189*/ OPC_Scope, 17, /*->7208*/ // 5 children in Scope
+/* 7191*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7193*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 7196*/ OPC_EmitMergeInputChains1_0,
+/* 7197*/ OPC_EmitInteger, MVT::i32, 0,
+/* 7200*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 7208*/ /*Scope*/ 17, /*->7226*/
+/* 7209*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7211*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 7214*/ OPC_EmitMergeInputChains1_0,
+/* 7215*/ OPC_EmitInteger, MVT::i64, 0,
+/* 7218*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 7226*/ /*Scope*/ 17, /*->7244*/
+/* 7227*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 7229*/ OPC_CheckComplexPat, /*CP*/0, /*#*/2, // SelectAddrFI:$rs1 #3
+/* 7232*/ OPC_EmitMergeInputChains1_0,
+/* 7233*/ OPC_EmitInteger, MVT::i32, 0,
+/* 7236*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 3, 4,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 10
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 7244*/ /*Scope*/ 34, /*->7279*/
+/* 7245*/ OPC_CheckChild2Type, MVT::i32,
+/* 7247*/ OPC_Scope, 14, /*->7263*/ // 2 children in Scope
+/* 7249*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7251*/ OPC_EmitMergeInputChains1_0,
+/* 7252*/ OPC_EmitInteger, MVT::i32, 0,
+/* 7255*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 7263*/ /*Scope*/ 14, /*->7278*/
+/* 7264*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 7266*/ OPC_EmitMergeInputChains1_0,
+/* 7267*/ OPC_EmitInteger, MVT::i32, 0,
+/* 7270*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 7278*/ 0, /*End of Scope*/
+/* 7279*/ /*Scope*/ 16, /*->7296*/
+/* 7280*/ OPC_CheckChild2Type, MVT::i64,
+/* 7282*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 7284*/ OPC_EmitMergeInputChains1_0,
+/* 7285*/ OPC_EmitInteger, MVT::i64, 0,
+/* 7288*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FSD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> - Complexity = 4
+ // Dst: (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 7296*/ 0, /*End of Scope*/
+/* 7297*/ 0, /*End of Scope*/
+/* 7298*/ 0, /*End of Scope*/
+/* 7299*/ /*SwitchOpcode*/ 74|128,9/*1226*/, TARGET_VAL(ISD::ATOMIC_STORE),// ->8529
+/* 7303*/ OPC_RecordMemRef,
+/* 7304*/ OPC_RecordNode, // #0 = 'atomic_store' chained node
+/* 7305*/ OPC_Scope, 90|128,5/*730*/, /*->8038*/ // 2 children in Scope
+/* 7308*/ OPC_MoveChild1,
+/* 7309*/ OPC_SwitchOpcode /*2 cases */, 6|128,2/*262*/, TARGET_VAL(ISD::OR),// ->7576
+/* 7314*/ OPC_RecordChild0, // #1 = $rs1
+/* 7315*/ OPC_RecordChild1, // #2 = $imm12
+/* 7316*/ OPC_MoveChild1,
+/* 7317*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 7320*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 7322*/ OPC_MoveParent,
+/* 7323*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 7325*/ OPC_SwitchType /*2 cases */, 34|128,1/*162*/, MVT::i32,// ->7491
+/* 7329*/ OPC_MoveParent,
+/* 7330*/ OPC_RecordChild2, // #3 = $rs2
+/* 7331*/ OPC_CheckChild2Type, MVT::i32,
+/* 7333*/ OPC_Scope, 38, /*->7373*/ // 4 children in Scope
+/* 7335*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 7337*/ OPC_Scope, 16, /*->7355*/ // 2 children in Scope
+/* 7339*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7341*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7344*/ OPC_EmitMergeInputChains1_0,
+/* 7345*/ OPC_EmitConvertToTarget, 2,
+/* 7347*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 18
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7355*/ /*Scope*/ 16, /*->7372*/
+/* 7356*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7358*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7361*/ OPC_EmitMergeInputChains1_0,
+/* 7362*/ OPC_EmitConvertToTarget, 2,
+/* 7364*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 18
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7372*/ 0, /*End of Scope*/
+/* 7373*/ /*Scope*/ 38, /*->7412*/
+/* 7374*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 7376*/ OPC_Scope, 16, /*->7394*/ // 2 children in Scope
+/* 7378*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7380*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7383*/ OPC_EmitMergeInputChains1_0,
+/* 7384*/ OPC_EmitConvertToTarget, 2,
+/* 7386*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 18
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7394*/ /*Scope*/ 16, /*->7411*/
+/* 7395*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7397*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7400*/ OPC_EmitMergeInputChains1_0,
+/* 7401*/ OPC_EmitConvertToTarget, 2,
+/* 7403*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 18
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7411*/ 0, /*End of Scope*/
+/* 7412*/ /*Scope*/ 38, /*->7451*/
+/* 7413*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 7415*/ OPC_Scope, 16, /*->7433*/ // 2 children in Scope
+/* 7417*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7419*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7422*/ OPC_EmitMergeInputChains1_0,
+/* 7423*/ OPC_EmitConvertToTarget, 2,
+/* 7425*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7433*/ /*Scope*/ 16, /*->7450*/
+/* 7434*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7436*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7439*/ OPC_EmitMergeInputChains1_0,
+/* 7440*/ OPC_EmitConvertToTarget, 2,
+/* 7442*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7450*/ 0, /*End of Scope*/
+/* 7451*/ /*Scope*/ 38, /*->7490*/
+/* 7452*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 7454*/ OPC_Scope, 16, /*->7472*/ // 2 children in Scope
+/* 7456*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7458*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7461*/ OPC_EmitMergeInputChains1_0,
+/* 7462*/ OPC_EmitConvertToTarget, 2,
+/* 7464*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 18
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7472*/ /*Scope*/ 16, /*->7489*/
+/* 7473*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 7475*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7478*/ OPC_EmitMergeInputChains1_0,
+/* 7479*/ OPC_EmitConvertToTarget, 2,
+/* 7481*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 18
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7489*/ 0, /*End of Scope*/
+/* 7490*/ 0, /*End of Scope*/
+/* 7491*/ /*SwitchType*/ 82, MVT::i64,// ->7575
+/* 7493*/ OPC_MoveParent,
+/* 7494*/ OPC_RecordChild2, // #3 = $rs2
+/* 7495*/ OPC_CheckChild2Type, MVT::i64,
+/* 7497*/ OPC_Scope, 18, /*->7517*/ // 4 children in Scope
+/* 7499*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 7501*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7503*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7506*/ OPC_EmitMergeInputChains1_0,
+/* 7507*/ OPC_EmitConvertToTarget, 2,
+/* 7509*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 18
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7517*/ /*Scope*/ 18, /*->7536*/
+/* 7518*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 7520*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7522*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7525*/ OPC_EmitMergeInputChains1_0,
+/* 7526*/ OPC_EmitConvertToTarget, 2,
+/* 7528*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 18
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7536*/ /*Scope*/ 18, /*->7555*/
+/* 7537*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 7539*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7541*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7544*/ OPC_EmitMergeInputChains1_0,
+/* 7545*/ OPC_EmitConvertToTarget, 2,
+/* 7547*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 18
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7555*/ /*Scope*/ 18, /*->7574*/
+/* 7556*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 7558*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7560*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7563*/ OPC_EmitMergeInputChains1_0,
+/* 7564*/ OPC_EmitConvertToTarget, 2,
+/* 7566*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 18
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7574*/ 0, /*End of Scope*/
+/* 7575*/ 0, // EndSwitchType
+/* 7576*/ /*SwitchOpcode*/ 73|128,3/*457*/, TARGET_VAL(ISD::ADD),// ->8037
+/* 7580*/ OPC_RecordChild0, // #1 = $rs1
+/* 7581*/ OPC_RecordChild1, // #2 = $imm12
+/* 7582*/ OPC_MoveChild1,
+/* 7583*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 7586*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 7588*/ OPC_MoveParent,
+/* 7589*/ OPC_SwitchType /*2 cases */, 38|128,2/*294*/, MVT::i32,// ->7887
+/* 7593*/ OPC_MoveParent,
+/* 7594*/ OPC_RecordChild2, // #3 = $rs2
+/* 7595*/ OPC_CheckChild2Type, MVT::i32,
+/* 7597*/ OPC_Scope, 38, /*->7637*/ // 8 children in Scope
+/* 7599*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 7601*/ OPC_Scope, 16, /*->7619*/ // 2 children in Scope
+/* 7603*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7605*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7608*/ OPC_EmitMergeInputChains1_0,
+/* 7609*/ OPC_EmitConvertToTarget, 2,
+/* 7611*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 17
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7619*/ /*Scope*/ 16, /*->7636*/
+/* 7620*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7622*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7625*/ OPC_EmitMergeInputChains1_0,
+/* 7626*/ OPC_EmitConvertToTarget, 2,
+/* 7628*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 17
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7636*/ 0, /*End of Scope*/
+/* 7637*/ /*Scope*/ 38, /*->7676*/
+/* 7638*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 7640*/ OPC_Scope, 16, /*->7658*/ // 2 children in Scope
+/* 7642*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7644*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7647*/ OPC_EmitMergeInputChains1_0,
+/* 7648*/ OPC_EmitConvertToTarget, 2,
+/* 7650*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 17
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7658*/ /*Scope*/ 16, /*->7675*/
+/* 7659*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7661*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7664*/ OPC_EmitMergeInputChains1_0,
+/* 7665*/ OPC_EmitConvertToTarget, 2,
+/* 7667*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 17
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7675*/ 0, /*End of Scope*/
+/* 7676*/ /*Scope*/ 38, /*->7715*/
+/* 7677*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 7679*/ OPC_Scope, 16, /*->7697*/ // 2 children in Scope
+/* 7681*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7683*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7686*/ OPC_EmitMergeInputChains1_0,
+/* 7687*/ OPC_EmitConvertToTarget, 2,
+/* 7689*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7697*/ /*Scope*/ 16, /*->7714*/
+/* 7698*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7700*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7703*/ OPC_EmitMergeInputChains1_0,
+/* 7704*/ OPC_EmitConvertToTarget, 2,
+/* 7706*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7714*/ 0, /*End of Scope*/
+/* 7715*/ /*Scope*/ 38, /*->7754*/
+/* 7716*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 7718*/ OPC_Scope, 16, /*->7736*/ // 2 children in Scope
+/* 7720*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7722*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7725*/ OPC_EmitMergeInputChains1_0,
+/* 7726*/ OPC_EmitConvertToTarget, 2,
+/* 7728*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 17
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7736*/ /*Scope*/ 16, /*->7753*/
+/* 7737*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 7739*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7742*/ OPC_EmitMergeInputChains1_0,
+/* 7743*/ OPC_EmitConvertToTarget, 2,
+/* 7745*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 17
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7753*/ 0, /*End of Scope*/
+/* 7754*/ /*Scope*/ 32, /*->7787*/
+/* 7755*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 7757*/ OPC_Scope, 13, /*->7772*/ // 2 children in Scope
+/* 7759*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7761*/ OPC_EmitMergeInputChains1_0,
+/* 7762*/ OPC_EmitConvertToTarget, 2,
+/* 7764*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 11
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7772*/ /*Scope*/ 13, /*->7786*/
+/* 7773*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7775*/ OPC_EmitMergeInputChains1_0,
+/* 7776*/ OPC_EmitConvertToTarget, 2,
+/* 7778*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 11
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7786*/ 0, /*End of Scope*/
+/* 7787*/ /*Scope*/ 32, /*->7820*/
+/* 7788*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 7790*/ OPC_Scope, 13, /*->7805*/ // 2 children in Scope
+/* 7792*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7794*/ OPC_EmitMergeInputChains1_0,
+/* 7795*/ OPC_EmitConvertToTarget, 2,
+/* 7797*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 11
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7805*/ /*Scope*/ 13, /*->7819*/
+/* 7806*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7808*/ OPC_EmitMergeInputChains1_0,
+/* 7809*/ OPC_EmitConvertToTarget, 2,
+/* 7811*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 11
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7819*/ 0, /*End of Scope*/
+/* 7820*/ /*Scope*/ 32, /*->7853*/
+/* 7821*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 7823*/ OPC_Scope, 13, /*->7838*/ // 2 children in Scope
+/* 7825*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7827*/ OPC_EmitMergeInputChains1_0,
+/* 7828*/ OPC_EmitConvertToTarget, 2,
+/* 7830*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7838*/ /*Scope*/ 13, /*->7852*/
+/* 7839*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 7841*/ OPC_EmitMergeInputChains1_0,
+/* 7842*/ OPC_EmitConvertToTarget, 2,
+/* 7844*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7852*/ 0, /*End of Scope*/
+/* 7853*/ /*Scope*/ 32, /*->7886*/
+/* 7854*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 7856*/ OPC_Scope, 13, /*->7871*/ // 2 children in Scope
+/* 7858*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 7860*/ OPC_EmitMergeInputChains1_0,
+/* 7861*/ OPC_EmitConvertToTarget, 2,
+/* 7863*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 11
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7871*/ /*Scope*/ 13, /*->7885*/
+/* 7872*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 7874*/ OPC_EmitMergeInputChains1_0,
+/* 7875*/ OPC_EmitConvertToTarget, 2,
+/* 7877*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 11
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 7885*/ 0, /*End of Scope*/
+/* 7886*/ 0, /*End of Scope*/
+/* 7887*/ /*SwitchType*/ 18|128,1/*146*/, MVT::i64,// ->8036
+/* 7890*/ OPC_MoveParent,
+/* 7891*/ OPC_RecordChild2, // #3 = $rs2
+/* 7892*/ OPC_CheckChild2Type, MVT::i64,
+/* 7894*/ OPC_Scope, 18, /*->7914*/ // 8 children in Scope
+/* 7896*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 7898*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7900*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7903*/ OPC_EmitMergeInputChains1_0,
+/* 7904*/ OPC_EmitConvertToTarget, 2,
+/* 7906*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 17
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7914*/ /*Scope*/ 18, /*->7933*/
+/* 7915*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 7917*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7919*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7922*/ OPC_EmitMergeInputChains1_0,
+/* 7923*/ OPC_EmitConvertToTarget, 2,
+/* 7925*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 17
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7933*/ /*Scope*/ 18, /*->7952*/
+/* 7934*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 7936*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7938*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7941*/ OPC_EmitMergeInputChains1_0,
+/* 7942*/ OPC_EmitConvertToTarget, 2,
+/* 7944*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 17
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7952*/ /*Scope*/ 18, /*->7971*/
+/* 7953*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 7955*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7957*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #4
+/* 7960*/ OPC_EmitMergeInputChains1_0,
+/* 7961*/ OPC_EmitConvertToTarget, 2,
+/* 7963*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 4, 5,
+ // Src: (atomic_store (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 17
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7971*/ /*Scope*/ 15, /*->7987*/
+/* 7972*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 7974*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7976*/ OPC_EmitMergeInputChains1_0,
+/* 7977*/ OPC_EmitConvertToTarget, 2,
+/* 7979*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 11
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 7987*/ /*Scope*/ 15, /*->8003*/
+/* 7988*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 7990*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 7992*/ OPC_EmitMergeInputChains1_0,
+/* 7993*/ OPC_EmitConvertToTarget, 2,
+/* 7995*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 11
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 8003*/ /*Scope*/ 15, /*->8019*/
+/* 8004*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 8006*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8008*/ OPC_EmitMergeInputChains1_0,
+/* 8009*/ OPC_EmitConvertToTarget, 2,
+/* 8011*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 11
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 8019*/ /*Scope*/ 15, /*->8035*/
+/* 8020*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 8022*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8024*/ OPC_EmitMergeInputChains1_0,
+/* 8025*/ OPC_EmitConvertToTarget, 2,
+/* 8027*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 3, 1, 4,
+ // Src: (atomic_store (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 11
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 8035*/ 0, /*End of Scope*/
+/* 8036*/ 0, // EndSwitchType
+/* 8037*/ 0, // EndSwitchOpcode
+/* 8038*/ /*Scope*/ 104|128,3/*488*/, /*->8528*/
+/* 8040*/ OPC_RecordChild1, // #1 = $rs1
+/* 8041*/ OPC_Scope, 2|128,2/*258*/, /*->8302*/ // 3 children in Scope
+/* 8044*/ OPC_RecordChild2, // #2 = $rs2
+/* 8045*/ OPC_Scope, 40|128,1/*168*/, /*->8216*/ // 2 children in Scope
+/* 8048*/ OPC_CheckChild2Type, MVT::i32,
+/* 8050*/ OPC_Scope, 40, /*->8092*/ // 4 children in Scope
+/* 8052*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 8054*/ OPC_Scope, 17, /*->8073*/ // 2 children in Scope
+/* 8056*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8058*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8061*/ OPC_EmitMergeInputChains1_0,
+/* 8062*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8065*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 10
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8073*/ /*Scope*/ 17, /*->8091*/
+/* 8074*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8076*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8079*/ OPC_EmitMergeInputChains1_0,
+/* 8080*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8083*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 10
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8091*/ 0, /*End of Scope*/
+/* 8092*/ /*Scope*/ 40, /*->8133*/
+/* 8093*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 8095*/ OPC_Scope, 17, /*->8114*/ // 2 children in Scope
+/* 8097*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8099*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8102*/ OPC_EmitMergeInputChains1_0,
+/* 8103*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8106*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 10
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8114*/ /*Scope*/ 17, /*->8132*/
+/* 8115*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8117*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8120*/ OPC_EmitMergeInputChains1_0,
+/* 8121*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8124*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 10
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8132*/ 0, /*End of Scope*/
+/* 8133*/ /*Scope*/ 40, /*->8174*/
+/* 8134*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 8136*/ OPC_Scope, 17, /*->8155*/ // 2 children in Scope
+/* 8138*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8140*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8143*/ OPC_EmitMergeInputChains1_0,
+/* 8144*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8147*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8155*/ /*Scope*/ 17, /*->8173*/
+/* 8156*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8158*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8161*/ OPC_EmitMergeInputChains1_0,
+/* 8162*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8165*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8173*/ 0, /*End of Scope*/
+/* 8174*/ /*Scope*/ 40, /*->8215*/
+/* 8175*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 8177*/ OPC_Scope, 17, /*->8196*/ // 2 children in Scope
+/* 8179*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8181*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8184*/ OPC_EmitMergeInputChains1_0,
+/* 8185*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8188*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 10
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8196*/ /*Scope*/ 17, /*->8214*/
+/* 8197*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 8199*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8202*/ OPC_EmitMergeInputChains1_0,
+/* 8203*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8206*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 10
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8214*/ 0, /*End of Scope*/
+/* 8215*/ 0, /*End of Scope*/
+/* 8216*/ /*Scope*/ 84, /*->8301*/
+/* 8217*/ OPC_CheckChild2Type, MVT::i64,
+/* 8219*/ OPC_Scope, 19, /*->8240*/ // 4 children in Scope
+/* 8221*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 8223*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8225*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8228*/ OPC_EmitMergeInputChains1_0,
+/* 8229*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8232*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 10
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 8240*/ /*Scope*/ 19, /*->8260*/
+/* 8241*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 8243*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8245*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8248*/ OPC_EmitMergeInputChains1_0,
+/* 8249*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8252*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 10
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 8260*/ /*Scope*/ 19, /*->8280*/
+/* 8261*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 8263*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8265*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8268*/ OPC_EmitMergeInputChains1_0,
+/* 8269*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8272*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 10
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 8280*/ /*Scope*/ 19, /*->8300*/
+/* 8281*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 8283*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8285*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8288*/ OPC_EmitMergeInputChains1_0,
+/* 8289*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8292*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 3, 4,
+ // Src: (atomic_store AddrFI:{ *:[iPTR] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 10
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 8300*/ 0, /*End of Scope*/
+/* 8301*/ 0, /*End of Scope*/
+/* 8302*/ /*Scope*/ 19|128,1/*147*/, /*->8451*/
+/* 8304*/ OPC_CheckChild1Type, MVT::i32,
+/* 8306*/ OPC_RecordChild2, // #2 = $rs2
+/* 8307*/ OPC_CheckChild2Type, MVT::i32,
+/* 8309*/ OPC_Scope, 34, /*->8345*/ // 4 children in Scope
+/* 8311*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 8313*/ OPC_Scope, 14, /*->8329*/ // 2 children in Scope
+/* 8315*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8317*/ OPC_EmitMergeInputChains1_0,
+/* 8318*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8321*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 4
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8329*/ /*Scope*/ 14, /*->8344*/
+/* 8330*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8332*/ OPC_EmitMergeInputChains1_0,
+/* 8333*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8336*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 4
+ // Dst: (SB GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8344*/ 0, /*End of Scope*/
+/* 8345*/ /*Scope*/ 34, /*->8380*/
+/* 8346*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 8348*/ OPC_Scope, 14, /*->8364*/ // 2 children in Scope
+/* 8350*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8352*/ OPC_EmitMergeInputChains1_0,
+/* 8353*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8356*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 4
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8364*/ /*Scope*/ 14, /*->8379*/
+/* 8365*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8367*/ OPC_EmitMergeInputChains1_0,
+/* 8368*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8371*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 4
+ // Dst: (SH GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8379*/ 0, /*End of Scope*/
+/* 8380*/ /*Scope*/ 34, /*->8415*/
+/* 8381*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 8383*/ OPC_Scope, 14, /*->8399*/ // 2 children in Scope
+/* 8385*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8387*/ OPC_EmitMergeInputChains1_0,
+/* 8388*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8391*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8399*/ /*Scope*/ 14, /*->8414*/
+/* 8400*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8402*/ OPC_EmitMergeInputChains1_0,
+/* 8403*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8406*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8414*/ 0, /*End of Scope*/
+/* 8415*/ /*Scope*/ 34, /*->8450*/
+/* 8416*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 8418*/ OPC_Scope, 14, /*->8434*/ // 2 children in Scope
+/* 8420*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8422*/ OPC_EmitMergeInputChains1_0,
+/* 8423*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8426*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 4
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8434*/ /*Scope*/ 14, /*->8449*/
+/* 8435*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 8437*/ OPC_EmitMergeInputChains1_0,
+/* 8438*/ OPC_EmitInteger, MVT::i32, 0,
+/* 8441*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 4
+ // Dst: (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 8449*/ 0, /*End of Scope*/
+/* 8450*/ 0, /*End of Scope*/
+/* 8451*/ /*Scope*/ 75, /*->8527*/
+/* 8452*/ OPC_CheckChild1Type, MVT::i64,
+/* 8454*/ OPC_RecordChild2, // #2 = $rs2
+/* 8455*/ OPC_CheckChild2Type, MVT::i64,
+/* 8457*/ OPC_Scope, 16, /*->8475*/ // 4 children in Scope
+/* 8459*/ OPC_CheckPredicate, 5, // Predicate_atomic_store_8
+/* 8461*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8463*/ OPC_EmitMergeInputChains1_0,
+/* 8464*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8467*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SB), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_8>> - Complexity = 4
+ // Dst: (SB GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 8475*/ /*Scope*/ 16, /*->8492*/
+/* 8476*/ OPC_CheckPredicate, 7, // Predicate_atomic_store_16
+/* 8478*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8480*/ OPC_EmitMergeInputChains1_0,
+/* 8481*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8484*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SH), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_16>> - Complexity = 4
+ // Dst: (SH GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 8492*/ /*Scope*/ 16, /*->8509*/
+/* 8493*/ OPC_CheckPredicate, 10, // Predicate_atomic_store_32
+/* 8495*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8497*/ OPC_EmitMergeInputChains1_0,
+/* 8498*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8501*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SW), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_32>> - Complexity = 4
+ // Dst: (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 8509*/ /*Scope*/ 16, /*->8526*/
+/* 8510*/ OPC_CheckPredicate, 14, // Predicate_atomic_store_64
+/* 8512*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8514*/ OPC_EmitMergeInputChains1_0,
+/* 8515*/ OPC_EmitInteger, MVT::i64, 0,
+/* 8518*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SD), 0|OPFL_Chain|OPFL_MemRefs,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (atomic_store GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_store_64>> - Complexity = 4
+ // Dst: (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 8526*/ 0, /*End of Scope*/
+/* 8527*/ 0, /*End of Scope*/
+/* 8528*/ 0, /*End of Scope*/
+/* 8529*/ /*SwitchOpcode*/ 64|128,9/*1216*/, TARGET_VAL(ISD::ATOMIC_LOAD),// ->9749
+/* 8533*/ OPC_RecordMemRef,
+/* 8534*/ OPC_RecordNode, // #0 = 'atomic_load' chained node
+/* 8535*/ OPC_Scope, 86|128,5/*726*/, /*->9264*/ // 2 children in Scope
+/* 8538*/ OPC_MoveChild1,
+/* 8539*/ OPC_SwitchOpcode /*2 cases */, 4|128,2/*260*/, TARGET_VAL(ISD::OR),// ->8804
+/* 8544*/ OPC_RecordChild0, // #1 = $rs1
+/* 8545*/ OPC_RecordChild1, // #2 = $imm12
+/* 8546*/ OPC_MoveChild1,
+/* 8547*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8550*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 8552*/ OPC_MoveParent,
+/* 8553*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 8555*/ OPC_SwitchType /*2 cases */, 33|128,1/*161*/, MVT::i32,// ->8720
+/* 8559*/ OPC_MoveParent,
+/* 8560*/ OPC_CheckType, MVT::i32,
+/* 8562*/ OPC_Scope, 38, /*->8602*/ // 4 children in Scope
+/* 8564*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 8566*/ OPC_Scope, 16, /*->8584*/ // 2 children in Scope
+/* 8568*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8570*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8573*/ OPC_EmitMergeInputChains1_0,
+/* 8574*/ OPC_EmitConvertToTarget, 2,
+/* 8576*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_8>> - Complexity = 18
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8584*/ /*Scope*/ 16, /*->8601*/
+/* 8585*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8587*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8590*/ OPC_EmitMergeInputChains1_0,
+/* 8591*/ OPC_EmitConvertToTarget, 2,
+/* 8593*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_8>> - Complexity = 18
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8601*/ 0, /*End of Scope*/
+/* 8602*/ /*Scope*/ 38, /*->8641*/
+/* 8603*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 8605*/ OPC_Scope, 16, /*->8623*/ // 2 children in Scope
+/* 8607*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8609*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8612*/ OPC_EmitMergeInputChains1_0,
+/* 8613*/ OPC_EmitConvertToTarget, 2,
+/* 8615*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_16>> - Complexity = 18
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8623*/ /*Scope*/ 16, /*->8640*/
+/* 8624*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8626*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8629*/ OPC_EmitMergeInputChains1_0,
+/* 8630*/ OPC_EmitConvertToTarget, 2,
+/* 8632*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_16>> - Complexity = 18
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8640*/ 0, /*End of Scope*/
+/* 8641*/ /*Scope*/ 38, /*->8680*/
+/* 8642*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 8644*/ OPC_Scope, 16, /*->8662*/ // 2 children in Scope
+/* 8646*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8648*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8651*/ OPC_EmitMergeInputChains1_0,
+/* 8652*/ OPC_EmitConvertToTarget, 2,
+/* 8654*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_32>> - Complexity = 18
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8662*/ /*Scope*/ 16, /*->8679*/
+/* 8663*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8665*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8668*/ OPC_EmitMergeInputChains1_0,
+/* 8669*/ OPC_EmitConvertToTarget, 2,
+/* 8671*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_32>> - Complexity = 18
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8679*/ 0, /*End of Scope*/
+/* 8680*/ /*Scope*/ 38, /*->8719*/
+/* 8681*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 8683*/ OPC_Scope, 16, /*->8701*/ // 2 children in Scope
+/* 8685*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8687*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8690*/ OPC_EmitMergeInputChains1_0,
+/* 8691*/ OPC_EmitConvertToTarget, 2,
+/* 8693*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_64>> - Complexity = 18
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8701*/ /*Scope*/ 16, /*->8718*/
+/* 8702*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 8704*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8707*/ OPC_EmitMergeInputChains1_0,
+/* 8708*/ OPC_EmitConvertToTarget, 2,
+/* 8710*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (or:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_64>> - Complexity = 18
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8718*/ 0, /*End of Scope*/
+/* 8719*/ 0, /*End of Scope*/
+/* 8720*/ /*SwitchType*/ 81, MVT::i64,// ->8803
+/* 8722*/ OPC_MoveParent,
+/* 8723*/ OPC_CheckType, MVT::i64,
+/* 8725*/ OPC_Scope, 18, /*->8745*/ // 4 children in Scope
+/* 8727*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 8729*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 8731*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8734*/ OPC_EmitMergeInputChains1_0,
+/* 8735*/ OPC_EmitConvertToTarget, 2,
+/* 8737*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_8>> - Complexity = 18
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 8745*/ /*Scope*/ 18, /*->8764*/
+/* 8746*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 8748*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8750*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8753*/ OPC_EmitMergeInputChains1_0,
+/* 8754*/ OPC_EmitConvertToTarget, 2,
+/* 8756*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_16>> - Complexity = 18
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 8764*/ /*Scope*/ 18, /*->8783*/
+/* 8765*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 8767*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8769*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8772*/ OPC_EmitMergeInputChains1_0,
+/* 8773*/ OPC_EmitConvertToTarget, 2,
+/* 8775*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_32>> - Complexity = 18
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 8783*/ /*Scope*/ 18, /*->8802*/
+/* 8784*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 8786*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 8788*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8791*/ OPC_EmitMergeInputChains1_0,
+/* 8792*/ OPC_EmitConvertToTarget, 2,
+/* 8794*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i64] } (or:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>>)<<P:Predicate_atomic_load_64>> - Complexity = 18
+ // Dst: (LD:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 8802*/ 0, /*End of Scope*/
+/* 8803*/ 0, // EndSwitchType
+/* 8804*/ /*SwitchOpcode*/ 71|128,3/*455*/, TARGET_VAL(ISD::ADD),// ->9263
+/* 8808*/ OPC_RecordChild0, // #1 = $rs1
+/* 8809*/ OPC_RecordChild1, // #2 = $imm12
+/* 8810*/ OPC_MoveChild1,
+/* 8811*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 8814*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 8816*/ OPC_MoveParent,
+/* 8817*/ OPC_SwitchType /*2 cases */, 37|128,2/*293*/, MVT::i32,// ->9114
+/* 8821*/ OPC_MoveParent,
+/* 8822*/ OPC_CheckType, MVT::i32,
+/* 8824*/ OPC_Scope, 38, /*->8864*/ // 8 children in Scope
+/* 8826*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 8828*/ OPC_Scope, 16, /*->8846*/ // 2 children in Scope
+/* 8830*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8832*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8835*/ OPC_EmitMergeInputChains1_0,
+/* 8836*/ OPC_EmitConvertToTarget, 2,
+/* 8838*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> - Complexity = 17
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8846*/ /*Scope*/ 16, /*->8863*/
+/* 8847*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8849*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8852*/ OPC_EmitMergeInputChains1_0,
+/* 8853*/ OPC_EmitConvertToTarget, 2,
+/* 8855*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> - Complexity = 17
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8863*/ 0, /*End of Scope*/
+/* 8864*/ /*Scope*/ 38, /*->8903*/
+/* 8865*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 8867*/ OPC_Scope, 16, /*->8885*/ // 2 children in Scope
+/* 8869*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8871*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8874*/ OPC_EmitMergeInputChains1_0,
+/* 8875*/ OPC_EmitConvertToTarget, 2,
+/* 8877*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> - Complexity = 17
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8885*/ /*Scope*/ 16, /*->8902*/
+/* 8886*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8888*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8891*/ OPC_EmitMergeInputChains1_0,
+/* 8892*/ OPC_EmitConvertToTarget, 2,
+/* 8894*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> - Complexity = 17
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8902*/ 0, /*End of Scope*/
+/* 8903*/ /*Scope*/ 38, /*->8942*/
+/* 8904*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 8906*/ OPC_Scope, 16, /*->8924*/ // 2 children in Scope
+/* 8908*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8910*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8913*/ OPC_EmitMergeInputChains1_0,
+/* 8914*/ OPC_EmitConvertToTarget, 2,
+/* 8916*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> - Complexity = 17
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8924*/ /*Scope*/ 16, /*->8941*/
+/* 8925*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 8927*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8930*/ OPC_EmitMergeInputChains1_0,
+/* 8931*/ OPC_EmitConvertToTarget, 2,
+/* 8933*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> - Complexity = 17
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8941*/ 0, /*End of Scope*/
+/* 8942*/ /*Scope*/ 38, /*->8981*/
+/* 8943*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 8945*/ OPC_Scope, 16, /*->8963*/ // 2 children in Scope
+/* 8947*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8949*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8952*/ OPC_EmitMergeInputChains1_0,
+/* 8953*/ OPC_EmitConvertToTarget, 2,
+/* 8955*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> - Complexity = 17
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8963*/ /*Scope*/ 16, /*->8980*/
+/* 8964*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 8966*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 8969*/ OPC_EmitMergeInputChains1_0,
+/* 8970*/ OPC_EmitConvertToTarget, 2,
+/* 8972*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> - Complexity = 17
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8980*/ 0, /*End of Scope*/
+/* 8981*/ /*Scope*/ 32, /*->9014*/
+/* 8982*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 8984*/ OPC_Scope, 13, /*->8999*/ // 2 children in Scope
+/* 8986*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 8988*/ OPC_EmitMergeInputChains1_0,
+/* 8989*/ OPC_EmitConvertToTarget, 2,
+/* 8991*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> - Complexity = 11
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 8999*/ /*Scope*/ 13, /*->9013*/
+/* 9000*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9002*/ OPC_EmitMergeInputChains1_0,
+/* 9003*/ OPC_EmitConvertToTarget, 2,
+/* 9005*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> - Complexity = 11
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9013*/ 0, /*End of Scope*/
+/* 9014*/ /*Scope*/ 32, /*->9047*/
+/* 9015*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 9017*/ OPC_Scope, 13, /*->9032*/ // 2 children in Scope
+/* 9019*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9021*/ OPC_EmitMergeInputChains1_0,
+/* 9022*/ OPC_EmitConvertToTarget, 2,
+/* 9024*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> - Complexity = 11
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9032*/ /*Scope*/ 13, /*->9046*/
+/* 9033*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9035*/ OPC_EmitMergeInputChains1_0,
+/* 9036*/ OPC_EmitConvertToTarget, 2,
+/* 9038*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> - Complexity = 11
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9046*/ 0, /*End of Scope*/
+/* 9047*/ /*Scope*/ 32, /*->9080*/
+/* 9048*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 9050*/ OPC_Scope, 13, /*->9065*/ // 2 children in Scope
+/* 9052*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9054*/ OPC_EmitMergeInputChains1_0,
+/* 9055*/ OPC_EmitConvertToTarget, 2,
+/* 9057*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> - Complexity = 11
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9065*/ /*Scope*/ 13, /*->9079*/
+/* 9066*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9068*/ OPC_EmitMergeInputChains1_0,
+/* 9069*/ OPC_EmitConvertToTarget, 2,
+/* 9071*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> - Complexity = 11
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9079*/ 0, /*End of Scope*/
+/* 9080*/ /*Scope*/ 32, /*->9113*/
+/* 9081*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 9083*/ OPC_Scope, 13, /*->9098*/ // 2 children in Scope
+/* 9085*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9087*/ OPC_EmitMergeInputChains1_0,
+/* 9088*/ OPC_EmitConvertToTarget, 2,
+/* 9090*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> - Complexity = 11
+ // Dst: (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9098*/ /*Scope*/ 13, /*->9112*/
+/* 9099*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 9101*/ OPC_EmitMergeInputChains1_0,
+/* 9102*/ OPC_EmitConvertToTarget, 2,
+/* 9104*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> - Complexity = 11
+ // Dst: (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9112*/ 0, /*End of Scope*/
+/* 9113*/ 0, /*End of Scope*/
+/* 9114*/ /*SwitchType*/ 17|128,1/*145*/, MVT::i64,// ->9262
+/* 9117*/ OPC_MoveParent,
+/* 9118*/ OPC_CheckType, MVT::i64,
+/* 9120*/ OPC_Scope, 18, /*->9140*/ // 8 children in Scope
+/* 9122*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 9124*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9126*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 9129*/ OPC_EmitMergeInputChains1_0,
+/* 9130*/ OPC_EmitConvertToTarget, 2,
+/* 9132*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> - Complexity = 17
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9140*/ /*Scope*/ 18, /*->9159*/
+/* 9141*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 9143*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9145*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 9148*/ OPC_EmitMergeInputChains1_0,
+/* 9149*/ OPC_EmitConvertToTarget, 2,
+/* 9151*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> - Complexity = 17
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9159*/ /*Scope*/ 18, /*->9178*/
+/* 9160*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 9162*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9164*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 9167*/ OPC_EmitMergeInputChains1_0,
+/* 9168*/ OPC_EmitConvertToTarget, 2,
+/* 9170*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> - Complexity = 17
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9178*/ /*Scope*/ 18, /*->9197*/
+/* 9179*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 9181*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9183*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #3
+/* 9186*/ OPC_EmitMergeInputChains1_0,
+/* 9187*/ OPC_EmitConvertToTarget, 2,
+/* 9189*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (atomic_load:{ *:[i64] } (add:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> - Complexity = 17
+ // Dst: (LD:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9197*/ /*Scope*/ 15, /*->9213*/
+/* 9198*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 9200*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9202*/ OPC_EmitMergeInputChains1_0,
+/* 9203*/ OPC_EmitConvertToTarget, 2,
+/* 9205*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> - Complexity = 11
+ // Dst: (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9213*/ /*Scope*/ 15, /*->9229*/
+/* 9214*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 9216*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9218*/ OPC_EmitMergeInputChains1_0,
+/* 9219*/ OPC_EmitConvertToTarget, 2,
+/* 9221*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> - Complexity = 11
+ // Dst: (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9229*/ /*Scope*/ 15, /*->9245*/
+/* 9230*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 9232*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9234*/ OPC_EmitMergeInputChains1_0,
+/* 9235*/ OPC_EmitConvertToTarget, 2,
+/* 9237*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> - Complexity = 11
+ // Dst: (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9245*/ /*Scope*/ 15, /*->9261*/
+/* 9246*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 9248*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9250*/ OPC_EmitMergeInputChains1_0,
+/* 9251*/ OPC_EmitConvertToTarget, 2,
+/* 9253*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 3,
+ // Src: (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> - Complexity = 11
+ // Dst: (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9261*/ 0, /*End of Scope*/
+/* 9262*/ 0, // EndSwitchType
+/* 9263*/ 0, // EndSwitchOpcode
+/* 9264*/ /*Scope*/ 98|128,3/*482*/, /*->9748*/
+/* 9266*/ OPC_RecordChild1, // #1 = $rs1
+/* 9267*/ OPC_Scope, 63, /*->9332*/ // 6 children in Scope
+/* 9269*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 9271*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->9312
+/* 9274*/ OPC_Scope, 17, /*->9293*/ // 2 children in Scope
+/* 9276*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9278*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9281*/ OPC_EmitMergeInputChains1_0,
+/* 9282*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9285*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_8>> - Complexity = 10
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9293*/ /*Scope*/ 17, /*->9311*/
+/* 9294*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9296*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9299*/ OPC_EmitMergeInputChains1_0,
+/* 9300*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9303*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_8>> - Complexity = 10
+ // Dst: (LB:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9311*/ 0, /*End of Scope*/
+/* 9312*/ /*SwitchType*/ 17, MVT::i64,// ->9331
+/* 9314*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 9316*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9319*/ OPC_EmitMergeInputChains1_0,
+/* 9320*/ OPC_EmitInteger, MVT::i64, 0,
+/* 9323*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_8>> - Complexity = 10
+ // Dst: (LB:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 9331*/ 0, // EndSwitchType
+/* 9332*/ /*Scope*/ 63, /*->9396*/
+/* 9333*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 9335*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->9376
+/* 9338*/ OPC_Scope, 17, /*->9357*/ // 2 children in Scope
+/* 9340*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9342*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9345*/ OPC_EmitMergeInputChains1_0,
+/* 9346*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9349*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_16>> - Complexity = 10
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9357*/ /*Scope*/ 17, /*->9375*/
+/* 9358*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9360*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9363*/ OPC_EmitMergeInputChains1_0,
+/* 9364*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9367*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_16>> - Complexity = 10
+ // Dst: (LH:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9375*/ 0, /*End of Scope*/
+/* 9376*/ /*SwitchType*/ 17, MVT::i64,// ->9395
+/* 9378*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 9380*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9383*/ OPC_EmitMergeInputChains1_0,
+/* 9384*/ OPC_EmitInteger, MVT::i64, 0,
+/* 9387*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_16>> - Complexity = 10
+ // Dst: (LH:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 9395*/ 0, // EndSwitchType
+/* 9396*/ /*Scope*/ 63, /*->9460*/
+/* 9397*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 9399*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->9440
+/* 9402*/ OPC_Scope, 17, /*->9421*/ // 2 children in Scope
+/* 9404*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9406*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9409*/ OPC_EmitMergeInputChains1_0,
+/* 9410*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9413*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_32>> - Complexity = 10
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9421*/ /*Scope*/ 17, /*->9439*/
+/* 9422*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9424*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9427*/ OPC_EmitMergeInputChains1_0,
+/* 9428*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9431*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_32>> - Complexity = 10
+ // Dst: (LW:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9439*/ 0, /*End of Scope*/
+/* 9440*/ /*SwitchType*/ 17, MVT::i64,// ->9459
+/* 9442*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 9444*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9447*/ OPC_EmitMergeInputChains1_0,
+/* 9448*/ OPC_EmitInteger, MVT::i64, 0,
+/* 9451*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_32>> - Complexity = 10
+ // Dst: (LW:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 9459*/ 0, // EndSwitchType
+/* 9460*/ /*Scope*/ 63, /*->9524*/
+/* 9461*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 9463*/ OPC_SwitchType /*2 cases */, 38, MVT::i32,// ->9504
+/* 9466*/ OPC_Scope, 17, /*->9485*/ // 2 children in Scope
+/* 9468*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9470*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9473*/ OPC_EmitMergeInputChains1_0,
+/* 9474*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9477*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_64>> - Complexity = 10
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9485*/ /*Scope*/ 17, /*->9503*/
+/* 9486*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 9488*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9491*/ OPC_EmitMergeInputChains1_0,
+/* 9492*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9495*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i32] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_64>> - Complexity = 10
+ // Dst: (LD:{ *:[i32] } AddrFI:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9503*/ 0, /*End of Scope*/
+/* 9504*/ /*SwitchType*/ 17, MVT::i64,// ->9523
+/* 9506*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("64bit"))
+/* 9508*/ OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddrFI:$rs1 #2
+/* 9511*/ OPC_EmitMergeInputChains1_0,
+/* 9512*/ OPC_EmitInteger, MVT::i64, 0,
+/* 9515*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (atomic_load:{ *:[i64] } AddrFI:{ *:[iPTR] }:$rs1)<<P:Predicate_atomic_load_64>> - Complexity = 10
+ // Dst: (LD:{ *:[i64] } AddrFI:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 9523*/ 0, // EndSwitchType
+/* 9524*/ /*Scope*/ 18|128,1/*146*/, /*->9672*/
+/* 9526*/ OPC_CheckChild1Type, MVT::i32,
+/* 9528*/ OPC_CheckType, MVT::i32,
+/* 9530*/ OPC_Scope, 34, /*->9566*/ // 4 children in Scope
+/* 9532*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 9534*/ OPC_Scope, 14, /*->9550*/ // 2 children in Scope
+/* 9536*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9538*/ OPC_EmitMergeInputChains1_0,
+/* 9539*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9542*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_8>> - Complexity = 4
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9550*/ /*Scope*/ 14, /*->9565*/
+/* 9551*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9553*/ OPC_EmitMergeInputChains1_0,
+/* 9554*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9557*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_8>> - Complexity = 4
+ // Dst: (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9565*/ 0, /*End of Scope*/
+/* 9566*/ /*Scope*/ 34, /*->9601*/
+/* 9567*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 9569*/ OPC_Scope, 14, /*->9585*/ // 2 children in Scope
+/* 9571*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9573*/ OPC_EmitMergeInputChains1_0,
+/* 9574*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9577*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_16>> - Complexity = 4
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9585*/ /*Scope*/ 14, /*->9600*/
+/* 9586*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9588*/ OPC_EmitMergeInputChains1_0,
+/* 9589*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9592*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_16>> - Complexity = 4
+ // Dst: (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9600*/ 0, /*End of Scope*/
+/* 9601*/ /*Scope*/ 34, /*->9636*/
+/* 9602*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 9604*/ OPC_Scope, 14, /*->9620*/ // 2 children in Scope
+/* 9606*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9608*/ OPC_EmitMergeInputChains1_0,
+/* 9609*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9612*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_32>> - Complexity = 4
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9620*/ /*Scope*/ 14, /*->9635*/
+/* 9621*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 9623*/ OPC_EmitMergeInputChains1_0,
+/* 9624*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9627*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_32>> - Complexity = 4
+ // Dst: (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9635*/ 0, /*End of Scope*/
+/* 9636*/ /*Scope*/ 34, /*->9671*/
+/* 9637*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 9639*/ OPC_Scope, 14, /*->9655*/ // 2 children in Scope
+/* 9641*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9643*/ OPC_EmitMergeInputChains1_0,
+/* 9644*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9647*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_64>> - Complexity = 4
+ // Dst: (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9655*/ /*Scope*/ 14, /*->9670*/
+/* 9656*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 9658*/ OPC_EmitMergeInputChains1_0,
+/* 9659*/ OPC_EmitInteger, MVT::i32, 0,
+/* 9662*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_64>> - Complexity = 4
+ // Dst: (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 9670*/ 0, /*End of Scope*/
+/* 9671*/ 0, /*End of Scope*/
+/* 9672*/ /*Scope*/ 74, /*->9747*/
+/* 9673*/ OPC_CheckChild1Type, MVT::i64,
+/* 9675*/ OPC_CheckType, MVT::i64,
+/* 9677*/ OPC_Scope, 16, /*->9695*/ // 4 children in Scope
+/* 9679*/ OPC_CheckPredicate, 5, // Predicate_atomic_load_8
+/* 9681*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9683*/ OPC_EmitMergeInputChains1_0,
+/* 9684*/ OPC_EmitInteger, MVT::i64, 0,
+/* 9687*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LB), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_8>> - Complexity = 4
+ // Dst: (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 9695*/ /*Scope*/ 16, /*->9712*/
+/* 9696*/ OPC_CheckPredicate, 7, // Predicate_atomic_load_16
+/* 9698*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9700*/ OPC_EmitMergeInputChains1_0,
+/* 9701*/ OPC_EmitInteger, MVT::i64, 0,
+/* 9704*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LH), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_16>> - Complexity = 4
+ // Dst: (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 9712*/ /*Scope*/ 16, /*->9729*/
+/* 9713*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_32
+/* 9715*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9717*/ OPC_EmitMergeInputChains1_0,
+/* 9718*/ OPC_EmitInteger, MVT::i64, 0,
+/* 9721*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LW), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_32>> - Complexity = 4
+ // Dst: (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 9729*/ /*Scope*/ 16, /*->9746*/
+/* 9730*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_64
+/* 9732*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9734*/ OPC_EmitMergeInputChains1_0,
+/* 9735*/ OPC_EmitInteger, MVT::i64, 0,
+/* 9738*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LD), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_64>> - Complexity = 4
+ // Dst: (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 9746*/ 0, /*End of Scope*/
+/* 9747*/ 0, /*End of Scope*/
+/* 9748*/ 0, /*End of Scope*/
+/* 9749*/ /*SwitchOpcode*/ 1|128,1/*129*/, TARGET_VAL(ISD::OR),// ->9882
+/* 9753*/ OPC_RecordChild0, // #0 = $Rs
+/* 9754*/ OPC_RecordChild1, // #1 = $imm12
+/* 9755*/ OPC_Scope, 86, /*->9843*/ // 3 children in Scope
+/* 9757*/ OPC_MoveChild1,
+/* 9758*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 9761*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 9763*/ OPC_MoveParent,
+/* 9764*/ OPC_SwitchType /*2 cases */, 61, MVT::i32,// ->9828
+/* 9767*/ OPC_Scope, 34, /*->9803*/ // 3 children in Scope
+/* 9769*/ OPC_CheckPredicate, 2, // Predicate_IsOrAdd
+/* 9771*/ OPC_Scope, 15, /*->9788*/ // 2 children in Scope
+/* 9773*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9775*/ OPC_CheckComplexPat, /*CP*/0, /*#*/0, // SelectAddrFI:$Rs #2
+/* 9778*/ OPC_EmitConvertToTarget, 1,
+/* 9780*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (or:{ *:[i32] } AddrFI:{ *:[i32] }:$Rs, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>> - Complexity = 14
+ // Dst: (ADDI:{ *:[i32] } AddrFI:{ *:[i32] }:$Rs, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9788*/ /*Scope*/ 13, /*->9802*/
+/* 9789*/ OPC_CheckComplexPat, /*CP*/0, /*#*/0, // SelectAddrFI:$Rs #2
+/* 9792*/ OPC_EmitConvertToTarget, 1,
+/* 9794*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (or:{ *:[i32] } AddrFI:{ *:[i32] }:$Rs, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)<<P:Predicate_IsOrAdd>> - Complexity = 14
+ // Dst: (ADDI:{ *:[i32] } AddrFI:{ *:[i32] }:$Rs, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9802*/ 0, /*End of Scope*/
+/* 9803*/ /*Scope*/ 12, /*->9816*/
+/* 9804*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9806*/ OPC_EmitConvertToTarget, 1,
+/* 9808*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ORI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9816*/ /*Scope*/ 10, /*->9827*/
+/* 9817*/ OPC_EmitConvertToTarget, 1,
+/* 9819*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ORI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 9827*/ 0, /*End of Scope*/
+/* 9828*/ /*SwitchType*/ 12, MVT::i64,// ->9842
+/* 9830*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9832*/ OPC_EmitConvertToTarget, 1,
+/* 9834*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ORI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 9842*/ 0, // EndSwitchType
+/* 9843*/ /*Scope*/ 24, /*->9868*/
+/* 9844*/ OPC_CheckType, MVT::i32,
+/* 9846*/ OPC_Scope, 10, /*->9858*/ // 2 children in Scope
+/* 9848*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 9850*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::OR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 9858*/ /*Scope*/ 8, /*->9867*/
+/* 9859*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::OR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 9867*/ 0, /*End of Scope*/
+/* 9868*/ /*Scope*/ 12, /*->9881*/
+/* 9869*/ OPC_CheckType, MVT::i64,
+/* 9871*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9873*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::OR), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (OR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 9881*/ 0, /*End of Scope*/
+/* 9882*/ /*SwitchOpcode*/ 8|128,3/*392*/, TARGET_VAL(ISD::SIGN_EXTEND_INREG),// ->10278
+/* 9886*/ OPC_Scope, 113|128,2/*369*/, /*->10258*/ // 2 children in Scope
+/* 9889*/ OPC_MoveChild0,
+/* 9890*/ OPC_Scope, 34, /*->9926*/ // 9 children in Scope
+/* 9892*/ OPC_CheckOpcode, TARGET_VAL(ISD::SREM),
+/* 9895*/ OPC_MoveChild0,
+/* 9896*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertSext),
+/* 9899*/ OPC_RecordChild0, // #0 = $rs1
+/* 9900*/ OPC_CheckPredicate, 0, // Predicate_assertsexti32
+/* 9902*/ OPC_MoveParent,
+/* 9903*/ OPC_MoveChild1,
+/* 9904*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertSext),
+/* 9907*/ OPC_RecordChild0, // #1 = $rs2
+/* 9908*/ OPC_CheckPredicate, 0, // Predicate_assertsexti32
+/* 9910*/ OPC_MoveParent,
+/* 9911*/ OPC_MoveParent,
+/* 9912*/ OPC_MoveChild1,
+/* 9913*/ OPC_CheckValueType, MVT::i32,
+/* 9915*/ OPC_MoveParent,
+/* 9916*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9918*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (srem:{ *:[i64] } (assertsext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertsexti32>>, (assertsext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertsexti32>>), i32:{ *:[Other] }) - Complexity = 14
+ // Dst: (REMW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 9926*/ /*Scope*/ 32, /*->9959*/
+/* 9927*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 9933*/ OPC_MoveChild0,
+/* 9934*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_TO_UINT),
+/* 9937*/ OPC_RecordChild0, // #0 = $rs1
+/* 9938*/ OPC_CheckChild0Type, MVT::f64,
+/* 9940*/ OPC_MoveParent,
+/* 9941*/ OPC_MoveParent,
+/* 9942*/ OPC_MoveChild1,
+/* 9943*/ OPC_CheckValueType, MVT::i32,
+/* 9945*/ OPC_MoveParent,
+/* 9946*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9948*/ OPC_EmitInteger, MVT::i64, 1,
+/* 9951*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (and:{ *:[i64] } (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1), 4294967295:{ *:[i64] }), i32:{ *:[Other] }) - Complexity = 14
+ // Dst: (FCVT_WU_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+/* 9959*/ /*Scope*/ 96, /*->10056*/
+/* 9960*/ OPC_CheckOpcode, TARGET_VAL(ISD::SREM),
+/* 9963*/ OPC_MoveChild0,
+/* 9964*/ OPC_SwitchOpcode /*2 cases */, 55, TARGET_VAL(ISD::SIGN_EXTEND_INREG),// ->10023
+/* 9968*/ OPC_RecordChild0, // #0 = $rs1
+/* 9969*/ OPC_MoveChild1,
+/* 9970*/ OPC_CheckValueType, MVT::i32,
+/* 9972*/ OPC_MoveParent,
+/* 9973*/ OPC_MoveParent,
+/* 9974*/ OPC_MoveChild1,
+/* 9975*/ OPC_SwitchOpcode /*2 cases */, 19, TARGET_VAL(ISD::AssertSext),// ->9998
+/* 9979*/ OPC_RecordChild0, // #1 = $rs2
+/* 9980*/ OPC_CheckPredicate, 0, // Predicate_assertsexti32
+/* 9982*/ OPC_MoveParent,
+/* 9983*/ OPC_MoveParent,
+/* 9984*/ OPC_MoveChild1,
+/* 9985*/ OPC_CheckValueType, MVT::i32,
+/* 9987*/ OPC_MoveParent,
+/* 9988*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 9990*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (srem:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs1, i32:{ *:[Other] }), (assertsext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertsexti32>>), i32:{ *:[Other] }) - Complexity = 13
+ // Dst: (REMW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 9998*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::SIGN_EXTEND_INREG),// ->10022
+/* 10001*/ OPC_RecordChild0, // #1 = $rs2
+/* 10002*/ OPC_MoveChild1,
+/* 10003*/ OPC_CheckValueType, MVT::i32,
+/* 10005*/ OPC_MoveParent,
+/* 10006*/ OPC_MoveParent,
+/* 10007*/ OPC_MoveParent,
+/* 10008*/ OPC_MoveChild1,
+/* 10009*/ OPC_CheckValueType, MVT::i32,
+/* 10011*/ OPC_MoveParent,
+/* 10012*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10014*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (srem:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs1, i32:{ *:[Other] }), (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs2, i32:{ *:[Other] })), i32:{ *:[Other] }) - Complexity = 12
+ // Dst: (REMW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10022*/ 0, // EndSwitchOpcode
+/* 10023*/ /*SwitchOpcode*/ 29, TARGET_VAL(ISD::AssertSext),// ->10055
+/* 10026*/ OPC_RecordChild0, // #0 = $rs1
+/* 10027*/ OPC_CheckPredicate, 0, // Predicate_assertsexti32
+/* 10029*/ OPC_MoveParent,
+/* 10030*/ OPC_MoveChild1,
+/* 10031*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND_INREG),
+/* 10034*/ OPC_RecordChild0, // #1 = $rs2
+/* 10035*/ OPC_MoveChild1,
+/* 10036*/ OPC_CheckValueType, MVT::i32,
+/* 10038*/ OPC_MoveParent,
+/* 10039*/ OPC_MoveParent,
+/* 10040*/ OPC_MoveParent,
+/* 10041*/ OPC_MoveChild1,
+/* 10042*/ OPC_CheckValueType, MVT::i32,
+/* 10044*/ OPC_MoveParent,
+/* 10045*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10047*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (srem:{ *:[i64] } (assertsext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertsexti32>>, (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs2, i32:{ *:[Other] })), i32:{ *:[Other] }) - Complexity = 13
+ // Dst: (REMW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10055*/ 0, // EndSwitchOpcode
+/* 10056*/ /*Scope*/ 48, /*->10105*/
+/* 10057*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+/* 10060*/ OPC_RecordChild0, // #0 = $rs1
+/* 10061*/ OPC_RecordChild1, // #1 = $imm12
+/* 10062*/ OPC_Scope, 24, /*->10088*/ // 2 children in Scope
+/* 10064*/ OPC_MoveChild1,
+/* 10065*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 10068*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 10070*/ OPC_MoveParent,
+/* 10071*/ OPC_MoveParent,
+/* 10072*/ OPC_MoveChild1,
+/* 10073*/ OPC_CheckValueType, MVT::i32,
+/* 10075*/ OPC_MoveParent,
+/* 10076*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10078*/ OPC_EmitConvertToTarget, 1,
+/* 10080*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDIW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (sext_inreg:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), i32:{ *:[Other] }) - Complexity = 10
+ // Dst: (ADDIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 10088*/ /*Scope*/ 15, /*->10104*/
+/* 10089*/ OPC_MoveParent,
+/* 10090*/ OPC_MoveChild1,
+/* 10091*/ OPC_CheckValueType, MVT::i32,
+/* 10093*/ OPC_MoveParent,
+/* 10094*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10096*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), i32:{ *:[Other] }) - Complexity = 6
+ // Dst: (ADDW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10104*/ 0, /*End of Scope*/
+/* 10105*/ /*Scope*/ 31, /*->10137*/
+/* 10106*/ OPC_CheckOpcode, TARGET_VAL(ISD::SHL),
+/* 10109*/ OPC_RecordChild0, // #0 = $rs1
+/* 10110*/ OPC_RecordChild1, // #1 = $shamt
+/* 10111*/ OPC_MoveChild1,
+/* 10112*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 10115*/ OPC_CheckPredicate, 15, // Predicate_uimm5
+/* 10117*/ OPC_CheckType, MVT::i64,
+/* 10119*/ OPC_MoveParent,
+/* 10120*/ OPC_MoveParent,
+/* 10121*/ OPC_MoveChild1,
+/* 10122*/ OPC_CheckValueType, MVT::i32,
+/* 10124*/ OPC_MoveParent,
+/* 10125*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10127*/ OPC_EmitConvertToTarget, 1,
+/* 10129*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLLIW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (sext_inreg:{ *:[i64] } (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt), i32:{ *:[Other] }) - Complexity = 10
+ // Dst: (SLLIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt)
+/* 10137*/ /*Scope*/ 58, /*->10196*/
+/* 10138*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 10141*/ OPC_MoveChild0,
+/* 10142*/ OPC_CheckOpcode, TARGET_VAL(ISD::FP_TO_UINT),
+/* 10145*/ OPC_RecordChild0, // #0 = $rs1
+/* 10146*/ OPC_Scope, 23, /*->10171*/ // 2 children in Scope
+/* 10148*/ OPC_CheckChild0Type, MVT::f32,
+/* 10150*/ OPC_MoveParent,
+/* 10151*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 10153*/ OPC_MoveParent,
+/* 10154*/ OPC_MoveChild1,
+/* 10155*/ OPC_CheckValueType, MVT::i32,
+/* 10157*/ OPC_MoveParent,
+/* 10158*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10160*/ OPC_EmitInteger, MVT::i64, 1,
+/* 10163*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (assertzext:{ *:[i64] } (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1))<<P:Predicate_assertzexti32>>, i32:{ *:[Other] }) - Complexity = 10
+ // Dst: (FCVT_WU_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] })
+/* 10171*/ /*Scope*/ 23, /*->10195*/
+/* 10172*/ OPC_CheckChild0Type, MVT::f64,
+/* 10174*/ OPC_MoveParent,
+/* 10175*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 10177*/ OPC_MoveParent,
+/* 10178*/ OPC_MoveChild1,
+/* 10179*/ OPC_CheckValueType, MVT::i32,
+/* 10181*/ OPC_MoveParent,
+/* 10182*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10184*/ OPC_EmitInteger, MVT::i64, 1,
+/* 10187*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (assertzext:{ *:[i64] } (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1))<<P:Predicate_assertzexti32>>, i32:{ *:[Other] }) - Complexity = 10
+ // Dst: (FCVT_WU_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+/* 10195*/ 0, /*End of Scope*/
+/* 10196*/ /*Scope*/ 20, /*->10217*/
+/* 10197*/ OPC_CheckOpcode, TARGET_VAL(ISD::SUB),
+/* 10200*/ OPC_RecordChild0, // #0 = $rs1
+/* 10201*/ OPC_RecordChild1, // #1 = $rs2
+/* 10202*/ OPC_MoveParent,
+/* 10203*/ OPC_MoveChild1,
+/* 10204*/ OPC_CheckValueType, MVT::i32,
+/* 10206*/ OPC_MoveParent,
+/* 10207*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10209*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SUBW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), i32:{ *:[Other] }) - Complexity = 6
+ // Dst: (SUBW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10217*/ /*Scope*/ 20, /*->10238*/
+/* 10218*/ OPC_CheckOpcode, TARGET_VAL(ISD::MUL),
+/* 10221*/ OPC_RecordChild0, // #0 = $rs1
+/* 10222*/ OPC_RecordChild1, // #1 = $rs2
+/* 10223*/ OPC_MoveParent,
+/* 10224*/ OPC_MoveChild1,
+/* 10225*/ OPC_CheckValueType, MVT::i32,
+/* 10227*/ OPC_MoveParent,
+/* 10228*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10230*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MULW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), i32:{ *:[Other] }) - Complexity = 6
+ // Dst: (MULW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10238*/ /*Scope*/ 18, /*->10257*/
+/* 10239*/ OPC_CheckOpcode, TARGET_VAL(RISCVISD::FMV_X_ANYEXTW_RV64),
+/* 10242*/ OPC_RecordChild0, // #0 = $src
+/* 10243*/ OPC_MoveParent,
+/* 10244*/ OPC_MoveChild1,
+/* 10245*/ OPC_CheckValueType, MVT::i32,
+/* 10247*/ OPC_MoveParent,
+/* 10248*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10250*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_W), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (sext_inreg:{ *:[i64] } (riscv_fmv_x_anyextw_rv64:{ *:[i64] } FPR32:{ *:[f32] }:$src), i32:{ *:[Other] }) - Complexity = 6
+ // Dst: (FMV_X_W:{ *:[i64] } FPR32:{ *:[f32] }:$src)
+/* 10257*/ 0, /*End of Scope*/
+/* 10258*/ /*Scope*/ 18, /*->10277*/
+/* 10259*/ OPC_RecordChild0, // #0 = $rs1
+/* 10260*/ OPC_MoveChild1,
+/* 10261*/ OPC_CheckValueType, MVT::i32,
+/* 10263*/ OPC_MoveParent,
+/* 10264*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10266*/ OPC_EmitInteger, MVT::i64, 0,
+/* 10269*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDIW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs1, i32:{ *:[Other] }) - Complexity = 3
+ // Dst: (ADDIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 10277*/ 0, /*End of Scope*/
+/* 10278*/ /*SwitchOpcode*/ 124, TARGET_VAL(ISD::ADD),// ->10405
+/* 10281*/ OPC_RecordChild0, // #0 = $Rs
+/* 10282*/ OPC_RecordChild1, // #1 = $imm12
+/* 10283*/ OPC_Scope, 81, /*->10366*/ // 3 children in Scope
+/* 10285*/ OPC_MoveChild1,
+/* 10286*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 10289*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 10291*/ OPC_MoveParent,
+/* 10292*/ OPC_SwitchType /*2 cases */, 56, MVT::i32,// ->10351
+/* 10295*/ OPC_Scope, 15, /*->10312*/ // 4 children in Scope
+/* 10297*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10299*/ OPC_CheckComplexPat, /*CP*/0, /*#*/0, // SelectAddrFI:$Rs #2
+/* 10302*/ OPC_EmitConvertToTarget, 1,
+/* 10304*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (add:{ *:[i32] } AddrFI:{ *:[i32] }:$Rs, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 13
+ // Dst: (ADDI:{ *:[i32] } AddrFI:{ *:[i32] }:$Rs, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 10312*/ /*Scope*/ 13, /*->10326*/
+/* 10313*/ OPC_CheckComplexPat, /*CP*/0, /*#*/0, // SelectAddrFI:$Rs #2
+/* 10316*/ OPC_EmitConvertToTarget, 1,
+/* 10318*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (add:{ *:[i32] } AddrFI:{ *:[i32] }:$Rs, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 13
+ // Dst: (ADDI:{ *:[i32] } AddrFI:{ *:[i32] }:$Rs, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 10326*/ /*Scope*/ 12, /*->10339*/
+/* 10327*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10329*/ OPC_EmitConvertToTarget, 1,
+/* 10331*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 10339*/ /*Scope*/ 10, /*->10350*/
+/* 10340*/ OPC_EmitConvertToTarget, 1,
+/* 10342*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 10350*/ 0, /*End of Scope*/
+/* 10351*/ /*SwitchType*/ 12, MVT::i64,// ->10365
+/* 10353*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10355*/ OPC_EmitConvertToTarget, 1,
+/* 10357*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (ADDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 10365*/ 0, // EndSwitchType
+/* 10366*/ /*Scope*/ 24, /*->10391*/
+/* 10367*/ OPC_CheckType, MVT::i32,
+/* 10369*/ OPC_Scope, 10, /*->10381*/ // 2 children in Scope
+/* 10371*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10373*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADD), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 10381*/ /*Scope*/ 8, /*->10390*/
+/* 10382*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADD), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 10390*/ 0, /*End of Scope*/
+/* 10391*/ /*Scope*/ 12, /*->10404*/
+/* 10392*/ OPC_CheckType, MVT::i64,
+/* 10394*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10396*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADD), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10404*/ 0, /*End of Scope*/
+/* 10405*/ /*SwitchOpcode*/ 7|128,2/*263*/, TARGET_VAL(ISD::ATOMIC_FENCE),// ->10672
+/* 10409*/ OPC_RecordNode, // #0 = 'atomic_fence' chained node
+/* 10410*/ OPC_Scope, 70, /*->10482*/ // 4 children in Scope
+/* 10412*/ OPC_CheckChild1Integer, 4,
+/* 10414*/ OPC_Scope, 41, /*->10457*/ // 2 children in Scope
+/* 10416*/ OPC_CheckChild1Type, MVT::i32,
+/* 10418*/ OPC_MoveChild2,
+/* 10419*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10422*/ OPC_MoveParent,
+/* 10423*/ OPC_Scope, 16, /*->10441*/ // 2 children in Scope
+/* 10425*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10427*/ OPC_EmitMergeInputChains1_0,
+/* 10428*/ OPC_EmitInteger, MVT::i32, 2,
+/* 10431*/ OPC_EmitInteger, MVT::i32, 3,
+/* 10434*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 4:{ *:[i32] }, (timm:{ *:[i32] })) - Complexity = 11
+ // Dst: (FENCE 2:{ *:[i32] }, 3:{ *:[i32] })
+/* 10441*/ /*Scope*/ 14, /*->10456*/
+/* 10442*/ OPC_EmitMergeInputChains1_0,
+/* 10443*/ OPC_EmitInteger, MVT::i32, 2,
+/* 10446*/ OPC_EmitInteger, MVT::i32, 3,
+/* 10449*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 4:{ *:[i32] }, (timm:{ *:[i32] })) - Complexity = 11
+ // Dst: (FENCE 2:{ *:[i32] }, 3:{ *:[i32] })
+/* 10456*/ 0, /*End of Scope*/
+/* 10457*/ /*Scope*/ 23, /*->10481*/
+/* 10458*/ OPC_CheckChild1Type, MVT::i64,
+/* 10460*/ OPC_MoveChild2,
+/* 10461*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10464*/ OPC_MoveParent,
+/* 10465*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10467*/ OPC_EmitMergeInputChains1_0,
+/* 10468*/ OPC_EmitInteger, MVT::i64, 2,
+/* 10471*/ OPC_EmitInteger, MVT::i64, 3,
+/* 10474*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] })) - Complexity = 11
+ // Dst: (FENCE 2:{ *:[i64] }, 3:{ *:[i64] })
+/* 10481*/ 0, /*End of Scope*/
+/* 10482*/ /*Scope*/ 70, /*->10553*/
+/* 10483*/ OPC_CheckChild1Integer, 5,
+/* 10485*/ OPC_Scope, 41, /*->10528*/ // 2 children in Scope
+/* 10487*/ OPC_CheckChild1Type, MVT::i32,
+/* 10489*/ OPC_MoveChild2,
+/* 10490*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10493*/ OPC_MoveParent,
+/* 10494*/ OPC_Scope, 16, /*->10512*/ // 2 children in Scope
+/* 10496*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10498*/ OPC_EmitMergeInputChains1_0,
+/* 10499*/ OPC_EmitInteger, MVT::i32, 3,
+/* 10502*/ OPC_EmitInteger, MVT::i32, 1,
+/* 10505*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 5:{ *:[i32] }, (timm:{ *:[i32] })) - Complexity = 11
+ // Dst: (FENCE 3:{ *:[i32] }, 1:{ *:[i32] })
+/* 10512*/ /*Scope*/ 14, /*->10527*/
+/* 10513*/ OPC_EmitMergeInputChains1_0,
+/* 10514*/ OPC_EmitInteger, MVT::i32, 3,
+/* 10517*/ OPC_EmitInteger, MVT::i32, 1,
+/* 10520*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 5:{ *:[i32] }, (timm:{ *:[i32] })) - Complexity = 11
+ // Dst: (FENCE 3:{ *:[i32] }, 1:{ *:[i32] })
+/* 10527*/ 0, /*End of Scope*/
+/* 10528*/ /*Scope*/ 23, /*->10552*/
+/* 10529*/ OPC_CheckChild1Type, MVT::i64,
+/* 10531*/ OPC_MoveChild2,
+/* 10532*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10535*/ OPC_MoveParent,
+/* 10536*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10538*/ OPC_EmitMergeInputChains1_0,
+/* 10539*/ OPC_EmitInteger, MVT::i64, 3,
+/* 10542*/ OPC_EmitInteger, MVT::i64, 1,
+/* 10545*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 5:{ *:[i64] }, (timm:{ *:[i64] })) - Complexity = 11
+ // Dst: (FENCE 3:{ *:[i64] }, 1:{ *:[i64] })
+/* 10552*/ 0, /*End of Scope*/
+/* 10553*/ /*Scope*/ 46, /*->10600*/
+/* 10554*/ OPC_CheckChild1Integer, 6,
+/* 10556*/ OPC_Scope, 25, /*->10583*/ // 2 children in Scope
+/* 10558*/ OPC_CheckChild1Type, MVT::i32,
+/* 10560*/ OPC_MoveChild2,
+/* 10561*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10564*/ OPC_MoveParent,
+/* 10565*/ OPC_Scope, 8, /*->10575*/ // 2 children in Scope
+/* 10567*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10569*/ OPC_EmitMergeInputChains1_0,
+/* 10570*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE_TSO), 0|OPFL_Chain,
+ 0/*#Ops*/,
+ // Src: (atomic_fence 6:{ *:[i32] }, (timm:{ *:[i32] })) - Complexity = 11
+ // Dst: (FENCE_TSO)
+/* 10575*/ /*Scope*/ 6, /*->10582*/
+/* 10576*/ OPC_EmitMergeInputChains1_0,
+/* 10577*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE_TSO), 0|OPFL_Chain,
+ 0/*#Ops*/,
+ // Src: (atomic_fence 6:{ *:[i32] }, (timm:{ *:[i32] })) - Complexity = 11
+ // Dst: (FENCE_TSO)
+/* 10582*/ 0, /*End of Scope*/
+/* 10583*/ /*Scope*/ 15, /*->10599*/
+/* 10584*/ OPC_CheckChild1Type, MVT::i64,
+/* 10586*/ OPC_MoveChild2,
+/* 10587*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10590*/ OPC_MoveParent,
+/* 10591*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10593*/ OPC_EmitMergeInputChains1_0,
+/* 10594*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE_TSO), 0|OPFL_Chain,
+ 0/*#Ops*/,
+ // Src: (atomic_fence 6:{ *:[i64] }, (timm:{ *:[i64] })) - Complexity = 11
+ // Dst: (FENCE_TSO)
+/* 10599*/ 0, /*End of Scope*/
+/* 10600*/ /*Scope*/ 70, /*->10671*/
+/* 10601*/ OPC_CheckChild1Integer, 7,
+/* 10603*/ OPC_Scope, 41, /*->10646*/ // 2 children in Scope
+/* 10605*/ OPC_CheckChild1Type, MVT::i32,
+/* 10607*/ OPC_MoveChild2,
+/* 10608*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10611*/ OPC_MoveParent,
+/* 10612*/ OPC_Scope, 16, /*->10630*/ // 2 children in Scope
+/* 10614*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10616*/ OPC_EmitMergeInputChains1_0,
+/* 10617*/ OPC_EmitInteger, MVT::i32, 3,
+/* 10620*/ OPC_EmitInteger, MVT::i32, 3,
+/* 10623*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) - Complexity = 11
+ // Dst: (FENCE 3:{ *:[i32] }, 3:{ *:[i32] })
+/* 10630*/ /*Scope*/ 14, /*->10645*/
+/* 10631*/ OPC_EmitMergeInputChains1_0,
+/* 10632*/ OPC_EmitInteger, MVT::i32, 3,
+/* 10635*/ OPC_EmitInteger, MVT::i32, 3,
+/* 10638*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) - Complexity = 11
+ // Dst: (FENCE 3:{ *:[i32] }, 3:{ *:[i32] })
+/* 10645*/ 0, /*End of Scope*/
+/* 10646*/ /*Scope*/ 23, /*->10670*/
+/* 10647*/ OPC_CheckChild1Type, MVT::i64,
+/* 10649*/ OPC_MoveChild2,
+/* 10650*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10653*/ OPC_MoveParent,
+/* 10654*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10656*/ OPC_EmitMergeInputChains1_0,
+/* 10657*/ OPC_EmitInteger, MVT::i64, 3,
+/* 10660*/ OPC_EmitInteger, MVT::i64, 3,
+/* 10663*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::FENCE), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] })) - Complexity = 11
+ // Dst: (FENCE 3:{ *:[i64] }, 3:{ *:[i64] })
+/* 10670*/ 0, /*End of Scope*/
+/* 10671*/ 0, /*End of Scope*/
+/* 10672*/ /*SwitchOpcode*/ 17|128,1/*145*/, TARGET_VAL(ISD::SREM),// ->10821
+/* 10676*/ OPC_Scope, 99, /*->10777*/ // 2 children in Scope
+/* 10678*/ OPC_MoveChild0,
+/* 10679*/ OPC_SwitchOpcode /*2 cases */, 45, TARGET_VAL(ISD::AssertSext),// ->10728
+/* 10683*/ OPC_RecordChild0, // #0 = $rs1
+/* 10684*/ OPC_CheckPredicate, 0, // Predicate_assertsexti32
+/* 10686*/ OPC_MoveParent,
+/* 10687*/ OPC_MoveChild1,
+/* 10688*/ OPC_SwitchOpcode /*2 cases */, 16, TARGET_VAL(ISD::AssertSext),// ->10708
+/* 10692*/ OPC_RecordChild0, // #1 = $rs2
+/* 10693*/ OPC_CheckPredicate, 0, // Predicate_assertsexti32
+/* 10695*/ OPC_MoveParent,
+/* 10696*/ OPC_CheckType, MVT::i64,
+/* 10698*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10700*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i64] } (assertsext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertsexti32>>, (assertsext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertsexti32>>) - Complexity = 11
+ // Dst: (REMW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10708*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::SIGN_EXTEND_INREG),// ->10727
+/* 10711*/ OPC_RecordChild0, // #1 = $rs2
+/* 10712*/ OPC_MoveChild1,
+/* 10713*/ OPC_CheckValueType, MVT::i32,
+/* 10715*/ OPC_MoveParent,
+/* 10716*/ OPC_MoveParent,
+/* 10717*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10719*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i64] } (assertsext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertsexti32>>, (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs2, i32:{ *:[Other] })) - Complexity = 10
+ // Dst: (REMW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10727*/ 0, // EndSwitchOpcode
+/* 10728*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::SIGN_EXTEND_INREG),// ->10776
+/* 10731*/ OPC_RecordChild0, // #0 = $rs1
+/* 10732*/ OPC_MoveChild1,
+/* 10733*/ OPC_CheckValueType, MVT::i32,
+/* 10735*/ OPC_MoveParent,
+/* 10736*/ OPC_MoveParent,
+/* 10737*/ OPC_MoveChild1,
+/* 10738*/ OPC_SwitchOpcode /*2 cases */, 14, TARGET_VAL(ISD::AssertSext),// ->10756
+/* 10742*/ OPC_RecordChild0, // #1 = $rs2
+/* 10743*/ OPC_CheckPredicate, 0, // Predicate_assertsexti32
+/* 10745*/ OPC_MoveParent,
+/* 10746*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10748*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs1, i32:{ *:[Other] }), (assertsext:{ *:[i64] } GPR:{ *:[i64] }:$rs2)<<P:Predicate_assertsexti32>>) - Complexity = 10
+ // Dst: (REMW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10756*/ /*SwitchOpcode*/ 16, TARGET_VAL(ISD::SIGN_EXTEND_INREG),// ->10775
+/* 10759*/ OPC_RecordChild0, // #1 = $rs2
+/* 10760*/ OPC_MoveChild1,
+/* 10761*/ OPC_CheckValueType, MVT::i32,
+/* 10763*/ OPC_MoveParent,
+/* 10764*/ OPC_MoveParent,
+/* 10765*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10767*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs1, i32:{ *:[Other] }), (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs2, i32:{ *:[Other] })) - Complexity = 9
+ // Dst: (REMW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10775*/ 0, // EndSwitchOpcode
+/* 10776*/ 0, // EndSwitchOpcode
+/* 10777*/ /*Scope*/ 42, /*->10820*/
+/* 10778*/ OPC_RecordChild0, // #0 = $rs1
+/* 10779*/ OPC_RecordChild1, // #1 = $rs2
+/* 10780*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->10807
+/* 10783*/ OPC_Scope, 10, /*->10795*/ // 2 children in Scope
+/* 10785*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10787*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 10795*/ /*Scope*/ 10, /*->10806*/
+/* 10796*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasStdExtM())
+/* 10798*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REM), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 10806*/ 0, /*End of Scope*/
+/* 10807*/ /*SwitchType*/ 10, MVT::i64,// ->10819
+/* 10809*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 10811*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REM), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (REM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 10819*/ 0, // EndSwitchType
+/* 10820*/ 0, /*End of Scope*/
+/* 10821*/ /*SwitchOpcode*/ 12|128,6/*780*/, TARGET_VAL(ISD::INTRINSIC_W_CHAIN),// ->11605
+/* 10825*/ OPC_RecordNode, // #0 = 'intrinsic_w_chain' chained node
+/* 10826*/ OPC_Scope, 50, /*->10878*/ // 18 children in Scope
+/* 10828*/ OPC_CheckChild1Integer, 37|128,47/*6053*/,
+/* 10831*/ OPC_RecordChild2, // #1 = $addr
+/* 10832*/ OPC_CheckChild2Type, MVT::i32,
+/* 10834*/ OPC_RecordChild3, // #2 = $incr
+/* 10835*/ OPC_RecordChild4, // #3 = $mask
+/* 10836*/ OPC_RecordChild5, // #4 = $ordering
+/* 10837*/ OPC_MoveChild5,
+/* 10838*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10841*/ OPC_MoveParent,
+/* 10842*/ OPC_Scope, 16, /*->10860*/ // 2 children in Scope
+/* 10844*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10846*/ OPC_EmitMergeInputChains1_0,
+/* 10847*/ OPC_EmitConvertToTarget, 4,
+/* 10849*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicSwap32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6053:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicSwap32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 10860*/ /*Scope*/ 16, /*->10877*/
+/* 10861*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 10863*/ OPC_EmitMergeInputChains1_0,
+/* 10864*/ OPC_EmitConvertToTarget, 4,
+/* 10866*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicSwap32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6053:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicSwap32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 10877*/ 0, /*End of Scope*/
+/* 10878*/ /*Scope*/ 50, /*->10929*/
+/* 10879*/ OPC_CheckChild1Integer, 23|128,47/*6039*/,
+/* 10882*/ OPC_RecordChild2, // #1 = $addr
+/* 10883*/ OPC_CheckChild2Type, MVT::i32,
+/* 10885*/ OPC_RecordChild3, // #2 = $incr
+/* 10886*/ OPC_RecordChild4, // #3 = $mask
+/* 10887*/ OPC_RecordChild5, // #4 = $ordering
+/* 10888*/ OPC_MoveChild5,
+/* 10889*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10892*/ OPC_MoveParent,
+/* 10893*/ OPC_Scope, 16, /*->10911*/ // 2 children in Scope
+/* 10895*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10897*/ OPC_EmitMergeInputChains1_0,
+/* 10898*/ OPC_EmitConvertToTarget, 4,
+/* 10900*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadAdd32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6039:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadAdd32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 10911*/ /*Scope*/ 16, /*->10928*/
+/* 10912*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 10914*/ OPC_EmitMergeInputChains1_0,
+/* 10915*/ OPC_EmitConvertToTarget, 4,
+/* 10917*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadAdd32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6039:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadAdd32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 10928*/ 0, /*End of Scope*/
+/* 10929*/ /*Scope*/ 50, /*->10980*/
+/* 10930*/ OPC_CheckChild1Integer, 31|128,47/*6047*/,
+/* 10933*/ OPC_RecordChild2, // #1 = $addr
+/* 10934*/ OPC_CheckChild2Type, MVT::i32,
+/* 10936*/ OPC_RecordChild3, // #2 = $incr
+/* 10937*/ OPC_RecordChild4, // #3 = $mask
+/* 10938*/ OPC_RecordChild5, // #4 = $ordering
+/* 10939*/ OPC_MoveChild5,
+/* 10940*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10943*/ OPC_MoveParent,
+/* 10944*/ OPC_Scope, 16, /*->10962*/ // 2 children in Scope
+/* 10946*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10948*/ OPC_EmitMergeInputChains1_0,
+/* 10949*/ OPC_EmitConvertToTarget, 4,
+/* 10951*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadSub32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6047:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadSub32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 10962*/ /*Scope*/ 16, /*->10979*/
+/* 10963*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 10965*/ OPC_EmitMergeInputChains1_0,
+/* 10966*/ OPC_EmitConvertToTarget, 4,
+/* 10968*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadSub32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6047:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadSub32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 10979*/ 0, /*End of Scope*/
+/* 10980*/ /*Scope*/ 50, /*->11031*/
+/* 10981*/ OPC_CheckChild1Integer, 29|128,47/*6045*/,
+/* 10984*/ OPC_RecordChild2, // #1 = $addr
+/* 10985*/ OPC_CheckChild2Type, MVT::i32,
+/* 10987*/ OPC_RecordChild3, // #2 = $incr
+/* 10988*/ OPC_RecordChild4, // #3 = $mask
+/* 10989*/ OPC_RecordChild5, // #4 = $ordering
+/* 10990*/ OPC_MoveChild5,
+/* 10991*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 10994*/ OPC_MoveParent,
+/* 10995*/ OPC_Scope, 16, /*->11013*/ // 2 children in Scope
+/* 10997*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 10999*/ OPC_EmitMergeInputChains1_0,
+/* 11000*/ OPC_EmitConvertToTarget, 4,
+/* 11002*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadNand32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6045:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 11013*/ /*Scope*/ 16, /*->11030*/
+/* 11014*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 11016*/ OPC_EmitMergeInputChains1_0,
+/* 11017*/ OPC_EmitConvertToTarget, 4,
+/* 11019*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadNand32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6045:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 11030*/ 0, /*End of Scope*/
+/* 11031*/ /*Scope*/ 57, /*->11089*/
+/* 11032*/ OPC_CheckChild1Integer, 25|128,47/*6041*/,
+/* 11035*/ OPC_RecordChild2, // #1 = $addr
+/* 11036*/ OPC_CheckChild2Type, MVT::i32,
+/* 11038*/ OPC_RecordChild3, // #2 = $incr
+/* 11039*/ OPC_RecordChild4, // #3 = $mask
+/* 11040*/ OPC_RecordChild5, // #4 = $shiftamt
+/* 11041*/ OPC_RecordChild6, // #5 = $ordering
+/* 11042*/ OPC_MoveChild6,
+/* 11043*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11046*/ OPC_MoveParent,
+/* 11047*/ OPC_Scope, 19, /*->11068*/ // 2 children in Scope
+/* 11049*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11051*/ OPC_EmitMergeInputChains1_0,
+/* 11052*/ OPC_EmitConvertToTarget, 5,
+/* 11054*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadMax32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i32, MVT::i32, MVT::i32, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6041:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadMax32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (imm:{ *:[i32] }):$ordering)
+/* 11068*/ /*Scope*/ 19, /*->11088*/
+/* 11069*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 11071*/ OPC_EmitMergeInputChains1_0,
+/* 11072*/ OPC_EmitConvertToTarget, 5,
+/* 11074*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadMax32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i32, MVT::i32, MVT::i32, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6041:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadMax32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (imm:{ *:[i32] }):$ordering)
+/* 11088*/ 0, /*End of Scope*/
+/* 11089*/ /*Scope*/ 57, /*->11147*/
+/* 11090*/ OPC_CheckChild1Integer, 27|128,47/*6043*/,
+/* 11093*/ OPC_RecordChild2, // #1 = $addr
+/* 11094*/ OPC_CheckChild2Type, MVT::i32,
+/* 11096*/ OPC_RecordChild3, // #2 = $incr
+/* 11097*/ OPC_RecordChild4, // #3 = $mask
+/* 11098*/ OPC_RecordChild5, // #4 = $shiftamt
+/* 11099*/ OPC_RecordChild6, // #5 = $ordering
+/* 11100*/ OPC_MoveChild6,
+/* 11101*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11104*/ OPC_MoveParent,
+/* 11105*/ OPC_Scope, 19, /*->11126*/ // 2 children in Scope
+/* 11107*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11109*/ OPC_EmitMergeInputChains1_0,
+/* 11110*/ OPC_EmitConvertToTarget, 5,
+/* 11112*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadMin32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i32, MVT::i32, MVT::i32, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6043:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadMin32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (imm:{ *:[i32] }):$ordering)
+/* 11126*/ /*Scope*/ 19, /*->11146*/
+/* 11127*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 11129*/ OPC_EmitMergeInputChains1_0,
+/* 11130*/ OPC_EmitConvertToTarget, 5,
+/* 11132*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadMin32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i32, MVT::i32, MVT::i32, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6043:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadMin32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, GPR:{ *:[i32] }:$shiftamt, (imm:{ *:[i32] }):$ordering)
+/* 11146*/ 0, /*End of Scope*/
+/* 11147*/ /*Scope*/ 54, /*->11202*/
+/* 11148*/ OPC_CheckChild1Integer, 33|128,47/*6049*/,
+/* 11151*/ OPC_RecordChild2, // #1 = $addr
+/* 11152*/ OPC_CheckChild2Type, MVT::i32,
+/* 11154*/ OPC_RecordChild3, // #2 = $incr
+/* 11155*/ OPC_RecordChild4, // #3 = $mask
+/* 11156*/ OPC_RecordChild5, // #4 = $ordering
+/* 11157*/ OPC_MoveChild5,
+/* 11158*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11161*/ OPC_MoveParent,
+/* 11162*/ OPC_Scope, 18, /*->11182*/ // 2 children in Scope
+/* 11164*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11166*/ OPC_EmitMergeInputChains1_0,
+/* 11167*/ OPC_EmitConvertToTarget, 4,
+/* 11169*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadUMax32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i32, MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6049:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadUMax32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 11182*/ /*Scope*/ 18, /*->11201*/
+/* 11183*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 11185*/ OPC_EmitMergeInputChains1_0,
+/* 11186*/ OPC_EmitConvertToTarget, 4,
+/* 11188*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadUMax32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i32, MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6049:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadUMax32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 11201*/ 0, /*End of Scope*/
+/* 11202*/ /*Scope*/ 54, /*->11257*/
+/* 11203*/ OPC_CheckChild1Integer, 35|128,47/*6051*/,
+/* 11206*/ OPC_RecordChild2, // #1 = $addr
+/* 11207*/ OPC_CheckChild2Type, MVT::i32,
+/* 11209*/ OPC_RecordChild3, // #2 = $incr
+/* 11210*/ OPC_RecordChild4, // #3 = $mask
+/* 11211*/ OPC_RecordChild5, // #4 = $ordering
+/* 11212*/ OPC_MoveChild5,
+/* 11213*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11216*/ OPC_MoveParent,
+/* 11217*/ OPC_Scope, 18, /*->11237*/ // 2 children in Scope
+/* 11219*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11221*/ OPC_EmitMergeInputChains1_0,
+/* 11222*/ OPC_EmitConvertToTarget, 4,
+/* 11224*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadUMin32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i32, MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6051:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadUMin32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 11237*/ /*Scope*/ 18, /*->11256*/
+/* 11238*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 11240*/ OPC_EmitMergeInputChains1_0,
+/* 11241*/ OPC_EmitConvertToTarget, 4,
+/* 11243*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadUMin32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i32, MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6051:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadUMin32:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 11256*/ 0, /*End of Scope*/
+/* 11257*/ /*Scope*/ 53, /*->11311*/
+/* 11258*/ OPC_CheckChild1Integer, 39|128,47/*6055*/,
+/* 11261*/ OPC_RecordChild2, // #1 = $addr
+/* 11262*/ OPC_CheckChild2Type, MVT::i32,
+/* 11264*/ OPC_RecordChild3, // #2 = $cmpval
+/* 11265*/ OPC_RecordChild4, // #3 = $newval
+/* 11266*/ OPC_RecordChild5, // #4 = $mask
+/* 11267*/ OPC_RecordChild6, // #5 = $ordering
+/* 11268*/ OPC_MoveChild6,
+/* 11269*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11272*/ OPC_MoveParent,
+/* 11273*/ OPC_Scope, 17, /*->11292*/ // 2 children in Scope
+/* 11275*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11277*/ OPC_EmitMergeInputChains1_0,
+/* 11278*/ OPC_EmitConvertToTarget, 5,
+/* 11280*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedCmpXchg32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6055:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmpval, GPR:{ *:[i32] }:$newval, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmpval, GPR:{ *:[i32] }:$newval, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 11292*/ /*Scope*/ 17, /*->11310*/
+/* 11293*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 11295*/ OPC_EmitMergeInputChains1_0,
+/* 11296*/ OPC_EmitConvertToTarget, 5,
+/* 11298*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedCmpXchg32), 0|OPFL_Chain,
+ MVT::i32, MVT::i32, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i32] } 6055:{ *:[iPTR] }, GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmpval, GPR:{ *:[i32] }:$newval, GPR:{ *:[i32] }:$mask, (timm:{ *:[i32] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmpval, GPR:{ *:[i32] }:$newval, GPR:{ *:[i32] }:$mask, (imm:{ *:[i32] }):$ordering)
+/* 11310*/ 0, /*End of Scope*/
+/* 11311*/ /*Scope*/ 30, /*->11342*/
+/* 11312*/ OPC_CheckChild1Integer, 38|128,47/*6054*/,
+/* 11315*/ OPC_RecordChild2, // #1 = $addr
+/* 11316*/ OPC_CheckChild2Type, MVT::i64,
+/* 11318*/ OPC_RecordChild3, // #2 = $incr
+/* 11319*/ OPC_RecordChild4, // #3 = $mask
+/* 11320*/ OPC_RecordChild5, // #4 = $ordering
+/* 11321*/ OPC_MoveChild5,
+/* 11322*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11325*/ OPC_MoveParent,
+/* 11326*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11328*/ OPC_EmitMergeInputChains1_0,
+/* 11329*/ OPC_EmitConvertToTarget, 4,
+/* 11331*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicSwap32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6054:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicSwap32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (imm:{ *:[i64] }):$ordering)
+/* 11342*/ /*Scope*/ 30, /*->11373*/
+/* 11343*/ OPC_CheckChild1Integer, 24|128,47/*6040*/,
+/* 11346*/ OPC_RecordChild2, // #1 = $addr
+/* 11347*/ OPC_CheckChild2Type, MVT::i64,
+/* 11349*/ OPC_RecordChild3, // #2 = $incr
+/* 11350*/ OPC_RecordChild4, // #3 = $mask
+/* 11351*/ OPC_RecordChild5, // #4 = $ordering
+/* 11352*/ OPC_MoveChild5,
+/* 11353*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11356*/ OPC_MoveParent,
+/* 11357*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11359*/ OPC_EmitMergeInputChains1_0,
+/* 11360*/ OPC_EmitConvertToTarget, 4,
+/* 11362*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadAdd32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6040:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadAdd32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (imm:{ *:[i64] }):$ordering)
+/* 11373*/ /*Scope*/ 30, /*->11404*/
+/* 11374*/ OPC_CheckChild1Integer, 32|128,47/*6048*/,
+/* 11377*/ OPC_RecordChild2, // #1 = $addr
+/* 11378*/ OPC_CheckChild2Type, MVT::i64,
+/* 11380*/ OPC_RecordChild3, // #2 = $incr
+/* 11381*/ OPC_RecordChild4, // #3 = $mask
+/* 11382*/ OPC_RecordChild5, // #4 = $ordering
+/* 11383*/ OPC_MoveChild5,
+/* 11384*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11387*/ OPC_MoveParent,
+/* 11388*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11390*/ OPC_EmitMergeInputChains1_0,
+/* 11391*/ OPC_EmitConvertToTarget, 4,
+/* 11393*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadSub32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6048:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadSub32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (imm:{ *:[i64] }):$ordering)
+/* 11404*/ /*Scope*/ 30, /*->11435*/
+/* 11405*/ OPC_CheckChild1Integer, 30|128,47/*6046*/,
+/* 11408*/ OPC_RecordChild2, // #1 = $addr
+/* 11409*/ OPC_CheckChild2Type, MVT::i64,
+/* 11411*/ OPC_RecordChild3, // #2 = $incr
+/* 11412*/ OPC_RecordChild4, // #3 = $mask
+/* 11413*/ OPC_RecordChild5, // #4 = $ordering
+/* 11414*/ OPC_MoveChild5,
+/* 11415*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11418*/ OPC_MoveParent,
+/* 11419*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11421*/ OPC_EmitMergeInputChains1_0,
+/* 11422*/ OPC_EmitConvertToTarget, 4,
+/* 11424*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadNand32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6046:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (imm:{ *:[i64] }):$ordering)
+/* 11435*/ /*Scope*/ 34, /*->11470*/
+/* 11436*/ OPC_CheckChild1Integer, 26|128,47/*6042*/,
+/* 11439*/ OPC_RecordChild2, // #1 = $addr
+/* 11440*/ OPC_CheckChild2Type, MVT::i64,
+/* 11442*/ OPC_RecordChild3, // #2 = $incr
+/* 11443*/ OPC_RecordChild4, // #3 = $mask
+/* 11444*/ OPC_RecordChild5, // #4 = $shiftamt
+/* 11445*/ OPC_RecordChild6, // #5 = $ordering
+/* 11446*/ OPC_MoveChild6,
+/* 11447*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11450*/ OPC_MoveParent,
+/* 11451*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11453*/ OPC_EmitMergeInputChains1_0,
+/* 11454*/ OPC_EmitConvertToTarget, 5,
+/* 11456*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadMax32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i64, MVT::i64, MVT::i64, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6042:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, GPR:{ *:[i64] }:$shiftamt, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadMax32:{ *:[i64] }:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, GPR:{ *:[i64] }:$shiftamt, (imm:{ *:[i64] }):$ordering)
+/* 11470*/ /*Scope*/ 34, /*->11505*/
+/* 11471*/ OPC_CheckChild1Integer, 28|128,47/*6044*/,
+/* 11474*/ OPC_RecordChild2, // #1 = $addr
+/* 11475*/ OPC_CheckChild2Type, MVT::i64,
+/* 11477*/ OPC_RecordChild3, // #2 = $incr
+/* 11478*/ OPC_RecordChild4, // #3 = $mask
+/* 11479*/ OPC_RecordChild5, // #4 = $shiftamt
+/* 11480*/ OPC_RecordChild6, // #5 = $ordering
+/* 11481*/ OPC_MoveChild6,
+/* 11482*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11485*/ OPC_MoveParent,
+/* 11486*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11488*/ OPC_EmitMergeInputChains1_0,
+/* 11489*/ OPC_EmitConvertToTarget, 5,
+/* 11491*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadMin32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i64, MVT::i64, MVT::i64, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6044:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, GPR:{ *:[i64] }:$shiftamt, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadMin32:{ *:[i64] }:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, GPR:{ *:[i64] }:$shiftamt, (imm:{ *:[i64] }):$ordering)
+/* 11505*/ /*Scope*/ 32, /*->11538*/
+/* 11506*/ OPC_CheckChild1Integer, 34|128,47/*6050*/,
+/* 11509*/ OPC_RecordChild2, // #1 = $addr
+/* 11510*/ OPC_CheckChild2Type, MVT::i64,
+/* 11512*/ OPC_RecordChild3, // #2 = $incr
+/* 11513*/ OPC_RecordChild4, // #3 = $mask
+/* 11514*/ OPC_RecordChild5, // #4 = $ordering
+/* 11515*/ OPC_MoveChild5,
+/* 11516*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11519*/ OPC_MoveParent,
+/* 11520*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11522*/ OPC_EmitMergeInputChains1_0,
+/* 11523*/ OPC_EmitConvertToTarget, 4,
+/* 11525*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadUMax32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i64, MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6050:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadUMax32:{ *:[i64] }:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (imm:{ *:[i64] }):$ordering)
+/* 11538*/ /*Scope*/ 32, /*->11571*/
+/* 11539*/ OPC_CheckChild1Integer, 36|128,47/*6052*/,
+/* 11542*/ OPC_RecordChild2, // #1 = $addr
+/* 11543*/ OPC_CheckChild2Type, MVT::i64,
+/* 11545*/ OPC_RecordChild3, // #2 = $incr
+/* 11546*/ OPC_RecordChild4, // #3 = $mask
+/* 11547*/ OPC_RecordChild5, // #4 = $ordering
+/* 11548*/ OPC_MoveChild5,
+/* 11549*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11552*/ OPC_MoveParent,
+/* 11553*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11555*/ OPC_EmitMergeInputChains1_0,
+/* 11556*/ OPC_EmitConvertToTarget, 4,
+/* 11558*/ OPC_MorphNodeTo, TARGET_VAL(RISCV::PseudoMaskedAtomicLoadUMin32), 0|OPFL_Chain,
+ 3/*#VTs*/, MVT::i64, MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 5,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6052:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedAtomicLoadUMin32:{ *:[i64] }:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, GPR:{ *:[i64] }:$mask, (imm:{ *:[i64] }):$ordering)
+/* 11571*/ /*Scope*/ 32, /*->11604*/
+/* 11572*/ OPC_CheckChild1Integer, 40|128,47/*6056*/,
+/* 11575*/ OPC_RecordChild2, // #1 = $addr
+/* 11576*/ OPC_CheckChild2Type, MVT::i64,
+/* 11578*/ OPC_RecordChild3, // #2 = $cmpval
+/* 11579*/ OPC_RecordChild4, // #3 = $newval
+/* 11580*/ OPC_RecordChild5, // #4 = $mask
+/* 11581*/ OPC_RecordChild6, // #5 = $ordering
+/* 11582*/ OPC_MoveChild6,
+/* 11583*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 11586*/ OPC_MoveParent,
+/* 11587*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11589*/ OPC_EmitMergeInputChains1_0,
+/* 11590*/ OPC_EmitConvertToTarget, 5,
+/* 11592*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoMaskedCmpXchg32), 0|OPFL_Chain,
+ MVT::i64, MVT::i64, 5/*#Ops*/, 1, 2, 3, 4, 6,
+ // Src: (intrinsic_w_chain:{ *:[i64] } 6056:{ *:[iPTR] }, GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmpval, GPR:{ *:[i64] }:$newval, GPR:{ *:[i64] }:$mask, (timm:{ *:[i64] }):$ordering) - Complexity = 11
+ // Dst: (PseudoMaskedCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmpval, GPR:{ *:[i64] }:$newval, GPR:{ *:[i64] }:$mask, (imm:{ *:[i64] }):$ordering)
+/* 11604*/ 0, /*End of Scope*/
+/* 11605*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::SHL),// ->11772
+/* 11609*/ OPC_RecordChild0, // #0 = $rs1
+/* 11610*/ OPC_Scope, 56, /*->11668*/ // 2 children in Scope
+/* 11612*/ OPC_MoveChild1,
+/* 11613*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 11616*/ OPC_RecordChild0, // #1 = $rs2
+/* 11617*/ OPC_MoveChild1,
+/* 11618*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 11621*/ OPC_CheckPredicate, 16, // Predicate_immbottomxlenset
+/* 11623*/ OPC_MoveParent,
+/* 11624*/ OPC_SwitchType /*2 cases */, 25, MVT::i32,// ->11652
+/* 11627*/ OPC_MoveParent,
+/* 11628*/ OPC_CheckType, MVT::i32,
+/* 11630*/ OPC_Scope, 10, /*->11642*/ // 2 children in Scope
+/* 11632*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11634*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11642*/ /*Scope*/ 8, /*->11651*/
+/* 11643*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11651*/ 0, /*End of Scope*/
+/* 11652*/ /*SwitchType*/ 13, MVT::i64,// ->11667
+/* 11654*/ OPC_MoveParent,
+/* 11655*/ OPC_CheckType, MVT::i64,
+/* 11657*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11659*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLL), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SLL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 11667*/ 0, // EndSwitchType
+/* 11668*/ /*Scope*/ 102, /*->11771*/
+/* 11669*/ OPC_RecordChild1, // #1 = $shamt
+/* 11670*/ OPC_Scope, 56, /*->11728*/ // 3 children in Scope
+/* 11672*/ OPC_MoveChild1,
+/* 11673*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 11676*/ OPC_CheckPredicate, 17, // Predicate_uimmlog2xlen
+/* 11678*/ OPC_SwitchType /*2 cases */, 29, MVT::i32,// ->11710
+/* 11681*/ OPC_MoveParent,
+/* 11682*/ OPC_CheckType, MVT::i32,
+/* 11684*/ OPC_Scope, 12, /*->11698*/ // 2 children in Scope
+/* 11686*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11688*/ OPC_EmitConvertToTarget, 1,
+/* 11690*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLLI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 11698*/ /*Scope*/ 10, /*->11709*/
+/* 11699*/ OPC_EmitConvertToTarget, 1,
+/* 11701*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLLI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 11709*/ 0, /*End of Scope*/
+/* 11710*/ /*SwitchType*/ 15, MVT::i64,// ->11727
+/* 11712*/ OPC_MoveParent,
+/* 11713*/ OPC_CheckType, MVT::i64,
+/* 11715*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11717*/ OPC_EmitConvertToTarget, 1,
+/* 11719*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLLI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 11727*/ 0, // EndSwitchType
+/* 11728*/ /*Scope*/ 26, /*->11755*/
+/* 11729*/ OPC_CheckChild1Type, MVT::i32,
+/* 11731*/ OPC_CheckType, MVT::i32,
+/* 11733*/ OPC_Scope, 10, /*->11745*/ // 2 children in Scope
+/* 11735*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11737*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11745*/ /*Scope*/ 8, /*->11754*/
+/* 11746*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11754*/ 0, /*End of Scope*/
+/* 11755*/ /*Scope*/ 14, /*->11770*/
+/* 11756*/ OPC_CheckChild1Type, MVT::i64,
+/* 11758*/ OPC_CheckType, MVT::i64,
+/* 11760*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11762*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLL), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (SLL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 11770*/ 0, /*End of Scope*/
+/* 11771*/ 0, /*End of Scope*/
+/* 11772*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::SRL),// ->11939
+/* 11776*/ OPC_RecordChild0, // #0 = $rs1
+/* 11777*/ OPC_Scope, 56, /*->11835*/ // 2 children in Scope
+/* 11779*/ OPC_MoveChild1,
+/* 11780*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 11783*/ OPC_RecordChild0, // #1 = $rs2
+/* 11784*/ OPC_MoveChild1,
+/* 11785*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 11788*/ OPC_CheckPredicate, 16, // Predicate_immbottomxlenset
+/* 11790*/ OPC_MoveParent,
+/* 11791*/ OPC_SwitchType /*2 cases */, 25, MVT::i32,// ->11819
+/* 11794*/ OPC_MoveParent,
+/* 11795*/ OPC_CheckType, MVT::i32,
+/* 11797*/ OPC_Scope, 10, /*->11809*/ // 2 children in Scope
+/* 11799*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11801*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11809*/ /*Scope*/ 8, /*->11818*/
+/* 11810*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11818*/ 0, /*End of Scope*/
+/* 11819*/ /*SwitchType*/ 13, MVT::i64,// ->11834
+/* 11821*/ OPC_MoveParent,
+/* 11822*/ OPC_CheckType, MVT::i64,
+/* 11824*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11826*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRL), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SRL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 11834*/ 0, // EndSwitchType
+/* 11835*/ /*Scope*/ 102, /*->11938*/
+/* 11836*/ OPC_RecordChild1, // #1 = $shamt
+/* 11837*/ OPC_Scope, 56, /*->11895*/ // 3 children in Scope
+/* 11839*/ OPC_MoveChild1,
+/* 11840*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 11843*/ OPC_CheckPredicate, 17, // Predicate_uimmlog2xlen
+/* 11845*/ OPC_SwitchType /*2 cases */, 29, MVT::i32,// ->11877
+/* 11848*/ OPC_MoveParent,
+/* 11849*/ OPC_CheckType, MVT::i32,
+/* 11851*/ OPC_Scope, 12, /*->11865*/ // 2 children in Scope
+/* 11853*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11855*/ OPC_EmitConvertToTarget, 1,
+/* 11857*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 11865*/ /*Scope*/ 10, /*->11876*/
+/* 11866*/ OPC_EmitConvertToTarget, 1,
+/* 11868*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 11876*/ 0, /*End of Scope*/
+/* 11877*/ /*SwitchType*/ 15, MVT::i64,// ->11894
+/* 11879*/ OPC_MoveParent,
+/* 11880*/ OPC_CheckType, MVT::i64,
+/* 11882*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11884*/ OPC_EmitConvertToTarget, 1,
+/* 11886*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 11894*/ 0, // EndSwitchType
+/* 11895*/ /*Scope*/ 26, /*->11922*/
+/* 11896*/ OPC_CheckChild1Type, MVT::i32,
+/* 11898*/ OPC_CheckType, MVT::i32,
+/* 11900*/ OPC_Scope, 10, /*->11912*/ // 2 children in Scope
+/* 11902*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11904*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11912*/ /*Scope*/ 8, /*->11921*/
+/* 11913*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11921*/ 0, /*End of Scope*/
+/* 11922*/ /*Scope*/ 14, /*->11937*/
+/* 11923*/ OPC_CheckChild1Type, MVT::i64,
+/* 11925*/ OPC_CheckType, MVT::i64,
+/* 11927*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11929*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRL), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (SRL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 11937*/ 0, /*End of Scope*/
+/* 11938*/ 0, /*End of Scope*/
+/* 11939*/ /*SwitchOpcode*/ 69|128,1/*197*/, TARGET_VAL(ISD::SRA),// ->12140
+/* 11943*/ OPC_Scope, 57, /*->12002*/ // 3 children in Scope
+/* 11945*/ OPC_RecordChild0, // #0 = $rs1
+/* 11946*/ OPC_MoveChild1,
+/* 11947*/ OPC_CheckOpcode, TARGET_VAL(ISD::AND),
+/* 11950*/ OPC_RecordChild0, // #1 = $rs2
+/* 11951*/ OPC_MoveChild1,
+/* 11952*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 11955*/ OPC_CheckPredicate, 16, // Predicate_immbottomxlenset
+/* 11957*/ OPC_MoveParent,
+/* 11958*/ OPC_SwitchType /*2 cases */, 25, MVT::i32,// ->11986
+/* 11961*/ OPC_MoveParent,
+/* 11962*/ OPC_CheckType, MVT::i32,
+/* 11964*/ OPC_Scope, 10, /*->11976*/ // 2 children in Scope
+/* 11966*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 11968*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11976*/ /*Scope*/ 8, /*->11985*/
+/* 11977*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 11985*/ 0, /*End of Scope*/
+/* 11986*/ /*SwitchType*/ 13, MVT::i64,// ->12001
+/* 11988*/ OPC_MoveParent,
+/* 11989*/ OPC_CheckType, MVT::i64,
+/* 11991*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 11993*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRA), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) - Complexity = 10
+ // Dst: (SRA:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 12001*/ 0, // EndSwitchType
+/* 12002*/ /*Scope*/ 32, /*->12035*/
+/* 12003*/ OPC_MoveChild0,
+/* 12004*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND_INREG),
+/* 12007*/ OPC_RecordChild0, // #0 = $rs1
+/* 12008*/ OPC_MoveChild1,
+/* 12009*/ OPC_CheckValueType, MVT::i32,
+/* 12011*/ OPC_MoveParent,
+/* 12012*/ OPC_MoveParent,
+/* 12013*/ OPC_RecordChild1, // #1 = $shamt
+/* 12014*/ OPC_MoveChild1,
+/* 12015*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 12018*/ OPC_CheckPredicate, 15, // Predicate_uimm5
+/* 12020*/ OPC_CheckType, MVT::i64,
+/* 12022*/ OPC_MoveParent,
+/* 12023*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 12025*/ OPC_EmitConvertToTarget, 1,
+/* 12027*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRAIW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs1, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt) - Complexity = 10
+ // Dst: (SRAIW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimm5>>:$shamt)
+/* 12035*/ /*Scope*/ 103, /*->12139*/
+/* 12036*/ OPC_RecordChild0, // #0 = $rs1
+/* 12037*/ OPC_RecordChild1, // #1 = $shamt
+/* 12038*/ OPC_Scope, 56, /*->12096*/ // 3 children in Scope
+/* 12040*/ OPC_MoveChild1,
+/* 12041*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 12044*/ OPC_CheckPredicate, 17, // Predicate_uimmlog2xlen
+/* 12046*/ OPC_SwitchType /*2 cases */, 29, MVT::i32,// ->12078
+/* 12049*/ OPC_MoveParent,
+/* 12050*/ OPC_CheckType, MVT::i32,
+/* 12052*/ OPC_Scope, 12, /*->12066*/ // 2 children in Scope
+/* 12054*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12056*/ OPC_EmitConvertToTarget, 1,
+/* 12058*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRAI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SRAI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 12066*/ /*Scope*/ 10, /*->12077*/
+/* 12067*/ OPC_EmitConvertToTarget, 1,
+/* 12069*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRAI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SRAI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 12077*/ 0, /*End of Scope*/
+/* 12078*/ /*SwitchType*/ 15, MVT::i64,// ->12095
+/* 12080*/ OPC_MoveParent,
+/* 12081*/ OPC_CheckType, MVT::i64,
+/* 12083*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 12085*/ OPC_EmitConvertToTarget, 1,
+/* 12087*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRAI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) - Complexity = 7
+ // Dst: (SRAI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+/* 12095*/ 0, // EndSwitchType
+/* 12096*/ /*Scope*/ 26, /*->12123*/
+/* 12097*/ OPC_CheckChild1Type, MVT::i32,
+/* 12099*/ OPC_CheckType, MVT::i32,
+/* 12101*/ OPC_Scope, 10, /*->12113*/ // 2 children in Scope
+/* 12103*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12105*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 12113*/ /*Scope*/ 8, /*->12122*/
+/* 12114*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRA), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 12122*/ 0, /*End of Scope*/
+/* 12123*/ /*Scope*/ 14, /*->12138*/
+/* 12124*/ OPC_CheckChild1Type, MVT::i64,
+/* 12126*/ OPC_CheckType, MVT::i64,
+/* 12128*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 12130*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRA), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (SRA:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 12138*/ 0, /*End of Scope*/
+/* 12139*/ 0, /*End of Scope*/
+/* 12140*/ /*SwitchOpcode*/ 114, TARGET_VAL(ISD::BRIND),// ->12257
+/* 12143*/ OPC_RecordNode, // #0 = 'brind' chained node
+/* 12144*/ OPC_Scope, 59, /*->12205*/ // 2 children in Scope
+/* 12146*/ OPC_MoveChild1,
+/* 12147*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+/* 12150*/ OPC_RecordChild0, // #1 = $rs1
+/* 12151*/ OPC_RecordChild1, // #2 = $imm12
+/* 12152*/ OPC_MoveChild1,
+/* 12153*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 12156*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 12158*/ OPC_MoveParent,
+/* 12159*/ OPC_SwitchType /*2 cases */, 27, MVT::i32,// ->12189
+/* 12162*/ OPC_MoveParent,
+/* 12163*/ OPC_Scope, 12, /*->12177*/ // 2 children in Scope
+/* 12165*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12167*/ OPC_EmitMergeInputChains1_0,
+/* 12168*/ OPC_EmitConvertToTarget, 2,
+/* 12170*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoBRIND), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 3,
+ // Src: (brind (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)) - Complexity = 10
+ // Dst: (PseudoBRIND GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 12177*/ /*Scope*/ 10, /*->12188*/
+/* 12178*/ OPC_EmitMergeInputChains1_0,
+/* 12179*/ OPC_EmitConvertToTarget, 2,
+/* 12181*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoBRIND), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 3,
+ // Src: (brind (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)) - Complexity = 10
+ // Dst: (PseudoBRIND GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 12188*/ 0, /*End of Scope*/
+/* 12189*/ /*SwitchType*/ 13, MVT::i64,// ->12204
+/* 12191*/ OPC_MoveParent,
+/* 12192*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 12194*/ OPC_EmitMergeInputChains1_0,
+/* 12195*/ OPC_EmitConvertToTarget, 2,
+/* 12197*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoBRIND), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 3,
+ // Src: (brind (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)) - Complexity = 10
+ // Dst: (PseudoBRIND GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 12204*/ 0, // EndSwitchType
+/* 12205*/ /*Scope*/ 50, /*->12256*/
+/* 12206*/ OPC_RecordChild1, // #1 = $rs1
+/* 12207*/ OPC_Scope, 30, /*->12239*/ // 2 children in Scope
+/* 12209*/ OPC_CheckChild1Type, MVT::i32,
+/* 12211*/ OPC_Scope, 13, /*->12226*/ // 2 children in Scope
+/* 12213*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12215*/ OPC_EmitMergeInputChains1_0,
+/* 12216*/ OPC_EmitInteger, MVT::i32, 0,
+/* 12219*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoBRIND), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brind GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (PseudoBRIND GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 12226*/ /*Scope*/ 11, /*->12238*/
+/* 12227*/ OPC_EmitMergeInputChains1_0,
+/* 12228*/ OPC_EmitInteger, MVT::i32, 0,
+/* 12231*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoBRIND), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brind GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (PseudoBRIND GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+/* 12238*/ 0, /*End of Scope*/
+/* 12239*/ /*Scope*/ 15, /*->12255*/
+/* 12240*/ OPC_CheckChild1Type, MVT::i64,
+/* 12242*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 12244*/ OPC_EmitMergeInputChains1_0,
+/* 12245*/ OPC_EmitInteger, MVT::i64, 0,
+/* 12248*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoBRIND), 0|OPFL_Chain,
+ 2/*#Ops*/, 1, 2,
+ // Src: (brind GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (PseudoBRIND GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+/* 12255*/ 0, /*End of Scope*/
+/* 12256*/ 0, /*End of Scope*/
+/* 12257*/ /*SwitchOpcode*/ 21, TARGET_VAL(ISD::CALLSEQ_START),// ->12281
+/* 12260*/ OPC_RecordNode, // #0 = 'callseq_start' chained node
+/* 12261*/ OPC_RecordChild1, // #1 = $amt1
+/* 12262*/ OPC_MoveChild1,
+/* 12263*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 12266*/ OPC_MoveParent,
+/* 12267*/ OPC_RecordChild2, // #2 = $amt2
+/* 12268*/ OPC_MoveChild2,
+/* 12269*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 12272*/ OPC_MoveParent,
+/* 12273*/ OPC_EmitMergeInputChains1_0,
+/* 12274*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::ADJCALLSTACKDOWN), 0|OPFL_Chain|OPFL_GlueOutput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (callseq_start (timm:{ *:[i32] }):$amt1, (timm:{ *:[i32] }):$amt2) - Complexity = 9
+ // Dst: (ADJCALLSTACKDOWN (timm:{ *:[i32] }):$amt1, (timm:{ *:[i32] }):$amt2)
+/* 12281*/ /*SwitchOpcode*/ 22, TARGET_VAL(ISD::CALLSEQ_END),// ->12306
+/* 12284*/ OPC_RecordNode, // #0 = 'callseq_end' chained node
+/* 12285*/ OPC_CaptureGlueInput,
+/* 12286*/ OPC_RecordChild1, // #1 = $amt1
+/* 12287*/ OPC_MoveChild1,
+/* 12288*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 12291*/ OPC_MoveParent,
+/* 12292*/ OPC_RecordChild2, // #2 = $amt2
+/* 12293*/ OPC_MoveChild2,
+/* 12294*/ OPC_CheckOpcode, TARGET_VAL(ISD::TargetConstant),
+/* 12297*/ OPC_MoveParent,
+/* 12298*/ OPC_EmitMergeInputChains1_0,
+/* 12299*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::ADJCALLSTACKUP), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (callseq_end (timm:{ *:[i32] }):$amt1, (timm:{ *:[i32] }):$amt2) - Complexity = 9
+ // Dst: (ADJCALLSTACKUP (timm:{ *:[i32] }):$amt1, (timm:{ *:[i32] }):$amt2)
+/* 12306*/ /*SwitchOpcode*/ 58|128,15/*1978*/, TARGET_VAL(ISD::SETCC),// ->14288
+/* 12310*/ OPC_RecordChild0, // #0 = $rs1
+/* 12311*/ OPC_Scope, 13|128,5/*653*/, /*->12967*/ // 4 children in Scope
+/* 12314*/ OPC_CheckChild0Type, MVT::i32,
+/* 12316*/ OPC_Scope, 68, /*->12386*/ // 2 children in Scope
+/* 12318*/ OPC_CheckChild1Integer, 0,
+/* 12320*/ OPC_CheckType, MVT::i32,
+/* 12322*/ OPC_Scope, 30, /*->12354*/ // 2 children in Scope
+/* 12324*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 12326*/ OPC_Scope, 13, /*->12341*/ // 2 children in Scope
+/* 12328*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12330*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12333*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] })
+/* 12341*/ /*Scope*/ 11, /*->12353*/
+/* 12342*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12345*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] })
+/* 12353*/ 0, /*End of Scope*/
+/* 12354*/ /*Scope*/ 30, /*->12385*/
+/* 12355*/ OPC_CheckChild2CondCode, ISD::SETNE,
+/* 12357*/ OPC_Scope, 13, /*->12372*/ // 2 children in Scope
+/* 12359*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12361*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 12364*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1)
+/* 12372*/ /*Scope*/ 11, /*->12384*/
+/* 12373*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 12376*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1)
+/* 12384*/ 0, /*End of Scope*/
+/* 12385*/ 0, /*End of Scope*/
+/* 12386*/ /*Scope*/ 66|128,4/*578*/, /*->12966*/
+/* 12388*/ OPC_RecordChild1, // #1 = $imm12
+/* 12389*/ OPC_Scope, 43|128,1/*171*/, /*->12563*/ // 11 children in Scope
+/* 12392*/ OPC_MoveChild1,
+/* 12393*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 12396*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 12398*/ OPC_MoveParent,
+/* 12399*/ OPC_CheckType, MVT::i32,
+/* 12401*/ OPC_Scope, 28, /*->12431*/ // 4 children in Scope
+/* 12403*/ OPC_CheckChild2CondCode, ISD::SETLT,
+/* 12405*/ OPC_Scope, 12, /*->12419*/ // 2 children in Scope
+/* 12407*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12409*/ OPC_EmitConvertToTarget, 1,
+/* 12411*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 12419*/ /*Scope*/ 10, /*->12430*/
+/* 12420*/ OPC_EmitConvertToTarget, 1,
+/* 12422*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 12430*/ 0, /*End of Scope*/
+/* 12431*/ /*Scope*/ 28, /*->12460*/
+/* 12432*/ OPC_CheckChild2CondCode, ISD::SETULT,
+/* 12434*/ OPC_Scope, 12, /*->12448*/ // 2 children in Scope
+/* 12436*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12438*/ OPC_EmitConvertToTarget, 1,
+/* 12440*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 12448*/ /*Scope*/ 10, /*->12459*/
+/* 12449*/ OPC_EmitConvertToTarget, 1,
+/* 12451*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 12459*/ 0, /*End of Scope*/
+/* 12460*/ /*Scope*/ 50, /*->12511*/
+/* 12461*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 12463*/ OPC_Scope, 23, /*->12488*/ // 2 children in Scope
+/* 12465*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12467*/ OPC_EmitConvertToTarget, 1,
+/* 12469*/ OPC_EmitNode1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
+/* 12477*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12480*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTIU:{ *:[i32] } (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i32] })
+/* 12488*/ /*Scope*/ 21, /*->12510*/
+/* 12489*/ OPC_EmitConvertToTarget, 1,
+/* 12491*/ OPC_EmitNode1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2, // Results = #3
+/* 12499*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12502*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTIU:{ *:[i32] } (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i32] })
+/* 12510*/ 0, /*End of Scope*/
+/* 12511*/ /*Scope*/ 50, /*->12562*/
+/* 12512*/ OPC_CheckChild2CondCode, ISD::SETNE,
+/* 12514*/ OPC_Scope, 23, /*->12539*/ // 2 children in Scope
+/* 12516*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12518*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 12521*/ OPC_EmitConvertToTarget, 1,
+/* 12523*/ OPC_EmitNode1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
+/* 12531*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 2, 4,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))
+/* 12539*/ /*Scope*/ 21, /*->12561*/
+/* 12540*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 12543*/ OPC_EmitConvertToTarget, 1,
+/* 12545*/ OPC_EmitNode1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 3, // Results = #4
+/* 12553*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 2, 4,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))
+/* 12561*/ 0, /*End of Scope*/
+/* 12562*/ 0, /*End of Scope*/
+/* 12563*/ /*Scope*/ 26, /*->12590*/
+/* 12564*/ OPC_CheckChild2CondCode, ISD::SETLT,
+/* 12566*/ OPC_CheckType, MVT::i32,
+/* 12568*/ OPC_Scope, 10, /*->12580*/ // 2 children in Scope
+/* 12570*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12572*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 12580*/ /*Scope*/ 8, /*->12589*/
+/* 12581*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 12589*/ 0, /*End of Scope*/
+/* 12590*/ /*Scope*/ 26, /*->12617*/
+/* 12591*/ OPC_CheckChild2CondCode, ISD::SETULT,
+/* 12593*/ OPC_CheckType, MVT::i32,
+/* 12595*/ OPC_Scope, 10, /*->12607*/ // 2 children in Scope
+/* 12597*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12599*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 12607*/ /*Scope*/ 8, /*->12616*/
+/* 12608*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 12616*/ 0, /*End of Scope*/
+/* 12617*/ /*Scope*/ 26, /*->12644*/
+/* 12618*/ OPC_CheckChild2CondCode, ISD::SETUGT,
+/* 12620*/ OPC_CheckType, MVT::i32,
+/* 12622*/ OPC_Scope, 10, /*->12634*/ // 2 children in Scope
+/* 12624*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12626*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
+/* 12634*/ /*Scope*/ 8, /*->12643*/
+/* 12635*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
+/* 12643*/ 0, /*End of Scope*/
+/* 12644*/ /*Scope*/ 26, /*->12671*/
+/* 12645*/ OPC_CheckChild2CondCode, ISD::SETGT,
+/* 12647*/ OPC_CheckType, MVT::i32,
+/* 12649*/ OPC_Scope, 10, /*->12661*/ // 2 children in Scope
+/* 12651*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12653*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
+/* 12661*/ /*Scope*/ 8, /*->12670*/
+/* 12662*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
+/* 12670*/ 0, /*End of Scope*/
+/* 12671*/ /*Scope*/ 48, /*->12720*/
+/* 12672*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 12674*/ OPC_CheckType, MVT::i32,
+/* 12676*/ OPC_Scope, 21, /*->12699*/ // 2 children in Scope
+/* 12678*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12680*/ OPC_EmitNode1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 12688*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12691*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+/* 12699*/ /*Scope*/ 19, /*->12719*/
+/* 12700*/ OPC_EmitNode1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 12708*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12711*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+/* 12719*/ 0, /*End of Scope*/
+/* 12720*/ /*Scope*/ 48, /*->12769*/
+/* 12721*/ OPC_CheckChild2CondCode, ISD::SETNE,
+/* 12723*/ OPC_CheckType, MVT::i32,
+/* 12725*/ OPC_Scope, 21, /*->12748*/ // 2 children in Scope
+/* 12727*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12729*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 12732*/ OPC_EmitNode1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 12740*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2))
+/* 12748*/ /*Scope*/ 19, /*->12768*/
+/* 12749*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 12752*/ OPC_EmitNode1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #3
+/* 12760*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2))
+/* 12768*/ 0, /*End of Scope*/
+/* 12769*/ /*Scope*/ 48, /*->12818*/
+/* 12770*/ OPC_CheckChild2CondCode, ISD::SETUGE,
+/* 12772*/ OPC_CheckType, MVT::i32,
+/* 12774*/ OPC_Scope, 21, /*->12797*/ // 2 children in Scope
+/* 12776*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12778*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 12786*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12789*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+/* 12797*/ /*Scope*/ 19, /*->12817*/
+/* 12798*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 12806*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12809*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+/* 12817*/ 0, /*End of Scope*/
+/* 12818*/ /*Scope*/ 48, /*->12867*/
+/* 12819*/ OPC_CheckChild2CondCode, ISD::SETULE,
+/* 12821*/ OPC_CheckType, MVT::i32,
+/* 12823*/ OPC_Scope, 21, /*->12846*/ // 2 children in Scope
+/* 12825*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12827*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 12835*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12838*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] })
+/* 12846*/ /*Scope*/ 19, /*->12866*/
+/* 12847*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 12855*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12858*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] })
+/* 12866*/ 0, /*End of Scope*/
+/* 12867*/ /*Scope*/ 48, /*->12916*/
+/* 12868*/ OPC_CheckChild2CondCode, ISD::SETGE,
+/* 12870*/ OPC_CheckType, MVT::i32,
+/* 12872*/ OPC_Scope, 21, /*->12895*/ // 2 children in Scope
+/* 12874*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12876*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 12884*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12887*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+/* 12895*/ /*Scope*/ 19, /*->12915*/
+/* 12896*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1, // Results = #2
+/* 12904*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12907*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+/* 12915*/ 0, /*End of Scope*/
+/* 12916*/ /*Scope*/ 48, /*->12965*/
+/* 12917*/ OPC_CheckChild2CondCode, ISD::SETLE,
+/* 12919*/ OPC_CheckType, MVT::i32,
+/* 12921*/ OPC_Scope, 21, /*->12944*/ // 2 children in Scope
+/* 12923*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 12925*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 12933*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12936*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] })
+/* 12944*/ /*Scope*/ 19, /*->12964*/
+/* 12945*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i32, 2/*#Ops*/, 1, 0, // Results = #2
+/* 12953*/ OPC_EmitInteger, MVT::i32, 1,
+/* 12956*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] })
+/* 12964*/ 0, /*End of Scope*/
+/* 12965*/ 0, /*End of Scope*/
+/* 12966*/ 0, /*End of Scope*/
+/* 12967*/ /*Scope*/ 102|128,2/*358*/, /*->13327*/
+/* 12969*/ OPC_CheckChild0Type, MVT::i64,
+/* 12971*/ OPC_Scope, 38, /*->13011*/ // 2 children in Scope
+/* 12973*/ OPC_CheckChild1Integer, 0,
+/* 12975*/ OPC_CheckType, MVT::i64,
+/* 12977*/ OPC_Scope, 15, /*->12994*/ // 2 children in Scope
+/* 12979*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 12981*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 12983*/ OPC_EmitInteger, MVT::i64, 1,
+/* 12986*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] })
+/* 12994*/ /*Scope*/ 15, /*->13010*/
+/* 12995*/ OPC_CheckChild2CondCode, ISD::SETNE,
+/* 12997*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 12999*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 13002*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETNE:{ *:[Other] }) - Complexity = 8
+ // Dst: (SLTU:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)
+/* 13010*/ 0, /*End of Scope*/
+/* 13011*/ /*Scope*/ 57|128,2/*313*/, /*->13326*/
+/* 13013*/ OPC_RecordChild1, // #1 = $imm12
+/* 13014*/ OPC_Scope, 93, /*->13109*/ // 11 children in Scope
+/* 13016*/ OPC_MoveChild1,
+/* 13017*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 13020*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 13022*/ OPC_MoveParent,
+/* 13023*/ OPC_CheckType, MVT::i64,
+/* 13025*/ OPC_Scope, 14, /*->13041*/ // 4 children in Scope
+/* 13027*/ OPC_CheckChild2CondCode, ISD::SETLT,
+/* 13029*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13031*/ OPC_EmitConvertToTarget, 1,
+/* 13033*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 13041*/ /*Scope*/ 14, /*->13056*/
+/* 13042*/ OPC_CheckChild2CondCode, ISD::SETULT,
+/* 13044*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13046*/ OPC_EmitConvertToTarget, 1,
+/* 13048*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 13056*/ /*Scope*/ 25, /*->13082*/
+/* 13057*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 13059*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13061*/ OPC_EmitConvertToTarget, 1,
+/* 13063*/ OPC_EmitNode1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2, // Results = #3
+/* 13071*/ OPC_EmitInteger, MVT::i64, 1,
+/* 13074*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i64, 2/*#Ops*/, 3, 4,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTIU:{ *:[i64] } (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i64] })
+/* 13082*/ /*Scope*/ 25, /*->13108*/
+/* 13083*/ OPC_CheckChild2CondCode, ISD::SETNE,
+/* 13085*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13087*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 13090*/ OPC_EmitConvertToTarget, 1,
+/* 13092*/ OPC_EmitNode1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 3, // Results = #4
+/* 13100*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i64, 2/*#Ops*/, 2, 4,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) - Complexity = 7
+ // Dst: (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))
+/* 13108*/ 0, /*End of Scope*/
+/* 13109*/ /*Scope*/ 14, /*->13124*/
+/* 13110*/ OPC_CheckChild2CondCode, ISD::SETLT,
+/* 13112*/ OPC_CheckType, MVT::i64,
+/* 13114*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13116*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 13124*/ /*Scope*/ 14, /*->13139*/
+/* 13125*/ OPC_CheckChild2CondCode, ISD::SETULT,
+/* 13127*/ OPC_CheckType, MVT::i64,
+/* 13129*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13131*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 13139*/ /*Scope*/ 14, /*->13154*/
+/* 13140*/ OPC_CheckChild2CondCode, ISD::SETUGT,
+/* 13142*/ OPC_CheckType, MVT::i64,
+/* 13144*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13146*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)
+/* 13154*/ /*Scope*/ 14, /*->13169*/
+/* 13155*/ OPC_CheckChild2CondCode, ISD::SETGT,
+/* 13157*/ OPC_CheckType, MVT::i64,
+/* 13159*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13161*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGT:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)
+/* 13169*/ /*Scope*/ 25, /*->13195*/
+/* 13170*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 13172*/ OPC_CheckType, MVT::i64,
+/* 13174*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13176*/ OPC_EmitNode1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #2
+/* 13184*/ OPC_EmitInteger, MVT::i64, 1,
+/* 13187*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i64] } (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] })
+/* 13195*/ /*Scope*/ 25, /*->13221*/
+/* 13196*/ OPC_CheckChild2CondCode, ISD::SETNE,
+/* 13198*/ OPC_CheckType, MVT::i64,
+/* 13200*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13202*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 13205*/ OPC_EmitNode1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #3
+/* 13213*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETNE:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2))
+/* 13221*/ /*Scope*/ 25, /*->13247*/
+/* 13222*/ OPC_CheckChild2CondCode, ISD::SETUGE,
+/* 13224*/ OPC_CheckType, MVT::i64,
+/* 13226*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13228*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #2
+/* 13236*/ OPC_EmitInteger, MVT::i64, 1,
+/* 13239*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i64] } (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] })
+/* 13247*/ /*Scope*/ 25, /*->13273*/
+/* 13248*/ OPC_CheckChild2CondCode, ISD::SETULE,
+/* 13250*/ OPC_CheckType, MVT::i64,
+/* 13252*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13254*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLTU), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0, // Results = #2
+/* 13262*/ OPC_EmitInteger, MVT::i64, 1,
+/* 13265*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i64] } (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] })
+/* 13273*/ /*Scope*/ 25, /*->13299*/
+/* 13274*/ OPC_CheckChild2CondCode, ISD::SETGE,
+/* 13276*/ OPC_CheckType, MVT::i64,
+/* 13278*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13280*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1, // Results = #2
+/* 13288*/ OPC_EmitInteger, MVT::i64, 1,
+/* 13291*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i64] } (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] })
+/* 13299*/ /*Scope*/ 25, /*->13325*/
+/* 13300*/ OPC_CheckChild2CondCode, ISD::SETLE,
+/* 13302*/ OPC_CheckType, MVT::i64,
+/* 13304*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13306*/ OPC_EmitNode1, TARGET_VAL(RISCV::SLT), 0,
+ MVT::i64, 2/*#Ops*/, 1, 0, // Results = #2
+/* 13314*/ OPC_EmitInteger, MVT::i64, 1,
+/* 13317*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (XORI:{ *:[i64] } (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] })
+/* 13325*/ 0, /*End of Scope*/
+/* 13326*/ 0, /*End of Scope*/
+/* 13327*/ /*Scope*/ 94|128,3/*478*/, /*->13807*/
+/* 13329*/ OPC_CheckChild0Type, MVT::f32,
+/* 13331*/ OPC_RecordChild1, // #1 = $rs2
+/* 13332*/ OPC_Scope, 42, /*->13376*/ // 8 children in Scope
+/* 13334*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 13336*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13363
+/* 13339*/ OPC_Scope, 10, /*->13351*/ // 2 children in Scope
+/* 13341*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13343*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13351*/ /*Scope*/ 10, /*->13362*/
+/* 13352*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 13354*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13362*/ 0, /*End of Scope*/
+/* 13363*/ /*SwitchType*/ 10, MVT::i64,// ->13375
+/* 13365*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13367*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13375*/ 0, // EndSwitchType
+/* 13376*/ /*Scope*/ 42, /*->13419*/
+/* 13377*/ OPC_CheckChild2CondCode, ISD::SETOEQ,
+/* 13379*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13406
+/* 13382*/ OPC_Scope, 10, /*->13394*/ // 2 children in Scope
+/* 13384*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13386*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13394*/ /*Scope*/ 10, /*->13405*/
+/* 13395*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 13397*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13405*/ 0, /*End of Scope*/
+/* 13406*/ /*SwitchType*/ 10, MVT::i64,// ->13418
+/* 13408*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13410*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13418*/ 0, // EndSwitchType
+/* 13419*/ /*Scope*/ 42, /*->13462*/
+/* 13420*/ OPC_CheckChild2CondCode, ISD::SETLT,
+/* 13422*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13449
+/* 13425*/ OPC_Scope, 10, /*->13437*/ // 2 children in Scope
+/* 13427*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13429*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13437*/ /*Scope*/ 10, /*->13448*/
+/* 13438*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 13440*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13448*/ 0, /*End of Scope*/
+/* 13449*/ /*SwitchType*/ 10, MVT::i64,// ->13461
+/* 13451*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13453*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13461*/ 0, // EndSwitchType
+/* 13462*/ /*Scope*/ 42, /*->13505*/
+/* 13463*/ OPC_CheckChild2CondCode, ISD::SETOLT,
+/* 13465*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13492
+/* 13468*/ OPC_Scope, 10, /*->13480*/ // 2 children in Scope
+/* 13470*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13472*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13480*/ /*Scope*/ 10, /*->13491*/
+/* 13481*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 13483*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13491*/ 0, /*End of Scope*/
+/* 13492*/ /*SwitchType*/ 10, MVT::i64,// ->13504
+/* 13494*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13496*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13504*/ 0, // EndSwitchType
+/* 13505*/ /*Scope*/ 42, /*->13548*/
+/* 13506*/ OPC_CheckChild2CondCode, ISD::SETLE,
+/* 13508*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13535
+/* 13511*/ OPC_Scope, 10, /*->13523*/ // 2 children in Scope
+/* 13513*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13515*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13523*/ /*Scope*/ 10, /*->13534*/
+/* 13524*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 13526*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13534*/ 0, /*End of Scope*/
+/* 13535*/ /*SwitchType*/ 10, MVT::i64,// ->13547
+/* 13537*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13539*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13547*/ 0, // EndSwitchType
+/* 13548*/ /*Scope*/ 42, /*->13591*/
+/* 13549*/ OPC_CheckChild2CondCode, ISD::SETOLE,
+/* 13551*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13578
+/* 13554*/ OPC_Scope, 10, /*->13566*/ // 2 children in Scope
+/* 13556*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13558*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13566*/ /*Scope*/ 10, /*->13577*/
+/* 13567*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 13569*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13577*/ 0, /*End of Scope*/
+/* 13578*/ /*SwitchType*/ 10, MVT::i64,// ->13590
+/* 13580*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13582*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 13590*/ 0, // EndSwitchType
+/* 13591*/ /*Scope*/ 90, /*->13682*/
+/* 13592*/ OPC_CheckChild2CondCode, ISD::SETO,
+/* 13594*/ OPC_SwitchType /*2 cases */, 56, MVT::i32,// ->13653
+/* 13597*/ OPC_Scope, 26, /*->13625*/ // 2 children in Scope
+/* 13599*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13601*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 0, // Results = #2
+/* 13609*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 1, 1, // Results = #3
+/* 13617*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2))
+/* 13625*/ /*Scope*/ 26, /*->13652*/
+/* 13626*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 13628*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 0, // Results = #2
+/* 13636*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 1, 1, // Results = #3
+/* 13644*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2))
+/* 13652*/ 0, /*End of Scope*/
+/* 13653*/ /*SwitchType*/ 26, MVT::i64,// ->13681
+/* 13655*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13657*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 0, // Results = #2
+/* 13665*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i64, 2/*#Ops*/, 1, 1, // Results = #3
+/* 13673*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (AND:{ *:[i64] } (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2))
+/* 13681*/ 0, // EndSwitchType
+/* 13682*/ /*Scope*/ 123, /*->13806*/
+/* 13683*/ OPC_CheckChild2CondCode, ISD::SETUO,
+/* 13685*/ OPC_SwitchType /*2 cases */, 78, MVT::i32,// ->13766
+/* 13688*/ OPC_Scope, 37, /*->13727*/ // 2 children in Scope
+/* 13690*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13692*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 0, // Results = #2
+/* 13700*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 1, 1, // Results = #3
+/* 13708*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 13716*/ OPC_EmitInteger, MVT::i32, 1,
+/* 13719*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i32] })
+/* 13727*/ /*Scope*/ 37, /*->13765*/
+/* 13728*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 13730*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 0, // Results = #2
+/* 13738*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i32, 2/*#Ops*/, 1, 1, // Results = #3
+/* 13746*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 13754*/ OPC_EmitInteger, MVT::i32, 1,
+/* 13757*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5,
+ // Src: (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i32] })
+/* 13765*/ 0, /*End of Scope*/
+/* 13766*/ /*SwitchType*/ 37, MVT::i64,// ->13805
+/* 13768*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13770*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 0, // Results = #2
+/* 13778*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_S), 0,
+ MVT::i64, 2/*#Ops*/, 1, 1, // Results = #3
+/* 13786*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3, // Results = #4
+/* 13794*/ OPC_EmitInteger, MVT::i64, 1,
+/* 13797*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i64, 2/*#Ops*/, 4, 5,
+ // Src: (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i64] } (AND:{ *:[i64] } (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i64] })
+/* 13805*/ 0, // EndSwitchType
+/* 13806*/ 0, /*End of Scope*/
+/* 13807*/ /*Scope*/ 94|128,3/*478*/, /*->14287*/
+/* 13809*/ OPC_CheckChild0Type, MVT::f64,
+/* 13811*/ OPC_RecordChild1, // #1 = $rs2
+/* 13812*/ OPC_Scope, 42, /*->13856*/ // 8 children in Scope
+/* 13814*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 13816*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13843
+/* 13819*/ OPC_Scope, 10, /*->13831*/ // 2 children in Scope
+/* 13821*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13823*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13831*/ /*Scope*/ 10, /*->13842*/
+/* 13832*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 13834*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13842*/ 0, /*End of Scope*/
+/* 13843*/ /*SwitchType*/ 10, MVT::i64,// ->13855
+/* 13845*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13847*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13855*/ 0, // EndSwitchType
+/* 13856*/ /*Scope*/ 42, /*->13899*/
+/* 13857*/ OPC_CheckChild2CondCode, ISD::SETOEQ,
+/* 13859*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13886
+/* 13862*/ OPC_Scope, 10, /*->13874*/ // 2 children in Scope
+/* 13864*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13866*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13874*/ /*Scope*/ 10, /*->13885*/
+/* 13875*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 13877*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13885*/ 0, /*End of Scope*/
+/* 13886*/ /*SwitchType*/ 10, MVT::i64,// ->13898
+/* 13888*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13890*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOEQ:{ *:[Other] }) - Complexity = 3
+ // Dst: (FEQ_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13898*/ 0, // EndSwitchType
+/* 13899*/ /*Scope*/ 42, /*->13942*/
+/* 13900*/ OPC_CheckChild2CondCode, ISD::SETLT,
+/* 13902*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13929
+/* 13905*/ OPC_Scope, 10, /*->13917*/ // 2 children in Scope
+/* 13907*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13909*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13917*/ /*Scope*/ 10, /*->13928*/
+/* 13918*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 13920*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13928*/ 0, /*End of Scope*/
+/* 13929*/ /*SwitchType*/ 10, MVT::i64,// ->13941
+/* 13931*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13933*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13941*/ 0, // EndSwitchType
+/* 13942*/ /*Scope*/ 42, /*->13985*/
+/* 13943*/ OPC_CheckChild2CondCode, ISD::SETOLT,
+/* 13945*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->13972
+/* 13948*/ OPC_Scope, 10, /*->13960*/ // 2 children in Scope
+/* 13950*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13952*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13960*/ /*Scope*/ 10, /*->13971*/
+/* 13961*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 13963*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13971*/ 0, /*End of Scope*/
+/* 13972*/ /*SwitchType*/ 10, MVT::i64,// ->13984
+/* 13974*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 13976*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLT_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLT:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLT_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 13984*/ 0, // EndSwitchType
+/* 13985*/ /*Scope*/ 42, /*->14028*/
+/* 13986*/ OPC_CheckChild2CondCode, ISD::SETLE,
+/* 13988*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->14015
+/* 13991*/ OPC_Scope, 10, /*->14003*/ // 2 children in Scope
+/* 13993*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 13995*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 14003*/ /*Scope*/ 10, /*->14014*/
+/* 14004*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 14006*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 14014*/ 0, /*End of Scope*/
+/* 14015*/ /*SwitchType*/ 10, MVT::i64,// ->14027
+/* 14017*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14019*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 14027*/ 0, // EndSwitchType
+/* 14028*/ /*Scope*/ 42, /*->14071*/
+/* 14029*/ OPC_CheckChild2CondCode, ISD::SETOLE,
+/* 14031*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->14058
+/* 14034*/ OPC_Scope, 10, /*->14046*/ // 2 children in Scope
+/* 14036*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14038*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 14046*/ /*Scope*/ 10, /*->14057*/
+/* 14047*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 14049*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_D:{ *:[i32] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 14057*/ 0, /*End of Scope*/
+/* 14058*/ /*SwitchType*/ 10, MVT::i64,// ->14070
+/* 14060*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14062*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FLE_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETOLE:{ *:[Other] }) - Complexity = 3
+ // Dst: (FLE_D:{ *:[i64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 14070*/ 0, // EndSwitchType
+/* 14071*/ /*Scope*/ 90, /*->14162*/
+/* 14072*/ OPC_CheckChild2CondCode, ISD::SETO,
+/* 14074*/ OPC_SwitchType /*2 cases */, 56, MVT::i32,// ->14133
+/* 14077*/ OPC_Scope, 26, /*->14105*/ // 2 children in Scope
+/* 14079*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14081*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 0, // Results = #2
+/* 14089*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 1, 1, // Results = #3
+/* 14097*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2))
+/* 14105*/ /*Scope*/ 26, /*->14132*/
+/* 14106*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 14108*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 0, // Results = #2
+/* 14116*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 1, 1, // Results = #3
+/* 14124*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2))
+/* 14132*/ 0, /*End of Scope*/
+/* 14133*/ /*SwitchType*/ 26, MVT::i64,// ->14161
+/* 14135*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14137*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 0, // Results = #2
+/* 14145*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i64, 2/*#Ops*/, 1, 1, // Results = #3
+/* 14153*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3,
+ // Src: (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) - Complexity = 3
+ // Dst: (AND:{ *:[i64] } (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2))
+/* 14161*/ 0, // EndSwitchType
+/* 14162*/ /*Scope*/ 123, /*->14286*/
+/* 14163*/ OPC_CheckChild2CondCode, ISD::SETUO,
+/* 14165*/ OPC_SwitchType /*2 cases */, 78, MVT::i32,// ->14246
+/* 14168*/ OPC_Scope, 37, /*->14207*/ // 2 children in Scope
+/* 14170*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14172*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 0, // Results = #2
+/* 14180*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 1, 1, // Results = #3
+/* 14188*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 14196*/ OPC_EmitInteger, MVT::i32, 1,
+/* 14199*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i32] })
+/* 14207*/ /*Scope*/ 37, /*->14245*/
+/* 14208*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 14210*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 0, // Results = #2
+/* 14218*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i32, 2/*#Ops*/, 1, 1, // Results = #3
+/* 14226*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i32, 2/*#Ops*/, 2, 3, // Results = #4
+/* 14234*/ OPC_EmitInteger, MVT::i32, 1,
+/* 14237*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i32, 2/*#Ops*/, 4, 5,
+ // Src: (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i32] })
+/* 14245*/ 0, /*End of Scope*/
+/* 14246*/ /*SwitchType*/ 37, MVT::i64,// ->14285
+/* 14248*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14250*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 0, // Results = #2
+/* 14258*/ OPC_EmitNode1, TARGET_VAL(RISCV::FEQ_D), 0,
+ MVT::i64, 2/*#Ops*/, 1, 1, // Results = #3
+/* 14266*/ OPC_EmitNode1, TARGET_VAL(RISCV::AND), 0,
+ MVT::i64, 2/*#Ops*/, 2, 3, // Results = #4
+/* 14274*/ OPC_EmitInteger, MVT::i64, 1,
+/* 14277*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTIU), 0,
+ MVT::i64, 2/*#Ops*/, 4, 5,
+ // Src: (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) - Complexity = 3
+ // Dst: (SLTIU:{ *:[i64] } (AND:{ *:[i64] } (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i64] })
+/* 14285*/ 0, // EndSwitchType
+/* 14286*/ 0, /*End of Scope*/
+/* 14287*/ 0, /*End of Scope*/
+/* 14288*/ /*SwitchOpcode*/ 94, TARGET_VAL(ISD::XOR),// ->14385
+/* 14291*/ OPC_RecordChild0, // #0 = $rs1
+/* 14292*/ OPC_RecordChild1, // #1 = $imm12
+/* 14293*/ OPC_Scope, 51, /*->14346*/ // 3 children in Scope
+/* 14295*/ OPC_MoveChild1,
+/* 14296*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 14299*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 14301*/ OPC_MoveParent,
+/* 14302*/ OPC_SwitchType /*2 cases */, 26, MVT::i32,// ->14331
+/* 14305*/ OPC_Scope, 12, /*->14319*/ // 2 children in Scope
+/* 14307*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14309*/ OPC_EmitConvertToTarget, 1,
+/* 14311*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 14319*/ /*Scope*/ 10, /*->14330*/
+/* 14320*/ OPC_EmitConvertToTarget, 1,
+/* 14322*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i32, 2/*#Ops*/, 0, 2,
+ // Src: (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+/* 14330*/ 0, /*End of Scope*/
+/* 14331*/ /*SwitchType*/ 12, MVT::i64,// ->14345
+/* 14333*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14335*/ OPC_EmitConvertToTarget, 1,
+/* 14337*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XORI), 0,
+ MVT::i64, 2/*#Ops*/, 0, 2,
+ // Src: (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) - Complexity = 7
+ // Dst: (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+/* 14345*/ 0, // EndSwitchType
+/* 14346*/ /*Scope*/ 24, /*->14371*/
+/* 14347*/ OPC_CheckType, MVT::i32,
+/* 14349*/ OPC_Scope, 10, /*->14361*/ // 2 children in Scope
+/* 14351*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14353*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 14361*/ /*Scope*/ 8, /*->14370*/
+/* 14362*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 14370*/ 0, /*End of Scope*/
+/* 14371*/ /*Scope*/ 12, /*->14384*/
+/* 14372*/ OPC_CheckType, MVT::i64,
+/* 14374*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14376*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::XOR), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 14384*/ 0, /*End of Scope*/
+/* 14385*/ /*SwitchOpcode*/ 17, TARGET_VAL(ISD::AssertSext),// ->14405
+/* 14388*/ OPC_MoveChild0,
+/* 14389*/ OPC_CheckOpcode, TARGET_VAL(RISCVISD::FMV_X_ANYEXTW_RV64),
+/* 14392*/ OPC_RecordChild0, // #0 = $src
+/* 14393*/ OPC_MoveParent,
+/* 14394*/ OPC_CheckPredicate, 0, // Predicate_assertsexti32
+/* 14396*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14398*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_W), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (assertsext:{ *:[i64] } (riscv_fmv_x_anyextw_rv64:{ *:[i64] } FPR32:{ *:[f32] }:$src))<<P:Predicate_assertsexti32>> - Complexity = 7
+ // Dst: (FMV_X_W:{ *:[i64] } FPR32:{ *:[f32] }:$src)
+/* 14405*/ /*SwitchOpcode*/ 4|128,5/*644*/, TARGET_VAL(ISD::BRCOND),// ->15053
+/* 14409*/ OPC_RecordNode, // #0 = 'brcond' chained node
+/* 14410*/ OPC_Scope, 61|128,4/*573*/, /*->14986*/ // 2 children in Scope
+/* 14413*/ OPC_MoveChild1,
+/* 14414*/ OPC_CheckOpcode, TARGET_VAL(ISD::SETCC),
+/* 14417*/ OPC_RecordChild0, // #1 = $rs1
+/* 14418*/ OPC_SwitchType /*2 cases */, 89|128,2/*345*/, MVT::i32,// ->14767
+/* 14422*/ OPC_CheckChild0Type, MVT::i32,
+/* 14424*/ OPC_RecordChild1, // #2 = $rs2
+/* 14425*/ OPC_Scope, 33, /*->14460*/ // 10 children in Scope
+/* 14427*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 14429*/ OPC_MoveParent,
+/* 14430*/ OPC_RecordChild2, // #3 = $imm12
+/* 14431*/ OPC_MoveChild2,
+/* 14432*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14435*/ OPC_MoveParent,
+/* 14436*/ OPC_Scope, 11, /*->14449*/ // 2 children in Scope
+/* 14438*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14440*/ OPC_EmitMergeInputChains1_0,
+/* 14441*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BEQ GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14449*/ /*Scope*/ 9, /*->14459*/
+/* 14450*/ OPC_EmitMergeInputChains1_0,
+/* 14451*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BEQ GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14459*/ 0, /*End of Scope*/
+/* 14460*/ /*Scope*/ 33, /*->14494*/
+/* 14461*/ OPC_CheckChild2CondCode, ISD::SETNE,
+/* 14463*/ OPC_MoveParent,
+/* 14464*/ OPC_RecordChild2, // #3 = $imm12
+/* 14465*/ OPC_MoveChild2,
+/* 14466*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14469*/ OPC_MoveParent,
+/* 14470*/ OPC_Scope, 11, /*->14483*/ // 2 children in Scope
+/* 14472*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14474*/ OPC_EmitMergeInputChains1_0,
+/* 14475*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BNE GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14483*/ /*Scope*/ 9, /*->14493*/
+/* 14484*/ OPC_EmitMergeInputChains1_0,
+/* 14485*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BNE GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14493*/ 0, /*End of Scope*/
+/* 14494*/ /*Scope*/ 33, /*->14528*/
+/* 14495*/ OPC_CheckChild2CondCode, ISD::SETLT,
+/* 14497*/ OPC_MoveParent,
+/* 14498*/ OPC_RecordChild2, // #3 = $imm12
+/* 14499*/ OPC_MoveChild2,
+/* 14500*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14503*/ OPC_MoveParent,
+/* 14504*/ OPC_Scope, 11, /*->14517*/ // 2 children in Scope
+/* 14506*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14508*/ OPC_EmitMergeInputChains1_0,
+/* 14509*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLT), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLT GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14517*/ /*Scope*/ 9, /*->14527*/
+/* 14518*/ OPC_EmitMergeInputChains1_0,
+/* 14519*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLT), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLT GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14527*/ 0, /*End of Scope*/
+/* 14528*/ /*Scope*/ 33, /*->14562*/
+/* 14529*/ OPC_CheckChild2CondCode, ISD::SETGE,
+/* 14531*/ OPC_MoveParent,
+/* 14532*/ OPC_RecordChild2, // #3 = $imm12
+/* 14533*/ OPC_MoveChild2,
+/* 14534*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14537*/ OPC_MoveParent,
+/* 14538*/ OPC_Scope, 11, /*->14551*/ // 2 children in Scope
+/* 14540*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14542*/ OPC_EmitMergeInputChains1_0,
+/* 14543*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGE GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14551*/ /*Scope*/ 9, /*->14561*/
+/* 14552*/ OPC_EmitMergeInputChains1_0,
+/* 14553*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGE GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14561*/ 0, /*End of Scope*/
+/* 14562*/ /*Scope*/ 33, /*->14596*/
+/* 14563*/ OPC_CheckChild2CondCode, ISD::SETULT,
+/* 14565*/ OPC_MoveParent,
+/* 14566*/ OPC_RecordChild2, // #3 = $imm12
+/* 14567*/ OPC_MoveChild2,
+/* 14568*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14571*/ OPC_MoveParent,
+/* 14572*/ OPC_Scope, 11, /*->14585*/ // 2 children in Scope
+/* 14574*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14576*/ OPC_EmitMergeInputChains1_0,
+/* 14577*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLTU), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLTU GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14585*/ /*Scope*/ 9, /*->14595*/
+/* 14586*/ OPC_EmitMergeInputChains1_0,
+/* 14587*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLTU), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLTU GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14595*/ 0, /*End of Scope*/
+/* 14596*/ /*Scope*/ 33, /*->14630*/
+/* 14597*/ OPC_CheckChild2CondCode, ISD::SETUGE,
+/* 14599*/ OPC_MoveParent,
+/* 14600*/ OPC_RecordChild2, // #3 = $imm12
+/* 14601*/ OPC_MoveChild2,
+/* 14602*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14605*/ OPC_MoveParent,
+/* 14606*/ OPC_Scope, 11, /*->14619*/ // 2 children in Scope
+/* 14608*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14610*/ OPC_EmitMergeInputChains1_0,
+/* 14611*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGEU), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGEU GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14619*/ /*Scope*/ 9, /*->14629*/
+/* 14620*/ OPC_EmitMergeInputChains1_0,
+/* 14621*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGEU), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGEU GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14629*/ 0, /*End of Scope*/
+/* 14630*/ /*Scope*/ 33, /*->14664*/
+/* 14631*/ OPC_CheckChild2CondCode, ISD::SETGT,
+/* 14633*/ OPC_MoveParent,
+/* 14634*/ OPC_RecordChild2, // #3 = $imm12
+/* 14635*/ OPC_MoveChild2,
+/* 14636*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14639*/ OPC_MoveParent,
+/* 14640*/ OPC_Scope, 11, /*->14653*/ // 2 children in Scope
+/* 14642*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14644*/ OPC_EmitMergeInputChains1_0,
+/* 14645*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLT), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLT GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14653*/ /*Scope*/ 9, /*->14663*/
+/* 14654*/ OPC_EmitMergeInputChains1_0,
+/* 14655*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLT), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLT GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14663*/ 0, /*End of Scope*/
+/* 14664*/ /*Scope*/ 33, /*->14698*/
+/* 14665*/ OPC_CheckChild2CondCode, ISD::SETLE,
+/* 14667*/ OPC_MoveParent,
+/* 14668*/ OPC_RecordChild2, // #3 = $imm12
+/* 14669*/ OPC_MoveChild2,
+/* 14670*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14673*/ OPC_MoveParent,
+/* 14674*/ OPC_Scope, 11, /*->14687*/ // 2 children in Scope
+/* 14676*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14678*/ OPC_EmitMergeInputChains1_0,
+/* 14679*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGE), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGE GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14687*/ /*Scope*/ 9, /*->14697*/
+/* 14688*/ OPC_EmitMergeInputChains1_0,
+/* 14689*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGE), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGE GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14697*/ 0, /*End of Scope*/
+/* 14698*/ /*Scope*/ 33, /*->14732*/
+/* 14699*/ OPC_CheckChild2CondCode, ISD::SETUGT,
+/* 14701*/ OPC_MoveParent,
+/* 14702*/ OPC_RecordChild2, // #3 = $imm12
+/* 14703*/ OPC_MoveChild2,
+/* 14704*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14707*/ OPC_MoveParent,
+/* 14708*/ OPC_Scope, 11, /*->14721*/ // 2 children in Scope
+/* 14710*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14712*/ OPC_EmitMergeInputChains1_0,
+/* 14713*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLTU), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLTU GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14721*/ /*Scope*/ 9, /*->14731*/
+/* 14722*/ OPC_EmitMergeInputChains1_0,
+/* 14723*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLTU), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLTU GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14731*/ 0, /*End of Scope*/
+/* 14732*/ /*Scope*/ 33, /*->14766*/
+/* 14733*/ OPC_CheckChild2CondCode, ISD::SETULE,
+/* 14735*/ OPC_MoveParent,
+/* 14736*/ OPC_RecordChild2, // #3 = $imm12
+/* 14737*/ OPC_MoveChild2,
+/* 14738*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14741*/ OPC_MoveParent,
+/* 14742*/ OPC_Scope, 11, /*->14755*/ // 2 children in Scope
+/* 14744*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 14746*/ OPC_EmitMergeInputChains1_0,
+/* 14747*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGEU), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGEU GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14755*/ /*Scope*/ 9, /*->14765*/
+/* 14756*/ OPC_EmitMergeInputChains1_0,
+/* 14757*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGEU), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGEU GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14765*/ 0, /*End of Scope*/
+/* 14766*/ 0, /*End of Scope*/
+/* 14767*/ /*SwitchType*/ 87|128,1/*215*/, MVT::i64,// ->14985
+/* 14770*/ OPC_CheckChild0Type, MVT::i64,
+/* 14772*/ OPC_RecordChild1, // #2 = $rs2
+/* 14773*/ OPC_Scope, 20, /*->14795*/ // 10 children in Scope
+/* 14775*/ OPC_CheckChild2CondCode, ISD::SETEQ,
+/* 14777*/ OPC_MoveParent,
+/* 14778*/ OPC_RecordChild2, // #3 = $imm12
+/* 14779*/ OPC_MoveChild2,
+/* 14780*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14783*/ OPC_MoveParent,
+/* 14784*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14786*/ OPC_EmitMergeInputChains1_0,
+/* 14787*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BEQ), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BEQ GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14795*/ /*Scope*/ 20, /*->14816*/
+/* 14796*/ OPC_CheckChild2CondCode, ISD::SETNE,
+/* 14798*/ OPC_MoveParent,
+/* 14799*/ OPC_RecordChild2, // #3 = $imm12
+/* 14800*/ OPC_MoveChild2,
+/* 14801*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14804*/ OPC_MoveParent,
+/* 14805*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14807*/ OPC_EmitMergeInputChains1_0,
+/* 14808*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BNE GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14816*/ /*Scope*/ 20, /*->14837*/
+/* 14817*/ OPC_CheckChild2CondCode, ISD::SETLT,
+/* 14819*/ OPC_MoveParent,
+/* 14820*/ OPC_RecordChild2, // #3 = $imm12
+/* 14821*/ OPC_MoveChild2,
+/* 14822*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14825*/ OPC_MoveParent,
+/* 14826*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14828*/ OPC_EmitMergeInputChains1_0,
+/* 14829*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLT), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLT GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14837*/ /*Scope*/ 20, /*->14858*/
+/* 14838*/ OPC_CheckChild2CondCode, ISD::SETGE,
+/* 14840*/ OPC_MoveParent,
+/* 14841*/ OPC_RecordChild2, // #3 = $imm12
+/* 14842*/ OPC_MoveChild2,
+/* 14843*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14846*/ OPC_MoveParent,
+/* 14847*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14849*/ OPC_EmitMergeInputChains1_0,
+/* 14850*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGE GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14858*/ /*Scope*/ 20, /*->14879*/
+/* 14859*/ OPC_CheckChild2CondCode, ISD::SETULT,
+/* 14861*/ OPC_MoveParent,
+/* 14862*/ OPC_RecordChild2, // #3 = $imm12
+/* 14863*/ OPC_MoveChild2,
+/* 14864*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14867*/ OPC_MoveParent,
+/* 14868*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14870*/ OPC_EmitMergeInputChains1_0,
+/* 14871*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLTU), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLTU GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14879*/ /*Scope*/ 20, /*->14900*/
+/* 14880*/ OPC_CheckChild2CondCode, ISD::SETUGE,
+/* 14882*/ OPC_MoveParent,
+/* 14883*/ OPC_RecordChild2, // #3 = $imm12
+/* 14884*/ OPC_MoveChild2,
+/* 14885*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14888*/ OPC_MoveParent,
+/* 14889*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14891*/ OPC_EmitMergeInputChains1_0,
+/* 14892*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGEU), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 2, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGEU GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, simm13_lsb0:{ *:[Other] }:$imm12)
+/* 14900*/ /*Scope*/ 20, /*->14921*/
+/* 14901*/ OPC_CheckChild2CondCode, ISD::SETGT,
+/* 14903*/ OPC_MoveParent,
+/* 14904*/ OPC_RecordChild2, // #3 = $imm12
+/* 14905*/ OPC_MoveChild2,
+/* 14906*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14909*/ OPC_MoveParent,
+/* 14910*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14912*/ OPC_EmitMergeInputChains1_0,
+/* 14913*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLT), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLT GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14921*/ /*Scope*/ 20, /*->14942*/
+/* 14922*/ OPC_CheckChild2CondCode, ISD::SETLE,
+/* 14924*/ OPC_MoveParent,
+/* 14925*/ OPC_RecordChild2, // #3 = $imm12
+/* 14926*/ OPC_MoveChild2,
+/* 14927*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14930*/ OPC_MoveParent,
+/* 14931*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14933*/ OPC_EmitMergeInputChains1_0,
+/* 14934*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGE), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGE GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14942*/ /*Scope*/ 20, /*->14963*/
+/* 14943*/ OPC_CheckChild2CondCode, ISD::SETUGT,
+/* 14945*/ OPC_MoveParent,
+/* 14946*/ OPC_RecordChild2, // #3 = $imm12
+/* 14947*/ OPC_MoveChild2,
+/* 14948*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14951*/ OPC_MoveParent,
+/* 14952*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14954*/ OPC_EmitMergeInputChains1_0,
+/* 14955*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BLTU), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BLTU GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14963*/ /*Scope*/ 20, /*->14984*/
+/* 14964*/ OPC_CheckChild2CondCode, ISD::SETULE,
+/* 14966*/ OPC_MoveParent,
+/* 14967*/ OPC_RecordChild2, // #3 = $imm12
+/* 14968*/ OPC_MoveChild2,
+/* 14969*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14972*/ OPC_MoveParent,
+/* 14973*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 14975*/ OPC_EmitMergeInputChains1_0,
+/* 14976*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BGEU), 0|OPFL_Chain,
+ 3/*#Ops*/, 2, 1, 3,
+ // Src: (brcond (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$imm12) - Complexity = 6
+ // Dst: (BGEU GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (bb:{ *:[Other] }):$imm12)
+/* 14984*/ 0, /*End of Scope*/
+/* 14985*/ 0, // EndSwitchType
+/* 14986*/ /*Scope*/ 65, /*->15052*/
+/* 14987*/ OPC_RecordChild1, // #1 = $cond
+/* 14988*/ OPC_Scope, 38, /*->15028*/ // 2 children in Scope
+/* 14990*/ OPC_CheckChild1Type, MVT::i32,
+/* 14992*/ OPC_RecordChild2, // #2 = $imm12
+/* 14993*/ OPC_MoveChild2,
+/* 14994*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 14997*/ OPC_MoveParent,
+/* 14998*/ OPC_Scope, 14, /*->15014*/ // 2 children in Scope
+/* 15000*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15002*/ OPC_EmitMergeInputChains1_0,
+/* 15003*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 15006*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond GPR:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$imm12) - Complexity = 3
+ // Dst: (BNE GPR:{ *:[i32] }:$cond, X0:{ *:[i32] }, (bb:{ *:[Other] }):$imm12)
+/* 15014*/ /*Scope*/ 12, /*->15027*/
+/* 15015*/ OPC_EmitMergeInputChains1_0,
+/* 15016*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 15019*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond GPR:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$imm12) - Complexity = 3
+ // Dst: (BNE GPR:{ *:[i32] }:$cond, X0:{ *:[i32] }, (bb:{ *:[Other] }):$imm12)
+/* 15027*/ 0, /*End of Scope*/
+/* 15028*/ /*Scope*/ 22, /*->15051*/
+/* 15029*/ OPC_CheckChild1Type, MVT::i64,
+/* 15031*/ OPC_RecordChild2, // #2 = $imm12
+/* 15032*/ OPC_MoveChild2,
+/* 15033*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 15036*/ OPC_MoveParent,
+/* 15037*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15039*/ OPC_EmitMergeInputChains1_0,
+/* 15040*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 15043*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::BNE), 0|OPFL_Chain,
+ 3/*#Ops*/, 1, 3, 2,
+ // Src: (brcond GPR:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$imm12) - Complexity = 3
+ // Dst: (BNE GPR:{ *:[i64] }:$cond, X0:{ *:[i64] }, (bb:{ *:[Other] }):$imm12)
+/* 15051*/ 0, /*End of Scope*/
+/* 15052*/ 0, /*End of Scope*/
+/* 15053*/ /*SwitchOpcode*/ 124, TARGET_VAL(RISCVISD::CALL),// ->15180
+/* 15056*/ OPC_RecordNode, // #0 = 'riscv_call' chained node
+/* 15057*/ OPC_CaptureGlueInput,
+/* 15058*/ OPC_RecordChild1, // #1 = $func
+/* 15059*/ OPC_Scope, 83, /*->15144*/ // 3 children in Scope
+/* 15061*/ OPC_MoveChild1,
+/* 15062*/ OPC_SwitchOpcode /*2 cases */, 37, TARGET_VAL(ISD::TargetGlobalAddress),// ->15103
+/* 15066*/ OPC_SwitchType /*2 cases */, 21, MVT::i32,// ->15090
+/* 15069*/ OPC_MoveParent,
+/* 15070*/ OPC_Scope, 9, /*->15081*/ // 2 children in Scope
+/* 15072*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15074*/ OPC_EmitMergeInputChains1_0,
+/* 15075*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call (tglobaladdr:{ *:[i32] }):$func) - Complexity = 6
+ // Dst: (PseudoCALL (tglobaladdr:{ *:[i32] }):$func)
+/* 15081*/ /*Scope*/ 7, /*->15089*/
+/* 15082*/ OPC_EmitMergeInputChains1_0,
+/* 15083*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call (tglobaladdr:{ *:[i32] }):$func) - Complexity = 6
+ // Dst: (PseudoCALL (tglobaladdr:{ *:[i32] }):$func)
+/* 15089*/ 0, /*End of Scope*/
+/* 15090*/ /*SwitchType*/ 10, MVT::i64,// ->15102
+/* 15092*/ OPC_MoveParent,
+/* 15093*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15095*/ OPC_EmitMergeInputChains1_0,
+/* 15096*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call (tglobaladdr:{ *:[i64] }):$func) - Complexity = 6
+ // Dst: (PseudoCALL (tglobaladdr:{ *:[i64] }):$func)
+/* 15102*/ 0, // EndSwitchType
+/* 15103*/ /*SwitchOpcode*/ 37, TARGET_VAL(ISD::TargetExternalSymbol),// ->15143
+/* 15106*/ OPC_SwitchType /*2 cases */, 21, MVT::i32,// ->15130
+/* 15109*/ OPC_MoveParent,
+/* 15110*/ OPC_Scope, 9, /*->15121*/ // 2 children in Scope
+/* 15112*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15114*/ OPC_EmitMergeInputChains1_0,
+/* 15115*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call (texternalsym:{ *:[i32] }):$func) - Complexity = 6
+ // Dst: (PseudoCALL (texternalsym:{ *:[i32] }):$func)
+/* 15121*/ /*Scope*/ 7, /*->15129*/
+/* 15122*/ OPC_EmitMergeInputChains1_0,
+/* 15123*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call (texternalsym:{ *:[i32] }):$func) - Complexity = 6
+ // Dst: (PseudoCALL (texternalsym:{ *:[i32] }):$func)
+/* 15129*/ 0, /*End of Scope*/
+/* 15130*/ /*SwitchType*/ 10, MVT::i64,// ->15142
+/* 15132*/ OPC_MoveParent,
+/* 15133*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15135*/ OPC_EmitMergeInputChains1_0,
+/* 15136*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call (texternalsym:{ *:[i64] }):$func) - Complexity = 6
+ // Dst: (PseudoCALL (texternalsym:{ *:[i64] }):$func)
+/* 15142*/ 0, // EndSwitchType
+/* 15143*/ 0, // EndSwitchOpcode
+/* 15144*/ /*Scope*/ 22, /*->15167*/
+/* 15145*/ OPC_CheckChild1Type, MVT::i32,
+/* 15147*/ OPC_Scope, 9, /*->15158*/ // 2 children in Scope
+/* 15149*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15151*/ OPC_EmitMergeInputChains1_0,
+/* 15152*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALLIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (PseudoCALLIndirect GPR:{ *:[i32] }:$rs1)
+/* 15158*/ /*Scope*/ 7, /*->15166*/
+/* 15159*/ OPC_EmitMergeInputChains1_0,
+/* 15160*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALLIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (PseudoCALLIndirect GPR:{ *:[i32] }:$rs1)
+/* 15166*/ 0, /*End of Scope*/
+/* 15167*/ /*Scope*/ 11, /*->15179*/
+/* 15168*/ OPC_CheckChild1Type, MVT::i64,
+/* 15170*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15172*/ OPC_EmitMergeInputChains1_0,
+/* 15173*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoCALLIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_call GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (PseudoCALLIndirect GPR:{ *:[i64] }:$rs1)
+/* 15179*/ 0, /*End of Scope*/
+/* 15180*/ /*SwitchOpcode*/ 124, TARGET_VAL(RISCVISD::TAIL),// ->15307
+/* 15183*/ OPC_RecordNode, // #0 = 'riscv_tail' chained node
+/* 15184*/ OPC_CaptureGlueInput,
+/* 15185*/ OPC_RecordChild1, // #1 = $dst
+/* 15186*/ OPC_Scope, 83, /*->15271*/ // 3 children in Scope
+/* 15188*/ OPC_MoveChild1,
+/* 15189*/ OPC_SwitchOpcode /*2 cases */, 37, TARGET_VAL(ISD::TargetGlobalAddress),// ->15230
+/* 15193*/ OPC_SwitchType /*2 cases */, 21, MVT::i32,// ->15217
+/* 15196*/ OPC_MoveParent,
+/* 15197*/ OPC_Scope, 9, /*->15208*/ // 2 children in Scope
+/* 15199*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15201*/ OPC_EmitMergeInputChains1_0,
+/* 15202*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail (tglobaladdr:{ *:[i32] }):$dst) - Complexity = 6
+ // Dst: (PseudoTAIL (texternalsym:{ *:[i32] }):$dst)
+/* 15208*/ /*Scope*/ 7, /*->15216*/
+/* 15209*/ OPC_EmitMergeInputChains1_0,
+/* 15210*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail (tglobaladdr:{ *:[i32] }):$dst) - Complexity = 6
+ // Dst: (PseudoTAIL (texternalsym:{ *:[i32] }):$dst)
+/* 15216*/ 0, /*End of Scope*/
+/* 15217*/ /*SwitchType*/ 10, MVT::i64,// ->15229
+/* 15219*/ OPC_MoveParent,
+/* 15220*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15222*/ OPC_EmitMergeInputChains1_0,
+/* 15223*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail (tglobaladdr:{ *:[i64] }):$dst) - Complexity = 6
+ // Dst: (PseudoTAIL (texternalsym:{ *:[i64] }):$dst)
+/* 15229*/ 0, // EndSwitchType
+/* 15230*/ /*SwitchOpcode*/ 37, TARGET_VAL(ISD::TargetExternalSymbol),// ->15270
+/* 15233*/ OPC_SwitchType /*2 cases */, 21, MVT::i32,// ->15257
+/* 15236*/ OPC_MoveParent,
+/* 15237*/ OPC_Scope, 9, /*->15248*/ // 2 children in Scope
+/* 15239*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15241*/ OPC_EmitMergeInputChains1_0,
+/* 15242*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail (texternalsym:{ *:[i32] }):$dst) - Complexity = 6
+ // Dst: (PseudoTAIL (texternalsym:{ *:[i32] }):$dst)
+/* 15248*/ /*Scope*/ 7, /*->15256*/
+/* 15249*/ OPC_EmitMergeInputChains1_0,
+/* 15250*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail (texternalsym:{ *:[i32] }):$dst) - Complexity = 6
+ // Dst: (PseudoTAIL (texternalsym:{ *:[i32] }):$dst)
+/* 15256*/ 0, /*End of Scope*/
+/* 15257*/ /*SwitchType*/ 10, MVT::i64,// ->15269
+/* 15259*/ OPC_MoveParent,
+/* 15260*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15262*/ OPC_EmitMergeInputChains1_0,
+/* 15263*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAIL), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail (texternalsym:{ *:[i64] }):$dst) - Complexity = 6
+ // Dst: (PseudoTAIL (texternalsym:{ *:[i64] }):$dst)
+/* 15269*/ 0, // EndSwitchType
+/* 15270*/ 0, // EndSwitchOpcode
+/* 15271*/ /*Scope*/ 22, /*->15294*/
+/* 15272*/ OPC_CheckChild1Type, MVT::i32,
+/* 15274*/ OPC_Scope, 9, /*->15285*/ // 2 children in Scope
+/* 15276*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15278*/ OPC_EmitMergeInputChains1_0,
+/* 15279*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAILIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail GPRTC:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (PseudoTAILIndirect GPRTC:{ *:[i32] }:$rs1)
+/* 15285*/ /*Scope*/ 7, /*->15293*/
+/* 15286*/ OPC_EmitMergeInputChains1_0,
+/* 15287*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAILIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail GPRTC:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (PseudoTAILIndirect GPRTC:{ *:[i32] }:$rs1)
+/* 15293*/ 0, /*End of Scope*/
+/* 15294*/ /*Scope*/ 11, /*->15306*/
+/* 15295*/ OPC_CheckChild1Type, MVT::i64,
+/* 15297*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15299*/ OPC_EmitMergeInputChains1_0,
+/* 15300*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoTAILIndirect), 0|OPFL_Chain|OPFL_GlueInput|OPFL_GlueOutput|OPFL_Variadic1,
+ 1/*#Ops*/, 1,
+ // Src: (riscv_tail GPRTC:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (PseudoTAILIndirect GPRTC:{ *:[i64] }:$rs1)
+/* 15306*/ 0, /*End of Scope*/
+/* 15307*/ /*SwitchOpcode*/ 65|128,1/*193*/, TARGET_VAL(RISCVISD::SELECT_CC),// ->15504
+/* 15311*/ OPC_CaptureGlueInput,
+/* 15312*/ OPC_RecordChild0, // #0 = $lhs
+/* 15313*/ OPC_Scope, 121, /*->15436*/ // 2 children in Scope
+/* 15315*/ OPC_CheckChild0Type, MVT::i32,
+/* 15317*/ OPC_RecordChild1, // #1 = $rhs
+/* 15318*/ OPC_RecordChild2, // #2 = $imm
+/* 15319*/ OPC_MoveChild2,
+/* 15320*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 15323*/ OPC_CheckType, MVT::i32,
+/* 15325*/ OPC_MoveParent,
+/* 15326*/ OPC_RecordChild3, // #3 = $truev
+/* 15327*/ OPC_RecordChild4, // #4 = $falsev
+/* 15328*/ OPC_SwitchType /*3 cases */, 32, MVT::i32,// ->15363
+/* 15331*/ OPC_Scope, 15, /*->15348*/ // 2 children in Scope
+/* 15333*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15335*/ OPC_EmitConvertToTarget, 2,
+/* 15337*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_GPR_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::i32, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[i32] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, GPR:{ *:[i32] }:$truev, GPR:{ *:[i32] }:$falsev) - Complexity = 6
+ // Dst: (Select_GPR_Using_CC_GPR:{ *:[i32] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, GPR:{ *:[i32] }:$truev, GPR:{ *:[i32] }:$falsev)
+/* 15348*/ /*Scope*/ 13, /*->15362*/
+/* 15349*/ OPC_EmitConvertToTarget, 2,
+/* 15351*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_GPR_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::i32, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[i32] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, GPR:{ *:[i32] }:$truev, GPR:{ *:[i32] }:$falsev) - Complexity = 6
+ // Dst: (Select_GPR_Using_CC_GPR:{ *:[i32] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, GPR:{ *:[i32] }:$truev, GPR:{ *:[i32] }:$falsev)
+/* 15362*/ 0, /*End of Scope*/
+/* 15363*/ /*SwitchType*/ 34, MVT::f32,// ->15399
+/* 15365*/ OPC_Scope, 15, /*->15382*/ // 2 children in Scope
+/* 15367*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15369*/ OPC_EmitConvertToTarget, 2,
+/* 15371*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_FPR32_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::f32, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[f32] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, FPR32:{ *:[f32] }:$truev, FPR32:{ *:[f32] }:$falsev) - Complexity = 6
+ // Dst: (Select_FPR32_Using_CC_GPR:{ *:[f32] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, FPR32:{ *:[f32] }:$truev, FPR32:{ *:[f32] }:$falsev)
+/* 15382*/ /*Scope*/ 15, /*->15398*/
+/* 15383*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 15385*/ OPC_EmitConvertToTarget, 2,
+/* 15387*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_FPR32_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::f32, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[f32] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, FPR32:{ *:[f32] }:$truev, FPR32:{ *:[f32] }:$falsev) - Complexity = 6
+ // Dst: (Select_FPR32_Using_CC_GPR:{ *:[f32] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, FPR32:{ *:[f32] }:$truev, FPR32:{ *:[f32] }:$falsev)
+/* 15398*/ 0, /*End of Scope*/
+/* 15399*/ /*SwitchType*/ 34, MVT::f64,// ->15435
+/* 15401*/ OPC_Scope, 15, /*->15418*/ // 2 children in Scope
+/* 15403*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15405*/ OPC_EmitConvertToTarget, 2,
+/* 15407*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_FPR64_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::f64, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[f64] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, FPR64:{ *:[f64] }:$truev, FPR64:{ *:[f64] }:$falsev) - Complexity = 6
+ // Dst: (Select_FPR64_Using_CC_GPR:{ *:[f64] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, FPR64:{ *:[f64] }:$truev, FPR64:{ *:[f64] }:$falsev)
+/* 15418*/ /*Scope*/ 15, /*->15434*/
+/* 15419*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 15421*/ OPC_EmitConvertToTarget, 2,
+/* 15423*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_FPR64_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::f64, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[f64] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, FPR64:{ *:[f64] }:$truev, FPR64:{ *:[f64] }:$falsev) - Complexity = 6
+ // Dst: (Select_FPR64_Using_CC_GPR:{ *:[f64] } GPR:{ *:[i32] }:$lhs, GPR:{ *:[i32] }:$rhs, (imm:{ *:[i32] }):$imm, FPR64:{ *:[f64] }:$truev, FPR64:{ *:[f64] }:$falsev)
+/* 15434*/ 0, /*End of Scope*/
+/* 15435*/ 0, // EndSwitchType
+/* 15436*/ /*Scope*/ 66, /*->15503*/
+/* 15437*/ OPC_CheckChild0Type, MVT::i64,
+/* 15439*/ OPC_RecordChild1, // #1 = $rhs
+/* 15440*/ OPC_RecordChild2, // #2 = $imm
+/* 15441*/ OPC_MoveChild2,
+/* 15442*/ OPC_CheckOpcode, TARGET_VAL(ISD::Constant),
+/* 15445*/ OPC_CheckType, MVT::i64,
+/* 15447*/ OPC_MoveParent,
+/* 15448*/ OPC_RecordChild3, // #3 = $truev
+/* 15449*/ OPC_RecordChild4, // #4 = $falsev
+/* 15450*/ OPC_SwitchType /*3 cases */, 15, MVT::i64,// ->15468
+/* 15453*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15455*/ OPC_EmitConvertToTarget, 2,
+/* 15457*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_GPR_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::i64, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[i64] } GPR:{ *:[i64] }:$lhs, GPR:{ *:[i64] }:$rhs, (imm:{ *:[i64] }):$imm, GPR:{ *:[i64] }:$truev, GPR:{ *:[i64] }:$falsev) - Complexity = 6
+ // Dst: (Select_GPR_Using_CC_GPR:{ *:[i64] } GPR:{ *:[i64] }:$lhs, GPR:{ *:[i64] }:$rhs, (imm:{ *:[i64] }):$imm, GPR:{ *:[i64] }:$truev, GPR:{ *:[i64] }:$falsev)
+/* 15468*/ /*SwitchType*/ 15, MVT::f32,// ->15485
+/* 15470*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15472*/ OPC_EmitConvertToTarget, 2,
+/* 15474*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_FPR32_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::f32, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[f32] } GPR:{ *:[i64] }:$lhs, GPR:{ *:[i64] }:$rhs, (imm:{ *:[i64] }):$imm, FPR32:{ *:[f32] }:$truev, FPR32:{ *:[f32] }:$falsev) - Complexity = 6
+ // Dst: (Select_FPR32_Using_CC_GPR:{ *:[f32] } GPR:{ *:[i64] }:$lhs, GPR:{ *:[i64] }:$rhs, (imm:{ *:[i64] }):$imm, FPR32:{ *:[f32] }:$truev, FPR32:{ *:[f32] }:$falsev)
+/* 15485*/ /*SwitchType*/ 15, MVT::f64,// ->15502
+/* 15487*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15489*/ OPC_EmitConvertToTarget, 2,
+/* 15491*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::Select_FPR64_Using_CC_GPR), 0|OPFL_GlueInput,
+ MVT::f64, 5/*#Ops*/, 0, 1, 5, 3, 4,
+ // Src: (riscv_selectcc:{ *:[f64] } GPR:{ *:[i64] }:$lhs, GPR:{ *:[i64] }:$rhs, (imm:{ *:[i64] }):$imm, FPR64:{ *:[f64] }:$truev, FPR64:{ *:[f64] }:$falsev) - Complexity = 6
+ // Dst: (Select_FPR64_Using_CC_GPR:{ *:[f64] } GPR:{ *:[i64] }:$lhs, GPR:{ *:[i64] }:$rhs, (imm:{ *:[i64] }):$imm, FPR64:{ *:[f64] }:$truev, FPR64:{ *:[f64] }:$falsev)
+/* 15502*/ 0, // EndSwitchType
+/* 15503*/ 0, /*End of Scope*/
+/* 15504*/ /*SwitchOpcode*/ 78|128,1/*206*/, TARGET_VAL(ISD::Constant),// ->15714
+/* 15508*/ OPC_RecordNode, // #0 = $imm
+/* 15509*/ OPC_Scope, 55, /*->15566*/ // 3 children in Scope
+/* 15511*/ OPC_CheckPredicate, 1, // Predicate_simm12
+/* 15513*/ OPC_SwitchType /*2 cases */, 32, MVT::i32,// ->15548
+/* 15516*/ OPC_Scope, 15, /*->15533*/ // 2 children in Scope
+/* 15518*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15520*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 15523*/ OPC_EmitConvertToTarget, 0,
+/* 15525*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm - Complexity = 4
+ // Dst: (ADDI:{ *:[i32] } X0:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
+/* 15533*/ /*Scope*/ 13, /*->15547*/
+/* 15534*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 15537*/ OPC_EmitConvertToTarget, 0,
+/* 15539*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm - Complexity = 4
+ // Dst: (ADDI:{ *:[i32] } X0:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
+/* 15547*/ 0, /*End of Scope*/
+/* 15548*/ /*SwitchType*/ 15, MVT::i64,// ->15565
+/* 15550*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15552*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 15555*/ OPC_EmitConvertToTarget, 0,
+/* 15557*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm - Complexity = 4
+ // Dst: (ADDI:{ *:[i64] } X0:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)
+/* 15565*/ 0, // EndSwitchType
+/* 15566*/ /*Scope*/ 52, /*->15619*/
+/* 15567*/ OPC_CheckPredicate, 18, // Predicate_simm32hi20
+/* 15569*/ OPC_SwitchType /*2 cases */, 30, MVT::i32,// ->15602
+/* 15572*/ OPC_Scope, 14, /*->15588*/ // 2 children in Scope
+/* 15574*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15576*/ OPC_EmitConvertToTarget, 0,
+/* 15578*/ OPC_EmitNodeXForm, 0, 1, // HI20
+/* 15581*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LUI), 0,
+ MVT::i32, 1/*#Ops*/, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_simm32hi20>>:$imm - Complexity = 4
+ // Dst: (LUI:{ *:[i32] } (HI20:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 15588*/ /*Scope*/ 12, /*->15601*/
+/* 15589*/ OPC_EmitConvertToTarget, 0,
+/* 15591*/ OPC_EmitNodeXForm, 0, 1, // HI20
+/* 15594*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LUI), 0,
+ MVT::i32, 1/*#Ops*/, 2,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_simm32hi20>>:$imm - Complexity = 4
+ // Dst: (LUI:{ *:[i32] } (HI20:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 15601*/ 0, /*End of Scope*/
+/* 15602*/ /*SwitchType*/ 14, MVT::i64,// ->15618
+/* 15604*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15606*/ OPC_EmitConvertToTarget, 0,
+/* 15608*/ OPC_EmitNodeXForm, 0, 1, // HI20
+/* 15611*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::LUI), 0,
+ MVT::i64, 1/*#Ops*/, 2,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_simm32hi20>>:$imm - Complexity = 4
+ // Dst: (LUI:{ *:[i64] } (HI20:{ *:[i64] } (imm:{ *:[i64] }):$imm))
+/* 15618*/ 0, // EndSwitchType
+/* 15619*/ /*Scope*/ 93, /*->15713*/
+/* 15620*/ OPC_CheckPredicate, 19, // Predicate_simm32
+/* 15622*/ OPC_SwitchType /*2 cases */, 58, MVT::i32,// ->15683
+/* 15625*/ OPC_Scope, 27, /*->15654*/ // 2 children in Scope
+/* 15627*/ OPC_CheckPatternPredicate, 8, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15629*/ OPC_EmitConvertToTarget, 0,
+/* 15631*/ OPC_EmitNodeXForm, 0, 1, // HI20
+/* 15634*/ OPC_EmitNode1, TARGET_VAL(RISCV::LUI), 0,
+ MVT::i32, 1/*#Ops*/, 2, // Results = #3
+/* 15641*/ OPC_EmitConvertToTarget, 0,
+/* 15643*/ OPC_EmitNodeXForm, 1, 4, // LO12Sext
+/* 15646*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 3, 5,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_simm32>>:$imm - Complexity = 4
+ // Dst: (ADDI:{ *:[i32] } (LUI:{ *:[i32] } (HI20:{ *:[i32] } (imm:{ *:[i32] }):$imm)), (LO12Sext:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 15654*/ /*Scope*/ 27, /*->15682*/
+/* 15655*/ OPC_CheckPatternPredicate, 9, // (!Subtarget->is64Bit())
+/* 15657*/ OPC_EmitConvertToTarget, 0,
+/* 15659*/ OPC_EmitNodeXForm, 0, 1, // HI20
+/* 15662*/ OPC_EmitNode1, TARGET_VAL(RISCV::LUI), 0,
+ MVT::i32, 1/*#Ops*/, 2, // Results = #3
+/* 15669*/ OPC_EmitConvertToTarget, 0,
+/* 15671*/ OPC_EmitNodeXForm, 1, 4, // LO12Sext
+/* 15674*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i32, 2/*#Ops*/, 3, 5,
+ // Src: (imm:{ *:[i32] })<<P:Predicate_simm32>>:$imm - Complexity = 4
+ // Dst: (ADDI:{ *:[i32] } (LUI:{ *:[i32] } (HI20:{ *:[i32] } (imm:{ *:[i32] }):$imm)), (LO12Sext:{ *:[i32] } (imm:{ *:[i32] }):$imm))
+/* 15682*/ 0, /*End of Scope*/
+/* 15683*/ /*SwitchType*/ 27, MVT::i64,// ->15712
+/* 15685*/ OPC_CheckPatternPredicate, 10, // (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 15687*/ OPC_EmitConvertToTarget, 0,
+/* 15689*/ OPC_EmitNodeXForm, 0, 1, // HI20
+/* 15692*/ OPC_EmitNode1, TARGET_VAL(RISCV::LUI), 0,
+ MVT::i64, 1/*#Ops*/, 2, // Results = #3
+/* 15699*/ OPC_EmitConvertToTarget, 0,
+/* 15701*/ OPC_EmitNodeXForm, 1, 4, // LO12Sext
+/* 15704*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::ADDI), 0,
+ MVT::i64, 2/*#Ops*/, 3, 5,
+ // Src: (imm:{ *:[i64] })<<P:Predicate_simm32>>:$imm - Complexity = 4
+ // Dst: (ADDI:{ *:[i64] } (LUI:{ *:[i64] } (HI20:{ *:[i64] } (imm:{ *:[i64] }):$imm)), (LO12Sext:{ *:[i64] } (imm:{ *:[i64] }):$imm))
+/* 15712*/ 0, // EndSwitchType
+/* 15713*/ 0, /*End of Scope*/
+/* 15714*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_SWAP),// ->16191
+/* 15718*/ OPC_RecordMemRef,
+/* 15719*/ OPC_RecordNode, // #0 = 'atomic_swap' chained node
+/* 15720*/ OPC_RecordChild1, // #1 = $rs1
+/* 15721*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->16032
+/* 15725*/ OPC_CheckChild1Type, MVT::i32,
+/* 15727*/ OPC_RecordChild2, // #2 = $rs2
+/* 15728*/ OPC_Scope, 21|128,1/*149*/, /*->15880*/ // 2 children in Scope
+/* 15731*/ OPC_CheckPredicate, 10, // Predicate_atomic_swap_32
+/* 15733*/ OPC_Scope, 28, /*->15763*/ // 5 children in Scope
+/* 15735*/ OPC_CheckPredicate, 20, // Predicate_atomic_swap_32_monotonic
+/* 15737*/ OPC_Scope, 11, /*->15750*/ // 2 children in Scope
+/* 15739*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15741*/ OPC_EmitMergeInputChains1_0,
+/* 15742*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> - Complexity = 4
+ // Dst: (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15750*/ /*Scope*/ 11, /*->15762*/
+/* 15751*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 15753*/ OPC_EmitMergeInputChains1_0,
+/* 15754*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> - Complexity = 4
+ // Dst: (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15762*/ 0, /*End of Scope*/
+/* 15763*/ /*Scope*/ 28, /*->15792*/
+/* 15764*/ OPC_CheckPredicate, 21, // Predicate_atomic_swap_32_acquire
+/* 15766*/ OPC_Scope, 11, /*->15779*/ // 2 children in Scope
+/* 15768*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15770*/ OPC_EmitMergeInputChains1_0,
+/* 15771*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15779*/ /*Scope*/ 11, /*->15791*/
+/* 15780*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 15782*/ OPC_EmitMergeInputChains1_0,
+/* 15783*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15791*/ 0, /*End of Scope*/
+/* 15792*/ /*Scope*/ 28, /*->15821*/
+/* 15793*/ OPC_CheckPredicate, 22, // Predicate_atomic_swap_32_release
+/* 15795*/ OPC_Scope, 11, /*->15808*/ // 2 children in Scope
+/* 15797*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15799*/ OPC_EmitMergeInputChains1_0,
+/* 15800*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> - Complexity = 4
+ // Dst: (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15808*/ /*Scope*/ 11, /*->15820*/
+/* 15809*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 15811*/ OPC_EmitMergeInputChains1_0,
+/* 15812*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> - Complexity = 4
+ // Dst: (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15820*/ 0, /*End of Scope*/
+/* 15821*/ /*Scope*/ 28, /*->15850*/
+/* 15822*/ OPC_CheckPredicate, 23, // Predicate_atomic_swap_32_acq_rel
+/* 15824*/ OPC_Scope, 11, /*->15837*/ // 2 children in Scope
+/* 15826*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15828*/ OPC_EmitMergeInputChains1_0,
+/* 15829*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15837*/ /*Scope*/ 11, /*->15849*/
+/* 15838*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 15840*/ OPC_EmitMergeInputChains1_0,
+/* 15841*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15849*/ 0, /*End of Scope*/
+/* 15850*/ /*Scope*/ 28, /*->15879*/
+/* 15851*/ OPC_CheckPredicate, 24, // Predicate_atomic_swap_32_seq_cst
+/* 15853*/ OPC_Scope, 11, /*->15866*/ // 2 children in Scope
+/* 15855*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15857*/ OPC_EmitMergeInputChains1_0,
+/* 15858*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15866*/ /*Scope*/ 11, /*->15878*/
+/* 15867*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 15869*/ OPC_EmitMergeInputChains1_0,
+/* 15870*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15878*/ 0, /*End of Scope*/
+/* 15879*/ 0, /*End of Scope*/
+/* 15880*/ /*Scope*/ 21|128,1/*149*/, /*->16031*/
+/* 15882*/ OPC_CheckPredicate, 14, // Predicate_atomic_swap_64
+/* 15884*/ OPC_Scope, 28, /*->15914*/ // 5 children in Scope
+/* 15886*/ OPC_CheckPredicate, 20, // Predicate_atomic_swap_64_monotonic
+/* 15888*/ OPC_Scope, 11, /*->15901*/ // 2 children in Scope
+/* 15890*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15892*/ OPC_EmitMergeInputChains1_0,
+/* 15893*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> - Complexity = 4
+ // Dst: (AMOSWAP_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15901*/ /*Scope*/ 11, /*->15913*/
+/* 15902*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 15904*/ OPC_EmitMergeInputChains1_0,
+/* 15905*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> - Complexity = 4
+ // Dst: (AMOSWAP_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15913*/ 0, /*End of Scope*/
+/* 15914*/ /*Scope*/ 28, /*->15943*/
+/* 15915*/ OPC_CheckPredicate, 21, // Predicate_atomic_swap_64_acquire
+/* 15917*/ OPC_Scope, 11, /*->15930*/ // 2 children in Scope
+/* 15919*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15921*/ OPC_EmitMergeInputChains1_0,
+/* 15922*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15930*/ /*Scope*/ 11, /*->15942*/
+/* 15931*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 15933*/ OPC_EmitMergeInputChains1_0,
+/* 15934*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15942*/ 0, /*End of Scope*/
+/* 15943*/ /*Scope*/ 28, /*->15972*/
+/* 15944*/ OPC_CheckPredicate, 22, // Predicate_atomic_swap_64_release
+/* 15946*/ OPC_Scope, 11, /*->15959*/ // 2 children in Scope
+/* 15948*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15950*/ OPC_EmitMergeInputChains1_0,
+/* 15951*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> - Complexity = 4
+ // Dst: (AMOSWAP_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15959*/ /*Scope*/ 11, /*->15971*/
+/* 15960*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 15962*/ OPC_EmitMergeInputChains1_0,
+/* 15963*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> - Complexity = 4
+ // Dst: (AMOSWAP_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15971*/ 0, /*End of Scope*/
+/* 15972*/ /*Scope*/ 28, /*->16001*/
+/* 15973*/ OPC_CheckPredicate, 23, // Predicate_atomic_swap_64_acq_rel
+/* 15975*/ OPC_Scope, 11, /*->15988*/ // 2 children in Scope
+/* 15977*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 15979*/ OPC_EmitMergeInputChains1_0,
+/* 15980*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 15988*/ /*Scope*/ 11, /*->16000*/
+/* 15989*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 15991*/ OPC_EmitMergeInputChains1_0,
+/* 15992*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16000*/ 0, /*End of Scope*/
+/* 16001*/ /*Scope*/ 28, /*->16030*/
+/* 16002*/ OPC_CheckPredicate, 24, // Predicate_atomic_swap_64_seq_cst
+/* 16004*/ OPC_Scope, 11, /*->16017*/ // 2 children in Scope
+/* 16006*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16008*/ OPC_EmitMergeInputChains1_0,
+/* 16009*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16017*/ /*Scope*/ 11, /*->16029*/
+/* 16018*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16020*/ OPC_EmitMergeInputChains1_0,
+/* 16021*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16029*/ 0, /*End of Scope*/
+/* 16030*/ 0, /*End of Scope*/
+/* 16031*/ 0, /*End of Scope*/
+/* 16032*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->16190
+/* 16035*/ OPC_CheckChild1Type, MVT::i64,
+/* 16037*/ OPC_RecordChild2, // #2 = $rs2
+/* 16038*/ OPC_Scope, 74, /*->16114*/ // 2 children in Scope
+/* 16040*/ OPC_CheckPredicate, 10, // Predicate_atomic_swap_32
+/* 16042*/ OPC_Scope, 13, /*->16057*/ // 5 children in Scope
+/* 16044*/ OPC_CheckPredicate, 20, // Predicate_atomic_swap_32_monotonic
+/* 16046*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16048*/ OPC_EmitMergeInputChains1_0,
+/* 16049*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> - Complexity = 4
+ // Dst: (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16057*/ /*Scope*/ 13, /*->16071*/
+/* 16058*/ OPC_CheckPredicate, 21, // Predicate_atomic_swap_32_acquire
+/* 16060*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16062*/ OPC_EmitMergeInputChains1_0,
+/* 16063*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16071*/ /*Scope*/ 13, /*->16085*/
+/* 16072*/ OPC_CheckPredicate, 22, // Predicate_atomic_swap_32_release
+/* 16074*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16076*/ OPC_EmitMergeInputChains1_0,
+/* 16077*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> - Complexity = 4
+ // Dst: (AMOSWAP_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16085*/ /*Scope*/ 13, /*->16099*/
+/* 16086*/ OPC_CheckPredicate, 23, // Predicate_atomic_swap_32_acq_rel
+/* 16088*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16090*/ OPC_EmitMergeInputChains1_0,
+/* 16091*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16099*/ /*Scope*/ 13, /*->16113*/
+/* 16100*/ OPC_CheckPredicate, 24, // Predicate_atomic_swap_32_seq_cst
+/* 16102*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16104*/ OPC_EmitMergeInputChains1_0,
+/* 16105*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16113*/ 0, /*End of Scope*/
+/* 16114*/ /*Scope*/ 74, /*->16189*/
+/* 16115*/ OPC_CheckPredicate, 14, // Predicate_atomic_swap_64
+/* 16117*/ OPC_Scope, 13, /*->16132*/ // 5 children in Scope
+/* 16119*/ OPC_CheckPredicate, 20, // Predicate_atomic_swap_64_monotonic
+/* 16121*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16123*/ OPC_EmitMergeInputChains1_0,
+/* 16124*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> - Complexity = 4
+ // Dst: (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16132*/ /*Scope*/ 13, /*->16146*/
+/* 16133*/ OPC_CheckPredicate, 21, // Predicate_atomic_swap_64_acquire
+/* 16135*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16137*/ OPC_EmitMergeInputChains1_0,
+/* 16138*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16146*/ /*Scope*/ 13, /*->16160*/
+/* 16147*/ OPC_CheckPredicate, 22, // Predicate_atomic_swap_64_release
+/* 16149*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16151*/ OPC_EmitMergeInputChains1_0,
+/* 16152*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> - Complexity = 4
+ // Dst: (AMOSWAP_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16160*/ /*Scope*/ 13, /*->16174*/
+/* 16161*/ OPC_CheckPredicate, 23, // Predicate_atomic_swap_64_acq_rel
+/* 16163*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16165*/ OPC_EmitMergeInputChains1_0,
+/* 16166*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16174*/ /*Scope*/ 13, /*->16188*/
+/* 16175*/ OPC_CheckPredicate, 24, // Predicate_atomic_swap_64_seq_cst
+/* 16177*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16179*/ OPC_EmitMergeInputChains1_0,
+/* 16180*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOSWAP_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16188*/ 0, /*End of Scope*/
+/* 16189*/ 0, /*End of Scope*/
+/* 16190*/ 0, // EndSwitchType
+/* 16191*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_ADD),// ->16668
+/* 16195*/ OPC_RecordMemRef,
+/* 16196*/ OPC_RecordNode, // #0 = 'atomic_load_add' chained node
+/* 16197*/ OPC_RecordChild1, // #1 = $rs1
+/* 16198*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->16509
+/* 16202*/ OPC_CheckChild1Type, MVT::i32,
+/* 16204*/ OPC_RecordChild2, // #2 = $rs2
+/* 16205*/ OPC_Scope, 21|128,1/*149*/, /*->16357*/ // 2 children in Scope
+/* 16208*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_add_32
+/* 16210*/ OPC_Scope, 28, /*->16240*/ // 5 children in Scope
+/* 16212*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_add_32_monotonic
+/* 16214*/ OPC_Scope, 11, /*->16227*/ // 2 children in Scope
+/* 16216*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16218*/ OPC_EmitMergeInputChains1_0,
+/* 16219*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16227*/ /*Scope*/ 11, /*->16239*/
+/* 16228*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16230*/ OPC_EmitMergeInputChains1_0,
+/* 16231*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16239*/ 0, /*End of Scope*/
+/* 16240*/ /*Scope*/ 28, /*->16269*/
+/* 16241*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_add_32_acquire
+/* 16243*/ OPC_Scope, 11, /*->16256*/ // 2 children in Scope
+/* 16245*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16247*/ OPC_EmitMergeInputChains1_0,
+/* 16248*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16256*/ /*Scope*/ 11, /*->16268*/
+/* 16257*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16259*/ OPC_EmitMergeInputChains1_0,
+/* 16260*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16268*/ 0, /*End of Scope*/
+/* 16269*/ /*Scope*/ 28, /*->16298*/
+/* 16270*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_add_32_release
+/* 16272*/ OPC_Scope, 11, /*->16285*/ // 2 children in Scope
+/* 16274*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16276*/ OPC_EmitMergeInputChains1_0,
+/* 16277*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> - Complexity = 4
+ // Dst: (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16285*/ /*Scope*/ 11, /*->16297*/
+/* 16286*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16288*/ OPC_EmitMergeInputChains1_0,
+/* 16289*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> - Complexity = 4
+ // Dst: (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16297*/ 0, /*End of Scope*/
+/* 16298*/ /*Scope*/ 28, /*->16327*/
+/* 16299*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_add_32_acq_rel
+/* 16301*/ OPC_Scope, 11, /*->16314*/ // 2 children in Scope
+/* 16303*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16305*/ OPC_EmitMergeInputChains1_0,
+/* 16306*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16314*/ /*Scope*/ 11, /*->16326*/
+/* 16315*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16317*/ OPC_EmitMergeInputChains1_0,
+/* 16318*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16326*/ 0, /*End of Scope*/
+/* 16327*/ /*Scope*/ 28, /*->16356*/
+/* 16328*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_add_32_seq_cst
+/* 16330*/ OPC_Scope, 11, /*->16343*/ // 2 children in Scope
+/* 16332*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16334*/ OPC_EmitMergeInputChains1_0,
+/* 16335*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16343*/ /*Scope*/ 11, /*->16355*/
+/* 16344*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16346*/ OPC_EmitMergeInputChains1_0,
+/* 16347*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16355*/ 0, /*End of Scope*/
+/* 16356*/ 0, /*End of Scope*/
+/* 16357*/ /*Scope*/ 21|128,1/*149*/, /*->16508*/
+/* 16359*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_add_64
+/* 16361*/ OPC_Scope, 28, /*->16391*/ // 5 children in Scope
+/* 16363*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_add_64_monotonic
+/* 16365*/ OPC_Scope, 11, /*->16378*/ // 2 children in Scope
+/* 16367*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16369*/ OPC_EmitMergeInputChains1_0,
+/* 16370*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16378*/ /*Scope*/ 11, /*->16390*/
+/* 16379*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16381*/ OPC_EmitMergeInputChains1_0,
+/* 16382*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16390*/ 0, /*End of Scope*/
+/* 16391*/ /*Scope*/ 28, /*->16420*/
+/* 16392*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_add_64_acquire
+/* 16394*/ OPC_Scope, 11, /*->16407*/ // 2 children in Scope
+/* 16396*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16398*/ OPC_EmitMergeInputChains1_0,
+/* 16399*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16407*/ /*Scope*/ 11, /*->16419*/
+/* 16408*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16410*/ OPC_EmitMergeInputChains1_0,
+/* 16411*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16419*/ 0, /*End of Scope*/
+/* 16420*/ /*Scope*/ 28, /*->16449*/
+/* 16421*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_add_64_release
+/* 16423*/ OPC_Scope, 11, /*->16436*/ // 2 children in Scope
+/* 16425*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16427*/ OPC_EmitMergeInputChains1_0,
+/* 16428*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> - Complexity = 4
+ // Dst: (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16436*/ /*Scope*/ 11, /*->16448*/
+/* 16437*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16439*/ OPC_EmitMergeInputChains1_0,
+/* 16440*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> - Complexity = 4
+ // Dst: (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16448*/ 0, /*End of Scope*/
+/* 16449*/ /*Scope*/ 28, /*->16478*/
+/* 16450*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_add_64_acq_rel
+/* 16452*/ OPC_Scope, 11, /*->16465*/ // 2 children in Scope
+/* 16454*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16456*/ OPC_EmitMergeInputChains1_0,
+/* 16457*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16465*/ /*Scope*/ 11, /*->16477*/
+/* 16466*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16468*/ OPC_EmitMergeInputChains1_0,
+/* 16469*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16477*/ 0, /*End of Scope*/
+/* 16478*/ /*Scope*/ 28, /*->16507*/
+/* 16479*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_add_64_seq_cst
+/* 16481*/ OPC_Scope, 11, /*->16494*/ // 2 children in Scope
+/* 16483*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16485*/ OPC_EmitMergeInputChains1_0,
+/* 16486*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16494*/ /*Scope*/ 11, /*->16506*/
+/* 16495*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16497*/ OPC_EmitMergeInputChains1_0,
+/* 16498*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16506*/ 0, /*End of Scope*/
+/* 16507*/ 0, /*End of Scope*/
+/* 16508*/ 0, /*End of Scope*/
+/* 16509*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->16667
+/* 16512*/ OPC_CheckChild1Type, MVT::i64,
+/* 16514*/ OPC_RecordChild2, // #2 = $rs2
+/* 16515*/ OPC_Scope, 74, /*->16591*/ // 2 children in Scope
+/* 16517*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_add_32
+/* 16519*/ OPC_Scope, 13, /*->16534*/ // 5 children in Scope
+/* 16521*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_add_32_monotonic
+/* 16523*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16525*/ OPC_EmitMergeInputChains1_0,
+/* 16526*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16534*/ /*Scope*/ 13, /*->16548*/
+/* 16535*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_add_32_acquire
+/* 16537*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16539*/ OPC_EmitMergeInputChains1_0,
+/* 16540*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16548*/ /*Scope*/ 13, /*->16562*/
+/* 16549*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_add_32_release
+/* 16551*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16553*/ OPC_EmitMergeInputChains1_0,
+/* 16554*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> - Complexity = 4
+ // Dst: (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16562*/ /*Scope*/ 13, /*->16576*/
+/* 16563*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_add_32_acq_rel
+/* 16565*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16567*/ OPC_EmitMergeInputChains1_0,
+/* 16568*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16576*/ /*Scope*/ 13, /*->16590*/
+/* 16577*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_add_32_seq_cst
+/* 16579*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16581*/ OPC_EmitMergeInputChains1_0,
+/* 16582*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16590*/ 0, /*End of Scope*/
+/* 16591*/ /*Scope*/ 74, /*->16666*/
+/* 16592*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_add_64
+/* 16594*/ OPC_Scope, 13, /*->16609*/ // 5 children in Scope
+/* 16596*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_add_64_monotonic
+/* 16598*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16600*/ OPC_EmitMergeInputChains1_0,
+/* 16601*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16609*/ /*Scope*/ 13, /*->16623*/
+/* 16610*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_add_64_acquire
+/* 16612*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16614*/ OPC_EmitMergeInputChains1_0,
+/* 16615*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16623*/ /*Scope*/ 13, /*->16637*/
+/* 16624*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_add_64_release
+/* 16626*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16628*/ OPC_EmitMergeInputChains1_0,
+/* 16629*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> - Complexity = 4
+ // Dst: (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16637*/ /*Scope*/ 13, /*->16651*/
+/* 16638*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_add_64_acq_rel
+/* 16640*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16642*/ OPC_EmitMergeInputChains1_0,
+/* 16643*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16651*/ /*Scope*/ 13, /*->16665*/
+/* 16652*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_add_64_seq_cst
+/* 16654*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 16656*/ OPC_EmitMergeInputChains1_0,
+/* 16657*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 16665*/ 0, /*End of Scope*/
+/* 16666*/ 0, /*End of Scope*/
+/* 16667*/ 0, // EndSwitchType
+/* 16668*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_AND),// ->17145
+/* 16672*/ OPC_RecordMemRef,
+/* 16673*/ OPC_RecordNode, // #0 = 'atomic_load_and' chained node
+/* 16674*/ OPC_RecordChild1, // #1 = $rs1
+/* 16675*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->16986
+/* 16679*/ OPC_CheckChild1Type, MVT::i32,
+/* 16681*/ OPC_RecordChild2, // #2 = $rs2
+/* 16682*/ OPC_Scope, 21|128,1/*149*/, /*->16834*/ // 2 children in Scope
+/* 16685*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_and_32
+/* 16687*/ OPC_Scope, 28, /*->16717*/ // 5 children in Scope
+/* 16689*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_and_32_monotonic
+/* 16691*/ OPC_Scope, 11, /*->16704*/ // 2 children in Scope
+/* 16693*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16695*/ OPC_EmitMergeInputChains1_0,
+/* 16696*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> - Complexity = 4
+ // Dst: (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16704*/ /*Scope*/ 11, /*->16716*/
+/* 16705*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16707*/ OPC_EmitMergeInputChains1_0,
+/* 16708*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> - Complexity = 4
+ // Dst: (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16716*/ 0, /*End of Scope*/
+/* 16717*/ /*Scope*/ 28, /*->16746*/
+/* 16718*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_and_32_acquire
+/* 16720*/ OPC_Scope, 11, /*->16733*/ // 2 children in Scope
+/* 16722*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16724*/ OPC_EmitMergeInputChains1_0,
+/* 16725*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16733*/ /*Scope*/ 11, /*->16745*/
+/* 16734*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16736*/ OPC_EmitMergeInputChains1_0,
+/* 16737*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16745*/ 0, /*End of Scope*/
+/* 16746*/ /*Scope*/ 28, /*->16775*/
+/* 16747*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_and_32_release
+/* 16749*/ OPC_Scope, 11, /*->16762*/ // 2 children in Scope
+/* 16751*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16753*/ OPC_EmitMergeInputChains1_0,
+/* 16754*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> - Complexity = 4
+ // Dst: (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16762*/ /*Scope*/ 11, /*->16774*/
+/* 16763*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16765*/ OPC_EmitMergeInputChains1_0,
+/* 16766*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> - Complexity = 4
+ // Dst: (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16774*/ 0, /*End of Scope*/
+/* 16775*/ /*Scope*/ 28, /*->16804*/
+/* 16776*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_and_32_acq_rel
+/* 16778*/ OPC_Scope, 11, /*->16791*/ // 2 children in Scope
+/* 16780*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16782*/ OPC_EmitMergeInputChains1_0,
+/* 16783*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16791*/ /*Scope*/ 11, /*->16803*/
+/* 16792*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16794*/ OPC_EmitMergeInputChains1_0,
+/* 16795*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16803*/ 0, /*End of Scope*/
+/* 16804*/ /*Scope*/ 28, /*->16833*/
+/* 16805*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_and_32_seq_cst
+/* 16807*/ OPC_Scope, 11, /*->16820*/ // 2 children in Scope
+/* 16809*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16811*/ OPC_EmitMergeInputChains1_0,
+/* 16812*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16820*/ /*Scope*/ 11, /*->16832*/
+/* 16821*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 16823*/ OPC_EmitMergeInputChains1_0,
+/* 16824*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16832*/ 0, /*End of Scope*/
+/* 16833*/ 0, /*End of Scope*/
+/* 16834*/ /*Scope*/ 21|128,1/*149*/, /*->16985*/
+/* 16836*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_and_64
+/* 16838*/ OPC_Scope, 28, /*->16868*/ // 5 children in Scope
+/* 16840*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_and_64_monotonic
+/* 16842*/ OPC_Scope, 11, /*->16855*/ // 2 children in Scope
+/* 16844*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16846*/ OPC_EmitMergeInputChains1_0,
+/* 16847*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> - Complexity = 4
+ // Dst: (AMOAND_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16855*/ /*Scope*/ 11, /*->16867*/
+/* 16856*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16858*/ OPC_EmitMergeInputChains1_0,
+/* 16859*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> - Complexity = 4
+ // Dst: (AMOAND_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16867*/ 0, /*End of Scope*/
+/* 16868*/ /*Scope*/ 28, /*->16897*/
+/* 16869*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_and_64_acquire
+/* 16871*/ OPC_Scope, 11, /*->16884*/ // 2 children in Scope
+/* 16873*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16875*/ OPC_EmitMergeInputChains1_0,
+/* 16876*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16884*/ /*Scope*/ 11, /*->16896*/
+/* 16885*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16887*/ OPC_EmitMergeInputChains1_0,
+/* 16888*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16896*/ 0, /*End of Scope*/
+/* 16897*/ /*Scope*/ 28, /*->16926*/
+/* 16898*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_and_64_release
+/* 16900*/ OPC_Scope, 11, /*->16913*/ // 2 children in Scope
+/* 16902*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16904*/ OPC_EmitMergeInputChains1_0,
+/* 16905*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> - Complexity = 4
+ // Dst: (AMOAND_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16913*/ /*Scope*/ 11, /*->16925*/
+/* 16914*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16916*/ OPC_EmitMergeInputChains1_0,
+/* 16917*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> - Complexity = 4
+ // Dst: (AMOAND_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16925*/ 0, /*End of Scope*/
+/* 16926*/ /*Scope*/ 28, /*->16955*/
+/* 16927*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_and_64_acq_rel
+/* 16929*/ OPC_Scope, 11, /*->16942*/ // 2 children in Scope
+/* 16931*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16933*/ OPC_EmitMergeInputChains1_0,
+/* 16934*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16942*/ /*Scope*/ 11, /*->16954*/
+/* 16943*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16945*/ OPC_EmitMergeInputChains1_0,
+/* 16946*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16954*/ 0, /*End of Scope*/
+/* 16955*/ /*Scope*/ 28, /*->16984*/
+/* 16956*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_and_64_seq_cst
+/* 16958*/ OPC_Scope, 11, /*->16971*/ // 2 children in Scope
+/* 16960*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 16962*/ OPC_EmitMergeInputChains1_0,
+/* 16963*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16971*/ /*Scope*/ 11, /*->16983*/
+/* 16972*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 16974*/ OPC_EmitMergeInputChains1_0,
+/* 16975*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 16983*/ 0, /*End of Scope*/
+/* 16984*/ 0, /*End of Scope*/
+/* 16985*/ 0, /*End of Scope*/
+/* 16986*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->17144
+/* 16989*/ OPC_CheckChild1Type, MVT::i64,
+/* 16991*/ OPC_RecordChild2, // #2 = $rs2
+/* 16992*/ OPC_Scope, 74, /*->17068*/ // 2 children in Scope
+/* 16994*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_and_32
+/* 16996*/ OPC_Scope, 13, /*->17011*/ // 5 children in Scope
+/* 16998*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_and_32_monotonic
+/* 17000*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17002*/ OPC_EmitMergeInputChains1_0,
+/* 17003*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> - Complexity = 4
+ // Dst: (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17011*/ /*Scope*/ 13, /*->17025*/
+/* 17012*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_and_32_acquire
+/* 17014*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17016*/ OPC_EmitMergeInputChains1_0,
+/* 17017*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17025*/ /*Scope*/ 13, /*->17039*/
+/* 17026*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_and_32_release
+/* 17028*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17030*/ OPC_EmitMergeInputChains1_0,
+/* 17031*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> - Complexity = 4
+ // Dst: (AMOAND_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17039*/ /*Scope*/ 13, /*->17053*/
+/* 17040*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_and_32_acq_rel
+/* 17042*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17044*/ OPC_EmitMergeInputChains1_0,
+/* 17045*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17053*/ /*Scope*/ 13, /*->17067*/
+/* 17054*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_and_32_seq_cst
+/* 17056*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17058*/ OPC_EmitMergeInputChains1_0,
+/* 17059*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17067*/ 0, /*End of Scope*/
+/* 17068*/ /*Scope*/ 74, /*->17143*/
+/* 17069*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_and_64
+/* 17071*/ OPC_Scope, 13, /*->17086*/ // 5 children in Scope
+/* 17073*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_and_64_monotonic
+/* 17075*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17077*/ OPC_EmitMergeInputChains1_0,
+/* 17078*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> - Complexity = 4
+ // Dst: (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17086*/ /*Scope*/ 13, /*->17100*/
+/* 17087*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_and_64_acquire
+/* 17089*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17091*/ OPC_EmitMergeInputChains1_0,
+/* 17092*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17100*/ /*Scope*/ 13, /*->17114*/
+/* 17101*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_and_64_release
+/* 17103*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17105*/ OPC_EmitMergeInputChains1_0,
+/* 17106*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> - Complexity = 4
+ // Dst: (AMOAND_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17114*/ /*Scope*/ 13, /*->17128*/
+/* 17115*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_and_64_acq_rel
+/* 17117*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17119*/ OPC_EmitMergeInputChains1_0,
+/* 17120*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17128*/ /*Scope*/ 13, /*->17142*/
+/* 17129*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_and_64_seq_cst
+/* 17131*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17133*/ OPC_EmitMergeInputChains1_0,
+/* 17134*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOAND_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17142*/ 0, /*End of Scope*/
+/* 17143*/ 0, /*End of Scope*/
+/* 17144*/ 0, // EndSwitchType
+/* 17145*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_OR),// ->17622
+/* 17149*/ OPC_RecordMemRef,
+/* 17150*/ OPC_RecordNode, // #0 = 'atomic_load_or' chained node
+/* 17151*/ OPC_RecordChild1, // #1 = $rs1
+/* 17152*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->17463
+/* 17156*/ OPC_CheckChild1Type, MVT::i32,
+/* 17158*/ OPC_RecordChild2, // #2 = $rs2
+/* 17159*/ OPC_Scope, 21|128,1/*149*/, /*->17311*/ // 2 children in Scope
+/* 17162*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_or_32
+/* 17164*/ OPC_Scope, 28, /*->17194*/ // 5 children in Scope
+/* 17166*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_or_32_monotonic
+/* 17168*/ OPC_Scope, 11, /*->17181*/ // 2 children in Scope
+/* 17170*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17172*/ OPC_EmitMergeInputChains1_0,
+/* 17173*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> - Complexity = 4
+ // Dst: (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17181*/ /*Scope*/ 11, /*->17193*/
+/* 17182*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17184*/ OPC_EmitMergeInputChains1_0,
+/* 17185*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> - Complexity = 4
+ // Dst: (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17193*/ 0, /*End of Scope*/
+/* 17194*/ /*Scope*/ 28, /*->17223*/
+/* 17195*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_or_32_acquire
+/* 17197*/ OPC_Scope, 11, /*->17210*/ // 2 children in Scope
+/* 17199*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17201*/ OPC_EmitMergeInputChains1_0,
+/* 17202*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17210*/ /*Scope*/ 11, /*->17222*/
+/* 17211*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17213*/ OPC_EmitMergeInputChains1_0,
+/* 17214*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17222*/ 0, /*End of Scope*/
+/* 17223*/ /*Scope*/ 28, /*->17252*/
+/* 17224*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_or_32_release
+/* 17226*/ OPC_Scope, 11, /*->17239*/ // 2 children in Scope
+/* 17228*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17230*/ OPC_EmitMergeInputChains1_0,
+/* 17231*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> - Complexity = 4
+ // Dst: (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17239*/ /*Scope*/ 11, /*->17251*/
+/* 17240*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17242*/ OPC_EmitMergeInputChains1_0,
+/* 17243*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> - Complexity = 4
+ // Dst: (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17251*/ 0, /*End of Scope*/
+/* 17252*/ /*Scope*/ 28, /*->17281*/
+/* 17253*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_or_32_acq_rel
+/* 17255*/ OPC_Scope, 11, /*->17268*/ // 2 children in Scope
+/* 17257*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17259*/ OPC_EmitMergeInputChains1_0,
+/* 17260*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17268*/ /*Scope*/ 11, /*->17280*/
+/* 17269*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17271*/ OPC_EmitMergeInputChains1_0,
+/* 17272*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17280*/ 0, /*End of Scope*/
+/* 17281*/ /*Scope*/ 28, /*->17310*/
+/* 17282*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_or_32_seq_cst
+/* 17284*/ OPC_Scope, 11, /*->17297*/ // 2 children in Scope
+/* 17286*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17288*/ OPC_EmitMergeInputChains1_0,
+/* 17289*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17297*/ /*Scope*/ 11, /*->17309*/
+/* 17298*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17300*/ OPC_EmitMergeInputChains1_0,
+/* 17301*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17309*/ 0, /*End of Scope*/
+/* 17310*/ 0, /*End of Scope*/
+/* 17311*/ /*Scope*/ 21|128,1/*149*/, /*->17462*/
+/* 17313*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_or_64
+/* 17315*/ OPC_Scope, 28, /*->17345*/ // 5 children in Scope
+/* 17317*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_or_64_monotonic
+/* 17319*/ OPC_Scope, 11, /*->17332*/ // 2 children in Scope
+/* 17321*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17323*/ OPC_EmitMergeInputChains1_0,
+/* 17324*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> - Complexity = 4
+ // Dst: (AMOOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17332*/ /*Scope*/ 11, /*->17344*/
+/* 17333*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17335*/ OPC_EmitMergeInputChains1_0,
+/* 17336*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> - Complexity = 4
+ // Dst: (AMOOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17344*/ 0, /*End of Scope*/
+/* 17345*/ /*Scope*/ 28, /*->17374*/
+/* 17346*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_or_64_acquire
+/* 17348*/ OPC_Scope, 11, /*->17361*/ // 2 children in Scope
+/* 17350*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17352*/ OPC_EmitMergeInputChains1_0,
+/* 17353*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17361*/ /*Scope*/ 11, /*->17373*/
+/* 17362*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17364*/ OPC_EmitMergeInputChains1_0,
+/* 17365*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17373*/ 0, /*End of Scope*/
+/* 17374*/ /*Scope*/ 28, /*->17403*/
+/* 17375*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_or_64_release
+/* 17377*/ OPC_Scope, 11, /*->17390*/ // 2 children in Scope
+/* 17379*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17381*/ OPC_EmitMergeInputChains1_0,
+/* 17382*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> - Complexity = 4
+ // Dst: (AMOOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17390*/ /*Scope*/ 11, /*->17402*/
+/* 17391*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17393*/ OPC_EmitMergeInputChains1_0,
+/* 17394*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> - Complexity = 4
+ // Dst: (AMOOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17402*/ 0, /*End of Scope*/
+/* 17403*/ /*Scope*/ 28, /*->17432*/
+/* 17404*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_or_64_acq_rel
+/* 17406*/ OPC_Scope, 11, /*->17419*/ // 2 children in Scope
+/* 17408*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17410*/ OPC_EmitMergeInputChains1_0,
+/* 17411*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17419*/ /*Scope*/ 11, /*->17431*/
+/* 17420*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17422*/ OPC_EmitMergeInputChains1_0,
+/* 17423*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17431*/ 0, /*End of Scope*/
+/* 17432*/ /*Scope*/ 28, /*->17461*/
+/* 17433*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_or_64_seq_cst
+/* 17435*/ OPC_Scope, 11, /*->17448*/ // 2 children in Scope
+/* 17437*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17439*/ OPC_EmitMergeInputChains1_0,
+/* 17440*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17448*/ /*Scope*/ 11, /*->17460*/
+/* 17449*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17451*/ OPC_EmitMergeInputChains1_0,
+/* 17452*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17460*/ 0, /*End of Scope*/
+/* 17461*/ 0, /*End of Scope*/
+/* 17462*/ 0, /*End of Scope*/
+/* 17463*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->17621
+/* 17466*/ OPC_CheckChild1Type, MVT::i64,
+/* 17468*/ OPC_RecordChild2, // #2 = $rs2
+/* 17469*/ OPC_Scope, 74, /*->17545*/ // 2 children in Scope
+/* 17471*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_or_32
+/* 17473*/ OPC_Scope, 13, /*->17488*/ // 5 children in Scope
+/* 17475*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_or_32_monotonic
+/* 17477*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17479*/ OPC_EmitMergeInputChains1_0,
+/* 17480*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> - Complexity = 4
+ // Dst: (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17488*/ /*Scope*/ 13, /*->17502*/
+/* 17489*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_or_32_acquire
+/* 17491*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17493*/ OPC_EmitMergeInputChains1_0,
+/* 17494*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17502*/ /*Scope*/ 13, /*->17516*/
+/* 17503*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_or_32_release
+/* 17505*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17507*/ OPC_EmitMergeInputChains1_0,
+/* 17508*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> - Complexity = 4
+ // Dst: (AMOOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17516*/ /*Scope*/ 13, /*->17530*/
+/* 17517*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_or_32_acq_rel
+/* 17519*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17521*/ OPC_EmitMergeInputChains1_0,
+/* 17522*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17530*/ /*Scope*/ 13, /*->17544*/
+/* 17531*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_or_32_seq_cst
+/* 17533*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17535*/ OPC_EmitMergeInputChains1_0,
+/* 17536*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17544*/ 0, /*End of Scope*/
+/* 17545*/ /*Scope*/ 74, /*->17620*/
+/* 17546*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_or_64
+/* 17548*/ OPC_Scope, 13, /*->17563*/ // 5 children in Scope
+/* 17550*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_or_64_monotonic
+/* 17552*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17554*/ OPC_EmitMergeInputChains1_0,
+/* 17555*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> - Complexity = 4
+ // Dst: (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17563*/ /*Scope*/ 13, /*->17577*/
+/* 17564*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_or_64_acquire
+/* 17566*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17568*/ OPC_EmitMergeInputChains1_0,
+/* 17569*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17577*/ /*Scope*/ 13, /*->17591*/
+/* 17578*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_or_64_release
+/* 17580*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17582*/ OPC_EmitMergeInputChains1_0,
+/* 17583*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> - Complexity = 4
+ // Dst: (AMOOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17591*/ /*Scope*/ 13, /*->17605*/
+/* 17592*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_or_64_acq_rel
+/* 17594*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17596*/ OPC_EmitMergeInputChains1_0,
+/* 17597*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17605*/ /*Scope*/ 13, /*->17619*/
+/* 17606*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_or_64_seq_cst
+/* 17608*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17610*/ OPC_EmitMergeInputChains1_0,
+/* 17611*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17619*/ 0, /*End of Scope*/
+/* 17620*/ 0, /*End of Scope*/
+/* 17621*/ 0, // EndSwitchType
+/* 17622*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_XOR),// ->18099
+/* 17626*/ OPC_RecordMemRef,
+/* 17627*/ OPC_RecordNode, // #0 = 'atomic_load_xor' chained node
+/* 17628*/ OPC_RecordChild1, // #1 = $rs1
+/* 17629*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->17940
+/* 17633*/ OPC_CheckChild1Type, MVT::i32,
+/* 17635*/ OPC_RecordChild2, // #2 = $rs2
+/* 17636*/ OPC_Scope, 21|128,1/*149*/, /*->17788*/ // 2 children in Scope
+/* 17639*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_xor_32
+/* 17641*/ OPC_Scope, 28, /*->17671*/ // 5 children in Scope
+/* 17643*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_xor_32_monotonic
+/* 17645*/ OPC_Scope, 11, /*->17658*/ // 2 children in Scope
+/* 17647*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17649*/ OPC_EmitMergeInputChains1_0,
+/* 17650*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> - Complexity = 4
+ // Dst: (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17658*/ /*Scope*/ 11, /*->17670*/
+/* 17659*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17661*/ OPC_EmitMergeInputChains1_0,
+/* 17662*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> - Complexity = 4
+ // Dst: (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17670*/ 0, /*End of Scope*/
+/* 17671*/ /*Scope*/ 28, /*->17700*/
+/* 17672*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_xor_32_acquire
+/* 17674*/ OPC_Scope, 11, /*->17687*/ // 2 children in Scope
+/* 17676*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17678*/ OPC_EmitMergeInputChains1_0,
+/* 17679*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17687*/ /*Scope*/ 11, /*->17699*/
+/* 17688*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17690*/ OPC_EmitMergeInputChains1_0,
+/* 17691*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17699*/ 0, /*End of Scope*/
+/* 17700*/ /*Scope*/ 28, /*->17729*/
+/* 17701*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_xor_32_release
+/* 17703*/ OPC_Scope, 11, /*->17716*/ // 2 children in Scope
+/* 17705*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17707*/ OPC_EmitMergeInputChains1_0,
+/* 17708*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> - Complexity = 4
+ // Dst: (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17716*/ /*Scope*/ 11, /*->17728*/
+/* 17717*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17719*/ OPC_EmitMergeInputChains1_0,
+/* 17720*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> - Complexity = 4
+ // Dst: (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17728*/ 0, /*End of Scope*/
+/* 17729*/ /*Scope*/ 28, /*->17758*/
+/* 17730*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_xor_32_acq_rel
+/* 17732*/ OPC_Scope, 11, /*->17745*/ // 2 children in Scope
+/* 17734*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17736*/ OPC_EmitMergeInputChains1_0,
+/* 17737*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17745*/ /*Scope*/ 11, /*->17757*/
+/* 17746*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17748*/ OPC_EmitMergeInputChains1_0,
+/* 17749*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17757*/ 0, /*End of Scope*/
+/* 17758*/ /*Scope*/ 28, /*->17787*/
+/* 17759*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_xor_32_seq_cst
+/* 17761*/ OPC_Scope, 11, /*->17774*/ // 2 children in Scope
+/* 17763*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17765*/ OPC_EmitMergeInputChains1_0,
+/* 17766*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17774*/ /*Scope*/ 11, /*->17786*/
+/* 17775*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 17777*/ OPC_EmitMergeInputChains1_0,
+/* 17778*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17786*/ 0, /*End of Scope*/
+/* 17787*/ 0, /*End of Scope*/
+/* 17788*/ /*Scope*/ 21|128,1/*149*/, /*->17939*/
+/* 17790*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_xor_64
+/* 17792*/ OPC_Scope, 28, /*->17822*/ // 5 children in Scope
+/* 17794*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_xor_64_monotonic
+/* 17796*/ OPC_Scope, 11, /*->17809*/ // 2 children in Scope
+/* 17798*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17800*/ OPC_EmitMergeInputChains1_0,
+/* 17801*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> - Complexity = 4
+ // Dst: (AMOXOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17809*/ /*Scope*/ 11, /*->17821*/
+/* 17810*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17812*/ OPC_EmitMergeInputChains1_0,
+/* 17813*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> - Complexity = 4
+ // Dst: (AMOXOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17821*/ 0, /*End of Scope*/
+/* 17822*/ /*Scope*/ 28, /*->17851*/
+/* 17823*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_xor_64_acquire
+/* 17825*/ OPC_Scope, 11, /*->17838*/ // 2 children in Scope
+/* 17827*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17829*/ OPC_EmitMergeInputChains1_0,
+/* 17830*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17838*/ /*Scope*/ 11, /*->17850*/
+/* 17839*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17841*/ OPC_EmitMergeInputChains1_0,
+/* 17842*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17850*/ 0, /*End of Scope*/
+/* 17851*/ /*Scope*/ 28, /*->17880*/
+/* 17852*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_xor_64_release
+/* 17854*/ OPC_Scope, 11, /*->17867*/ // 2 children in Scope
+/* 17856*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17858*/ OPC_EmitMergeInputChains1_0,
+/* 17859*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> - Complexity = 4
+ // Dst: (AMOXOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17867*/ /*Scope*/ 11, /*->17879*/
+/* 17868*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17870*/ OPC_EmitMergeInputChains1_0,
+/* 17871*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> - Complexity = 4
+ // Dst: (AMOXOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17879*/ 0, /*End of Scope*/
+/* 17880*/ /*Scope*/ 28, /*->17909*/
+/* 17881*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_xor_64_acq_rel
+/* 17883*/ OPC_Scope, 11, /*->17896*/ // 2 children in Scope
+/* 17885*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17887*/ OPC_EmitMergeInputChains1_0,
+/* 17888*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17896*/ /*Scope*/ 11, /*->17908*/
+/* 17897*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17899*/ OPC_EmitMergeInputChains1_0,
+/* 17900*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17908*/ 0, /*End of Scope*/
+/* 17909*/ /*Scope*/ 28, /*->17938*/
+/* 17910*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_xor_64_seq_cst
+/* 17912*/ OPC_Scope, 11, /*->17925*/ // 2 children in Scope
+/* 17914*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 17916*/ OPC_EmitMergeInputChains1_0,
+/* 17917*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17925*/ /*Scope*/ 11, /*->17937*/
+/* 17926*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 17928*/ OPC_EmitMergeInputChains1_0,
+/* 17929*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 17937*/ 0, /*End of Scope*/
+/* 17938*/ 0, /*End of Scope*/
+/* 17939*/ 0, /*End of Scope*/
+/* 17940*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->18098
+/* 17943*/ OPC_CheckChild1Type, MVT::i64,
+/* 17945*/ OPC_RecordChild2, // #2 = $rs2
+/* 17946*/ OPC_Scope, 74, /*->18022*/ // 2 children in Scope
+/* 17948*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_xor_32
+/* 17950*/ OPC_Scope, 13, /*->17965*/ // 5 children in Scope
+/* 17952*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_xor_32_monotonic
+/* 17954*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17956*/ OPC_EmitMergeInputChains1_0,
+/* 17957*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> - Complexity = 4
+ // Dst: (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17965*/ /*Scope*/ 13, /*->17979*/
+/* 17966*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_xor_32_acquire
+/* 17968*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17970*/ OPC_EmitMergeInputChains1_0,
+/* 17971*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17979*/ /*Scope*/ 13, /*->17993*/
+/* 17980*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_xor_32_release
+/* 17982*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17984*/ OPC_EmitMergeInputChains1_0,
+/* 17985*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> - Complexity = 4
+ // Dst: (AMOXOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 17993*/ /*Scope*/ 13, /*->18007*/
+/* 17994*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_xor_32_acq_rel
+/* 17996*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 17998*/ OPC_EmitMergeInputChains1_0,
+/* 17999*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18007*/ /*Scope*/ 13, /*->18021*/
+/* 18008*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_xor_32_seq_cst
+/* 18010*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18012*/ OPC_EmitMergeInputChains1_0,
+/* 18013*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18021*/ 0, /*End of Scope*/
+/* 18022*/ /*Scope*/ 74, /*->18097*/
+/* 18023*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_xor_64
+/* 18025*/ OPC_Scope, 13, /*->18040*/ // 5 children in Scope
+/* 18027*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_xor_64_monotonic
+/* 18029*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18031*/ OPC_EmitMergeInputChains1_0,
+/* 18032*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> - Complexity = 4
+ // Dst: (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18040*/ /*Scope*/ 13, /*->18054*/
+/* 18041*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_xor_64_acquire
+/* 18043*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18045*/ OPC_EmitMergeInputChains1_0,
+/* 18046*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18054*/ /*Scope*/ 13, /*->18068*/
+/* 18055*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_xor_64_release
+/* 18057*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18059*/ OPC_EmitMergeInputChains1_0,
+/* 18060*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> - Complexity = 4
+ // Dst: (AMOXOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18068*/ /*Scope*/ 13, /*->18082*/
+/* 18069*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_xor_64_acq_rel
+/* 18071*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18073*/ OPC_EmitMergeInputChains1_0,
+/* 18074*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18082*/ /*Scope*/ 13, /*->18096*/
+/* 18083*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_xor_64_seq_cst
+/* 18085*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18087*/ OPC_EmitMergeInputChains1_0,
+/* 18088*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOXOR_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18096*/ 0, /*End of Scope*/
+/* 18097*/ 0, /*End of Scope*/
+/* 18098*/ 0, // EndSwitchType
+/* 18099*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_MAX),// ->18576
+/* 18103*/ OPC_RecordMemRef,
+/* 18104*/ OPC_RecordNode, // #0 = 'atomic_load_max' chained node
+/* 18105*/ OPC_RecordChild1, // #1 = $rs1
+/* 18106*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->18417
+/* 18110*/ OPC_CheckChild1Type, MVT::i32,
+/* 18112*/ OPC_RecordChild2, // #2 = $rs2
+/* 18113*/ OPC_Scope, 21|128,1/*149*/, /*->18265*/ // 2 children in Scope
+/* 18116*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_max_32
+/* 18118*/ OPC_Scope, 28, /*->18148*/ // 5 children in Scope
+/* 18120*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_max_32_monotonic
+/* 18122*/ OPC_Scope, 11, /*->18135*/ // 2 children in Scope
+/* 18124*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18126*/ OPC_EmitMergeInputChains1_0,
+/* 18127*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18135*/ /*Scope*/ 11, /*->18147*/
+/* 18136*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18138*/ OPC_EmitMergeInputChains1_0,
+/* 18139*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18147*/ 0, /*End of Scope*/
+/* 18148*/ /*Scope*/ 28, /*->18177*/
+/* 18149*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_max_32_acquire
+/* 18151*/ OPC_Scope, 11, /*->18164*/ // 2 children in Scope
+/* 18153*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18155*/ OPC_EmitMergeInputChains1_0,
+/* 18156*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18164*/ /*Scope*/ 11, /*->18176*/
+/* 18165*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18167*/ OPC_EmitMergeInputChains1_0,
+/* 18168*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18176*/ 0, /*End of Scope*/
+/* 18177*/ /*Scope*/ 28, /*->18206*/
+/* 18178*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_max_32_release
+/* 18180*/ OPC_Scope, 11, /*->18193*/ // 2 children in Scope
+/* 18182*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18184*/ OPC_EmitMergeInputChains1_0,
+/* 18185*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> - Complexity = 4
+ // Dst: (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18193*/ /*Scope*/ 11, /*->18205*/
+/* 18194*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18196*/ OPC_EmitMergeInputChains1_0,
+/* 18197*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> - Complexity = 4
+ // Dst: (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18205*/ 0, /*End of Scope*/
+/* 18206*/ /*Scope*/ 28, /*->18235*/
+/* 18207*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_max_32_acq_rel
+/* 18209*/ OPC_Scope, 11, /*->18222*/ // 2 children in Scope
+/* 18211*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18213*/ OPC_EmitMergeInputChains1_0,
+/* 18214*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18222*/ /*Scope*/ 11, /*->18234*/
+/* 18223*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18225*/ OPC_EmitMergeInputChains1_0,
+/* 18226*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18234*/ 0, /*End of Scope*/
+/* 18235*/ /*Scope*/ 28, /*->18264*/
+/* 18236*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_max_32_seq_cst
+/* 18238*/ OPC_Scope, 11, /*->18251*/ // 2 children in Scope
+/* 18240*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18242*/ OPC_EmitMergeInputChains1_0,
+/* 18243*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18251*/ /*Scope*/ 11, /*->18263*/
+/* 18252*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18254*/ OPC_EmitMergeInputChains1_0,
+/* 18255*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18263*/ 0, /*End of Scope*/
+/* 18264*/ 0, /*End of Scope*/
+/* 18265*/ /*Scope*/ 21|128,1/*149*/, /*->18416*/
+/* 18267*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_max_64
+/* 18269*/ OPC_Scope, 28, /*->18299*/ // 5 children in Scope
+/* 18271*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_max_64_monotonic
+/* 18273*/ OPC_Scope, 11, /*->18286*/ // 2 children in Scope
+/* 18275*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18277*/ OPC_EmitMergeInputChains1_0,
+/* 18278*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMAX_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18286*/ /*Scope*/ 11, /*->18298*/
+/* 18287*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18289*/ OPC_EmitMergeInputChains1_0,
+/* 18290*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMAX_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18298*/ 0, /*End of Scope*/
+/* 18299*/ /*Scope*/ 28, /*->18328*/
+/* 18300*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_max_64_acquire
+/* 18302*/ OPC_Scope, 11, /*->18315*/ // 2 children in Scope
+/* 18304*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18306*/ OPC_EmitMergeInputChains1_0,
+/* 18307*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18315*/ /*Scope*/ 11, /*->18327*/
+/* 18316*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18318*/ OPC_EmitMergeInputChains1_0,
+/* 18319*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18327*/ 0, /*End of Scope*/
+/* 18328*/ /*Scope*/ 28, /*->18357*/
+/* 18329*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_max_64_release
+/* 18331*/ OPC_Scope, 11, /*->18344*/ // 2 children in Scope
+/* 18333*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18335*/ OPC_EmitMergeInputChains1_0,
+/* 18336*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> - Complexity = 4
+ // Dst: (AMOMAX_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18344*/ /*Scope*/ 11, /*->18356*/
+/* 18345*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18347*/ OPC_EmitMergeInputChains1_0,
+/* 18348*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> - Complexity = 4
+ // Dst: (AMOMAX_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18356*/ 0, /*End of Scope*/
+/* 18357*/ /*Scope*/ 28, /*->18386*/
+/* 18358*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_max_64_acq_rel
+/* 18360*/ OPC_Scope, 11, /*->18373*/ // 2 children in Scope
+/* 18362*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18364*/ OPC_EmitMergeInputChains1_0,
+/* 18365*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18373*/ /*Scope*/ 11, /*->18385*/
+/* 18374*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18376*/ OPC_EmitMergeInputChains1_0,
+/* 18377*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18385*/ 0, /*End of Scope*/
+/* 18386*/ /*Scope*/ 28, /*->18415*/
+/* 18387*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_max_64_seq_cst
+/* 18389*/ OPC_Scope, 11, /*->18402*/ // 2 children in Scope
+/* 18391*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18393*/ OPC_EmitMergeInputChains1_0,
+/* 18394*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18402*/ /*Scope*/ 11, /*->18414*/
+/* 18403*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18405*/ OPC_EmitMergeInputChains1_0,
+/* 18406*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18414*/ 0, /*End of Scope*/
+/* 18415*/ 0, /*End of Scope*/
+/* 18416*/ 0, /*End of Scope*/
+/* 18417*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->18575
+/* 18420*/ OPC_CheckChild1Type, MVT::i64,
+/* 18422*/ OPC_RecordChild2, // #2 = $rs2
+/* 18423*/ OPC_Scope, 74, /*->18499*/ // 2 children in Scope
+/* 18425*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_max_32
+/* 18427*/ OPC_Scope, 13, /*->18442*/ // 5 children in Scope
+/* 18429*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_max_32_monotonic
+/* 18431*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18433*/ OPC_EmitMergeInputChains1_0,
+/* 18434*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18442*/ /*Scope*/ 13, /*->18456*/
+/* 18443*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_max_32_acquire
+/* 18445*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18447*/ OPC_EmitMergeInputChains1_0,
+/* 18448*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18456*/ /*Scope*/ 13, /*->18470*/
+/* 18457*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_max_32_release
+/* 18459*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18461*/ OPC_EmitMergeInputChains1_0,
+/* 18462*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> - Complexity = 4
+ // Dst: (AMOMAX_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18470*/ /*Scope*/ 13, /*->18484*/
+/* 18471*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_max_32_acq_rel
+/* 18473*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18475*/ OPC_EmitMergeInputChains1_0,
+/* 18476*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18484*/ /*Scope*/ 13, /*->18498*/
+/* 18485*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_max_32_seq_cst
+/* 18487*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18489*/ OPC_EmitMergeInputChains1_0,
+/* 18490*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18498*/ 0, /*End of Scope*/
+/* 18499*/ /*Scope*/ 74, /*->18574*/
+/* 18500*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_max_64
+/* 18502*/ OPC_Scope, 13, /*->18517*/ // 5 children in Scope
+/* 18504*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_max_64_monotonic
+/* 18506*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18508*/ OPC_EmitMergeInputChains1_0,
+/* 18509*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18517*/ /*Scope*/ 13, /*->18531*/
+/* 18518*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_max_64_acquire
+/* 18520*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18522*/ OPC_EmitMergeInputChains1_0,
+/* 18523*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18531*/ /*Scope*/ 13, /*->18545*/
+/* 18532*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_max_64_release
+/* 18534*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18536*/ OPC_EmitMergeInputChains1_0,
+/* 18537*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> - Complexity = 4
+ // Dst: (AMOMAX_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18545*/ /*Scope*/ 13, /*->18559*/
+/* 18546*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_max_64_acq_rel
+/* 18548*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18550*/ OPC_EmitMergeInputChains1_0,
+/* 18551*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18559*/ /*Scope*/ 13, /*->18573*/
+/* 18560*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_max_64_seq_cst
+/* 18562*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18564*/ OPC_EmitMergeInputChains1_0,
+/* 18565*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAX_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18573*/ 0, /*End of Scope*/
+/* 18574*/ 0, /*End of Scope*/
+/* 18575*/ 0, // EndSwitchType
+/* 18576*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_MIN),// ->19053
+/* 18580*/ OPC_RecordMemRef,
+/* 18581*/ OPC_RecordNode, // #0 = 'atomic_load_min' chained node
+/* 18582*/ OPC_RecordChild1, // #1 = $rs1
+/* 18583*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->18894
+/* 18587*/ OPC_CheckChild1Type, MVT::i32,
+/* 18589*/ OPC_RecordChild2, // #2 = $rs2
+/* 18590*/ OPC_Scope, 21|128,1/*149*/, /*->18742*/ // 2 children in Scope
+/* 18593*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_min_32
+/* 18595*/ OPC_Scope, 28, /*->18625*/ // 5 children in Scope
+/* 18597*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_min_32_monotonic
+/* 18599*/ OPC_Scope, 11, /*->18612*/ // 2 children in Scope
+/* 18601*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18603*/ OPC_EmitMergeInputChains1_0,
+/* 18604*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18612*/ /*Scope*/ 11, /*->18624*/
+/* 18613*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18615*/ OPC_EmitMergeInputChains1_0,
+/* 18616*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18624*/ 0, /*End of Scope*/
+/* 18625*/ /*Scope*/ 28, /*->18654*/
+/* 18626*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_min_32_acquire
+/* 18628*/ OPC_Scope, 11, /*->18641*/ // 2 children in Scope
+/* 18630*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18632*/ OPC_EmitMergeInputChains1_0,
+/* 18633*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18641*/ /*Scope*/ 11, /*->18653*/
+/* 18642*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18644*/ OPC_EmitMergeInputChains1_0,
+/* 18645*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18653*/ 0, /*End of Scope*/
+/* 18654*/ /*Scope*/ 28, /*->18683*/
+/* 18655*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_min_32_release
+/* 18657*/ OPC_Scope, 11, /*->18670*/ // 2 children in Scope
+/* 18659*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18661*/ OPC_EmitMergeInputChains1_0,
+/* 18662*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> - Complexity = 4
+ // Dst: (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18670*/ /*Scope*/ 11, /*->18682*/
+/* 18671*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18673*/ OPC_EmitMergeInputChains1_0,
+/* 18674*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> - Complexity = 4
+ // Dst: (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18682*/ 0, /*End of Scope*/
+/* 18683*/ /*Scope*/ 28, /*->18712*/
+/* 18684*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_min_32_acq_rel
+/* 18686*/ OPC_Scope, 11, /*->18699*/ // 2 children in Scope
+/* 18688*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18690*/ OPC_EmitMergeInputChains1_0,
+/* 18691*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18699*/ /*Scope*/ 11, /*->18711*/
+/* 18700*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18702*/ OPC_EmitMergeInputChains1_0,
+/* 18703*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18711*/ 0, /*End of Scope*/
+/* 18712*/ /*Scope*/ 28, /*->18741*/
+/* 18713*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_min_32_seq_cst
+/* 18715*/ OPC_Scope, 11, /*->18728*/ // 2 children in Scope
+/* 18717*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18719*/ OPC_EmitMergeInputChains1_0,
+/* 18720*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18728*/ /*Scope*/ 11, /*->18740*/
+/* 18729*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 18731*/ OPC_EmitMergeInputChains1_0,
+/* 18732*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18740*/ 0, /*End of Scope*/
+/* 18741*/ 0, /*End of Scope*/
+/* 18742*/ /*Scope*/ 21|128,1/*149*/, /*->18893*/
+/* 18744*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_min_64
+/* 18746*/ OPC_Scope, 28, /*->18776*/ // 5 children in Scope
+/* 18748*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_min_64_monotonic
+/* 18750*/ OPC_Scope, 11, /*->18763*/ // 2 children in Scope
+/* 18752*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18754*/ OPC_EmitMergeInputChains1_0,
+/* 18755*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMIN_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18763*/ /*Scope*/ 11, /*->18775*/
+/* 18764*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18766*/ OPC_EmitMergeInputChains1_0,
+/* 18767*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMIN_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18775*/ 0, /*End of Scope*/
+/* 18776*/ /*Scope*/ 28, /*->18805*/
+/* 18777*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_min_64_acquire
+/* 18779*/ OPC_Scope, 11, /*->18792*/ // 2 children in Scope
+/* 18781*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18783*/ OPC_EmitMergeInputChains1_0,
+/* 18784*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18792*/ /*Scope*/ 11, /*->18804*/
+/* 18793*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18795*/ OPC_EmitMergeInputChains1_0,
+/* 18796*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18804*/ 0, /*End of Scope*/
+/* 18805*/ /*Scope*/ 28, /*->18834*/
+/* 18806*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_min_64_release
+/* 18808*/ OPC_Scope, 11, /*->18821*/ // 2 children in Scope
+/* 18810*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18812*/ OPC_EmitMergeInputChains1_0,
+/* 18813*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> - Complexity = 4
+ // Dst: (AMOMIN_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18821*/ /*Scope*/ 11, /*->18833*/
+/* 18822*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18824*/ OPC_EmitMergeInputChains1_0,
+/* 18825*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> - Complexity = 4
+ // Dst: (AMOMIN_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18833*/ 0, /*End of Scope*/
+/* 18834*/ /*Scope*/ 28, /*->18863*/
+/* 18835*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_min_64_acq_rel
+/* 18837*/ OPC_Scope, 11, /*->18850*/ // 2 children in Scope
+/* 18839*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18841*/ OPC_EmitMergeInputChains1_0,
+/* 18842*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18850*/ /*Scope*/ 11, /*->18862*/
+/* 18851*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18853*/ OPC_EmitMergeInputChains1_0,
+/* 18854*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18862*/ 0, /*End of Scope*/
+/* 18863*/ /*Scope*/ 28, /*->18892*/
+/* 18864*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_min_64_seq_cst
+/* 18866*/ OPC_Scope, 11, /*->18879*/ // 2 children in Scope
+/* 18868*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 18870*/ OPC_EmitMergeInputChains1_0,
+/* 18871*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18879*/ /*Scope*/ 11, /*->18891*/
+/* 18880*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 18882*/ OPC_EmitMergeInputChains1_0,
+/* 18883*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 18891*/ 0, /*End of Scope*/
+/* 18892*/ 0, /*End of Scope*/
+/* 18893*/ 0, /*End of Scope*/
+/* 18894*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->19052
+/* 18897*/ OPC_CheckChild1Type, MVT::i64,
+/* 18899*/ OPC_RecordChild2, // #2 = $rs2
+/* 18900*/ OPC_Scope, 74, /*->18976*/ // 2 children in Scope
+/* 18902*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_min_32
+/* 18904*/ OPC_Scope, 13, /*->18919*/ // 5 children in Scope
+/* 18906*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_min_32_monotonic
+/* 18908*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18910*/ OPC_EmitMergeInputChains1_0,
+/* 18911*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18919*/ /*Scope*/ 13, /*->18933*/
+/* 18920*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_min_32_acquire
+/* 18922*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18924*/ OPC_EmitMergeInputChains1_0,
+/* 18925*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18933*/ /*Scope*/ 13, /*->18947*/
+/* 18934*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_min_32_release
+/* 18936*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18938*/ OPC_EmitMergeInputChains1_0,
+/* 18939*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> - Complexity = 4
+ // Dst: (AMOMIN_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18947*/ /*Scope*/ 13, /*->18961*/
+/* 18948*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_min_32_acq_rel
+/* 18950*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18952*/ OPC_EmitMergeInputChains1_0,
+/* 18953*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18961*/ /*Scope*/ 13, /*->18975*/
+/* 18962*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_min_32_seq_cst
+/* 18964*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18966*/ OPC_EmitMergeInputChains1_0,
+/* 18967*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18975*/ 0, /*End of Scope*/
+/* 18976*/ /*Scope*/ 74, /*->19051*/
+/* 18977*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_min_64
+/* 18979*/ OPC_Scope, 13, /*->18994*/ // 5 children in Scope
+/* 18981*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_min_64_monotonic
+/* 18983*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18985*/ OPC_EmitMergeInputChains1_0,
+/* 18986*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 18994*/ /*Scope*/ 13, /*->19008*/
+/* 18995*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_min_64_acquire
+/* 18997*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 18999*/ OPC_EmitMergeInputChains1_0,
+/* 19000*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19008*/ /*Scope*/ 13, /*->19022*/
+/* 19009*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_min_64_release
+/* 19011*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19013*/ OPC_EmitMergeInputChains1_0,
+/* 19014*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> - Complexity = 4
+ // Dst: (AMOMIN_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19022*/ /*Scope*/ 13, /*->19036*/
+/* 19023*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_min_64_acq_rel
+/* 19025*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19027*/ OPC_EmitMergeInputChains1_0,
+/* 19028*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19036*/ /*Scope*/ 13, /*->19050*/
+/* 19037*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_min_64_seq_cst
+/* 19039*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19041*/ OPC_EmitMergeInputChains1_0,
+/* 19042*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMIN_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19050*/ 0, /*End of Scope*/
+/* 19051*/ 0, /*End of Scope*/
+/* 19052*/ 0, // EndSwitchType
+/* 19053*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_UMAX),// ->19530
+/* 19057*/ OPC_RecordMemRef,
+/* 19058*/ OPC_RecordNode, // #0 = 'atomic_load_umax' chained node
+/* 19059*/ OPC_RecordChild1, // #1 = $rs1
+/* 19060*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->19371
+/* 19064*/ OPC_CheckChild1Type, MVT::i32,
+/* 19066*/ OPC_RecordChild2, // #2 = $rs2
+/* 19067*/ OPC_Scope, 21|128,1/*149*/, /*->19219*/ // 2 children in Scope
+/* 19070*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_umax_32
+/* 19072*/ OPC_Scope, 28, /*->19102*/ // 5 children in Scope
+/* 19074*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_umax_32_monotonic
+/* 19076*/ OPC_Scope, 11, /*->19089*/ // 2 children in Scope
+/* 19078*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19080*/ OPC_EmitMergeInputChains1_0,
+/* 19081*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19089*/ /*Scope*/ 11, /*->19101*/
+/* 19090*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19092*/ OPC_EmitMergeInputChains1_0,
+/* 19093*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19101*/ 0, /*End of Scope*/
+/* 19102*/ /*Scope*/ 28, /*->19131*/
+/* 19103*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_umax_32_acquire
+/* 19105*/ OPC_Scope, 11, /*->19118*/ // 2 children in Scope
+/* 19107*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19109*/ OPC_EmitMergeInputChains1_0,
+/* 19110*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19118*/ /*Scope*/ 11, /*->19130*/
+/* 19119*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19121*/ OPC_EmitMergeInputChains1_0,
+/* 19122*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19130*/ 0, /*End of Scope*/
+/* 19131*/ /*Scope*/ 28, /*->19160*/
+/* 19132*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_umax_32_release
+/* 19134*/ OPC_Scope, 11, /*->19147*/ // 2 children in Scope
+/* 19136*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19138*/ OPC_EmitMergeInputChains1_0,
+/* 19139*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> - Complexity = 4
+ // Dst: (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19147*/ /*Scope*/ 11, /*->19159*/
+/* 19148*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19150*/ OPC_EmitMergeInputChains1_0,
+/* 19151*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> - Complexity = 4
+ // Dst: (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19159*/ 0, /*End of Scope*/
+/* 19160*/ /*Scope*/ 28, /*->19189*/
+/* 19161*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_umax_32_acq_rel
+/* 19163*/ OPC_Scope, 11, /*->19176*/ // 2 children in Scope
+/* 19165*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19167*/ OPC_EmitMergeInputChains1_0,
+/* 19168*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19176*/ /*Scope*/ 11, /*->19188*/
+/* 19177*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19179*/ OPC_EmitMergeInputChains1_0,
+/* 19180*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19188*/ 0, /*End of Scope*/
+/* 19189*/ /*Scope*/ 28, /*->19218*/
+/* 19190*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_umax_32_seq_cst
+/* 19192*/ OPC_Scope, 11, /*->19205*/ // 2 children in Scope
+/* 19194*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19196*/ OPC_EmitMergeInputChains1_0,
+/* 19197*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19205*/ /*Scope*/ 11, /*->19217*/
+/* 19206*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19208*/ OPC_EmitMergeInputChains1_0,
+/* 19209*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19217*/ 0, /*End of Scope*/
+/* 19218*/ 0, /*End of Scope*/
+/* 19219*/ /*Scope*/ 21|128,1/*149*/, /*->19370*/
+/* 19221*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_umax_64
+/* 19223*/ OPC_Scope, 28, /*->19253*/ // 5 children in Scope
+/* 19225*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_umax_64_monotonic
+/* 19227*/ OPC_Scope, 11, /*->19240*/ // 2 children in Scope
+/* 19229*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19231*/ OPC_EmitMergeInputChains1_0,
+/* 19232*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMAXU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19240*/ /*Scope*/ 11, /*->19252*/
+/* 19241*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19243*/ OPC_EmitMergeInputChains1_0,
+/* 19244*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMAXU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19252*/ 0, /*End of Scope*/
+/* 19253*/ /*Scope*/ 28, /*->19282*/
+/* 19254*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_umax_64_acquire
+/* 19256*/ OPC_Scope, 11, /*->19269*/ // 2 children in Scope
+/* 19258*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19260*/ OPC_EmitMergeInputChains1_0,
+/* 19261*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19269*/ /*Scope*/ 11, /*->19281*/
+/* 19270*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19272*/ OPC_EmitMergeInputChains1_0,
+/* 19273*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19281*/ 0, /*End of Scope*/
+/* 19282*/ /*Scope*/ 28, /*->19311*/
+/* 19283*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_umax_64_release
+/* 19285*/ OPC_Scope, 11, /*->19298*/ // 2 children in Scope
+/* 19287*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19289*/ OPC_EmitMergeInputChains1_0,
+/* 19290*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> - Complexity = 4
+ // Dst: (AMOMAXU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19298*/ /*Scope*/ 11, /*->19310*/
+/* 19299*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19301*/ OPC_EmitMergeInputChains1_0,
+/* 19302*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> - Complexity = 4
+ // Dst: (AMOMAXU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19310*/ 0, /*End of Scope*/
+/* 19311*/ /*Scope*/ 28, /*->19340*/
+/* 19312*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_umax_64_acq_rel
+/* 19314*/ OPC_Scope, 11, /*->19327*/ // 2 children in Scope
+/* 19316*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19318*/ OPC_EmitMergeInputChains1_0,
+/* 19319*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19327*/ /*Scope*/ 11, /*->19339*/
+/* 19328*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19330*/ OPC_EmitMergeInputChains1_0,
+/* 19331*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19339*/ 0, /*End of Scope*/
+/* 19340*/ /*Scope*/ 28, /*->19369*/
+/* 19341*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_umax_64_seq_cst
+/* 19343*/ OPC_Scope, 11, /*->19356*/ // 2 children in Scope
+/* 19345*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19347*/ OPC_EmitMergeInputChains1_0,
+/* 19348*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19356*/ /*Scope*/ 11, /*->19368*/
+/* 19357*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19359*/ OPC_EmitMergeInputChains1_0,
+/* 19360*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19368*/ 0, /*End of Scope*/
+/* 19369*/ 0, /*End of Scope*/
+/* 19370*/ 0, /*End of Scope*/
+/* 19371*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->19529
+/* 19374*/ OPC_CheckChild1Type, MVT::i64,
+/* 19376*/ OPC_RecordChild2, // #2 = $rs2
+/* 19377*/ OPC_Scope, 74, /*->19453*/ // 2 children in Scope
+/* 19379*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_umax_32
+/* 19381*/ OPC_Scope, 13, /*->19396*/ // 5 children in Scope
+/* 19383*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_umax_32_monotonic
+/* 19385*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19387*/ OPC_EmitMergeInputChains1_0,
+/* 19388*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19396*/ /*Scope*/ 13, /*->19410*/
+/* 19397*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_umax_32_acquire
+/* 19399*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19401*/ OPC_EmitMergeInputChains1_0,
+/* 19402*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19410*/ /*Scope*/ 13, /*->19424*/
+/* 19411*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_umax_32_release
+/* 19413*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19415*/ OPC_EmitMergeInputChains1_0,
+/* 19416*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> - Complexity = 4
+ // Dst: (AMOMAXU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19424*/ /*Scope*/ 13, /*->19438*/
+/* 19425*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_umax_32_acq_rel
+/* 19427*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19429*/ OPC_EmitMergeInputChains1_0,
+/* 19430*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19438*/ /*Scope*/ 13, /*->19452*/
+/* 19439*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_umax_32_seq_cst
+/* 19441*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19443*/ OPC_EmitMergeInputChains1_0,
+/* 19444*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19452*/ 0, /*End of Scope*/
+/* 19453*/ /*Scope*/ 74, /*->19528*/
+/* 19454*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_umax_64
+/* 19456*/ OPC_Scope, 13, /*->19471*/ // 5 children in Scope
+/* 19458*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_umax_64_monotonic
+/* 19460*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19462*/ OPC_EmitMergeInputChains1_0,
+/* 19463*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19471*/ /*Scope*/ 13, /*->19485*/
+/* 19472*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_umax_64_acquire
+/* 19474*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19476*/ OPC_EmitMergeInputChains1_0,
+/* 19477*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19485*/ /*Scope*/ 13, /*->19499*/
+/* 19486*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_umax_64_release
+/* 19488*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19490*/ OPC_EmitMergeInputChains1_0,
+/* 19491*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> - Complexity = 4
+ // Dst: (AMOMAXU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19499*/ /*Scope*/ 13, /*->19513*/
+/* 19500*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_umax_64_acq_rel
+/* 19502*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19504*/ OPC_EmitMergeInputChains1_0,
+/* 19505*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19513*/ /*Scope*/ 13, /*->19527*/
+/* 19514*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_umax_64_seq_cst
+/* 19516*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19518*/ OPC_EmitMergeInputChains1_0,
+/* 19519*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMAXU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19527*/ 0, /*End of Scope*/
+/* 19528*/ 0, /*End of Scope*/
+/* 19529*/ 0, // EndSwitchType
+/* 19530*/ /*SwitchOpcode*/ 89|128,3/*473*/, TARGET_VAL(ISD::ATOMIC_LOAD_UMIN),// ->20007
+/* 19534*/ OPC_RecordMemRef,
+/* 19535*/ OPC_RecordNode, // #0 = 'atomic_load_umin' chained node
+/* 19536*/ OPC_RecordChild1, // #1 = $rs1
+/* 19537*/ OPC_SwitchType /*2 cases */, 51|128,2/*307*/, MVT::i32,// ->19848
+/* 19541*/ OPC_CheckChild1Type, MVT::i32,
+/* 19543*/ OPC_RecordChild2, // #2 = $rs2
+/* 19544*/ OPC_Scope, 21|128,1/*149*/, /*->19696*/ // 2 children in Scope
+/* 19547*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_umin_32
+/* 19549*/ OPC_Scope, 28, /*->19579*/ // 5 children in Scope
+/* 19551*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_umin_32_monotonic
+/* 19553*/ OPC_Scope, 11, /*->19566*/ // 2 children in Scope
+/* 19555*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19557*/ OPC_EmitMergeInputChains1_0,
+/* 19558*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19566*/ /*Scope*/ 11, /*->19578*/
+/* 19567*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19569*/ OPC_EmitMergeInputChains1_0,
+/* 19570*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19578*/ 0, /*End of Scope*/
+/* 19579*/ /*Scope*/ 28, /*->19608*/
+/* 19580*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_umin_32_acquire
+/* 19582*/ OPC_Scope, 11, /*->19595*/ // 2 children in Scope
+/* 19584*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19586*/ OPC_EmitMergeInputChains1_0,
+/* 19587*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19595*/ /*Scope*/ 11, /*->19607*/
+/* 19596*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19598*/ OPC_EmitMergeInputChains1_0,
+/* 19599*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19607*/ 0, /*End of Scope*/
+/* 19608*/ /*Scope*/ 28, /*->19637*/
+/* 19609*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_umin_32_release
+/* 19611*/ OPC_Scope, 11, /*->19624*/ // 2 children in Scope
+/* 19613*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19615*/ OPC_EmitMergeInputChains1_0,
+/* 19616*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> - Complexity = 4
+ // Dst: (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19624*/ /*Scope*/ 11, /*->19636*/
+/* 19625*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19627*/ OPC_EmitMergeInputChains1_0,
+/* 19628*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> - Complexity = 4
+ // Dst: (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19636*/ 0, /*End of Scope*/
+/* 19637*/ /*Scope*/ 28, /*->19666*/
+/* 19638*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_umin_32_acq_rel
+/* 19640*/ OPC_Scope, 11, /*->19653*/ // 2 children in Scope
+/* 19642*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19644*/ OPC_EmitMergeInputChains1_0,
+/* 19645*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19653*/ /*Scope*/ 11, /*->19665*/
+/* 19654*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19656*/ OPC_EmitMergeInputChains1_0,
+/* 19657*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19665*/ 0, /*End of Scope*/
+/* 19666*/ /*Scope*/ 28, /*->19695*/
+/* 19667*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_umin_32_seq_cst
+/* 19669*/ OPC_Scope, 11, /*->19682*/ // 2 children in Scope
+/* 19671*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19673*/ OPC_EmitMergeInputChains1_0,
+/* 19674*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19682*/ /*Scope*/ 11, /*->19694*/
+/* 19683*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 19685*/ OPC_EmitMergeInputChains1_0,
+/* 19686*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19694*/ 0, /*End of Scope*/
+/* 19695*/ 0, /*End of Scope*/
+/* 19696*/ /*Scope*/ 21|128,1/*149*/, /*->19847*/
+/* 19698*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_umin_64
+/* 19700*/ OPC_Scope, 28, /*->19730*/ // 5 children in Scope
+/* 19702*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_umin_64_monotonic
+/* 19704*/ OPC_Scope, 11, /*->19717*/ // 2 children in Scope
+/* 19706*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19708*/ OPC_EmitMergeInputChains1_0,
+/* 19709*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMINU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19717*/ /*Scope*/ 11, /*->19729*/
+/* 19718*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19720*/ OPC_EmitMergeInputChains1_0,
+/* 19721*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMINU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19729*/ 0, /*End of Scope*/
+/* 19730*/ /*Scope*/ 28, /*->19759*/
+/* 19731*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_umin_64_acquire
+/* 19733*/ OPC_Scope, 11, /*->19746*/ // 2 children in Scope
+/* 19735*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19737*/ OPC_EmitMergeInputChains1_0,
+/* 19738*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19746*/ /*Scope*/ 11, /*->19758*/
+/* 19747*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19749*/ OPC_EmitMergeInputChains1_0,
+/* 19750*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19758*/ 0, /*End of Scope*/
+/* 19759*/ /*Scope*/ 28, /*->19788*/
+/* 19760*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_umin_64_release
+/* 19762*/ OPC_Scope, 11, /*->19775*/ // 2 children in Scope
+/* 19764*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19766*/ OPC_EmitMergeInputChains1_0,
+/* 19767*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> - Complexity = 4
+ // Dst: (AMOMINU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19775*/ /*Scope*/ 11, /*->19787*/
+/* 19776*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19778*/ OPC_EmitMergeInputChains1_0,
+/* 19779*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> - Complexity = 4
+ // Dst: (AMOMINU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19787*/ 0, /*End of Scope*/
+/* 19788*/ /*Scope*/ 28, /*->19817*/
+/* 19789*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_umin_64_acq_rel
+/* 19791*/ OPC_Scope, 11, /*->19804*/ // 2 children in Scope
+/* 19793*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19795*/ OPC_EmitMergeInputChains1_0,
+/* 19796*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19804*/ /*Scope*/ 11, /*->19816*/
+/* 19805*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19807*/ OPC_EmitMergeInputChains1_0,
+/* 19808*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19816*/ 0, /*End of Scope*/
+/* 19817*/ /*Scope*/ 28, /*->19846*/
+/* 19818*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_umin_64_seq_cst
+/* 19820*/ OPC_Scope, 11, /*->19833*/ // 2 children in Scope
+/* 19822*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 19824*/ OPC_EmitMergeInputChains1_0,
+/* 19825*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19833*/ /*Scope*/ 11, /*->19845*/
+/* 19834*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 19836*/ OPC_EmitMergeInputChains1_0,
+/* 19837*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 19845*/ 0, /*End of Scope*/
+/* 19846*/ 0, /*End of Scope*/
+/* 19847*/ 0, /*End of Scope*/
+/* 19848*/ /*SwitchType*/ 27|128,1/*155*/, MVT::i64,// ->20006
+/* 19851*/ OPC_CheckChild1Type, MVT::i64,
+/* 19853*/ OPC_RecordChild2, // #2 = $rs2
+/* 19854*/ OPC_Scope, 74, /*->19930*/ // 2 children in Scope
+/* 19856*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_umin_32
+/* 19858*/ OPC_Scope, 13, /*->19873*/ // 5 children in Scope
+/* 19860*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_umin_32_monotonic
+/* 19862*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19864*/ OPC_EmitMergeInputChains1_0,
+/* 19865*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> - Complexity = 4
+ // Dst: (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19873*/ /*Scope*/ 13, /*->19887*/
+/* 19874*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_umin_32_acquire
+/* 19876*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19878*/ OPC_EmitMergeInputChains1_0,
+/* 19879*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19887*/ /*Scope*/ 13, /*->19901*/
+/* 19888*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_umin_32_release
+/* 19890*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19892*/ OPC_EmitMergeInputChains1_0,
+/* 19893*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> - Complexity = 4
+ // Dst: (AMOMINU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19901*/ /*Scope*/ 13, /*->19915*/
+/* 19902*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_umin_32_acq_rel
+/* 19904*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19906*/ OPC_EmitMergeInputChains1_0,
+/* 19907*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19915*/ /*Scope*/ 13, /*->19929*/
+/* 19916*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_umin_32_seq_cst
+/* 19918*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19920*/ OPC_EmitMergeInputChains1_0,
+/* 19921*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19929*/ 0, /*End of Scope*/
+/* 19930*/ /*Scope*/ 74, /*->20005*/
+/* 19931*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_umin_64
+/* 19933*/ OPC_Scope, 13, /*->19948*/ // 5 children in Scope
+/* 19935*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_umin_64_monotonic
+/* 19937*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19939*/ OPC_EmitMergeInputChains1_0,
+/* 19940*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> - Complexity = 4
+ // Dst: (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19948*/ /*Scope*/ 13, /*->19962*/
+/* 19949*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_umin_64_acquire
+/* 19951*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19953*/ OPC_EmitMergeInputChains1_0,
+/* 19954*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19962*/ /*Scope*/ 13, /*->19976*/
+/* 19963*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_umin_64_release
+/* 19965*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19967*/ OPC_EmitMergeInputChains1_0,
+/* 19968*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> - Complexity = 4
+ // Dst: (AMOMINU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19976*/ /*Scope*/ 13, /*->19990*/
+/* 19977*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_umin_64_acq_rel
+/* 19979*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19981*/ OPC_EmitMergeInputChains1_0,
+/* 19982*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 19990*/ /*Scope*/ 13, /*->20004*/
+/* 19991*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_umin_64_seq_cst
+/* 19993*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 19995*/ OPC_EmitMergeInputChains1_0,
+/* 19996*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOMINU_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 20004*/ 0, /*End of Scope*/
+/* 20005*/ 0, /*End of Scope*/
+/* 20006*/ 0, // EndSwitchType
+/* 20007*/ /*SwitchOpcode*/ 111|128,4/*623*/, TARGET_VAL(ISD::ATOMIC_LOAD_NAND),// ->20634
+/* 20011*/ OPC_RecordMemRef,
+/* 20012*/ OPC_RecordNode, // #0 = 'atomic_load_nand' chained node
+/* 20013*/ OPC_RecordChild1, // #1 = $addr
+/* 20014*/ OPC_SwitchType /*2 cases */, 23|128,3/*407*/, MVT::i32,// ->20425
+/* 20018*/ OPC_CheckChild1Type, MVT::i32,
+/* 20020*/ OPC_RecordChild2, // #2 = $incr
+/* 20021*/ OPC_Scope, 71|128,1/*199*/, /*->20223*/ // 2 children in Scope
+/* 20024*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_nand_32
+/* 20026*/ OPC_Scope, 38, /*->20066*/ // 5 children in Scope
+/* 20028*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_nand_32_monotonic
+/* 20030*/ OPC_Scope, 16, /*->20048*/ // 2 children in Scope
+/* 20032*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20034*/ OPC_EmitMergeInputChains1_0,
+/* 20035*/ OPC_EmitInteger, MVT::i32, 2,
+/* 20038*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_monotonic>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 2:{ *:[i32] })
+/* 20048*/ /*Scope*/ 16, /*->20065*/
+/* 20049*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20051*/ OPC_EmitMergeInputChains1_0,
+/* 20052*/ OPC_EmitInteger, MVT::i32, 2,
+/* 20055*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_monotonic>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 2:{ *:[i32] })
+/* 20065*/ 0, /*End of Scope*/
+/* 20066*/ /*Scope*/ 38, /*->20105*/
+/* 20067*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_nand_32_acquire
+/* 20069*/ OPC_Scope, 16, /*->20087*/ // 2 children in Scope
+/* 20071*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20073*/ OPC_EmitMergeInputChains1_0,
+/* 20074*/ OPC_EmitInteger, MVT::i32, 4,
+/* 20077*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acquire>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 4:{ *:[i32] })
+/* 20087*/ /*Scope*/ 16, /*->20104*/
+/* 20088*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20090*/ OPC_EmitMergeInputChains1_0,
+/* 20091*/ OPC_EmitInteger, MVT::i32, 4,
+/* 20094*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acquire>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 4:{ *:[i32] })
+/* 20104*/ 0, /*End of Scope*/
+/* 20105*/ /*Scope*/ 38, /*->20144*/
+/* 20106*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_nand_32_release
+/* 20108*/ OPC_Scope, 16, /*->20126*/ // 2 children in Scope
+/* 20110*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20112*/ OPC_EmitMergeInputChains1_0,
+/* 20113*/ OPC_EmitInteger, MVT::i32, 5,
+/* 20116*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_release>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 5:{ *:[i32] })
+/* 20126*/ /*Scope*/ 16, /*->20143*/
+/* 20127*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20129*/ OPC_EmitMergeInputChains1_0,
+/* 20130*/ OPC_EmitInteger, MVT::i32, 5,
+/* 20133*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_release>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 5:{ *:[i32] })
+/* 20143*/ 0, /*End of Scope*/
+/* 20144*/ /*Scope*/ 38, /*->20183*/
+/* 20145*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_nand_32_acq_rel
+/* 20147*/ OPC_Scope, 16, /*->20165*/ // 2 children in Scope
+/* 20149*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20151*/ OPC_EmitMergeInputChains1_0,
+/* 20152*/ OPC_EmitInteger, MVT::i32, 6,
+/* 20155*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acq_rel>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 6:{ *:[i32] })
+/* 20165*/ /*Scope*/ 16, /*->20182*/
+/* 20166*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20168*/ OPC_EmitMergeInputChains1_0,
+/* 20169*/ OPC_EmitInteger, MVT::i32, 6,
+/* 20172*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acq_rel>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 6:{ *:[i32] })
+/* 20182*/ 0, /*End of Scope*/
+/* 20183*/ /*Scope*/ 38, /*->20222*/
+/* 20184*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_nand_32_seq_cst
+/* 20186*/ OPC_Scope, 16, /*->20204*/ // 2 children in Scope
+/* 20188*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20190*/ OPC_EmitMergeInputChains1_0,
+/* 20191*/ OPC_EmitInteger, MVT::i32, 7,
+/* 20194*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_seq_cst>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 7:{ *:[i32] })
+/* 20204*/ /*Scope*/ 16, /*->20221*/
+/* 20205*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20207*/ OPC_EmitMergeInputChains1_0,
+/* 20208*/ OPC_EmitInteger, MVT::i32, 7,
+/* 20211*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_seq_cst>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 7:{ *:[i32] })
+/* 20221*/ 0, /*End of Scope*/
+/* 20222*/ 0, /*End of Scope*/
+/* 20223*/ /*Scope*/ 71|128,1/*199*/, /*->20424*/
+/* 20225*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_nand_64
+/* 20227*/ OPC_Scope, 38, /*->20267*/ // 5 children in Scope
+/* 20229*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_nand_64_monotonic
+/* 20231*/ OPC_Scope, 16, /*->20249*/ // 2 children in Scope
+/* 20233*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20235*/ OPC_EmitMergeInputChains1_0,
+/* 20236*/ OPC_EmitInteger, MVT::i32, 2,
+/* 20239*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_monotonic>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 2:{ *:[i32] })
+/* 20249*/ /*Scope*/ 16, /*->20266*/
+/* 20250*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 20252*/ OPC_EmitMergeInputChains1_0,
+/* 20253*/ OPC_EmitInteger, MVT::i32, 2,
+/* 20256*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_monotonic>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 2:{ *:[i32] })
+/* 20266*/ 0, /*End of Scope*/
+/* 20267*/ /*Scope*/ 38, /*->20306*/
+/* 20268*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_nand_64_acquire
+/* 20270*/ OPC_Scope, 16, /*->20288*/ // 2 children in Scope
+/* 20272*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20274*/ OPC_EmitMergeInputChains1_0,
+/* 20275*/ OPC_EmitInteger, MVT::i32, 4,
+/* 20278*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_acquire>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 4:{ *:[i32] })
+/* 20288*/ /*Scope*/ 16, /*->20305*/
+/* 20289*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 20291*/ OPC_EmitMergeInputChains1_0,
+/* 20292*/ OPC_EmitInteger, MVT::i32, 4,
+/* 20295*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_acquire>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 4:{ *:[i32] })
+/* 20305*/ 0, /*End of Scope*/
+/* 20306*/ /*Scope*/ 38, /*->20345*/
+/* 20307*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_nand_64_release
+/* 20309*/ OPC_Scope, 16, /*->20327*/ // 2 children in Scope
+/* 20311*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20313*/ OPC_EmitMergeInputChains1_0,
+/* 20314*/ OPC_EmitInteger, MVT::i32, 5,
+/* 20317*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_release>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 5:{ *:[i32] })
+/* 20327*/ /*Scope*/ 16, /*->20344*/
+/* 20328*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 20330*/ OPC_EmitMergeInputChains1_0,
+/* 20331*/ OPC_EmitInteger, MVT::i32, 5,
+/* 20334*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_release>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 5:{ *:[i32] })
+/* 20344*/ 0, /*End of Scope*/
+/* 20345*/ /*Scope*/ 38, /*->20384*/
+/* 20346*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_nand_64_acq_rel
+/* 20348*/ OPC_Scope, 16, /*->20366*/ // 2 children in Scope
+/* 20350*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20352*/ OPC_EmitMergeInputChains1_0,
+/* 20353*/ OPC_EmitInteger, MVT::i32, 6,
+/* 20356*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_acq_rel>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 6:{ *:[i32] })
+/* 20366*/ /*Scope*/ 16, /*->20383*/
+/* 20367*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 20369*/ OPC_EmitMergeInputChains1_0,
+/* 20370*/ OPC_EmitInteger, MVT::i32, 6,
+/* 20373*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_acq_rel>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 6:{ *:[i32] })
+/* 20383*/ 0, /*End of Scope*/
+/* 20384*/ /*Scope*/ 38, /*->20423*/
+/* 20385*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_nand_64_seq_cst
+/* 20387*/ OPC_Scope, 16, /*->20405*/ // 2 children in Scope
+/* 20389*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20391*/ OPC_EmitMergeInputChains1_0,
+/* 20392*/ OPC_EmitInteger, MVT::i32, 7,
+/* 20395*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_seq_cst>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 7:{ *:[i32] })
+/* 20405*/ /*Scope*/ 16, /*->20422*/
+/* 20406*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 20408*/ OPC_EmitMergeInputChains1_0,
+/* 20409*/ OPC_EmitInteger, MVT::i32, 7,
+/* 20412*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_seq_cst>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr, 7:{ *:[i32] })
+/* 20422*/ 0, /*End of Scope*/
+/* 20423*/ 0, /*End of Scope*/
+/* 20424*/ 0, /*End of Scope*/
+/* 20425*/ /*SwitchType*/ 77|128,1/*205*/, MVT::i64,// ->20633
+/* 20428*/ OPC_CheckChild1Type, MVT::i64,
+/* 20430*/ OPC_RecordChild2, // #2 = $incr
+/* 20431*/ OPC_Scope, 99, /*->20532*/ // 2 children in Scope
+/* 20433*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_nand_32
+/* 20435*/ OPC_Scope, 18, /*->20455*/ // 5 children in Scope
+/* 20437*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_nand_32_monotonic
+/* 20439*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20441*/ OPC_EmitMergeInputChains1_0,
+/* 20442*/ OPC_EmitInteger, MVT::i64, 2,
+/* 20445*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_monotonic>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 2:{ *:[i64] })
+/* 20455*/ /*Scope*/ 18, /*->20474*/
+/* 20456*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_nand_32_acquire
+/* 20458*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20460*/ OPC_EmitMergeInputChains1_0,
+/* 20461*/ OPC_EmitInteger, MVT::i64, 4,
+/* 20464*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acquire>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 4:{ *:[i64] })
+/* 20474*/ /*Scope*/ 18, /*->20493*/
+/* 20475*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_nand_32_release
+/* 20477*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20479*/ OPC_EmitMergeInputChains1_0,
+/* 20480*/ OPC_EmitInteger, MVT::i64, 5,
+/* 20483*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_release>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 5:{ *:[i64] })
+/* 20493*/ /*Scope*/ 18, /*->20512*/
+/* 20494*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_nand_32_acq_rel
+/* 20496*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20498*/ OPC_EmitMergeInputChains1_0,
+/* 20499*/ OPC_EmitInteger, MVT::i64, 6,
+/* 20502*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_acq_rel>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 6:{ *:[i64] })
+/* 20512*/ /*Scope*/ 18, /*->20531*/
+/* 20513*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_nand_32_seq_cst
+/* 20515*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20517*/ OPC_EmitMergeInputChains1_0,
+/* 20518*/ OPC_EmitInteger, MVT::i64, 7,
+/* 20521*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_32>><<P:Predicate_atomic_load_nand_32_seq_cst>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 7:{ *:[i64] })
+/* 20531*/ 0, /*End of Scope*/
+/* 20532*/ /*Scope*/ 99, /*->20632*/
+/* 20533*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_nand_64
+/* 20535*/ OPC_Scope, 18, /*->20555*/ // 5 children in Scope
+/* 20537*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_nand_64_monotonic
+/* 20539*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20541*/ OPC_EmitMergeInputChains1_0,
+/* 20542*/ OPC_EmitInteger, MVT::i64, 2,
+/* 20545*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_monotonic>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 2:{ *:[i64] })
+/* 20555*/ /*Scope*/ 18, /*->20574*/
+/* 20556*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_nand_64_acquire
+/* 20558*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20560*/ OPC_EmitMergeInputChains1_0,
+/* 20561*/ OPC_EmitInteger, MVT::i64, 4,
+/* 20564*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_acquire>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 4:{ *:[i64] })
+/* 20574*/ /*Scope*/ 18, /*->20593*/
+/* 20575*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_nand_64_release
+/* 20577*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20579*/ OPC_EmitMergeInputChains1_0,
+/* 20580*/ OPC_EmitInteger, MVT::i64, 5,
+/* 20583*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_release>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 5:{ *:[i64] })
+/* 20593*/ /*Scope*/ 18, /*->20612*/
+/* 20594*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_nand_64_acq_rel
+/* 20596*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20598*/ OPC_EmitMergeInputChains1_0,
+/* 20599*/ OPC_EmitInteger, MVT::i64, 6,
+/* 20602*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_acq_rel>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 6:{ *:[i64] })
+/* 20612*/ /*Scope*/ 18, /*->20631*/
+/* 20613*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_nand_64_seq_cst
+/* 20615*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 20617*/ OPC_EmitMergeInputChains1_0,
+/* 20618*/ OPC_EmitInteger, MVT::i64, 7,
+/* 20621*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoAtomicLoadNand64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 3/*#Ops*/, 1, 2, 3,
+ // Src: (atomic_load_nand:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_64>><<P:Predicate_atomic_load_nand_64_seq_cst>> - Complexity = 4
+ // Dst: (PseudoAtomicLoadNand64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr, 7:{ *:[i64] })
+/* 20631*/ 0, /*End of Scope*/
+/* 20632*/ 0, /*End of Scope*/
+/* 20633*/ 0, // EndSwitchType
+/* 20634*/ /*SwitchOpcode*/ 15|128,5/*655*/, TARGET_VAL(ISD::ATOMIC_CMP_SWAP),// ->21293
+/* 20638*/ OPC_RecordMemRef,
+/* 20639*/ OPC_RecordNode, // #0 = 'atomic_cmp_swap' chained node
+/* 20640*/ OPC_RecordChild1, // #1 = $addr
+/* 20641*/ OPC_SwitchType /*2 cases */, 44|128,3/*428*/, MVT::i32,// ->21073
+/* 20645*/ OPC_CheckChild1Type, MVT::i32,
+/* 20647*/ OPC_RecordChild2, // #2 = $cmp
+/* 20648*/ OPC_RecordChild3, // #3 = $new
+/* 20649*/ OPC_Scope, 81|128,1/*209*/, /*->20861*/ // 2 children in Scope
+/* 20652*/ OPC_CheckPredicate, 10, // Predicate_atomic_cmp_swap_32
+/* 20654*/ OPC_Scope, 40, /*->20696*/ // 5 children in Scope
+/* 20656*/ OPC_CheckPredicate, 20, // Predicate_atomic_cmp_swap_32_monotonic
+/* 20658*/ OPC_Scope, 17, /*->20677*/ // 2 children in Scope
+/* 20660*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20662*/ OPC_EmitMergeInputChains1_0,
+/* 20663*/ OPC_EmitInteger, MVT::i32, 2,
+/* 20666*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_monotonic>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 2:{ *:[i32] })
+/* 20677*/ /*Scope*/ 17, /*->20695*/
+/* 20678*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20680*/ OPC_EmitMergeInputChains1_0,
+/* 20681*/ OPC_EmitInteger, MVT::i32, 2,
+/* 20684*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_monotonic>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 2:{ *:[i32] })
+/* 20695*/ 0, /*End of Scope*/
+/* 20696*/ /*Scope*/ 40, /*->20737*/
+/* 20697*/ OPC_CheckPredicate, 21, // Predicate_atomic_cmp_swap_32_acquire
+/* 20699*/ OPC_Scope, 17, /*->20718*/ // 2 children in Scope
+/* 20701*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20703*/ OPC_EmitMergeInputChains1_0,
+/* 20704*/ OPC_EmitInteger, MVT::i32, 4,
+/* 20707*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acquire>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 4:{ *:[i32] })
+/* 20718*/ /*Scope*/ 17, /*->20736*/
+/* 20719*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20721*/ OPC_EmitMergeInputChains1_0,
+/* 20722*/ OPC_EmitInteger, MVT::i32, 4,
+/* 20725*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acquire>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 4:{ *:[i32] })
+/* 20736*/ 0, /*End of Scope*/
+/* 20737*/ /*Scope*/ 40, /*->20778*/
+/* 20738*/ OPC_CheckPredicate, 22, // Predicate_atomic_cmp_swap_32_release
+/* 20740*/ OPC_Scope, 17, /*->20759*/ // 2 children in Scope
+/* 20742*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20744*/ OPC_EmitMergeInputChains1_0,
+/* 20745*/ OPC_EmitInteger, MVT::i32, 5,
+/* 20748*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_release>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 5:{ *:[i32] })
+/* 20759*/ /*Scope*/ 17, /*->20777*/
+/* 20760*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20762*/ OPC_EmitMergeInputChains1_0,
+/* 20763*/ OPC_EmitInteger, MVT::i32, 5,
+/* 20766*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_release>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 5:{ *:[i32] })
+/* 20777*/ 0, /*End of Scope*/
+/* 20778*/ /*Scope*/ 40, /*->20819*/
+/* 20779*/ OPC_CheckPredicate, 23, // Predicate_atomic_cmp_swap_32_acq_rel
+/* 20781*/ OPC_Scope, 17, /*->20800*/ // 2 children in Scope
+/* 20783*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20785*/ OPC_EmitMergeInputChains1_0,
+/* 20786*/ OPC_EmitInteger, MVT::i32, 6,
+/* 20789*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acq_rel>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 6:{ *:[i32] })
+/* 20800*/ /*Scope*/ 17, /*->20818*/
+/* 20801*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20803*/ OPC_EmitMergeInputChains1_0,
+/* 20804*/ OPC_EmitInteger, MVT::i32, 6,
+/* 20807*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acq_rel>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 6:{ *:[i32] })
+/* 20818*/ 0, /*End of Scope*/
+/* 20819*/ /*Scope*/ 40, /*->20860*/
+/* 20820*/ OPC_CheckPredicate, 24, // Predicate_atomic_cmp_swap_32_seq_cst
+/* 20822*/ OPC_Scope, 17, /*->20841*/ // 2 children in Scope
+/* 20824*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20826*/ OPC_EmitMergeInputChains1_0,
+/* 20827*/ OPC_EmitInteger, MVT::i32, 7,
+/* 20830*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_seq_cst>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 7:{ *:[i32] })
+/* 20841*/ /*Scope*/ 17, /*->20859*/
+/* 20842*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 20844*/ OPC_EmitMergeInputChains1_0,
+/* 20845*/ OPC_EmitInteger, MVT::i32, 7,
+/* 20848*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_seq_cst>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 7:{ *:[i32] })
+/* 20859*/ 0, /*End of Scope*/
+/* 20860*/ 0, /*End of Scope*/
+/* 20861*/ /*Scope*/ 81|128,1/*209*/, /*->21072*/
+/* 20863*/ OPC_CheckPredicate, 14, // Predicate_atomic_cmp_swap_64
+/* 20865*/ OPC_Scope, 40, /*->20907*/ // 5 children in Scope
+/* 20867*/ OPC_CheckPredicate, 20, // Predicate_atomic_cmp_swap_64_monotonic
+/* 20869*/ OPC_Scope, 17, /*->20888*/ // 2 children in Scope
+/* 20871*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20873*/ OPC_EmitMergeInputChains1_0,
+/* 20874*/ OPC_EmitInteger, MVT::i32, 2,
+/* 20877*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_monotonic>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 2:{ *:[i32] })
+/* 20888*/ /*Scope*/ 17, /*->20906*/
+/* 20889*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 20891*/ OPC_EmitMergeInputChains1_0,
+/* 20892*/ OPC_EmitInteger, MVT::i32, 2,
+/* 20895*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_monotonic>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 2:{ *:[i32] })
+/* 20906*/ 0, /*End of Scope*/
+/* 20907*/ /*Scope*/ 40, /*->20948*/
+/* 20908*/ OPC_CheckPredicate, 21, // Predicate_atomic_cmp_swap_64_acquire
+/* 20910*/ OPC_Scope, 17, /*->20929*/ // 2 children in Scope
+/* 20912*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20914*/ OPC_EmitMergeInputChains1_0,
+/* 20915*/ OPC_EmitInteger, MVT::i32, 4,
+/* 20918*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acquire>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 4:{ *:[i32] })
+/* 20929*/ /*Scope*/ 17, /*->20947*/
+/* 20930*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 20932*/ OPC_EmitMergeInputChains1_0,
+/* 20933*/ OPC_EmitInteger, MVT::i32, 4,
+/* 20936*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acquire>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 4:{ *:[i32] })
+/* 20947*/ 0, /*End of Scope*/
+/* 20948*/ /*Scope*/ 40, /*->20989*/
+/* 20949*/ OPC_CheckPredicate, 22, // Predicate_atomic_cmp_swap_64_release
+/* 20951*/ OPC_Scope, 17, /*->20970*/ // 2 children in Scope
+/* 20953*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20955*/ OPC_EmitMergeInputChains1_0,
+/* 20956*/ OPC_EmitInteger, MVT::i32, 5,
+/* 20959*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_release>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 5:{ *:[i32] })
+/* 20970*/ /*Scope*/ 17, /*->20988*/
+/* 20971*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 20973*/ OPC_EmitMergeInputChains1_0,
+/* 20974*/ OPC_EmitInteger, MVT::i32, 5,
+/* 20977*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_release>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 5:{ *:[i32] })
+/* 20988*/ 0, /*End of Scope*/
+/* 20989*/ /*Scope*/ 40, /*->21030*/
+/* 20990*/ OPC_CheckPredicate, 23, // Predicate_atomic_cmp_swap_64_acq_rel
+/* 20992*/ OPC_Scope, 17, /*->21011*/ // 2 children in Scope
+/* 20994*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 20996*/ OPC_EmitMergeInputChains1_0,
+/* 20997*/ OPC_EmitInteger, MVT::i32, 6,
+/* 21000*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acq_rel>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 6:{ *:[i32] })
+/* 21011*/ /*Scope*/ 17, /*->21029*/
+/* 21012*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 21014*/ OPC_EmitMergeInputChains1_0,
+/* 21015*/ OPC_EmitInteger, MVT::i32, 6,
+/* 21018*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acq_rel>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 6:{ *:[i32] })
+/* 21029*/ 0, /*End of Scope*/
+/* 21030*/ /*Scope*/ 40, /*->21071*/
+/* 21031*/ OPC_CheckPredicate, 24, // Predicate_atomic_cmp_swap_64_seq_cst
+/* 21033*/ OPC_Scope, 17, /*->21052*/ // 2 children in Scope
+/* 21035*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21037*/ OPC_EmitMergeInputChains1_0,
+/* 21038*/ OPC_EmitInteger, MVT::i32, 7,
+/* 21041*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_seq_cst>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 7:{ *:[i32] })
+/* 21052*/ /*Scope*/ 17, /*->21070*/
+/* 21053*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 21055*/ OPC_EmitMergeInputChains1_0,
+/* 21056*/ OPC_EmitInteger, MVT::i32, 7,
+/* 21059*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, MVT::i32, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_seq_cst>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i32] }:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$cmp, GPR:{ *:[i32] }:$new, 7:{ *:[i32] })
+/* 21070*/ 0, /*End of Scope*/
+/* 21071*/ 0, /*End of Scope*/
+/* 21072*/ 0, /*End of Scope*/
+/* 21073*/ /*SwitchType*/ 88|128,1/*216*/, MVT::i64,// ->21292
+/* 21076*/ OPC_CheckChild1Type, MVT::i64,
+/* 21078*/ OPC_RecordChild2, // #2 = $cmp
+/* 21079*/ OPC_RecordChild3, // #3 = $new
+/* 21080*/ OPC_Scope, 104, /*->21186*/ // 2 children in Scope
+/* 21082*/ OPC_CheckPredicate, 10, // Predicate_atomic_cmp_swap_32
+/* 21084*/ OPC_Scope, 19, /*->21105*/ // 5 children in Scope
+/* 21086*/ OPC_CheckPredicate, 20, // Predicate_atomic_cmp_swap_32_monotonic
+/* 21088*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21090*/ OPC_EmitMergeInputChains1_0,
+/* 21091*/ OPC_EmitInteger, MVT::i64, 2,
+/* 21094*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_monotonic>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 2:{ *:[i64] })
+/* 21105*/ /*Scope*/ 19, /*->21125*/
+/* 21106*/ OPC_CheckPredicate, 21, // Predicate_atomic_cmp_swap_32_acquire
+/* 21108*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21110*/ OPC_EmitMergeInputChains1_0,
+/* 21111*/ OPC_EmitInteger, MVT::i64, 4,
+/* 21114*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acquire>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 4:{ *:[i64] })
+/* 21125*/ /*Scope*/ 19, /*->21145*/
+/* 21126*/ OPC_CheckPredicate, 22, // Predicate_atomic_cmp_swap_32_release
+/* 21128*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21130*/ OPC_EmitMergeInputChains1_0,
+/* 21131*/ OPC_EmitInteger, MVT::i64, 5,
+/* 21134*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_release>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 5:{ *:[i64] })
+/* 21145*/ /*Scope*/ 19, /*->21165*/
+/* 21146*/ OPC_CheckPredicate, 23, // Predicate_atomic_cmp_swap_32_acq_rel
+/* 21148*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21150*/ OPC_EmitMergeInputChains1_0,
+/* 21151*/ OPC_EmitInteger, MVT::i64, 6,
+/* 21154*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_acq_rel>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 6:{ *:[i64] })
+/* 21165*/ /*Scope*/ 19, /*->21185*/
+/* 21166*/ OPC_CheckPredicate, 24, // Predicate_atomic_cmp_swap_32_seq_cst
+/* 21168*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21170*/ OPC_EmitMergeInputChains1_0,
+/* 21171*/ OPC_EmitInteger, MVT::i64, 7,
+/* 21174*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg32), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_32>><<P:Predicate_atomic_cmp_swap_32_seq_cst>> - Complexity = 4
+ // Dst: (PseudoCmpXchg32:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 7:{ *:[i64] })
+/* 21185*/ 0, /*End of Scope*/
+/* 21186*/ /*Scope*/ 104, /*->21291*/
+/* 21187*/ OPC_CheckPredicate, 14, // Predicate_atomic_cmp_swap_64
+/* 21189*/ OPC_Scope, 19, /*->21210*/ // 5 children in Scope
+/* 21191*/ OPC_CheckPredicate, 20, // Predicate_atomic_cmp_swap_64_monotonic
+/* 21193*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21195*/ OPC_EmitMergeInputChains1_0,
+/* 21196*/ OPC_EmitInteger, MVT::i64, 2,
+/* 21199*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_monotonic>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 2:{ *:[i64] })
+/* 21210*/ /*Scope*/ 19, /*->21230*/
+/* 21211*/ OPC_CheckPredicate, 21, // Predicate_atomic_cmp_swap_64_acquire
+/* 21213*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21215*/ OPC_EmitMergeInputChains1_0,
+/* 21216*/ OPC_EmitInteger, MVT::i64, 4,
+/* 21219*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acquire>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 4:{ *:[i64] })
+/* 21230*/ /*Scope*/ 19, /*->21250*/
+/* 21231*/ OPC_CheckPredicate, 22, // Predicate_atomic_cmp_swap_64_release
+/* 21233*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21235*/ OPC_EmitMergeInputChains1_0,
+/* 21236*/ OPC_EmitInteger, MVT::i64, 5,
+/* 21239*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_release>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 5:{ *:[i64] })
+/* 21250*/ /*Scope*/ 19, /*->21270*/
+/* 21251*/ OPC_CheckPredicate, 23, // Predicate_atomic_cmp_swap_64_acq_rel
+/* 21253*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21255*/ OPC_EmitMergeInputChains1_0,
+/* 21256*/ OPC_EmitInteger, MVT::i64, 6,
+/* 21259*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_acq_rel>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 6:{ *:[i64] })
+/* 21270*/ /*Scope*/ 19, /*->21290*/
+/* 21271*/ OPC_CheckPredicate, 24, // Predicate_atomic_cmp_swap_64_seq_cst
+/* 21273*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21275*/ OPC_EmitMergeInputChains1_0,
+/* 21276*/ OPC_EmitInteger, MVT::i64, 7,
+/* 21279*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::PseudoCmpXchg64), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, MVT::i64, 4/*#Ops*/, 1, 2, 3, 4,
+ // Src: (atomic_cmp_swap:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_64>><<P:Predicate_atomic_cmp_swap_64_seq_cst>> - Complexity = 4
+ // Dst: (PseudoCmpXchg64:{ *:[i64] }:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$cmp, GPR:{ *:[i64] }:$new, 7:{ *:[i64] })
+/* 21290*/ 0, /*End of Scope*/
+/* 21291*/ 0, /*End of Scope*/
+/* 21292*/ 0, // EndSwitchType
+/* 21293*/ /*SwitchOpcode*/ 37|128,6/*805*/, TARGET_VAL(ISD::ATOMIC_LOAD_SUB),// ->22102
+/* 21297*/ OPC_RecordMemRef,
+/* 21298*/ OPC_RecordNode, // #0 = 'atomic_load_sub' chained node
+/* 21299*/ OPC_RecordChild1, // #1 = $addr
+/* 21300*/ OPC_SwitchType /*2 cases */, 15|128,4/*527*/, MVT::i32,// ->21831
+/* 21304*/ OPC_CheckChild1Type, MVT::i32,
+/* 21306*/ OPC_RecordChild2, // #2 = $incr
+/* 21307*/ OPC_Scope, 3|128,2/*259*/, /*->21569*/ // 2 children in Scope
+/* 21310*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_sub_32
+/* 21312*/ OPC_Scope, 50, /*->21364*/ // 5 children in Scope
+/* 21314*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_sub_32_monotonic
+/* 21316*/ OPC_Scope, 22, /*->21340*/ // 2 children in Scope
+/* 21318*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21320*/ OPC_EmitMergeInputChains1_0,
+/* 21321*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21324*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21332*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21340*/ /*Scope*/ 22, /*->21363*/
+/* 21341*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 21343*/ OPC_EmitMergeInputChains1_0,
+/* 21344*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21347*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21355*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21363*/ 0, /*End of Scope*/
+/* 21364*/ /*Scope*/ 50, /*->21415*/
+/* 21365*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_sub_32_acquire
+/* 21367*/ OPC_Scope, 22, /*->21391*/ // 2 children in Scope
+/* 21369*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21371*/ OPC_EmitMergeInputChains1_0,
+/* 21372*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21375*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21383*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21391*/ /*Scope*/ 22, /*->21414*/
+/* 21392*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 21394*/ OPC_EmitMergeInputChains1_0,
+/* 21395*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21398*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21406*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21414*/ 0, /*End of Scope*/
+/* 21415*/ /*Scope*/ 50, /*->21466*/
+/* 21416*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_sub_32_release
+/* 21418*/ OPC_Scope, 22, /*->21442*/ // 2 children in Scope
+/* 21420*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21422*/ OPC_EmitMergeInputChains1_0,
+/* 21423*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21426*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21434*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> - Complexity = 4
+ // Dst: (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21442*/ /*Scope*/ 22, /*->21465*/
+/* 21443*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 21445*/ OPC_EmitMergeInputChains1_0,
+/* 21446*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21449*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21457*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> - Complexity = 4
+ // Dst: (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21465*/ 0, /*End of Scope*/
+/* 21466*/ /*Scope*/ 50, /*->21517*/
+/* 21467*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_sub_32_acq_rel
+/* 21469*/ OPC_Scope, 22, /*->21493*/ // 2 children in Scope
+/* 21471*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21473*/ OPC_EmitMergeInputChains1_0,
+/* 21474*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21477*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21485*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21493*/ /*Scope*/ 22, /*->21516*/
+/* 21494*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 21496*/ OPC_EmitMergeInputChains1_0,
+/* 21497*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21500*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21508*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21516*/ 0, /*End of Scope*/
+/* 21517*/ /*Scope*/ 50, /*->21568*/
+/* 21518*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_sub_32_seq_cst
+/* 21520*/ OPC_Scope, 22, /*->21544*/ // 2 children in Scope
+/* 21522*/ OPC_CheckPatternPredicate, 17, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21524*/ OPC_EmitMergeInputChains1_0,
+/* 21525*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21528*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21536*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21544*/ /*Scope*/ 22, /*->21567*/
+/* 21545*/ OPC_CheckPatternPredicate, 18, // (Subtarget->hasStdExtA())
+/* 21547*/ OPC_EmitMergeInputChains1_0,
+/* 21548*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21551*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21559*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21567*/ 0, /*End of Scope*/
+/* 21568*/ 0, /*End of Scope*/
+/* 21569*/ /*Scope*/ 3|128,2/*259*/, /*->21830*/
+/* 21571*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_sub_64
+/* 21573*/ OPC_Scope, 50, /*->21625*/ // 5 children in Scope
+/* 21575*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_sub_64_monotonic
+/* 21577*/ OPC_Scope, 22, /*->21601*/ // 2 children in Scope
+/* 21579*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21581*/ OPC_EmitMergeInputChains1_0,
+/* 21582*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21585*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21593*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21601*/ /*Scope*/ 22, /*->21624*/
+/* 21602*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 21604*/ OPC_EmitMergeInputChains1_0,
+/* 21605*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21608*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21616*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21624*/ 0, /*End of Scope*/
+/* 21625*/ /*Scope*/ 50, /*->21676*/
+/* 21626*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_sub_64_acquire
+/* 21628*/ OPC_Scope, 22, /*->21652*/ // 2 children in Scope
+/* 21630*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21632*/ OPC_EmitMergeInputChains1_0,
+/* 21633*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21636*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21644*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21652*/ /*Scope*/ 22, /*->21675*/
+/* 21653*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 21655*/ OPC_EmitMergeInputChains1_0,
+/* 21656*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21659*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21667*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21675*/ 0, /*End of Scope*/
+/* 21676*/ /*Scope*/ 50, /*->21727*/
+/* 21677*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_sub_64_release
+/* 21679*/ OPC_Scope, 22, /*->21703*/ // 2 children in Scope
+/* 21681*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21683*/ OPC_EmitMergeInputChains1_0,
+/* 21684*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21687*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21695*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> - Complexity = 4
+ // Dst: (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21703*/ /*Scope*/ 22, /*->21726*/
+/* 21704*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 21706*/ OPC_EmitMergeInputChains1_0,
+/* 21707*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21710*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21718*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> - Complexity = 4
+ // Dst: (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21726*/ 0, /*End of Scope*/
+/* 21727*/ /*Scope*/ 50, /*->21778*/
+/* 21728*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_sub_64_acq_rel
+/* 21730*/ OPC_Scope, 22, /*->21754*/ // 2 children in Scope
+/* 21732*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21734*/ OPC_EmitMergeInputChains1_0,
+/* 21735*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21738*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21746*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21754*/ /*Scope*/ 22, /*->21777*/
+/* 21755*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 21757*/ OPC_EmitMergeInputChains1_0,
+/* 21758*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21761*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21769*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21777*/ 0, /*End of Scope*/
+/* 21778*/ /*Scope*/ 50, /*->21829*/
+/* 21779*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_sub_64_seq_cst
+/* 21781*/ OPC_Scope, 22, /*->21805*/ // 2 children in Scope
+/* 21783*/ OPC_CheckPatternPredicate, 19, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 21785*/ OPC_EmitMergeInputChains1_0,
+/* 21786*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21789*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21797*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21805*/ /*Scope*/ 22, /*->21828*/
+/* 21806*/ OPC_CheckPatternPredicate, 20, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit())
+/* 21808*/ OPC_EmitMergeInputChains1_0,
+/* 21809*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 21812*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21820*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i32, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+/* 21828*/ 0, /*End of Scope*/
+/* 21829*/ 0, /*End of Scope*/
+/* 21830*/ 0, /*End of Scope*/
+/* 21831*/ /*SwitchType*/ 11|128,2/*267*/, MVT::i64,// ->22101
+/* 21834*/ OPC_CheckChild1Type, MVT::i64,
+/* 21836*/ OPC_RecordChild2, // #2 = $incr
+/* 21837*/ OPC_Scope, 1|128,1/*129*/, /*->21969*/ // 2 children in Scope
+/* 21840*/ OPC_CheckPredicate, 10, // Predicate_atomic_load_sub_32
+/* 21842*/ OPC_Scope, 24, /*->21868*/ // 5 children in Scope
+/* 21844*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_sub_32_monotonic
+/* 21846*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21848*/ OPC_EmitMergeInputChains1_0,
+/* 21849*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 21852*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21860*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 21868*/ /*Scope*/ 24, /*->21893*/
+/* 21869*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_sub_32_acquire
+/* 21871*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21873*/ OPC_EmitMergeInputChains1_0,
+/* 21874*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 21877*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21885*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 21893*/ /*Scope*/ 24, /*->21918*/
+/* 21894*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_sub_32_release
+/* 21896*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21898*/ OPC_EmitMergeInputChains1_0,
+/* 21899*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 21902*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21910*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> - Complexity = 4
+ // Dst: (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 21918*/ /*Scope*/ 24, /*->21943*/
+/* 21919*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_sub_32_acq_rel
+/* 21921*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21923*/ OPC_EmitMergeInputChains1_0,
+/* 21924*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 21927*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21935*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 21943*/ /*Scope*/ 24, /*->21968*/
+/* 21944*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_sub_32_seq_cst
+/* 21946*/ OPC_CheckPatternPredicate, 21, // (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21948*/ OPC_EmitMergeInputChains1_0,
+/* 21949*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 21952*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21960*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_W_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 21968*/ 0, /*End of Scope*/
+/* 21969*/ /*Scope*/ 1|128,1/*129*/, /*->22100*/
+/* 21971*/ OPC_CheckPredicate, 14, // Predicate_atomic_load_sub_64
+/* 21973*/ OPC_Scope, 24, /*->21999*/ // 5 children in Scope
+/* 21975*/ OPC_CheckPredicate, 20, // Predicate_atomic_load_sub_64_monotonic
+/* 21977*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 21979*/ OPC_EmitMergeInputChains1_0,
+/* 21980*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 21983*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 21991*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> - Complexity = 4
+ // Dst: (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 21999*/ /*Scope*/ 24, /*->22024*/
+/* 22000*/ OPC_CheckPredicate, 21, // Predicate_atomic_load_sub_64_acquire
+/* 22002*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22004*/ OPC_EmitMergeInputChains1_0,
+/* 22005*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22008*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 22016*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 22024*/ /*Scope*/ 24, /*->22049*/
+/* 22025*/ OPC_CheckPredicate, 22, // Predicate_atomic_load_sub_64_release
+/* 22027*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22029*/ OPC_EmitMergeInputChains1_0,
+/* 22030*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22033*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 22041*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> - Complexity = 4
+ // Dst: (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 22049*/ /*Scope*/ 24, /*->22074*/
+/* 22050*/ OPC_CheckPredicate, 23, // Predicate_atomic_load_sub_64_acq_rel
+/* 22052*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22054*/ OPC_EmitMergeInputChains1_0,
+/* 22055*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22058*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 22066*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 22074*/ /*Scope*/ 24, /*->22099*/
+/* 22075*/ OPC_CheckPredicate, 24, // Predicate_atomic_load_sub_64_seq_cst
+/* 22077*/ OPC_CheckPatternPredicate, 22, // (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22079*/ OPC_EmitMergeInputChains1_0,
+/* 22080*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22083*/ OPC_EmitNode1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 3, 2, // Results = #4
+/* 22091*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::AMOADD_D_AQ_RL), 0|OPFL_Chain|OPFL_MemRefs,
+ MVT::i64, 2/*#Ops*/, 1, 4,
+ // Src: (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> - Complexity = 4
+ // Dst: (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+/* 22099*/ 0, /*End of Scope*/
+/* 22100*/ 0, /*End of Scope*/
+/* 22101*/ 0, // EndSwitchType
+/* 22102*/ /*SwitchOpcode*/ 14, TARGET_VAL(ISD::BR),// ->22119
+/* 22105*/ OPC_RecordNode, // #0 = 'br' chained node
+/* 22106*/ OPC_RecordChild1, // #1 = $imm20
+/* 22107*/ OPC_MoveChild1,
+/* 22108*/ OPC_CheckOpcode, TARGET_VAL(ISD::BasicBlock),
+/* 22111*/ OPC_MoveParent,
+/* 22112*/ OPC_EmitMergeInputChains1_0,
+/* 22113*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoBR), 0|OPFL_Chain,
+ 1/*#Ops*/, 1,
+ // Src: (br (bb:{ *:[Other] }):$imm20) - Complexity = 3
+ // Dst: (PseudoBR (bb:{ *:[Other] }):$imm20)
+/* 22119*/ /*SwitchOpcode*/ 8, TARGET_VAL(RISCVISD::RET_FLAG),// ->22130
+/* 22122*/ OPC_RecordNode, // #0 = 'riscv_ret_flag' chained node
+/* 22123*/ OPC_CaptureGlueInput,
+/* 22124*/ OPC_EmitMergeInputChains1_0,
+/* 22125*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::PseudoRET), 0|OPFL_Chain|OPFL_GlueInput|OPFL_Variadic0,
+ 0/*#Ops*/,
+ // Src: (riscv_ret_flag) - Complexity = 3
+ // Dst: (PseudoRET)
+/* 22130*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->22140
+/* 22133*/ OPC_RecordNode, // #0 = 'trap' chained node
+/* 22134*/ OPC_EmitMergeInputChains1_0,
+/* 22135*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::UNIMP), 0|OPFL_Chain,
+ 0/*#Ops*/,
+ // Src: (trap) - Complexity = 3
+ // Dst: (UNIMP)
+/* 22140*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::DEBUGTRAP),// ->22150
+/* 22143*/ OPC_RecordNode, // #0 = 'debugtrap' chained node
+/* 22144*/ OPC_EmitMergeInputChains1_0,
+/* 22145*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::EBREAK), 0|OPFL_Chain,
+ 0/*#Ops*/,
+ // Src: (debugtrap) - Complexity = 3
+ // Dst: (EBREAK)
+/* 22150*/ /*SwitchOpcode*/ 40, TARGET_VAL(ISD::SUB),// ->22193
+/* 22153*/ OPC_RecordChild0, // #0 = $rs1
+/* 22154*/ OPC_RecordChild1, // #1 = $rs2
+/* 22155*/ OPC_SwitchType /*2 cases */, 22, MVT::i32,// ->22180
+/* 22158*/ OPC_Scope, 10, /*->22170*/ // 2 children in Scope
+/* 22160*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22162*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22170*/ /*Scope*/ 8, /*->22179*/
+/* 22171*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22179*/ 0, /*End of Scope*/
+/* 22180*/ /*SwitchType*/ 10, MVT::i64,// ->22192
+/* 22182*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22184*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SUB), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (SUB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22192*/ 0, // EndSwitchType
+/* 22193*/ /*SwitchOpcode*/ 53, TARGET_VAL(RISCVISD::URET_FLAG),// ->22249
+/* 22196*/ OPC_RecordNode, // #0 = 'riscv_uret_flag' chained node
+/* 22197*/ OPC_CaptureGlueInput,
+/* 22198*/ OPC_Scope, 16, /*->22216*/ // 3 children in Scope
+/* 22200*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22202*/ OPC_EmitMergeInputChains1_0,
+/* 22203*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22206*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22209*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::URET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_uret_flag) - Complexity = 3
+ // Dst: (URET X0:{ *:[i32] }, X0:{ *:[i32] })
+/* 22216*/ /*Scope*/ 16, /*->22233*/
+/* 22217*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22219*/ OPC_EmitMergeInputChains1_0,
+/* 22220*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22223*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22226*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::URET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_uret_flag) - Complexity = 3
+ // Dst: (URET X0:{ *:[i64] }, X0:{ *:[i64] })
+/* 22233*/ /*Scope*/ 14, /*->22248*/
+/* 22234*/ OPC_EmitMergeInputChains1_0,
+/* 22235*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22238*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22241*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::URET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_uret_flag) - Complexity = 3
+ // Dst: (URET X0:{ *:[i32] }, X0:{ *:[i32] })
+/* 22248*/ 0, /*End of Scope*/
+/* 22249*/ /*SwitchOpcode*/ 53, TARGET_VAL(RISCVISD::SRET_FLAG),// ->22305
+/* 22252*/ OPC_RecordNode, // #0 = 'riscv_sret_flag' chained node
+/* 22253*/ OPC_CaptureGlueInput,
+/* 22254*/ OPC_Scope, 16, /*->22272*/ // 3 children in Scope
+/* 22256*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22258*/ OPC_EmitMergeInputChains1_0,
+/* 22259*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22262*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22265*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SRET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_sret_flag) - Complexity = 3
+ // Dst: (SRET X0:{ *:[i32] }, X0:{ *:[i32] })
+/* 22272*/ /*Scope*/ 16, /*->22289*/
+/* 22273*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22275*/ OPC_EmitMergeInputChains1_0,
+/* 22276*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22279*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22282*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SRET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_sret_flag) - Complexity = 3
+ // Dst: (SRET X0:{ *:[i64] }, X0:{ *:[i64] })
+/* 22289*/ /*Scope*/ 14, /*->22304*/
+/* 22290*/ OPC_EmitMergeInputChains1_0,
+/* 22291*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22294*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22297*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::SRET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_sret_flag) - Complexity = 3
+ // Dst: (SRET X0:{ *:[i32] }, X0:{ *:[i32] })
+/* 22304*/ 0, /*End of Scope*/
+/* 22305*/ /*SwitchOpcode*/ 53, TARGET_VAL(RISCVISD::MRET_FLAG),// ->22361
+/* 22308*/ OPC_RecordNode, // #0 = 'riscv_mret_flag' chained node
+/* 22309*/ OPC_CaptureGlueInput,
+/* 22310*/ OPC_Scope, 16, /*->22328*/ // 3 children in Scope
+/* 22312*/ OPC_CheckPatternPredicate, 6, // (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22314*/ OPC_EmitMergeInputChains1_0,
+/* 22315*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22318*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22321*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::MRET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_mret_flag) - Complexity = 3
+ // Dst: (MRET X0:{ *:[i32] }, X0:{ *:[i32] })
+/* 22328*/ /*Scope*/ 16, /*->22345*/
+/* 22329*/ OPC_CheckPatternPredicate, 7, // (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22331*/ OPC_EmitMergeInputChains1_0,
+/* 22332*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22335*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22338*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::MRET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_mret_flag) - Complexity = 3
+ // Dst: (MRET X0:{ *:[i64] }, X0:{ *:[i64] })
+/* 22345*/ /*Scope*/ 14, /*->22360*/
+/* 22346*/ OPC_EmitMergeInputChains1_0,
+/* 22347*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22350*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22353*/ OPC_MorphNodeTo0, TARGET_VAL(RISCV::MRET), 0|OPFL_Chain|OPFL_GlueInput,
+ 2/*#Ops*/, 1, 2,
+ // Src: (riscv_mret_flag) - Complexity = 3
+ // Dst: (MRET X0:{ *:[i32] }, X0:{ *:[i32] })
+/* 22360*/ 0, /*End of Scope*/
+/* 22361*/ /*SwitchOpcode*/ 46, TARGET_VAL(RISCVISD::SLLW),// ->22410
+/* 22364*/ OPC_RecordChild0, // #0 = $rs1
+/* 22365*/ OPC_RecordChild1, // #1 = $rs2
+/* 22366*/ OPC_SwitchType /*2 cases */, 26, MVT::i32,// ->22395
+/* 22369*/ OPC_CheckChild1Type, MVT::i32,
+/* 22371*/ OPC_Scope, 10, /*->22383*/ // 2 children in Scope
+/* 22373*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22375*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLLW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_sllw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SLLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22383*/ /*Scope*/ 10, /*->22394*/
+/* 22384*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 22386*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLLW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_sllw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SLLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22394*/ 0, /*End of Scope*/
+/* 22395*/ /*SwitchType*/ 12, MVT::i64,// ->22409
+/* 22397*/ OPC_CheckChild1Type, MVT::i64,
+/* 22399*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22401*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLLW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_sllw:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (SLLW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22409*/ 0, // EndSwitchType
+/* 22410*/ /*SwitchOpcode*/ 46, TARGET_VAL(RISCVISD::SRLW),// ->22459
+/* 22413*/ OPC_RecordChild0, // #0 = $rs1
+/* 22414*/ OPC_RecordChild1, // #1 = $rs2
+/* 22415*/ OPC_SwitchType /*2 cases */, 26, MVT::i32,// ->22444
+/* 22418*/ OPC_CheckChild1Type, MVT::i32,
+/* 22420*/ OPC_Scope, 10, /*->22432*/ // 2 children in Scope
+/* 22422*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22424*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_srlw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SRLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22432*/ /*Scope*/ 10, /*->22443*/
+/* 22433*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 22435*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_srlw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SRLW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22443*/ 0, /*End of Scope*/
+/* 22444*/ /*SwitchType*/ 12, MVT::i64,// ->22458
+/* 22446*/ OPC_CheckChild1Type, MVT::i64,
+/* 22448*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22450*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRLW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_srlw:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (SRLW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22458*/ 0, // EndSwitchType
+/* 22459*/ /*SwitchOpcode*/ 46, TARGET_VAL(RISCVISD::SRAW),// ->22508
+/* 22462*/ OPC_RecordChild0, // #0 = $rs1
+/* 22463*/ OPC_RecordChild1, // #1 = $rs2
+/* 22464*/ OPC_SwitchType /*2 cases */, 26, MVT::i32,// ->22493
+/* 22467*/ OPC_CheckChild1Type, MVT::i32,
+/* 22469*/ OPC_Scope, 10, /*->22481*/ // 2 children in Scope
+/* 22471*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22473*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRAW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_sraw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SRAW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22481*/ /*Scope*/ 10, /*->22492*/
+/* 22482*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 22484*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRAW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_sraw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (SRAW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22492*/ 0, /*End of Scope*/
+/* 22493*/ /*SwitchType*/ 12, MVT::i64,// ->22507
+/* 22495*/ OPC_CheckChild1Type, MVT::i64,
+/* 22497*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22499*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SRAW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_sraw:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (SRAW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22507*/ 0, // EndSwitchType
+/* 22508*/ /*SwitchOpcode*/ 65, TARGET_VAL(ISD::READCYCLECOUNTER),// ->22576
+/* 22511*/ OPC_RecordNode, // #0 = 'readcyclecounter' chained node
+/* 22512*/ OPC_SwitchType /*2 cases */, 40, MVT::i32,// ->22555
+/* 22515*/ OPC_Scope, 18, /*->22535*/ // 2 children in Scope
+/* 22517*/ OPC_CheckPatternPredicate, 3, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22519*/ OPC_EmitMergeInputChains1_0,
+/* 22520*/ OPC_EmitInteger, MVT::i32, 0|128,24/*3072*/,
+/* 22524*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22527*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::CSRRS), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (readcyclecounter:{ *:[i32] }) - Complexity = 3
+ // Dst: (CSRRS:{ *:[i32] } 3072:{ *:[i32] }, X0:{ *:[i32] })
+/* 22535*/ /*Scope*/ 18, /*->22554*/
+/* 22536*/ OPC_CheckPatternPredicate, 4, // (Subtarget->is64Bit())
+/* 22538*/ OPC_EmitMergeInputChains1_0,
+/* 22539*/ OPC_EmitInteger, MVT::i32, 0|128,24/*3072*/,
+/* 22543*/ OPC_EmitRegister, MVT::i32, RISCV::X0,
+/* 22546*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::CSRRS), 0|OPFL_Chain,
+ MVT::i32, 2/*#Ops*/, 1, 2,
+ // Src: (readcyclecounter:{ *:[i32] }) - Complexity = 3
+ // Dst: (CSRRS:{ *:[i32] } 3072:{ *:[i32] }, X0:{ *:[i32] })
+/* 22554*/ 0, /*End of Scope*/
+/* 22555*/ /*SwitchType*/ 18, MVT::i64,// ->22575
+/* 22557*/ OPC_CheckPatternPredicate, 5, // (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22559*/ OPC_EmitMergeInputChains1_0,
+/* 22560*/ OPC_EmitInteger, MVT::i64, 0|128,24/*3072*/,
+/* 22564*/ OPC_EmitRegister, MVT::i64, RISCV::X0,
+/* 22567*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::CSRRS), 0|OPFL_Chain,
+ MVT::i64, 2/*#Ops*/, 1, 2,
+ // Src: (readcyclecounter:{ *:[i64] }) - Complexity = 3
+ // Dst: (CSRRS:{ *:[i64] } 3072:{ *:[i64] }, X0:{ *:[i64] })
+/* 22575*/ 0, // EndSwitchType
+/* 22576*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MUL),// ->22621
+/* 22579*/ OPC_RecordChild0, // #0 = $rs1
+/* 22580*/ OPC_RecordChild1, // #1 = $rs2
+/* 22581*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22608
+/* 22584*/ OPC_Scope, 10, /*->22596*/ // 2 children in Scope
+/* 22586*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22588*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MUL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22596*/ /*Scope*/ 10, /*->22607*/
+/* 22597*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasStdExtM())
+/* 22599*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MUL), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22607*/ 0, /*End of Scope*/
+/* 22608*/ /*SwitchType*/ 10, MVT::i64,// ->22620
+/* 22610*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22612*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MUL), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (MUL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22620*/ 0, // EndSwitchType
+/* 22621*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MULHS),// ->22666
+/* 22624*/ OPC_RecordChild0, // #0 = $rs1
+/* 22625*/ OPC_RecordChild1, // #1 = $rs2
+/* 22626*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22653
+/* 22629*/ OPC_Scope, 10, /*->22641*/ // 2 children in Scope
+/* 22631*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22633*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MULH), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (MULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22641*/ /*Scope*/ 10, /*->22652*/
+/* 22642*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasStdExtM())
+/* 22644*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MULH), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (MULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22652*/ 0, /*End of Scope*/
+/* 22653*/ /*SwitchType*/ 10, MVT::i64,// ->22665
+/* 22655*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22657*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MULH), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (mulhs:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (MULH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22665*/ 0, // EndSwitchType
+/* 22666*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::MULHU),// ->22711
+/* 22669*/ OPC_RecordChild0, // #0 = $rs1
+/* 22670*/ OPC_RecordChild1, // #1 = $rs2
+/* 22671*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22698
+/* 22674*/ OPC_Scope, 10, /*->22686*/ // 2 children in Scope
+/* 22676*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22678*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MULHU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mulhu:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (MULHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22686*/ /*Scope*/ 10, /*->22697*/
+/* 22687*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasStdExtM())
+/* 22689*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MULHU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (mulhu:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (MULHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22697*/ 0, /*End of Scope*/
+/* 22698*/ /*SwitchType*/ 10, MVT::i64,// ->22710
+/* 22700*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22702*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::MULHU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (mulhu:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (MULHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22710*/ 0, // EndSwitchType
+/* 22711*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::SDIV),// ->22756
+/* 22714*/ OPC_RecordChild0, // #0 = $rs1
+/* 22715*/ OPC_RecordChild1, // #1 = $rs2
+/* 22716*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22743
+/* 22719*/ OPC_Scope, 10, /*->22731*/ // 2 children in Scope
+/* 22721*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22723*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22731*/ /*Scope*/ 10, /*->22742*/
+/* 22732*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasStdExtM())
+/* 22734*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIV), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22742*/ 0, /*End of Scope*/
+/* 22743*/ /*SwitchType*/ 10, MVT::i64,// ->22755
+/* 22745*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22747*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIV), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (sdiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (DIV:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22755*/ 0, // EndSwitchType
+/* 22756*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::UDIV),// ->22801
+/* 22759*/ OPC_RecordChild0, // #0 = $rs1
+/* 22760*/ OPC_RecordChild1, // #1 = $rs2
+/* 22761*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22788
+/* 22764*/ OPC_Scope, 10, /*->22776*/ // 2 children in Scope
+/* 22766*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22768*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22776*/ /*Scope*/ 10, /*->22787*/
+/* 22777*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasStdExtM())
+/* 22779*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22787*/ 0, /*End of Scope*/
+/* 22788*/ /*SwitchType*/ 10, MVT::i64,// ->22800
+/* 22790*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22792*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (udiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22800*/ 0, // EndSwitchType
+/* 22801*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::UREM),// ->22846
+/* 22804*/ OPC_RecordChild0, // #0 = $rs1
+/* 22805*/ OPC_RecordChild1, // #1 = $rs2
+/* 22806*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22833
+/* 22809*/ OPC_Scope, 10, /*->22821*/ // 2 children in Scope
+/* 22811*/ OPC_CheckPatternPredicate, 25, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22813*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22821*/ /*Scope*/ 10, /*->22832*/
+/* 22822*/ OPC_CheckPatternPredicate, 26, // (Subtarget->hasStdExtM())
+/* 22824*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22832*/ 0, /*End of Scope*/
+/* 22833*/ /*SwitchType*/ 10, MVT::i64,// ->22845
+/* 22835*/ OPC_CheckPatternPredicate, 27, // (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22837*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMU), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (urem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22845*/ 0, // EndSwitchType
+/* 22846*/ /*SwitchOpcode*/ 42, TARGET_VAL(RISCVISD::DIVW),// ->22891
+/* 22849*/ OPC_RecordChild0, // #0 = $rs1
+/* 22850*/ OPC_RecordChild1, // #1 = $rs2
+/* 22851*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22878
+/* 22854*/ OPC_Scope, 10, /*->22866*/ // 2 children in Scope
+/* 22856*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22858*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_divw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (DIVW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22866*/ /*Scope*/ 10, /*->22877*/
+/* 22867*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 22869*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_divw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (DIVW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22877*/ 0, /*End of Scope*/
+/* 22878*/ /*SwitchType*/ 10, MVT::i64,// ->22890
+/* 22880*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22882*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_divw:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (DIVW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22890*/ 0, // EndSwitchType
+/* 22891*/ /*SwitchOpcode*/ 42, TARGET_VAL(RISCVISD::DIVUW),// ->22936
+/* 22894*/ OPC_RecordChild0, // #0 = $rs1
+/* 22895*/ OPC_RecordChild1, // #1 = $rs2
+/* 22896*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22923
+/* 22899*/ OPC_Scope, 10, /*->22911*/ // 2 children in Scope
+/* 22901*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22903*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVUW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_divuw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (DIVUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22911*/ /*Scope*/ 10, /*->22922*/
+/* 22912*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 22914*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVUW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_divuw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (DIVUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22922*/ 0, /*End of Scope*/
+/* 22923*/ /*SwitchType*/ 10, MVT::i64,// ->22935
+/* 22925*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22927*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::DIVUW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_divuw:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (DIVUW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22935*/ 0, // EndSwitchType
+/* 22936*/ /*SwitchOpcode*/ 42, TARGET_VAL(RISCVISD::REMUW),// ->22981
+/* 22939*/ OPC_RecordChild0, // #0 = $rs1
+/* 22940*/ OPC_RecordChild1, // #1 = $rs2
+/* 22941*/ OPC_SwitchType /*2 cases */, 24, MVT::i32,// ->22968
+/* 22944*/ OPC_Scope, 10, /*->22956*/ // 2 children in Scope
+/* 22946*/ OPC_CheckPatternPredicate, 0, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22948*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMUW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_remuw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (REMUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22956*/ /*Scope*/ 10, /*->22967*/
+/* 22957*/ OPC_CheckPatternPredicate, 1, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit())
+/* 22959*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMUW), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_remuw:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) - Complexity = 3
+ // Dst: (REMUW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+/* 22967*/ 0, /*End of Scope*/
+/* 22968*/ /*SwitchType*/ 10, MVT::i64,// ->22980
+/* 22970*/ OPC_CheckPatternPredicate, 2, // (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 22972*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::REMUW), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (riscv_remuw:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) - Complexity = 3
+ // Dst: (REMUW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+/* 22980*/ 0, // EndSwitchType
+/* 22981*/ /*SwitchOpcode*/ 35|128,1/*163*/, TARGET_VAL(ISD::BITCAST),// ->23148
+/* 22985*/ OPC_RecordChild0, // #0 = $rs1
+/* 22986*/ OPC_Scope, 39, /*->23027*/ // 4 children in Scope
+/* 22988*/ OPC_CheckChild0Type, MVT::f32,
+/* 22990*/ OPC_SwitchType /*2 cases */, 22, MVT::i32,// ->23015
+/* 22993*/ OPC_Scope, 9, /*->23004*/ // 2 children in Scope
+/* 22995*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 22997*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_W), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1)
+/* 23004*/ /*Scope*/ 9, /*->23014*/
+/* 23005*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 23007*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_W), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1)
+/* 23014*/ 0, /*End of Scope*/
+/* 23015*/ /*SwitchType*/ 9, MVT::i64,// ->23026
+/* 23017*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23019*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_W), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FMV_X_W:{ *:[i64] } FPR32:{ *:[f32] }:$rs1)
+/* 23026*/ 0, // EndSwitchType
+/* 23027*/ /*Scope*/ 39, /*->23067*/
+/* 23028*/ OPC_CheckChild0Type, MVT::f64,
+/* 23030*/ OPC_SwitchType /*2 cases */, 22, MVT::i32,// ->23055
+/* 23033*/ OPC_Scope, 9, /*->23044*/ // 2 children in Scope
+/* 23035*/ OPC_CheckPatternPredicate, 28, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23037*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_D), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FMV_X_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1)
+/* 23044*/ /*Scope*/ 9, /*->23054*/
+/* 23045*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit())
+/* 23047*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_D), 0,
+ MVT::i32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FMV_X_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1)
+/* 23054*/ 0, /*End of Scope*/
+/* 23055*/ /*SwitchType*/ 9, MVT::i64,// ->23066
+/* 23057*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23059*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_D), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FMV_X_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1)
+/* 23066*/ 0, // EndSwitchType
+/* 23067*/ /*Scope*/ 52, /*->23120*/
+/* 23068*/ OPC_CheckChild0Type, MVT::i32,
+/* 23070*/ OPC_SwitchType /*2 cases */, 22, MVT::f32,// ->23095
+/* 23073*/ OPC_Scope, 9, /*->23084*/ // 2 children in Scope
+/* 23075*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23077*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_W_X), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1)
+/* 23084*/ /*Scope*/ 9, /*->23094*/
+/* 23085*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 23087*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_W_X), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1)
+/* 23094*/ 0, /*End of Scope*/
+/* 23095*/ /*SwitchType*/ 22, MVT::f64,// ->23119
+/* 23097*/ OPC_Scope, 9, /*->23108*/ // 2 children in Scope
+/* 23099*/ OPC_CheckPatternPredicate, 28, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23101*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_D_X), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FMV_D_X:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+/* 23108*/ /*Scope*/ 9, /*->23118*/
+/* 23109*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit())
+/* 23111*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_D_X), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FMV_D_X:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+/* 23118*/ 0, /*End of Scope*/
+/* 23119*/ 0, // EndSwitchType
+/* 23120*/ /*Scope*/ 26, /*->23147*/
+/* 23121*/ OPC_CheckChild0Type, MVT::i64,
+/* 23123*/ OPC_SwitchType /*2 cases */, 9, MVT::f32,// ->23135
+/* 23126*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23128*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_W_X), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f32] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FMV_W_X:{ *:[f32] } GPR:{ *:[i64] }:$rs1)
+/* 23135*/ /*SwitchType*/ 9, MVT::f64,// ->23146
+/* 23137*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23139*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_D_X), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (bitconvert:{ *:[f64] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FMV_D_X:{ *:[f64] } GPR:{ *:[i64] }:$rs1)
+/* 23146*/ 0, // EndSwitchType
+/* 23147*/ 0, /*End of Scope*/
+/* 23148*/ /*SwitchOpcode*/ 97|128,1/*225*/, TARGET_VAL(ISD::FP_TO_SINT),// ->23377
+/* 23152*/ OPC_RecordChild0, // #0 = $rs1
+/* 23153*/ OPC_Scope, 124, /*->23279*/ // 2 children in Scope
+/* 23155*/ OPC_CheckChild0Type, MVT::f32,
+/* 23157*/ OPC_SwitchType /*2 cases */, 86, MVT::i32,// ->23246
+/* 23160*/ OPC_Scope, 13, /*->23175*/ // 6 children in Scope
+/* 23162*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23164*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23167*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_W_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23175*/ /*Scope*/ 13, /*->23189*/
+/* 23176*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit())
+/* 23178*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23181*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_W_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23189*/ /*Scope*/ 13, /*->23203*/
+/* 23190*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23192*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23195*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_W_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23203*/ /*Scope*/ 13, /*->23217*/
+/* 23204*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit())
+/* 23206*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23209*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_W_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_W_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23217*/ /*Scope*/ 13, /*->23231*/
+/* 23218*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23220*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23223*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_L_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_L_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23231*/ /*Scope*/ 13, /*->23245*/
+/* 23232*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit())
+/* 23234*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23237*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_L_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_L_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23245*/ 0, /*End of Scope*/
+/* 23246*/ /*SwitchType*/ 30, MVT::i64,// ->23278
+/* 23248*/ OPC_Scope, 13, /*->23263*/ // 2 children in Scope
+/* 23250*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23252*/ OPC_EmitInteger, MVT::i64, 1,
+/* 23255*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_W_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_W_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] })
+/* 23263*/ /*Scope*/ 13, /*->23277*/
+/* 23264*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23266*/ OPC_EmitInteger, MVT::i64, 1,
+/* 23269*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_L_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_L_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] })
+/* 23277*/ 0, /*End of Scope*/
+/* 23278*/ 0, // EndSwitchType
+/* 23279*/ /*Scope*/ 96, /*->23376*/
+/* 23280*/ OPC_CheckChild0Type, MVT::f64,
+/* 23282*/ OPC_SwitchType /*2 cases */, 58, MVT::i32,// ->23343
+/* 23285*/ OPC_Scope, 13, /*->23300*/ // 4 children in Scope
+/* 23287*/ OPC_CheckPatternPredicate, 35, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23289*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23292*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_W_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+/* 23300*/ /*Scope*/ 13, /*->23314*/
+/* 23301*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit())
+/* 23303*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23306*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_W_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+/* 23314*/ /*Scope*/ 13, /*->23328*/
+/* 23315*/ OPC_CheckPatternPredicate, 28, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23317*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23320*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_L_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_L_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+/* 23328*/ /*Scope*/ 13, /*->23342*/
+/* 23329*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit())
+/* 23331*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23334*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_L_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_L_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+/* 23342*/ 0, /*End of Scope*/
+/* 23343*/ /*SwitchType*/ 30, MVT::i64,// ->23375
+/* 23345*/ OPC_Scope, 13, /*->23360*/ // 2 children in Scope
+/* 23347*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23349*/ OPC_EmitInteger, MVT::i64, 1,
+/* 23352*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_W_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_W_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+/* 23360*/ /*Scope*/ 13, /*->23374*/
+/* 23361*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23363*/ OPC_EmitInteger, MVT::i64, 1,
+/* 23366*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_L_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_L_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+/* 23374*/ 0, /*End of Scope*/
+/* 23375*/ 0, // EndSwitchType
+/* 23376*/ 0, /*End of Scope*/
+/* 23377*/ /*SwitchOpcode*/ 97|128,1/*225*/, TARGET_VAL(ISD::FP_TO_UINT),// ->23606
+/* 23381*/ OPC_RecordChild0, // #0 = $rs1
+/* 23382*/ OPC_Scope, 124, /*->23508*/ // 2 children in Scope
+/* 23384*/ OPC_CheckChild0Type, MVT::f32,
+/* 23386*/ OPC_SwitchType /*2 cases */, 86, MVT::i32,// ->23475
+/* 23389*/ OPC_Scope, 13, /*->23404*/ // 6 children in Scope
+/* 23391*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23393*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23396*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_WU_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23404*/ /*Scope*/ 13, /*->23418*/
+/* 23405*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit())
+/* 23407*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23410*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_WU_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23418*/ /*Scope*/ 13, /*->23432*/
+/* 23419*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23421*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23424*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_WU_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23432*/ /*Scope*/ 13, /*->23446*/
+/* 23433*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit())
+/* 23435*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23438*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_WU_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23446*/ /*Scope*/ 13, /*->23460*/
+/* 23447*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23449*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23452*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_LU_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_LU_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23460*/ /*Scope*/ 13, /*->23474*/
+/* 23461*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit())
+/* 23463*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23466*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_LU_S), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_LU_S:{ *:[i32] } ?:{ *:[f32] }:$rs1, 1:{ *:[i32] })
+/* 23474*/ 0, /*End of Scope*/
+/* 23475*/ /*SwitchType*/ 30, MVT::i64,// ->23507
+/* 23477*/ OPC_Scope, 13, /*->23492*/ // 2 children in Scope
+/* 23479*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23481*/ OPC_EmitInteger, MVT::i64, 1,
+/* 23484*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_WU_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] })
+/* 23492*/ /*Scope*/ 13, /*->23506*/
+/* 23493*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23495*/ OPC_EmitInteger, MVT::i64, 1,
+/* 23498*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_LU_S), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_LU_S:{ *:[i64] } ?:{ *:[f32] }:$rs1, 1:{ *:[i64] })
+/* 23506*/ 0, /*End of Scope*/
+/* 23507*/ 0, // EndSwitchType
+/* 23508*/ /*Scope*/ 96, /*->23605*/
+/* 23509*/ OPC_CheckChild0Type, MVT::f64,
+/* 23511*/ OPC_SwitchType /*2 cases */, 58, MVT::i32,// ->23572
+/* 23514*/ OPC_Scope, 13, /*->23529*/ // 4 children in Scope
+/* 23516*/ OPC_CheckPatternPredicate, 35, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23518*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23521*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+/* 23529*/ /*Scope*/ 13, /*->23543*/
+/* 23530*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit())
+/* 23532*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23535*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+/* 23543*/ /*Scope*/ 13, /*->23557*/
+/* 23544*/ OPC_CheckPatternPredicate, 28, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23546*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23549*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_LU_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_LU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+/* 23557*/ /*Scope*/ 13, /*->23571*/
+/* 23558*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit())
+/* 23560*/ OPC_EmitInteger, MVT::i32, 1,
+/* 23563*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_LU_D), 0,
+ MVT::i32, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_LU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+/* 23571*/ 0, /*End of Scope*/
+/* 23572*/ /*SwitchType*/ 30, MVT::i64,// ->23604
+/* 23574*/ OPC_Scope, 13, /*->23589*/ // 2 children in Scope
+/* 23576*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23578*/ OPC_EmitInteger, MVT::i64, 1,
+/* 23581*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_WU_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_WU_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+/* 23589*/ /*Scope*/ 13, /*->23603*/
+/* 23590*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23592*/ OPC_EmitInteger, MVT::i64, 1,
+/* 23595*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_LU_D), 0,
+ MVT::i64, 2/*#Ops*/, 0, 1,
+ // Src: (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_LU_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+/* 23603*/ 0, /*End of Scope*/
+/* 23604*/ 0, // EndSwitchType
+/* 23605*/ 0, /*End of Scope*/
+/* 23606*/ /*SwitchOpcode*/ 10, TARGET_VAL(RISCVISD::FMV_X_ANYEXTW_RV64),// ->23619
+/* 23609*/ OPC_RecordChild0, // #0 = $src
+/* 23610*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23612*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_X_W), 0,
+ MVT::i64, 1/*#Ops*/, 0,
+ // Src: (riscv_fmv_x_anyextw_rv64:{ *:[i64] } FPR32:{ *:[f32] }:$src) - Complexity = 3
+ // Dst: (FMV_X_W:{ *:[i64] } FPR32:{ *:[f32] }:$src)
+/* 23619*/ /*SwitchOpcode*/ 25, TARGET_VAL(RISCVISD::SplitF64),// ->23647
+/* 23622*/ OPC_RecordChild0, // #0 = $src
+/* 23623*/ OPC_Scope, 10, /*->23635*/ // 2 children in Scope
+/* 23625*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23627*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::SplitF64Pseudo), 0,
+ MVT::i32, MVT::i32, 1/*#Ops*/, 0,
+ // Src: (RISCVSplitF64:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (SplitF64Pseudo:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$src)
+/* 23635*/ /*Scope*/ 10, /*->23646*/
+/* 23636*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 23638*/ OPC_MorphNodeTo2, TARGET_VAL(RISCV::SplitF64Pseudo), 0,
+ MVT::i32, MVT::i32, 1/*#Ops*/, 0,
+ // Src: (RISCVSplitF64:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$src) - Complexity = 3
+ // Dst: (SplitF64Pseudo:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$src)
+/* 23646*/ 0, /*End of Scope*/
+/* 23647*/ /*SwitchOpcode*/ 42|128,3/*426*/, TARGET_VAL(ISD::UINT_TO_FP),// ->24077
+/* 23651*/ OPC_Scope, 78|128,1/*206*/, /*->23860*/ // 2 children in Scope
+/* 23654*/ OPC_MoveChild0,
+/* 23655*/ OPC_Scope, 101, /*->23758*/ // 2 children in Scope
+/* 23657*/ OPC_CheckAndImm, 127|128,127|128,127|128,127|128,15/*4294967295*/,
+/* 23663*/ OPC_RecordChild0, // #0 = $rs1
+/* 23664*/ OPC_SwitchType /*2 cases */, 59, MVT::i32,// ->23726
+/* 23667*/ OPC_MoveParent,
+/* 23668*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->23701
+/* 23671*/ OPC_Scope, 13, /*->23686*/ // 2 children in Scope
+/* 23673*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23675*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23678*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] })) - Complexity = 11
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23686*/ /*Scope*/ 13, /*->23700*/
+/* 23687*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit())
+/* 23689*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23692*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] })) - Complexity = 11
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23700*/ 0, /*End of Scope*/
+/* 23701*/ /*SwitchType*/ 22, MVT::f64,// ->23725
+/* 23703*/ OPC_Scope, 9, /*->23714*/ // 2 children in Scope
+/* 23705*/ OPC_CheckPatternPredicate, 28, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23707*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] })) - Complexity = 11
+ // Dst: (FCVT_D_WU:{ *:[f64] } ?:{ *:[i32] }:$rs1)
+/* 23714*/ /*Scope*/ 9, /*->23724*/
+/* 23715*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit())
+/* 23717*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] })) - Complexity = 11
+ // Dst: (FCVT_D_WU:{ *:[f64] } ?:{ *:[i32] }:$rs1)
+/* 23724*/ 0, /*End of Scope*/
+/* 23725*/ 0, // EndSwitchType
+/* 23726*/ /*SwitchType*/ 29, MVT::i64,// ->23757
+/* 23728*/ OPC_MoveParent,
+/* 23729*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->23745
+/* 23732*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23734*/ OPC_EmitInteger, MVT::i64, 7,
+/* 23737*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] })) - Complexity = 11
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 23745*/ /*SwitchType*/ 9, MVT::f64,// ->23756
+/* 23747*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23749*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] })) - Complexity = 11
+ // Dst: (FCVT_D_WU:{ *:[f64] } ?:{ *:[i64] }:$rs1)
+/* 23756*/ 0, // EndSwitchType
+/* 23757*/ 0, // EndSwitchType
+/* 23758*/ /*Scope*/ 100, /*->23859*/
+/* 23759*/ OPC_CheckOpcode, TARGET_VAL(ISD::AssertZext),
+/* 23762*/ OPC_RecordChild0, // #0 = $rs1
+/* 23763*/ OPC_CheckPredicate, 0, // Predicate_assertzexti32
+/* 23765*/ OPC_SwitchType /*2 cases */, 59, MVT::i32,// ->23827
+/* 23768*/ OPC_MoveParent,
+/* 23769*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->23802
+/* 23772*/ OPC_Scope, 13, /*->23787*/ // 2 children in Scope
+/* 23774*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23776*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23779*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>) - Complexity = 7
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23787*/ /*Scope*/ 13, /*->23801*/
+/* 23788*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit())
+/* 23790*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23793*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>) - Complexity = 7
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23801*/ 0, /*End of Scope*/
+/* 23802*/ /*SwitchType*/ 22, MVT::f64,// ->23826
+/* 23804*/ OPC_Scope, 9, /*->23815*/ // 2 children in Scope
+/* 23806*/ OPC_CheckPatternPredicate, 28, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23808*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>) - Complexity = 7
+ // Dst: (FCVT_D_WU:{ *:[f64] } ?:{ *:[i32] }:$rs1)
+/* 23815*/ /*Scope*/ 9, /*->23825*/
+/* 23816*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit())
+/* 23818*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } (assertzext:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_assertzexti32>>) - Complexity = 7
+ // Dst: (FCVT_D_WU:{ *:[f64] } ?:{ *:[i32] }:$rs1)
+/* 23825*/ 0, /*End of Scope*/
+/* 23826*/ 0, // EndSwitchType
+/* 23827*/ /*SwitchType*/ 29, MVT::i64,// ->23858
+/* 23829*/ OPC_MoveParent,
+/* 23830*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->23846
+/* 23833*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23835*/ OPC_EmitInteger, MVT::i64, 7,
+/* 23838*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>) - Complexity = 7
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 23846*/ /*SwitchType*/ 9, MVT::f64,// ->23857
+/* 23848*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 23850*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } (assertzext:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_assertzexti32>>) - Complexity = 7
+ // Dst: (FCVT_D_WU:{ *:[f64] } ?:{ *:[i64] }:$rs1)
+/* 23857*/ 0, // EndSwitchType
+/* 23858*/ 0, // EndSwitchType
+/* 23859*/ 0, /*End of Scope*/
+/* 23860*/ /*Scope*/ 86|128,1/*214*/, /*->24076*/
+/* 23862*/ OPC_RecordChild0, // #0 = $rs1
+/* 23863*/ OPC_Scope, 16|128,1/*144*/, /*->24010*/ // 2 children in Scope
+/* 23866*/ OPC_CheckChild0Type, MVT::i32,
+/* 23868*/ OPC_SwitchType /*2 cases */, 86, MVT::f32,// ->23957
+/* 23871*/ OPC_Scope, 13, /*->23886*/ // 6 children in Scope
+/* 23873*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23875*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23878*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23886*/ /*Scope*/ 13, /*->23900*/
+/* 23887*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit())
+/* 23889*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23892*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23900*/ /*Scope*/ 13, /*->23914*/
+/* 23901*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23903*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23906*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23914*/ /*Scope*/ 13, /*->23928*/
+/* 23915*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit())
+/* 23917*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23920*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23928*/ /*Scope*/ 13, /*->23942*/
+/* 23929*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23931*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23934*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_LU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_LU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23942*/ /*Scope*/ 13, /*->23956*/
+/* 23943*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit())
+/* 23945*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23948*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_LU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_LU:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23956*/ 0, /*End of Scope*/
+/* 23957*/ /*SwitchType*/ 50, MVT::f64,// ->24009
+/* 23959*/ OPC_Scope, 9, /*->23970*/ // 4 children in Scope
+/* 23961*/ OPC_CheckPatternPredicate, 35, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23963*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+/* 23970*/ /*Scope*/ 9, /*->23980*/
+/* 23971*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit())
+/* 23973*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+/* 23980*/ /*Scope*/ 13, /*->23994*/
+/* 23981*/ OPC_CheckPatternPredicate, 28, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 23983*/ OPC_EmitInteger, MVT::i32, 7,
+/* 23986*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_LU), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 23994*/ /*Scope*/ 13, /*->24008*/
+/* 23995*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit())
+/* 23997*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24000*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_LU), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24008*/ 0, /*End of Scope*/
+/* 24009*/ 0, // EndSwitchType
+/* 24010*/ /*Scope*/ 64, /*->24075*/
+/* 24011*/ OPC_CheckChild0Type, MVT::i64,
+/* 24013*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->24046
+/* 24016*/ OPC_Scope, 13, /*->24031*/ // 2 children in Scope
+/* 24018*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24020*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24023*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_WU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_WU:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 24031*/ /*Scope*/ 13, /*->24045*/
+/* 24032*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24034*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24037*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_LU), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f32] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_LU:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 24045*/ 0, /*End of Scope*/
+/* 24046*/ /*SwitchType*/ 26, MVT::f64,// ->24074
+/* 24048*/ OPC_Scope, 9, /*->24059*/ // 2 children in Scope
+/* 24050*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24052*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_WU), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i64] }:$rs1)
+/* 24059*/ /*Scope*/ 13, /*->24073*/
+/* 24060*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24062*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24065*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_LU), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 24073*/ 0, /*End of Scope*/
+/* 24074*/ 0, // EndSwitchType
+/* 24075*/ 0, /*End of Scope*/
+/* 24076*/ 0, /*End of Scope*/
+/* 24077*/ /*SwitchOpcode*/ 92|128,3/*476*/, TARGET_VAL(ISD::FMA),// ->24557
+/* 24081*/ OPC_Scope, 119, /*->24202*/ // 6 children in Scope
+/* 24083*/ OPC_MoveChild0,
+/* 24084*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+/* 24087*/ OPC_RecordChild0, // #0 = $rs1
+/* 24088*/ OPC_MoveParent,
+/* 24089*/ OPC_RecordChild1, // #1 = $rs2
+/* 24090*/ OPC_MoveChild2,
+/* 24091*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+/* 24094*/ OPC_RecordChild0, // #2 = $rs3
+/* 24095*/ OPC_MoveParent,
+/* 24096*/ OPC_SwitchType /*2 cases */, 50, MVT::f32,// ->24149
+/* 24099*/ OPC_Scope, 15, /*->24116*/ // 3 children in Scope
+/* 24101*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24103*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24106*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMADD_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) - Complexity = 9
+ // Dst: (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+/* 24116*/ /*Scope*/ 15, /*->24132*/
+/* 24117*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24119*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24122*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMADD_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) - Complexity = 9
+ // Dst: (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
+/* 24132*/ /*Scope*/ 15, /*->24148*/
+/* 24133*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 24135*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24138*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMADD_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) - Complexity = 9
+ // Dst: (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+/* 24148*/ 0, /*End of Scope*/
+/* 24149*/ /*SwitchType*/ 50, MVT::f64,// ->24201
+/* 24151*/ OPC_Scope, 15, /*->24168*/ // 3 children in Scope
+/* 24153*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24155*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24158*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMADD_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) - Complexity = 9
+ // Dst: (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+/* 24168*/ /*Scope*/ 15, /*->24184*/
+/* 24169*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24171*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24174*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMADD_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) - Complexity = 9
+ // Dst: (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
+/* 24184*/ /*Scope*/ 15, /*->24200*/
+/* 24185*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 24187*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24190*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMADD_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) - Complexity = 9
+ // Dst: (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+/* 24200*/ 0, /*End of Scope*/
+/* 24201*/ 0, // EndSwitchType
+/* 24202*/ /*Scope*/ 60, /*->24263*/
+/* 24203*/ OPC_RecordChild0, // #0 = $rs1
+/* 24204*/ OPC_RecordChild1, // #1 = $rs2
+/* 24205*/ OPC_MoveChild2,
+/* 24206*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+/* 24209*/ OPC_RecordChild0, // #2 = $rs3
+/* 24210*/ OPC_MoveParent,
+/* 24211*/ OPC_CheckType, MVT::f32,
+/* 24213*/ OPC_Scope, 15, /*->24230*/ // 3 children in Scope
+/* 24215*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24217*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24220*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMSUB_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) - Complexity = 6
+ // Dst: (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+/* 24230*/ /*Scope*/ 15, /*->24246*/
+/* 24231*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24233*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24236*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMSUB_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) - Complexity = 6
+ // Dst: (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
+/* 24246*/ /*Scope*/ 15, /*->24262*/
+/* 24247*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 24249*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24252*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMSUB_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) - Complexity = 6
+ // Dst: (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+/* 24262*/ 0, /*End of Scope*/
+/* 24263*/ /*Scope*/ 60, /*->24324*/
+/* 24264*/ OPC_MoveChild0,
+/* 24265*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+/* 24268*/ OPC_RecordChild0, // #0 = $rs1
+/* 24269*/ OPC_MoveParent,
+/* 24270*/ OPC_RecordChild1, // #1 = $rs2
+/* 24271*/ OPC_RecordChild2, // #2 = $rs3
+/* 24272*/ OPC_CheckType, MVT::f32,
+/* 24274*/ OPC_Scope, 15, /*->24291*/ // 3 children in Scope
+/* 24276*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24278*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24281*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMSUB_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) - Complexity = 6
+ // Dst: (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+/* 24291*/ /*Scope*/ 15, /*->24307*/
+/* 24292*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24294*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24297*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMSUB_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) - Complexity = 6
+ // Dst: (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
+/* 24307*/ /*Scope*/ 15, /*->24323*/
+/* 24308*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 24310*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24313*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMSUB_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) - Complexity = 6
+ // Dst: (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+/* 24323*/ 0, /*End of Scope*/
+/* 24324*/ /*Scope*/ 60, /*->24385*/
+/* 24325*/ OPC_RecordChild0, // #0 = $rs1
+/* 24326*/ OPC_RecordChild1, // #1 = $rs2
+/* 24327*/ OPC_MoveChild2,
+/* 24328*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+/* 24331*/ OPC_RecordChild0, // #2 = $rs3
+/* 24332*/ OPC_MoveParent,
+/* 24333*/ OPC_CheckType, MVT::f64,
+/* 24335*/ OPC_Scope, 15, /*->24352*/ // 3 children in Scope
+/* 24337*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24339*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24342*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMSUB_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) - Complexity = 6
+ // Dst: (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+/* 24352*/ /*Scope*/ 15, /*->24368*/
+/* 24353*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24355*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24358*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMSUB_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) - Complexity = 6
+ // Dst: (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
+/* 24368*/ /*Scope*/ 15, /*->24384*/
+/* 24369*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 24371*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24374*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMSUB_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) - Complexity = 6
+ // Dst: (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+/* 24384*/ 0, /*End of Scope*/
+/* 24385*/ /*Scope*/ 60, /*->24446*/
+/* 24386*/ OPC_MoveChild0,
+/* 24387*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+/* 24390*/ OPC_RecordChild0, // #0 = $rs1
+/* 24391*/ OPC_MoveParent,
+/* 24392*/ OPC_RecordChild1, // #1 = $rs2
+/* 24393*/ OPC_RecordChild2, // #2 = $rs3
+/* 24394*/ OPC_CheckType, MVT::f64,
+/* 24396*/ OPC_Scope, 15, /*->24413*/ // 3 children in Scope
+/* 24398*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24400*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24403*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMSUB_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) - Complexity = 6
+ // Dst: (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+/* 24413*/ /*Scope*/ 15, /*->24429*/
+/* 24414*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24416*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24419*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMSUB_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) - Complexity = 6
+ // Dst: (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
+/* 24429*/ /*Scope*/ 15, /*->24445*/
+/* 24430*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 24432*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24435*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FNMSUB_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) - Complexity = 6
+ // Dst: (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+/* 24445*/ 0, /*End of Scope*/
+/* 24446*/ /*Scope*/ 109, /*->24556*/
+/* 24447*/ OPC_RecordChild0, // #0 = $rs1
+/* 24448*/ OPC_RecordChild1, // #1 = $rs2
+/* 24449*/ OPC_RecordChild2, // #2 = $rs3
+/* 24450*/ OPC_SwitchType /*2 cases */, 50, MVT::f32,// ->24503
+/* 24453*/ OPC_Scope, 15, /*->24470*/ // 3 children in Scope
+/* 24455*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24457*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24460*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMADD_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) - Complexity = 3
+ // Dst: (FMADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+/* 24470*/ /*Scope*/ 15, /*->24486*/
+/* 24471*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24473*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24476*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMADD_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) - Complexity = 3
+ // Dst: (FMADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i64] })
+/* 24486*/ /*Scope*/ 15, /*->24502*/
+/* 24487*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 24489*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24492*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMADD_S), 0,
+ MVT::f32, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) - Complexity = 3
+ // Dst: (FMADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, ?:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+/* 24502*/ 0, /*End of Scope*/
+/* 24503*/ /*SwitchType*/ 50, MVT::f64,// ->24555
+/* 24505*/ OPC_Scope, 15, /*->24522*/ // 3 children in Scope
+/* 24507*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24509*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24512*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMADD_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) - Complexity = 3
+ // Dst: (FMADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+/* 24522*/ /*Scope*/ 15, /*->24538*/
+/* 24523*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24525*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24528*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMADD_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) - Complexity = 3
+ // Dst: (FMADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i64] })
+/* 24538*/ /*Scope*/ 15, /*->24554*/
+/* 24539*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 24541*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24544*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMADD_D), 0,
+ MVT::f64, 4/*#Ops*/, 0, 1, 2, 3,
+ // Src: (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) - Complexity = 3
+ // Dst: (FMADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, ?:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+/* 24554*/ 0, /*End of Scope*/
+/* 24555*/ 0, // EndSwitchType
+/* 24556*/ 0, /*End of Scope*/
+/* 24557*/ /*SwitchOpcode*/ 40|128,1/*168*/, TARGET_VAL(ISD::FCOPYSIGN),// ->24729
+/* 24561*/ OPC_RecordChild0, // #0 = $rs1
+/* 24562*/ OPC_Scope, 37, /*->24601*/ // 2 children in Scope
+/* 24564*/ OPC_MoveChild1,
+/* 24565*/ OPC_CheckOpcode, TARGET_VAL(ISD::FNEG),
+/* 24568*/ OPC_RecordChild0, // #1 = $rs2
+/* 24569*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->24585
+/* 24572*/ OPC_MoveParent,
+/* 24573*/ OPC_CheckType, MVT::f32,
+/* 24575*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 24577*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJN_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs2)) - Complexity = 6
+ // Dst: (FSGNJN_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 24585*/ /*SwitchType*/ 13, MVT::f64,// ->24600
+/* 24587*/ OPC_MoveParent,
+/* 24588*/ OPC_CheckType, MVT::f64,
+/* 24590*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 24592*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJN_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fcopysign:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs2)) - Complexity = 6
+ // Dst: (FSGNJN_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 24600*/ 0, // EndSwitchType
+/* 24601*/ /*Scope*/ 126, /*->24728*/
+/* 24602*/ OPC_RecordChild1, // #1 = $rs2
+/* 24603*/ OPC_Scope, 35, /*->24640*/ // 2 children in Scope
+/* 24605*/ OPC_CheckChild1Type, MVT::f32,
+/* 24607*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->24620
+/* 24610*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 24612*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJ_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 24620*/ /*SwitchType*/ 17, MVT::f64,// ->24639
+/* 24622*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 24624*/ OPC_EmitNode1, TARGET_VAL(RISCV::FCVT_D_S), 0,
+ MVT::f64, 1/*#Ops*/, 1, // Results = #2
+/* 24631*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJ_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 2,
+ // Src: (fcopysign:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FSGNJ_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, (FCVT_D_S:{ *:[f64] } ?:{ *:[f32] }:$rs2))
+/* 24639*/ 0, // EndSwitchType
+/* 24640*/ /*Scope*/ 86, /*->24727*/
+/* 24641*/ OPC_CheckChild1Type, MVT::f64,
+/* 24643*/ OPC_SwitchType /*2 cases */, 10, MVT::f64,// ->24656
+/* 24646*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 24648*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJ_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fcopysign:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FSGNJ_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 24656*/ /*SwitchType*/ 68, MVT::f32,// ->24726
+/* 24658*/ OPC_Scope, 21, /*->24681*/ // 3 children in Scope
+/* 24660*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24662*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24665*/ OPC_EmitNode1, TARGET_VAL(RISCV::FCVT_S_D), 0,
+ MVT::f32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 24673*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJ_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 3,
+ // Src: (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_D:{ *:[f32] } ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }))
+/* 24681*/ /*Scope*/ 21, /*->24703*/
+/* 24682*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24684*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24687*/ OPC_EmitNode1, TARGET_VAL(RISCV::FCVT_S_D), 0,
+ MVT::f32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 24695*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJ_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 3,
+ // Src: (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_D:{ *:[f32] } ?:{ *:[f64] }:$rs2, 7:{ *:[i64] }))
+/* 24703*/ /*Scope*/ 21, /*->24725*/
+/* 24704*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 24706*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24709*/ OPC_EmitNode1, TARGET_VAL(RISCV::FCVT_S_D), 0,
+ MVT::f32, 2/*#Ops*/, 1, 2, // Results = #3
+/* 24717*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJ_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 3,
+ // Src: (fcopysign:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FSGNJ_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, (FCVT_S_D:{ *:[f32] } ?:{ *:[f64] }:$rs2, 7:{ *:[i32] }))
+/* 24725*/ 0, /*End of Scope*/
+/* 24726*/ 0, // EndSwitchType
+/* 24727*/ 0, /*End of Scope*/
+/* 24728*/ 0, /*End of Scope*/
+/* 24729*/ /*SwitchOpcode*/ 1|128,2/*257*/, TARGET_VAL(ISD::SINT_TO_FP),// ->24990
+/* 24733*/ OPC_Scope, 38, /*->24773*/ // 2 children in Scope
+/* 24735*/ OPC_MoveChild0,
+/* 24736*/ OPC_CheckOpcode, TARGET_VAL(ISD::SIGN_EXTEND_INREG),
+/* 24739*/ OPC_RecordChild0, // #0 = $rs1
+/* 24740*/ OPC_MoveChild1,
+/* 24741*/ OPC_CheckValueType, MVT::i32,
+/* 24743*/ OPC_MoveParent,
+/* 24744*/ OPC_MoveParent,
+/* 24745*/ OPC_SwitchType /*2 cases */, 13, MVT::f32,// ->24761
+/* 24748*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24750*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24753*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_W), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs1, i32:{ *:[Other] })) - Complexity = 6
+ // Dst: (FCVT_S_W:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 24761*/ /*SwitchType*/ 9, MVT::f64,// ->24772
+/* 24763*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24765*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_W), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[f64] } (sext_inreg:{ *:[i64] } GPR:{ *:[i64] }:$rs1, i32:{ *:[Other] })) - Complexity = 6
+ // Dst: (FCVT_D_W:{ *:[f64] } ?:{ *:[i64] }:$rs1)
+/* 24772*/ 0, // EndSwitchType
+/* 24773*/ /*Scope*/ 86|128,1/*214*/, /*->24989*/
+/* 24775*/ OPC_RecordChild0, // #0 = $rs1
+/* 24776*/ OPC_Scope, 16|128,1/*144*/, /*->24923*/ // 2 children in Scope
+/* 24779*/ OPC_CheckChild0Type, MVT::i32,
+/* 24781*/ OPC_SwitchType /*2 cases */, 86, MVT::f32,// ->24870
+/* 24784*/ OPC_Scope, 13, /*->24799*/ // 6 children in Scope
+/* 24786*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24788*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24791*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_W), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24799*/ /*Scope*/ 13, /*->24813*/
+/* 24800*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit())
+/* 24802*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24805*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_W), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24813*/ /*Scope*/ 13, /*->24827*/
+/* 24814*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24816*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24819*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_W), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24827*/ /*Scope*/ 13, /*->24841*/
+/* 24828*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit())
+/* 24830*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24833*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_W), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_W:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24841*/ /*Scope*/ 13, /*->24855*/
+/* 24842*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24844*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24847*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_L), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_L:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24855*/ /*Scope*/ 13, /*->24869*/
+/* 24856*/ OPC_CheckPatternPredicate, 33, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit())
+/* 24858*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24861*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_L), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_L:{ *:[f32] } ?:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24869*/ 0, /*End of Scope*/
+/* 24870*/ /*SwitchType*/ 50, MVT::f64,// ->24922
+/* 24872*/ OPC_Scope, 9, /*->24883*/ // 4 children in Scope
+/* 24874*/ OPC_CheckPatternPredicate, 35, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24876*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_W), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+/* 24883*/ /*Scope*/ 9, /*->24893*/
+/* 24884*/ OPC_CheckPatternPredicate, 36, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit())
+/* 24886*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_W), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+/* 24893*/ /*Scope*/ 13, /*->24907*/
+/* 24894*/ OPC_CheckPatternPredicate, 28, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 24896*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24899*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_L), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_L:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24907*/ /*Scope*/ 13, /*->24921*/
+/* 24908*/ OPC_CheckPatternPredicate, 29, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit())
+/* 24910*/ OPC_EmitInteger, MVT::i32, 7,
+/* 24913*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_L), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_L:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+/* 24921*/ 0, /*End of Scope*/
+/* 24922*/ 0, // EndSwitchType
+/* 24923*/ /*Scope*/ 64, /*->24988*/
+/* 24924*/ OPC_CheckChild0Type, MVT::i64,
+/* 24926*/ OPC_SwitchType /*2 cases */, 30, MVT::f32,// ->24959
+/* 24929*/ OPC_Scope, 13, /*->24944*/ // 2 children in Scope
+/* 24931*/ OPC_CheckPatternPredicate, 34, // (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24933*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24936*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_W), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_W:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 24944*/ /*Scope*/ 13, /*->24958*/
+/* 24945*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24947*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24950*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_L), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f32] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_L:{ *:[f32] } ?:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 24958*/ 0, /*End of Scope*/
+/* 24959*/ /*SwitchType*/ 26, MVT::f64,// ->24987
+/* 24961*/ OPC_Scope, 9, /*->24972*/ // 2 children in Scope
+/* 24963*/ OPC_CheckPatternPredicate, 37, // (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24965*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_W), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_W:{ *:[f64] } GPR:{ *:[i64] }:$rs1)
+/* 24972*/ /*Scope*/ 13, /*->24986*/
+/* 24973*/ OPC_CheckPatternPredicate, 23, // (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 24975*/ OPC_EmitInteger, MVT::i64, 7,
+/* 24978*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_L), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_L:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+/* 24986*/ 0, /*End of Scope*/
+/* 24987*/ 0, // EndSwitchType
+/* 24988*/ 0, /*End of Scope*/
+/* 24989*/ 0, /*End of Scope*/
+/* 24990*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::FNEG),// ->25020
+/* 24993*/ OPC_RecordChild0, // #0 = $rs1
+/* 24994*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->25007
+/* 24997*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 24999*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJN_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 0,
+ // Src: (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FSGNJN_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs1)
+/* 25007*/ /*SwitchType*/ 10, MVT::f64,// ->25019
+/* 25009*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25011*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJN_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 0,
+ // Src: (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FSGNJN_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs1)
+/* 25019*/ 0, // EndSwitchType
+/* 25020*/ /*SwitchOpcode*/ 27, TARGET_VAL(ISD::FABS),// ->25050
+/* 25023*/ OPC_RecordChild0, // #0 = $rs1
+/* 25024*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->25037
+/* 25027*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 25029*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJX_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 0,
+ // Src: (fabs:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FSGNJX_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs1)
+/* 25037*/ /*SwitchType*/ 10, MVT::f64,// ->25049
+/* 25039*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25041*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSGNJX_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 0,
+ // Src: (fabs:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FSGNJX_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs1)
+/* 25049*/ 0, // EndSwitchType
+/* 25050*/ /*SwitchOpcode*/ 28, TARGET_VAL(ISD::FMINNUM),// ->25081
+/* 25053*/ OPC_RecordChild0, // #0 = $rs1
+/* 25054*/ OPC_RecordChild1, // #1 = $rs2
+/* 25055*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->25068
+/* 25058*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 25060*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMIN_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fminnum:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FMIN_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 25068*/ /*SwitchType*/ 10, MVT::f64,// ->25080
+/* 25070*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25072*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMIN_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fminnum:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FMIN_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 25080*/ 0, // EndSwitchType
+/* 25081*/ /*SwitchOpcode*/ 28, TARGET_VAL(ISD::FMAXNUM),// ->25112
+/* 25084*/ OPC_RecordChild0, // #0 = $rs1
+/* 25085*/ OPC_RecordChild1, // #1 = $rs2
+/* 25086*/ OPC_SwitchType /*2 cases */, 10, MVT::f32,// ->25099
+/* 25089*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 25091*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMAX_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fmaxnum:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FMAX_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2)
+/* 25099*/ /*SwitchType*/ 10, MVT::f64,// ->25111
+/* 25101*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25103*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMAX_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fmaxnum:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FMAX_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2)
+/* 25111*/ 0, // EndSwitchType
+/* 25112*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::FP_EXTEND),// ->25125
+/* 25115*/ OPC_RecordChild0, // #0 = $rs1
+/* 25116*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25118*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_D_S), 0,
+ MVT::f64, 1/*#Ops*/, 0,
+ // Src: (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_D_S:{ *:[f64] } FPR32:{ *:[f32] }:$rs1)
+/* 25125*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::FADD),// ->25230
+/* 25128*/ OPC_RecordChild0, // #0 = $rs1
+/* 25129*/ OPC_RecordChild1, // #1 = $rs2
+/* 25130*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->25180
+/* 25133*/ OPC_Scope, 14, /*->25149*/ // 3 children in Scope
+/* 25135*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25137*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25140*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })
+/* 25149*/ /*Scope*/ 14, /*->25164*/
+/* 25150*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25152*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25155*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] })
+/* 25164*/ /*Scope*/ 14, /*->25179*/
+/* 25165*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 25167*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25170*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FADD_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FADD_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })
+/* 25179*/ 0, /*End of Scope*/
+/* 25180*/ /*SwitchType*/ 47, MVT::f64,// ->25229
+/* 25182*/ OPC_Scope, 14, /*->25198*/ // 3 children in Scope
+/* 25184*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25186*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25189*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FADD_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })
+/* 25198*/ /*Scope*/ 14, /*->25213*/
+/* 25199*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25201*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25204*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FADD_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })
+/* 25213*/ /*Scope*/ 14, /*->25228*/
+/* 25214*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25216*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25219*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FADD_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FADD_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })
+/* 25228*/ 0, /*End of Scope*/
+/* 25229*/ 0, // EndSwitchType
+/* 25230*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::FSUB),// ->25335
+/* 25233*/ OPC_RecordChild0, // #0 = $rs1
+/* 25234*/ OPC_RecordChild1, // #1 = $rs2
+/* 25235*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->25285
+/* 25238*/ OPC_Scope, 14, /*->25254*/ // 3 children in Scope
+/* 25240*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25242*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25245*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSUB_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FSUB_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })
+/* 25254*/ /*Scope*/ 14, /*->25269*/
+/* 25255*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25257*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25260*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSUB_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FSUB_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] })
+/* 25269*/ /*Scope*/ 14, /*->25284*/
+/* 25270*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 25272*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25275*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSUB_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FSUB_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })
+/* 25284*/ 0, /*End of Scope*/
+/* 25285*/ /*SwitchType*/ 47, MVT::f64,// ->25334
+/* 25287*/ OPC_Scope, 14, /*->25303*/ // 3 children in Scope
+/* 25289*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25291*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25294*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSUB_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FSUB_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })
+/* 25303*/ /*Scope*/ 14, /*->25318*/
+/* 25304*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25306*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25309*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSUB_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FSUB_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })
+/* 25318*/ /*Scope*/ 14, /*->25333*/
+/* 25319*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25321*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25324*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSUB_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FSUB_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })
+/* 25333*/ 0, /*End of Scope*/
+/* 25334*/ 0, // EndSwitchType
+/* 25335*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::FMUL),// ->25440
+/* 25338*/ OPC_RecordChild0, // #0 = $rs1
+/* 25339*/ OPC_RecordChild1, // #1 = $rs2
+/* 25340*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->25390
+/* 25343*/ OPC_Scope, 14, /*->25359*/ // 3 children in Scope
+/* 25345*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25347*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25350*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMUL_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FMUL_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })
+/* 25359*/ /*Scope*/ 14, /*->25374*/
+/* 25360*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25362*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25365*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMUL_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FMUL_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] })
+/* 25374*/ /*Scope*/ 14, /*->25389*/
+/* 25375*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 25377*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25380*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMUL_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FMUL_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })
+/* 25389*/ 0, /*End of Scope*/
+/* 25390*/ /*SwitchType*/ 47, MVT::f64,// ->25439
+/* 25392*/ OPC_Scope, 14, /*->25408*/ // 3 children in Scope
+/* 25394*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25396*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25399*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMUL_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FMUL_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })
+/* 25408*/ /*Scope*/ 14, /*->25423*/
+/* 25409*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25411*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25414*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMUL_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FMUL_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })
+/* 25423*/ /*Scope*/ 14, /*->25438*/
+/* 25424*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25426*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25429*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMUL_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FMUL_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })
+/* 25438*/ 0, /*End of Scope*/
+/* 25439*/ 0, // EndSwitchType
+/* 25440*/ /*SwitchOpcode*/ 102, TARGET_VAL(ISD::FDIV),// ->25545
+/* 25443*/ OPC_RecordChild0, // #0 = $rs1
+/* 25444*/ OPC_RecordChild1, // #1 = $rs2
+/* 25445*/ OPC_SwitchType /*2 cases */, 47, MVT::f32,// ->25495
+/* 25448*/ OPC_Scope, 14, /*->25464*/ // 3 children in Scope
+/* 25450*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25452*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25455*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FDIV_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FDIV_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })
+/* 25464*/ /*Scope*/ 14, /*->25479*/
+/* 25465*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25467*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25470*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FDIV_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FDIV_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i64] })
+/* 25479*/ /*Scope*/ 14, /*->25494*/
+/* 25480*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 25482*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25485*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FDIV_S), 0,
+ MVT::f32, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2) - Complexity = 3
+ // Dst: (FDIV_S:{ *:[f32] } ?:{ *:[f32] }:$rs1, ?:{ *:[f32] }:$rs2, 7:{ *:[i32] })
+/* 25494*/ 0, /*End of Scope*/
+/* 25495*/ /*SwitchType*/ 47, MVT::f64,// ->25544
+/* 25497*/ OPC_Scope, 14, /*->25513*/ // 3 children in Scope
+/* 25499*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25501*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25504*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FDIV_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FDIV_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })
+/* 25513*/ /*Scope*/ 14, /*->25528*/
+/* 25514*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25516*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25519*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FDIV_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FDIV_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i64] })
+/* 25528*/ /*Scope*/ 14, /*->25543*/
+/* 25529*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25531*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25534*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FDIV_D), 0,
+ MVT::f64, 3/*#Ops*/, 0, 1, 2,
+ // Src: (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2) - Complexity = 3
+ // Dst: (FDIV_D:{ *:[f64] } ?:{ *:[f64] }:$rs1, ?:{ *:[f64] }:$rs2, 7:{ *:[i32] })
+/* 25543*/ 0, /*End of Scope*/
+/* 25544*/ 0, // EndSwitchType
+/* 25545*/ /*SwitchOpcode*/ 95, TARGET_VAL(ISD::FSQRT),// ->25643
+/* 25548*/ OPC_RecordChild0, // #0 = $rs1
+/* 25549*/ OPC_SwitchType /*2 cases */, 44, MVT::f32,// ->25596
+/* 25552*/ OPC_Scope, 13, /*->25567*/ // 3 children in Scope
+/* 25554*/ OPC_CheckPatternPredicate, 11, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25556*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25559*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSQRT_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] })
+/* 25567*/ /*Scope*/ 13, /*->25581*/
+/* 25568*/ OPC_CheckPatternPredicate, 15, // (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25570*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25573*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSQRT_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] })
+/* 25581*/ /*Scope*/ 13, /*->25595*/
+/* 25582*/ OPC_CheckPatternPredicate, 12, // (Subtarget->hasStdExtF())
+/* 25584*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25587*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSQRT_S), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) - Complexity = 3
+ // Dst: (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] })
+/* 25595*/ 0, /*End of Scope*/
+/* 25596*/ /*SwitchType*/ 44, MVT::f64,// ->25642
+/* 25598*/ OPC_Scope, 13, /*->25613*/ // 3 children in Scope
+/* 25600*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25602*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25605*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSQRT_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
+/* 25613*/ /*Scope*/ 13, /*->25627*/
+/* 25614*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25616*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25619*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSQRT_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] })
+/* 25627*/ /*Scope*/ 13, /*->25641*/
+/* 25628*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25630*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25633*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FSQRT_D), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
+/* 25641*/ 0, /*End of Scope*/
+/* 25642*/ 0, // EndSwitchType
+/* 25643*/ /*SwitchOpcode*/ 10, TARGET_VAL(RISCVISD::FMV_W_X_RV64),// ->25656
+/* 25646*/ OPC_RecordChild0, // #0 = $src
+/* 25647*/ OPC_CheckPatternPredicate, 24, // (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25649*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FMV_W_X), 0,
+ MVT::f32, 1/*#Ops*/, 0,
+ // Src: (riscv_fmv_w_x_rv64:{ *:[f32] } GPR:{ *:[i64] }:$src) - Complexity = 3
+ // Dst: (FMV_W_X:{ *:[f32] } GPR:{ *:[i64] }:$src)
+/* 25656*/ /*SwitchOpcode*/ 45, TARGET_VAL(ISD::FP_ROUND),// ->25704
+/* 25659*/ OPC_RecordChild0, // #0 = $rs1
+/* 25660*/ OPC_Scope, 13, /*->25675*/ // 3 children in Scope
+/* 25662*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25664*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25667*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_D), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
+/* 25675*/ /*Scope*/ 13, /*->25689*/
+/* 25676*/ OPC_CheckPatternPredicate, 16, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"))
+/* 25678*/ OPC_EmitInteger, MVT::i64, 7,
+/* 25681*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_D), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] })
+/* 25689*/ /*Scope*/ 13, /*->25703*/
+/* 25690*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25692*/ OPC_EmitInteger, MVT::i32, 7,
+/* 25695*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::FCVT_S_D), 0,
+ MVT::f32, 2/*#Ops*/, 0, 1,
+ // Src: (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) - Complexity = 3
+ // Dst: (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
+/* 25703*/ 0, /*End of Scope*/
+/* 25704*/ /*SwitchOpcode*/ 26, TARGET_VAL(RISCVISD::BuildPairF64),// ->25733
+/* 25707*/ OPC_RecordChild0, // #0 = $src1
+/* 25708*/ OPC_RecordChild1, // #1 = $src2
+/* 25709*/ OPC_Scope, 10, /*->25721*/ // 2 children in Scope
+/* 25711*/ OPC_CheckPatternPredicate, 13, // (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"))
+/* 25713*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::BuildPairF64Pseudo), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (RISCVBuildPairF64:{ *:[f64] } GPR:{ *:[i32] }:$src1, GPR:{ *:[i32] }:$src2) - Complexity = 3
+ // Dst: (BuildPairF64Pseudo:{ *:[f64] } GPR:{ *:[i32] }:$src1, GPR:{ *:[i32] }:$src2)
+/* 25721*/ /*Scope*/ 10, /*->25732*/
+/* 25722*/ OPC_CheckPatternPredicate, 14, // (Subtarget->hasStdExtD())
+/* 25724*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::BuildPairF64Pseudo), 0,
+ MVT::f64, 2/*#Ops*/, 0, 1,
+ // Src: (RISCVBuildPairF64:{ *:[f64] } GPR:{ *:[i32] }:$src1, GPR:{ *:[i32] }:$src2) - Complexity = 3
+ // Dst: (BuildPairF64Pseudo:{ *:[f64] } GPR:{ *:[i32] }:$src1, GPR:{ *:[i32] }:$src2)
+/* 25732*/ 0, /*End of Scope*/
+/* 25733*/ 0, // EndSwitchOpcode
+ 0
+ }; // Total Array size is 25735 bytes
+
+ // Opcode Histogram:
+ // #OPC_Scope = 627
+ // #OPC_RecordNode = 33
+ // #OPC_RecordChild = 364
+ // #OPC_RecordMemRef = 16
+ // #OPC_CaptureGlueInput = 8
+ // #OPC_MoveChild = 160
+ // #OPC_MoveParent = 260
+ // #OPC_CheckSame = 0
+ // #OPC_CheckChildSame = 0
+ // #OPC_CheckPatternPredicate = 1223
+ // #OPC_CheckPredicate = 721
+ // #OPC_CheckOpcode = 128
+ // #OPC_SwitchOpcode = 18
+ // #OPC_CheckType = 77
+ // #OPC_SwitchType = 146
+ // #OPC_CheckChildType = 123
+ // #OPC_CheckInteger = 0
+ // #OPC_CheckChildInteger = 24
+ // #OPC_CheckCondCode = 0
+ // #OPC_CheckChild2CondCode = 68
+ // #OPC_CheckValueType = 22
+ // #OPC_CheckComplexPat = 256
+ // #OPC_CheckAndImm = 15
+ // #OPC_CheckOrImm = 0
+ // #OPC_CheckImmAllOnesV = 0
+ // #OPC_CheckImmAllZerosV = 0
+ // #OPC_CheckFoldableChainNode = 0
+ // #OPC_EmitInteger = 406
+ // #OPC_EmitStringInteger = 0
+ // #OPC_EmitRegister = 66
+ // #OPC_EmitConvertToTarget = 343
+ // #OPC_EmitMergeInputChains = 894
+ // #OPC_EmitCopyToReg = 0
+ // #OPC_EmitNode = 94
+ // #OPC_EmitNodeXForm = 9
+ // #OPC_CompleteMatch = 0
+ // #OPC_MorphNodeTo = 1338
+
+ #undef TARGET_VAL
+ SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckPatternPredicate(unsigned PredNo) const override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckPatternPredicate(unsigned PredNo) const
+#if DAGISEL_INLINE
+ override
+#endif
+ {
+ switch (PredNo) {
+ default: llvm_unreachable("Invalid predicate in table?");
+ case 0: return (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 1: return (Subtarget->hasStdExtM()) && (Subtarget->is64Bit());
+ case 2: return (Subtarget->hasStdExtM()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 3: return (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 4: return (Subtarget->is64Bit());
+ case 5: return (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 6: return (MF->getSubtarget().checkFeatures("-64bit"));
+ case 7: return (MF->getSubtarget().checkFeatures("+64bit"));
+ case 8: return (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 9: return (!Subtarget->is64Bit());
+ case 10: return (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 11: return (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 12: return (Subtarget->hasStdExtF());
+ case 13: return (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 14: return (Subtarget->hasStdExtD());
+ case 15: return (Subtarget->hasStdExtF()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 16: return (Subtarget->hasStdExtD()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 17: return (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 18: return (Subtarget->hasStdExtA());
+ case 19: return (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 20: return (Subtarget->hasStdExtA()) && (Subtarget->is64Bit());
+ case 21: return (Subtarget->hasStdExtA()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 22: return (Subtarget->hasStdExtA()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 23: return (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 24: return (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 25: return (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 26: return (Subtarget->hasStdExtM());
+ case 27: return (Subtarget->hasStdExtM()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 28: return (Subtarget->hasStdExtD()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 29: return (Subtarget->hasStdExtD()) && (Subtarget->is64Bit());
+ case 30: return (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 31: return (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit());
+ case 32: return (Subtarget->hasStdExtF()) && (Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 33: return (Subtarget->hasStdExtF()) && (Subtarget->is64Bit());
+ case 34: return (Subtarget->hasStdExtF()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ case 35: return (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("-64bit"));
+ case 36: return (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit());
+ case 37: return (Subtarget->hasStdExtD()) && (!Subtarget->is64Bit()) && (MF->getSubtarget().checkFeatures("+64bit"));
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckNodePredicate(SDNode *Node, unsigned PredNo) const
+#if DAGISEL_INLINE
+ override
+#endif
+ {
+ switch (PredNo) {
+ default: llvm_unreachable("Invalid predicate in table?");
+ case 0: {
+ // Predicate_assertzexti32
+ // Predicate_assertsexti32
+ SDNode *N = Node;
+ (void)N;
+
+ return cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32;
+
+ }
+ case 1: {
+ // Predicate_simm12
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isInt<12>(Imm);
+ }
+ case 2: {
+ // Predicate_IsOrAdd
+ SDNode *N = Node;
+ (void)N;
+
+ return isOrEquivalentToAdd(N);
+
+ }
+ case 3: {
+ // Predicate_unindexedload
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getAddressingMode() != ISD::UNINDEXED) return false;
+return true;
+
+ }
+ case 4: {
+ // Predicate_sextload
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::SEXTLOAD) return false;
+return true;
+
+ }
+ case 5: {
+ // Predicate_sextloadi8
+ // Predicate_extloadi8
+ // Predicate_zextloadi8
+ // Predicate_truncstorei8
+ // Predicate_atomic_store_8
+ // Predicate_atomic_load_8
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i8) return false;
+return true;
+
+ }
+ case 6: {
+ // Predicate_extload
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::EXTLOAD) return false;
+return true;
+
+ }
+ case 7: {
+ // Predicate_sextloadi16
+ // Predicate_extloadi16
+ // Predicate_zextloadi16
+ // Predicate_truncstorei16
+ // Predicate_atomic_store_16
+ // Predicate_atomic_load_16
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i16) return false;
+return true;
+
+ }
+ case 8: {
+ // Predicate_load
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD) return false;
+return true;
+
+ }
+ case 9: {
+ // Predicate_zextload
+ SDNode *N = Node;
+ (void)N;
+if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
+return true;
+
+ }
+ case 10: {
+ // Predicate_sextloadi32
+ // Predicate_extloadi32
+ // Predicate_zextloadi32
+ // Predicate_truncstorei32
+ // Predicate_atomic_store_32
+ // Predicate_atomic_load_32
+ // Predicate_atomic_swap_32
+ // Predicate_atomic_load_add_32
+ // Predicate_atomic_load_and_32
+ // Predicate_atomic_load_or_32
+ // Predicate_atomic_load_xor_32
+ // Predicate_atomic_load_max_32
+ // Predicate_atomic_load_min_32
+ // Predicate_atomic_load_umax_32
+ // Predicate_atomic_load_umin_32
+ // Predicate_atomic_load_nand_32
+ // Predicate_atomic_cmp_swap_32
+ // Predicate_atomic_load_sub_32
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i32) return false;
+return true;
+
+ }
+ case 11: {
+ // Predicate_unindexedstore
+ SDNode *N = Node;
+ (void)N;
+if (cast<StoreSDNode>(N)->getAddressingMode() != ISD::UNINDEXED) return false;
+return true;
+
+ }
+ case 12: {
+ // Predicate_truncstore
+ SDNode *N = Node;
+ (void)N;
+ if (!cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 13: {
+ // Predicate_store
+ SDNode *N = Node;
+ (void)N;
+ if (cast<StoreSDNode>(N)->isTruncatingStore()) return false;
+return true;
+
+ }
+ case 14: {
+ // Predicate_atomic_store_64
+ // Predicate_atomic_load_64
+ // Predicate_atomic_swap_64
+ // Predicate_atomic_load_add_64
+ // Predicate_atomic_load_and_64
+ // Predicate_atomic_load_or_64
+ // Predicate_atomic_load_xor_64
+ // Predicate_atomic_load_max_64
+ // Predicate_atomic_load_min_64
+ // Predicate_atomic_load_umax_64
+ // Predicate_atomic_load_umin_64
+ // Predicate_atomic_load_nand_64
+ // Predicate_atomic_cmp_swap_64
+ // Predicate_atomic_load_sub_64
+ SDNode *N = Node;
+ (void)N;
+if (cast<MemSDNode>(N)->getMemoryVT() != MVT::i64) return false;
+return true;
+
+ }
+ case 15: {
+ // Predicate_uimm5
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isUInt<5>(Imm);
+ }
+ case 16: {
+ // Predicate_immbottomxlenset
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+
+ if (Subtarget->is64Bit())
+ return countTrailingOnes<uint64_t>(Imm) >= 6;
+ return countTrailingOnes<uint64_t>(Imm) >= 5;
+
+ }
+ case 17: {
+ // Predicate_uimmlog2xlen
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+
+ if (Subtarget->is64Bit())
+ return isUInt<6>(Imm);
+ return isUInt<5>(Imm);
+
+ }
+ case 18: {
+ // Predicate_simm32hi20
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isShiftedInt<20, 12>(Imm);
+ }
+ case 19: {
+ // Predicate_simm32
+ int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
+return isInt<32>(Imm);
+ }
+ case 20: {
+ // Predicate_atomic_swap_32_monotonic
+ // Predicate_atomic_swap_64_monotonic
+ // Predicate_atomic_load_add_32_monotonic
+ // Predicate_atomic_load_add_64_monotonic
+ // Predicate_atomic_load_and_32_monotonic
+ // Predicate_atomic_load_and_64_monotonic
+ // Predicate_atomic_load_or_32_monotonic
+ // Predicate_atomic_load_or_64_monotonic
+ // Predicate_atomic_load_xor_32_monotonic
+ // Predicate_atomic_load_xor_64_monotonic
+ // Predicate_atomic_load_max_32_monotonic
+ // Predicate_atomic_load_max_64_monotonic
+ // Predicate_atomic_load_min_32_monotonic
+ // Predicate_atomic_load_min_64_monotonic
+ // Predicate_atomic_load_umax_32_monotonic
+ // Predicate_atomic_load_umax_64_monotonic
+ // Predicate_atomic_load_umin_32_monotonic
+ // Predicate_atomic_load_umin_64_monotonic
+ // Predicate_atomic_load_nand_32_monotonic
+ // Predicate_atomic_load_nand_64_monotonic
+ // Predicate_atomic_cmp_swap_32_monotonic
+ // Predicate_atomic_cmp_swap_64_monotonic
+ // Predicate_atomic_load_sub_32_monotonic
+ // Predicate_atomic_load_sub_64_monotonic
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getOrdering() != AtomicOrdering::Monotonic) return false;
+return true;
+
+ }
+ case 21: {
+ // Predicate_atomic_swap_32_acquire
+ // Predicate_atomic_swap_64_acquire
+ // Predicate_atomic_load_add_32_acquire
+ // Predicate_atomic_load_add_64_acquire
+ // Predicate_atomic_load_and_32_acquire
+ // Predicate_atomic_load_and_64_acquire
+ // Predicate_atomic_load_or_32_acquire
+ // Predicate_atomic_load_or_64_acquire
+ // Predicate_atomic_load_xor_32_acquire
+ // Predicate_atomic_load_xor_64_acquire
+ // Predicate_atomic_load_max_32_acquire
+ // Predicate_atomic_load_max_64_acquire
+ // Predicate_atomic_load_min_32_acquire
+ // Predicate_atomic_load_min_64_acquire
+ // Predicate_atomic_load_umax_32_acquire
+ // Predicate_atomic_load_umax_64_acquire
+ // Predicate_atomic_load_umin_32_acquire
+ // Predicate_atomic_load_umin_64_acquire
+ // Predicate_atomic_load_nand_32_acquire
+ // Predicate_atomic_load_nand_64_acquire
+ // Predicate_atomic_cmp_swap_32_acquire
+ // Predicate_atomic_cmp_swap_64_acquire
+ // Predicate_atomic_load_sub_32_acquire
+ // Predicate_atomic_load_sub_64_acquire
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getOrdering() != AtomicOrdering::Acquire) return false;
+return true;
+
+ }
+ case 22: {
+ // Predicate_atomic_swap_32_release
+ // Predicate_atomic_swap_64_release
+ // Predicate_atomic_load_add_32_release
+ // Predicate_atomic_load_add_64_release
+ // Predicate_atomic_load_and_32_release
+ // Predicate_atomic_load_and_64_release
+ // Predicate_atomic_load_or_32_release
+ // Predicate_atomic_load_or_64_release
+ // Predicate_atomic_load_xor_32_release
+ // Predicate_atomic_load_xor_64_release
+ // Predicate_atomic_load_max_32_release
+ // Predicate_atomic_load_max_64_release
+ // Predicate_atomic_load_min_32_release
+ // Predicate_atomic_load_min_64_release
+ // Predicate_atomic_load_umax_32_release
+ // Predicate_atomic_load_umax_64_release
+ // Predicate_atomic_load_umin_32_release
+ // Predicate_atomic_load_umin_64_release
+ // Predicate_atomic_load_nand_32_release
+ // Predicate_atomic_load_nand_64_release
+ // Predicate_atomic_cmp_swap_32_release
+ // Predicate_atomic_cmp_swap_64_release
+ // Predicate_atomic_load_sub_32_release
+ // Predicate_atomic_load_sub_64_release
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getOrdering() != AtomicOrdering::Release) return false;
+return true;
+
+ }
+ case 23: {
+ // Predicate_atomic_swap_32_acq_rel
+ // Predicate_atomic_swap_64_acq_rel
+ // Predicate_atomic_load_add_32_acq_rel
+ // Predicate_atomic_load_add_64_acq_rel
+ // Predicate_atomic_load_and_32_acq_rel
+ // Predicate_atomic_load_and_64_acq_rel
+ // Predicate_atomic_load_or_32_acq_rel
+ // Predicate_atomic_load_or_64_acq_rel
+ // Predicate_atomic_load_xor_32_acq_rel
+ // Predicate_atomic_load_xor_64_acq_rel
+ // Predicate_atomic_load_max_32_acq_rel
+ // Predicate_atomic_load_max_64_acq_rel
+ // Predicate_atomic_load_min_32_acq_rel
+ // Predicate_atomic_load_min_64_acq_rel
+ // Predicate_atomic_load_umax_32_acq_rel
+ // Predicate_atomic_load_umax_64_acq_rel
+ // Predicate_atomic_load_umin_32_acq_rel
+ // Predicate_atomic_load_umin_64_acq_rel
+ // Predicate_atomic_load_nand_32_acq_rel
+ // Predicate_atomic_load_nand_64_acq_rel
+ // Predicate_atomic_cmp_swap_32_acq_rel
+ // Predicate_atomic_cmp_swap_64_acq_rel
+ // Predicate_atomic_load_sub_32_acq_rel
+ // Predicate_atomic_load_sub_64_acq_rel
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getOrdering() != AtomicOrdering::AcquireRelease) return false;
+return true;
+
+ }
+ case 24: {
+ // Predicate_atomic_swap_32_seq_cst
+ // Predicate_atomic_swap_64_seq_cst
+ // Predicate_atomic_load_add_32_seq_cst
+ // Predicate_atomic_load_add_64_seq_cst
+ // Predicate_atomic_load_and_32_seq_cst
+ // Predicate_atomic_load_and_64_seq_cst
+ // Predicate_atomic_load_or_32_seq_cst
+ // Predicate_atomic_load_or_64_seq_cst
+ // Predicate_atomic_load_xor_32_seq_cst
+ // Predicate_atomic_load_xor_64_seq_cst
+ // Predicate_atomic_load_max_32_seq_cst
+ // Predicate_atomic_load_max_64_seq_cst
+ // Predicate_atomic_load_min_32_seq_cst
+ // Predicate_atomic_load_min_64_seq_cst
+ // Predicate_atomic_load_umax_32_seq_cst
+ // Predicate_atomic_load_umax_64_seq_cst
+ // Predicate_atomic_load_umin_32_seq_cst
+ // Predicate_atomic_load_umin_64_seq_cst
+ // Predicate_atomic_load_nand_32_seq_cst
+ // Predicate_atomic_load_nand_64_seq_cst
+ // Predicate_atomic_cmp_swap_32_seq_cst
+ // Predicate_atomic_cmp_swap_64_seq_cst
+ // Predicate_atomic_load_sub_32_seq_cst
+ // Predicate_atomic_load_sub_64_seq_cst
+ SDNode *N = Node;
+ (void)N;
+if (cast<AtomicSDNode>(N)->getOrdering() != AtomicOrdering::SequentiallyConsistent) return false;
+return true;
+
+ }
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+bool CheckComplexPattern(SDNode *Root, SDNode *Parent,
+ SDValue N, unsigned PatternNo,
+ SmallVectorImpl<std::pair<SDValue, SDNode*>> &Result) override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+bool DAGISEL_CLASS_COLONCOLON CheckComplexPattern(SDNode *Root, SDNode *Parent,
+ SDValue N, unsigned PatternNo,
+ SmallVectorImpl<std::pair<SDValue, SDNode*>> &Result)
+#if DAGISEL_INLINE
+ override
+#endif
+ {
+ unsigned NextRes = Result.size();
+ switch (PatternNo) {
+ default: llvm_unreachable("Invalid pattern # in table?");
+ case 0:
+ Result.resize(NextRes+1);
+ return SelectAddrFI(N, Result[NextRes+0].first);
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+#ifdef GET_DAGISEL_DECL
+SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) override;
+#endif
+#if defined(GET_DAGISEL_BODY) || DAGISEL_INLINE
+SDValue DAGISEL_CLASS_COLONCOLON RunSDNodeXForm(SDValue V, unsigned XFormNo)
+#if DAGISEL_INLINE
+ override
+#endif
+ {
+ switch (XFormNo) {
+ default: llvm_unreachable("Invalid xform # in table?");
+ case 0: { // HI20
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return CurDAG->getTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff,
+ SDLoc(N), N->getValueType(0));
+
+ }
+ case 1: { // LO12Sext
+ ConstantSDNode *N = cast<ConstantSDNode>(V.getNode());
+
+ return CurDAG->getTargetConstant(SignExtend64<12>(N->getZExtValue()),
+ SDLoc(N), N->getValueType(0));
+
+ }
+ }
+}
+#endif // GET_DAGISEL_BODY
+
+
+#ifdef DAGISEL_INLINE
+#undef DAGISEL_INLINE
+#endif
+#ifdef DAGISEL_CLASS_COLONCOLON
+#undef DAGISEL_CLASS_COLONCOLON
+#endif
+#ifdef GET_DAGISEL_DECL
+#undef GET_DAGISEL_DECL
+#endif
+#ifdef GET_DAGISEL_BODY
+#undef GET_DAGISEL_BODY
+#endif
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenDisassemblerTables.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenDisassemblerTables.inc
new file mode 100644
index 0000000..d2d5b2a
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenDisassemblerTables.inc
@@ -0,0 +1,1898 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* * RISCV Disassembler *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#include "llvm/MC/MCInst.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/DataTypes.h"
+#include "llvm/Support/LEB128.h"
+#include "llvm/Support/raw_ostream.h"
+#include <assert.h>
+
+namespace llvm {
+
+// Helper functions for extracting fields from encoded instructions.
+// InsnType must either be integral or an APInt-like object that must:
+// * Have a static const max_size_in_bits equal to the number of bits in the
+// encoding.
+// * be default-constructible and copy-constructible
+// * be constructible from a uint64_t
+// * be constructible from an APInt (this can be private)
+// * Support getBitsSet(loBit, hiBit)
+// * be convertible to uint64_t
+// * Support the ~, &, ==, !=, and |= operators with other objects of the same type
+// * Support shift (<<, >>) with signed and unsigned integers on the RHS
+// * Support put (<<) to raw_ostream&
+template<typename InsnType>
+#if defined(_MSC_VER) && !defined(__clang__)
+__declspec(noinline)
+#endif
+static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
+ unsigned numBits, std::true_type) {
+ assert(startBit + numBits <= 64 && "Cannot support >64-bit extractions!");
+ assert(startBit + numBits <= (sizeof(InsnType) * 8) &&
+ "Instruction field out of bounds!");
+ InsnType fieldMask;
+ if (numBits == sizeof(InsnType) * 8)
+ fieldMask = (InsnType)(-1LL);
+ else
+ fieldMask = (((InsnType)1 << numBits) - 1) << startBit;
+ return (insn & fieldMask) >> startBit;
+}
+
+template<typename InsnType>
+static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
+ unsigned numBits, std::false_type) {
+ assert(startBit + numBits <= InsnType::max_size_in_bits && "Instruction field out of bounds!");
+ InsnType fieldMask = InsnType::getBitsSet(0, numBits);
+ return (insn >> startBit) & fieldMask;
+}
+
+template<typename InsnType>
+static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,
+ unsigned numBits) {
+ return fieldFromInstruction(insn, startBit, numBits, std::is_integral<InsnType>());
+}
+
+static const uint8_t DecoderTable16[] = {
+/* 0 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 132, 0, 0, // Skip to: 140
+/* 8 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 25, 0, 0, // Skip to: 41
+/* 16 */ MCD::OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 32
+/* 21 */ MCD::OPC_CheckField, 2, 11, 0, 4, 0, 0, // Skip to: 32
+/* 28 */ MCD::OPC_Decode, 243, 2, 0, // Opcode: C_UNIMP
+/* 32 */ MCD::OPC_CheckPredicate, 0, 24, 3, 0, // Skip to: 829
+/* 37 */ MCD::OPC_Decode, 193, 2, 1, // Opcode: C_ADDI4SPN
+/* 41 */ MCD::OPC_FilterValue, 1, 41, 0, 0, // Skip to: 87
+/* 46 */ MCD::OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 62
+/* 51 */ MCD::OPC_CheckField, 2, 11, 0, 4, 0, 0, // Skip to: 62
+/* 58 */ MCD::OPC_Decode, 227, 2, 0, // Opcode: C_NOP
+/* 62 */ MCD::OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 78
+/* 67 */ MCD::OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 78
+/* 74 */ MCD::OPC_Decode, 228, 2, 2, // Opcode: C_NOP_HINT
+/* 78 */ MCD::OPC_CheckPredicate, 0, 234, 2, 0, // Skip to: 829
+/* 83 */ MCD::OPC_Decode, 191, 2, 3, // Opcode: C_ADDI
+/* 87 */ MCD::OPC_FilterValue, 2, 225, 2, 0, // Skip to: 829
+/* 92 */ MCD::OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 115
+/* 97 */ MCD::OPC_CheckField, 12, 1, 0, 11, 0, 0, // Skip to: 115
+/* 104 */ MCD::OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 115
+/* 111 */ MCD::OPC_Decode, 233, 2, 4, // Opcode: C_SLLI64_HINT
+/* 115 */ MCD::OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 131
+/* 120 */ MCD::OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 131
+/* 127 */ MCD::OPC_Decode, 234, 2, 5, // Opcode: C_SLLI_HINT
+/* 131 */ MCD::OPC_CheckPredicate, 0, 181, 2, 0, // Skip to: 829
+/* 136 */ MCD::OPC_Decode, 232, 2, 6, // Opcode: C_SLLI
+/* 140 */ MCD::OPC_FilterValue, 1, 45, 0, 0, // Skip to: 190
+/* 145 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 148 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 162
+/* 153 */ MCD::OPC_CheckPredicate, 2, 159, 2, 0, // Skip to: 829
+/* 158 */ MCD::OPC_Decode, 205, 2, 7, // Opcode: C_FLD
+/* 162 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 176
+/* 167 */ MCD::OPC_CheckPredicate, 3, 145, 2, 0, // Skip to: 829
+/* 172 */ MCD::OPC_Decode, 194, 2, 3, // Opcode: C_ADDIW
+/* 176 */ MCD::OPC_FilterValue, 2, 136, 2, 0, // Skip to: 829
+/* 181 */ MCD::OPC_CheckPredicate, 2, 131, 2, 0, // Skip to: 829
+/* 186 */ MCD::OPC_Decode, 206, 2, 8, // Opcode: C_FLDSP
+/* 190 */ MCD::OPC_FilterValue, 2, 61, 0, 0, // Skip to: 256
+/* 195 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 198 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 212
+/* 203 */ MCD::OPC_CheckPredicate, 0, 109, 2, 0, // Skip to: 829
+/* 208 */ MCD::OPC_Decode, 223, 2, 9, // Opcode: C_LW
+/* 212 */ MCD::OPC_FilterValue, 1, 25, 0, 0, // Skip to: 242
+/* 217 */ MCD::OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 233
+/* 222 */ MCD::OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 233
+/* 229 */ MCD::OPC_Decode, 220, 2, 10, // Opcode: C_LI_HINT
+/* 233 */ MCD::OPC_CheckPredicate, 0, 79, 2, 0, // Skip to: 829
+/* 238 */ MCD::OPC_Decode, 219, 2, 11, // Opcode: C_LI
+/* 242 */ MCD::OPC_FilterValue, 2, 70, 2, 0, // Skip to: 829
+/* 247 */ MCD::OPC_CheckPredicate, 0, 65, 2, 0, // Skip to: 829
+/* 252 */ MCD::OPC_Decode, 224, 2, 12, // Opcode: C_LWSP
+/* 256 */ MCD::OPC_FilterValue, 3, 76, 0, 0, // Skip to: 337
+/* 261 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 264 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 278
+/* 269 */ MCD::OPC_CheckPredicate, 3, 43, 2, 0, // Skip to: 829
+/* 274 */ MCD::OPC_Decode, 217, 2, 13, // Opcode: C_LD
+/* 278 */ MCD::OPC_FilterValue, 1, 40, 0, 0, // Skip to: 323
+/* 283 */ MCD::OPC_ExtractField, 7, 5, // Inst{11-7} ...
+/* 286 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 300
+/* 291 */ MCD::OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 314
+/* 296 */ MCD::OPC_Decode, 222, 2, 10, // Opcode: C_LUI_HINT
+/* 300 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 314
+/* 305 */ MCD::OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 314
+/* 310 */ MCD::OPC_Decode, 192, 2, 14, // Opcode: C_ADDI16SP
+/* 314 */ MCD::OPC_CheckPredicate, 0, 254, 1, 0, // Skip to: 829
+/* 319 */ MCD::OPC_Decode, 221, 2, 15, // Opcode: C_LUI
+/* 323 */ MCD::OPC_FilterValue, 2, 245, 1, 0, // Skip to: 829
+/* 328 */ MCD::OPC_CheckPredicate, 3, 240, 1, 0, // Skip to: 829
+/* 333 */ MCD::OPC_Decode, 218, 2, 16, // Opcode: C_LDSP
+/* 337 */ MCD::OPC_FilterValue, 4, 81, 1, 0, // Skip to: 679
+/* 342 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 345 */ MCD::OPC_FilterValue, 1, 213, 0, 0, // Skip to: 563
+/* 350 */ MCD::OPC_ExtractField, 10, 2, // Inst{11-10} ...
+/* 353 */ MCD::OPC_FilterValue, 0, 32, 0, 0, // Skip to: 390
+/* 358 */ MCD::OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 381
+/* 363 */ MCD::OPC_CheckField, 12, 1, 0, 11, 0, 0, // Skip to: 381
+/* 370 */ MCD::OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 381
+/* 377 */ MCD::OPC_Decode, 238, 2, 17, // Opcode: C_SRLI64_HINT
+/* 381 */ MCD::OPC_CheckPredicate, 0, 187, 1, 0, // Skip to: 829
+/* 386 */ MCD::OPC_Decode, 237, 2, 18, // Opcode: C_SRLI
+/* 390 */ MCD::OPC_FilterValue, 1, 32, 0, 0, // Skip to: 427
+/* 395 */ MCD::OPC_CheckPredicate, 1, 18, 0, 0, // Skip to: 418
+/* 400 */ MCD::OPC_CheckField, 12, 1, 0, 11, 0, 0, // Skip to: 418
+/* 407 */ MCD::OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 418
+/* 414 */ MCD::OPC_Decode, 236, 2, 17, // Opcode: C_SRAI64_HINT
+/* 418 */ MCD::OPC_CheckPredicate, 0, 150, 1, 0, // Skip to: 829
+/* 423 */ MCD::OPC_Decode, 235, 2, 18, // Opcode: C_SRAI
+/* 427 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 441
+/* 432 */ MCD::OPC_CheckPredicate, 0, 136, 1, 0, // Skip to: 829
+/* 437 */ MCD::OPC_Decode, 201, 2, 19, // Opcode: C_ANDI
+/* 441 */ MCD::OPC_FilterValue, 3, 127, 1, 0, // Skip to: 829
+/* 446 */ MCD::OPC_ExtractField, 5, 2, // Inst{6-5} ...
+/* 449 */ MCD::OPC_FilterValue, 0, 31, 0, 0, // Skip to: 485
+/* 454 */ MCD::OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 457 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 471
+/* 462 */ MCD::OPC_CheckPredicate, 0, 106, 1, 0, // Skip to: 829
+/* 467 */ MCD::OPC_Decode, 239, 2, 20, // Opcode: C_SUB
+/* 471 */ MCD::OPC_FilterValue, 1, 97, 1, 0, // Skip to: 829
+/* 476 */ MCD::OPC_CheckPredicate, 3, 92, 1, 0, // Skip to: 829
+/* 481 */ MCD::OPC_Decode, 240, 2, 20, // Opcode: C_SUBW
+/* 485 */ MCD::OPC_FilterValue, 1, 31, 0, 0, // Skip to: 521
+/* 490 */ MCD::OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 493 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 507
+/* 498 */ MCD::OPC_CheckPredicate, 0, 70, 1, 0, // Skip to: 829
+/* 503 */ MCD::OPC_Decode, 244, 2, 20, // Opcode: C_XOR
+/* 507 */ MCD::OPC_FilterValue, 1, 61, 1, 0, // Skip to: 829
+/* 512 */ MCD::OPC_CheckPredicate, 3, 56, 1, 0, // Skip to: 829
+/* 517 */ MCD::OPC_Decode, 198, 2, 20, // Opcode: C_ADDW
+/* 521 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 542
+/* 526 */ MCD::OPC_CheckPredicate, 0, 42, 1, 0, // Skip to: 829
+/* 531 */ MCD::OPC_CheckField, 12, 1, 0, 35, 1, 0, // Skip to: 829
+/* 538 */ MCD::OPC_Decode, 229, 2, 20, // Opcode: C_OR
+/* 542 */ MCD::OPC_FilterValue, 3, 26, 1, 0, // Skip to: 829
+/* 547 */ MCD::OPC_CheckPredicate, 0, 21, 1, 0, // Skip to: 829
+/* 552 */ MCD::OPC_CheckField, 12, 1, 0, 14, 1, 0, // Skip to: 829
+/* 559 */ MCD::OPC_Decode, 200, 2, 20, // Opcode: C_AND
+/* 563 */ MCD::OPC_FilterValue, 2, 5, 1, 0, // Skip to: 829
+/* 568 */ MCD::OPC_ExtractField, 12, 1, // Inst{12} ...
+/* 571 */ MCD::OPC_FilterValue, 0, 41, 0, 0, // Skip to: 617
+/* 576 */ MCD::OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 592
+/* 581 */ MCD::OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 592
+/* 588 */ MCD::OPC_Decode, 216, 2, 21, // Opcode: C_JR
+/* 592 */ MCD::OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 608
+/* 597 */ MCD::OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 608
+/* 604 */ MCD::OPC_Decode, 226, 2, 22, // Opcode: C_MV_HINT
+/* 608 */ MCD::OPC_CheckPredicate, 0, 216, 0, 0, // Skip to: 829
+/* 613 */ MCD::OPC_Decode, 225, 2, 23, // Opcode: C_MV
+/* 617 */ MCD::OPC_FilterValue, 1, 207, 0, 0, // Skip to: 829
+/* 622 */ MCD::OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 638
+/* 627 */ MCD::OPC_CheckField, 2, 10, 0, 4, 0, 0, // Skip to: 638
+/* 634 */ MCD::OPC_Decode, 204, 2, 0, // Opcode: C_EBREAK
+/* 638 */ MCD::OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 654
+/* 643 */ MCD::OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 654
+/* 650 */ MCD::OPC_Decode, 199, 2, 24, // Opcode: C_ADD_HINT
+/* 654 */ MCD::OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 670
+/* 659 */ MCD::OPC_CheckField, 2, 5, 0, 4, 0, 0, // Skip to: 670
+/* 666 */ MCD::OPC_Decode, 215, 2, 21, // Opcode: C_JALR
+/* 670 */ MCD::OPC_CheckPredicate, 0, 154, 0, 0, // Skip to: 829
+/* 675 */ MCD::OPC_Decode, 190, 2, 25, // Opcode: C_ADD
+/* 679 */ MCD::OPC_FilterValue, 5, 45, 0, 0, // Skip to: 729
+/* 684 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 687 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 701
+/* 692 */ MCD::OPC_CheckPredicate, 2, 132, 0, 0, // Skip to: 829
+/* 697 */ MCD::OPC_Decode, 209, 2, 7, // Opcode: C_FSD
+/* 701 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 715
+/* 706 */ MCD::OPC_CheckPredicate, 0, 118, 0, 0, // Skip to: 829
+/* 711 */ MCD::OPC_Decode, 213, 2, 26, // Opcode: C_J
+/* 715 */ MCD::OPC_FilterValue, 2, 109, 0, 0, // Skip to: 829
+/* 720 */ MCD::OPC_CheckPredicate, 2, 104, 0, 0, // Skip to: 829
+/* 725 */ MCD::OPC_Decode, 210, 2, 27, // Opcode: C_FSDSP
+/* 729 */ MCD::OPC_FilterValue, 6, 45, 0, 0, // Skip to: 779
+/* 734 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 737 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 751
+/* 742 */ MCD::OPC_CheckPredicate, 0, 82, 0, 0, // Skip to: 829
+/* 747 */ MCD::OPC_Decode, 241, 2, 9, // Opcode: C_SW
+/* 751 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 765
+/* 756 */ MCD::OPC_CheckPredicate, 0, 68, 0, 0, // Skip to: 829
+/* 761 */ MCD::OPC_Decode, 202, 2, 28, // Opcode: C_BEQZ
+/* 765 */ MCD::OPC_FilterValue, 2, 59, 0, 0, // Skip to: 829
+/* 770 */ MCD::OPC_CheckPredicate, 0, 54, 0, 0, // Skip to: 829
+/* 775 */ MCD::OPC_Decode, 242, 2, 29, // Opcode: C_SWSP
+/* 779 */ MCD::OPC_FilterValue, 7, 45, 0, 0, // Skip to: 829
+/* 784 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 787 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 801
+/* 792 */ MCD::OPC_CheckPredicate, 3, 32, 0, 0, // Skip to: 829
+/* 797 */ MCD::OPC_Decode, 230, 2, 13, // Opcode: C_SD
+/* 801 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 815
+/* 806 */ MCD::OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 829
+/* 811 */ MCD::OPC_Decode, 203, 2, 28, // Opcode: C_BNEZ
+/* 815 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 829
+/* 820 */ MCD::OPC_CheckPredicate, 3, 4, 0, 0, // Skip to: 829
+/* 825 */ MCD::OPC_Decode, 231, 2, 30, // Opcode: C_SDSP
+/* 829 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTable32[] = {
+/* 0 */ MCD::OPC_ExtractField, 0, 7, // Inst{6-0} ...
+/* 3 */ MCD::OPC_FilterValue, 3, 76, 0, 0, // Skip to: 84
+/* 8 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 11 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 20
+/* 16 */ MCD::OPC_Decode, 190, 3, 31, // Opcode: LB
+/* 20 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 29
+/* 25 */ MCD::OPC_Decode, 193, 3, 31, // Opcode: LH
+/* 29 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 38
+/* 34 */ MCD::OPC_Decode, 204, 3, 31, // Opcode: LW
+/* 38 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 52
+/* 43 */ MCD::OPC_CheckPredicate, 4, 55, 15, 0, // Skip to: 3943
+/* 48 */ MCD::OPC_Decode, 192, 3, 31, // Opcode: LD
+/* 52 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 61
+/* 57 */ MCD::OPC_Decode, 191, 3, 31, // Opcode: LBU
+/* 61 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 70
+/* 66 */ MCD::OPC_Decode, 194, 3, 31, // Opcode: LHU
+/* 70 */ MCD::OPC_FilterValue, 6, 28, 15, 0, // Skip to: 3943
+/* 75 */ MCD::OPC_CheckPredicate, 4, 23, 15, 0, // Skip to: 3943
+/* 80 */ MCD::OPC_Decode, 205, 3, 31, // Opcode: LWU
+/* 84 */ MCD::OPC_FilterValue, 7, 31, 0, 0, // Skip to: 120
+/* 89 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 92 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 106
+/* 97 */ MCD::OPC_CheckPredicate, 5, 1, 15, 0, // Skip to: 3943
+/* 102 */ MCD::OPC_Decode, 157, 3, 32, // Opcode: FLW
+/* 106 */ MCD::OPC_FilterValue, 3, 248, 14, 0, // Skip to: 3943
+/* 111 */ MCD::OPC_CheckPredicate, 6, 243, 14, 0, // Skip to: 3943
+/* 116 */ MCD::OPC_Decode, 152, 3, 33, // Opcode: FLD
+/* 120 */ MCD::OPC_FilterValue, 15, 52, 0, 0, // Skip to: 177
+/* 125 */ MCD::OPC_ExtractField, 7, 13, // Inst{19-7} ...
+/* 128 */ MCD::OPC_FilterValue, 0, 28, 0, 0, // Skip to: 161
+/* 133 */ MCD::OPC_ExtractField, 28, 4, // Inst{31-28} ...
+/* 136 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 145
+/* 141 */ MCD::OPC_Decode, 147, 3, 34, // Opcode: FENCE
+/* 145 */ MCD::OPC_FilterValue, 8, 209, 14, 0, // Skip to: 3943
+/* 150 */ MCD::OPC_CheckField, 20, 8, 51, 202, 14, 0, // Skip to: 3943
+/* 157 */ MCD::OPC_Decode, 149, 3, 0, // Opcode: FENCE_TSO
+/* 161 */ MCD::OPC_FilterValue, 32, 193, 14, 0, // Skip to: 3943
+/* 166 */ MCD::OPC_CheckField, 20, 12, 0, 186, 14, 0, // Skip to: 3943
+/* 173 */ MCD::OPC_Decode, 148, 3, 0, // Opcode: FENCE_I
+/* 177 */ MCD::OPC_FilterValue, 19, 99, 0, 0, // Skip to: 281
+/* 182 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 185 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 194
+/* 190 */ MCD::OPC_Decode, 228, 1, 31, // Opcode: ADDI
+/* 194 */ MCD::OPC_FilterValue, 1, 11, 0, 0, // Skip to: 210
+/* 199 */ MCD::OPC_CheckField, 26, 6, 0, 153, 14, 0, // Skip to: 3943
+/* 206 */ MCD::OPC_Decode, 231, 3, 35, // Opcode: SLLI
+/* 210 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 219
+/* 215 */ MCD::OPC_Decode, 235, 3, 31, // Opcode: SLTI
+/* 219 */ MCD::OPC_FilterValue, 3, 4, 0, 0, // Skip to: 228
+/* 224 */ MCD::OPC_Decode, 236, 3, 31, // Opcode: SLTIU
+/* 228 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 237
+/* 233 */ MCD::OPC_Decode, 254, 3, 31, // Opcode: XORI
+/* 237 */ MCD::OPC_FilterValue, 5, 21, 0, 0, // Skip to: 263
+/* 242 */ MCD::OPC_ExtractField, 26, 6, // Inst{31-26} ...
+/* 245 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 254
+/* 250 */ MCD::OPC_Decode, 244, 3, 35, // Opcode: SRLI
+/* 254 */ MCD::OPC_FilterValue, 16, 100, 14, 0, // Skip to: 3943
+/* 259 */ MCD::OPC_Decode, 239, 3, 35, // Opcode: SRAI
+/* 263 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 272
+/* 268 */ MCD::OPC_Decode, 213, 3, 31, // Opcode: ORI
+/* 272 */ MCD::OPC_FilterValue, 7, 82, 14, 0, // Skip to: 3943
+/* 277 */ MCD::OPC_Decode, 176, 2, 31, // Opcode: ANDI
+/* 281 */ MCD::OPC_FilterValue, 23, 4, 0, 0, // Skip to: 290
+/* 286 */ MCD::OPC_Decode, 177, 2, 36, // Opcode: AUIPC
+/* 290 */ MCD::OPC_FilterValue, 27, 74, 0, 0, // Skip to: 369
+/* 295 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 298 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 312
+/* 303 */ MCD::OPC_CheckPredicate, 4, 51, 14, 0, // Skip to: 3943
+/* 308 */ MCD::OPC_Decode, 229, 1, 31, // Opcode: ADDIW
+/* 312 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 333
+/* 317 */ MCD::OPC_CheckPredicate, 4, 37, 14, 0, // Skip to: 3943
+/* 322 */ MCD::OPC_CheckField, 25, 7, 0, 30, 14, 0, // Skip to: 3943
+/* 329 */ MCD::OPC_Decode, 232, 3, 37, // Opcode: SLLIW
+/* 333 */ MCD::OPC_FilterValue, 5, 21, 14, 0, // Skip to: 3943
+/* 338 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 341 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 355
+/* 346 */ MCD::OPC_CheckPredicate, 4, 8, 14, 0, // Skip to: 3943
+/* 351 */ MCD::OPC_Decode, 245, 3, 37, // Opcode: SRLIW
+/* 355 */ MCD::OPC_FilterValue, 32, 255, 13, 0, // Skip to: 3943
+/* 360 */ MCD::OPC_CheckPredicate, 4, 250, 13, 0, // Skip to: 3943
+/* 365 */ MCD::OPC_Decode, 240, 3, 37, // Opcode: SRAIW
+/* 369 */ MCD::OPC_FilterValue, 35, 44, 0, 0, // Skip to: 418
+/* 374 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 377 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 386
+/* 382 */ MCD::OPC_Decode, 218, 3, 38, // Opcode: SB
+/* 386 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 395
+/* 391 */ MCD::OPC_Decode, 229, 3, 38, // Opcode: SH
+/* 395 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 404
+/* 400 */ MCD::OPC_Decode, 249, 3, 38, // Opcode: SW
+/* 404 */ MCD::OPC_FilterValue, 3, 206, 13, 0, // Skip to: 3943
+/* 409 */ MCD::OPC_CheckPredicate, 4, 201, 13, 0, // Skip to: 3943
+/* 414 */ MCD::OPC_Decode, 227, 3, 38, // Opcode: SD
+/* 418 */ MCD::OPC_FilterValue, 39, 31, 0, 0, // Skip to: 454
+/* 423 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 426 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 440
+/* 431 */ MCD::OPC_CheckPredicate, 5, 179, 13, 0, // Skip to: 3943
+/* 436 */ MCD::OPC_Decode, 187, 3, 39, // Opcode: FSW
+/* 440 */ MCD::OPC_FilterValue, 3, 170, 13, 0, // Skip to: 3943
+/* 445 */ MCD::OPC_CheckPredicate, 6, 165, 13, 0, // Skip to: 3943
+/* 450 */ MCD::OPC_Decode, 176, 3, 40, // Opcode: FSD
+/* 454 */ MCD::OPC_FilterValue, 47, 107, 6, 0, // Skip to: 2102
+/* 459 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 462 */ MCD::OPC_FilterValue, 0, 31, 0, 0, // Skip to: 498
+/* 467 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 470 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 484
+/* 475 */ MCD::OPC_CheckPredicate, 7, 135, 13, 0, // Skip to: 3943
+/* 480 */ MCD::OPC_Decode, 235, 1, 41, // Opcode: AMOADD_W
+/* 484 */ MCD::OPC_FilterValue, 3, 126, 13, 0, // Skip to: 3943
+/* 489 */ MCD::OPC_CheckPredicate, 8, 121, 13, 0, // Skip to: 3943
+/* 494 */ MCD::OPC_Decode, 231, 1, 41, // Opcode: AMOADD_D
+/* 498 */ MCD::OPC_FilterValue, 1, 31, 0, 0, // Skip to: 534
+/* 503 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 506 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 520
+/* 511 */ MCD::OPC_CheckPredicate, 7, 99, 13, 0, // Skip to: 3943
+/* 516 */ MCD::OPC_Decode, 238, 1, 41, // Opcode: AMOADD_W_RL
+/* 520 */ MCD::OPC_FilterValue, 3, 90, 13, 0, // Skip to: 3943
+/* 525 */ MCD::OPC_CheckPredicate, 8, 85, 13, 0, // Skip to: 3943
+/* 530 */ MCD::OPC_Decode, 234, 1, 41, // Opcode: AMOADD_D_RL
+/* 534 */ MCD::OPC_FilterValue, 2, 31, 0, 0, // Skip to: 570
+/* 539 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 542 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 556
+/* 547 */ MCD::OPC_CheckPredicate, 7, 63, 13, 0, // Skip to: 3943
+/* 552 */ MCD::OPC_Decode, 236, 1, 41, // Opcode: AMOADD_W_AQ
+/* 556 */ MCD::OPC_FilterValue, 3, 54, 13, 0, // Skip to: 3943
+/* 561 */ MCD::OPC_CheckPredicate, 8, 49, 13, 0, // Skip to: 3943
+/* 566 */ MCD::OPC_Decode, 232, 1, 41, // Opcode: AMOADD_D_AQ
+/* 570 */ MCD::OPC_FilterValue, 3, 31, 0, 0, // Skip to: 606
+/* 575 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 578 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 592
+/* 583 */ MCD::OPC_CheckPredicate, 7, 27, 13, 0, // Skip to: 3943
+/* 588 */ MCD::OPC_Decode, 237, 1, 41, // Opcode: AMOADD_W_AQ_RL
+/* 592 */ MCD::OPC_FilterValue, 3, 18, 13, 0, // Skip to: 3943
+/* 597 */ MCD::OPC_CheckPredicate, 8, 13, 13, 0, // Skip to: 3943
+/* 602 */ MCD::OPC_Decode, 233, 1, 41, // Opcode: AMOADD_D_AQ_RL
+/* 606 */ MCD::OPC_FilterValue, 4, 31, 0, 0, // Skip to: 642
+/* 611 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 614 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 628
+/* 619 */ MCD::OPC_CheckPredicate, 7, 247, 12, 0, // Skip to: 3943
+/* 624 */ MCD::OPC_Decode, 163, 2, 41, // Opcode: AMOSWAP_W
+/* 628 */ MCD::OPC_FilterValue, 3, 238, 12, 0, // Skip to: 3943
+/* 633 */ MCD::OPC_CheckPredicate, 8, 233, 12, 0, // Skip to: 3943
+/* 638 */ MCD::OPC_Decode, 159, 2, 41, // Opcode: AMOSWAP_D
+/* 642 */ MCD::OPC_FilterValue, 5, 31, 0, 0, // Skip to: 678
+/* 647 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 650 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 664
+/* 655 */ MCD::OPC_CheckPredicate, 7, 211, 12, 0, // Skip to: 3943
+/* 660 */ MCD::OPC_Decode, 166, 2, 41, // Opcode: AMOSWAP_W_RL
+/* 664 */ MCD::OPC_FilterValue, 3, 202, 12, 0, // Skip to: 3943
+/* 669 */ MCD::OPC_CheckPredicate, 8, 197, 12, 0, // Skip to: 3943
+/* 674 */ MCD::OPC_Decode, 162, 2, 41, // Opcode: AMOSWAP_D_RL
+/* 678 */ MCD::OPC_FilterValue, 6, 31, 0, 0, // Skip to: 714
+/* 683 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 686 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 700
+/* 691 */ MCD::OPC_CheckPredicate, 7, 175, 12, 0, // Skip to: 3943
+/* 696 */ MCD::OPC_Decode, 164, 2, 41, // Opcode: AMOSWAP_W_AQ
+/* 700 */ MCD::OPC_FilterValue, 3, 166, 12, 0, // Skip to: 3943
+/* 705 */ MCD::OPC_CheckPredicate, 8, 161, 12, 0, // Skip to: 3943
+/* 710 */ MCD::OPC_Decode, 160, 2, 41, // Opcode: AMOSWAP_D_AQ
+/* 714 */ MCD::OPC_FilterValue, 7, 31, 0, 0, // Skip to: 750
+/* 719 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 722 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 736
+/* 727 */ MCD::OPC_CheckPredicate, 7, 139, 12, 0, // Skip to: 3943
+/* 732 */ MCD::OPC_Decode, 165, 2, 41, // Opcode: AMOSWAP_W_AQ_RL
+/* 736 */ MCD::OPC_FilterValue, 3, 130, 12, 0, // Skip to: 3943
+/* 741 */ MCD::OPC_CheckPredicate, 8, 125, 12, 0, // Skip to: 3943
+/* 746 */ MCD::OPC_Decode, 161, 2, 41, // Opcode: AMOSWAP_D_AQ_RL
+/* 750 */ MCD::OPC_FilterValue, 8, 45, 0, 0, // Skip to: 800
+/* 755 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 758 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 779
+/* 763 */ MCD::OPC_CheckPredicate, 7, 103, 12, 0, // Skip to: 3943
+/* 768 */ MCD::OPC_CheckField, 20, 5, 0, 96, 12, 0, // Skip to: 3943
+/* 775 */ MCD::OPC_Decode, 199, 3, 42, // Opcode: LR_W
+/* 779 */ MCD::OPC_FilterValue, 3, 87, 12, 0, // Skip to: 3943
+/* 784 */ MCD::OPC_CheckPredicate, 8, 82, 12, 0, // Skip to: 3943
+/* 789 */ MCD::OPC_CheckField, 20, 5, 0, 75, 12, 0, // Skip to: 3943
+/* 796 */ MCD::OPC_Decode, 195, 3, 42, // Opcode: LR_D
+/* 800 */ MCD::OPC_FilterValue, 9, 45, 0, 0, // Skip to: 850
+/* 805 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 808 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 829
+/* 813 */ MCD::OPC_CheckPredicate, 7, 53, 12, 0, // Skip to: 3943
+/* 818 */ MCD::OPC_CheckField, 20, 5, 0, 46, 12, 0, // Skip to: 3943
+/* 825 */ MCD::OPC_Decode, 202, 3, 42, // Opcode: LR_W_RL
+/* 829 */ MCD::OPC_FilterValue, 3, 37, 12, 0, // Skip to: 3943
+/* 834 */ MCD::OPC_CheckPredicate, 8, 32, 12, 0, // Skip to: 3943
+/* 839 */ MCD::OPC_CheckField, 20, 5, 0, 25, 12, 0, // Skip to: 3943
+/* 846 */ MCD::OPC_Decode, 198, 3, 42, // Opcode: LR_D_RL
+/* 850 */ MCD::OPC_FilterValue, 10, 45, 0, 0, // Skip to: 900
+/* 855 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 858 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 879
+/* 863 */ MCD::OPC_CheckPredicate, 7, 3, 12, 0, // Skip to: 3943
+/* 868 */ MCD::OPC_CheckField, 20, 5, 0, 252, 11, 0, // Skip to: 3943
+/* 875 */ MCD::OPC_Decode, 200, 3, 42, // Opcode: LR_W_AQ
+/* 879 */ MCD::OPC_FilterValue, 3, 243, 11, 0, // Skip to: 3943
+/* 884 */ MCD::OPC_CheckPredicate, 8, 238, 11, 0, // Skip to: 3943
+/* 889 */ MCD::OPC_CheckField, 20, 5, 0, 231, 11, 0, // Skip to: 3943
+/* 896 */ MCD::OPC_Decode, 196, 3, 42, // Opcode: LR_D_AQ
+/* 900 */ MCD::OPC_FilterValue, 11, 45, 0, 0, // Skip to: 950
+/* 905 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 908 */ MCD::OPC_FilterValue, 2, 16, 0, 0, // Skip to: 929
+/* 913 */ MCD::OPC_CheckPredicate, 7, 209, 11, 0, // Skip to: 3943
+/* 918 */ MCD::OPC_CheckField, 20, 5, 0, 202, 11, 0, // Skip to: 3943
+/* 925 */ MCD::OPC_Decode, 201, 3, 42, // Opcode: LR_W_AQ_RL
+/* 929 */ MCD::OPC_FilterValue, 3, 193, 11, 0, // Skip to: 3943
+/* 934 */ MCD::OPC_CheckPredicate, 8, 188, 11, 0, // Skip to: 3943
+/* 939 */ MCD::OPC_CheckField, 20, 5, 0, 181, 11, 0, // Skip to: 3943
+/* 946 */ MCD::OPC_Decode, 197, 3, 42, // Opcode: LR_D_AQ_RL
+/* 950 */ MCD::OPC_FilterValue, 12, 31, 0, 0, // Skip to: 986
+/* 955 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 958 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 972
+/* 963 */ MCD::OPC_CheckPredicate, 7, 159, 11, 0, // Skip to: 3943
+/* 968 */ MCD::OPC_Decode, 223, 3, 41, // Opcode: SC_W
+/* 972 */ MCD::OPC_FilterValue, 3, 150, 11, 0, // Skip to: 3943
+/* 977 */ MCD::OPC_CheckPredicate, 8, 145, 11, 0, // Skip to: 3943
+/* 982 */ MCD::OPC_Decode, 219, 3, 41, // Opcode: SC_D
+/* 986 */ MCD::OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1022
+/* 991 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 994 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1008
+/* 999 */ MCD::OPC_CheckPredicate, 7, 123, 11, 0, // Skip to: 3943
+/* 1004 */ MCD::OPC_Decode, 226, 3, 41, // Opcode: SC_W_RL
+/* 1008 */ MCD::OPC_FilterValue, 3, 114, 11, 0, // Skip to: 3943
+/* 1013 */ MCD::OPC_CheckPredicate, 8, 109, 11, 0, // Skip to: 3943
+/* 1018 */ MCD::OPC_Decode, 222, 3, 41, // Opcode: SC_D_RL
+/* 1022 */ MCD::OPC_FilterValue, 14, 31, 0, 0, // Skip to: 1058
+/* 1027 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1030 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1044
+/* 1035 */ MCD::OPC_CheckPredicate, 7, 87, 11, 0, // Skip to: 3943
+/* 1040 */ MCD::OPC_Decode, 224, 3, 41, // Opcode: SC_W_AQ
+/* 1044 */ MCD::OPC_FilterValue, 3, 78, 11, 0, // Skip to: 3943
+/* 1049 */ MCD::OPC_CheckPredicate, 8, 73, 11, 0, // Skip to: 3943
+/* 1054 */ MCD::OPC_Decode, 220, 3, 41, // Opcode: SC_D_AQ
+/* 1058 */ MCD::OPC_FilterValue, 15, 31, 0, 0, // Skip to: 1094
+/* 1063 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1066 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1080
+/* 1071 */ MCD::OPC_CheckPredicate, 7, 51, 11, 0, // Skip to: 3943
+/* 1076 */ MCD::OPC_Decode, 225, 3, 41, // Opcode: SC_W_AQ_RL
+/* 1080 */ MCD::OPC_FilterValue, 3, 42, 11, 0, // Skip to: 3943
+/* 1085 */ MCD::OPC_CheckPredicate, 8, 37, 11, 0, // Skip to: 3943
+/* 1090 */ MCD::OPC_Decode, 221, 3, 41, // Opcode: SC_D_AQ_RL
+/* 1094 */ MCD::OPC_FilterValue, 16, 31, 0, 0, // Skip to: 1130
+/* 1099 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1102 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1116
+/* 1107 */ MCD::OPC_CheckPredicate, 7, 15, 11, 0, // Skip to: 3943
+/* 1112 */ MCD::OPC_Decode, 171, 2, 41, // Opcode: AMOXOR_W
+/* 1116 */ MCD::OPC_FilterValue, 3, 6, 11, 0, // Skip to: 3943
+/* 1121 */ MCD::OPC_CheckPredicate, 8, 1, 11, 0, // Skip to: 3943
+/* 1126 */ MCD::OPC_Decode, 167, 2, 41, // Opcode: AMOXOR_D
+/* 1130 */ MCD::OPC_FilterValue, 17, 31, 0, 0, // Skip to: 1166
+/* 1135 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1138 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1152
+/* 1143 */ MCD::OPC_CheckPredicate, 7, 235, 10, 0, // Skip to: 3943
+/* 1148 */ MCD::OPC_Decode, 174, 2, 41, // Opcode: AMOXOR_W_RL
+/* 1152 */ MCD::OPC_FilterValue, 3, 226, 10, 0, // Skip to: 3943
+/* 1157 */ MCD::OPC_CheckPredicate, 8, 221, 10, 0, // Skip to: 3943
+/* 1162 */ MCD::OPC_Decode, 170, 2, 41, // Opcode: AMOXOR_D_RL
+/* 1166 */ MCD::OPC_FilterValue, 18, 31, 0, 0, // Skip to: 1202
+/* 1171 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1174 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1188
+/* 1179 */ MCD::OPC_CheckPredicate, 7, 199, 10, 0, // Skip to: 3943
+/* 1184 */ MCD::OPC_Decode, 172, 2, 41, // Opcode: AMOXOR_W_AQ
+/* 1188 */ MCD::OPC_FilterValue, 3, 190, 10, 0, // Skip to: 3943
+/* 1193 */ MCD::OPC_CheckPredicate, 8, 185, 10, 0, // Skip to: 3943
+/* 1198 */ MCD::OPC_Decode, 168, 2, 41, // Opcode: AMOXOR_D_AQ
+/* 1202 */ MCD::OPC_FilterValue, 19, 31, 0, 0, // Skip to: 1238
+/* 1207 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1210 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1224
+/* 1215 */ MCD::OPC_CheckPredicate, 7, 163, 10, 0, // Skip to: 3943
+/* 1220 */ MCD::OPC_Decode, 173, 2, 41, // Opcode: AMOXOR_W_AQ_RL
+/* 1224 */ MCD::OPC_FilterValue, 3, 154, 10, 0, // Skip to: 3943
+/* 1229 */ MCD::OPC_CheckPredicate, 8, 149, 10, 0, // Skip to: 3943
+/* 1234 */ MCD::OPC_Decode, 169, 2, 41, // Opcode: AMOXOR_D_AQ_RL
+/* 1238 */ MCD::OPC_FilterValue, 32, 31, 0, 0, // Skip to: 1274
+/* 1243 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1246 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1260
+/* 1251 */ MCD::OPC_CheckPredicate, 7, 127, 10, 0, // Skip to: 3943
+/* 1256 */ MCD::OPC_Decode, 155, 2, 41, // Opcode: AMOOR_W
+/* 1260 */ MCD::OPC_FilterValue, 3, 118, 10, 0, // Skip to: 3943
+/* 1265 */ MCD::OPC_CheckPredicate, 8, 113, 10, 0, // Skip to: 3943
+/* 1270 */ MCD::OPC_Decode, 151, 2, 41, // Opcode: AMOOR_D
+/* 1274 */ MCD::OPC_FilterValue, 33, 31, 0, 0, // Skip to: 1310
+/* 1279 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1282 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1296
+/* 1287 */ MCD::OPC_CheckPredicate, 7, 91, 10, 0, // Skip to: 3943
+/* 1292 */ MCD::OPC_Decode, 158, 2, 41, // Opcode: AMOOR_W_RL
+/* 1296 */ MCD::OPC_FilterValue, 3, 82, 10, 0, // Skip to: 3943
+/* 1301 */ MCD::OPC_CheckPredicate, 8, 77, 10, 0, // Skip to: 3943
+/* 1306 */ MCD::OPC_Decode, 154, 2, 41, // Opcode: AMOOR_D_RL
+/* 1310 */ MCD::OPC_FilterValue, 34, 31, 0, 0, // Skip to: 1346
+/* 1315 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1318 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1332
+/* 1323 */ MCD::OPC_CheckPredicate, 7, 55, 10, 0, // Skip to: 3943
+/* 1328 */ MCD::OPC_Decode, 156, 2, 41, // Opcode: AMOOR_W_AQ
+/* 1332 */ MCD::OPC_FilterValue, 3, 46, 10, 0, // Skip to: 3943
+/* 1337 */ MCD::OPC_CheckPredicate, 8, 41, 10, 0, // Skip to: 3943
+/* 1342 */ MCD::OPC_Decode, 152, 2, 41, // Opcode: AMOOR_D_AQ
+/* 1346 */ MCD::OPC_FilterValue, 35, 31, 0, 0, // Skip to: 1382
+/* 1351 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1354 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1368
+/* 1359 */ MCD::OPC_CheckPredicate, 7, 19, 10, 0, // Skip to: 3943
+/* 1364 */ MCD::OPC_Decode, 157, 2, 41, // Opcode: AMOOR_W_AQ_RL
+/* 1368 */ MCD::OPC_FilterValue, 3, 10, 10, 0, // Skip to: 3943
+/* 1373 */ MCD::OPC_CheckPredicate, 8, 5, 10, 0, // Skip to: 3943
+/* 1378 */ MCD::OPC_Decode, 153, 2, 41, // Opcode: AMOOR_D_AQ_RL
+/* 1382 */ MCD::OPC_FilterValue, 48, 31, 0, 0, // Skip to: 1418
+/* 1387 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1390 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1404
+/* 1395 */ MCD::OPC_CheckPredicate, 7, 239, 9, 0, // Skip to: 3943
+/* 1400 */ MCD::OPC_Decode, 243, 1, 41, // Opcode: AMOAND_W
+/* 1404 */ MCD::OPC_FilterValue, 3, 230, 9, 0, // Skip to: 3943
+/* 1409 */ MCD::OPC_CheckPredicate, 8, 225, 9, 0, // Skip to: 3943
+/* 1414 */ MCD::OPC_Decode, 239, 1, 41, // Opcode: AMOAND_D
+/* 1418 */ MCD::OPC_FilterValue, 49, 31, 0, 0, // Skip to: 1454
+/* 1423 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1426 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1440
+/* 1431 */ MCD::OPC_CheckPredicate, 7, 203, 9, 0, // Skip to: 3943
+/* 1436 */ MCD::OPC_Decode, 246, 1, 41, // Opcode: AMOAND_W_RL
+/* 1440 */ MCD::OPC_FilterValue, 3, 194, 9, 0, // Skip to: 3943
+/* 1445 */ MCD::OPC_CheckPredicate, 8, 189, 9, 0, // Skip to: 3943
+/* 1450 */ MCD::OPC_Decode, 242, 1, 41, // Opcode: AMOAND_D_RL
+/* 1454 */ MCD::OPC_FilterValue, 50, 31, 0, 0, // Skip to: 1490
+/* 1459 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1462 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1476
+/* 1467 */ MCD::OPC_CheckPredicate, 7, 167, 9, 0, // Skip to: 3943
+/* 1472 */ MCD::OPC_Decode, 244, 1, 41, // Opcode: AMOAND_W_AQ
+/* 1476 */ MCD::OPC_FilterValue, 3, 158, 9, 0, // Skip to: 3943
+/* 1481 */ MCD::OPC_CheckPredicate, 8, 153, 9, 0, // Skip to: 3943
+/* 1486 */ MCD::OPC_Decode, 240, 1, 41, // Opcode: AMOAND_D_AQ
+/* 1490 */ MCD::OPC_FilterValue, 51, 31, 0, 0, // Skip to: 1526
+/* 1495 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1498 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1512
+/* 1503 */ MCD::OPC_CheckPredicate, 7, 131, 9, 0, // Skip to: 3943
+/* 1508 */ MCD::OPC_Decode, 245, 1, 41, // Opcode: AMOAND_W_AQ_RL
+/* 1512 */ MCD::OPC_FilterValue, 3, 122, 9, 0, // Skip to: 3943
+/* 1517 */ MCD::OPC_CheckPredicate, 8, 117, 9, 0, // Skip to: 3943
+/* 1522 */ MCD::OPC_Decode, 241, 1, 41, // Opcode: AMOAND_D_AQ_RL
+/* 1526 */ MCD::OPC_FilterValue, 64, 31, 0, 0, // Skip to: 1562
+/* 1531 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1534 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1548
+/* 1539 */ MCD::OPC_CheckPredicate, 7, 95, 9, 0, // Skip to: 3943
+/* 1544 */ MCD::OPC_Decode, 147, 2, 41, // Opcode: AMOMIN_W
+/* 1548 */ MCD::OPC_FilterValue, 3, 86, 9, 0, // Skip to: 3943
+/* 1553 */ MCD::OPC_CheckPredicate, 8, 81, 9, 0, // Skip to: 3943
+/* 1558 */ MCD::OPC_Decode, 143, 2, 41, // Opcode: AMOMIN_D
+/* 1562 */ MCD::OPC_FilterValue, 65, 31, 0, 0, // Skip to: 1598
+/* 1567 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1570 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1584
+/* 1575 */ MCD::OPC_CheckPredicate, 7, 59, 9, 0, // Skip to: 3943
+/* 1580 */ MCD::OPC_Decode, 150, 2, 41, // Opcode: AMOMIN_W_RL
+/* 1584 */ MCD::OPC_FilterValue, 3, 50, 9, 0, // Skip to: 3943
+/* 1589 */ MCD::OPC_CheckPredicate, 8, 45, 9, 0, // Skip to: 3943
+/* 1594 */ MCD::OPC_Decode, 146, 2, 41, // Opcode: AMOMIN_D_RL
+/* 1598 */ MCD::OPC_FilterValue, 66, 31, 0, 0, // Skip to: 1634
+/* 1603 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1606 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1620
+/* 1611 */ MCD::OPC_CheckPredicate, 7, 23, 9, 0, // Skip to: 3943
+/* 1616 */ MCD::OPC_Decode, 148, 2, 41, // Opcode: AMOMIN_W_AQ
+/* 1620 */ MCD::OPC_FilterValue, 3, 14, 9, 0, // Skip to: 3943
+/* 1625 */ MCD::OPC_CheckPredicate, 8, 9, 9, 0, // Skip to: 3943
+/* 1630 */ MCD::OPC_Decode, 144, 2, 41, // Opcode: AMOMIN_D_AQ
+/* 1634 */ MCD::OPC_FilterValue, 67, 31, 0, 0, // Skip to: 1670
+/* 1639 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1642 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1656
+/* 1647 */ MCD::OPC_CheckPredicate, 7, 243, 8, 0, // Skip to: 3943
+/* 1652 */ MCD::OPC_Decode, 149, 2, 41, // Opcode: AMOMIN_W_AQ_RL
+/* 1656 */ MCD::OPC_FilterValue, 3, 234, 8, 0, // Skip to: 3943
+/* 1661 */ MCD::OPC_CheckPredicate, 8, 229, 8, 0, // Skip to: 3943
+/* 1666 */ MCD::OPC_Decode, 145, 2, 41, // Opcode: AMOMIN_D_AQ_RL
+/* 1670 */ MCD::OPC_FilterValue, 80, 31, 0, 0, // Skip to: 1706
+/* 1675 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1678 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1692
+/* 1683 */ MCD::OPC_CheckPredicate, 7, 207, 8, 0, // Skip to: 3943
+/* 1688 */ MCD::OPC_Decode, 131, 2, 41, // Opcode: AMOMAX_W
+/* 1692 */ MCD::OPC_FilterValue, 3, 198, 8, 0, // Skip to: 3943
+/* 1697 */ MCD::OPC_CheckPredicate, 8, 193, 8, 0, // Skip to: 3943
+/* 1702 */ MCD::OPC_Decode, 255, 1, 41, // Opcode: AMOMAX_D
+/* 1706 */ MCD::OPC_FilterValue, 81, 31, 0, 0, // Skip to: 1742
+/* 1711 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1714 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1728
+/* 1719 */ MCD::OPC_CheckPredicate, 7, 171, 8, 0, // Skip to: 3943
+/* 1724 */ MCD::OPC_Decode, 134, 2, 41, // Opcode: AMOMAX_W_RL
+/* 1728 */ MCD::OPC_FilterValue, 3, 162, 8, 0, // Skip to: 3943
+/* 1733 */ MCD::OPC_CheckPredicate, 8, 157, 8, 0, // Skip to: 3943
+/* 1738 */ MCD::OPC_Decode, 130, 2, 41, // Opcode: AMOMAX_D_RL
+/* 1742 */ MCD::OPC_FilterValue, 82, 31, 0, 0, // Skip to: 1778
+/* 1747 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1750 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1764
+/* 1755 */ MCD::OPC_CheckPredicate, 7, 135, 8, 0, // Skip to: 3943
+/* 1760 */ MCD::OPC_Decode, 132, 2, 41, // Opcode: AMOMAX_W_AQ
+/* 1764 */ MCD::OPC_FilterValue, 3, 126, 8, 0, // Skip to: 3943
+/* 1769 */ MCD::OPC_CheckPredicate, 8, 121, 8, 0, // Skip to: 3943
+/* 1774 */ MCD::OPC_Decode, 128, 2, 41, // Opcode: AMOMAX_D_AQ
+/* 1778 */ MCD::OPC_FilterValue, 83, 31, 0, 0, // Skip to: 1814
+/* 1783 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1786 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1800
+/* 1791 */ MCD::OPC_CheckPredicate, 7, 99, 8, 0, // Skip to: 3943
+/* 1796 */ MCD::OPC_Decode, 133, 2, 41, // Opcode: AMOMAX_W_AQ_RL
+/* 1800 */ MCD::OPC_FilterValue, 3, 90, 8, 0, // Skip to: 3943
+/* 1805 */ MCD::OPC_CheckPredicate, 8, 85, 8, 0, // Skip to: 3943
+/* 1810 */ MCD::OPC_Decode, 129, 2, 41, // Opcode: AMOMAX_D_AQ_RL
+/* 1814 */ MCD::OPC_FilterValue, 96, 31, 0, 0, // Skip to: 1850
+/* 1819 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1822 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1836
+/* 1827 */ MCD::OPC_CheckPredicate, 7, 63, 8, 0, // Skip to: 3943
+/* 1832 */ MCD::OPC_Decode, 139, 2, 41, // Opcode: AMOMINU_W
+/* 1836 */ MCD::OPC_FilterValue, 3, 54, 8, 0, // Skip to: 3943
+/* 1841 */ MCD::OPC_CheckPredicate, 8, 49, 8, 0, // Skip to: 3943
+/* 1846 */ MCD::OPC_Decode, 135, 2, 41, // Opcode: AMOMINU_D
+/* 1850 */ MCD::OPC_FilterValue, 97, 31, 0, 0, // Skip to: 1886
+/* 1855 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1858 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1872
+/* 1863 */ MCD::OPC_CheckPredicate, 7, 27, 8, 0, // Skip to: 3943
+/* 1868 */ MCD::OPC_Decode, 142, 2, 41, // Opcode: AMOMINU_W_RL
+/* 1872 */ MCD::OPC_FilterValue, 3, 18, 8, 0, // Skip to: 3943
+/* 1877 */ MCD::OPC_CheckPredicate, 8, 13, 8, 0, // Skip to: 3943
+/* 1882 */ MCD::OPC_Decode, 138, 2, 41, // Opcode: AMOMINU_D_RL
+/* 1886 */ MCD::OPC_FilterValue, 98, 31, 0, 0, // Skip to: 1922
+/* 1891 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1894 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1908
+/* 1899 */ MCD::OPC_CheckPredicate, 7, 247, 7, 0, // Skip to: 3943
+/* 1904 */ MCD::OPC_Decode, 140, 2, 41, // Opcode: AMOMINU_W_AQ
+/* 1908 */ MCD::OPC_FilterValue, 3, 238, 7, 0, // Skip to: 3943
+/* 1913 */ MCD::OPC_CheckPredicate, 8, 233, 7, 0, // Skip to: 3943
+/* 1918 */ MCD::OPC_Decode, 136, 2, 41, // Opcode: AMOMINU_D_AQ
+/* 1922 */ MCD::OPC_FilterValue, 99, 31, 0, 0, // Skip to: 1958
+/* 1927 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1930 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1944
+/* 1935 */ MCD::OPC_CheckPredicate, 7, 211, 7, 0, // Skip to: 3943
+/* 1940 */ MCD::OPC_Decode, 141, 2, 41, // Opcode: AMOMINU_W_AQ_RL
+/* 1944 */ MCD::OPC_FilterValue, 3, 202, 7, 0, // Skip to: 3943
+/* 1949 */ MCD::OPC_CheckPredicate, 8, 197, 7, 0, // Skip to: 3943
+/* 1954 */ MCD::OPC_Decode, 137, 2, 41, // Opcode: AMOMINU_D_AQ_RL
+/* 1958 */ MCD::OPC_FilterValue, 112, 31, 0, 0, // Skip to: 1994
+/* 1963 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 1966 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 1980
+/* 1971 */ MCD::OPC_CheckPredicate, 7, 175, 7, 0, // Skip to: 3943
+/* 1976 */ MCD::OPC_Decode, 251, 1, 41, // Opcode: AMOMAXU_W
+/* 1980 */ MCD::OPC_FilterValue, 3, 166, 7, 0, // Skip to: 3943
+/* 1985 */ MCD::OPC_CheckPredicate, 8, 161, 7, 0, // Skip to: 3943
+/* 1990 */ MCD::OPC_Decode, 247, 1, 41, // Opcode: AMOMAXU_D
+/* 1994 */ MCD::OPC_FilterValue, 113, 31, 0, 0, // Skip to: 2030
+/* 1999 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2002 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2016
+/* 2007 */ MCD::OPC_CheckPredicate, 7, 139, 7, 0, // Skip to: 3943
+/* 2012 */ MCD::OPC_Decode, 254, 1, 41, // Opcode: AMOMAXU_W_RL
+/* 2016 */ MCD::OPC_FilterValue, 3, 130, 7, 0, // Skip to: 3943
+/* 2021 */ MCD::OPC_CheckPredicate, 8, 125, 7, 0, // Skip to: 3943
+/* 2026 */ MCD::OPC_Decode, 250, 1, 41, // Opcode: AMOMAXU_D_RL
+/* 2030 */ MCD::OPC_FilterValue, 114, 31, 0, 0, // Skip to: 2066
+/* 2035 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2038 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2052
+/* 2043 */ MCD::OPC_CheckPredicate, 7, 103, 7, 0, // Skip to: 3943
+/* 2048 */ MCD::OPC_Decode, 252, 1, 41, // Opcode: AMOMAXU_W_AQ
+/* 2052 */ MCD::OPC_FilterValue, 3, 94, 7, 0, // Skip to: 3943
+/* 2057 */ MCD::OPC_CheckPredicate, 8, 89, 7, 0, // Skip to: 3943
+/* 2062 */ MCD::OPC_Decode, 248, 1, 41, // Opcode: AMOMAXU_D_AQ
+/* 2066 */ MCD::OPC_FilterValue, 115, 80, 7, 0, // Skip to: 3943
+/* 2071 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2074 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2088
+/* 2079 */ MCD::OPC_CheckPredicate, 7, 67, 7, 0, // Skip to: 3943
+/* 2084 */ MCD::OPC_Decode, 253, 1, 41, // Opcode: AMOMAXU_W_AQ_RL
+/* 2088 */ MCD::OPC_FilterValue, 3, 58, 7, 0, // Skip to: 3943
+/* 2093 */ MCD::OPC_CheckPredicate, 8, 53, 7, 0, // Skip to: 3943
+/* 2098 */ MCD::OPC_Decode, 249, 1, 41, // Opcode: AMOMAXU_D_AQ_RL
+/* 2102 */ MCD::OPC_FilterValue, 51, 13, 1, 0, // Skip to: 2376
+/* 2107 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2110 */ MCD::OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2150
+/* 2115 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2118 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2127
+/* 2123 */ MCD::OPC_Decode, 227, 1, 41, // Opcode: ADD
+/* 2127 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2141
+/* 2132 */ MCD::OPC_CheckPredicate, 9, 14, 7, 0, // Skip to: 3943
+/* 2137 */ MCD::OPC_Decode, 207, 3, 41, // Opcode: MUL
+/* 2141 */ MCD::OPC_FilterValue, 32, 5, 7, 0, // Skip to: 3943
+/* 2146 */ MCD::OPC_Decode, 247, 3, 41, // Opcode: SUB
+/* 2150 */ MCD::OPC_FilterValue, 1, 26, 0, 0, // Skip to: 2181
+/* 2155 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2158 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2167
+/* 2163 */ MCD::OPC_Decode, 230, 3, 41, // Opcode: SLL
+/* 2167 */ MCD::OPC_FilterValue, 1, 235, 6, 0, // Skip to: 3943
+/* 2172 */ MCD::OPC_CheckPredicate, 9, 230, 6, 0, // Skip to: 3943
+/* 2177 */ MCD::OPC_Decode, 208, 3, 41, // Opcode: MULH
+/* 2181 */ MCD::OPC_FilterValue, 2, 26, 0, 0, // Skip to: 2212
+/* 2186 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2189 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2198
+/* 2194 */ MCD::OPC_Decode, 234, 3, 41, // Opcode: SLT
+/* 2198 */ MCD::OPC_FilterValue, 1, 204, 6, 0, // Skip to: 3943
+/* 2203 */ MCD::OPC_CheckPredicate, 9, 199, 6, 0, // Skip to: 3943
+/* 2208 */ MCD::OPC_Decode, 209, 3, 41, // Opcode: MULHSU
+/* 2212 */ MCD::OPC_FilterValue, 3, 26, 0, 0, // Skip to: 2243
+/* 2217 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2220 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2229
+/* 2225 */ MCD::OPC_Decode, 237, 3, 41, // Opcode: SLTU
+/* 2229 */ MCD::OPC_FilterValue, 1, 173, 6, 0, // Skip to: 3943
+/* 2234 */ MCD::OPC_CheckPredicate, 9, 168, 6, 0, // Skip to: 3943
+/* 2239 */ MCD::OPC_Decode, 210, 3, 41, // Opcode: MULHU
+/* 2243 */ MCD::OPC_FilterValue, 4, 26, 0, 0, // Skip to: 2274
+/* 2248 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2251 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2260
+/* 2256 */ MCD::OPC_Decode, 253, 3, 41, // Opcode: XOR
+/* 2260 */ MCD::OPC_FilterValue, 1, 142, 6, 0, // Skip to: 3943
+/* 2265 */ MCD::OPC_CheckPredicate, 9, 137, 6, 0, // Skip to: 3943
+/* 2270 */ MCD::OPC_Decode, 245, 2, 41, // Opcode: DIV
+/* 2274 */ MCD::OPC_FilterValue, 5, 35, 0, 0, // Skip to: 2314
+/* 2279 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2282 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2291
+/* 2287 */ MCD::OPC_Decode, 243, 3, 41, // Opcode: SRL
+/* 2291 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2305
+/* 2296 */ MCD::OPC_CheckPredicate, 9, 106, 6, 0, // Skip to: 3943
+/* 2301 */ MCD::OPC_Decode, 246, 2, 41, // Opcode: DIVU
+/* 2305 */ MCD::OPC_FilterValue, 32, 97, 6, 0, // Skip to: 3943
+/* 2310 */ MCD::OPC_Decode, 238, 3, 41, // Opcode: SRA
+/* 2314 */ MCD::OPC_FilterValue, 6, 26, 0, 0, // Skip to: 2345
+/* 2319 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2322 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2331
+/* 2327 */ MCD::OPC_Decode, 212, 3, 41, // Opcode: OR
+/* 2331 */ MCD::OPC_FilterValue, 1, 71, 6, 0, // Skip to: 3943
+/* 2336 */ MCD::OPC_CheckPredicate, 9, 66, 6, 0, // Skip to: 3943
+/* 2341 */ MCD::OPC_Decode, 214, 3, 41, // Opcode: REM
+/* 2345 */ MCD::OPC_FilterValue, 7, 57, 6, 0, // Skip to: 3943
+/* 2350 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2353 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 2362
+/* 2358 */ MCD::OPC_Decode, 175, 2, 41, // Opcode: AND
+/* 2362 */ MCD::OPC_FilterValue, 1, 40, 6, 0, // Skip to: 3943
+/* 2367 */ MCD::OPC_CheckPredicate, 9, 35, 6, 0, // Skip to: 3943
+/* 2372 */ MCD::OPC_Decode, 215, 3, 41, // Opcode: REMU
+/* 2376 */ MCD::OPC_FilterValue, 55, 4, 0, 0, // Skip to: 2385
+/* 2381 */ MCD::OPC_Decode, 203, 3, 36, // Opcode: LUI
+/* 2385 */ MCD::OPC_FilterValue, 59, 187, 0, 0, // Skip to: 2577
+/* 2390 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2393 */ MCD::OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2443
+/* 2398 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2401 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2415
+/* 2406 */ MCD::OPC_CheckPredicate, 4, 252, 5, 0, // Skip to: 3943
+/* 2411 */ MCD::OPC_Decode, 230, 1, 41, // Opcode: ADDW
+/* 2415 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2429
+/* 2420 */ MCD::OPC_CheckPredicate, 10, 238, 5, 0, // Skip to: 3943
+/* 2425 */ MCD::OPC_Decode, 211, 3, 41, // Opcode: MULW
+/* 2429 */ MCD::OPC_FilterValue, 32, 229, 5, 0, // Skip to: 3943
+/* 2434 */ MCD::OPC_CheckPredicate, 4, 224, 5, 0, // Skip to: 3943
+/* 2439 */ MCD::OPC_Decode, 248, 3, 41, // Opcode: SUBW
+/* 2443 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 2464
+/* 2448 */ MCD::OPC_CheckPredicate, 4, 210, 5, 0, // Skip to: 3943
+/* 2453 */ MCD::OPC_CheckField, 25, 7, 0, 203, 5, 0, // Skip to: 3943
+/* 2460 */ MCD::OPC_Decode, 233, 3, 41, // Opcode: SLLW
+/* 2464 */ MCD::OPC_FilterValue, 4, 16, 0, 0, // Skip to: 2485
+/* 2469 */ MCD::OPC_CheckPredicate, 10, 189, 5, 0, // Skip to: 3943
+/* 2474 */ MCD::OPC_CheckField, 25, 7, 1, 182, 5, 0, // Skip to: 3943
+/* 2481 */ MCD::OPC_Decode, 248, 2, 41, // Opcode: DIVW
+/* 2485 */ MCD::OPC_FilterValue, 5, 45, 0, 0, // Skip to: 2535
+/* 2490 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2493 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2507
+/* 2498 */ MCD::OPC_CheckPredicate, 4, 160, 5, 0, // Skip to: 3943
+/* 2503 */ MCD::OPC_Decode, 246, 3, 41, // Opcode: SRLW
+/* 2507 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2521
+/* 2512 */ MCD::OPC_CheckPredicate, 10, 146, 5, 0, // Skip to: 3943
+/* 2517 */ MCD::OPC_Decode, 247, 2, 41, // Opcode: DIVUW
+/* 2521 */ MCD::OPC_FilterValue, 32, 137, 5, 0, // Skip to: 3943
+/* 2526 */ MCD::OPC_CheckPredicate, 4, 132, 5, 0, // Skip to: 3943
+/* 2531 */ MCD::OPC_Decode, 241, 3, 41, // Opcode: SRAW
+/* 2535 */ MCD::OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2556
+/* 2540 */ MCD::OPC_CheckPredicate, 10, 118, 5, 0, // Skip to: 3943
+/* 2545 */ MCD::OPC_CheckField, 25, 7, 1, 111, 5, 0, // Skip to: 3943
+/* 2552 */ MCD::OPC_Decode, 217, 3, 41, // Opcode: REMW
+/* 2556 */ MCD::OPC_FilterValue, 7, 102, 5, 0, // Skip to: 3943
+/* 2561 */ MCD::OPC_CheckPredicate, 10, 97, 5, 0, // Skip to: 3943
+/* 2566 */ MCD::OPC_CheckField, 25, 7, 1, 90, 5, 0, // Skip to: 3943
+/* 2573 */ MCD::OPC_Decode, 216, 3, 41, // Opcode: REMUW
+/* 2577 */ MCD::OPC_FilterValue, 67, 31, 0, 0, // Skip to: 2613
+/* 2582 */ MCD::OPC_ExtractField, 25, 2, // Inst{26-25} ...
+/* 2585 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2599
+/* 2590 */ MCD::OPC_CheckPredicate, 5, 68, 5, 0, // Skip to: 3943
+/* 2595 */ MCD::OPC_Decode, 159, 3, 43, // Opcode: FMADD_S
+/* 2599 */ MCD::OPC_FilterValue, 1, 59, 5, 0, // Skip to: 3943
+/* 2604 */ MCD::OPC_CheckPredicate, 6, 54, 5, 0, // Skip to: 3943
+/* 2609 */ MCD::OPC_Decode, 158, 3, 44, // Opcode: FMADD_D
+/* 2613 */ MCD::OPC_FilterValue, 71, 31, 0, 0, // Skip to: 2649
+/* 2618 */ MCD::OPC_ExtractField, 25, 2, // Inst{26-25} ...
+/* 2621 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2635
+/* 2626 */ MCD::OPC_CheckPredicate, 5, 32, 5, 0, // Skip to: 3943
+/* 2631 */ MCD::OPC_Decode, 165, 3, 43, // Opcode: FMSUB_S
+/* 2635 */ MCD::OPC_FilterValue, 1, 23, 5, 0, // Skip to: 3943
+/* 2640 */ MCD::OPC_CheckPredicate, 6, 18, 5, 0, // Skip to: 3943
+/* 2645 */ MCD::OPC_Decode, 164, 3, 44, // Opcode: FMSUB_D
+/* 2649 */ MCD::OPC_FilterValue, 75, 31, 0, 0, // Skip to: 2685
+/* 2654 */ MCD::OPC_ExtractField, 25, 2, // Inst{26-25} ...
+/* 2657 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2671
+/* 2662 */ MCD::OPC_CheckPredicate, 5, 252, 4, 0, // Skip to: 3943
+/* 2667 */ MCD::OPC_Decode, 175, 3, 43, // Opcode: FNMSUB_S
+/* 2671 */ MCD::OPC_FilterValue, 1, 243, 4, 0, // Skip to: 3943
+/* 2676 */ MCD::OPC_CheckPredicate, 6, 238, 4, 0, // Skip to: 3943
+/* 2681 */ MCD::OPC_Decode, 174, 3, 44, // Opcode: FNMSUB_D
+/* 2685 */ MCD::OPC_FilterValue, 79, 31, 0, 0, // Skip to: 2721
+/* 2690 */ MCD::OPC_ExtractField, 25, 2, // Inst{26-25} ...
+/* 2693 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2707
+/* 2698 */ MCD::OPC_CheckPredicate, 5, 216, 4, 0, // Skip to: 3943
+/* 2703 */ MCD::OPC_Decode, 173, 3, 43, // Opcode: FNMADD_S
+/* 2707 */ MCD::OPC_FilterValue, 1, 207, 4, 0, // Skip to: 3943
+/* 2712 */ MCD::OPC_CheckPredicate, 6, 202, 4, 0, // Skip to: 3943
+/* 2717 */ MCD::OPC_Decode, 172, 3, 44, // Opcode: FNMADD_D
+/* 2721 */ MCD::OPC_FilterValue, 83, 136, 3, 0, // Skip to: 3630
+/* 2726 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 2729 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2743
+/* 2734 */ MCD::OPC_CheckPredicate, 5, 180, 4, 0, // Skip to: 3943
+/* 2739 */ MCD::OPC_Decode, 252, 2, 45, // Opcode: FADD_S
+/* 2743 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2757
+/* 2748 */ MCD::OPC_CheckPredicate, 6, 166, 4, 0, // Skip to: 3943
+/* 2753 */ MCD::OPC_Decode, 251, 2, 46, // Opcode: FADD_D
+/* 2757 */ MCD::OPC_FilterValue, 4, 9, 0, 0, // Skip to: 2771
+/* 2762 */ MCD::OPC_CheckPredicate, 5, 152, 4, 0, // Skip to: 3943
+/* 2767 */ MCD::OPC_Decode, 186, 3, 45, // Opcode: FSUB_S
+/* 2771 */ MCD::OPC_FilterValue, 5, 9, 0, 0, // Skip to: 2785
+/* 2776 */ MCD::OPC_CheckPredicate, 6, 138, 4, 0, // Skip to: 3943
+/* 2781 */ MCD::OPC_Decode, 185, 3, 46, // Opcode: FSUB_D
+/* 2785 */ MCD::OPC_FilterValue, 8, 9, 0, 0, // Skip to: 2799
+/* 2790 */ MCD::OPC_CheckPredicate, 5, 124, 4, 0, // Skip to: 3943
+/* 2795 */ MCD::OPC_Decode, 167, 3, 45, // Opcode: FMUL_S
+/* 2799 */ MCD::OPC_FilterValue, 9, 9, 0, 0, // Skip to: 2813
+/* 2804 */ MCD::OPC_CheckPredicate, 6, 110, 4, 0, // Skip to: 3943
+/* 2809 */ MCD::OPC_Decode, 166, 3, 46, // Opcode: FMUL_D
+/* 2813 */ MCD::OPC_FilterValue, 12, 9, 0, 0, // Skip to: 2827
+/* 2818 */ MCD::OPC_CheckPredicate, 5, 96, 4, 0, // Skip to: 3943
+/* 2823 */ MCD::OPC_Decode, 146, 3, 45, // Opcode: FDIV_S
+/* 2827 */ MCD::OPC_FilterValue, 13, 9, 0, 0, // Skip to: 2841
+/* 2832 */ MCD::OPC_CheckPredicate, 6, 82, 4, 0, // Skip to: 3943
+/* 2837 */ MCD::OPC_Decode, 145, 3, 46, // Opcode: FDIV_D
+/* 2841 */ MCD::OPC_FilterValue, 16, 45, 0, 0, // Skip to: 2891
+/* 2846 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2849 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2863
+/* 2854 */ MCD::OPC_CheckPredicate, 5, 60, 4, 0, // Skip to: 3943
+/* 2859 */ MCD::OPC_Decode, 182, 3, 47, // Opcode: FSGNJ_S
+/* 2863 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2877
+/* 2868 */ MCD::OPC_CheckPredicate, 5, 46, 4, 0, // Skip to: 3943
+/* 2873 */ MCD::OPC_Decode, 178, 3, 47, // Opcode: FSGNJN_S
+/* 2877 */ MCD::OPC_FilterValue, 2, 37, 4, 0, // Skip to: 3943
+/* 2882 */ MCD::OPC_CheckPredicate, 5, 32, 4, 0, // Skip to: 3943
+/* 2887 */ MCD::OPC_Decode, 180, 3, 47, // Opcode: FSGNJX_S
+/* 2891 */ MCD::OPC_FilterValue, 17, 45, 0, 0, // Skip to: 2941
+/* 2896 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2899 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2913
+/* 2904 */ MCD::OPC_CheckPredicate, 6, 10, 4, 0, // Skip to: 3943
+/* 2909 */ MCD::OPC_Decode, 181, 3, 48, // Opcode: FSGNJ_D
+/* 2913 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2927
+/* 2918 */ MCD::OPC_CheckPredicate, 6, 252, 3, 0, // Skip to: 3943
+/* 2923 */ MCD::OPC_Decode, 177, 3, 48, // Opcode: FSGNJN_D
+/* 2927 */ MCD::OPC_FilterValue, 2, 243, 3, 0, // Skip to: 3943
+/* 2932 */ MCD::OPC_CheckPredicate, 6, 238, 3, 0, // Skip to: 3943
+/* 2937 */ MCD::OPC_Decode, 179, 3, 48, // Opcode: FSGNJX_D
+/* 2941 */ MCD::OPC_FilterValue, 20, 31, 0, 0, // Skip to: 2977
+/* 2946 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2949 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2963
+/* 2954 */ MCD::OPC_CheckPredicate, 5, 216, 3, 0, // Skip to: 3943
+/* 2959 */ MCD::OPC_Decode, 163, 3, 47, // Opcode: FMIN_S
+/* 2963 */ MCD::OPC_FilterValue, 1, 207, 3, 0, // Skip to: 3943
+/* 2968 */ MCD::OPC_CheckPredicate, 5, 202, 3, 0, // Skip to: 3943
+/* 2973 */ MCD::OPC_Decode, 161, 3, 47, // Opcode: FMAX_S
+/* 2977 */ MCD::OPC_FilterValue, 21, 31, 0, 0, // Skip to: 3013
+/* 2982 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 2985 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2999
+/* 2990 */ MCD::OPC_CheckPredicate, 6, 180, 3, 0, // Skip to: 3943
+/* 2995 */ MCD::OPC_Decode, 162, 3, 48, // Opcode: FMIN_D
+/* 2999 */ MCD::OPC_FilterValue, 1, 171, 3, 0, // Skip to: 3943
+/* 3004 */ MCD::OPC_CheckPredicate, 6, 166, 3, 0, // Skip to: 3943
+/* 3009 */ MCD::OPC_Decode, 160, 3, 48, // Opcode: FMAX_D
+/* 3013 */ MCD::OPC_FilterValue, 32, 16, 0, 0, // Skip to: 3034
+/* 3018 */ MCD::OPC_CheckPredicate, 6, 152, 3, 0, // Skip to: 3943
+/* 3023 */ MCD::OPC_CheckField, 20, 5, 1, 145, 3, 0, // Skip to: 3943
+/* 3030 */ MCD::OPC_Decode, 136, 3, 49, // Opcode: FCVT_S_D
+/* 3034 */ MCD::OPC_FilterValue, 33, 23, 0, 0, // Skip to: 3062
+/* 3039 */ MCD::OPC_CheckPredicate, 6, 131, 3, 0, // Skip to: 3943
+/* 3044 */ MCD::OPC_CheckField, 20, 5, 0, 124, 3, 0, // Skip to: 3943
+/* 3051 */ MCD::OPC_CheckField, 12, 3, 0, 117, 3, 0, // Skip to: 3943
+/* 3058 */ MCD::OPC_Decode, 129, 3, 50, // Opcode: FCVT_D_S
+/* 3062 */ MCD::OPC_FilterValue, 44, 16, 0, 0, // Skip to: 3083
+/* 3067 */ MCD::OPC_CheckPredicate, 5, 103, 3, 0, // Skip to: 3943
+/* 3072 */ MCD::OPC_CheckField, 20, 5, 0, 96, 3, 0, // Skip to: 3943
+/* 3079 */ MCD::OPC_Decode, 184, 3, 51, // Opcode: FSQRT_S
+/* 3083 */ MCD::OPC_FilterValue, 45, 16, 0, 0, // Skip to: 3104
+/* 3088 */ MCD::OPC_CheckPredicate, 6, 82, 3, 0, // Skip to: 3943
+/* 3093 */ MCD::OPC_CheckField, 20, 5, 0, 75, 3, 0, // Skip to: 3943
+/* 3100 */ MCD::OPC_Decode, 183, 3, 52, // Opcode: FSQRT_D
+/* 3104 */ MCD::OPC_FilterValue, 80, 45, 0, 0, // Skip to: 3154
+/* 3109 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 3112 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3126
+/* 3117 */ MCD::OPC_CheckPredicate, 5, 53, 3, 0, // Skip to: 3943
+/* 3122 */ MCD::OPC_Decode, 154, 3, 53, // Opcode: FLE_S
+/* 3126 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3140
+/* 3131 */ MCD::OPC_CheckPredicate, 5, 39, 3, 0, // Skip to: 3943
+/* 3136 */ MCD::OPC_Decode, 156, 3, 53, // Opcode: FLT_S
+/* 3140 */ MCD::OPC_FilterValue, 2, 30, 3, 0, // Skip to: 3943
+/* 3145 */ MCD::OPC_CheckPredicate, 5, 25, 3, 0, // Skip to: 3943
+/* 3150 */ MCD::OPC_Decode, 151, 3, 53, // Opcode: FEQ_S
+/* 3154 */ MCD::OPC_FilterValue, 81, 45, 0, 0, // Skip to: 3204
+/* 3159 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 3162 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3176
+/* 3167 */ MCD::OPC_CheckPredicate, 6, 3, 3, 0, // Skip to: 3943
+/* 3172 */ MCD::OPC_Decode, 153, 3, 54, // Opcode: FLE_D
+/* 3176 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3190
+/* 3181 */ MCD::OPC_CheckPredicate, 6, 245, 2, 0, // Skip to: 3943
+/* 3186 */ MCD::OPC_Decode, 155, 3, 54, // Opcode: FLT_D
+/* 3190 */ MCD::OPC_FilterValue, 2, 236, 2, 0, // Skip to: 3943
+/* 3195 */ MCD::OPC_CheckPredicate, 6, 231, 2, 0, // Skip to: 3943
+/* 3200 */ MCD::OPC_Decode, 150, 3, 54, // Opcode: FEQ_D
+/* 3204 */ MCD::OPC_FilterValue, 96, 59, 0, 0, // Skip to: 3268
+/* 3209 */ MCD::OPC_ExtractField, 20, 5, // Inst{24-20} ...
+/* 3212 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3226
+/* 3217 */ MCD::OPC_CheckPredicate, 5, 209, 2, 0, // Skip to: 3943
+/* 3222 */ MCD::OPC_Decode, 144, 3, 55, // Opcode: FCVT_W_S
+/* 3226 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3240
+/* 3231 */ MCD::OPC_CheckPredicate, 5, 195, 2, 0, // Skip to: 3943
+/* 3236 */ MCD::OPC_Decode, 142, 3, 55, // Opcode: FCVT_WU_S
+/* 3240 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3254
+/* 3245 */ MCD::OPC_CheckPredicate, 11, 181, 2, 0, // Skip to: 3943
+/* 3250 */ MCD::OPC_Decode, 135, 3, 55, // Opcode: FCVT_L_S
+/* 3254 */ MCD::OPC_FilterValue, 3, 172, 2, 0, // Skip to: 3943
+/* 3259 */ MCD::OPC_CheckPredicate, 11, 167, 2, 0, // Skip to: 3943
+/* 3264 */ MCD::OPC_Decode, 133, 3, 55, // Opcode: FCVT_LU_S
+/* 3268 */ MCD::OPC_FilterValue, 97, 59, 0, 0, // Skip to: 3332
+/* 3273 */ MCD::OPC_ExtractField, 20, 5, // Inst{24-20} ...
+/* 3276 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3290
+/* 3281 */ MCD::OPC_CheckPredicate, 6, 145, 2, 0, // Skip to: 3943
+/* 3286 */ MCD::OPC_Decode, 143, 3, 56, // Opcode: FCVT_W_D
+/* 3290 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3304
+/* 3295 */ MCD::OPC_CheckPredicate, 6, 131, 2, 0, // Skip to: 3943
+/* 3300 */ MCD::OPC_Decode, 141, 3, 56, // Opcode: FCVT_WU_D
+/* 3304 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3318
+/* 3309 */ MCD::OPC_CheckPredicate, 12, 117, 2, 0, // Skip to: 3943
+/* 3314 */ MCD::OPC_Decode, 134, 3, 56, // Opcode: FCVT_L_D
+/* 3318 */ MCD::OPC_FilterValue, 3, 108, 2, 0, // Skip to: 3943
+/* 3323 */ MCD::OPC_CheckPredicate, 12, 103, 2, 0, // Skip to: 3943
+/* 3328 */ MCD::OPC_Decode, 132, 3, 56, // Opcode: FCVT_LU_D
+/* 3332 */ MCD::OPC_FilterValue, 104, 59, 0, 0, // Skip to: 3396
+/* 3337 */ MCD::OPC_ExtractField, 20, 5, // Inst{24-20} ...
+/* 3340 */ MCD::OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3354
+/* 3345 */ MCD::OPC_CheckPredicate, 5, 81, 2, 0, // Skip to: 3943
+/* 3350 */ MCD::OPC_Decode, 139, 3, 57, // Opcode: FCVT_S_W
+/* 3354 */ MCD::OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3368
+/* 3359 */ MCD::OPC_CheckPredicate, 5, 67, 2, 0, // Skip to: 3943
+/* 3364 */ MCD::OPC_Decode, 140, 3, 57, // Opcode: FCVT_S_WU
+/* 3368 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3382
+/* 3373 */ MCD::OPC_CheckPredicate, 11, 53, 2, 0, // Skip to: 3943
+/* 3378 */ MCD::OPC_Decode, 137, 3, 57, // Opcode: FCVT_S_L
+/* 3382 */ MCD::OPC_FilterValue, 3, 44, 2, 0, // Skip to: 3943
+/* 3387 */ MCD::OPC_CheckPredicate, 11, 39, 2, 0, // Skip to: 3943
+/* 3392 */ MCD::OPC_Decode, 138, 3, 57, // Opcode: FCVT_S_LU
+/* 3396 */ MCD::OPC_FilterValue, 105, 73, 0, 0, // Skip to: 3474
+/* 3401 */ MCD::OPC_ExtractField, 20, 5, // Inst{24-20} ...
+/* 3404 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3425
+/* 3409 */ MCD::OPC_CheckPredicate, 6, 17, 2, 0, // Skip to: 3943
+/* 3414 */ MCD::OPC_CheckField, 12, 3, 0, 10, 2, 0, // Skip to: 3943
+/* 3421 */ MCD::OPC_Decode, 130, 3, 58, // Opcode: FCVT_D_W
+/* 3425 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3446
+/* 3430 */ MCD::OPC_CheckPredicate, 6, 252, 1, 0, // Skip to: 3943
+/* 3435 */ MCD::OPC_CheckField, 12, 3, 0, 245, 1, 0, // Skip to: 3943
+/* 3442 */ MCD::OPC_Decode, 131, 3, 58, // Opcode: FCVT_D_WU
+/* 3446 */ MCD::OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3460
+/* 3451 */ MCD::OPC_CheckPredicate, 12, 231, 1, 0, // Skip to: 3943
+/* 3456 */ MCD::OPC_Decode, 255, 2, 59, // Opcode: FCVT_D_L
+/* 3460 */ MCD::OPC_FilterValue, 3, 222, 1, 0, // Skip to: 3943
+/* 3465 */ MCD::OPC_CheckPredicate, 12, 217, 1, 0, // Skip to: 3943
+/* 3470 */ MCD::OPC_Decode, 128, 3, 59, // Opcode: FCVT_D_LU
+/* 3474 */ MCD::OPC_FilterValue, 112, 45, 0, 0, // Skip to: 3524
+/* 3479 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 3482 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3503
+/* 3487 */ MCD::OPC_CheckPredicate, 5, 195, 1, 0, // Skip to: 3943
+/* 3492 */ MCD::OPC_CheckField, 20, 5, 0, 188, 1, 0, // Skip to: 3943
+/* 3499 */ MCD::OPC_Decode, 171, 3, 60, // Opcode: FMV_X_W
+/* 3503 */ MCD::OPC_FilterValue, 1, 179, 1, 0, // Skip to: 3943
+/* 3508 */ MCD::OPC_CheckPredicate, 5, 174, 1, 0, // Skip to: 3943
+/* 3513 */ MCD::OPC_CheckField, 20, 5, 0, 167, 1, 0, // Skip to: 3943
+/* 3520 */ MCD::OPC_Decode, 254, 2, 60, // Opcode: FCLASS_S
+/* 3524 */ MCD::OPC_FilterValue, 113, 45, 0, 0, // Skip to: 3574
+/* 3529 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 3532 */ MCD::OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3553
+/* 3537 */ MCD::OPC_CheckPredicate, 12, 145, 1, 0, // Skip to: 3943
+/* 3542 */ MCD::OPC_CheckField, 20, 5, 0, 138, 1, 0, // Skip to: 3943
+/* 3549 */ MCD::OPC_Decode, 170, 3, 61, // Opcode: FMV_X_D
+/* 3553 */ MCD::OPC_FilterValue, 1, 129, 1, 0, // Skip to: 3943
+/* 3558 */ MCD::OPC_CheckPredicate, 6, 124, 1, 0, // Skip to: 3943
+/* 3563 */ MCD::OPC_CheckField, 20, 5, 0, 117, 1, 0, // Skip to: 3943
+/* 3570 */ MCD::OPC_Decode, 253, 2, 61, // Opcode: FCLASS_D
+/* 3574 */ MCD::OPC_FilterValue, 120, 23, 0, 0, // Skip to: 3602
+/* 3579 */ MCD::OPC_CheckPredicate, 5, 103, 1, 0, // Skip to: 3943
+/* 3584 */ MCD::OPC_CheckField, 20, 5, 0, 96, 1, 0, // Skip to: 3943
+/* 3591 */ MCD::OPC_CheckField, 12, 3, 0, 89, 1, 0, // Skip to: 3943
+/* 3598 */ MCD::OPC_Decode, 169, 3, 62, // Opcode: FMV_W_X
+/* 3602 */ MCD::OPC_FilterValue, 121, 80, 1, 0, // Skip to: 3943
+/* 3607 */ MCD::OPC_CheckPredicate, 12, 75, 1, 0, // Skip to: 3943
+/* 3612 */ MCD::OPC_CheckField, 20, 5, 0, 68, 1, 0, // Skip to: 3943
+/* 3619 */ MCD::OPC_CheckField, 12, 3, 0, 61, 1, 0, // Skip to: 3943
+/* 3626 */ MCD::OPC_Decode, 168, 3, 58, // Opcode: FMV_D_X
+/* 3630 */ MCD::OPC_FilterValue, 99, 57, 0, 0, // Skip to: 3692
+/* 3635 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 3638 */ MCD::OPC_FilterValue, 0, 4, 0, 0, // Skip to: 3647
+/* 3643 */ MCD::OPC_Decode, 178, 2, 63, // Opcode: BEQ
+/* 3647 */ MCD::OPC_FilterValue, 1, 4, 0, 0, // Skip to: 3656
+/* 3652 */ MCD::OPC_Decode, 183, 2, 63, // Opcode: BNE
+/* 3656 */ MCD::OPC_FilterValue, 4, 4, 0, 0, // Skip to: 3665
+/* 3661 */ MCD::OPC_Decode, 181, 2, 63, // Opcode: BLT
+/* 3665 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 3674
+/* 3670 */ MCD::OPC_Decode, 179, 2, 63, // Opcode: BGE
+/* 3674 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 3683
+/* 3679 */ MCD::OPC_Decode, 182, 2, 63, // Opcode: BLTU
+/* 3683 */ MCD::OPC_FilterValue, 7, 255, 0, 0, // Skip to: 3943
+/* 3688 */ MCD::OPC_Decode, 180, 2, 63, // Opcode: BGEU
+/* 3692 */ MCD::OPC_FilterValue, 103, 11, 0, 0, // Skip to: 3708
+/* 3697 */ MCD::OPC_CheckField, 12, 3, 0, 239, 0, 0, // Skip to: 3943
+/* 3704 */ MCD::OPC_Decode, 189, 3, 31, // Opcode: JALR
+/* 3708 */ MCD::OPC_FilterValue, 111, 4, 0, 0, // Skip to: 3717
+/* 3713 */ MCD::OPC_Decode, 188, 3, 64, // Opcode: JAL
+/* 3717 */ MCD::OPC_FilterValue, 115, 221, 0, 0, // Skip to: 3943
+/* 3722 */ MCD::OPC_ExtractField, 12, 3, // Inst{14-12} ...
+/* 3725 */ MCD::OPC_FilterValue, 0, 139, 0, 0, // Skip to: 3869
+/* 3730 */ MCD::OPC_ExtractField, 25, 7, // Inst{31-25} ...
+/* 3733 */ MCD::OPC_FilterValue, 0, 51, 0, 0, // Skip to: 3789
+/* 3738 */ MCD::OPC_ExtractField, 15, 10, // Inst{24-15} ...
+/* 3741 */ MCD::OPC_FilterValue, 0, 11, 0, 0, // Skip to: 3757
+/* 3746 */ MCD::OPC_CheckField, 7, 5, 0, 190, 0, 0, // Skip to: 3943
+/* 3753 */ MCD::OPC_Decode, 250, 2, 0, // Opcode: ECALL
+/* 3757 */ MCD::OPC_FilterValue, 32, 11, 0, 0, // Skip to: 3773
+/* 3762 */ MCD::OPC_CheckField, 7, 5, 0, 174, 0, 0, // Skip to: 3943
+/* 3769 */ MCD::OPC_Decode, 249, 2, 0, // Opcode: EBREAK
+/* 3773 */ MCD::OPC_FilterValue, 64, 165, 0, 0, // Skip to: 3943
+/* 3778 */ MCD::OPC_CheckField, 7, 5, 0, 158, 0, 0, // Skip to: 3943
+/* 3785 */ MCD::OPC_Decode, 251, 3, 0, // Opcode: URET
+/* 3789 */ MCD::OPC_FilterValue, 8, 36, 0, 0, // Skip to: 3830
+/* 3794 */ MCD::OPC_ExtractField, 15, 10, // Inst{24-15} ...
+/* 3797 */ MCD::OPC_FilterValue, 64, 11, 0, 0, // Skip to: 3813
+/* 3802 */ MCD::OPC_CheckField, 7, 5, 0, 134, 0, 0, // Skip to: 3943
+/* 3809 */ MCD::OPC_Decode, 242, 3, 0, // Opcode: SRET
+/* 3813 */ MCD::OPC_FilterValue, 160, 1, 124, 0, 0, // Skip to: 3943
+/* 3819 */ MCD::OPC_CheckField, 7, 5, 0, 117, 0, 0, // Skip to: 3943
+/* 3826 */ MCD::OPC_Decode, 252, 3, 0, // Opcode: WFI
+/* 3830 */ MCD::OPC_FilterValue, 9, 11, 0, 0, // Skip to: 3846
+/* 3835 */ MCD::OPC_CheckField, 7, 5, 0, 101, 0, 0, // Skip to: 3943
+/* 3842 */ MCD::OPC_Decode, 228, 3, 65, // Opcode: SFENCE_VMA
+/* 3846 */ MCD::OPC_FilterValue, 24, 92, 0, 0, // Skip to: 3943
+/* 3851 */ MCD::OPC_CheckField, 15, 10, 64, 85, 0, 0, // Skip to: 3943
+/* 3858 */ MCD::OPC_CheckField, 7, 5, 0, 78, 0, 0, // Skip to: 3943
+/* 3865 */ MCD::OPC_Decode, 206, 3, 0, // Opcode: MRET
+/* 3869 */ MCD::OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3898
+/* 3874 */ MCD::OPC_CheckField, 15, 17, 128, 128, 6, 11, 0, 0, // Skip to: 3894
+/* 3883 */ MCD::OPC_CheckField, 7, 5, 0, 4, 0, 0, // Skip to: 3894
+/* 3890 */ MCD::OPC_Decode, 250, 3, 0, // Opcode: UNIMP
+/* 3894 */ MCD::OPC_Decode, 188, 2, 66, // Opcode: CSRRW
+/* 3898 */ MCD::OPC_FilterValue, 2, 4, 0, 0, // Skip to: 3907
+/* 3903 */ MCD::OPC_Decode, 186, 2, 66, // Opcode: CSRRS
+/* 3907 */ MCD::OPC_FilterValue, 3, 4, 0, 0, // Skip to: 3916
+/* 3912 */ MCD::OPC_Decode, 184, 2, 66, // Opcode: CSRRC
+/* 3916 */ MCD::OPC_FilterValue, 5, 4, 0, 0, // Skip to: 3925
+/* 3921 */ MCD::OPC_Decode, 189, 2, 67, // Opcode: CSRRWI
+/* 3925 */ MCD::OPC_FilterValue, 6, 4, 0, 0, // Skip to: 3934
+/* 3930 */ MCD::OPC_Decode, 187, 2, 67, // Opcode: CSRRSI
+/* 3934 */ MCD::OPC_FilterValue, 7, 4, 0, 0, // Skip to: 3943
+/* 3939 */ MCD::OPC_Decode, 185, 2, 67, // Opcode: CSRRCI
+/* 3943 */ MCD::OPC_Fail,
+ 0
+};
+
+static const uint8_t DecoderTableRISCV32Only_16[] = {
+/* 0 */ MCD::OPC_ExtractField, 0, 2, // Inst{1-0} ...
+/* 3 */ MCD::OPC_FilterValue, 0, 31, 0, 0, // Skip to: 39
+/* 8 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 11 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25
+/* 16 */ MCD::OPC_CheckPredicate, 13, 75, 0, 0, // Skip to: 96
+/* 21 */ MCD::OPC_Decode, 207, 2, 68, // Opcode: C_FLW
+/* 25 */ MCD::OPC_FilterValue, 7, 66, 0, 0, // Skip to: 96
+/* 30 */ MCD::OPC_CheckPredicate, 13, 61, 0, 0, // Skip to: 96
+/* 35 */ MCD::OPC_Decode, 211, 2, 68, // Opcode: C_FSW
+/* 39 */ MCD::OPC_FilterValue, 1, 16, 0, 0, // Skip to: 60
+/* 44 */ MCD::OPC_CheckPredicate, 14, 47, 0, 0, // Skip to: 96
+/* 49 */ MCD::OPC_CheckField, 13, 3, 1, 40, 0, 0, // Skip to: 96
+/* 56 */ MCD::OPC_Decode, 214, 2, 26, // Opcode: C_JAL
+/* 60 */ MCD::OPC_FilterValue, 2, 31, 0, 0, // Skip to: 96
+/* 65 */ MCD::OPC_ExtractField, 13, 3, // Inst{15-13} ...
+/* 68 */ MCD::OPC_FilterValue, 3, 9, 0, 0, // Skip to: 82
+/* 73 */ MCD::OPC_CheckPredicate, 13, 18, 0, 0, // Skip to: 96
+/* 78 */ MCD::OPC_Decode, 208, 2, 69, // Opcode: C_FLWSP
+/* 82 */ MCD::OPC_FilterValue, 7, 9, 0, 0, // Skip to: 96
+/* 87 */ MCD::OPC_CheckPredicate, 13, 4, 0, 0, // Skip to: 96
+/* 92 */ MCD::OPC_Decode, 212, 2, 70, // Opcode: C_FSWSP
+/* 96 */ MCD::OPC_Fail,
+ 0
+};
+
+static bool checkDecoderPredicate(unsigned Idx, const FeatureBitset& Bits) {
+ switch (Idx) {
+ default: llvm_unreachable("Invalid index!");
+ case 0:
+ return (Bits[RISCV::FeatureStdExtC]);
+ case 1:
+ return (Bits[RISCV::FeatureStdExtC] && Bits[RISCV::FeatureRVCHints]);
+ case 2:
+ return (Bits[RISCV::FeatureStdExtC] && Bits[RISCV::FeatureStdExtD]);
+ case 3:
+ return (Bits[RISCV::FeatureStdExtC] && Bits[RISCV::Feature64Bit]);
+ case 4:
+ return (Bits[RISCV::Feature64Bit]);
+ case 5:
+ return (Bits[RISCV::FeatureStdExtF]);
+ case 6:
+ return (Bits[RISCV::FeatureStdExtD]);
+ case 7:
+ return (Bits[RISCV::FeatureStdExtA]);
+ case 8:
+ return (Bits[RISCV::FeatureStdExtA] && Bits[RISCV::Feature64Bit]);
+ case 9:
+ return (Bits[RISCV::FeatureStdExtM]);
+ case 10:
+ return (Bits[RISCV::FeatureStdExtM] && Bits[RISCV::Feature64Bit]);
+ case 11:
+ return (Bits[RISCV::FeatureStdExtF] && Bits[RISCV::Feature64Bit]);
+ case 12:
+ return (Bits[RISCV::FeatureStdExtD] && Bits[RISCV::Feature64Bit]);
+ case 13:
+ return (Bits[RISCV::FeatureStdExtC] && Bits[RISCV::FeatureStdExtF] && !Bits[RISCV::Feature64Bit]);
+ case 14:
+ return (Bits[RISCV::FeatureStdExtC] && !Bits[RISCV::Feature64Bit]);
+ }
+}
+
+template<typename InsnType>
+static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, InsnType insn, MCInst &MI,
+ uint64_t Address, const void *Decoder, bool &DecodeComplete) {
+ DecodeComplete = true;
+ InsnType tmp;
+ switch (Idx) {
+ default: llvm_unreachable("Invalid index!");
+ case 0:
+ return S;
+ case 1:
+ tmp = fieldFromInstruction(insn, 2, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 5, 1) << 3;
+ tmp |= fieldFromInstruction(insn, 6, 1) << 2;
+ tmp |= fieldFromInstruction(insn, 7, 4) << 6;
+ tmp |= fieldFromInstruction(insn, 11, 2) << 4;
+ if (decodeUImmNonZeroOperand<10>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 2:
+ if (decodeRVCInstrSImm(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 3:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeSImmOperand<6>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 4:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 5:
+ if (decodeRVCInstrRdRs1UImm(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 6:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeUImmOperand<6>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 7:
+ tmp = fieldFromInstruction(insn, 2, 3);
+ if (DecodeFPR64CRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 5, 2) << 6;
+ tmp |= fieldFromInstruction(insn, 10, 3) << 3;
+ if (decodeUImmOperand<8>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 8:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 3) << 6;
+ tmp |= fieldFromInstruction(insn, 5, 2) << 3;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeUImmOperand<9>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 9:
+ tmp = fieldFromInstruction(insn, 2, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 5, 1) << 6;
+ tmp |= fieldFromInstruction(insn, 6, 1) << 2;
+ tmp |= fieldFromInstruction(insn, 10, 3) << 3;
+ if (decodeUImmOperand<7>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 10:
+ if (decodeRVCInstrRdSImm(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 11:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeSImmOperand<6>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 12:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 2) << 6;
+ tmp |= fieldFromInstruction(insn, 4, 3) << 2;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeUImmOperand<8>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 13:
+ tmp = fieldFromInstruction(insn, 2, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 5, 2) << 6;
+ tmp |= fieldFromInstruction(insn, 10, 3) << 3;
+ if (decodeUImmOperand<8>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 14:
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 1) << 5;
+ tmp |= fieldFromInstruction(insn, 3, 2) << 7;
+ tmp |= fieldFromInstruction(insn, 5, 1) << 6;
+ tmp |= fieldFromInstruction(insn, 6, 1) << 4;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 9;
+ if (decodeSImmNonZeroOperand<10>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 15:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0X2RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeCLUIImmOperand(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 16:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 3) << 6;
+ tmp |= fieldFromInstruction(insn, 5, 2) << 3;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeUImmOperand<9>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 17:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 18:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeUImmOperand<6>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 19:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeSImmOperand<6>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 20:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 2, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 21:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 22:
+ if (decodeRVCInstrRdRs2(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 23:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 2, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 24:
+ if (decodeRVCInstrRdRs1Rs2(MI, insn, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 25:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 2, 5);
+ if (DecodeGPRNoX0RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 26:
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 1) << 4;
+ tmp |= fieldFromInstruction(insn, 3, 3) << 0;
+ tmp |= fieldFromInstruction(insn, 6, 1) << 6;
+ tmp |= fieldFromInstruction(insn, 7, 1) << 5;
+ tmp |= fieldFromInstruction(insn, 8, 1) << 9;
+ tmp |= fieldFromInstruction(insn, 9, 2) << 7;
+ tmp |= fieldFromInstruction(insn, 11, 1) << 3;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 10;
+ if (decodeSImmOperandAndLsl1<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 27:
+ tmp = fieldFromInstruction(insn, 2, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 7, 3) << 6;
+ tmp |= fieldFromInstruction(insn, 10, 3) << 3;
+ if (decodeUImmOperand<9>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 28:
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 1) << 4;
+ tmp |= fieldFromInstruction(insn, 3, 2) << 0;
+ tmp |= fieldFromInstruction(insn, 5, 2) << 5;
+ tmp |= fieldFromInstruction(insn, 10, 2) << 2;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 7;
+ if (decodeSImmOperandAndLsl1<9>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 29:
+ tmp = fieldFromInstruction(insn, 2, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 7, 2) << 6;
+ tmp |= fieldFromInstruction(insn, 9, 4) << 2;
+ if (decodeUImmOperand<8>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 30:
+ tmp = fieldFromInstruction(insn, 2, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 7, 3) << 6;
+ tmp |= fieldFromInstruction(insn, 10, 3) << 3;
+ if (decodeUImmOperand<9>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 31:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 12);
+ if (decodeSImmOperand<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 32:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 12);
+ if (decodeSImmOperand<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 33:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 12);
+ if (decodeSImmOperand<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 34:
+ tmp = fieldFromInstruction(insn, 24, 4);
+ if (decodeUImmOperand<4>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 4);
+ if (decodeUImmOperand<4>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 35:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 6);
+ if (decodeUImmOperand<6>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 36:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 20);
+ if (decodeUImmOperand<20>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 37:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (decodeUImmOperand<5>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 38:
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 7, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 25, 7) << 5;
+ if (decodeSImmOperand<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 39:
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 7, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 25, 7) << 5;
+ if (decodeSImmOperand<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 40:
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 7, 5) << 0;
+ tmp |= fieldFromInstruction(insn, 25, 7) << 5;
+ if (decodeSImmOperand<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 41:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 42:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 43:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 27, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 44:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 27, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 45:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 46:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 47:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 48:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 49:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 50:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 51:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 52:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 53:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 54:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 55:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 56:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 57:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 58:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 59:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 12, 3);
+ if (decodeFRMArg(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 60:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 61:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeFPR64RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 62:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 63:
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 7, 1) << 10;
+ tmp |= fieldFromInstruction(insn, 8, 4) << 0;
+ tmp |= fieldFromInstruction(insn, 25, 6) << 4;
+ tmp |= fieldFromInstruction(insn, 31, 1) << 11;
+ if (decodeSImmOperandAndLsl1<13>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 64:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 12, 8) << 11;
+ tmp |= fieldFromInstruction(insn, 20, 1) << 10;
+ tmp |= fieldFromInstruction(insn, 21, 10) << 0;
+ tmp |= fieldFromInstruction(insn, 31, 1) << 19;
+ if (decodeSImmOperandAndLsl1<21>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 65:
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 66:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 12);
+ if (decodeUImmOperand<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 67:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeGPRRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 20, 12);
+ if (decodeUImmOperand<12>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 15, 5);
+ if (decodeUImmOperand<5>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 68:
+ tmp = fieldFromInstruction(insn, 2, 3);
+ if (DecodeFPR32CRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = fieldFromInstruction(insn, 7, 3);
+ if (DecodeGPRCRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 5, 1) << 6;
+ tmp |= fieldFromInstruction(insn, 6, 1) << 2;
+ tmp |= fieldFromInstruction(insn, 10, 3) << 3;
+ if (decodeUImmOperand<7>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 69:
+ tmp = fieldFromInstruction(insn, 7, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 2, 2) << 6;
+ tmp |= fieldFromInstruction(insn, 4, 3) << 2;
+ tmp |= fieldFromInstruction(insn, 12, 1) << 5;
+ if (decodeUImmOperand<8>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ case 70:
+ tmp = fieldFromInstruction(insn, 2, 5);
+ if (DecodeFPR32RegisterClass(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ tmp = 0x0;
+ tmp |= fieldFromInstruction(insn, 7, 2) << 6;
+ tmp |= fieldFromInstruction(insn, 9, 4) << 2;
+ if (decodeUImmOperand<8>(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { return MCDisassembler::Fail; }
+ return S;
+ }
+}
+
+template<typename InsnType>
+static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,
+ InsnType insn, uint64_t Address,
+ const void *DisAsm,
+ const MCSubtargetInfo &STI) {
+ const FeatureBitset& Bits = STI.getFeatureBits();
+
+ const uint8_t *Ptr = DecodeTable;
+ InsnType CurFieldValue = 0;
+ DecodeStatus S = MCDisassembler::Success;
+ while (true) {
+ ptrdiff_t Loc = Ptr - DecodeTable;
+ switch (*Ptr) {
+ default:
+ errs() << Loc << ": Unexpected decode table opcode!\n";
+ return MCDisassembler::Fail;
+ case MCD::OPC_ExtractField: {
+ unsigned Start = *++Ptr;
+ unsigned Len = *++Ptr;
+ ++Ptr;
+ CurFieldValue = fieldFromInstruction(insn, Start, Len);
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_ExtractField(" << Start << ", "
+ << Len << "): " << CurFieldValue << "\n");
+ break;
+ }
+ case MCD::OPC_FilterValue: {
+ // Decode the field value.
+ unsigned Len;
+ InsnType Val = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // Perform the filter operation.
+ if (Val != CurFieldValue)
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_FilterValue(" << Val << ", " << NumToSkip
+ << "): " << ((Val != CurFieldValue) ? "FAIL:" : "PASS:")
+ << " continuing at " << (Ptr - DecodeTable) << "\n");
+
+ break;
+ }
+ case MCD::OPC_CheckField: {
+ unsigned Start = *++Ptr;
+ unsigned Len = *++Ptr;
+ InsnType FieldValue = fieldFromInstruction(insn, Start, Len);
+ // Decode the field value.
+ InsnType ExpectedValue = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // If the actual and expected values don't match, skip.
+ if (ExpectedValue != FieldValue)
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckField(" << Start << ", "
+ << Len << ", " << ExpectedValue << ", " << NumToSkip
+ << "): FieldValue = " << FieldValue << ", ExpectedValue = "
+ << ExpectedValue << ": "
+ << ((ExpectedValue == FieldValue) ? "PASS\n" : "FAIL\n"));
+ break;
+ }
+ case MCD::OPC_CheckPredicate: {
+ unsigned Len;
+ // Decode the Predicate Index value.
+ unsigned PIdx = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+ // Check the predicate.
+ bool Pred;
+ if (!(Pred = checkDecoderPredicate(PIdx, Bits)))
+ Ptr += NumToSkip;
+ (void)Pred;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_CheckPredicate(" << PIdx << "): "
+ << (Pred ? "PASS\n" : "FAIL\n"));
+
+ break;
+ }
+ case MCD::OPC_Decode: {
+ unsigned Len;
+ // Decode the Opcode value.
+ unsigned Opc = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+
+ MI.clear();
+ MI.setOpcode(Opc);
+ bool DecodeComplete;
+ S = decodeToMCInst(S, DecodeIdx, insn, MI, Address, DisAsm, DecodeComplete);
+ assert(DecodeComplete);
+
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_Decode: opcode " << Opc
+ << ", using decoder " << DecodeIdx << ": "
+ << (S != MCDisassembler::Fail ? "PASS" : "FAIL") << "\n");
+ return S;
+ }
+ case MCD::OPC_TryDecode: {
+ unsigned Len;
+ // Decode the Opcode value.
+ unsigned Opc = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ unsigned DecodeIdx = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ // NumToSkip is a plain 24-bit integer.
+ unsigned NumToSkip = *Ptr++;
+ NumToSkip |= (*Ptr++) << 8;
+ NumToSkip |= (*Ptr++) << 16;
+
+ // Perform the decode operation.
+ MCInst TmpMI;
+ TmpMI.setOpcode(Opc);
+ bool DecodeComplete;
+ S = decodeToMCInst(S, DecodeIdx, insn, TmpMI, Address, DisAsm, DecodeComplete);
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_TryDecode: opcode " << Opc
+ << ", using decoder " << DecodeIdx << ": ");
+
+ if (DecodeComplete) {
+ // Decoding complete.
+ LLVM_DEBUG(dbgs() << (S != MCDisassembler::Fail ? "PASS" : "FAIL") << "\n");
+ MI = TmpMI;
+ return S;
+ } else {
+ assert(S == MCDisassembler::Fail);
+ // If the decoding was incomplete, skip.
+ Ptr += NumToSkip;
+ LLVM_DEBUG(dbgs() << "FAIL: continuing at " << (Ptr - DecodeTable) << "\n");
+ // Reset decode status. This also drops a SoftFail status that could be
+ // set before the decode attempt.
+ S = MCDisassembler::Success;
+ }
+ break;
+ }
+ case MCD::OPC_SoftFail: {
+ // Decode the mask values.
+ unsigned Len;
+ InsnType PositiveMask = decodeULEB128(++Ptr, &Len);
+ Ptr += Len;
+ InsnType NegativeMask = decodeULEB128(Ptr, &Len);
+ Ptr += Len;
+ bool Fail = (insn & PositiveMask) || (~insn & NegativeMask);
+ if (Fail)
+ S = MCDisassembler::SoftFail;
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_SoftFail: " << (Fail ? "FAIL\n":"PASS\n"));
+ break;
+ }
+ case MCD::OPC_Fail: {
+ LLVM_DEBUG(dbgs() << Loc << ": OPC_Fail\n");
+ return MCDisassembler::Fail;
+ }
+ }
+ }
+ llvm_unreachable("bogosity detected in disassembler state machine!");
+}
+
+
+} // end namespace llvm
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenGlobalISel.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenGlobalISel.inc
new file mode 100644
index 0000000..8b47216
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenGlobalISel.inc
@@ -0,0 +1,12519 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Global Instruction Selector for the RISCV target *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_GLOBALISEL_PREDICATE_BITSET
+const unsigned MAX_SUBTARGET_PREDICATES = 6;
+using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
+#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
+
+#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
+ mutable MatcherState State;
+ typedef ComplexRendererFns(RISCVInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
+ typedef void(RISCVInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&, int) const;
+ const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
+ static RISCVInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
+ static RISCVInstructionSelector::CustomRendererFn CustomRenderers[];
+ bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
+ bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
+ bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
+ const int64_t *getMatchTable() const override;
+ bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override;
+#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
+
+#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
+, State(0),
+ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
+#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
+
+#ifdef GET_GLOBALISEL_IMPL
+// Bits for subtarget features that participate in instruction matching.
+enum SubtargetFeatureBits : uint8_t {
+ Feature_HasStdExtMBit = 4,
+ Feature_HasStdExtABit = 5,
+ Feature_HasStdExtFBit = 0,
+ Feature_HasStdExtDBit = 1,
+ Feature_IsRV64Bit = 3,
+ Feature_IsRV32Bit = 2,
+};
+
+PredicateBitset RISCVInstructionSelector::
+computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const {
+ PredicateBitset Features;
+ if (Subtarget->hasStdExtM())
+ Features.set(Feature_HasStdExtMBit);
+ if (Subtarget->hasStdExtA())
+ Features.set(Feature_HasStdExtABit);
+ if (Subtarget->hasStdExtF())
+ Features.set(Feature_HasStdExtFBit);
+ if (Subtarget->hasStdExtD())
+ Features.set(Feature_HasStdExtDBit);
+ if (Subtarget->is64Bit())
+ Features.set(Feature_IsRV64Bit);
+ if (!Subtarget->is64Bit())
+ Features.set(Feature_IsRV32Bit);
+ return Features;
+}
+
+void RISCVInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
+ AvailableFunctionFeatures = computeAvailableFunctionFeatures((const RISCVSubtarget*)&MF.getSubtarget(), &MF);
+}
+PredicateBitset RISCVInstructionSelector::
+computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget, const MachineFunction *MF) const {
+ PredicateBitset Features;
+ return Features;
+}
+
+// LLT Objects.
+enum {
+ GILLT_s32,
+ GILLT_s64,
+};
+const static size_t NumTypeObjects = 2;
+const static LLT TypeObjects[] = {
+ LLT::scalar(32),
+ LLT::scalar(64),
+};
+
+// Feature bitsets.
+enum {
+ GIFBS_Invalid,
+ GIFBS_HasStdExtA,
+ GIFBS_HasStdExtD,
+ GIFBS_HasStdExtF,
+ GIFBS_HasStdExtM,
+ GIFBS_IsRV32,
+ GIFBS_IsRV64,
+ GIFBS_HasStdExtA_IsRV64,
+ GIFBS_HasStdExtD_IsRV32,
+ GIFBS_HasStdExtD_IsRV64,
+};
+const static PredicateBitset FeatureBitsets[] {
+ {}, // GIFBS_Invalid
+ {Feature_HasStdExtABit, },
+ {Feature_HasStdExtDBit, },
+ {Feature_HasStdExtFBit, },
+ {Feature_HasStdExtMBit, },
+ {Feature_IsRV32Bit, },
+ {Feature_IsRV64Bit, },
+ {Feature_HasStdExtABit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtDBit, Feature_IsRV32Bit, },
+ {Feature_HasStdExtDBit, Feature_IsRV64Bit, },
+};
+
+// ComplexPattern predicates.
+enum {
+ GICP_Invalid,
+};
+// See constructor for table contents
+
+// PatFrag predicates.
+enum {
+ GIPFP_I64_Predicate_c_lui_imm = GIPFP_I64_Invalid + 1,
+ GIPFP_I64_Predicate_immbottomxlenset,
+ GIPFP_I64_Predicate_immzero,
+ GIPFP_I64_Predicate_simm10_lsb0000nonzero,
+ GIPFP_I64_Predicate_simm12,
+ GIPFP_I64_Predicate_simm12_lsb0,
+ GIPFP_I64_Predicate_simm32,
+ GIPFP_I64_Predicate_simm32hi20,
+ GIPFP_I64_Predicate_simm6,
+ GIPFP_I64_Predicate_simm6nonzero,
+ GIPFP_I64_Predicate_simm9_lsb0,
+ GIPFP_I64_Predicate_uimm10_lsb00nonzero,
+ GIPFP_I64_Predicate_uimm5,
+ GIPFP_I64_Predicate_uimm7_lsb00,
+ GIPFP_I64_Predicate_uimm8_lsb00,
+ GIPFP_I64_Predicate_uimm8_lsb000,
+ GIPFP_I64_Predicate_uimm9_lsb000,
+ GIPFP_I64_Predicate_uimmlog2xlen,
+ GIPFP_I64_Predicate_uimmlog2xlennonzero,
+};
+bool RISCVInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
+ switch (PredicateID) {
+ case GIPFP_I64_Predicate_c_lui_imm: {
+ return (Imm != 0) &&
+ (isUInt<5>(Imm) ||
+ (Imm >= 0xfffe0 && Imm <= 0xfffff));
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immbottomxlenset: {
+
+ if (Subtarget->is64Bit())
+ return countTrailingOnes<uint64_t>(Imm) >= 6;
+ return countTrailingOnes<uint64_t>(Imm) >= 5;
+
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_immzero: {
+ return (Imm == 0);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_simm10_lsb0000nonzero: {
+ return (Imm != 0) && isShiftedInt<6, 4>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_simm12: {
+ return isInt<12>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_simm12_lsb0: {
+ return isShiftedInt<11, 1>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_simm32: {
+ return isInt<32>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_simm32hi20: {
+ return isShiftedInt<20, 12>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_simm6: {
+ return isInt<6>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_simm6nonzero: {
+ return (Imm != 0) && isInt<6>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_simm9_lsb0: {
+ return isShiftedInt<8, 1>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_uimm10_lsb00nonzero: {
+ return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_uimm5: {
+ return isUInt<5>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_uimm7_lsb00: {
+ return isShiftedUInt<5, 2>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_uimm8_lsb00: {
+ return isShiftedUInt<6, 2>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_uimm8_lsb000: {
+ return isShiftedUInt<5, 3>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_uimm9_lsb000: {
+ return isShiftedUInt<6, 3>(Imm);
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_uimmlog2xlen: {
+
+ if (Subtarget->is64Bit())
+ return isUInt<6>(Imm);
+ return isUInt<5>(Imm);
+
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ case GIPFP_I64_Predicate_uimmlog2xlennonzero: {
+
+ if (Subtarget->is64Bit())
+ return isUInt<6>(Imm) && (Imm != 0);
+ return isUInt<5>(Imm) && (Imm != 0);
+
+ llvm_unreachable("ImmediateCode should have returned");
+ return false;
+ }
+ }
+ llvm_unreachable("Unknown predicate");
+ return false;
+}
+bool RISCVInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
+ llvm_unreachable("Unknown predicate");
+ return false;
+}
+bool RISCVInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
+ llvm_unreachable("Unknown predicate");
+ return false;
+}
+bool RISCVInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const {
+ const MachineFunction &MF = *MI.getParent()->getParent();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+ (void)MRI;
+ llvm_unreachable("Unknown predicate");
+ return false;
+}
+
+RISCVInstructionSelector::ComplexMatcherMemFn
+RISCVInstructionSelector::ComplexPredicateFns[] = {
+ nullptr, // GICP_Invalid
+};
+
+// Custom renderers.
+enum {
+ GICR_Invalid,
+};
+RISCVInstructionSelector::CustomRendererFn
+RISCVInstructionSelector::CustomRenderers[] = {
+ nullptr, // GICR_Invalid
+};
+
+bool RISCVInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
+ MachineFunction &MF = *I.getParent()->getParent();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ const PredicateBitset AvailableFeatures = getAvailableFeatures();
+ NewMIVector OutMIs;
+ State.MIs.clear();
+ State.MIs.push_back(&I);
+
+ if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
+ return true;
+ }
+
+ return false;
+}
+
+const int64_t *RISCVInstructionSelector::getMatchTable() const {
+ constexpr static int64_t MatchTable0[] = {
+ GIM_SwitchOpcode, /*MI*/0, /*[*/35, 168, /*)*//*default:*//*Label 44*/ 28266,
+ /*TargetOpcode::G_ADD*//*Label 0*/ 138,
+ /*TargetOpcode::G_SUB*//*Label 1*/ 325,
+ /*TargetOpcode::G_MUL*//*Label 2*/ 406,
+ /*TargetOpcode::G_SDIV*//*Label 3*/ 493,
+ /*TargetOpcode::G_UDIV*//*Label 4*/ 580,
+ /*TargetOpcode::G_SREM*//*Label 5*/ 667,
+ /*TargetOpcode::G_UREM*//*Label 6*/ 754,
+ /*TargetOpcode::G_AND*//*Label 7*/ 841,
+ /*TargetOpcode::G_OR*//*Label 8*/ 1166,
+ /*TargetOpcode::G_XOR*//*Label 9*/ 1353, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_BITCAST*//*Label 10*/ 1540, 0, 0,
+ /*TargetOpcode::G_READCYCLECOUNTER*//*Label 11*/ 1827,
+ /*TargetOpcode::G_LOAD*//*Label 12*/ 1918,
+ /*TargetOpcode::G_SEXTLOAD*//*Label 13*/ 6036,
+ /*TargetOpcode::G_ZEXTLOAD*//*Label 14*/ 7130, 0, 0, 0,
+ /*TargetOpcode::G_STORE*//*Label 15*/ 8224, 0, 0, 0,
+ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 16*/ 9563,
+ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 17*/ 10608,
+ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 18*/ 11653,
+ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 19*/ 13808, 0,
+ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 20*/ 14853,
+ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 21*/ 15898,
+ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 22*/ 16943,
+ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 23*/ 17988,
+ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 24*/ 19033,
+ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 25*/ 20078, 0, 0,
+ /*TargetOpcode::G_FENCE*//*Label 26*/ 21123, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_CONSTANT*//*Label 27*/ 21392, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_SHL*//*Label 28*/ 21483,
+ /*TargetOpcode::G_LSHR*//*Label 29*/ 21835,
+ /*TargetOpcode::G_ASHR*//*Label 30*/ 22187,
+ /*TargetOpcode::G_ICMP*//*Label 31*/ 22539,
+ /*TargetOpcode::G_FCMP*//*Label 32*/ 24755, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_UMULH*//*Label 33*/ 25936,
+ /*TargetOpcode::G_SMULH*//*Label 34*/ 26023, 0, 0, 0,
+ /*TargetOpcode::G_FMA*//*Label 35*/ 26110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_FPEXT*//*Label 36*/ 27245,
+ /*TargetOpcode::G_FPTRUNC*//*Label 37*/ 27273,
+ /*TargetOpcode::G_FPTOSI*//*Label 38*/ 27362,
+ /*TargetOpcode::G_FPTOUI*//*Label 39*/ 27541,
+ /*TargetOpcode::G_SITOFP*//*Label 40*/ 27720,
+ /*TargetOpcode::G_UITOFP*//*Label 41*/ 27897, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_BR*//*Label 42*/ 28074, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ /*TargetOpcode::G_FSQRT*//*Label 43*/ 28087,
+ // Label 0: @138
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 47*/ 324,
+ /*GILLT_s32*//*Label 45*/ 146,
+ /*GILLT_s64*//*Label 46*/ 258,
+ // Label 45: @146
+ GIM_Try, /*On fail goto*//*Label 48*/ 257,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 49*/ 197, // Rule ID 35 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 35,
+ GIR_Done,
+ // Label 49: @197
+ GIM_Try, /*On fail goto*//*Label 50*/ 230, // Rule ID 37 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 37,
+ GIR_Done,
+ // Label 50: @230
+ GIM_Try, /*On fail goto*//*Label 51*/ 243, // Rule ID 32 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::ADD,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 32,
+ GIR_Done,
+ // Label 51: @243
+ GIM_Try, /*On fail goto*//*Label 52*/ 256, // Rule ID 34 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::ADD,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 34,
+ GIR_Done,
+ // Label 52: @256
+ GIM_Reject,
+ // Label 48: @257
+ GIM_Reject,
+ // Label 46: @258
+ GIM_Try, /*On fail goto*//*Label 53*/ 323,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 54*/ 309, // Rule ID 36 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 36,
+ GIR_Done,
+ // Label 54: @309
+ GIM_Try, /*On fail goto*//*Label 55*/ 322, // Rule ID 33 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::ADD,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 33,
+ GIR_Done,
+ // Label 55: @322
+ GIM_Reject,
+ // Label 53: @323
+ GIM_Reject,
+ // Label 47: @324
+ GIM_Reject,
+ // Label 1: @325
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 58*/ 405,
+ /*GILLT_s32*//*Label 56*/ 333,
+ /*GILLT_s64*//*Label 57*/ 375,
+ // Label 56: @333
+ GIM_Try, /*On fail goto*//*Label 59*/ 374,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 60*/ 364, // Rule ID 38 //
+ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 38,
+ GIR_Done,
+ // Label 60: @364
+ GIM_Try, /*On fail goto*//*Label 61*/ 373, // Rule ID 40 //
+ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 40,
+ GIR_Done,
+ // Label 61: @373
+ GIM_Reject,
+ // Label 59: @374
+ GIM_Reject,
+ // Label 57: @375
+ GIM_Try, /*On fail goto*//*Label 62*/ 404, // Rule ID 39 //
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SUB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 39,
+ GIR_Done,
+ // Label 62: @404
+ GIM_Reject,
+ // Label 58: @405
+ GIM_Reject,
+ // Label 2: @406
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 65*/ 492,
+ /*GILLT_s32*//*Label 63*/ 414,
+ /*GILLT_s64*//*Label 64*/ 460,
+ // Label 63: @414
+ GIM_Try, /*On fail goto*//*Label 66*/ 459,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 67*/ 447, // Rule ID 473 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MUL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 473,
+ GIR_Done,
+ // Label 67: @447
+ GIM_Try, /*On fail goto*//*Label 68*/ 458, // Rule ID 475 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MUL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 475,
+ GIR_Done,
+ // Label 68: @458
+ GIM_Reject,
+ // Label 66: @459
+ GIM_Reject,
+ // Label 64: @460
+ GIM_Try, /*On fail goto*//*Label 69*/ 491, // Rule ID 474 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MUL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MUL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 474,
+ GIR_Done,
+ // Label 69: @491
+ GIM_Reject,
+ // Label 65: @492
+ GIM_Reject,
+ // Label 3: @493
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 72*/ 579,
+ /*GILLT_s32*//*Label 70*/ 501,
+ /*GILLT_s64*//*Label 71*/ 547,
+ // Label 70: @501
+ GIM_Try, /*On fail goto*//*Label 73*/ 546,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 74*/ 534, // Rule ID 482 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 482,
+ GIR_Done,
+ // Label 74: @534
+ GIM_Try, /*On fail goto*//*Label 75*/ 545, // Rule ID 484 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 484,
+ GIR_Done,
+ // Label 75: @545
+ GIM_Reject,
+ // Label 73: @546
+ GIM_Reject,
+ // Label 71: @547
+ GIM_Try, /*On fail goto*//*Label 76*/ 578, // Rule ID 483 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (sdiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (DIV:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIV,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 483,
+ GIR_Done,
+ // Label 76: @578
+ GIM_Reject,
+ // Label 72: @579
+ GIM_Reject,
+ // Label 4: @580
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 79*/ 666,
+ /*GILLT_s32*//*Label 77*/ 588,
+ /*GILLT_s64*//*Label 78*/ 634,
+ // Label 77: @588
+ GIM_Try, /*On fail goto*//*Label 80*/ 633,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 81*/ 621, // Rule ID 485 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIVU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 485,
+ GIR_Done,
+ // Label 81: @621
+ GIM_Try, /*On fail goto*//*Label 82*/ 632, // Rule ID 487 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIVU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 487,
+ GIR_Done,
+ // Label 82: @632
+ GIM_Reject,
+ // Label 80: @633
+ GIM_Reject,
+ // Label 78: @634
+ GIM_Try, /*On fail goto*//*Label 83*/ 665, // Rule ID 486 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (udiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIVU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 486,
+ GIR_Done,
+ // Label 83: @665
+ GIM_Reject,
+ // Label 79: @666
+ GIM_Reject,
+ // Label 5: @667
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 86*/ 753,
+ /*GILLT_s32*//*Label 84*/ 675,
+ /*GILLT_s64*//*Label 85*/ 721,
+ // Label 84: @675
+ GIM_Try, /*On fail goto*//*Label 87*/ 720,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 88*/ 708, // Rule ID 488 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 488,
+ GIR_Done,
+ // Label 88: @708
+ GIM_Try, /*On fail goto*//*Label 89*/ 719, // Rule ID 490 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 490,
+ GIR_Done,
+ // Label 89: @719
+ GIM_Reject,
+ // Label 87: @720
+ GIM_Reject,
+ // Label 85: @721
+ GIM_Try, /*On fail goto*//*Label 90*/ 752, // Rule ID 489 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (srem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (REM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REM,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 489,
+ GIR_Done,
+ // Label 90: @752
+ GIM_Reject,
+ // Label 86: @753
+ GIM_Reject,
+ // Label 6: @754
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 93*/ 840,
+ /*GILLT_s32*//*Label 91*/ 762,
+ /*GILLT_s64*//*Label 92*/ 808,
+ // Label 91: @762
+ GIM_Try, /*On fail goto*//*Label 94*/ 807,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 95*/ 795, // Rule ID 491 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REMU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 491,
+ GIR_Done,
+ // Label 95: @795
+ GIM_Try, /*On fail goto*//*Label 96*/ 806, // Rule ID 493 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REMU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 493,
+ GIR_Done,
+ // Label 96: @806
+ GIM_Reject,
+ // Label 94: @807
+ GIM_Reject,
+ // Label 92: @808
+ GIM_Try, /*On fail goto*//*Label 97*/ 839, // Rule ID 492 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (urem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REMU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 492,
+ GIR_Done,
+ // Label 97: @839
+ GIM_Reject,
+ // Label 93: @840
+ GIM_Reject,
+ // Label 7: @841
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 100*/ 1165,
+ /*GILLT_s32*//*Label 98*/ 849,
+ /*GILLT_s64*//*Label 99*/ 1053,
+ // Label 98: @849
+ GIM_Try, /*On fail goto*//*Label 101*/ 1052,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 102*/ 913, // Rule ID 361 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295,
+ // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }) => (SRLI:{ *:[i32] } (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 32:{ *:[i32] }), 32:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/1, /*Imm*/32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/32,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 361,
+ GIR_Done,
+ // Label 102: @913
+ GIM_Try, /*On fail goto*//*Label 103*/ 959, // Rule ID 363 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295,
+ // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }) => (SRLI:{ *:[i32] } (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 32:{ *:[i32] }), 32:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/1, /*Imm*/32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/32,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 363,
+ GIR_Done,
+ // Label 103: @959
+ GIM_Try, /*On fail goto*//*Label 104*/ 992, // Rule ID 50 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 50,
+ GIR_Done,
+ // Label 104: @992
+ GIM_Try, /*On fail goto*//*Label 105*/ 1025, // Rule ID 52 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 52,
+ GIR_Done,
+ // Label 105: @1025
+ GIM_Try, /*On fail goto*//*Label 106*/ 1038, // Rule ID 47 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 47,
+ GIR_Done,
+ // Label 106: @1038
+ GIM_Try, /*On fail goto*//*Label 107*/ 1051, // Rule ID 49 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 49,
+ GIR_Done,
+ // Label 107: @1051
+ GIM_Reject,
+ // Label 101: @1052
+ GIM_Reject,
+ // Label 99: @1053
+ GIM_Try, /*On fail goto*//*Label 108*/ 1164,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 109*/ 1117, // Rule ID 362 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295,
+ // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }) => (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), 32:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/1, /*Imm*/32,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/32,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 362,
+ GIR_Done,
+ // Label 109: @1117
+ GIM_Try, /*On fail goto*//*Label 110*/ 1150, // Rule ID 51 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) => (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 51,
+ GIR_Done,
+ // Label 110: @1150
+ GIM_Try, /*On fail goto*//*Label 111*/ 1163, // Rule ID 48 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AND:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 48,
+ GIR_Done,
+ // Label 111: @1163
+ GIM_Reject,
+ // Label 108: @1164
+ GIM_Reject,
+ // Label 100: @1165
+ GIM_Reject,
+ // Label 8: @1166
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 114*/ 1352,
+ /*GILLT_s32*//*Label 112*/ 1174,
+ /*GILLT_s64*//*Label 113*/ 1286,
+ // Label 112: @1174
+ GIM_Try, /*On fail goto*//*Label 115*/ 1285,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 116*/ 1225, // Rule ID 44 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 44,
+ GIR_Done,
+ // Label 116: @1225
+ GIM_Try, /*On fail goto*//*Label 117*/ 1258, // Rule ID 46 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 46,
+ GIR_Done,
+ // Label 117: @1258
+ GIM_Try, /*On fail goto*//*Label 118*/ 1271, // Rule ID 41 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::OR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 41,
+ GIR_Done,
+ // Label 118: @1271
+ GIM_Try, /*On fail goto*//*Label 119*/ 1284, // Rule ID 43 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::OR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 43,
+ GIR_Done,
+ // Label 119: @1284
+ GIM_Reject,
+ // Label 115: @1285
+ GIM_Reject,
+ // Label 113: @1286
+ GIM_Try, /*On fail goto*//*Label 120*/ 1351,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 121*/ 1337, // Rule ID 45 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) => (ORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 45,
+ GIR_Done,
+ // Label 121: @1337
+ GIM_Try, /*On fail goto*//*Label 122*/ 1350, // Rule ID 42 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (OR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::OR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 42,
+ GIR_Done,
+ // Label 122: @1350
+ GIM_Reject,
+ // Label 120: @1351
+ GIM_Reject,
+ // Label 114: @1352
+ GIM_Reject,
+ // Label 9: @1353
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 125*/ 1539,
+ /*GILLT_s32*//*Label 123*/ 1361,
+ /*GILLT_s64*//*Label 124*/ 1473,
+ // Label 123: @1361
+ GIM_Try, /*On fail goto*//*Label 126*/ 1472,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 127*/ 1412, // Rule ID 56 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 56,
+ GIR_Done,
+ // Label 127: @1412
+ GIM_Try, /*On fail goto*//*Label 128*/ 1445, // Rule ID 58 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 58,
+ GIR_Done,
+ // Label 128: @1445
+ GIM_Try, /*On fail goto*//*Label 129*/ 1458, // Rule ID 53 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::XOR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 53,
+ GIR_Done,
+ // Label 129: @1458
+ GIM_Try, /*On fail goto*//*Label 130*/ 1471, // Rule ID 55 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::XOR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 55,
+ GIR_Done,
+ // Label 130: @1471
+ GIM_Reject,
+ // Label 126: @1472
+ GIM_Reject,
+ // Label 124: @1473
+ GIM_Try, /*On fail goto*//*Label 131*/ 1538,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 132*/ 1524, // Rule ID 57 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) => (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 57,
+ GIR_Done,
+ // Label 132: @1524
+ GIM_Try, /*On fail goto*//*Label 133*/ 1537, // Rule ID 54 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::XOR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 54,
+ GIR_Done,
+ // Label 133: @1537
+ GIM_Reject,
+ // Label 131: @1538
+ GIM_Reject,
+ // Label 125: @1539
+ GIM_Reject,
+ // Label 10: @1540
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 136*/ 1826,
+ /*GILLT_s32*//*Label 134*/ 1548,
+ /*GILLT_s64*//*Label 135*/ 1710,
+ // Label 134: @1548
+ GIM_Try, /*On fail goto*//*Label 137*/ 1571, // Rule ID 1067 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_W_X,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1067,
+ GIR_Done,
+ // Label 137: @1571
+ GIM_Try, /*On fail goto*//*Label 138*/ 1594, // Rule ID 1068 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (bitconvert:{ *:[f32] } GPR:{ *:[i64] }:$rs1) => (FMV_W_X:{ *:[f32] } GPR:{ *:[i64] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_W_X,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1068,
+ GIR_Done,
+ // Label 138: @1594
+ GIM_Try, /*On fail goto*//*Label 139*/ 1617, // Rule ID 1069 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_W_X,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1069,
+ GIR_Done,
+ // Label 139: @1617
+ GIM_Try, /*On fail goto*//*Label 140*/ 1640, // Rule ID 1070 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1070,
+ GIR_Done,
+ // Label 140: @1640
+ GIM_Try, /*On fail goto*//*Label 141*/ 1663, // Rule ID 1072 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1072,
+ GIR_Done,
+ // Label 141: @1663
+ GIM_Try, /*On fail goto*//*Label 142*/ 1686, // Rule ID 1318 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ // (bitconvert:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FMV_X_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1318,
+ GIR_Done,
+ // Label 142: @1686
+ GIM_Try, /*On fail goto*//*Label 143*/ 1709, // Rule ID 1320 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ // (bitconvert:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FMV_X_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1320,
+ GIR_Done,
+ // Label 143: @1709
+ GIM_Reject,
+ // Label 135: @1710
+ GIM_Try, /*On fail goto*//*Label 144*/ 1733, // Rule ID 1071 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ // (bitconvert:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FMV_X_W:{ *:[i64] } FPR32:{ *:[f32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1071,
+ GIR_Done,
+ // Label 144: @1733
+ GIM_Try, /*On fail goto*//*Label 145*/ 1756, // Rule ID 1315 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (bitconvert:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FMV_D_X:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_D_X,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1315,
+ GIR_Done,
+ // Label 145: @1756
+ GIM_Try, /*On fail goto*//*Label 146*/ 1779, // Rule ID 1316 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (bitconvert:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FMV_D_X:{ *:[f64] } GPR:{ *:[i64] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_D_X,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1316,
+ GIR_Done,
+ // Label 146: @1779
+ GIM_Try, /*On fail goto*//*Label 147*/ 1802, // Rule ID 1317 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (bitconvert:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FMV_D_X:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_D_X,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1317,
+ GIR_Done,
+ // Label 147: @1802
+ GIM_Try, /*On fail goto*//*Label 148*/ 1825, // Rule ID 1319 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FMV_X_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1319,
+ GIR_Done,
+ // Label 148: @1825
+ GIM_Reject,
+ // Label 136: @1826
+ GIM_Reject,
+ // Label 11: @1827
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 151*/ 1917,
+ /*GILLT_s32*//*Label 149*/ 1835,
+ /*GILLT_s64*//*Label 150*/ 1889,
+ // Label 149: @1835
+ GIM_Try, /*On fail goto*//*Label 152*/ 1888,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 153*/ 1864, // Rule ID 468 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ // (readcyclecounter:{ *:[i32] }) => (CSRRS:{ *:[i32] } 3072:{ *:[i32] }, X0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CSRRS,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3072,
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 468,
+ GIR_Done,
+ // Label 153: @1864
+ GIM_Try, /*On fail goto*//*Label 154*/ 1887, // Rule ID 470 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ // (readcyclecounter:{ *:[i32] }) => (CSRRS:{ *:[i32] } 3072:{ *:[i32] }, X0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CSRRS,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3072,
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 470,
+ GIR_Done,
+ // Label 154: @1887
+ GIM_Reject,
+ // Label 152: @1888
+ GIM_Reject,
+ // Label 150: @1889
+ GIM_Try, /*On fail goto*//*Label 155*/ 1916, // Rule ID 469 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // (readcyclecounter:{ *:[i64] }) => (CSRRS:{ *:[i64] } 3072:{ *:[i64] }, X0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CSRRS,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3072,
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 469,
+ GIR_Done,
+ // Label 155: @1916
+ GIM_Reject,
+ // Label 151: @1917
+ GIM_Reject,
+ // Label 12: @1918
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 158*/ 6035,
+ /*GILLT_s32*//*Label 156*/ 1926,
+ /*GILLT_s64*//*Label 157*/ 4542,
+ // Label 156: @1926
+ GIM_Try, /*On fail goto*//*Label 159*/ 2003, // Rule ID 581 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 581,
+ GIR_Done,
+ // Label 159: @2003
+ GIM_Try, /*On fail goto*//*Label 160*/ 2080, // Rule ID 583 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 583,
+ GIR_Done,
+ // Label 160: @2080
+ GIM_Try, /*On fail goto*//*Label 161*/ 2157, // Rule ID 596 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 596,
+ GIR_Done,
+ // Label 161: @2157
+ GIM_Try, /*On fail goto*//*Label 162*/ 2234, // Rule ID 598 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 598,
+ GIR_Done,
+ // Label 162: @2234
+ GIM_Try, /*On fail goto*//*Label 163*/ 2311, // Rule ID 611 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 611,
+ GIR_Done,
+ // Label 163: @2311
+ GIM_Try, /*On fail goto*//*Label 164*/ 2388, // Rule ID 613 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 613,
+ GIR_Done,
+ // Label 164: @2388
+ GIM_Try, /*On fail goto*//*Label 165*/ 2465, // Rule ID 854 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 854,
+ GIR_Done,
+ // Label 165: @2465
+ GIM_Try, /*On fail goto*//*Label 166*/ 2542, // Rule ID 856 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 856,
+ GIR_Done,
+ // Label 166: @2542
+ GIM_Try, /*On fail goto*//*Label 167*/ 2619, // Rule ID 264 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 264,
+ GIR_Done,
+ // Label 167: @2619
+ GIM_Try, /*On fail goto*//*Label 168*/ 2696, // Rule ID 266 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 266,
+ GIR_Done,
+ // Label 168: @2696
+ GIM_Try, /*On fail goto*//*Label 169*/ 2773, // Rule ID 429 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 429,
+ GIR_Done,
+ // Label 169: @2773
+ GIM_Try, /*On fail goto*//*Label 170*/ 2850, // Rule ID 431 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 431,
+ GIR_Done,
+ // Label 170: @2850
+ GIM_Try, /*On fail goto*//*Label 171*/ 2927, // Rule ID 1136 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[f32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1136,
+ GIR_Done,
+ // Label 171: @2927
+ GIM_Try, /*On fail goto*//*Label 172*/ 3004, // Rule ID 1137 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[f32] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1137,
+ GIR_Done,
+ // Label 172: @3004
+ GIM_Try, /*On fail goto*//*Label 173*/ 3081, // Rule ID 1138 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[f32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1138,
+ GIR_Done,
+ // Label 173: @3081
+ GIM_Try, /*On fail goto*//*Label 174*/ 3160, // Rule ID 219 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 219,
+ GIR_Done,
+ // Label 174: @3160
+ GIM_Try, /*On fail goto*//*Label 175*/ 3239, // Rule ID 221 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 221,
+ GIR_Done,
+ // Label 175: @3239
+ GIM_Try, /*On fail goto*//*Label 176*/ 3318, // Rule ID 249 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 249,
+ GIR_Done,
+ // Label 176: @3318
+ GIM_Try, /*On fail goto*//*Label 177*/ 3397, // Rule ID 251 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 251,
+ GIR_Done,
+ // Label 177: @3397
+ GIM_Try, /*On fail goto*//*Label 178*/ 3478, // Rule ID 399 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 399,
+ GIR_Done,
+ // Label 178: @3478
+ GIM_Try, /*On fail goto*//*Label 179*/ 3559, // Rule ID 401 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 401,
+ GIR_Done,
+ // Label 179: @3559
+ GIM_Try, /*On fail goto*//*Label 180*/ 3605, // Rule ID 575 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 575,
+ GIR_Done,
+ // Label 180: @3605
+ GIM_Try, /*On fail goto*//*Label 181*/ 3651, // Rule ID 577 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 577,
+ GIR_Done,
+ // Label 181: @3651
+ GIM_Try, /*On fail goto*//*Label 182*/ 3697, // Rule ID 590 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 590,
+ GIR_Done,
+ // Label 182: @3697
+ GIM_Try, /*On fail goto*//*Label 183*/ 3743, // Rule ID 592 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 592,
+ GIR_Done,
+ // Label 183: @3743
+ GIM_Try, /*On fail goto*//*Label 184*/ 3789, // Rule ID 605 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 605,
+ GIR_Done,
+ // Label 184: @3789
+ GIM_Try, /*On fail goto*//*Label 185*/ 3835, // Rule ID 607 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 607,
+ GIR_Done,
+ // Label 185: @3835
+ GIM_Try, /*On fail goto*//*Label 186*/ 3881, // Rule ID 848 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_64>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 848,
+ GIR_Done,
+ // Label 186: @3881
+ GIM_Try, /*On fail goto*//*Label 187*/ 3927, // Rule ID 850 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_64>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 850,
+ GIR_Done,
+ // Label 187: @3927
+ GIM_Try, /*On fail goto*//*Label 188*/ 3973, // Rule ID 258 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 258,
+ GIR_Done,
+ // Label 188: @3973
+ GIM_Try, /*On fail goto*//*Label 189*/ 4019, // Rule ID 260 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 260,
+ GIR_Done,
+ // Label 189: @4019
+ GIM_Try, /*On fail goto*//*Label 190*/ 4065, // Rule ID 423 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 423,
+ GIR_Done,
+ // Label 190: @4065
+ GIM_Try, /*On fail goto*//*Label 191*/ 4111, // Rule ID 425 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 425,
+ GIR_Done,
+ // Label 191: @4111
+ GIM_Try, /*On fail goto*//*Label 192*/ 4157, // Rule ID 1130 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1130,
+ GIR_Done,
+ // Label 192: @4157
+ GIM_Try, /*On fail goto*//*Label 193*/ 4203, // Rule ID 1131 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[f32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1131,
+ GIR_Done,
+ // Label 193: @4203
+ GIM_Try, /*On fail goto*//*Label 194*/ 4249, // Rule ID 1132 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1132,
+ GIR_Done,
+ // Label 194: @4249
+ GIM_Try, /*On fail goto*//*Label 195*/ 4297, // Rule ID 213 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 213,
+ GIR_Done,
+ // Label 195: @4297
+ GIM_Try, /*On fail goto*//*Label 196*/ 4345, // Rule ID 215 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 215,
+ GIR_Done,
+ // Label 196: @4345
+ GIM_Try, /*On fail goto*//*Label 197*/ 4393, // Rule ID 243 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 243,
+ GIR_Done,
+ // Label 197: @4393
+ GIM_Try, /*On fail goto*//*Label 198*/ 4441, // Rule ID 245 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 245,
+ GIR_Done,
+ // Label 198: @4441
+ GIM_Try, /*On fail goto*//*Label 199*/ 4491, // Rule ID 393 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 393,
+ GIR_Done,
+ // Label 199: @4491
+ GIM_Try, /*On fail goto*//*Label 200*/ 4541, // Rule ID 395 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 395,
+ GIR_Done,
+ // Label 200: @4541
+ GIM_Reject,
+ // Label 157: @4542
+ GIM_Try, /*On fail goto*//*Label 201*/ 4619, // Rule ID 582 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 582,
+ GIR_Done,
+ // Label 201: @4619
+ GIM_Try, /*On fail goto*//*Label 202*/ 4696, // Rule ID 597 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 597,
+ GIR_Done,
+ // Label 202: @4696
+ GIM_Try, /*On fail goto*//*Label 203*/ 4773, // Rule ID 612 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 612,
+ GIR_Done,
+ // Label 203: @4773
+ GIM_Try, /*On fail goto*//*Label 204*/ 4850, // Rule ID 855 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 855,
+ GIR_Done,
+ // Label 204: @4850
+ GIM_Try, /*On fail goto*//*Label 205*/ 4927, // Rule ID 265 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 265,
+ GIR_Done,
+ // Label 205: @4927
+ GIM_Try, /*On fail goto*//*Label 206*/ 5004, // Rule ID 430 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 430,
+ GIR_Done,
+ // Label 206: @5004
+ GIM_Try, /*On fail goto*//*Label 207*/ 5081, // Rule ID 1279 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[f64] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1279,
+ GIR_Done,
+ // Label 207: @5081
+ GIM_Try, /*On fail goto*//*Label 208*/ 5158, // Rule ID 1280 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[f64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1280,
+ GIR_Done,
+ // Label 208: @5158
+ GIM_Try, /*On fail goto*//*Label 209*/ 5235, // Rule ID 1281 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[f64] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1281,
+ GIR_Done,
+ // Label 209: @5235
+ GIM_Try, /*On fail goto*//*Label 210*/ 5314, // Rule ID 220 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 220,
+ GIR_Done,
+ // Label 210: @5314
+ GIM_Try, /*On fail goto*//*Label 211*/ 5393, // Rule ID 250 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 250,
+ GIR_Done,
+ // Label 211: @5393
+ GIM_Try, /*On fail goto*//*Label 212*/ 5474, // Rule ID 400 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 400,
+ GIR_Done,
+ // Label 212: @5474
+ GIM_Try, /*On fail goto*//*Label 213*/ 5520, // Rule ID 576 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 576,
+ GIR_Done,
+ // Label 213: @5520
+ GIM_Try, /*On fail goto*//*Label 214*/ 5566, // Rule ID 591 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 591,
+ GIR_Done,
+ // Label 214: @5566
+ GIM_Try, /*On fail goto*//*Label 215*/ 5612, // Rule ID 606 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 606,
+ GIR_Done,
+ // Label 215: @5612
+ GIM_Try, /*On fail goto*//*Label 216*/ 5658, // Rule ID 849 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_64>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 849,
+ GIR_Done,
+ // Label 216: @5658
+ GIM_Try, /*On fail goto*//*Label 217*/ 5704, // Rule ID 259 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 259,
+ GIR_Done,
+ // Label 217: @5704
+ GIM_Try, /*On fail goto*//*Label 218*/ 5750, // Rule ID 424 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 424,
+ GIR_Done,
+ // Label 218: @5750
+ GIM_Try, /*On fail goto*//*Label 219*/ 5796, // Rule ID 1273 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1273,
+ GIR_Done,
+ // Label 219: @5796
+ GIM_Try, /*On fail goto*//*Label 220*/ 5842, // Rule ID 1274 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[f64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1274,
+ GIR_Done,
+ // Label 220: @5842
+ GIM_Try, /*On fail goto*//*Label 221*/ 5888, // Rule ID 1275 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1275,
+ GIR_Done,
+ // Label 221: @5888
+ GIM_Try, /*On fail goto*//*Label 222*/ 5936, // Rule ID 214 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 214,
+ GIR_Done,
+ // Label 222: @5936
+ GIM_Try, /*On fail goto*//*Label 223*/ 5984, // Rule ID 244 //
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 244,
+ GIR_Done,
+ // Label 223: @5984
+ GIM_Try, /*On fail goto*//*Label 224*/ 6034, // Rule ID 394 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 394,
+ GIR_Done,
+ // Label 224: @6034
+ GIM_Reject,
+ // Label 158: @6035
+ GIM_Reject,
+ // Label 13: @6036
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 227*/ 7129,
+ /*GILLT_s32*//*Label 225*/ 6044,
+ /*GILLT_s64*//*Label 226*/ 6767,
+ // Label 225: @6044
+ GIM_Try, /*On fail goto*//*Label 228*/ 6119, // Rule ID 204 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 204,
+ GIR_Done,
+ // Label 228: @6119
+ GIM_Try, /*On fail goto*//*Label 229*/ 6194, // Rule ID 206 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 206,
+ GIR_Done,
+ // Label 229: @6194
+ GIM_Try, /*On fail goto*//*Label 230*/ 6269, // Rule ID 234 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 234,
+ GIR_Done,
+ // Label 230: @6269
+ GIM_Try, /*On fail goto*//*Label 231*/ 6344, // Rule ID 236 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 236,
+ GIR_Done,
+ // Label 231: @6344
+ GIM_Try, /*On fail goto*//*Label 232*/ 6421, // Rule ID 384 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 384,
+ GIR_Done,
+ // Label 232: @6421
+ GIM_Try, /*On fail goto*//*Label 233*/ 6498, // Rule ID 386 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 386,
+ GIR_Done,
+ // Label 233: @6498
+ GIM_Try, /*On fail goto*//*Label 234*/ 6542, // Rule ID 198 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 198,
+ GIR_Done,
+ // Label 234: @6542
+ GIM_Try, /*On fail goto*//*Label 235*/ 6586, // Rule ID 200 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 200,
+ GIR_Done,
+ // Label 235: @6586
+ GIM_Try, /*On fail goto*//*Label 236*/ 6630, // Rule ID 228 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 228,
+ GIR_Done,
+ // Label 236: @6630
+ GIM_Try, /*On fail goto*//*Label 237*/ 6674, // Rule ID 230 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 230,
+ GIR_Done,
+ // Label 237: @6674
+ GIM_Try, /*On fail goto*//*Label 238*/ 6720, // Rule ID 378 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 378,
+ GIR_Done,
+ // Label 238: @6720
+ GIM_Try, /*On fail goto*//*Label 239*/ 6766, // Rule ID 380 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 380,
+ GIR_Done,
+ // Label 239: @6766
+ GIM_Reject,
+ // Label 226: @6767
+ GIM_Try, /*On fail goto*//*Label 240*/ 6842, // Rule ID 205 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 205,
+ GIR_Done,
+ // Label 240: @6842
+ GIM_Try, /*On fail goto*//*Label 241*/ 6917, // Rule ID 235 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 235,
+ GIR_Done,
+ // Label 241: @6917
+ GIM_Try, /*On fail goto*//*Label 242*/ 6994, // Rule ID 385 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 385,
+ GIR_Done,
+ // Label 242: @6994
+ GIM_Try, /*On fail goto*//*Label 243*/ 7038, // Rule ID 199 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 199,
+ GIR_Done,
+ // Label 243: @7038
+ GIM_Try, /*On fail goto*//*Label 244*/ 7082, // Rule ID 229 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 229,
+ GIR_Done,
+ // Label 244: @7082
+ GIM_Try, /*On fail goto*//*Label 245*/ 7128, // Rule ID 379 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 379,
+ GIR_Done,
+ // Label 245: @7128
+ GIM_Reject,
+ // Label 227: @7129
+ GIM_Reject,
+ // Label 14: @7130
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 248*/ 8223,
+ /*GILLT_s32*//*Label 246*/ 7138,
+ /*GILLT_s64*//*Label 247*/ 7861,
+ // Label 246: @7138
+ GIM_Try, /*On fail goto*//*Label 249*/ 7213, // Rule ID 279 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 279,
+ GIR_Done,
+ // Label 249: @7213
+ GIM_Try, /*On fail goto*//*Label 250*/ 7288, // Rule ID 281 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 281,
+ GIR_Done,
+ // Label 250: @7288
+ GIM_Try, /*On fail goto*//*Label 251*/ 7363, // Rule ID 294 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 294,
+ GIR_Done,
+ // Label 251: @7363
+ GIM_Try, /*On fail goto*//*Label 252*/ 7438, // Rule ID 296 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 296,
+ GIR_Done,
+ // Label 252: @7438
+ GIM_Try, /*On fail goto*//*Label 253*/ 7515, // Rule ID 414 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 414,
+ GIR_Done,
+ // Label 253: @7515
+ GIM_Try, /*On fail goto*//*Label 254*/ 7592, // Rule ID 416 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 416,
+ GIR_Done,
+ // Label 254: @7592
+ GIM_Try, /*On fail goto*//*Label 255*/ 7636, // Rule ID 273 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 273,
+ GIR_Done,
+ // Label 255: @7636
+ GIM_Try, /*On fail goto*//*Label 256*/ 7680, // Rule ID 275 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 275,
+ GIR_Done,
+ // Label 256: @7680
+ GIM_Try, /*On fail goto*//*Label 257*/ 7724, // Rule ID 288 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 288,
+ GIR_Done,
+ // Label 257: @7724
+ GIM_Try, /*On fail goto*//*Label 258*/ 7768, // Rule ID 290 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 290,
+ GIR_Done,
+ // Label 258: @7768
+ GIM_Try, /*On fail goto*//*Label 259*/ 7814, // Rule ID 408 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 408,
+ GIR_Done,
+ // Label 259: @7814
+ GIM_Try, /*On fail goto*//*Label 260*/ 7860, // Rule ID 410 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 410,
+ GIR_Done,
+ // Label 260: @7860
+ GIM_Reject,
+ // Label 247: @7861
+ GIM_Try, /*On fail goto*//*Label 261*/ 7936, // Rule ID 280 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 280,
+ GIR_Done,
+ // Label 261: @7936
+ GIM_Try, /*On fail goto*//*Label 262*/ 8011, // Rule ID 295 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 295,
+ GIR_Done,
+ // Label 262: @8011
+ GIM_Try, /*On fail goto*//*Label 263*/ 8088, // Rule ID 415 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 415,
+ GIR_Done,
+ // Label 263: @8088
+ GIM_Try, /*On fail goto*//*Label 264*/ 8132, // Rule ID 274 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 274,
+ GIR_Done,
+ // Label 264: @8132
+ GIM_Try, /*On fail goto*//*Label 265*/ 8176, // Rule ID 289 //
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 289,
+ GIR_Done,
+ // Label 265: @8176
+ GIM_Try, /*On fail goto*//*Label 266*/ 8222, // Rule ID 409 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 409,
+ GIR_Done,
+ // Label 266: @8222
+ GIM_Reject,
+ // Label 248: @8223
+ GIM_Reject,
+ // Label 15: @8224
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 269*/ 9562,
+ /*GILLT_s32*//*Label 267*/ 8232,
+ /*GILLT_s64*//*Label 268*/ 9006,
+ // Label 267: @8232
+ GIM_Try, /*On fail goto*//*Label 270*/ 9005,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_Try, /*On fail goto*//*Label 271*/ 8311, // Rule ID 339 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 339,
+ GIR_Done,
+ // Label 271: @8311
+ GIM_Try, /*On fail goto*//*Label 272*/ 8381, // Rule ID 341 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 341,
+ GIR_Done,
+ // Label 272: @8381
+ GIM_Try, /*On fail goto*//*Label 273*/ 8451, // Rule ID 459 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 459,
+ GIR_Done,
+ // Label 273: @8451
+ GIM_Try, /*On fail goto*//*Label 274*/ 8521, // Rule ID 461 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 461,
+ GIR_Done,
+ // Label 274: @8521
+ GIM_Try, /*On fail goto*//*Label 275*/ 8591, // Rule ID 1151 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1151,
+ GIR_Done,
+ // Label 275: @8591
+ GIM_Try, /*On fail goto*//*Label 276*/ 8661, // Rule ID 1152 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1152,
+ GIR_Done,
+ // Label 276: @8661
+ GIM_Try, /*On fail goto*//*Label 277*/ 8731, // Rule ID 1153 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1153,
+ GIR_Done,
+ // Label 277: @8731
+ GIM_Try, /*On fail goto*//*Label 278*/ 8770, // Rule ID 333 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 333,
+ GIR_Done,
+ // Label 278: @8770
+ GIM_Try, /*On fail goto*//*Label 279*/ 8809, // Rule ID 335 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 335,
+ GIR_Done,
+ // Label 279: @8809
+ GIM_Try, /*On fail goto*//*Label 280*/ 8848, // Rule ID 453 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 453,
+ GIR_Done,
+ // Label 280: @8848
+ GIM_Try, /*On fail goto*//*Label 281*/ 8887, // Rule ID 455 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 455,
+ GIR_Done,
+ // Label 281: @8887
+ GIM_Try, /*On fail goto*//*Label 282*/ 8926, // Rule ID 1145 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1145,
+ GIR_Done,
+ // Label 282: @8926
+ GIM_Try, /*On fail goto*//*Label 283*/ 8965, // Rule ID 1146 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1146,
+ GIR_Done,
+ // Label 283: @8965
+ GIM_Try, /*On fail goto*//*Label 284*/ 9004, // Rule ID 1147 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1147,
+ GIR_Done,
+ // Label 284: @9004
+ GIM_Reject,
+ // Label 270: @9005
+ GIM_Reject,
+ // Label 268: @9006
+ GIM_Try, /*On fail goto*//*Label 285*/ 9561,
+ GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic,
+ GIM_Try, /*On fail goto*//*Label 286*/ 9085, // Rule ID 340 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 340,
+ GIR_Done,
+ // Label 286: @9085
+ GIM_Try, /*On fail goto*//*Label 287*/ 9155, // Rule ID 460 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 460,
+ GIR_Done,
+ // Label 287: @9155
+ GIM_Try, /*On fail goto*//*Label 288*/ 9225, // Rule ID 1294 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1294,
+ GIR_Done,
+ // Label 288: @9225
+ GIM_Try, /*On fail goto*//*Label 289*/ 9295, // Rule ID 1295 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1295,
+ GIR_Done,
+ // Label 289: @9295
+ GIM_Try, /*On fail goto*//*Label 290*/ 9365, // Rule ID 1296 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1296,
+ GIR_Done,
+ // Label 290: @9365
+ GIM_Try, /*On fail goto*//*Label 291*/ 9404, // Rule ID 334 //
+ GIM_CheckFeatures, GIFBS_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 334,
+ GIR_Done,
+ // Label 291: @9404
+ GIM_Try, /*On fail goto*//*Label 292*/ 9443, // Rule ID 454 //
+ GIM_CheckFeatures, GIFBS_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 454,
+ GIR_Done,
+ // Label 292: @9443
+ GIM_Try, /*On fail goto*//*Label 293*/ 9482, // Rule ID 1288 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1288,
+ GIR_Done,
+ // Label 293: @9482
+ GIM_Try, /*On fail goto*//*Label 294*/ 9521, // Rule ID 1289 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1289,
+ GIR_Done,
+ // Label 294: @9521
+ GIM_Try, /*On fail goto*//*Label 295*/ 9560, // Rule ID 1290 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1290,
+ GIR_Done,
+ // Label 295: @9560
+ GIM_Reject,
+ // Label 285: @9561
+ GIM_Reject,
+ // Label 269: @9562
+ GIM_Reject,
+ // Label 16: @9563
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 298*/ 10607,
+ /*GILLT_s32*//*Label 296*/ 9571,
+ /*GILLT_s64*//*Label 297*/ 10259,
+ // Label 296: @9571
+ GIM_Try, /*On fail goto*//*Label 299*/ 10258,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 300*/ 9611, // Rule ID 650 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 650,
+ GIR_Done,
+ // Label 300: @9611
+ GIM_Try, /*On fail goto*//*Label 301*/ 9645, // Rule ID 652 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 652,
+ GIR_Done,
+ // Label 301: @9645
+ GIM_Try, /*On fail goto*//*Label 302*/ 9679, // Rule ID 653 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> => (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 653,
+ GIR_Done,
+ // Label 302: @9679
+ GIM_Try, /*On fail goto*//*Label 303*/ 9713, // Rule ID 655 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> => (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 655,
+ GIR_Done,
+ // Label 303: @9713
+ GIM_Try, /*On fail goto*//*Label 304*/ 9747, // Rule ID 656 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> => (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 656,
+ GIR_Done,
+ // Label 304: @9747
+ GIM_Try, /*On fail goto*//*Label 305*/ 9781, // Rule ID 658 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> => (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 658,
+ GIR_Done,
+ // Label 305: @9781
+ GIM_Try, /*On fail goto*//*Label 306*/ 9815, // Rule ID 659 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 659,
+ GIR_Done,
+ // Label 306: @9815
+ GIM_Try, /*On fail goto*//*Label 307*/ 9849, // Rule ID 661 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 661,
+ GIR_Done,
+ // Label 307: @9849
+ GIM_Try, /*On fail goto*//*Label 308*/ 9883, // Rule ID 662 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 662,
+ GIR_Done,
+ // Label 308: @9883
+ GIM_Try, /*On fail goto*//*Label 309*/ 9917, // Rule ID 664 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 664,
+ GIR_Done,
+ // Label 309: @9917
+ GIM_Try, /*On fail goto*//*Label 310*/ 9951, // Rule ID 878 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> => (AMOSWAP_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 878,
+ GIR_Done,
+ // Label 310: @9951
+ GIM_Try, /*On fail goto*//*Label 311*/ 9985, // Rule ID 880 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> => (AMOSWAP_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 880,
+ GIR_Done,
+ // Label 311: @9985
+ GIM_Try, /*On fail goto*//*Label 312*/ 10019, // Rule ID 881 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> => (AMOSWAP_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 881,
+ GIR_Done,
+ // Label 312: @10019
+ GIM_Try, /*On fail goto*//*Label 313*/ 10053, // Rule ID 883 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> => (AMOSWAP_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 883,
+ GIR_Done,
+ // Label 313: @10053
+ GIM_Try, /*On fail goto*//*Label 314*/ 10087, // Rule ID 884 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> => (AMOSWAP_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 884,
+ GIR_Done,
+ // Label 314: @10087
+ GIM_Try, /*On fail goto*//*Label 315*/ 10121, // Rule ID 886 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> => (AMOSWAP_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 886,
+ GIR_Done,
+ // Label 315: @10121
+ GIM_Try, /*On fail goto*//*Label 316*/ 10155, // Rule ID 887 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> => (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 887,
+ GIR_Done,
+ // Label 316: @10155
+ GIM_Try, /*On fail goto*//*Label 317*/ 10189, // Rule ID 889 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> => (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 889,
+ GIR_Done,
+ // Label 317: @10189
+ GIM_Try, /*On fail goto*//*Label 318*/ 10223, // Rule ID 890 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> => (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 890,
+ GIR_Done,
+ // Label 318: @10223
+ GIM_Try, /*On fail goto*//*Label 319*/ 10257, // Rule ID 892 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> => (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 892,
+ GIR_Done,
+ // Label 319: @10257
+ GIM_Reject,
+ // Label 299: @10258
+ GIM_Reject,
+ // Label 297: @10259
+ GIM_Try, /*On fail goto*//*Label 320*/ 10606,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 321*/ 10299, // Rule ID 651 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> => (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 651,
+ GIR_Done,
+ // Label 321: @10299
+ GIM_Try, /*On fail goto*//*Label 322*/ 10333, // Rule ID 654 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> => (AMOSWAP_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 654,
+ GIR_Done,
+ // Label 322: @10333
+ GIM_Try, /*On fail goto*//*Label 323*/ 10367, // Rule ID 657 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> => (AMOSWAP_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 657,
+ GIR_Done,
+ // Label 323: @10367
+ GIM_Try, /*On fail goto*//*Label 324*/ 10401, // Rule ID 660 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 660,
+ GIR_Done,
+ // Label 324: @10401
+ GIM_Try, /*On fail goto*//*Label 325*/ 10435, // Rule ID 663 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 663,
+ GIR_Done,
+ // Label 325: @10435
+ GIM_Try, /*On fail goto*//*Label 326*/ 10469, // Rule ID 879 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> => (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 879,
+ GIR_Done,
+ // Label 326: @10469
+ GIM_Try, /*On fail goto*//*Label 327*/ 10503, // Rule ID 882 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> => (AMOSWAP_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 882,
+ GIR_Done,
+ // Label 327: @10503
+ GIM_Try, /*On fail goto*//*Label 328*/ 10537, // Rule ID 885 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> => (AMOSWAP_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 885,
+ GIR_Done,
+ // Label 328: @10537
+ GIM_Try, /*On fail goto*//*Label 329*/ 10571, // Rule ID 888 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> => (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 888,
+ GIR_Done,
+ // Label 329: @10571
+ GIM_Try, /*On fail goto*//*Label 330*/ 10605, // Rule ID 891 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> => (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 891,
+ GIR_Done,
+ // Label 330: @10605
+ GIM_Reject,
+ // Label 320: @10606
+ GIM_Reject,
+ // Label 298: @10607
+ GIM_Reject,
+ // Label 17: @10608
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 333*/ 11652,
+ /*GILLT_s32*//*Label 331*/ 10616,
+ /*GILLT_s64*//*Label 332*/ 11304,
+ // Label 331: @10616
+ GIM_Try, /*On fail goto*//*Label 334*/ 11303,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 335*/ 10656, // Rule ID 665 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 665,
+ GIR_Done,
+ // Label 335: @10656
+ GIM_Try, /*On fail goto*//*Label 336*/ 10690, // Rule ID 667 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 667,
+ GIR_Done,
+ // Label 336: @10690
+ GIM_Try, /*On fail goto*//*Label 337*/ 10724, // Rule ID 668 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 668,
+ GIR_Done,
+ // Label 337: @10724
+ GIM_Try, /*On fail goto*//*Label 338*/ 10758, // Rule ID 670 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 670,
+ GIR_Done,
+ // Label 338: @10758
+ GIM_Try, /*On fail goto*//*Label 339*/ 10792, // Rule ID 671 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 671,
+ GIR_Done,
+ // Label 339: @10792
+ GIM_Try, /*On fail goto*//*Label 340*/ 10826, // Rule ID 673 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 673,
+ GIR_Done,
+ // Label 340: @10826
+ GIM_Try, /*On fail goto*//*Label 341*/ 10860, // Rule ID 674 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 674,
+ GIR_Done,
+ // Label 341: @10860
+ GIM_Try, /*On fail goto*//*Label 342*/ 10894, // Rule ID 676 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 676,
+ GIR_Done,
+ // Label 342: @10894
+ GIM_Try, /*On fail goto*//*Label 343*/ 10928, // Rule ID 677 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 677,
+ GIR_Done,
+ // Label 343: @10928
+ GIM_Try, /*On fail goto*//*Label 344*/ 10962, // Rule ID 679 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 679,
+ GIR_Done,
+ // Label 344: @10962
+ GIM_Try, /*On fail goto*//*Label 345*/ 10996, // Rule ID 893 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> => (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 893,
+ GIR_Done,
+ // Label 345: @10996
+ GIM_Try, /*On fail goto*//*Label 346*/ 11030, // Rule ID 895 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> => (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 895,
+ GIR_Done,
+ // Label 346: @11030
+ GIM_Try, /*On fail goto*//*Label 347*/ 11064, // Rule ID 896 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> => (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 896,
+ GIR_Done,
+ // Label 347: @11064
+ GIM_Try, /*On fail goto*//*Label 348*/ 11098, // Rule ID 898 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> => (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 898,
+ GIR_Done,
+ // Label 348: @11098
+ GIM_Try, /*On fail goto*//*Label 349*/ 11132, // Rule ID 899 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> => (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 899,
+ GIR_Done,
+ // Label 349: @11132
+ GIM_Try, /*On fail goto*//*Label 350*/ 11166, // Rule ID 901 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> => (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 901,
+ GIR_Done,
+ // Label 350: @11166
+ GIM_Try, /*On fail goto*//*Label 351*/ 11200, // Rule ID 902 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 902,
+ GIR_Done,
+ // Label 351: @11200
+ GIM_Try, /*On fail goto*//*Label 352*/ 11234, // Rule ID 904 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 904,
+ GIR_Done,
+ // Label 352: @11234
+ GIM_Try, /*On fail goto*//*Label 353*/ 11268, // Rule ID 905 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 905,
+ GIR_Done,
+ // Label 353: @11268
+ GIM_Try, /*On fail goto*//*Label 354*/ 11302, // Rule ID 907 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 907,
+ GIR_Done,
+ // Label 354: @11302
+ GIM_Reject,
+ // Label 334: @11303
+ GIM_Reject,
+ // Label 332: @11304
+ GIM_Try, /*On fail goto*//*Label 355*/ 11651,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 356*/ 11344, // Rule ID 666 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 666,
+ GIR_Done,
+ // Label 356: @11344
+ GIM_Try, /*On fail goto*//*Label 357*/ 11378, // Rule ID 669 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> => (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 669,
+ GIR_Done,
+ // Label 357: @11378
+ GIM_Try, /*On fail goto*//*Label 358*/ 11412, // Rule ID 672 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> => (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 672,
+ GIR_Done,
+ // Label 358: @11412
+ GIM_Try, /*On fail goto*//*Label 359*/ 11446, // Rule ID 675 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 675,
+ GIR_Done,
+ // Label 359: @11446
+ GIM_Try, /*On fail goto*//*Label 360*/ 11480, // Rule ID 678 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 678,
+ GIR_Done,
+ // Label 360: @11480
+ GIM_Try, /*On fail goto*//*Label 361*/ 11514, // Rule ID 894 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 894,
+ GIR_Done,
+ // Label 361: @11514
+ GIM_Try, /*On fail goto*//*Label 362*/ 11548, // Rule ID 897 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> => (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 897,
+ GIR_Done,
+ // Label 362: @11548
+ GIM_Try, /*On fail goto*//*Label 363*/ 11582, // Rule ID 900 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> => (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 900,
+ GIR_Done,
+ // Label 363: @11582
+ GIM_Try, /*On fail goto*//*Label 364*/ 11616, // Rule ID 903 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 903,
+ GIR_Done,
+ // Label 364: @11616
+ GIM_Try, /*On fail goto*//*Label 365*/ 11650, // Rule ID 906 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 906,
+ GIR_Done,
+ // Label 365: @11650
+ GIM_Reject,
+ // Label 355: @11651
+ GIM_Reject,
+ // Label 333: @11652
+ GIM_Reject,
+ // Label 18: @11653
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 368*/ 13807,
+ /*GILLT_s32*//*Label 366*/ 11661,
+ /*GILLT_s64*//*Label 367*/ 13089,
+ // Label 366: @11661
+ GIM_Try, /*On fail goto*//*Label 369*/ 13088,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 370*/ 11738, // Rule ID 785 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 785,
+ GIR_Done,
+ // Label 370: @11738
+ GIM_Try, /*On fail goto*//*Label 371*/ 11809, // Rule ID 787 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 787,
+ GIR_Done,
+ // Label 371: @11809
+ GIM_Try, /*On fail goto*//*Label 372*/ 11880, // Rule ID 788 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 788,
+ GIR_Done,
+ // Label 372: @11880
+ GIM_Try, /*On fail goto*//*Label 373*/ 11951, // Rule ID 790 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 790,
+ GIR_Done,
+ // Label 373: @11951
+ GIM_Try, /*On fail goto*//*Label 374*/ 12022, // Rule ID 791 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 791,
+ GIR_Done,
+ // Label 374: @12022
+ GIM_Try, /*On fail goto*//*Label 375*/ 12093, // Rule ID 793 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 793,
+ GIR_Done,
+ // Label 375: @12093
+ GIM_Try, /*On fail goto*//*Label 376*/ 12164, // Rule ID 794 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 794,
+ GIR_Done,
+ // Label 376: @12164
+ GIM_Try, /*On fail goto*//*Label 377*/ 12235, // Rule ID 796 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 796,
+ GIR_Done,
+ // Label 377: @12235
+ GIM_Try, /*On fail goto*//*Label 378*/ 12306, // Rule ID 797 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 797,
+ GIR_Done,
+ // Label 378: @12306
+ GIM_Try, /*On fail goto*//*Label 379*/ 12377, // Rule ID 799 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 799,
+ GIR_Done,
+ // Label 379: @12377
+ GIM_Try, /*On fail goto*//*Label 380*/ 12448, // Rule ID 1013 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> => (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1013,
+ GIR_Done,
+ // Label 380: @12448
+ GIM_Try, /*On fail goto*//*Label 381*/ 12519, // Rule ID 1015 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> => (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1015,
+ GIR_Done,
+ // Label 381: @12519
+ GIM_Try, /*On fail goto*//*Label 382*/ 12590, // Rule ID 1016 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> => (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1016,
+ GIR_Done,
+ // Label 382: @12590
+ GIM_Try, /*On fail goto*//*Label 383*/ 12661, // Rule ID 1018 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> => (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1018,
+ GIR_Done,
+ // Label 383: @12661
+ GIM_Try, /*On fail goto*//*Label 384*/ 12732, // Rule ID 1019 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> => (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1019,
+ GIR_Done,
+ // Label 384: @12732
+ GIM_Try, /*On fail goto*//*Label 385*/ 12803, // Rule ID 1021 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> => (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1021,
+ GIR_Done,
+ // Label 385: @12803
+ GIM_Try, /*On fail goto*//*Label 386*/ 12874, // Rule ID 1022 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1022,
+ GIR_Done,
+ // Label 386: @12874
+ GIM_Try, /*On fail goto*//*Label 387*/ 12945, // Rule ID 1024 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1024,
+ GIR_Done,
+ // Label 387: @12945
+ GIM_Try, /*On fail goto*//*Label 388*/ 13016, // Rule ID 1025 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1025,
+ GIR_Done,
+ // Label 388: @13016
+ GIM_Try, /*On fail goto*//*Label 389*/ 13087, // Rule ID 1027 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1027,
+ GIR_Done,
+ // Label 389: @13087
+ GIM_Reject,
+ // Label 369: @13088
+ GIM_Reject,
+ // Label 367: @13089
+ GIM_Try, /*On fail goto*//*Label 390*/ 13806,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 391*/ 13166, // Rule ID 786 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 786,
+ GIR_Done,
+ // Label 391: @13166
+ GIM_Try, /*On fail goto*//*Label 392*/ 13237, // Rule ID 789 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> => (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 789,
+ GIR_Done,
+ // Label 392: @13237
+ GIM_Try, /*On fail goto*//*Label 393*/ 13308, // Rule ID 792 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> => (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 792,
+ GIR_Done,
+ // Label 393: @13308
+ GIM_Try, /*On fail goto*//*Label 394*/ 13379, // Rule ID 795 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 795,
+ GIR_Done,
+ // Label 394: @13379
+ GIM_Try, /*On fail goto*//*Label 395*/ 13450, // Rule ID 798 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 798,
+ GIR_Done,
+ // Label 395: @13450
+ GIM_Try, /*On fail goto*//*Label 396*/ 13521, // Rule ID 1014 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1014,
+ GIR_Done,
+ // Label 396: @13521
+ GIM_Try, /*On fail goto*//*Label 397*/ 13592, // Rule ID 1017 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> => (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1017,
+ GIR_Done,
+ // Label 397: @13592
+ GIM_Try, /*On fail goto*//*Label 398*/ 13663, // Rule ID 1020 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> => (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1020,
+ GIR_Done,
+ // Label 398: @13663
+ GIM_Try, /*On fail goto*//*Label 399*/ 13734, // Rule ID 1023 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1023,
+ GIR_Done,
+ // Label 399: @13734
+ GIM_Try, /*On fail goto*//*Label 400*/ 13805, // Rule ID 1026 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] addr
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1026,
+ GIR_Done,
+ // Label 400: @13805
+ GIM_Reject,
+ // Label 390: @13806
+ GIM_Reject,
+ // Label 368: @13807
+ GIM_Reject,
+ // Label 19: @13808
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 403*/ 14852,
+ /*GILLT_s32*//*Label 401*/ 13816,
+ /*GILLT_s64*//*Label 402*/ 14504,
+ // Label 401: @13816
+ GIM_Try, /*On fail goto*//*Label 404*/ 14503,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 405*/ 13856, // Rule ID 680 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 680,
+ GIR_Done,
+ // Label 405: @13856
+ GIM_Try, /*On fail goto*//*Label 406*/ 13890, // Rule ID 682 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 682,
+ GIR_Done,
+ // Label 406: @13890
+ GIM_Try, /*On fail goto*//*Label 407*/ 13924, // Rule ID 683 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> => (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 683,
+ GIR_Done,
+ // Label 407: @13924
+ GIM_Try, /*On fail goto*//*Label 408*/ 13958, // Rule ID 685 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> => (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 685,
+ GIR_Done,
+ // Label 408: @13958
+ GIM_Try, /*On fail goto*//*Label 409*/ 13992, // Rule ID 686 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> => (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 686,
+ GIR_Done,
+ // Label 409: @13992
+ GIM_Try, /*On fail goto*//*Label 410*/ 14026, // Rule ID 688 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> => (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 688,
+ GIR_Done,
+ // Label 410: @14026
+ GIM_Try, /*On fail goto*//*Label 411*/ 14060, // Rule ID 689 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 689,
+ GIR_Done,
+ // Label 411: @14060
+ GIM_Try, /*On fail goto*//*Label 412*/ 14094, // Rule ID 691 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 691,
+ GIR_Done,
+ // Label 412: @14094
+ GIM_Try, /*On fail goto*//*Label 413*/ 14128, // Rule ID 692 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 692,
+ GIR_Done,
+ // Label 413: @14128
+ GIM_Try, /*On fail goto*//*Label 414*/ 14162, // Rule ID 694 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 694,
+ GIR_Done,
+ // Label 414: @14162
+ GIM_Try, /*On fail goto*//*Label 415*/ 14196, // Rule ID 908 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> => (AMOAND_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 908,
+ GIR_Done,
+ // Label 415: @14196
+ GIM_Try, /*On fail goto*//*Label 416*/ 14230, // Rule ID 910 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> => (AMOAND_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 910,
+ GIR_Done,
+ // Label 416: @14230
+ GIM_Try, /*On fail goto*//*Label 417*/ 14264, // Rule ID 911 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> => (AMOAND_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 911,
+ GIR_Done,
+ // Label 417: @14264
+ GIM_Try, /*On fail goto*//*Label 418*/ 14298, // Rule ID 913 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> => (AMOAND_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 913,
+ GIR_Done,
+ // Label 418: @14298
+ GIM_Try, /*On fail goto*//*Label 419*/ 14332, // Rule ID 914 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> => (AMOAND_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 914,
+ GIR_Done,
+ // Label 419: @14332
+ GIM_Try, /*On fail goto*//*Label 420*/ 14366, // Rule ID 916 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> => (AMOAND_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 916,
+ GIR_Done,
+ // Label 420: @14366
+ GIM_Try, /*On fail goto*//*Label 421*/ 14400, // Rule ID 917 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> => (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 917,
+ GIR_Done,
+ // Label 421: @14400
+ GIM_Try, /*On fail goto*//*Label 422*/ 14434, // Rule ID 919 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> => (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 919,
+ GIR_Done,
+ // Label 422: @14434
+ GIM_Try, /*On fail goto*//*Label 423*/ 14468, // Rule ID 920 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> => (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 920,
+ GIR_Done,
+ // Label 423: @14468
+ GIM_Try, /*On fail goto*//*Label 424*/ 14502, // Rule ID 922 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> => (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 922,
+ GIR_Done,
+ // Label 424: @14502
+ GIM_Reject,
+ // Label 404: @14503
+ GIM_Reject,
+ // Label 402: @14504
+ GIM_Try, /*On fail goto*//*Label 425*/ 14851,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 426*/ 14544, // Rule ID 681 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> => (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 681,
+ GIR_Done,
+ // Label 426: @14544
+ GIM_Try, /*On fail goto*//*Label 427*/ 14578, // Rule ID 684 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> => (AMOAND_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 684,
+ GIR_Done,
+ // Label 427: @14578
+ GIM_Try, /*On fail goto*//*Label 428*/ 14612, // Rule ID 687 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> => (AMOAND_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 687,
+ GIR_Done,
+ // Label 428: @14612
+ GIM_Try, /*On fail goto*//*Label 429*/ 14646, // Rule ID 690 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 690,
+ GIR_Done,
+ // Label 429: @14646
+ GIM_Try, /*On fail goto*//*Label 430*/ 14680, // Rule ID 693 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 693,
+ GIR_Done,
+ // Label 430: @14680
+ GIM_Try, /*On fail goto*//*Label 431*/ 14714, // Rule ID 909 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> => (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 909,
+ GIR_Done,
+ // Label 431: @14714
+ GIM_Try, /*On fail goto*//*Label 432*/ 14748, // Rule ID 912 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> => (AMOAND_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 912,
+ GIR_Done,
+ // Label 432: @14748
+ GIM_Try, /*On fail goto*//*Label 433*/ 14782, // Rule ID 915 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> => (AMOAND_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 915,
+ GIR_Done,
+ // Label 433: @14782
+ GIM_Try, /*On fail goto*//*Label 434*/ 14816, // Rule ID 918 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> => (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 918,
+ GIR_Done,
+ // Label 434: @14816
+ GIM_Try, /*On fail goto*//*Label 435*/ 14850, // Rule ID 921 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> => (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 921,
+ GIR_Done,
+ // Label 435: @14850
+ GIM_Reject,
+ // Label 425: @14851
+ GIM_Reject,
+ // Label 403: @14852
+ GIM_Reject,
+ // Label 20: @14853
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 438*/ 15897,
+ /*GILLT_s32*//*Label 436*/ 14861,
+ /*GILLT_s64*//*Label 437*/ 15549,
+ // Label 436: @14861
+ GIM_Try, /*On fail goto*//*Label 439*/ 15548,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 440*/ 14901, // Rule ID 695 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 695,
+ GIR_Done,
+ // Label 440: @14901
+ GIM_Try, /*On fail goto*//*Label 441*/ 14935, // Rule ID 697 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 697,
+ GIR_Done,
+ // Label 441: @14935
+ GIM_Try, /*On fail goto*//*Label 442*/ 14969, // Rule ID 698 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> => (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 698,
+ GIR_Done,
+ // Label 442: @14969
+ GIM_Try, /*On fail goto*//*Label 443*/ 15003, // Rule ID 700 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> => (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 700,
+ GIR_Done,
+ // Label 443: @15003
+ GIM_Try, /*On fail goto*//*Label 444*/ 15037, // Rule ID 701 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> => (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 701,
+ GIR_Done,
+ // Label 444: @15037
+ GIM_Try, /*On fail goto*//*Label 445*/ 15071, // Rule ID 703 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> => (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 703,
+ GIR_Done,
+ // Label 445: @15071
+ GIM_Try, /*On fail goto*//*Label 446*/ 15105, // Rule ID 704 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 704,
+ GIR_Done,
+ // Label 446: @15105
+ GIM_Try, /*On fail goto*//*Label 447*/ 15139, // Rule ID 706 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 706,
+ GIR_Done,
+ // Label 447: @15139
+ GIM_Try, /*On fail goto*//*Label 448*/ 15173, // Rule ID 707 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 707,
+ GIR_Done,
+ // Label 448: @15173
+ GIM_Try, /*On fail goto*//*Label 449*/ 15207, // Rule ID 709 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 709,
+ GIR_Done,
+ // Label 449: @15207
+ GIM_Try, /*On fail goto*//*Label 450*/ 15241, // Rule ID 923 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> => (AMOOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 923,
+ GIR_Done,
+ // Label 450: @15241
+ GIM_Try, /*On fail goto*//*Label 451*/ 15275, // Rule ID 925 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> => (AMOOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 925,
+ GIR_Done,
+ // Label 451: @15275
+ GIM_Try, /*On fail goto*//*Label 452*/ 15309, // Rule ID 926 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> => (AMOOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 926,
+ GIR_Done,
+ // Label 452: @15309
+ GIM_Try, /*On fail goto*//*Label 453*/ 15343, // Rule ID 928 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> => (AMOOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 928,
+ GIR_Done,
+ // Label 453: @15343
+ GIM_Try, /*On fail goto*//*Label 454*/ 15377, // Rule ID 929 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> => (AMOOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 929,
+ GIR_Done,
+ // Label 454: @15377
+ GIM_Try, /*On fail goto*//*Label 455*/ 15411, // Rule ID 931 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> => (AMOOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 931,
+ GIR_Done,
+ // Label 455: @15411
+ GIM_Try, /*On fail goto*//*Label 456*/ 15445, // Rule ID 932 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> => (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 932,
+ GIR_Done,
+ // Label 456: @15445
+ GIM_Try, /*On fail goto*//*Label 457*/ 15479, // Rule ID 934 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> => (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 934,
+ GIR_Done,
+ // Label 457: @15479
+ GIM_Try, /*On fail goto*//*Label 458*/ 15513, // Rule ID 935 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> => (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 935,
+ GIR_Done,
+ // Label 458: @15513
+ GIM_Try, /*On fail goto*//*Label 459*/ 15547, // Rule ID 937 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> => (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 937,
+ GIR_Done,
+ // Label 459: @15547
+ GIM_Reject,
+ // Label 439: @15548
+ GIM_Reject,
+ // Label 437: @15549
+ GIM_Try, /*On fail goto*//*Label 460*/ 15896,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 461*/ 15589, // Rule ID 696 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> => (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 696,
+ GIR_Done,
+ // Label 461: @15589
+ GIM_Try, /*On fail goto*//*Label 462*/ 15623, // Rule ID 699 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> => (AMOOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 699,
+ GIR_Done,
+ // Label 462: @15623
+ GIM_Try, /*On fail goto*//*Label 463*/ 15657, // Rule ID 702 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> => (AMOOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 702,
+ GIR_Done,
+ // Label 463: @15657
+ GIM_Try, /*On fail goto*//*Label 464*/ 15691, // Rule ID 705 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 705,
+ GIR_Done,
+ // Label 464: @15691
+ GIM_Try, /*On fail goto*//*Label 465*/ 15725, // Rule ID 708 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 708,
+ GIR_Done,
+ // Label 465: @15725
+ GIM_Try, /*On fail goto*//*Label 466*/ 15759, // Rule ID 924 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> => (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 924,
+ GIR_Done,
+ // Label 466: @15759
+ GIM_Try, /*On fail goto*//*Label 467*/ 15793, // Rule ID 927 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> => (AMOOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 927,
+ GIR_Done,
+ // Label 467: @15793
+ GIM_Try, /*On fail goto*//*Label 468*/ 15827, // Rule ID 930 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> => (AMOOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 930,
+ GIR_Done,
+ // Label 468: @15827
+ GIM_Try, /*On fail goto*//*Label 469*/ 15861, // Rule ID 933 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> => (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 933,
+ GIR_Done,
+ // Label 469: @15861
+ GIM_Try, /*On fail goto*//*Label 470*/ 15895, // Rule ID 936 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> => (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 936,
+ GIR_Done,
+ // Label 470: @15895
+ GIM_Reject,
+ // Label 460: @15896
+ GIM_Reject,
+ // Label 438: @15897
+ GIM_Reject,
+ // Label 21: @15898
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 473*/ 16942,
+ /*GILLT_s32*//*Label 471*/ 15906,
+ /*GILLT_s64*//*Label 472*/ 16594,
+ // Label 471: @15906
+ GIM_Try, /*On fail goto*//*Label 474*/ 16593,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 475*/ 15946, // Rule ID 710 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 710,
+ GIR_Done,
+ // Label 475: @15946
+ GIM_Try, /*On fail goto*//*Label 476*/ 15980, // Rule ID 712 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 712,
+ GIR_Done,
+ // Label 476: @15980
+ GIM_Try, /*On fail goto*//*Label 477*/ 16014, // Rule ID 713 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> => (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 713,
+ GIR_Done,
+ // Label 477: @16014
+ GIM_Try, /*On fail goto*//*Label 478*/ 16048, // Rule ID 715 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> => (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 715,
+ GIR_Done,
+ // Label 478: @16048
+ GIM_Try, /*On fail goto*//*Label 479*/ 16082, // Rule ID 716 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> => (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 716,
+ GIR_Done,
+ // Label 479: @16082
+ GIM_Try, /*On fail goto*//*Label 480*/ 16116, // Rule ID 718 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> => (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 718,
+ GIR_Done,
+ // Label 480: @16116
+ GIM_Try, /*On fail goto*//*Label 481*/ 16150, // Rule ID 719 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 719,
+ GIR_Done,
+ // Label 481: @16150
+ GIM_Try, /*On fail goto*//*Label 482*/ 16184, // Rule ID 721 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 721,
+ GIR_Done,
+ // Label 482: @16184
+ GIM_Try, /*On fail goto*//*Label 483*/ 16218, // Rule ID 722 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 722,
+ GIR_Done,
+ // Label 483: @16218
+ GIM_Try, /*On fail goto*//*Label 484*/ 16252, // Rule ID 724 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 724,
+ GIR_Done,
+ // Label 484: @16252
+ GIM_Try, /*On fail goto*//*Label 485*/ 16286, // Rule ID 938 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> => (AMOXOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 938,
+ GIR_Done,
+ // Label 485: @16286
+ GIM_Try, /*On fail goto*//*Label 486*/ 16320, // Rule ID 940 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> => (AMOXOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 940,
+ GIR_Done,
+ // Label 486: @16320
+ GIM_Try, /*On fail goto*//*Label 487*/ 16354, // Rule ID 941 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> => (AMOXOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 941,
+ GIR_Done,
+ // Label 487: @16354
+ GIM_Try, /*On fail goto*//*Label 488*/ 16388, // Rule ID 943 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> => (AMOXOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 943,
+ GIR_Done,
+ // Label 488: @16388
+ GIM_Try, /*On fail goto*//*Label 489*/ 16422, // Rule ID 944 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> => (AMOXOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 944,
+ GIR_Done,
+ // Label 489: @16422
+ GIM_Try, /*On fail goto*//*Label 490*/ 16456, // Rule ID 946 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> => (AMOXOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 946,
+ GIR_Done,
+ // Label 490: @16456
+ GIM_Try, /*On fail goto*//*Label 491*/ 16490, // Rule ID 947 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> => (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 947,
+ GIR_Done,
+ // Label 491: @16490
+ GIM_Try, /*On fail goto*//*Label 492*/ 16524, // Rule ID 949 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> => (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 949,
+ GIR_Done,
+ // Label 492: @16524
+ GIM_Try, /*On fail goto*//*Label 493*/ 16558, // Rule ID 950 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> => (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 950,
+ GIR_Done,
+ // Label 493: @16558
+ GIM_Try, /*On fail goto*//*Label 494*/ 16592, // Rule ID 952 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> => (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 952,
+ GIR_Done,
+ // Label 494: @16592
+ GIM_Reject,
+ // Label 474: @16593
+ GIM_Reject,
+ // Label 472: @16594
+ GIM_Try, /*On fail goto*//*Label 495*/ 16941,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 496*/ 16634, // Rule ID 711 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> => (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 711,
+ GIR_Done,
+ // Label 496: @16634
+ GIM_Try, /*On fail goto*//*Label 497*/ 16668, // Rule ID 714 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> => (AMOXOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 714,
+ GIR_Done,
+ // Label 497: @16668
+ GIM_Try, /*On fail goto*//*Label 498*/ 16702, // Rule ID 717 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> => (AMOXOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 717,
+ GIR_Done,
+ // Label 498: @16702
+ GIM_Try, /*On fail goto*//*Label 499*/ 16736, // Rule ID 720 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 720,
+ GIR_Done,
+ // Label 499: @16736
+ GIM_Try, /*On fail goto*//*Label 500*/ 16770, // Rule ID 723 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 723,
+ GIR_Done,
+ // Label 500: @16770
+ GIM_Try, /*On fail goto*//*Label 501*/ 16804, // Rule ID 939 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> => (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 939,
+ GIR_Done,
+ // Label 501: @16804
+ GIM_Try, /*On fail goto*//*Label 502*/ 16838, // Rule ID 942 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> => (AMOXOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 942,
+ GIR_Done,
+ // Label 502: @16838
+ GIM_Try, /*On fail goto*//*Label 503*/ 16872, // Rule ID 945 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> => (AMOXOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 945,
+ GIR_Done,
+ // Label 503: @16872
+ GIM_Try, /*On fail goto*//*Label 504*/ 16906, // Rule ID 948 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> => (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 948,
+ GIR_Done,
+ // Label 504: @16906
+ GIM_Try, /*On fail goto*//*Label 505*/ 16940, // Rule ID 951 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> => (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 951,
+ GIR_Done,
+ // Label 505: @16940
+ GIM_Reject,
+ // Label 495: @16941
+ GIM_Reject,
+ // Label 473: @16942
+ GIM_Reject,
+ // Label 22: @16943
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 508*/ 17987,
+ /*GILLT_s32*//*Label 506*/ 16951,
+ /*GILLT_s64*//*Label 507*/ 17639,
+ // Label 506: @16951
+ GIM_Try, /*On fail goto*//*Label 509*/ 17638,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 510*/ 16991, // Rule ID 725 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 725,
+ GIR_Done,
+ // Label 510: @16991
+ GIM_Try, /*On fail goto*//*Label 511*/ 17025, // Rule ID 727 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 727,
+ GIR_Done,
+ // Label 511: @17025
+ GIM_Try, /*On fail goto*//*Label 512*/ 17059, // Rule ID 728 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> => (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 728,
+ GIR_Done,
+ // Label 512: @17059
+ GIM_Try, /*On fail goto*//*Label 513*/ 17093, // Rule ID 730 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> => (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 730,
+ GIR_Done,
+ // Label 513: @17093
+ GIM_Try, /*On fail goto*//*Label 514*/ 17127, // Rule ID 731 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> => (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 731,
+ GIR_Done,
+ // Label 514: @17127
+ GIM_Try, /*On fail goto*//*Label 515*/ 17161, // Rule ID 733 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> => (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 733,
+ GIR_Done,
+ // Label 515: @17161
+ GIM_Try, /*On fail goto*//*Label 516*/ 17195, // Rule ID 734 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 734,
+ GIR_Done,
+ // Label 516: @17195
+ GIM_Try, /*On fail goto*//*Label 517*/ 17229, // Rule ID 736 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 736,
+ GIR_Done,
+ // Label 517: @17229
+ GIM_Try, /*On fail goto*//*Label 518*/ 17263, // Rule ID 737 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 737,
+ GIR_Done,
+ // Label 518: @17263
+ GIM_Try, /*On fail goto*//*Label 519*/ 17297, // Rule ID 739 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 739,
+ GIR_Done,
+ // Label 519: @17297
+ GIM_Try, /*On fail goto*//*Label 520*/ 17331, // Rule ID 953 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> => (AMOMAX_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 953,
+ GIR_Done,
+ // Label 520: @17331
+ GIM_Try, /*On fail goto*//*Label 521*/ 17365, // Rule ID 955 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> => (AMOMAX_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 955,
+ GIR_Done,
+ // Label 521: @17365
+ GIM_Try, /*On fail goto*//*Label 522*/ 17399, // Rule ID 956 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> => (AMOMAX_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 956,
+ GIR_Done,
+ // Label 522: @17399
+ GIM_Try, /*On fail goto*//*Label 523*/ 17433, // Rule ID 958 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> => (AMOMAX_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 958,
+ GIR_Done,
+ // Label 523: @17433
+ GIM_Try, /*On fail goto*//*Label 524*/ 17467, // Rule ID 959 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> => (AMOMAX_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 959,
+ GIR_Done,
+ // Label 524: @17467
+ GIM_Try, /*On fail goto*//*Label 525*/ 17501, // Rule ID 961 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> => (AMOMAX_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 961,
+ GIR_Done,
+ // Label 525: @17501
+ GIM_Try, /*On fail goto*//*Label 526*/ 17535, // Rule ID 962 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> => (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 962,
+ GIR_Done,
+ // Label 526: @17535
+ GIM_Try, /*On fail goto*//*Label 527*/ 17569, // Rule ID 964 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> => (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 964,
+ GIR_Done,
+ // Label 527: @17569
+ GIM_Try, /*On fail goto*//*Label 528*/ 17603, // Rule ID 965 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> => (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 965,
+ GIR_Done,
+ // Label 528: @17603
+ GIM_Try, /*On fail goto*//*Label 529*/ 17637, // Rule ID 967 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> => (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 967,
+ GIR_Done,
+ // Label 529: @17637
+ GIM_Reject,
+ // Label 509: @17638
+ GIM_Reject,
+ // Label 507: @17639
+ GIM_Try, /*On fail goto*//*Label 530*/ 17986,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 531*/ 17679, // Rule ID 726 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> => (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 726,
+ GIR_Done,
+ // Label 531: @17679
+ GIM_Try, /*On fail goto*//*Label 532*/ 17713, // Rule ID 729 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> => (AMOMAX_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 729,
+ GIR_Done,
+ // Label 532: @17713
+ GIM_Try, /*On fail goto*//*Label 533*/ 17747, // Rule ID 732 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> => (AMOMAX_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 732,
+ GIR_Done,
+ // Label 533: @17747
+ GIM_Try, /*On fail goto*//*Label 534*/ 17781, // Rule ID 735 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 735,
+ GIR_Done,
+ // Label 534: @17781
+ GIM_Try, /*On fail goto*//*Label 535*/ 17815, // Rule ID 738 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 738,
+ GIR_Done,
+ // Label 535: @17815
+ GIM_Try, /*On fail goto*//*Label 536*/ 17849, // Rule ID 954 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> => (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 954,
+ GIR_Done,
+ // Label 536: @17849
+ GIM_Try, /*On fail goto*//*Label 537*/ 17883, // Rule ID 957 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> => (AMOMAX_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 957,
+ GIR_Done,
+ // Label 537: @17883
+ GIM_Try, /*On fail goto*//*Label 538*/ 17917, // Rule ID 960 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> => (AMOMAX_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 960,
+ GIR_Done,
+ // Label 538: @17917
+ GIM_Try, /*On fail goto*//*Label 539*/ 17951, // Rule ID 963 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> => (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 963,
+ GIR_Done,
+ // Label 539: @17951
+ GIM_Try, /*On fail goto*//*Label 540*/ 17985, // Rule ID 966 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> => (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 966,
+ GIR_Done,
+ // Label 540: @17985
+ GIM_Reject,
+ // Label 530: @17986
+ GIM_Reject,
+ // Label 508: @17987
+ GIM_Reject,
+ // Label 23: @17988
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 543*/ 19032,
+ /*GILLT_s32*//*Label 541*/ 17996,
+ /*GILLT_s64*//*Label 542*/ 18684,
+ // Label 541: @17996
+ GIM_Try, /*On fail goto*//*Label 544*/ 18683,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 545*/ 18036, // Rule ID 740 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 740,
+ GIR_Done,
+ // Label 545: @18036
+ GIM_Try, /*On fail goto*//*Label 546*/ 18070, // Rule ID 742 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 742,
+ GIR_Done,
+ // Label 546: @18070
+ GIM_Try, /*On fail goto*//*Label 547*/ 18104, // Rule ID 743 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> => (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 743,
+ GIR_Done,
+ // Label 547: @18104
+ GIM_Try, /*On fail goto*//*Label 548*/ 18138, // Rule ID 745 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> => (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 745,
+ GIR_Done,
+ // Label 548: @18138
+ GIM_Try, /*On fail goto*//*Label 549*/ 18172, // Rule ID 746 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> => (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 746,
+ GIR_Done,
+ // Label 549: @18172
+ GIM_Try, /*On fail goto*//*Label 550*/ 18206, // Rule ID 748 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> => (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 748,
+ GIR_Done,
+ // Label 550: @18206
+ GIM_Try, /*On fail goto*//*Label 551*/ 18240, // Rule ID 749 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 749,
+ GIR_Done,
+ // Label 551: @18240
+ GIM_Try, /*On fail goto*//*Label 552*/ 18274, // Rule ID 751 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 751,
+ GIR_Done,
+ // Label 552: @18274
+ GIM_Try, /*On fail goto*//*Label 553*/ 18308, // Rule ID 752 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 752,
+ GIR_Done,
+ // Label 553: @18308
+ GIM_Try, /*On fail goto*//*Label 554*/ 18342, // Rule ID 754 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 754,
+ GIR_Done,
+ // Label 554: @18342
+ GIM_Try, /*On fail goto*//*Label 555*/ 18376, // Rule ID 968 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> => (AMOMIN_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 968,
+ GIR_Done,
+ // Label 555: @18376
+ GIM_Try, /*On fail goto*//*Label 556*/ 18410, // Rule ID 970 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> => (AMOMIN_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 970,
+ GIR_Done,
+ // Label 556: @18410
+ GIM_Try, /*On fail goto*//*Label 557*/ 18444, // Rule ID 971 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> => (AMOMIN_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 971,
+ GIR_Done,
+ // Label 557: @18444
+ GIM_Try, /*On fail goto*//*Label 558*/ 18478, // Rule ID 973 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> => (AMOMIN_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 973,
+ GIR_Done,
+ // Label 558: @18478
+ GIM_Try, /*On fail goto*//*Label 559*/ 18512, // Rule ID 974 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> => (AMOMIN_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 974,
+ GIR_Done,
+ // Label 559: @18512
+ GIM_Try, /*On fail goto*//*Label 560*/ 18546, // Rule ID 976 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> => (AMOMIN_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 976,
+ GIR_Done,
+ // Label 560: @18546
+ GIM_Try, /*On fail goto*//*Label 561*/ 18580, // Rule ID 977 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> => (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 977,
+ GIR_Done,
+ // Label 561: @18580
+ GIM_Try, /*On fail goto*//*Label 562*/ 18614, // Rule ID 979 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> => (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 979,
+ GIR_Done,
+ // Label 562: @18614
+ GIM_Try, /*On fail goto*//*Label 563*/ 18648, // Rule ID 980 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> => (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 980,
+ GIR_Done,
+ // Label 563: @18648
+ GIM_Try, /*On fail goto*//*Label 564*/ 18682, // Rule ID 982 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> => (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 982,
+ GIR_Done,
+ // Label 564: @18682
+ GIM_Reject,
+ // Label 544: @18683
+ GIM_Reject,
+ // Label 542: @18684
+ GIM_Try, /*On fail goto*//*Label 565*/ 19031,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 566*/ 18724, // Rule ID 741 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> => (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 741,
+ GIR_Done,
+ // Label 566: @18724
+ GIM_Try, /*On fail goto*//*Label 567*/ 18758, // Rule ID 744 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> => (AMOMIN_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 744,
+ GIR_Done,
+ // Label 567: @18758
+ GIM_Try, /*On fail goto*//*Label 568*/ 18792, // Rule ID 747 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> => (AMOMIN_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 747,
+ GIR_Done,
+ // Label 568: @18792
+ GIM_Try, /*On fail goto*//*Label 569*/ 18826, // Rule ID 750 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 750,
+ GIR_Done,
+ // Label 569: @18826
+ GIM_Try, /*On fail goto*//*Label 570*/ 18860, // Rule ID 753 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 753,
+ GIR_Done,
+ // Label 570: @18860
+ GIM_Try, /*On fail goto*//*Label 571*/ 18894, // Rule ID 969 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> => (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 969,
+ GIR_Done,
+ // Label 571: @18894
+ GIM_Try, /*On fail goto*//*Label 572*/ 18928, // Rule ID 972 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> => (AMOMIN_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 972,
+ GIR_Done,
+ // Label 572: @18928
+ GIM_Try, /*On fail goto*//*Label 573*/ 18962, // Rule ID 975 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> => (AMOMIN_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 975,
+ GIR_Done,
+ // Label 573: @18962
+ GIM_Try, /*On fail goto*//*Label 574*/ 18996, // Rule ID 978 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> => (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 978,
+ GIR_Done,
+ // Label 574: @18996
+ GIM_Try, /*On fail goto*//*Label 575*/ 19030, // Rule ID 981 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> => (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 981,
+ GIR_Done,
+ // Label 575: @19030
+ GIM_Reject,
+ // Label 565: @19031
+ GIM_Reject,
+ // Label 543: @19032
+ GIM_Reject,
+ // Label 24: @19033
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 578*/ 20077,
+ /*GILLT_s32*//*Label 576*/ 19041,
+ /*GILLT_s64*//*Label 577*/ 19729,
+ // Label 576: @19041
+ GIM_Try, /*On fail goto*//*Label 579*/ 19728,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 580*/ 19081, // Rule ID 755 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 755,
+ GIR_Done,
+ // Label 580: @19081
+ GIM_Try, /*On fail goto*//*Label 581*/ 19115, // Rule ID 757 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 757,
+ GIR_Done,
+ // Label 581: @19115
+ GIM_Try, /*On fail goto*//*Label 582*/ 19149, // Rule ID 758 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> => (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 758,
+ GIR_Done,
+ // Label 582: @19149
+ GIM_Try, /*On fail goto*//*Label 583*/ 19183, // Rule ID 760 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> => (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 760,
+ GIR_Done,
+ // Label 583: @19183
+ GIM_Try, /*On fail goto*//*Label 584*/ 19217, // Rule ID 761 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> => (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 761,
+ GIR_Done,
+ // Label 584: @19217
+ GIM_Try, /*On fail goto*//*Label 585*/ 19251, // Rule ID 763 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> => (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 763,
+ GIR_Done,
+ // Label 585: @19251
+ GIM_Try, /*On fail goto*//*Label 586*/ 19285, // Rule ID 764 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 764,
+ GIR_Done,
+ // Label 586: @19285
+ GIM_Try, /*On fail goto*//*Label 587*/ 19319, // Rule ID 766 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 766,
+ GIR_Done,
+ // Label 587: @19319
+ GIM_Try, /*On fail goto*//*Label 588*/ 19353, // Rule ID 767 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 767,
+ GIR_Done,
+ // Label 588: @19353
+ GIM_Try, /*On fail goto*//*Label 589*/ 19387, // Rule ID 769 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 769,
+ GIR_Done,
+ // Label 589: @19387
+ GIM_Try, /*On fail goto*//*Label 590*/ 19421, // Rule ID 983 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> => (AMOMAXU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 983,
+ GIR_Done,
+ // Label 590: @19421
+ GIM_Try, /*On fail goto*//*Label 591*/ 19455, // Rule ID 985 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> => (AMOMAXU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 985,
+ GIR_Done,
+ // Label 591: @19455
+ GIM_Try, /*On fail goto*//*Label 592*/ 19489, // Rule ID 986 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> => (AMOMAXU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 986,
+ GIR_Done,
+ // Label 592: @19489
+ GIM_Try, /*On fail goto*//*Label 593*/ 19523, // Rule ID 988 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> => (AMOMAXU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 988,
+ GIR_Done,
+ // Label 593: @19523
+ GIM_Try, /*On fail goto*//*Label 594*/ 19557, // Rule ID 989 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> => (AMOMAXU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 989,
+ GIR_Done,
+ // Label 594: @19557
+ GIM_Try, /*On fail goto*//*Label 595*/ 19591, // Rule ID 991 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> => (AMOMAXU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 991,
+ GIR_Done,
+ // Label 595: @19591
+ GIM_Try, /*On fail goto*//*Label 596*/ 19625, // Rule ID 992 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> => (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 992,
+ GIR_Done,
+ // Label 596: @19625
+ GIM_Try, /*On fail goto*//*Label 597*/ 19659, // Rule ID 994 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> => (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 994,
+ GIR_Done,
+ // Label 597: @19659
+ GIM_Try, /*On fail goto*//*Label 598*/ 19693, // Rule ID 995 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> => (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 995,
+ GIR_Done,
+ // Label 598: @19693
+ GIM_Try, /*On fail goto*//*Label 599*/ 19727, // Rule ID 997 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> => (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 997,
+ GIR_Done,
+ // Label 599: @19727
+ GIM_Reject,
+ // Label 579: @19728
+ GIM_Reject,
+ // Label 577: @19729
+ GIM_Try, /*On fail goto*//*Label 600*/ 20076,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 601*/ 19769, // Rule ID 756 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> => (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 756,
+ GIR_Done,
+ // Label 601: @19769
+ GIM_Try, /*On fail goto*//*Label 602*/ 19803, // Rule ID 759 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> => (AMOMAXU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 759,
+ GIR_Done,
+ // Label 602: @19803
+ GIM_Try, /*On fail goto*//*Label 603*/ 19837, // Rule ID 762 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> => (AMOMAXU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 762,
+ GIR_Done,
+ // Label 603: @19837
+ GIM_Try, /*On fail goto*//*Label 604*/ 19871, // Rule ID 765 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 765,
+ GIR_Done,
+ // Label 604: @19871
+ GIM_Try, /*On fail goto*//*Label 605*/ 19905, // Rule ID 768 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 768,
+ GIR_Done,
+ // Label 605: @19905
+ GIM_Try, /*On fail goto*//*Label 606*/ 19939, // Rule ID 984 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> => (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 984,
+ GIR_Done,
+ // Label 606: @19939
+ GIM_Try, /*On fail goto*//*Label 607*/ 19973, // Rule ID 987 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> => (AMOMAXU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 987,
+ GIR_Done,
+ // Label 607: @19973
+ GIM_Try, /*On fail goto*//*Label 608*/ 20007, // Rule ID 990 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> => (AMOMAXU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 990,
+ GIR_Done,
+ // Label 608: @20007
+ GIM_Try, /*On fail goto*//*Label 609*/ 20041, // Rule ID 993 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> => (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 993,
+ GIR_Done,
+ // Label 609: @20041
+ GIM_Try, /*On fail goto*//*Label 610*/ 20075, // Rule ID 996 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> => (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 996,
+ GIR_Done,
+ // Label 610: @20075
+ GIM_Reject,
+ // Label 600: @20076
+ GIM_Reject,
+ // Label 578: @20077
+ GIM_Reject,
+ // Label 25: @20078
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 613*/ 21122,
+ /*GILLT_s32*//*Label 611*/ 20086,
+ /*GILLT_s64*//*Label 612*/ 20774,
+ // Label 611: @20086
+ GIM_Try, /*On fail goto*//*Label 614*/ 20773,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_Try, /*On fail goto*//*Label 615*/ 20126, // Rule ID 770 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 770,
+ GIR_Done,
+ // Label 615: @20126
+ GIM_Try, /*On fail goto*//*Label 616*/ 20160, // Rule ID 772 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 772,
+ GIR_Done,
+ // Label 616: @20160
+ GIM_Try, /*On fail goto*//*Label 617*/ 20194, // Rule ID 773 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> => (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 773,
+ GIR_Done,
+ // Label 617: @20194
+ GIM_Try, /*On fail goto*//*Label 618*/ 20228, // Rule ID 775 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> => (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 775,
+ GIR_Done,
+ // Label 618: @20228
+ GIM_Try, /*On fail goto*//*Label 619*/ 20262, // Rule ID 776 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> => (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 776,
+ GIR_Done,
+ // Label 619: @20262
+ GIM_Try, /*On fail goto*//*Label 620*/ 20296, // Rule ID 778 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> => (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 778,
+ GIR_Done,
+ // Label 620: @20296
+ GIM_Try, /*On fail goto*//*Label 621*/ 20330, // Rule ID 779 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 779,
+ GIR_Done,
+ // Label 621: @20330
+ GIM_Try, /*On fail goto*//*Label 622*/ 20364, // Rule ID 781 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 781,
+ GIR_Done,
+ // Label 622: @20364
+ GIM_Try, /*On fail goto*//*Label 623*/ 20398, // Rule ID 782 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 782,
+ GIR_Done,
+ // Label 623: @20398
+ GIM_Try, /*On fail goto*//*Label 624*/ 20432, // Rule ID 784 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 784,
+ GIR_Done,
+ // Label 624: @20432
+ GIM_Try, /*On fail goto*//*Label 625*/ 20466, // Rule ID 998 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> => (AMOMINU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 998,
+ GIR_Done,
+ // Label 625: @20466
+ GIM_Try, /*On fail goto*//*Label 626*/ 20500, // Rule ID 1000 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> => (AMOMINU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1000,
+ GIR_Done,
+ // Label 626: @20500
+ GIM_Try, /*On fail goto*//*Label 627*/ 20534, // Rule ID 1001 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> => (AMOMINU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1001,
+ GIR_Done,
+ // Label 627: @20534
+ GIM_Try, /*On fail goto*//*Label 628*/ 20568, // Rule ID 1003 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> => (AMOMINU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1003,
+ GIR_Done,
+ // Label 628: @20568
+ GIM_Try, /*On fail goto*//*Label 629*/ 20602, // Rule ID 1004 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> => (AMOMINU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1004,
+ GIR_Done,
+ // Label 629: @20602
+ GIM_Try, /*On fail goto*//*Label 630*/ 20636, // Rule ID 1006 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> => (AMOMINU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1006,
+ GIR_Done,
+ // Label 630: @20636
+ GIM_Try, /*On fail goto*//*Label 631*/ 20670, // Rule ID 1007 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> => (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1007,
+ GIR_Done,
+ // Label 631: @20670
+ GIM_Try, /*On fail goto*//*Label 632*/ 20704, // Rule ID 1009 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> => (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1009,
+ GIR_Done,
+ // Label 632: @20704
+ GIM_Try, /*On fail goto*//*Label 633*/ 20738, // Rule ID 1010 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> => (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1010,
+ GIR_Done,
+ // Label 633: @20738
+ GIM_Try, /*On fail goto*//*Label 634*/ 20772, // Rule ID 1012 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> => (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1012,
+ GIR_Done,
+ // Label 634: @20772
+ GIM_Reject,
+ // Label 614: @20773
+ GIM_Reject,
+ // Label 612: @20774
+ GIM_Try, /*On fail goto*//*Label 635*/ 21121,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_Try, /*On fail goto*//*Label 636*/ 20814, // Rule ID 771 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> => (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 771,
+ GIR_Done,
+ // Label 636: @20814
+ GIM_Try, /*On fail goto*//*Label 637*/ 20848, // Rule ID 774 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> => (AMOMINU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 774,
+ GIR_Done,
+ // Label 637: @20848
+ GIM_Try, /*On fail goto*//*Label 638*/ 20882, // Rule ID 777 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> => (AMOMINU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 777,
+ GIR_Done,
+ // Label 638: @20882
+ GIM_Try, /*On fail goto*//*Label 639*/ 20916, // Rule ID 780 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 780,
+ GIR_Done,
+ // Label 639: @20916
+ GIM_Try, /*On fail goto*//*Label 640*/ 20950, // Rule ID 783 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 783,
+ GIR_Done,
+ // Label 640: @20950
+ GIM_Try, /*On fail goto*//*Label 641*/ 20984, // Rule ID 999 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> => (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 999,
+ GIR_Done,
+ // Label 641: @20984
+ GIM_Try, /*On fail goto*//*Label 642*/ 21018, // Rule ID 1002 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> => (AMOMINU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1002,
+ GIR_Done,
+ // Label 642: @21018
+ GIM_Try, /*On fail goto*//*Label 643*/ 21052, // Rule ID 1005 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> => (AMOMINU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1005,
+ GIR_Done,
+ // Label 643: @21052
+ GIM_Try, /*On fail goto*//*Label 644*/ 21086, // Rule ID 1008 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> => (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1008,
+ GIR_Done,
+ // Label 644: @21086
+ GIM_Try, /*On fail goto*//*Label 645*/ 21120, // Rule ID 1011 //
+ GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64,
+ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8,
+ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] rs1
+ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> => (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1011,
+ GIR_Done,
+ // Label 645: @21120
+ GIM_Reject,
+ // Label 635: @21121
+ GIM_Reject,
+ // Label 613: @21122
+ GIM_Reject,
+ // Label 26: @21123
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 648*/ 21391,
+ /*GILLT_s32*//*Label 646*/ 21131,
+ /*GILLT_s64*//*Label 647*/ 21304,
+ // Label 646: @21131
+ GIM_Try, /*On fail goto*//*Label 649*/ 21154, // Rule ID 348 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 4:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 2:{ *:[i32] }, 3:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/2,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 348,
+ GIR_Done,
+ // Label 649: @21154
+ GIM_Try, /*On fail goto*//*Label 650*/ 21177, // Rule ID 350 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 4:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 2:{ *:[i32] }, 3:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/2,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 350,
+ GIR_Done,
+ // Label 650: @21177
+ GIM_Try, /*On fail goto*//*Label 651*/ 21200, // Rule ID 351 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 5,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 5:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 351,
+ GIR_Done,
+ // Label 651: @21200
+ GIM_Try, /*On fail goto*//*Label 652*/ 21223, // Rule ID 353 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 5,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 5:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 353,
+ GIR_Done,
+ // Label 652: @21223
+ GIM_Try, /*On fail goto*//*Label 653*/ 21240, // Rule ID 354 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 6,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 6:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE_TSO)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 354,
+ GIR_Done,
+ // Label 653: @21240
+ GIM_Try, /*On fail goto*//*Label 654*/ 21257, // Rule ID 356 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 6,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 6:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE_TSO)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 356,
+ GIR_Done,
+ // Label 654: @21257
+ GIM_Try, /*On fail goto*//*Label 655*/ 21280, // Rule ID 357 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 3:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 357,
+ GIR_Done,
+ // Label 655: @21280
+ GIM_Try, /*On fail goto*//*Label 656*/ 21303, // Rule ID 359 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 3:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 359,
+ GIR_Done,
+ // Label 656: @21303
+ GIM_Reject,
+ // Label 647: @21304
+ GIM_Try, /*On fail goto*//*Label 657*/ 21327, // Rule ID 349 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 2:{ *:[i64] }, 3:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/2,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 349,
+ GIR_Done,
+ // Label 657: @21327
+ GIM_Try, /*On fail goto*//*Label 658*/ 21350, // Rule ID 352 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 5,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 5:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 3:{ *:[i64] }, 1:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 352,
+ GIR_Done,
+ // Label 658: @21350
+ GIM_Try, /*On fail goto*//*Label 659*/ 21367, // Rule ID 355 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 6,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 6:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE_TSO)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 355,
+ GIR_Done,
+ // Label 659: @21367
+ GIM_Try, /*On fail goto*//*Label 660*/ 21390, // Rule ID 358 //
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7,
+ // MIs[0] Operand 1
+ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
+ // (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 3:{ *:[i64] }, 3:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/3,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 358,
+ GIR_Done,
+ // Label 660: @21390
+ GIM_Reject,
+ // Label 648: @21391
+ GIM_Reject,
+ // Label 27: @21392
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 663*/ 21482,
+ /*GILLT_s32*//*Label 661*/ 21400,
+ /*GILLT_s64*//*Label 662*/ 21453,
+ // Label 661: @21400
+ GIM_Try, /*On fail goto*//*Label 664*/ 21452,
+ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 665*/ 21430, // Rule ID 23 //
+ // MIs[0] Operand 1
+ // No operand predicates
+ // (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm => (ADDI:{ *:[i32] } X0:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 23,
+ GIR_Done,
+ // Label 665: @21430
+ GIM_Try, /*On fail goto*//*Label 666*/ 21451, // Rule ID 25 //
+ // MIs[0] Operand 1
+ // No operand predicates
+ // (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm => (ADDI:{ *:[i32] } X0:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 25,
+ GIR_Done,
+ // Label 666: @21451
+ GIM_Reject,
+ // Label 664: @21452
+ GIM_Reject,
+ // Label 662: @21453
+ GIM_Try, /*On fail goto*//*Label 667*/ 21481, // Rule ID 24 //
+ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ // No operand predicates
+ // (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm => (ADDI:{ *:[i64] } X0:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 24,
+ GIR_Done,
+ // Label 667: @21481
+ GIM_Reject,
+ // Label 663: @21482
+ GIM_Reject,
+ // Label 28: @21483
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 670*/ 21834,
+ /*GILLT_s32*//*Label 668*/ 21491,
+ /*GILLT_s64*//*Label 669*/ 21713,
+ // Label 668: @21491
+ GIM_Try, /*On fail goto*//*Label 671*/ 21712,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 672*/ 21564, // Rule ID 71 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 71,
+ GIR_Done,
+ // Label 672: @21564
+ GIM_Try, /*On fail goto*//*Label 673*/ 21619, // Rule ID 73 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 73,
+ GIR_Done,
+ // Label 673: @21619
+ GIM_Try, /*On fail goto*//*Label 674*/ 21652, // Rule ID 59 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 59,
+ GIR_Done,
+ // Label 674: @21652
+ GIM_Try, /*On fail goto*//*Label 675*/ 21685, // Rule ID 61 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 61,
+ GIR_Done,
+ // Label 675: @21685
+ GIM_Try, /*On fail goto*//*Label 676*/ 21698, // Rule ID 68 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SLL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 68,
+ GIR_Done,
+ // Label 676: @21698
+ GIM_Try, /*On fail goto*//*Label 677*/ 21711, // Rule ID 70 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SLL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 70,
+ GIR_Done,
+ // Label 677: @21711
+ GIM_Reject,
+ // Label 671: @21712
+ GIM_Reject,
+ // Label 669: @21713
+ GIM_Try, /*On fail goto*//*Label 678*/ 21833,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 679*/ 21786, // Rule ID 72 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) => (SLL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 72,
+ GIR_Done,
+ // Label 679: @21786
+ GIM_Try, /*On fail goto*//*Label 680*/ 21819, // Rule ID 60 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 60,
+ GIR_Done,
+ // Label 680: @21819
+ GIM_Try, /*On fail goto*//*Label 681*/ 21832, // Rule ID 69 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SLL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SLL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 69,
+ GIR_Done,
+ // Label 681: @21832
+ GIM_Reject,
+ // Label 678: @21833
+ GIM_Reject,
+ // Label 670: @21834
+ GIM_Reject,
+ // Label 29: @21835
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 684*/ 22186,
+ /*GILLT_s32*//*Label 682*/ 21843,
+ /*GILLT_s64*//*Label 683*/ 22065,
+ // Label 682: @21843
+ GIM_Try, /*On fail goto*//*Label 685*/ 22064,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 686*/ 21916, // Rule ID 77 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 77,
+ GIR_Done,
+ // Label 686: @21916
+ GIM_Try, /*On fail goto*//*Label 687*/ 21971, // Rule ID 79 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 79,
+ GIR_Done,
+ // Label 687: @21971
+ GIM_Try, /*On fail goto*//*Label 688*/ 22004, // Rule ID 62 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 62,
+ GIR_Done,
+ // Label 688: @22004
+ GIM_Try, /*On fail goto*//*Label 689*/ 22037, // Rule ID 64 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 64,
+ GIR_Done,
+ // Label 689: @22037
+ GIM_Try, /*On fail goto*//*Label 690*/ 22050, // Rule ID 74 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 74,
+ GIR_Done,
+ // Label 690: @22050
+ GIM_Try, /*On fail goto*//*Label 691*/ 22063, // Rule ID 76 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 76,
+ GIR_Done,
+ // Label 691: @22063
+ GIM_Reject,
+ // Label 685: @22064
+ GIM_Reject,
+ // Label 683: @22065
+ GIM_Try, /*On fail goto*//*Label 692*/ 22185,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 693*/ 22138, // Rule ID 78 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) => (SRL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 78,
+ GIR_Done,
+ // Label 693: @22138
+ GIM_Try, /*On fail goto*//*Label 694*/ 22171, // Rule ID 63 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 63,
+ GIR_Done,
+ // Label 694: @22171
+ GIM_Try, /*On fail goto*//*Label 695*/ 22184, // Rule ID 75 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SRL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRL,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 75,
+ GIR_Done,
+ // Label 695: @22184
+ GIM_Reject,
+ // Label 692: @22185
+ GIM_Reject,
+ // Label 684: @22186
+ GIM_Reject,
+ // Label 30: @22187
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 698*/ 22538,
+ /*GILLT_s32*//*Label 696*/ 22195,
+ /*GILLT_s64*//*Label 697*/ 22417,
+ // Label 696: @22195
+ GIM_Try, /*On fail goto*//*Label 699*/ 22416,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 700*/ 22268, // Rule ID 83 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 83,
+ GIR_Done,
+ // Label 700: @22268
+ GIM_Try, /*On fail goto*//*Label 701*/ 22323, // Rule ID 85 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 85,
+ GIR_Done,
+ // Label 701: @22323
+ GIM_Try, /*On fail goto*//*Label 702*/ 22356, // Rule ID 65 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRAI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 65,
+ GIR_Done,
+ // Label 702: @22356
+ GIM_Try, /*On fail goto*//*Label 703*/ 22389, // Rule ID 67 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRAI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 67,
+ GIR_Done,
+ // Label 703: @22389
+ GIM_Try, /*On fail goto*//*Label 704*/ 22402, // Rule ID 80 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRA,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 80,
+ GIR_Done,
+ // Label 704: @22402
+ GIM_Try, /*On fail goto*//*Label 705*/ 22415, // Rule ID 82 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRA,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 82,
+ GIR_Done,
+ // Label 705: @22415
+ GIM_Reject,
+ // Label 699: @22416
+ GIM_Reject,
+ // Label 697: @22417
+ GIM_Try, /*On fail goto*//*Label 706*/ 22537,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 707*/ 22490, // Rule ID 84 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset,
+ // MIs[2] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) => (SRA:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 84,
+ GIR_Done,
+ // Label 707: @22490
+ GIM_Try, /*On fail goto*//*Label 708*/ 22523, // Rule ID 66 //
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRAI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 66,
+ GIR_Done,
+ // Label 708: @22523
+ GIM_Try, /*On fail goto*//*Label 709*/ 22536, // Rule ID 81 //
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SRA:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRA,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 81,
+ GIR_Done,
+ // Label 709: @22536
+ GIM_Reject,
+ // Label 706: @22537
+ GIM_Reject,
+ // Label 698: @22538
+ GIM_Reject,
+ // Label 31: @22539
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 712*/ 24754,
+ /*GILLT_s32*//*Label 710*/ 22547,
+ /*GILLT_s64*//*Label 711*/ 24013,
+ // Label 710: @22547
+ GIM_Try, /*On fail goto*//*Label 713*/ 24012,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 714*/ 22594, // Rule ID 102 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 102,
+ GIR_Done,
+ // Label 714: @22594
+ GIM_Try, /*On fail goto*//*Label 715*/ 22627, // Rule ID 104 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 104,
+ GIR_Done,
+ // Label 715: @22627
+ GIM_Try, /*On fail goto*//*Label 716*/ 22661, // Rule ID 111 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 111,
+ GIR_Done,
+ // Label 716: @22661
+ GIM_Try, /*On fail goto*//*Label 717*/ 22695, // Rule ID 113 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 113,
+ GIR_Done,
+ // Label 717: @22695
+ GIM_Try, /*On fail goto*//*Label 718*/ 22736, // Rule ID 93 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 93,
+ GIR_Done,
+ // Label 718: @22736
+ GIM_Try, /*On fail goto*//*Label 719*/ 22777, // Rule ID 95 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 95,
+ GIR_Done,
+ // Label 719: @22777
+ GIM_Try, /*On fail goto*//*Label 720*/ 22818, // Rule ID 99 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 99,
+ GIR_Done,
+ // Label 720: @22818
+ GIM_Try, /*On fail goto*//*Label 721*/ 22859, // Rule ID 101 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 101,
+ GIR_Done,
+ // Label 721: @22859
+ GIM_Try, /*On fail goto*//*Label 722*/ 22919, // Rule ID 108 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 108,
+ GIR_Done,
+ // Label 722: @22919
+ GIM_Try, /*On fail goto*//*Label 723*/ 22979, // Rule ID 110 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 110,
+ GIR_Done,
+ // Label 723: @22979
+ GIM_Try, /*On fail goto*//*Label 724*/ 23040, // Rule ID 117 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 117,
+ GIR_Done,
+ // Label 724: @23040
+ GIM_Try, /*On fail goto*//*Label 725*/ 23101, // Rule ID 119 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 119,
+ GIR_Done,
+ // Label 725: @23101
+ GIM_Try, /*On fail goto*//*Label 726*/ 23135, // Rule ID 90 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 90,
+ GIR_Done,
+ // Label 726: @23135
+ GIM_Try, /*On fail goto*//*Label 727*/ 23169, // Rule ID 92 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 92,
+ GIR_Done,
+ // Label 727: @23169
+ GIM_Try, /*On fail goto*//*Label 728*/ 23203, // Rule ID 96 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 96,
+ GIR_Done,
+ // Label 728: @23203
+ GIM_Try, /*On fail goto*//*Label 729*/ 23237, // Rule ID 98 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 98,
+ GIR_Done,
+ // Label 729: @23237
+ GIM_Try, /*On fail goto*//*Label 730*/ 23290, // Rule ID 105 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 105,
+ GIR_Done,
+ // Label 730: @23290
+ GIM_Try, /*On fail goto*//*Label 731*/ 23343, // Rule ID 107 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 107,
+ GIR_Done,
+ // Label 731: @23343
+ GIM_Try, /*On fail goto*//*Label 732*/ 23397, // Rule ID 114 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 114,
+ GIR_Done,
+ // Label 732: @23397
+ GIM_Try, /*On fail goto*//*Label 733*/ 23451, // Rule ID 116 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 116,
+ GIR_Done,
+ // Label 733: @23451
+ GIM_Try, /*On fail goto*//*Label 734*/ 23485, // Rule ID 120 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 120,
+ GIR_Done,
+ // Label 734: @23485
+ GIM_Try, /*On fail goto*//*Label 735*/ 23519, // Rule ID 122 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 122,
+ GIR_Done,
+ // Label 735: @23519
+ GIM_Try, /*On fail goto*//*Label 736*/ 23572, // Rule ID 123 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 123,
+ GIR_Done,
+ // Label 736: @23572
+ GIM_Try, /*On fail goto*//*Label 737*/ 23625, // Rule ID 125 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 125,
+ GIR_Done,
+ // Label 737: @23625
+ GIM_Try, /*On fail goto*//*Label 738*/ 23678, // Rule ID 126 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 126,
+ GIR_Done,
+ // Label 738: @23678
+ GIM_Try, /*On fail goto*//*Label 739*/ 23731, // Rule ID 128 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 128,
+ GIR_Done,
+ // Label 739: @23731
+ GIM_Try, /*On fail goto*//*Label 740*/ 23765, // Rule ID 129 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 129,
+ GIR_Done,
+ // Label 740: @23765
+ GIM_Try, /*On fail goto*//*Label 741*/ 23799, // Rule ID 131 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 131,
+ GIR_Done,
+ // Label 741: @23799
+ GIM_Try, /*On fail goto*//*Label 742*/ 23852, // Rule ID 132 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 132,
+ GIR_Done,
+ // Label 742: @23852
+ GIM_Try, /*On fail goto*//*Label 743*/ 23905, // Rule ID 134 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 134,
+ GIR_Done,
+ // Label 743: @23905
+ GIM_Try, /*On fail goto*//*Label 744*/ 23958, // Rule ID 135 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 135,
+ GIR_Done,
+ // Label 744: @23958
+ GIM_Try, /*On fail goto*//*Label 745*/ 24011, // Rule ID 137 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 137,
+ GIR_Done,
+ // Label 745: @24011
+ GIM_Reject,
+ // Label 713: @24012
+ GIM_Reject,
+ // Label 711: @24013
+ GIM_Try, /*On fail goto*//*Label 746*/ 24753,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 747*/ 24060, // Rule ID 103 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 103,
+ GIR_Done,
+ // Label 747: @24060
+ GIM_Try, /*On fail goto*//*Label 748*/ 24094, // Rule ID 112 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 112,
+ GIR_Done,
+ // Label 748: @24094
+ GIM_Try, /*On fail goto*//*Label 749*/ 24135, // Rule ID 94 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 94,
+ GIR_Done,
+ // Label 749: @24135
+ GIM_Try, /*On fail goto*//*Label 750*/ 24176, // Rule ID 100 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 100,
+ GIR_Done,
+ // Label 750: @24176
+ GIM_Try, /*On fail goto*//*Label 751*/ 24236, // Rule ID 109 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 109,
+ GIR_Done,
+ // Label 751: @24236
+ GIM_Try, /*On fail goto*//*Label 752*/ 24297, // Rule ID 118 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
+ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12,
+ // MIs[1] Operand 1
+ // No operand predicates
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 118,
+ GIR_Done,
+ // Label 752: @24297
+ GIM_Try, /*On fail goto*//*Label 753*/ 24331, // Rule ID 91 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 91,
+ GIR_Done,
+ // Label 753: @24331
+ GIM_Try, /*On fail goto*//*Label 754*/ 24365, // Rule ID 97 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 97,
+ GIR_Done,
+ // Label 754: @24365
+ GIM_Try, /*On fail goto*//*Label 755*/ 24418, // Rule ID 106 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 106,
+ GIR_Done,
+ // Label 755: @24418
+ GIM_Try, /*On fail goto*//*Label 756*/ 24472, // Rule ID 115 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 115,
+ GIR_Done,
+ // Label 756: @24472
+ GIM_Try, /*On fail goto*//*Label 757*/ 24506, // Rule ID 121 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 121,
+ GIR_Done,
+ // Label 757: @24506
+ GIM_Try, /*On fail goto*//*Label 758*/ 24559, // Rule ID 124 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 124,
+ GIR_Done,
+ // Label 758: @24559
+ GIM_Try, /*On fail goto*//*Label 759*/ 24612, // Rule ID 127 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 127,
+ GIR_Done,
+ // Label 759: @24612
+ GIM_Try, /*On fail goto*//*Label 760*/ 24646, // Rule ID 130 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 130,
+ GIR_Done,
+ // Label 760: @24646
+ GIM_Try, /*On fail goto*//*Label 761*/ 24699, // Rule ID 133 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 133,
+ GIR_Done,
+ // Label 761: @24699
+ GIM_Try, /*On fail goto*//*Label 762*/ 24752, // Rule ID 136 //
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID,
+ // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 136,
+ GIR_Done,
+ // Label 762: @24752
+ GIM_Reject,
+ // Label 746: @24753
+ GIM_Reject,
+ // Label 712: @24754
+ GIM_Reject,
+ // Label 32: @24755
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 765*/ 25935,
+ /*GILLT_s32*//*Label 763*/ 24763,
+ /*GILLT_s64*//*Label 764*/ 25544,
+ // Label 763: @24763
+ GIM_Try, /*On fail goto*//*Label 766*/ 24851, // Rule ID 1124 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1124,
+ GIR_Done,
+ // Label 766: @24851
+ GIM_Try, /*On fail goto*//*Label 767*/ 24939, // Rule ID 1126 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1126,
+ GIR_Done,
+ // Label 767: @24939
+ GIM_Try, /*On fail goto*//*Label 768*/ 25046, // Rule ID 1127 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1127,
+ GIR_Done,
+ // Label 768: @25046
+ GIM_Try, /*On fail goto*//*Label 769*/ 25153, // Rule ID 1129 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1129,
+ GIR_Done,
+ // Label 769: @25153
+ GIM_Try, /*On fail goto*//*Label 770*/ 25241, // Rule ID 1267 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1267,
+ GIR_Done,
+ // Label 770: @25241
+ GIM_Try, /*On fail goto*//*Label 771*/ 25329, // Rule ID 1269 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1269,
+ GIR_Done,
+ // Label 771: @25329
+ GIM_Try, /*On fail goto*//*Label 772*/ 25436, // Rule ID 1270 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1270,
+ GIR_Done,
+ // Label 772: @25436
+ GIM_Try, /*On fail goto*//*Label 773*/ 25543, // Rule ID 1272 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i32] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1272,
+ GIR_Done,
+ // Label 773: @25543
+ GIM_Reject,
+ // Label 764: @25544
+ GIM_Try, /*On fail goto*//*Label 774*/ 25632, // Rule ID 1125 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ // (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i64] } (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1125,
+ GIR_Done,
+ // Label 774: @25632
+ GIM_Try, /*On fail goto*//*Label 775*/ 25739, // Rule ID 1128 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ // (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i64] } (AND:{ *:[i64] } (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1128,
+ GIR_Done,
+ // Label 775: @25739
+ GIM_Try, /*On fail goto*//*Label 776*/ 25827, // Rule ID 1268 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ // (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i64] } (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2))
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1268,
+ GIR_Done,
+ // Label 776: @25827
+ GIM_Try, /*On fail goto*//*Label 777*/ 25934, // Rule ID 1271 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ // MIs[0] Operand 1
+ GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ // (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i64] } (AND:{ *:[i64] } (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i64] })
+ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
+ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
+ GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
+ GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D,
+ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define,
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
+ GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0,
+ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0,
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1271,
+ GIR_Done,
+ // Label 777: @25934
+ GIM_Reject,
+ // Label 765: @25935
+ GIM_Reject,
+ // Label 33: @25936
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 780*/ 26022,
+ /*GILLT_s32*//*Label 778*/ 25944,
+ /*GILLT_s64*//*Label 779*/ 25990,
+ // Label 778: @25944
+ GIM_Try, /*On fail goto*//*Label 781*/ 25989,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 782*/ 25977, // Rule ID 479 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (mulhu:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULHU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 479,
+ GIR_Done,
+ // Label 782: @25977
+ GIM_Try, /*On fail goto*//*Label 783*/ 25988, // Rule ID 481 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (mulhu:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULHU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 481,
+ GIR_Done,
+ // Label 783: @25988
+ GIM_Reject,
+ // Label 781: @25989
+ GIM_Reject,
+ // Label 779: @25990
+ GIM_Try, /*On fail goto*//*Label 784*/ 26021, // Rule ID 480 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (mulhu:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MULHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULHU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 480,
+ GIR_Done,
+ // Label 784: @26021
+ GIM_Reject,
+ // Label 780: @26022
+ GIM_Reject,
+ // Label 34: @26023
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 787*/ 26109,
+ /*GILLT_s32*//*Label 785*/ 26031,
+ /*GILLT_s64*//*Label 786*/ 26077,
+ // Label 785: @26031
+ GIM_Try, /*On fail goto*//*Label 788*/ 26076,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 789*/ 26064, // Rule ID 476 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULH,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 476,
+ GIR_Done,
+ // Label 789: @26064
+ GIM_Try, /*On fail goto*//*Label 790*/ 26075, // Rule ID 478 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULH,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 478,
+ GIR_Done,
+ // Label 790: @26075
+ GIM_Reject,
+ // Label 788: @26076
+ GIM_Reject,
+ // Label 786: @26077
+ GIM_Try, /*On fail goto*//*Label 791*/ 26108, // Rule ID 477 //
+ GIM_CheckFeatures, GIFBS_HasStdExtM,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID,
+ // (mulhs:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MULH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULH,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 477,
+ GIR_Done,
+ // Label 791: @26108
+ GIM_Reject,
+ // Label 787: @26109
+ GIM_Reject,
+ // Label 35: @26110
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 794*/ 27244,
+ /*GILLT_s32*//*Label 792*/ 26118,
+ /*GILLT_s64*//*Label 793*/ 26681,
+ // Label 792: @26118
+ GIM_Try, /*On fail goto*//*Label 795*/ 26680,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 796*/ 26205, // Rule ID 1101 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1101,
+ GIR_Done,
+ // Label 796: @26205
+ GIM_Try, /*On fail goto*//*Label 797*/ 26274, // Rule ID 1102 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1102,
+ GIR_Done,
+ // Label 797: @26274
+ GIM_Try, /*On fail goto*//*Label 798*/ 26343, // Rule ID 1103 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1103,
+ GIR_Done,
+ // Label 798: @26343
+ GIM_Try, /*On fail goto*//*Label 799*/ 26399, // Rule ID 1098 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1098,
+ GIR_Done,
+ // Label 799: @26399
+ GIM_Try, /*On fail goto*//*Label 800*/ 26455, // Rule ID 1099 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1099,
+ GIR_Done,
+ // Label 800: @26455
+ GIM_Try, /*On fail goto*//*Label 801*/ 26511, // Rule ID 1100 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1100,
+ GIR_Done,
+ // Label 801: @26511
+ GIM_Try, /*On fail goto*//*Label 802*/ 26567, // Rule ID 1095 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1095,
+ GIR_Done,
+ // Label 802: @26567
+ GIM_Try, /*On fail goto*//*Label 803*/ 26623, // Rule ID 1096 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1096,
+ GIR_Done,
+ // Label 803: @26623
+ GIM_Try, /*On fail goto*//*Label 804*/ 26679, // Rule ID 1097 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1097,
+ GIR_Done,
+ // Label 804: @26679
+ GIM_Reject,
+ // Label 795: @26680
+ GIM_Reject,
+ // Label 793: @26681
+ GIM_Try, /*On fail goto*//*Label 805*/ 27243,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 806*/ 26768, // Rule ID 1244 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1244,
+ GIR_Done,
+ // Label 806: @26768
+ GIM_Try, /*On fail goto*//*Label 807*/ 26837, // Rule ID 1245 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1245,
+ GIR_Done,
+ // Label 807: @26837
+ GIM_Try, /*On fail goto*//*Label 808*/ 26906, // Rule ID 1246 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
+ GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ GIM_CheckIsSafeToFold, /*InsnID*/2,
+ // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1246,
+ GIR_Done,
+ // Label 808: @26906
+ GIM_Try, /*On fail goto*//*Label 809*/ 26962, // Rule ID 1241 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1241,
+ GIR_Done,
+ // Label 809: @26962
+ GIM_Try, /*On fail goto*//*Label 810*/ 27018, // Rule ID 1242 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1242,
+ GIR_Done,
+ // Label 810: @27018
+ GIM_Try, /*On fail goto*//*Label 811*/ 27074, // Rule ID 1243 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1243,
+ GIR_Done,
+ // Label 811: @27074
+ GIM_Try, /*On fail goto*//*Label 812*/ 27130, // Rule ID 1238 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1238,
+ GIR_Done,
+ // Label 812: @27130
+ GIM_Try, /*On fail goto*//*Label 813*/ 27186, // Rule ID 1239 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1239,
+ GIR_Done,
+ // Label 813: @27186
+ GIM_Try, /*On fail goto*//*Label 814*/ 27242, // Rule ID 1240 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID,
+ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+ GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG,
+ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckIsSafeToFold, /*InsnID*/1,
+ // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1240,
+ GIR_Done,
+ // Label 814: @27242
+ GIM_Reject,
+ // Label 805: @27243
+ GIM_Reject,
+ // Label 794: @27244
+ GIM_Reject,
+ // Label 36: @27245
+ GIM_Try, /*On fail goto*//*Label 815*/ 27272, // Rule ID 1211 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_D_S:{ *:[f64] } FPR32:{ *:[f32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_S,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1211,
+ GIR_Done,
+ // Label 815: @27272
+ GIM_Reject,
+ // Label 37: @27273
+ GIM_Try, /*On fail goto*//*Label 816*/ 27361,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 817*/ 27314, // Rule ID 1208 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1208,
+ GIR_Done,
+ // Label 817: @27314
+ GIM_Try, /*On fail goto*//*Label 818*/ 27337, // Rule ID 1209 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1209,
+ GIR_Done,
+ // Label 818: @27337
+ GIM_Try, /*On fail goto*//*Label 819*/ 27360, // Rule ID 1210 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1210,
+ GIR_Done,
+ // Label 819: @27360
+ GIM_Reject,
+ // Label 816: @27361
+ GIM_Reject,
+ // Label 38: @27362
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 822*/ 27540,
+ /*GILLT_s32*//*Label 820*/ 27370,
+ /*GILLT_s64*//*Label 821*/ 27478,
+ // Label 820: @27370
+ GIM_Try, /*On fail goto*//*Label 823*/ 27477,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 824*/ 27407, // Rule ID 1303 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1303,
+ GIR_Done,
+ // Label 824: @27407
+ GIM_Try, /*On fail goto*//*Label 825*/ 27430, // Rule ID 1305 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1305,
+ GIR_Done,
+ // Label 825: @27430
+ GIM_Try, /*On fail goto*//*Label 826*/ 27453, // Rule ID 1330 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1330,
+ GIR_Done,
+ // Label 826: @27453
+ GIM_Try, /*On fail goto*//*Label 827*/ 27476, // Rule ID 1332 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1332,
+ GIR_Done,
+ // Label 827: @27476
+ GIM_Reject,
+ // Label 823: @27477
+ GIM_Reject,
+ // Label 821: @27478
+ GIM_Try, /*On fail goto*//*Label 828*/ 27539,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 829*/ 27515, // Rule ID 1304 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1304,
+ GIR_Done,
+ // Label 829: @27515
+ GIM_Try, /*On fail goto*//*Label 830*/ 27538, // Rule ID 1331 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1331,
+ GIR_Done,
+ // Label 830: @27538
+ GIM_Reject,
+ // Label 828: @27539
+ GIM_Reject,
+ // Label 822: @27540
+ GIM_Reject,
+ // Label 39: @27541
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 833*/ 27719,
+ /*GILLT_s32*//*Label 831*/ 27549,
+ /*GILLT_s64*//*Label 832*/ 27657,
+ // Label 831: @27549
+ GIM_Try, /*On fail goto*//*Label 834*/ 27656,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 835*/ 27586, // Rule ID 1306 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1306,
+ GIR_Done,
+ // Label 835: @27586
+ GIM_Try, /*On fail goto*//*Label 836*/ 27609, // Rule ID 1308 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1308,
+ GIR_Done,
+ // Label 836: @27609
+ GIM_Try, /*On fail goto*//*Label 837*/ 27632, // Rule ID 1333 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_LU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1333,
+ GIR_Done,
+ // Label 837: @27632
+ GIM_Try, /*On fail goto*//*Label 838*/ 27655, // Rule ID 1335 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_LU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1335,
+ GIR_Done,
+ // Label 838: @27655
+ GIM_Reject,
+ // Label 834: @27656
+ GIM_Reject,
+ // Label 832: @27657
+ GIM_Try, /*On fail goto*//*Label 839*/ 27718,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 840*/ 27694, // Rule ID 1307 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_WU_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1307,
+ GIR_Done,
+ // Label 840: @27694
+ GIM_Try, /*On fail goto*//*Label 841*/ 27717, // Rule ID 1334 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_LU_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1334,
+ GIR_Done,
+ // Label 841: @27717
+ GIM_Reject,
+ // Label 839: @27718
+ GIM_Reject,
+ // Label 833: @27719
+ GIM_Reject,
+ // Label 40: @27720
+ GIM_Try, /*On fail goto*//*Label 842*/ 27896,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
+ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 2, /*)*//*default:*//*Label 845*/ 27774,
+ /*GILLT_s32*//*Label 843*/ 27734,
+ /*GILLT_s64*//*Label 844*/ 27754,
+ // Label 843: @27734
+ GIM_Try, /*On fail goto*//*Label 846*/ 27753, // Rule ID 1309 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1309,
+ GIR_Done,
+ // Label 846: @27753
+ GIM_Reject,
+ // Label 844: @27754
+ GIM_Try, /*On fail goto*//*Label 847*/ 27773, // Rule ID 1310 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_W:{ *:[f64] } GPR:{ *:[i64] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1310,
+ GIR_Done,
+ // Label 847: @27773
+ GIM_Reject,
+ // Label 845: @27774
+ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 2, /*)*//*default:*//*Label 850*/ 27860,
+ /*GILLT_s32*//*Label 848*/ 27782,
+ /*GILLT_s64*//*Label 849*/ 27828,
+ // Label 848: @27782
+ GIM_Try, /*On fail goto*//*Label 851*/ 27827,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 852*/ 27803, // Rule ID 1311 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_W,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1311,
+ GIR_Done,
+ // Label 852: @27803
+ GIM_Try, /*On fail goto*//*Label 853*/ 27826, // Rule ID 1336 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_L:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1336,
+ GIR_Done,
+ // Label 853: @27826
+ GIM_Reject,
+ // Label 851: @27827
+ GIM_Reject,
+ // Label 849: @27828
+ GIM_Try, /*On fail goto*//*Label 854*/ 27859, // Rule ID 1337 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_L:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1337,
+ GIR_Done,
+ // Label 854: @27859
+ GIM_Reject,
+ // Label 850: @27860
+ GIM_Try, /*On fail goto*//*Label 855*/ 27895, // Rule ID 1338 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_L:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1338,
+ GIR_Done,
+ // Label 855: @27895
+ GIM_Reject,
+ // Label 842: @27896
+ GIM_Reject,
+ // Label 41: @27897
+ GIM_Try, /*On fail goto*//*Label 856*/ 28073,
+ GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
+ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 2, /*)*//*default:*//*Label 859*/ 27951,
+ /*GILLT_s32*//*Label 857*/ 27911,
+ /*GILLT_s64*//*Label 858*/ 27931,
+ // Label 857: @27911
+ GIM_Try, /*On fail goto*//*Label 860*/ 27930, // Rule ID 1312 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_WU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1312,
+ GIR_Done,
+ // Label 860: @27930
+ GIM_Reject,
+ // Label 858: @27931
+ GIM_Try, /*On fail goto*//*Label 861*/ 27950, // Rule ID 1313 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i64] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_WU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1313,
+ GIR_Done,
+ // Label 861: @27950
+ GIM_Reject,
+ // Label 859: @27951
+ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 2, /*)*//*default:*//*Label 864*/ 28037,
+ /*GILLT_s32*//*Label 862*/ 27959,
+ /*GILLT_s64*//*Label 863*/ 28005,
+ // Label 862: @27959
+ GIM_Try, /*On fail goto*//*Label 865*/ 28004,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ GIM_Try, /*On fail goto*//*Label 866*/ 27980, // Rule ID 1314 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32,
+ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_WU,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1314,
+ GIR_Done,
+ // Label 866: @27980
+ GIM_Try, /*On fail goto*//*Label 867*/ 28003, // Rule ID 1339 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1339,
+ GIR_Done,
+ // Label 867: @28003
+ GIM_Reject,
+ // Label 865: @28004
+ GIM_Reject,
+ // Label 863: @28005
+ GIM_Try, /*On fail goto*//*Label 868*/ 28036, // Rule ID 1340 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1340,
+ GIR_Done,
+ // Label 868: @28036
+ GIM_Reject,
+ // Label 864: @28037
+ GIM_Try, /*On fail goto*//*Label 869*/ 28072, // Rule ID 1341 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID,
+ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1341,
+ GIR_Done,
+ // Label 869: @28072
+ GIM_Reject,
+ // Label 856: @28073
+ GIM_Reject,
+ // Label 42: @28074
+ GIM_Try, /*On fail goto*//*Label 870*/ 28086, // Rule ID 3 //
+ // MIs[0] imm20
+ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
+ // (br (bb:{ *:[Other] }):$imm20) => (PseudoBR (bb:{ *:[Other] }):$imm20)
+ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::PseudoBR,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 3,
+ GIR_Done,
+ // Label 870: @28086
+ GIM_Reject,
+ // Label 43: @28087
+ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 873*/ 28265,
+ /*GILLT_s32*//*Label 871*/ 28095,
+ /*GILLT_s64*//*Label 872*/ 28180,
+ // Label 871: @28095
+ GIM_Try, /*On fail goto*//*Label 874*/ 28179,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID,
+ GIM_Try, /*On fail goto*//*Label 875*/ 28132, // Rule ID 1085 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1085,
+ GIR_Done,
+ // Label 875: @28132
+ GIM_Try, /*On fail goto*//*Label 876*/ 28155, // Rule ID 1086 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1086,
+ GIR_Done,
+ // Label 876: @28155
+ GIM_Try, /*On fail goto*//*Label 877*/ 28178, // Rule ID 1087 //
+ GIM_CheckFeatures, GIFBS_HasStdExtF,
+ // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1087,
+ GIR_Done,
+ // Label 877: @28178
+ GIM_Reject,
+ // Label 874: @28179
+ GIM_Reject,
+ // Label 872: @28180
+ GIM_Try, /*On fail goto*//*Label 878*/ 28264,
+ GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID,
+ GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID,
+ GIM_Try, /*On fail goto*//*Label 879*/ 28217, // Rule ID 1224 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1224,
+ GIR_Done,
+ // Label 879: @28217
+ GIM_Try, /*On fail goto*//*Label 880*/ 28240, // Rule ID 1225 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1225,
+ GIR_Done,
+ // Label 880: @28240
+ GIM_Try, /*On fail goto*//*Label 881*/ 28263, // Rule ID 1226 //
+ GIM_CheckFeatures, GIFBS_HasStdExtD,
+ // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] })
+ GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D,
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
+ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
+ GIR_AddImm, /*InsnID*/0, /*Imm*/7,
+ GIR_EraseFromParent, /*InsnID*/0,
+ GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+ // GIR_Coverage, 1226,
+ GIR_Done,
+ // Label 881: @28263
+ GIM_Reject,
+ // Label 878: @28264
+ GIM_Reject,
+ // Label 873: @28265
+ GIM_Reject,
+ // Label 44: @28266
+ GIM_Reject,
+ };
+ return MatchTable0;
+}
+#endif // ifdef GET_GLOBALISEL_IMPL
+#ifdef GET_GLOBALISEL_PREDICATES_DECL
+PredicateBitset AvailableModuleFeatures;
+mutable PredicateBitset AvailableFunctionFeatures;
+PredicateBitset getAvailableFeatures() const {
+ return AvailableModuleFeatures | AvailableFunctionFeatures;
+}
+PredicateBitset
+computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const;
+PredicateBitset
+computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget,
+ const MachineFunction *MF) const;
+void setupGeneratedPerFunctionState(MachineFunction &MF) override;
+#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
+#ifdef GET_GLOBALISEL_PREDICATES_INIT
+AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
+AvailableFunctionFeatures()
+#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenInstrInfo.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenInstrInfo.inc
new file mode 100644
index 0000000..c2fe2c4
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenInstrInfo.inc
@@ -0,0 +1,2962 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Instruction Enum Values and Descriptors *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_INSTRINFO_ENUM
+#undef GET_INSTRINFO_ENUM
+namespace llvm {
+
+namespace RISCV {
+ enum {
+ PHI = 0,
+ INLINEASM = 1,
+ INLINEASM_BR = 2,
+ CFI_INSTRUCTION = 3,
+ EH_LABEL = 4,
+ GC_LABEL = 5,
+ ANNOTATION_LABEL = 6,
+ KILL = 7,
+ EXTRACT_SUBREG = 8,
+ INSERT_SUBREG = 9,
+ IMPLICIT_DEF = 10,
+ SUBREG_TO_REG = 11,
+ COPY_TO_REGCLASS = 12,
+ DBG_VALUE = 13,
+ DBG_LABEL = 14,
+ REG_SEQUENCE = 15,
+ COPY = 16,
+ BUNDLE = 17,
+ LIFETIME_START = 18,
+ LIFETIME_END = 19,
+ STACKMAP = 20,
+ FENTRY_CALL = 21,
+ PATCHPOINT = 22,
+ LOAD_STACK_GUARD = 23,
+ STATEPOINT = 24,
+ LOCAL_ESCAPE = 25,
+ FAULTING_OP = 26,
+ PATCHABLE_OP = 27,
+ PATCHABLE_FUNCTION_ENTER = 28,
+ PATCHABLE_RET = 29,
+ PATCHABLE_FUNCTION_EXIT = 30,
+ PATCHABLE_TAIL_CALL = 31,
+ PATCHABLE_EVENT_CALL = 32,
+ PATCHABLE_TYPED_EVENT_CALL = 33,
+ ICALL_BRANCH_FUNNEL = 34,
+ G_ADD = 35,
+ G_SUB = 36,
+ G_MUL = 37,
+ G_SDIV = 38,
+ G_UDIV = 39,
+ G_SREM = 40,
+ G_UREM = 41,
+ G_AND = 42,
+ G_OR = 43,
+ G_XOR = 44,
+ G_IMPLICIT_DEF = 45,
+ G_PHI = 46,
+ G_FRAME_INDEX = 47,
+ G_GLOBAL_VALUE = 48,
+ G_EXTRACT = 49,
+ G_UNMERGE_VALUES = 50,
+ G_INSERT = 51,
+ G_MERGE_VALUES = 52,
+ G_BUILD_VECTOR = 53,
+ G_BUILD_VECTOR_TRUNC = 54,
+ G_CONCAT_VECTORS = 55,
+ G_PTRTOINT = 56,
+ G_INTTOPTR = 57,
+ G_BITCAST = 58,
+ G_INTRINSIC_TRUNC = 59,
+ G_INTRINSIC_ROUND = 60,
+ G_READCYCLECOUNTER = 61,
+ G_LOAD = 62,
+ G_SEXTLOAD = 63,
+ G_ZEXTLOAD = 64,
+ G_INDEXED_LOAD = 65,
+ G_INDEXED_SEXTLOAD = 66,
+ G_INDEXED_ZEXTLOAD = 67,
+ G_STORE = 68,
+ G_INDEXED_STORE = 69,
+ G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70,
+ G_ATOMIC_CMPXCHG = 71,
+ G_ATOMICRMW_XCHG = 72,
+ G_ATOMICRMW_ADD = 73,
+ G_ATOMICRMW_SUB = 74,
+ G_ATOMICRMW_AND = 75,
+ G_ATOMICRMW_NAND = 76,
+ G_ATOMICRMW_OR = 77,
+ G_ATOMICRMW_XOR = 78,
+ G_ATOMICRMW_MAX = 79,
+ G_ATOMICRMW_MIN = 80,
+ G_ATOMICRMW_UMAX = 81,
+ G_ATOMICRMW_UMIN = 82,
+ G_ATOMICRMW_FADD = 83,
+ G_ATOMICRMW_FSUB = 84,
+ G_FENCE = 85,
+ G_BRCOND = 86,
+ G_BRINDIRECT = 87,
+ G_INTRINSIC = 88,
+ G_INTRINSIC_W_SIDE_EFFECTS = 89,
+ G_ANYEXT = 90,
+ G_TRUNC = 91,
+ G_CONSTANT = 92,
+ G_FCONSTANT = 93,
+ G_VASTART = 94,
+ G_VAARG = 95,
+ G_SEXT = 96,
+ G_SEXT_INREG = 97,
+ G_ZEXT = 98,
+ G_SHL = 99,
+ G_LSHR = 100,
+ G_ASHR = 101,
+ G_ICMP = 102,
+ G_FCMP = 103,
+ G_SELECT = 104,
+ G_UADDO = 105,
+ G_UADDE = 106,
+ G_USUBO = 107,
+ G_USUBE = 108,
+ G_SADDO = 109,
+ G_SADDE = 110,
+ G_SSUBO = 111,
+ G_SSUBE = 112,
+ G_UMULO = 113,
+ G_SMULO = 114,
+ G_UMULH = 115,
+ G_SMULH = 116,
+ G_FADD = 117,
+ G_FSUB = 118,
+ G_FMUL = 119,
+ G_FMA = 120,
+ G_FMAD = 121,
+ G_FDIV = 122,
+ G_FREM = 123,
+ G_FPOW = 124,
+ G_FEXP = 125,
+ G_FEXP2 = 126,
+ G_FLOG = 127,
+ G_FLOG2 = 128,
+ G_FLOG10 = 129,
+ G_FNEG = 130,
+ G_FPEXT = 131,
+ G_FPTRUNC = 132,
+ G_FPTOSI = 133,
+ G_FPTOUI = 134,
+ G_SITOFP = 135,
+ G_UITOFP = 136,
+ G_FABS = 137,
+ G_FCOPYSIGN = 138,
+ G_FCANONICALIZE = 139,
+ G_FMINNUM = 140,
+ G_FMAXNUM = 141,
+ G_FMINNUM_IEEE = 142,
+ G_FMAXNUM_IEEE = 143,
+ G_FMINIMUM = 144,
+ G_FMAXIMUM = 145,
+ G_PTR_ADD = 146,
+ G_PTR_MASK = 147,
+ G_SMIN = 148,
+ G_SMAX = 149,
+ G_UMIN = 150,
+ G_UMAX = 151,
+ G_BR = 152,
+ G_BRJT = 153,
+ G_INSERT_VECTOR_ELT = 154,
+ G_EXTRACT_VECTOR_ELT = 155,
+ G_SHUFFLE_VECTOR = 156,
+ G_CTTZ = 157,
+ G_CTTZ_ZERO_UNDEF = 158,
+ G_CTLZ = 159,
+ G_CTLZ_ZERO_UNDEF = 160,
+ G_CTPOP = 161,
+ G_BSWAP = 162,
+ G_BITREVERSE = 163,
+ G_FCEIL = 164,
+ G_FCOS = 165,
+ G_FSIN = 166,
+ G_FSQRT = 167,
+ G_FFLOOR = 168,
+ G_FRINT = 169,
+ G_FNEARBYINT = 170,
+ G_ADDRSPACE_CAST = 171,
+ G_BLOCK_ADDR = 172,
+ G_JUMP_TABLE = 173,
+ G_DYN_STACKALLOC = 174,
+ G_READ_REGISTER = 175,
+ G_WRITE_REGISTER = 176,
+ ADJCALLSTACKDOWN = 177,
+ ADJCALLSTACKUP = 178,
+ BuildPairF64Pseudo = 179,
+ PseudoAddTPRel = 180,
+ PseudoAtomicLoadNand32 = 181,
+ PseudoAtomicLoadNand64 = 182,
+ PseudoBR = 183,
+ PseudoBRIND = 184,
+ PseudoCALL = 185,
+ PseudoCALLIndirect = 186,
+ PseudoCALLReg = 187,
+ PseudoCmpXchg32 = 188,
+ PseudoCmpXchg64 = 189,
+ PseudoFLD = 190,
+ PseudoFLW = 191,
+ PseudoFSD = 192,
+ PseudoFSW = 193,
+ PseudoLA = 194,
+ PseudoLA_TLS_GD = 195,
+ PseudoLA_TLS_IE = 196,
+ PseudoLB = 197,
+ PseudoLBU = 198,
+ PseudoLD = 199,
+ PseudoLH = 200,
+ PseudoLHU = 201,
+ PseudoLI = 202,
+ PseudoLLA = 203,
+ PseudoLW = 204,
+ PseudoLWU = 205,
+ PseudoMaskedAtomicLoadAdd32 = 206,
+ PseudoMaskedAtomicLoadMax32 = 207,
+ PseudoMaskedAtomicLoadMin32 = 208,
+ PseudoMaskedAtomicLoadNand32 = 209,
+ PseudoMaskedAtomicLoadSub32 = 210,
+ PseudoMaskedAtomicLoadUMax32 = 211,
+ PseudoMaskedAtomicLoadUMin32 = 212,
+ PseudoMaskedAtomicSwap32 = 213,
+ PseudoMaskedCmpXchg32 = 214,
+ PseudoRET = 215,
+ PseudoSB = 216,
+ PseudoSD = 217,
+ PseudoSH = 218,
+ PseudoSW = 219,
+ PseudoTAIL = 220,
+ PseudoTAILIndirect = 221,
+ ReadCycleWide = 222,
+ Select_FPR32_Using_CC_GPR = 223,
+ Select_FPR64_Using_CC_GPR = 224,
+ Select_GPR_Using_CC_GPR = 225,
+ SplitF64Pseudo = 226,
+ ADD = 227,
+ ADDI = 228,
+ ADDIW = 229,
+ ADDW = 230,
+ AMOADD_D = 231,
+ AMOADD_D_AQ = 232,
+ AMOADD_D_AQ_RL = 233,
+ AMOADD_D_RL = 234,
+ AMOADD_W = 235,
+ AMOADD_W_AQ = 236,
+ AMOADD_W_AQ_RL = 237,
+ AMOADD_W_RL = 238,
+ AMOAND_D = 239,
+ AMOAND_D_AQ = 240,
+ AMOAND_D_AQ_RL = 241,
+ AMOAND_D_RL = 242,
+ AMOAND_W = 243,
+ AMOAND_W_AQ = 244,
+ AMOAND_W_AQ_RL = 245,
+ AMOAND_W_RL = 246,
+ AMOMAXU_D = 247,
+ AMOMAXU_D_AQ = 248,
+ AMOMAXU_D_AQ_RL = 249,
+ AMOMAXU_D_RL = 250,
+ AMOMAXU_W = 251,
+ AMOMAXU_W_AQ = 252,
+ AMOMAXU_W_AQ_RL = 253,
+ AMOMAXU_W_RL = 254,
+ AMOMAX_D = 255,
+ AMOMAX_D_AQ = 256,
+ AMOMAX_D_AQ_RL = 257,
+ AMOMAX_D_RL = 258,
+ AMOMAX_W = 259,
+ AMOMAX_W_AQ = 260,
+ AMOMAX_W_AQ_RL = 261,
+ AMOMAX_W_RL = 262,
+ AMOMINU_D = 263,
+ AMOMINU_D_AQ = 264,
+ AMOMINU_D_AQ_RL = 265,
+ AMOMINU_D_RL = 266,
+ AMOMINU_W = 267,
+ AMOMINU_W_AQ = 268,
+ AMOMINU_W_AQ_RL = 269,
+ AMOMINU_W_RL = 270,
+ AMOMIN_D = 271,
+ AMOMIN_D_AQ = 272,
+ AMOMIN_D_AQ_RL = 273,
+ AMOMIN_D_RL = 274,
+ AMOMIN_W = 275,
+ AMOMIN_W_AQ = 276,
+ AMOMIN_W_AQ_RL = 277,
+ AMOMIN_W_RL = 278,
+ AMOOR_D = 279,
+ AMOOR_D_AQ = 280,
+ AMOOR_D_AQ_RL = 281,
+ AMOOR_D_RL = 282,
+ AMOOR_W = 283,
+ AMOOR_W_AQ = 284,
+ AMOOR_W_AQ_RL = 285,
+ AMOOR_W_RL = 286,
+ AMOSWAP_D = 287,
+ AMOSWAP_D_AQ = 288,
+ AMOSWAP_D_AQ_RL = 289,
+ AMOSWAP_D_RL = 290,
+ AMOSWAP_W = 291,
+ AMOSWAP_W_AQ = 292,
+ AMOSWAP_W_AQ_RL = 293,
+ AMOSWAP_W_RL = 294,
+ AMOXOR_D = 295,
+ AMOXOR_D_AQ = 296,
+ AMOXOR_D_AQ_RL = 297,
+ AMOXOR_D_RL = 298,
+ AMOXOR_W = 299,
+ AMOXOR_W_AQ = 300,
+ AMOXOR_W_AQ_RL = 301,
+ AMOXOR_W_RL = 302,
+ AND = 303,
+ ANDI = 304,
+ AUIPC = 305,
+ BEQ = 306,
+ BGE = 307,
+ BGEU = 308,
+ BLT = 309,
+ BLTU = 310,
+ BNE = 311,
+ CSRRC = 312,
+ CSRRCI = 313,
+ CSRRS = 314,
+ CSRRSI = 315,
+ CSRRW = 316,
+ CSRRWI = 317,
+ C_ADD = 318,
+ C_ADDI = 319,
+ C_ADDI16SP = 320,
+ C_ADDI4SPN = 321,
+ C_ADDIW = 322,
+ C_ADDI_HINT_IMM_ZERO = 323,
+ C_ADDI_HINT_X0 = 324,
+ C_ADDI_NOP = 325,
+ C_ADDW = 326,
+ C_ADD_HINT = 327,
+ C_AND = 328,
+ C_ANDI = 329,
+ C_BEQZ = 330,
+ C_BNEZ = 331,
+ C_EBREAK = 332,
+ C_FLD = 333,
+ C_FLDSP = 334,
+ C_FLW = 335,
+ C_FLWSP = 336,
+ C_FSD = 337,
+ C_FSDSP = 338,
+ C_FSW = 339,
+ C_FSWSP = 340,
+ C_J = 341,
+ C_JAL = 342,
+ C_JALR = 343,
+ C_JR = 344,
+ C_LD = 345,
+ C_LDSP = 346,
+ C_LI = 347,
+ C_LI_HINT = 348,
+ C_LUI = 349,
+ C_LUI_HINT = 350,
+ C_LW = 351,
+ C_LWSP = 352,
+ C_MV = 353,
+ C_MV_HINT = 354,
+ C_NOP = 355,
+ C_NOP_HINT = 356,
+ C_OR = 357,
+ C_SD = 358,
+ C_SDSP = 359,
+ C_SLLI = 360,
+ C_SLLI64_HINT = 361,
+ C_SLLI_HINT = 362,
+ C_SRAI = 363,
+ C_SRAI64_HINT = 364,
+ C_SRLI = 365,
+ C_SRLI64_HINT = 366,
+ C_SUB = 367,
+ C_SUBW = 368,
+ C_SW = 369,
+ C_SWSP = 370,
+ C_UNIMP = 371,
+ C_XOR = 372,
+ DIV = 373,
+ DIVU = 374,
+ DIVUW = 375,
+ DIVW = 376,
+ EBREAK = 377,
+ ECALL = 378,
+ FADD_D = 379,
+ FADD_S = 380,
+ FCLASS_D = 381,
+ FCLASS_S = 382,
+ FCVT_D_L = 383,
+ FCVT_D_LU = 384,
+ FCVT_D_S = 385,
+ FCVT_D_W = 386,
+ FCVT_D_WU = 387,
+ FCVT_LU_D = 388,
+ FCVT_LU_S = 389,
+ FCVT_L_D = 390,
+ FCVT_L_S = 391,
+ FCVT_S_D = 392,
+ FCVT_S_L = 393,
+ FCVT_S_LU = 394,
+ FCVT_S_W = 395,
+ FCVT_S_WU = 396,
+ FCVT_WU_D = 397,
+ FCVT_WU_S = 398,
+ FCVT_W_D = 399,
+ FCVT_W_S = 400,
+ FDIV_D = 401,
+ FDIV_S = 402,
+ FENCE = 403,
+ FENCE_I = 404,
+ FENCE_TSO = 405,
+ FEQ_D = 406,
+ FEQ_S = 407,
+ FLD = 408,
+ FLE_D = 409,
+ FLE_S = 410,
+ FLT_D = 411,
+ FLT_S = 412,
+ FLW = 413,
+ FMADD_D = 414,
+ FMADD_S = 415,
+ FMAX_D = 416,
+ FMAX_S = 417,
+ FMIN_D = 418,
+ FMIN_S = 419,
+ FMSUB_D = 420,
+ FMSUB_S = 421,
+ FMUL_D = 422,
+ FMUL_S = 423,
+ FMV_D_X = 424,
+ FMV_W_X = 425,
+ FMV_X_D = 426,
+ FMV_X_W = 427,
+ FNMADD_D = 428,
+ FNMADD_S = 429,
+ FNMSUB_D = 430,
+ FNMSUB_S = 431,
+ FSD = 432,
+ FSGNJN_D = 433,
+ FSGNJN_S = 434,
+ FSGNJX_D = 435,
+ FSGNJX_S = 436,
+ FSGNJ_D = 437,
+ FSGNJ_S = 438,
+ FSQRT_D = 439,
+ FSQRT_S = 440,
+ FSUB_D = 441,
+ FSUB_S = 442,
+ FSW = 443,
+ JAL = 444,
+ JALR = 445,
+ LB = 446,
+ LBU = 447,
+ LD = 448,
+ LH = 449,
+ LHU = 450,
+ LR_D = 451,
+ LR_D_AQ = 452,
+ LR_D_AQ_RL = 453,
+ LR_D_RL = 454,
+ LR_W = 455,
+ LR_W_AQ = 456,
+ LR_W_AQ_RL = 457,
+ LR_W_RL = 458,
+ LUI = 459,
+ LW = 460,
+ LWU = 461,
+ MRET = 462,
+ MUL = 463,
+ MULH = 464,
+ MULHSU = 465,
+ MULHU = 466,
+ MULW = 467,
+ OR = 468,
+ ORI = 469,
+ REM = 470,
+ REMU = 471,
+ REMUW = 472,
+ REMW = 473,
+ SB = 474,
+ SC_D = 475,
+ SC_D_AQ = 476,
+ SC_D_AQ_RL = 477,
+ SC_D_RL = 478,
+ SC_W = 479,
+ SC_W_AQ = 480,
+ SC_W_AQ_RL = 481,
+ SC_W_RL = 482,
+ SD = 483,
+ SFENCE_VMA = 484,
+ SH = 485,
+ SLL = 486,
+ SLLI = 487,
+ SLLIW = 488,
+ SLLW = 489,
+ SLT = 490,
+ SLTI = 491,
+ SLTIU = 492,
+ SLTU = 493,
+ SRA = 494,
+ SRAI = 495,
+ SRAIW = 496,
+ SRAW = 497,
+ SRET = 498,
+ SRL = 499,
+ SRLI = 500,
+ SRLIW = 501,
+ SRLW = 502,
+ SUB = 503,
+ SUBW = 504,
+ SW = 505,
+ UNIMP = 506,
+ URET = 507,
+ WFI = 508,
+ XOR = 509,
+ XORI = 510,
+ INSTRUCTION_LIST_END = 511
+ };
+
+} // end namespace RISCV
+} // end namespace llvm
+#endif // GET_INSTRINFO_ENUM
+
+#ifdef GET_INSTRINFO_SCHED_ENUM
+#undef GET_INSTRINFO_SCHED_ENUM
+namespace llvm {
+
+namespace RISCV {
+namespace Sched {
+ enum {
+ NoInstrModel = 0,
+ WriteIALU_ReadIALU_ReadIALU = 1,
+ WriteIALU_ReadIALU = 2,
+ WriteIALU32_ReadIALU32 = 3,
+ WriteIALU32_ReadIALU32_ReadIALU32 = 4,
+ WriteAtomicD_ReadAtomicDA_ReadAtomicDD = 5,
+ WriteAtomicW_ReadAtomicWA_ReadAtomicWD = 6,
+ WriteIALU = 7,
+ WriteJmp = 8,
+ WriteCSR_ReadCSR = 9,
+ WriteCSR = 10,
+ WriteFLD64_ReadMemBase = 11,
+ WriteFLD32_ReadMemBase = 12,
+ WriteFST64_ReadStoreData_ReadMemBase = 13,
+ WriteFST32_ReadStoreData_ReadMemBase = 14,
+ WriteJal = 15,
+ WriteJalr_ReadJalr = 16,
+ WriteJmpReg = 17,
+ WriteLDD_ReadMemBase = 18,
+ WriteLDW_ReadMemBase = 19,
+ WriteNop = 20,
+ WriteSTD_ReadStoreData_ReadMemBase = 21,
+ WriteShift_ReadShift = 22,
+ WriteSTW_ReadStoreData_ReadMemBase = 23,
+ WriteIDiv_ReadIDiv_ReadIDiv = 24,
+ WriteIDiv32_ReadIDiv32_ReadIDiv32 = 25,
+ WriteFALU64_ReadFALU64_ReadFALU64 = 26,
+ WriteFALU32_ReadFALU32_ReadFALU32 = 27,
+ WriteFClass64_ReadFClass64 = 28,
+ WriteFClass32_ReadFClass32 = 29,
+ WriteFCvtI64ToF64_ReadFCvtI64ToF64 = 30,
+ WriteFCvtF32ToF64_ReadFCvtF32ToF64 = 31,
+ WriteFCvtI32ToF64_ReadFCvtI32ToF64 = 32,
+ WriteFCvtF64ToI64_ReadFCvtF64ToI64 = 33,
+ WriteFCvtF32ToI64_ReadFCvtF32ToI64 = 34,
+ WriteFCvtF64ToF32_ReadFCvtF64ToF32 = 35,
+ WriteFCvtI64ToF32_ReadFCvtI64ToF32 = 36,
+ WriteFCvtI32ToF32_ReadFCvtI32ToF32 = 37,
+ WriteFCvtF64ToI32_ReadFCvtF64ToI32 = 38,
+ WriteFCvtF32ToI32_ReadFCvtF32ToI32 = 39,
+ WriteFDiv32_ReadFDiv32_ReadFDiv32 = 40,
+ WriteFCmp64_ReadFCmp64_ReadFCmp64 = 41,
+ WriteFCmp32_ReadFCmp32_ReadFCmp32 = 42,
+ WriteFMulAdd64_ReadFMulAdd64_ReadFMulAdd64_ReadFMulAdd64 = 43,
+ WriteFMulAdd32_ReadFMulAdd32_ReadFMulAdd32_ReadFMulAdd32 = 44,
+ WriteFMulSub64_ReadFMulSub64_ReadFMulSub64_ReadFMulSub64 = 45,
+ WriteFMulSub32_ReadFMulSub32_ReadFMulSub32_ReadFMulSub32 = 46,
+ WriteFMul32_ReadFMul32_ReadFMul32 = 47,
+ WriteFMovI64ToF64_ReadFMovI64ToF64 = 48,
+ WriteFMovI32ToF32_ReadFMovI32ToF32 = 49,
+ WriteFMovF64ToI64_ReadFMovF64ToI64 = 50,
+ WriteFMovF32ToI32_ReadFMovF32ToI32 = 51,
+ WriteFSqrt32_ReadFSqrt32 = 52,
+ WriteLDB_ReadMemBase = 53,
+ WriteLDH_ReadMemBase = 54,
+ WriteAtomicLDD_ReadAtomicLDD = 55,
+ WriteAtomicLDW_ReadAtomicLDW = 56,
+ WriteLDWU_ReadMemBase = 57,
+ WriteIMul_ReadIMul_ReadIMul = 58,
+ WriteIMul32_ReadIMul32_ReadIMul32 = 59,
+ WriteSTB_ReadStoreData_ReadMemBase = 60,
+ WriteAtomicSTD_ReadAtomicSTD_ReadAtomicSTD = 61,
+ WriteAtomicSTW_ReadAtomicSTW_ReadAtomicSTW = 62,
+ WriteSTH_ReadStoreData_ReadMemBase = 63,
+ WriteShift32_ReadShift32 = 64,
+ COPY = 65,
+ SCHED_LIST_END = 66
+ };
+} // end namespace Sched
+} // end namespace RISCV
+} // end namespace llvm
+#endif // GET_INSTRINFO_SCHED_ENUM
+
+#ifdef GET_INSTRINFO_MC_DESC
+#undef GET_INSTRINFO_MC_DESC
+namespace llvm {
+
+static const MCPhysReg ImplicitList1[] = { RISCV::X2, 0 };
+static const MCPhysReg ImplicitList2[] = { RISCV::X1, 0 };
+
+static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo38[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo39[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo40[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo41[] = { { -1, 0, RISCVOp::OPERAND_SIMM21_LSB0, 0 }, };
+static const MCOperandInfo OperandInfo42[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_SIMM12, 0 }, };
+static const MCOperandInfo OperandInfo43[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo44[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo45[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo46[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo47[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo48[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo49[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo50[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo51[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo52[] = { { RISCV::GPRTCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo53[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo54[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo55[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo56[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo57[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo58[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo59[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_SIMM12, 0 }, };
+static const MCOperandInfo OperandInfo60[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_UIMM20, 0 }, };
+static const MCOperandInfo OperandInfo61[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_SIMM13_LSB0, 0 }, };
+static const MCOperandInfo OperandInfo62[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_UIMM12, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo63[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_UIMM12, 0 }, { -1, 0, RISCVOp::OPERAND_UIMM5, 0 }, };
+static const MCOperandInfo OperandInfo64[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo65[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo66[] = { { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo67[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo68[] = { { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo69[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo70[] = { { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo71[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo72[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo73[] = { { RISCV::FPR64CRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo74[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo75[] = { { RISCV::FPR32CRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo76[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo77[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo78[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo79[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo80[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo81[] = { { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo82[] = { { RISCV::GPRNoX0X2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo83[] = { { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo84[] = { { RISCV::GPRX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRNoX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo85[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::SPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo86[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo87[] = { { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
+static const MCOperandInfo OperandInfo88[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo89[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo90[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo91[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo92[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo93[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo94[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo95[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo96[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo97[] = { { -1, 0, RISCVOp::OPERAND_UIMM4, 0 }, { -1, 0, RISCVOp::OPERAND_UIMM4, 0 }, };
+static const MCOperandInfo OperandInfo98[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo99[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo100[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_SIMM12, 0 }, };
+static const MCOperandInfo OperandInfo101[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_SIMM12, 0 }, };
+static const MCOperandInfo OperandInfo102[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo103[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo104[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo105[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo106[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo107[] = { { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo108[] = { { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo109[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_SIMM21_LSB0, 0 }, };
+static const MCOperandInfo OperandInfo110[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_UIMMLOG2XLEN, 0 }, };
+static const MCOperandInfo OperandInfo111[] = { { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { RISCV::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, RISCVOp::OPERAND_UIMM5, 0 }, };
+
+extern const MCInstrDesc RISCVInsts[] = {
+ { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI
+ { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM
+ { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR
+ { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION
+ { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL
+ { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL
+ { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL
+ { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL
+ { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG
+ { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG
+ { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF
+ { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG
+ { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS
+ { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE
+ { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL
+ { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE
+ { 16, 2, 1, 0, 65, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY
+ { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE
+ { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START
+ { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END
+ { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP
+ { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL
+ { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT
+ { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD
+ { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT
+ { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE
+ { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP
+ { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP
+ { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER
+ { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET
+ { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT
+ { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL
+ { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL
+ { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL
+ { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL
+ { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #35 = G_ADD
+ { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #36 = G_SUB
+ { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #37 = G_MUL
+ { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #38 = G_SDIV
+ { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #39 = G_UDIV
+ { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #40 = G_SREM
+ { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #41 = G_UREM
+ { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #42 = G_AND
+ { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #43 = G_OR
+ { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = G_XOR
+ { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF
+ { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #46 = G_PHI
+ { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX
+ { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE
+ { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #49 = G_EXTRACT
+ { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES
+ { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #51 = G_INSERT
+ { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES
+ { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR
+ { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC
+ { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS
+ { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #56 = G_PTRTOINT
+ { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #57 = G_INTTOPTR
+ { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #58 = G_BITCAST
+ { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC
+ { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND
+ { 61, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #61 = G_READCYCLECOUNTER
+ { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #62 = G_LOAD
+ { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #63 = G_SEXTLOAD
+ { 64, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #64 = G_ZEXTLOAD
+ { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #65 = G_INDEXED_LOAD
+ { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #66 = G_INDEXED_SEXTLOAD
+ { 67, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #67 = G_INDEXED_ZEXTLOAD
+ { 68, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #68 = G_STORE
+ { 69, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_INDEXED_STORE
+ { 70, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
+ { 71, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMIC_CMPXCHG
+ { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_XCHG
+ { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_ADD
+ { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_SUB
+ { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_AND
+ { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_NAND
+ { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_OR
+ { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_XOR
+ { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MAX
+ { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_MIN
+ { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMAX
+ { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_UMIN
+ { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FADD
+ { 84, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #84 = G_ATOMICRMW_FSUB
+ { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #85 = G_FENCE
+ { 86, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #86 = G_BRCOND
+ { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #87 = G_BRINDIRECT
+ { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC
+ { 89, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #89 = G_INTRINSIC_W_SIDE_EFFECTS
+ { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #90 = G_ANYEXT
+ { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #91 = G_TRUNC
+ { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #92 = G_CONSTANT
+ { 93, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #93 = G_FCONSTANT
+ { 94, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #94 = G_VASTART
+ { 95, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_VAARG
+ { 96, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #96 = G_SEXT
+ { 97, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #97 = G_SEXT_INREG
+ { 98, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #98 = G_ZEXT
+ { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #99 = G_SHL
+ { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #100 = G_LSHR
+ { 101, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ASHR
+ { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #102 = G_ICMP
+ { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #103 = G_FCMP
+ { 104, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #104 = G_SELECT
+ { 105, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #105 = G_UADDO
+ { 106, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #106 = G_UADDE
+ { 107, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #107 = G_USUBO
+ { 108, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #108 = G_USUBE
+ { 109, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #109 = G_SADDO
+ { 110, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #110 = G_SADDE
+ { 111, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #111 = G_SSUBO
+ { 112, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #112 = G_SSUBE
+ { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #113 = G_UMULO
+ { 114, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #114 = G_SMULO
+ { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #115 = G_UMULH
+ { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #116 = G_SMULH
+ { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #117 = G_FADD
+ { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #118 = G_FSUB
+ { 119, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #119 = G_FMUL
+ { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #120 = G_FMA
+ { 121, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #121 = G_FMAD
+ { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #122 = G_FDIV
+ { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #123 = G_FREM
+ { 124, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #124 = G_FPOW
+ { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #125 = G_FEXP
+ { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #126 = G_FEXP2
+ { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #127 = G_FLOG
+ { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #128 = G_FLOG2
+ { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #129 = G_FLOG10
+ { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #130 = G_FNEG
+ { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #131 = G_FPEXT
+ { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #132 = G_FPTRUNC
+ { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #133 = G_FPTOSI
+ { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #134 = G_FPTOUI
+ { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #135 = G_SITOFP
+ { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #136 = G_UITOFP
+ { 137, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #137 = G_FABS
+ { 138, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #138 = G_FCOPYSIGN
+ { 139, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #139 = G_FCANONICALIZE
+ { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #140 = G_FMINNUM
+ { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #141 = G_FMAXNUM
+ { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #142 = G_FMINNUM_IEEE
+ { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #143 = G_FMAXNUM_IEEE
+ { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #144 = G_FMINIMUM
+ { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #145 = G_FMAXIMUM
+ { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #146 = G_PTR_ADD
+ { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #147 = G_PTR_MASK
+ { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #148 = G_SMIN
+ { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #149 = G_SMAX
+ { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #150 = G_UMIN
+ { 151, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #151 = G_UMAX
+ { 152, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #152 = G_BR
+ { 153, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_BRJT
+ { 154, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_INSERT_VECTOR_ELT
+ { 155, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_EXTRACT_VECTOR_ELT
+ { 156, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #156 = G_SHUFFLE_VECTOR
+ { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #157 = G_CTTZ
+ { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #158 = G_CTTZ_ZERO_UNDEF
+ { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #159 = G_CTLZ
+ { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #160 = G_CTLZ_ZERO_UNDEF
+ { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #161 = G_CTPOP
+ { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #162 = G_BSWAP
+ { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #163 = G_BITREVERSE
+ { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #164 = G_FCEIL
+ { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #165 = G_FCOS
+ { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #166 = G_FSIN
+ { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #167 = G_FSQRT
+ { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #168 = G_FFLOOR
+ { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #169 = G_FRINT
+ { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #170 = G_FNEARBYINT
+ { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #171 = G_ADDRSPACE_CAST
+ { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #172 = G_BLOCK_ADDR
+ { 173, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #173 = G_JUMP_TABLE
+ { 174, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = G_DYN_STACKALLOC
+ { 175, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #175 = G_READ_REGISTER
+ { 176, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #176 = G_WRITE_REGISTER
+ { 177, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #177 = ADJCALLSTACKDOWN
+ { 178, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #178 = ADJCALLSTACKUP
+ { 179, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #179 = BuildPairF64Pseudo
+ { 180, 4, 1, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #180 = PseudoAddTPRel
+ { 181, 5, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #181 = PseudoAtomicLoadNand32
+ { 182, 5, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #182 = PseudoAtomicLoadNand64
+ { 183, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #183 = PseudoBR
+ { 184, 2, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList2, OperandInfo42, -1 ,nullptr }, // Inst #184 = PseudoBRIND
+ { 185, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #185 = PseudoCALL
+ { 186, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList2, OperandInfo43, -1 ,nullptr }, // Inst #186 = PseudoCALLIndirect
+ { 187, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #187 = PseudoCALLReg
+ { 188, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #188 = PseudoCmpXchg32
+ { 189, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #189 = PseudoCmpXchg64
+ { 190, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #190 = PseudoFLD
+ { 191, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #191 = PseudoFLW
+ { 192, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #192 = PseudoFSD
+ { 193, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #193 = PseudoFSW
+ { 194, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #194 = PseudoLA
+ { 195, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #195 = PseudoLA_TLS_GD
+ { 196, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #196 = PseudoLA_TLS_IE
+ { 197, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #197 = PseudoLB
+ { 198, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #198 = PseudoLBU
+ { 199, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #199 = PseudoLD
+ { 200, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #200 = PseudoLH
+ { 201, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #201 = PseudoLHU
+ { 202, 2, 1, 32, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #202 = PseudoLI
+ { 203, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #203 = PseudoLLA
+ { 204, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #204 = PseudoLW
+ { 205, 2, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #205 = PseudoLWU
+ { 206, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #206 = PseudoMaskedAtomicLoadAdd32
+ { 207, 8, 3, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #207 = PseudoMaskedAtomicLoadMax32
+ { 208, 8, 3, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #208 = PseudoMaskedAtomicLoadMin32
+ { 209, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #209 = PseudoMaskedAtomicLoadNand32
+ { 210, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #210 = PseudoMaskedAtomicLoadSub32
+ { 211, 7, 3, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #211 = PseudoMaskedAtomicLoadUMax32
+ { 212, 7, 3, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #212 = PseudoMaskedAtomicLoadUMin32
+ { 213, 6, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #213 = PseudoMaskedAtomicSwap32
+ { 214, 7, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #214 = PseudoMaskedCmpXchg32
+ { 215, 0, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #215 = PseudoRET
+ { 216, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #216 = PseudoSB
+ { 217, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #217 = PseudoSD
+ { 218, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #218 = PseudoSH
+ { 219, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #219 = PseudoSW
+ { 220, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #220 = PseudoTAIL
+ { 221, 1, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #221 = PseudoTAILIndirect
+ { 222, 2, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #222 = ReadCycleWide
+ { 223, 6, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #223 = Select_FPR32_Using_CC_GPR
+ { 224, 6, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #224 = Select_FPR64_Using_CC_GPR
+ { 225, 6, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #225 = Select_GPR_Using_CC_GPR
+ { 226, 3, 2, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #226 = SplitF64Pseudo
+ { 227, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #227 = ADD
+ { 228, 3, 1, 4, 2, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #228 = ADDI
+ { 229, 3, 1, 4, 3, 0, 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #229 = ADDIW
+ { 230, 3, 1, 4, 4, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #230 = ADDW
+ { 231, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #231 = AMOADD_D
+ { 232, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #232 = AMOADD_D_AQ
+ { 233, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #233 = AMOADD_D_AQ_RL
+ { 234, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #234 = AMOADD_D_RL
+ { 235, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #235 = AMOADD_W
+ { 236, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #236 = AMOADD_W_AQ
+ { 237, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #237 = AMOADD_W_AQ_RL
+ { 238, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #238 = AMOADD_W_RL
+ { 239, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #239 = AMOAND_D
+ { 240, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #240 = AMOAND_D_AQ
+ { 241, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #241 = AMOAND_D_AQ_RL
+ { 242, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #242 = AMOAND_D_RL
+ { 243, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #243 = AMOAND_W
+ { 244, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #244 = AMOAND_W_AQ
+ { 245, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #245 = AMOAND_W_AQ_RL
+ { 246, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #246 = AMOAND_W_RL
+ { 247, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #247 = AMOMAXU_D
+ { 248, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #248 = AMOMAXU_D_AQ
+ { 249, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #249 = AMOMAXU_D_AQ_RL
+ { 250, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #250 = AMOMAXU_D_RL
+ { 251, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #251 = AMOMAXU_W
+ { 252, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #252 = AMOMAXU_W_AQ
+ { 253, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #253 = AMOMAXU_W_AQ_RL
+ { 254, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #254 = AMOMAXU_W_RL
+ { 255, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #255 = AMOMAX_D
+ { 256, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #256 = AMOMAX_D_AQ
+ { 257, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #257 = AMOMAX_D_AQ_RL
+ { 258, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #258 = AMOMAX_D_RL
+ { 259, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #259 = AMOMAX_W
+ { 260, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #260 = AMOMAX_W_AQ
+ { 261, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #261 = AMOMAX_W_AQ_RL
+ { 262, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #262 = AMOMAX_W_RL
+ { 263, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #263 = AMOMINU_D
+ { 264, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #264 = AMOMINU_D_AQ
+ { 265, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #265 = AMOMINU_D_AQ_RL
+ { 266, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #266 = AMOMINU_D_RL
+ { 267, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #267 = AMOMINU_W
+ { 268, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #268 = AMOMINU_W_AQ
+ { 269, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #269 = AMOMINU_W_AQ_RL
+ { 270, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #270 = AMOMINU_W_RL
+ { 271, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #271 = AMOMIN_D
+ { 272, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #272 = AMOMIN_D_AQ
+ { 273, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #273 = AMOMIN_D_AQ_RL
+ { 274, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #274 = AMOMIN_D_RL
+ { 275, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #275 = AMOMIN_W
+ { 276, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #276 = AMOMIN_W_AQ
+ { 277, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #277 = AMOMIN_W_AQ_RL
+ { 278, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #278 = AMOMIN_W_RL
+ { 279, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #279 = AMOOR_D
+ { 280, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #280 = AMOOR_D_AQ
+ { 281, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #281 = AMOOR_D_AQ_RL
+ { 282, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #282 = AMOOR_D_RL
+ { 283, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #283 = AMOOR_W
+ { 284, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #284 = AMOOR_W_AQ
+ { 285, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #285 = AMOOR_W_AQ_RL
+ { 286, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #286 = AMOOR_W_RL
+ { 287, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #287 = AMOSWAP_D
+ { 288, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #288 = AMOSWAP_D_AQ
+ { 289, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #289 = AMOSWAP_D_AQ_RL
+ { 290, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #290 = AMOSWAP_D_RL
+ { 291, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #291 = AMOSWAP_W
+ { 292, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #292 = AMOSWAP_W_AQ
+ { 293, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #293 = AMOSWAP_W_AQ_RL
+ { 294, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #294 = AMOSWAP_W_RL
+ { 295, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #295 = AMOXOR_D
+ { 296, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #296 = AMOXOR_D_AQ
+ { 297, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #297 = AMOXOR_D_AQ_RL
+ { 298, 3, 1, 4, 5, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #298 = AMOXOR_D_RL
+ { 299, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #299 = AMOXOR_W
+ { 300, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #300 = AMOXOR_W_AQ
+ { 301, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #301 = AMOXOR_W_AQ_RL
+ { 302, 3, 1, 4, 6, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #302 = AMOXOR_W_RL
+ { 303, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #303 = AND
+ { 304, 3, 1, 4, 2, 0, 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #304 = ANDI
+ { 305, 2, 1, 4, 7, 0, 0x6ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #305 = AUIPC
+ { 306, 3, 0, 4, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #306 = BEQ
+ { 307, 3, 0, 4, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #307 = BGE
+ { 308, 3, 0, 4, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #308 = BGEU
+ { 309, 3, 0, 4, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #309 = BLT
+ { 310, 3, 0, 4, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #310 = BLTU
+ { 311, 3, 0, 4, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #311 = BNE
+ { 312, 3, 1, 4, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #312 = CSRRC
+ { 313, 3, 1, 4, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #313 = CSRRCI
+ { 314, 3, 1, 4, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #314 = CSRRS
+ { 315, 3, 1, 4, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #315 = CSRRSI
+ { 316, 3, 1, 4, 9, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #316 = CSRRW
+ { 317, 3, 1, 4, 10, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #317 = CSRRWI
+ { 318, 3, 1, 2, 1, 0, 0x8ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #318 = C_ADD
+ { 319, 3, 1, 2, 2, 0, 0x9ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #319 = C_ADDI
+ { 320, 3, 1, 2, 2, 0, 0x9ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #320 = C_ADDI16SP
+ { 321, 3, 1, 2, 2, 0, 0xbULL, ImplicitList1, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #321 = C_ADDI4SPN
+ { 322, 3, 1, 2, 3, 0, 0x9ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #322 = C_ADDIW
+ { 323, 3, 1, 2, 2, 0, 0x9ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #323 = C_ADDI_HINT_IMM_ZERO
+ { 324, 3, 1, 2, 2, 0, 0x9ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #324 = C_ADDI_HINT_X0
+ { 325, 3, 1, 2, 2, 0, 0x9ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #325 = C_ADDI_NOP
+ { 326, 3, 1, 2, 4, 0, 0xeULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #326 = C_ADDW
+ { 327, 3, 1, 2, 1, 0, 0x8ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #327 = C_ADD_HINT
+ { 328, 3, 1, 2, 1, 0, 0xeULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #328 = C_AND
+ { 329, 3, 1, 2, 2, 0, 0xfULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #329 = C_ANDI
+ { 330, 2, 0, 2, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xfULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #330 = C_BEQZ
+ { 331, 2, 0, 2, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0xfULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #331 = C_BNEZ
+ { 332, 0, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #332 = C_EBREAK
+ { 333, 3, 1, 2, 11, 0|(1ULL<<MCID::MayLoad), 0xcULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #333 = C_FLD
+ { 334, 3, 1, 2, 11, 0|(1ULL<<MCID::MayLoad), 0x9ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #334 = C_FLDSP
+ { 335, 3, 1, 2, 12, 0|(1ULL<<MCID::MayLoad), 0xcULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #335 = C_FLW
+ { 336, 3, 1, 2, 12, 0|(1ULL<<MCID::MayLoad), 0x9ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #336 = C_FLWSP
+ { 337, 3, 0, 2, 13, 0|(1ULL<<MCID::MayStore), 0xdULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #337 = C_FSD
+ { 338, 3, 0, 2, 13, 0|(1ULL<<MCID::MayStore), 0xaULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #338 = C_FSDSP
+ { 339, 3, 0, 2, 14, 0|(1ULL<<MCID::MayStore), 0xdULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #339 = C_FSW
+ { 340, 3, 0, 2, 14, 0|(1ULL<<MCID::MayStore), 0xaULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #340 = C_FSWSP
+ { 341, 1, 0, 2, 8, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #341 = C_J
+ { 342, 1, 0, 2, 15, 0|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #342 = C_JAL
+ { 343, 1, 0, 2, 16, 0|(1ULL<<MCID::Call), 0x8ULL, nullptr, ImplicitList2, OperandInfo77, -1 ,nullptr }, // Inst #343 = C_JALR
+ { 344, 1, 0, 2, 17, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #344 = C_JR
+ { 345, 3, 1, 2, 18, 0|(1ULL<<MCID::MayLoad), 0xcULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #345 = C_LD
+ { 346, 3, 1, 2, 18, 0|(1ULL<<MCID::MayLoad), 0x9ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #346 = C_LDSP
+ { 347, 2, 1, 2, 7, 0, 0x9ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #347 = C_LI
+ { 348, 2, 1, 2, 7, 0, 0x9ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #348 = C_LI_HINT
+ { 349, 2, 1, 2, 7, 0, 0x9ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #349 = C_LUI
+ { 350, 2, 1, 2, 7, 0, 0x9ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #350 = C_LUI_HINT
+ { 351, 3, 1, 2, 19, 0|(1ULL<<MCID::MayLoad), 0xcULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #351 = C_LW
+ { 352, 3, 1, 2, 19, 0|(1ULL<<MCID::MayLoad), 0x9ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #352 = C_LWSP
+ { 353, 2, 1, 2, 2, 0, 0x8ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #353 = C_MV
+ { 354, 2, 1, 2, 2, 0, 0x8ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #354 = C_MV_HINT
+ { 355, 0, 0, 2, 20, 0, 0x9ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #355 = C_NOP
+ { 356, 1, 0, 2, 20, 0, 0x9ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #356 = C_NOP_HINT
+ { 357, 3, 1, 2, 1, 0, 0xeULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #357 = C_OR
+ { 358, 3, 0, 2, 21, 0|(1ULL<<MCID::MayStore), 0xdULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #358 = C_SD
+ { 359, 3, 0, 2, 21, 0|(1ULL<<MCID::MayStore), 0xaULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #359 = C_SDSP
+ { 360, 3, 1, 2, 22, 0, 0x9ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #360 = C_SLLI
+ { 361, 2, 1, 2, 22, 0, 0x9ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #361 = C_SLLI64_HINT
+ { 362, 3, 1, 2, 22, 0, 0x9ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #362 = C_SLLI_HINT
+ { 363, 3, 1, 2, 22, 0, 0xfULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #363 = C_SRAI
+ { 364, 2, 1, 2, 22, 0, 0x9ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #364 = C_SRAI64_HINT
+ { 365, 3, 1, 2, 22, 0, 0xfULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #365 = C_SRLI
+ { 366, 2, 1, 2, 22, 0, 0x9ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #366 = C_SRLI64_HINT
+ { 367, 3, 1, 2, 1, 0, 0xeULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #367 = C_SUB
+ { 368, 3, 1, 2, 4, 0, 0xeULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #368 = C_SUBW
+ { 369, 3, 0, 2, 23, 0|(1ULL<<MCID::MayStore), 0xdULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #369 = C_SW
+ { 370, 3, 0, 2, 23, 0|(1ULL<<MCID::MayStore), 0xaULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #370 = C_SWSP
+ { 371, 0, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #371 = C_UNIMP
+ { 372, 3, 1, 2, 1, 0, 0xeULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #372 = C_XOR
+ { 373, 3, 1, 4, 24, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #373 = DIV
+ { 374, 3, 1, 4, 24, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #374 = DIVU
+ { 375, 3, 1, 4, 25, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #375 = DIVUW
+ { 376, 3, 1, 4, 25, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #376 = DIVW
+ { 377, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #377 = EBREAK
+ { 378, 0, 0, 4, 8, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #378 = ECALL
+ { 379, 4, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #379 = FADD_D
+ { 380, 4, 1, 4, 27, 0, 0x1ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #380 = FADD_S
+ { 381, 2, 1, 4, 28, 0, 0x1ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #381 = FCLASS_D
+ { 382, 2, 1, 4, 29, 0, 0x1ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #382 = FCLASS_S
+ { 383, 3, 1, 4, 30, 0, 0x1ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #383 = FCVT_D_L
+ { 384, 3, 1, 4, 30, 0, 0x1ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #384 = FCVT_D_LU
+ { 385, 2, 1, 4, 31, 0, 0x1ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #385 = FCVT_D_S
+ { 386, 2, 1, 4, 32, 0, 0x1ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #386 = FCVT_D_W
+ { 387, 2, 1, 4, 32, 0, 0x1ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #387 = FCVT_D_WU
+ { 388, 3, 1, 4, 33, 0, 0x1ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #388 = FCVT_LU_D
+ { 389, 3, 1, 4, 34, 0, 0x1ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #389 = FCVT_LU_S
+ { 390, 3, 1, 4, 33, 0, 0x1ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #390 = FCVT_L_D
+ { 391, 3, 1, 4, 34, 0, 0x1ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #391 = FCVT_L_S
+ { 392, 3, 1, 4, 35, 0, 0x1ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #392 = FCVT_S_D
+ { 393, 3, 1, 4, 36, 0, 0x1ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #393 = FCVT_S_L
+ { 394, 3, 1, 4, 36, 0, 0x1ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #394 = FCVT_S_LU
+ { 395, 3, 1, 4, 37, 0, 0x1ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #395 = FCVT_S_W
+ { 396, 3, 1, 4, 37, 0, 0x1ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #396 = FCVT_S_WU
+ { 397, 3, 1, 4, 38, 0, 0x1ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #397 = FCVT_WU_D
+ { 398, 3, 1, 4, 39, 0, 0x1ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #398 = FCVT_WU_S
+ { 399, 3, 1, 4, 38, 0, 0x1ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #399 = FCVT_W_D
+ { 400, 3, 1, 4, 39, 0, 0x1ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #400 = FCVT_W_S
+ { 401, 4, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #401 = FDIV_D
+ { 402, 4, 1, 4, 40, 0, 0x1ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #402 = FDIV_S
+ { 403, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #403 = FENCE
+ { 404, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #404 = FENCE_I
+ { 405, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #405 = FENCE_TSO
+ { 406, 3, 1, 4, 41, 0, 0x1ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #406 = FEQ_D
+ { 407, 3, 1, 4, 42, 0, 0x1ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #407 = FEQ_S
+ { 408, 3, 1, 4, 11, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #408 = FLD
+ { 409, 3, 1, 4, 41, 0, 0x1ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #409 = FLE_D
+ { 410, 3, 1, 4, 42, 0, 0x1ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #410 = FLE_S
+ { 411, 3, 1, 4, 41, 0, 0x1ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #411 = FLT_D
+ { 412, 3, 1, 4, 42, 0, 0x1ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #412 = FLT_S
+ { 413, 3, 1, 4, 12, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #413 = FLW
+ { 414, 5, 1, 4, 43, 0, 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #414 = FMADD_D
+ { 415, 5, 1, 4, 44, 0, 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #415 = FMADD_S
+ { 416, 3, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #416 = FMAX_D
+ { 417, 3, 1, 4, 27, 0, 0x1ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #417 = FMAX_S
+ { 418, 3, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #418 = FMIN_D
+ { 419, 3, 1, 4, 27, 0, 0x1ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #419 = FMIN_S
+ { 420, 5, 1, 4, 45, 0, 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #420 = FMSUB_D
+ { 421, 5, 1, 4, 46, 0, 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #421 = FMSUB_S
+ { 422, 4, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #422 = FMUL_D
+ { 423, 4, 1, 4, 47, 0, 0x1ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #423 = FMUL_S
+ { 424, 2, 1, 4, 48, 0, 0x1ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #424 = FMV_D_X
+ { 425, 2, 1, 4, 49, 0, 0x1ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #425 = FMV_W_X
+ { 426, 2, 1, 4, 50, 0, 0x1ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #426 = FMV_X_D
+ { 427, 2, 1, 4, 51, 0, 0x1ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #427 = FMV_X_W
+ { 428, 5, 1, 4, 43, 0, 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #428 = FNMADD_D
+ { 429, 5, 1, 4, 44, 0, 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #429 = FNMADD_S
+ { 430, 5, 1, 4, 45, 0, 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #430 = FNMSUB_D
+ { 431, 5, 1, 4, 46, 0, 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #431 = FNMSUB_S
+ { 432, 3, 0, 4, 13, 0|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #432 = FSD
+ { 433, 3, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #433 = FSGNJN_D
+ { 434, 3, 1, 4, 27, 0, 0x1ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #434 = FSGNJN_S
+ { 435, 3, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #435 = FSGNJX_D
+ { 436, 3, 1, 4, 27, 0, 0x1ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #436 = FSGNJX_S
+ { 437, 3, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #437 = FSGNJ_D
+ { 438, 3, 1, 4, 27, 0, 0x1ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #438 = FSGNJ_S
+ { 439, 3, 1, 4, 52, 0, 0x1ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #439 = FSQRT_D
+ { 440, 3, 1, 4, 52, 0, 0x1ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #440 = FSQRT_S
+ { 441, 4, 1, 4, 26, 0, 0x1ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #441 = FSUB_D
+ { 442, 4, 1, 4, 27, 0, 0x1ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #442 = FSUB_S
+ { 443, 3, 0, 4, 14, 0|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #443 = FSW
+ { 444, 2, 1, 4, 15, 0|(1ULL<<MCID::Call), 0x7ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #444 = JAL
+ { 445, 3, 1, 4, 16, 0|(1ULL<<MCID::Call), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #445 = JALR
+ { 446, 3, 1, 4, 53, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #446 = LB
+ { 447, 3, 1, 4, 53, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #447 = LBU
+ { 448, 3, 1, 4, 18, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #448 = LD
+ { 449, 3, 1, 4, 54, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #449 = LH
+ { 450, 3, 1, 4, 54, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #450 = LHU
+ { 451, 2, 1, 4, 55, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #451 = LR_D
+ { 452, 2, 1, 4, 55, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #452 = LR_D_AQ
+ { 453, 2, 1, 4, 55, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #453 = LR_D_AQ_RL
+ { 454, 2, 1, 4, 55, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #454 = LR_D_RL
+ { 455, 2, 1, 4, 56, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #455 = LR_W
+ { 456, 2, 1, 4, 56, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #456 = LR_W_AQ
+ { 457, 2, 1, 4, 56, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #457 = LR_W_AQ_RL
+ { 458, 2, 1, 4, 56, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #458 = LR_W_RL
+ { 459, 2, 1, 4, 7, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x6ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #459 = LUI
+ { 460, 3, 1, 4, 19, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #460 = LW
+ { 461, 3, 1, 4, 57, 0|(1ULL<<MCID::MayLoad), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #461 = LWU
+ { 462, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #462 = MRET
+ { 463, 3, 1, 4, 58, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #463 = MUL
+ { 464, 3, 1, 4, 58, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #464 = MULH
+ { 465, 3, 1, 4, 58, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #465 = MULHSU
+ { 466, 3, 1, 4, 58, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #466 = MULHU
+ { 467, 3, 1, 4, 59, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #467 = MULW
+ { 468, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #468 = OR
+ { 469, 3, 1, 4, 2, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #469 = ORI
+ { 470, 3, 1, 4, 24, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #470 = REM
+ { 471, 3, 1, 4, 24, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #471 = REMU
+ { 472, 3, 1, 4, 25, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #472 = REMUW
+ { 473, 3, 1, 4, 25, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #473 = REMW
+ { 474, 3, 0, 4, 60, 0|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #474 = SB
+ { 475, 3, 1, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #475 = SC_D
+ { 476, 3, 1, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #476 = SC_D_AQ
+ { 477, 3, 1, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #477 = SC_D_AQ_RL
+ { 478, 3, 1, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #478 = SC_D_RL
+ { 479, 3, 1, 4, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #479 = SC_W
+ { 480, 3, 1, 4, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #480 = SC_W_AQ
+ { 481, 3, 1, 4, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #481 = SC_W_AQ_RL
+ { 482, 3, 1, 4, 62, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #482 = SC_W_RL
+ { 483, 3, 0, 4, 21, 0|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #483 = SD
+ { 484, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #484 = SFENCE_VMA
+ { 485, 3, 0, 4, 63, 0|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #485 = SH
+ { 486, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #486 = SLL
+ { 487, 3, 1, 4, 22, 0, 0x3ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #487 = SLLI
+ { 488, 3, 1, 4, 64, 0, 0x3ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #488 = SLLIW
+ { 489, 3, 1, 4, 4, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #489 = SLLW
+ { 490, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #490 = SLT
+ { 491, 3, 1, 4, 2, 0, 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #491 = SLTI
+ { 492, 3, 1, 4, 2, 0, 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #492 = SLTIU
+ { 493, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #493 = SLTU
+ { 494, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #494 = SRA
+ { 495, 3, 1, 4, 22, 0, 0x3ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #495 = SRAI
+ { 496, 3, 1, 4, 64, 0, 0x3ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #496 = SRAIW
+ { 497, 3, 1, 4, 4, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #497 = SRAW
+ { 498, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #498 = SRET
+ { 499, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #499 = SRL
+ { 500, 3, 1, 4, 22, 0, 0x3ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #500 = SRLI
+ { 501, 3, 1, 4, 64, 0, 0x3ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #501 = SRLIW
+ { 502, 3, 1, 4, 4, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #502 = SRLW
+ { 503, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #503 = SUB
+ { 504, 3, 1, 4, 4, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #504 = SUBW
+ { 505, 3, 0, 4, 23, 0|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #505 = SW
+ { 506, 0, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #506 = UNIMP
+ { 507, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #507 = URET
+ { 508, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #508 = WFI
+ { 509, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #509 = XOR
+ { 510, 3, 1, 4, 2, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #510 = XORI
+};
+
+extern const char RISCVInstrNameData[] = {
+ /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0,
+ /* 9 */ 'C', '_', 'A', 'D', 'D', 'I', '_', 'H', 'I', 'N', 'T', '_', 'X', '0', 0,
+ /* 24 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'S', 'u', 'b', '3', '2', 0,
+ /* 52 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'A', 'd', 'd', '3', '2', 0,
+ /* 80 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'N', 'a', 'n', 'd', '3', '2', 0,
+ /* 109 */ 'P', 's', 'e', 'u', 'd', 'o', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'N', 'a', 'n', 'd', '3', '2', 0,
+ /* 132 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'C', 'm', 'p', 'X', 'c', 'h', 'g', '3', '2', 0,
+ /* 154 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'm', 'p', 'X', 'c', 'h', 'g', '3', '2', 0,
+ /* 170 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'U', 'M', 'i', 'n', '3', '2', 0,
+ /* 199 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'M', 'i', 'n', '3', '2', 0,
+ /* 227 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'A', 't', 'o', 'm', 'i', 'c', 'S', 'w', 'a', 'p', '3', '2', 0,
+ /* 252 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'U', 'M', 'a', 'x', '3', '2', 0,
+ /* 281 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'a', 's', 'k', 'e', 'd', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'M', 'a', 'x', '3', '2', 0,
+ /* 309 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0,
+ /* 317 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0,
+ /* 325 */ 'P', 's', 'e', 'u', 'd', 'o', 'A', 't', 'o', 'm', 'i', 'c', 'L', 'o', 'a', 'd', 'N', 'a', 'n', 'd', '6', '4', 0,
+ /* 348 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'm', 'p', 'X', 'c', 'h', 'g', '6', '4', 0,
+ /* 364 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'L', 'A', 0,
+ /* 374 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'A', 0,
+ /* 383 */ 'G', '_', 'F', 'M', 'A', 0,
+ /* 389 */ 'S', 'F', 'E', 'N', 'C', 'E', '_', 'V', 'M', 'A', 0,
+ /* 400 */ 'S', 'R', 'A', 0,
+ /* 404 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'B', 0,
+ /* 413 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'B', 0,
+ /* 422 */ 'G', '_', 'F', 'S', 'U', 'B', 0,
+ /* 429 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'S', 'U', 'B', 0,
+ /* 446 */ 'C', '_', 'S', 'U', 'B', 0,
+ /* 452 */ 'G', '_', 'S', 'U', 'B', 0,
+ /* 458 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0,
+ /* 474 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0,
+ /* 486 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0,
+ /* 496 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0,
+ /* 514 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0,
+ /* 522 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0,
+ /* 543 */ 'G', '_', 'D', 'Y', 'N', '_', 'S', 'T', 'A', 'C', 'K', 'A', 'L', 'L', 'O', 'C', 0,
+ /* 560 */ 'A', 'U', 'I', 'P', 'C', 0,
+ /* 566 */ 'C', 'S', 'R', 'R', 'C', 0,
+ /* 572 */ 'G', '_', 'F', 'M', 'A', 'D', 0,
+ /* 579 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
+ /* 598 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
+ /* 609 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
+ /* 628 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0,
+ /* 639 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'L', 'O', 'A', 'D', 0,
+ /* 654 */ 'G', '_', 'L', 'O', 'A', 'D', 0,
+ /* 661 */ 'G', '_', 'F', 'A', 'D', 'D', 0,
+ /* 668 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'A', 'D', 'D', 0,
+ /* 685 */ 'C', '_', 'A', 'D', 'D', 0,
+ /* 691 */ 'G', '_', 'A', 'D', 'D', 0,
+ /* 697 */ 'G', '_', 'P', 'T', 'R', '_', 'A', 'D', 'D', 0,
+ /* 707 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0,
+ /* 723 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'A', '_', 'T', 'L', 'S', '_', 'G', 'D', 0,
+ /* 739 */ 'C', '_', 'F', 'L', 'D', 0,
+ /* 745 */ 'P', 's', 'e', 'u', 'd', 'o', 'F', 'L', 'D', 0,
+ /* 755 */ 'C', '_', 'L', 'D', 0,
+ /* 760 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'D', 0,
+ /* 769 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0,
+ /* 786 */ 'C', '_', 'A', 'N', 'D', 0,
+ /* 792 */ 'G', '_', 'A', 'N', 'D', 0,
+ /* 798 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0,
+ /* 814 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
+ /* 827 */ 'P', 's', 'e', 'u', 'd', 'o', 'B', 'R', 'I', 'N', 'D', 0,
+ /* 839 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0,
+ /* 848 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0,
+ /* 866 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0,
+ /* 883 */ 'C', '_', 'F', 'S', 'D', 0,
+ /* 889 */ 'P', 's', 'e', 'u', 'd', 'o', 'F', 'S', 'D', 0,
+ /* 899 */ 'C', '_', 'S', 'D', 0,
+ /* 904 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'D', 0,
+ /* 913 */ 'F', 'S', 'U', 'B', '_', 'D', 0,
+ /* 920 */ 'F', 'M', 'S', 'U', 'B', '_', 'D', 0,
+ /* 928 */ 'F', 'N', 'M', 'S', 'U', 'B', '_', 'D', 0,
+ /* 937 */ 'S', 'C', '_', 'D', 0,
+ /* 942 */ 'F', 'A', 'D', 'D', '_', 'D', 0,
+ /* 949 */ 'F', 'M', 'A', 'D', 'D', '_', 'D', 0,
+ /* 957 */ 'F', 'N', 'M', 'A', 'D', 'D', '_', 'D', 0,
+ /* 966 */ 'A', 'M', 'O', 'A', 'D', 'D', '_', 'D', 0,
+ /* 975 */ 'A', 'M', 'O', 'A', 'N', 'D', '_', 'D', 0,
+ /* 984 */ 'F', 'L', 'E', '_', 'D', 0,
+ /* 990 */ 'F', 'S', 'G', 'N', 'J', '_', 'D', 0,
+ /* 998 */ 'F', 'M', 'U', 'L', '_', 'D', 0,
+ /* 1005 */ 'F', 'C', 'V', 'T', '_', 'L', '_', 'D', 0,
+ /* 1014 */ 'F', 'M', 'I', 'N', '_', 'D', 0,
+ /* 1021 */ 'A', 'M', 'O', 'M', 'I', 'N', '_', 'D', 0,
+ /* 1030 */ 'F', 'S', 'G', 'N', 'J', 'N', '_', 'D', 0,
+ /* 1039 */ 'A', 'M', 'O', 'S', 'W', 'A', 'P', '_', 'D', 0,
+ /* 1049 */ 'F', 'E', 'Q', '_', 'D', 0,
+ /* 1055 */ 'L', 'R', '_', 'D', 0,
+ /* 1060 */ 'A', 'M', 'O', 'O', 'R', '_', 'D', 0,
+ /* 1068 */ 'A', 'M', 'O', 'X', 'O', 'R', '_', 'D', 0,
+ /* 1077 */ 'F', 'C', 'L', 'A', 'S', 'S', '_', 'D', 0,
+ /* 1086 */ 'F', 'C', 'V', 'T', '_', 'S', '_', 'D', 0,
+ /* 1095 */ 'F', 'L', 'T', '_', 'D', 0,
+ /* 1101 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', 0,
+ /* 1109 */ 'F', 'C', 'V', 'T', '_', 'L', 'U', '_', 'D', 0,
+ /* 1119 */ 'A', 'M', 'O', 'M', 'I', 'N', 'U', '_', 'D', 0,
+ /* 1129 */ 'F', 'C', 'V', 'T', '_', 'W', 'U', '_', 'D', 0,
+ /* 1139 */ 'A', 'M', 'O', 'M', 'A', 'X', 'U', '_', 'D', 0,
+ /* 1149 */ 'F', 'D', 'I', 'V', '_', 'D', 0,
+ /* 1156 */ 'F', 'C', 'V', 'T', '_', 'W', '_', 'D', 0,
+ /* 1165 */ 'F', 'M', 'A', 'X', '_', 'D', 0,
+ /* 1172 */ 'A', 'M', 'O', 'M', 'A', 'X', '_', 'D', 0,
+ /* 1181 */ 'F', 'S', 'G', 'N', 'J', 'X', '_', 'D', 0,
+ /* 1190 */ 'F', 'M', 'V', '_', 'X', '_', 'D', 0,
+ /* 1198 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0,
+ /* 1206 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0,
+ /* 1214 */ 'G', '_', 'F', 'E', 'N', 'C', 'E', 0,
+ /* 1222 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0,
+ /* 1235 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0,
+ /* 1243 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0,
+ /* 1251 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
+ /* 1266 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0,
+ /* 1281 */ 'B', 'G', 'E', 0,
+ /* 1285 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'A', '_', 'T', 'L', 'S', '_', 'I', 'E', 0,
+ /* 1301 */ 'G', '_', 'J', 'U', 'M', 'P', '_', 'T', 'A', 'B', 'L', 'E', 0,
+ /* 1314 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
+ /* 1321 */ 'B', 'N', 'E', 0,
+ /* 1325 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0,
+ /* 1338 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'T', 'O', 'R', 'E', 0,
+ /* 1354 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0,
+ /* 1362 */ 'G', '_', 'B', 'I', 'T', 'R', 'E', 'V', 'E', 'R', 'S', 'E', 0,
+ /* 1375 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 1385 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0,
+ /* 1400 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0,
+ /* 1416 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
+ /* 1434 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0,
+ /* 1452 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0,
+ /* 1467 */ 'G', '_', 'F', 'N', 'E', 'G', 0,
+ /* 1474 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
+ /* 1489 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0,
+ /* 1503 */ 'G', '_', 'S', 'E', 'X', 'T', '_', 'I', 'N', 'R', 'E', 'G', 0,
+ /* 1516 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0,
+ /* 1530 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0,
+ /* 1547 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0,
+ /* 1564 */ 'G', '_', 'F', 'L', 'O', 'G', 0,
+ /* 1571 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0,
+ /* 1579 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0,
+ /* 1587 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0,
+ /* 1595 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'H', 0,
+ /* 1604 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'H', 0,
+ /* 1613 */ 'C', '_', 'S', 'R', 'A', 'I', 0,
+ /* 1620 */ 'C', 'S', 'R', 'R', 'C', 'I', 0,
+ /* 1627 */ 'C', '_', 'A', 'D', 'D', 'I', 0,
+ /* 1634 */ 'C', '_', 'A', 'N', 'D', 'I', 0,
+ /* 1641 */ 'W', 'F', 'I', 0,
+ /* 1645 */ 'G', '_', 'P', 'H', 'I', 0,
+ /* 1651 */ 'C', '_', 'S', 'L', 'L', 'I', 0,
+ /* 1658 */ 'C', '_', 'S', 'R', 'L', 'I', 0,
+ /* 1665 */ 'C', '_', 'L', 'I', 0,
+ /* 1670 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'I', 0,
+ /* 1679 */ 'X', 'O', 'R', 'I', 0,
+ /* 1684 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0,
+ /* 1693 */ 'C', 'S', 'R', 'R', 'S', 'I', 0,
+ /* 1700 */ 'S', 'L', 'T', 'I', 0,
+ /* 1705 */ 'C', '_', 'L', 'U', 'I', 0,
+ /* 1711 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0,
+ /* 1720 */ 'C', 'S', 'R', 'R', 'W', 'I', 0,
+ /* 1727 */ 'F', 'E', 'N', 'C', 'E', '_', 'I', 0,
+ /* 1735 */ 'C', '_', 'J', 0,
+ /* 1739 */ 'C', '_', 'E', 'B', 'R', 'E', 'A', 'K', 0,
+ /* 1748 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0,
+ /* 1759 */ 'C', '_', 'J', 'A', 'L', 0,
+ /* 1765 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 1774 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 1784 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 1793 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0,
+ /* 1810 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0,
+ /* 1830 */ 'G', '_', 'S', 'H', 'L', 0,
+ /* 1836 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'A', 'I', 'L', 0,
+ /* 1847 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0,
+ /* 1855 */ 'E', 'C', 'A', 'L', 'L', 0,
+ /* 1861 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0,
+ /* 1881 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
+ /* 1908 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0,
+ /* 1929 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0,
+ /* 1941 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'A', 'L', 'L', 0,
+ /* 1952 */ 'K', 'I', 'L', 'L', 0,
+ /* 1957 */ 'S', 'L', 'L', 0,
+ /* 1961 */ 'S', 'R', 'L', 0,
+ /* 1965 */ 'S', 'C', '_', 'D', '_', 'R', 'L', 0,
+ /* 1973 */ 'A', 'M', 'O', 'A', 'D', 'D', '_', 'D', '_', 'R', 'L', 0,
+ /* 1985 */ 'A', 'M', 'O', 'A', 'N', 'D', '_', 'D', '_', 'R', 'L', 0,
+ /* 1997 */ 'A', 'M', 'O', 'M', 'I', 'N', '_', 'D', '_', 'R', 'L', 0,
+ /* 2009 */ 'A', 'M', 'O', 'S', 'W', 'A', 'P', '_', 'D', '_', 'R', 'L', 0,
+ /* 2022 */ 'L', 'R', '_', 'D', '_', 'R', 'L', 0,
+ /* 2030 */ 'A', 'M', 'O', 'O', 'R', '_', 'D', '_', 'R', 'L', 0,
+ /* 2041 */ 'A', 'M', 'O', 'X', 'O', 'R', '_', 'D', '_', 'R', 'L', 0,
+ /* 2053 */ 'A', 'M', 'O', 'M', 'I', 'N', 'U', '_', 'D', '_', 'R', 'L', 0,
+ /* 2066 */ 'A', 'M', 'O', 'M', 'A', 'X', 'U', '_', 'D', '_', 'R', 'L', 0,
+ /* 2079 */ 'A', 'M', 'O', 'M', 'A', 'X', '_', 'D', '_', 'R', 'L', 0,
+ /* 2091 */ 'S', 'C', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2102 */ 'A', 'M', 'O', 'A', 'D', 'D', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2117 */ 'A', 'M', 'O', 'A', 'N', 'D', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2132 */ 'A', 'M', 'O', 'M', 'I', 'N', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2147 */ 'A', 'M', 'O', 'S', 'W', 'A', 'P', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2163 */ 'L', 'R', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2174 */ 'A', 'M', 'O', 'O', 'R', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2188 */ 'A', 'M', 'O', 'X', 'O', 'R', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2203 */ 'A', 'M', 'O', 'M', 'I', 'N', 'U', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2219 */ 'A', 'M', 'O', 'M', 'A', 'X', 'U', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2235 */ 'A', 'M', 'O', 'M', 'A', 'X', '_', 'D', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2250 */ 'S', 'C', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2261 */ 'A', 'M', 'O', 'A', 'D', 'D', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2276 */ 'A', 'M', 'O', 'A', 'N', 'D', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2291 */ 'A', 'M', 'O', 'M', 'I', 'N', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2306 */ 'A', 'M', 'O', 'S', 'W', 'A', 'P', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2322 */ 'L', 'R', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2333 */ 'A', 'M', 'O', 'O', 'R', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2347 */ 'A', 'M', 'O', 'X', 'O', 'R', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2362 */ 'A', 'M', 'O', 'M', 'I', 'N', 'U', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2378 */ 'A', 'M', 'O', 'M', 'A', 'X', 'U', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2394 */ 'A', 'M', 'O', 'M', 'A', 'X', '_', 'W', '_', 'A', 'Q', '_', 'R', 'L', 0,
+ /* 2409 */ 'S', 'C', '_', 'W', '_', 'R', 'L', 0,
+ /* 2417 */ 'A', 'M', 'O', 'A', 'D', 'D', '_', 'W', '_', 'R', 'L', 0,
+ /* 2429 */ 'A', 'M', 'O', 'A', 'N', 'D', '_', 'W', '_', 'R', 'L', 0,
+ /* 2441 */ 'A', 'M', 'O', 'M', 'I', 'N', '_', 'W', '_', 'R', 'L', 0,
+ /* 2453 */ 'A', 'M', 'O', 'S', 'W', 'A', 'P', '_', 'W', '_', 'R', 'L', 0,
+ /* 2466 */ 'L', 'R', '_', 'W', '_', 'R', 'L', 0,
+ /* 2474 */ 'A', 'M', 'O', 'O', 'R', '_', 'W', '_', 'R', 'L', 0,
+ /* 2485 */ 'A', 'M', 'O', 'X', 'O', 'R', '_', 'W', '_', 'R', 'L', 0,
+ /* 2497 */ 'A', 'M', 'O', 'M', 'I', 'N', 'U', '_', 'W', '_', 'R', 'L', 0,
+ /* 2510 */ 'A', 'M', 'O', 'M', 'A', 'X', 'U', '_', 'W', '_', 'R', 'L', 0,
+ /* 2523 */ 'A', 'M', 'O', 'M', 'A', 'X', '_', 'W', '_', 'R', 'L', 0,
+ /* 2535 */ 'G', '_', 'F', 'M', 'U', 'L', 0,
+ /* 2542 */ 'G', '_', 'M', 'U', 'L', 0,
+ /* 2548 */ 'F', 'C', 'V', 'T', '_', 'D', '_', 'L', 0,
+ /* 2557 */ 'F', 'C', 'V', 'T', '_', 'S', '_', 'L', 0,
+ /* 2566 */ 'G', '_', 'F', 'R', 'E', 'M', 0,
+ /* 2573 */ 'G', '_', 'S', 'R', 'E', 'M', 0,
+ /* 2580 */ 'G', '_', 'U', 'R', 'E', 'M', 0,
+ /* 2587 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0,
+ /* 2597 */ 'G', '_', 'F', 'M', 'I', 'N', 'I', 'M', 'U', 'M', 0,
+ /* 2608 */ 'G', '_', 'F', 'M', 'A', 'X', 'I', 'M', 'U', 'M', 0,
+ /* 2619 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', 0,
+ /* 2629 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', 0,
+ /* 2639 */ 'G', '_', 'F', 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', 0,
+ /* 2651 */ 'G', '_', 'S', 'M', 'I', 'N', 0,
+ /* 2658 */ 'G', '_', 'U', 'M', 'I', 'N', 0,
+ /* 2665 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0,
+ /* 2682 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0,
+ /* 2698 */ 'G', '_', 'F', 'S', 'I', 'N', 0,
+ /* 2705 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0,
+ /* 2721 */ 'C', '_', 'A', 'D', 'D', 'I', '4', 'S', 'P', 'N', 0,
+ /* 2732 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0,
+ /* 2749 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0,
+ /* 2757 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0,
+ /* 2765 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0,
+ /* 2773 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0,
+ /* 2781 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0,
+ /* 2789 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0,
+ /* 2797 */ 'C', '_', 'A', 'D', 'D', 'I', '_', 'H', 'I', 'N', 'T', '_', 'I', 'M', 'M', '_', 'Z', 'E', 'R', 'O', 0,
+ /* 2818 */ 'F', 'E', 'N', 'C', 'E', '_', 'T', 'S', 'O', 0,
+ /* 2828 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0,
+ /* 2837 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0,
+ /* 2845 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0,
+ /* 2854 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0,
+ /* 2863 */ 'G', '_', 'F', 'C', 'M', 'P', 0,
+ /* 2870 */ 'G', '_', 'I', 'C', 'M', 'P', 0,
+ /* 2877 */ 'C', '_', 'U', 'N', 'I', 'M', 'P', 0,
+ /* 2885 */ 'C', '_', 'N', 'O', 'P', 0,
+ /* 2891 */ 'C', '_', 'A', 'D', 'D', 'I', '_', 'N', 'O', 'P', 0,
+ /* 2902 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0,
+ /* 2910 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0,
+ /* 2923 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0,
+ /* 2935 */ 'C', '_', 'A', 'D', 'D', 'I', '1', '6', 'S', 'P', 0,
+ /* 2946 */ 'C', '_', 'F', 'L', 'D', 'S', 'P', 0,
+ /* 2954 */ 'C', '_', 'L', 'D', 'S', 'P', 0,
+ /* 2961 */ 'C', '_', 'F', 'S', 'D', 'S', 'P', 0,
+ /* 2969 */ 'C', '_', 'S', 'D', 'S', 'P', 0,
+ /* 2976 */ 'C', '_', 'F', 'L', 'W', 'S', 'P', 0,
+ /* 2984 */ 'C', '_', 'L', 'W', 'S', 'P', 0,
+ /* 2991 */ 'C', '_', 'F', 'S', 'W', 'S', 'P', 0,
+ /* 2999 */ 'C', '_', 'S', 'W', 'S', 'P', 0,
+ /* 3006 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0,
+ /* 3021 */ 'G', '_', 'F', 'E', 'X', 'P', 0,
+ /* 3028 */ 'S', 'C', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3036 */ 'A', 'M', 'O', 'A', 'D', 'D', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3048 */ 'A', 'M', 'O', 'A', 'N', 'D', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3060 */ 'A', 'M', 'O', 'M', 'I', 'N', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3072 */ 'A', 'M', 'O', 'S', 'W', 'A', 'P', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3085 */ 'L', 'R', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3093 */ 'A', 'M', 'O', 'O', 'R', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3104 */ 'A', 'M', 'O', 'X', 'O', 'R', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3116 */ 'A', 'M', 'O', 'M', 'I', 'N', 'U', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3129 */ 'A', 'M', 'O', 'M', 'A', 'X', 'U', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3142 */ 'A', 'M', 'O', 'M', 'A', 'X', '_', 'D', '_', 'A', 'Q', 0,
+ /* 3154 */ 'S', 'C', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3162 */ 'A', 'M', 'O', 'A', 'D', 'D', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3174 */ 'A', 'M', 'O', 'A', 'N', 'D', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3186 */ 'A', 'M', 'O', 'M', 'I', 'N', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3198 */ 'A', 'M', 'O', 'S', 'W', 'A', 'P', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3211 */ 'L', 'R', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3219 */ 'A', 'M', 'O', 'O', 'R', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3230 */ 'A', 'M', 'O', 'X', 'O', 'R', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3242 */ 'A', 'M', 'O', 'M', 'I', 'N', 'U', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3255 */ 'A', 'M', 'O', 'M', 'A', 'X', 'U', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3268 */ 'A', 'M', 'O', 'M', 'A', 'X', '_', 'W', '_', 'A', 'Q', 0,
+ /* 3280 */ 'B', 'E', 'Q', 0,
+ /* 3284 */ 'G', '_', 'B', 'R', 0,
+ /* 3289 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0,
+ /* 3302 */ 'P', 's', 'e', 'u', 'd', 'o', 'B', 'R', 0,
+ /* 3311 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0,
+ /* 3324 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0,
+ /* 3349 */ 'G', '_', 'R', 'E', 'A', 'D', 'C', 'Y', 'C', 'L', 'E', 'C', 'O', 'U', 'N', 'T', 'E', 'R', 0,
+ /* 3368 */ 'G', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'G', 'I', 'S', 'T', 'E', 'R', 0,
+ /* 3384 */ 'G', '_', 'W', 'R', 'I', 'T', 'E', '_', 'R', 'E', 'G', 'I', 'S', 'T', 'E', 'R', 0,
+ /* 3401 */ 'G', '_', 'A', 'S', 'H', 'R', 0,
+ /* 3408 */ 'G', '_', 'L', 'S', 'H', 'R', 0,
+ /* 3415 */ 'C', '_', 'J', 'R', 0,
+ /* 3420 */ 'C', '_', 'J', 'A', 'L', 'R', 0,
+ /* 3427 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0,
+ /* 3436 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
+ /* 3451 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0,
+ /* 3468 */ 'C', '_', 'X', 'O', 'R', 0,
+ /* 3474 */ 'G', '_', 'X', 'O', 'R', 0,
+ /* 3480 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0,
+ /* 3496 */ 'C', '_', 'O', 'R', 0,
+ /* 3501 */ 'G', '_', 'O', 'R', 0,
+ /* 3506 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0,
+ /* 3521 */ 'S', 'e', 'l', 'e', 'c', 't', '_', 'F', 'P', 'R', '3', '2', '_', 'U', 's', 'i', 'n', 'g', '_', 'C', 'C', '_', 'G', 'P', 'R', 0,
+ /* 3547 */ 'S', 'e', 'l', 'e', 'c', 't', '_', 'F', 'P', 'R', '6', '4', '_', 'U', 's', 'i', 'n', 'g', '_', 'C', 'C', '_', 'G', 'P', 'R', 0,
+ /* 3573 */ 'S', 'e', 'l', 'e', 'c', 't', '_', 'G', 'P', 'R', '_', 'U', 's', 'i', 'n', 'g', '_', 'C', 'C', '_', 'G', 'P', 'R', 0,
+ /* 3597 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0,
+ /* 3608 */ 'G', '_', 'F', 'A', 'B', 'S', 0,
+ /* 3615 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
+ /* 3632 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0,
+ /* 3647 */ 'G', '_', 'F', 'C', 'O', 'S', 0,
+ /* 3654 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0,
+ /* 3671 */ 'C', 'S', 'R', 'R', 'S', 0,
+ /* 3677 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0,
+ /* 3694 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0,
+ /* 3724 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0,
+ /* 3751 */ 'F', 'S', 'U', 'B', '_', 'S', 0,
+ /* 3758 */ 'F', 'M', 'S', 'U', 'B', '_', 'S', 0,
+ /* 3766 */ 'F', 'N', 'M', 'S', 'U', 'B', '_', 'S', 0,
+ /* 3775 */ 'F', 'A', 'D', 'D', '_', 'S', 0,
+ /* 3782 */ 'F', 'M', 'A', 'D', 'D', '_', 'S', 0,
+ /* 3790 */ 'F', 'N', 'M', 'A', 'D', 'D', '_', 'S', 0,
+ /* 3799 */ 'F', 'C', 'V', 'T', '_', 'D', '_', 'S', 0,
+ /* 3808 */ 'F', 'L', 'E', '_', 'S', 0,
+ /* 3814 */ 'F', 'S', 'G', 'N', 'J', '_', 'S', 0,
+ /* 3822 */ 'F', 'M', 'U', 'L', '_', 'S', 0,
+ /* 3829 */ 'F', 'C', 'V', 'T', '_', 'L', '_', 'S', 0,
+ /* 3838 */ 'F', 'M', 'I', 'N', '_', 'S', 0,
+ /* 3845 */ 'F', 'S', 'G', 'N', 'J', 'N', '_', 'S', 0,
+ /* 3854 */ 'F', 'E', 'Q', '_', 'S', 0,
+ /* 3860 */ 'F', 'C', 'L', 'A', 'S', 'S', '_', 'S', 0,
+ /* 3869 */ 'F', 'L', 'T', '_', 'S', 0,
+ /* 3875 */ 'F', 'S', 'Q', 'R', 'T', '_', 'S', 0,
+ /* 3883 */ 'F', 'C', 'V', 'T', '_', 'L', 'U', '_', 'S', 0,
+ /* 3893 */ 'F', 'C', 'V', 'T', '_', 'W', 'U', '_', 'S', 0,
+ /* 3903 */ 'F', 'D', 'I', 'V', '_', 'S', 0,
+ /* 3910 */ 'F', 'C', 'V', 'T', '_', 'W', '_', 'S', 0,
+ /* 3919 */ 'F', 'M', 'A', 'X', '_', 'S', 0,
+ /* 3926 */ 'F', 'S', 'G', 'N', 'J', 'X', '_', 'S', 0,
+ /* 3935 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0,
+ /* 3945 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0,
+ /* 3954 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0,
+ /* 3967 */ 'M', 'R', 'E', 'T', 0,
+ /* 3972 */ 'S', 'R', 'E', 'T', 0,
+ /* 3977 */ 'U', 'R', 'E', 'T', 0,
+ /* 3982 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0,
+ /* 3996 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'E', 'T', 0,
+ /* 4006 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0,
+ /* 4030 */ 'G', '_', 'B', 'R', 'J', 'T', 0,
+ /* 4037 */ 'B', 'L', 'T', 0,
+ /* 4041 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
+ /* 4062 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0,
+ /* 4082 */ 'S', 'L', 'T', 0,
+ /* 4086 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
+ /* 4098 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0,
+ /* 4109 */ 'C', '_', 'S', 'R', 'A', 'I', '6', '4', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4123 */ 'C', '_', 'S', 'L', 'L', 'I', '6', '4', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4137 */ 'C', '_', 'S', 'R', 'L', 'I', '6', '4', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4151 */ 'C', '_', 'A', 'D', 'D', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4162 */ 'C', '_', 'S', 'L', 'L', 'I', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4174 */ 'C', '_', 'L', 'I', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4184 */ 'C', '_', 'L', 'U', 'I', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4195 */ 'C', '_', 'N', 'O', 'P', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4206 */ 'C', '_', 'M', 'V', '_', 'H', 'I', 'N', 'T', 0,
+ /* 4216 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0,
+ /* 4227 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0,
+ /* 4238 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0,
+ /* 4249 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0,
+ /* 4257 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0,
+ /* 4270 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 4280 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
+ /* 4295 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0,
+ /* 4304 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0,
+ /* 4312 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0,
+ /* 4322 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0,
+ /* 4339 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0,
+ /* 4347 */ 'G', '_', 'S', 'E', 'X', 'T', 0,
+ /* 4354 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0,
+ /* 4363 */ 'G', '_', 'Z', 'E', 'X', 'T', 0,
+ /* 4370 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'B', 'U', 0,
+ /* 4380 */ 'B', 'G', 'E', 'U', 0,
+ /* 4385 */ 'M', 'U', 'L', 'H', 'U', 0,
+ /* 4391 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'H', 'U', 0,
+ /* 4401 */ 'S', 'L', 'T', 'I', 'U', 0,
+ /* 4407 */ 'F', 'C', 'V', 'T', '_', 'D', '_', 'L', 'U', 0,
+ /* 4417 */ 'F', 'C', 'V', 'T', '_', 'S', '_', 'L', 'U', 0,
+ /* 4427 */ 'R', 'E', 'M', 'U', 0,
+ /* 4432 */ 'M', 'U', 'L', 'H', 'S', 'U', 0,
+ /* 4439 */ 'B', 'L', 'T', 'U', 0,
+ /* 4444 */ 'S', 'L', 'T', 'U', 0,
+ /* 4449 */ 'D', 'I', 'V', 'U', 0,
+ /* 4454 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'W', 'U', 0,
+ /* 4464 */ 'F', 'C', 'V', 'T', '_', 'D', '_', 'W', 'U', 0,
+ /* 4474 */ 'F', 'C', 'V', 'T', '_', 'S', '_', 'W', 'U', 0,
+ /* 4484 */ 'G', '_', 'F', 'D', 'I', 'V', 0,
+ /* 4491 */ 'G', '_', 'S', 'D', 'I', 'V', 0,
+ /* 4498 */ 'G', '_', 'U', 'D', 'I', 'V', 0,
+ /* 4505 */ 'C', '_', 'M', 'V', 0,
+ /* 4510 */ 'S', 'R', 'A', 'W', 0,
+ /* 4515 */ 'C', '_', 'S', 'U', 'B', 'W', 0,
+ /* 4522 */ 'C', '_', 'A', 'D', 'D', 'W', 0,
+ /* 4529 */ 'S', 'R', 'A', 'I', 'W', 0,
+ /* 4535 */ 'C', '_', 'A', 'D', 'D', 'I', 'W', 0,
+ /* 4543 */ 'S', 'L', 'L', 'I', 'W', 0,
+ /* 4549 */ 'S', 'R', 'L', 'I', 'W', 0,
+ /* 4555 */ 'C', '_', 'F', 'L', 'W', 0,
+ /* 4561 */ 'P', 's', 'e', 'u', 'd', 'o', 'F', 'L', 'W', 0,
+ /* 4571 */ 'S', 'L', 'L', 'W', 0,
+ /* 4576 */ 'S', 'R', 'L', 'W', 0,
+ /* 4581 */ 'M', 'U', 'L', 'W', 0,
+ /* 4586 */ 'C', '_', 'L', 'W', 0,
+ /* 4591 */ 'P', 's', 'e', 'u', 'd', 'o', 'L', 'W', 0,
+ /* 4600 */ 'R', 'E', 'M', 'W', 0,
+ /* 4605 */ 'G', '_', 'F', 'P', 'O', 'W', 0,
+ /* 4612 */ 'C', 'S', 'R', 'R', 'W', 0,
+ /* 4618 */ 'C', '_', 'F', 'S', 'W', 0,
+ /* 4624 */ 'P', 's', 'e', 'u', 'd', 'o', 'F', 'S', 'W', 0,
+ /* 4634 */ 'C', '_', 'S', 'W', 0,
+ /* 4639 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'W', 0,
+ /* 4648 */ 'R', 'E', 'M', 'U', 'W', 0,
+ /* 4654 */ 'D', 'I', 'V', 'U', 'W', 0,
+ /* 4660 */ 'D', 'I', 'V', 'W', 0,
+ /* 4665 */ 'S', 'C', '_', 'W', 0,
+ /* 4670 */ 'A', 'M', 'O', 'A', 'D', 'D', '_', 'W', 0,
+ /* 4679 */ 'A', 'M', 'O', 'A', 'N', 'D', '_', 'W', 0,
+ /* 4688 */ 'F', 'C', 'V', 'T', '_', 'D', '_', 'W', 0,
+ /* 4697 */ 'A', 'M', 'O', 'M', 'I', 'N', '_', 'W', 0,
+ /* 4706 */ 'A', 'M', 'O', 'S', 'W', 'A', 'P', '_', 'W', 0,
+ /* 4716 */ 'L', 'R', '_', 'W', 0,
+ /* 4721 */ 'A', 'M', 'O', 'O', 'R', '_', 'W', 0,
+ /* 4729 */ 'A', 'M', 'O', 'X', 'O', 'R', '_', 'W', 0,
+ /* 4738 */ 'F', 'C', 'V', 'T', '_', 'S', '_', 'W', 0,
+ /* 4747 */ 'A', 'M', 'O', 'M', 'I', 'N', 'U', '_', 'W', 0,
+ /* 4757 */ 'A', 'M', 'O', 'M', 'A', 'X', 'U', '_', 'W', 0,
+ /* 4767 */ 'A', 'M', 'O', 'M', 'A', 'X', '_', 'W', 0,
+ /* 4776 */ 'F', 'M', 'V', '_', 'X', '_', 'W', 0,
+ /* 4784 */ 'G', '_', 'S', 'M', 'A', 'X', 0,
+ /* 4791 */ 'G', '_', 'U', 'M', 'A', 'X', 0,
+ /* 4798 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0,
+ /* 4815 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0,
+ /* 4831 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0,
+ /* 4845 */ 'F', 'M', 'V', '_', 'D', '_', 'X', 0,
+ /* 4853 */ 'F', 'M', 'V', '_', 'W', '_', 'X', 0,
+ /* 4861 */ 'C', 'O', 'P', 'Y', 0,
+ /* 4866 */ 'C', '_', 'B', 'N', 'E', 'Z', 0,
+ /* 4873 */ 'G', '_', 'C', 'T', 'L', 'Z', 0,
+ /* 4880 */ 'C', '_', 'B', 'E', 'Q', 'Z', 0,
+ /* 4887 */ 'G', '_', 'C', 'T', 'T', 'Z', 0,
+ /* 4894 */ 'R', 'e', 'a', 'd', 'C', 'y', 'c', 'l', 'e', 'W', 'i', 'd', 'e', 0,
+ /* 4908 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'A', 'L', 'L', 'R', 'e', 'g', 0,
+ /* 4922 */ 'P', 's', 'e', 'u', 'd', 'o', 'A', 'd', 'd', 'T', 'P', 'R', 'e', 'l', 0,
+ /* 4937 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 4956 */ 'S', 'p', 'l', 'i', 't', 'F', '6', '4', 'P', 's', 'e', 'u', 'd', 'o', 0,
+ /* 4971 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'A', 'I', 'L', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 0,
+ /* 4990 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'A', 'L', 'L', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 0,
+};
+
+extern const unsigned RISCVInstrNameIndices[] = {
+ 1647U, 2587U, 3289U, 2705U, 1784U, 1765U, 1793U, 1952U,
+ 1474U, 1489U, 1454U, 1516U, 3677U, 1375U, 1774U, 1222U,
+ 4861U, 1314U, 4280U, 814U, 2828U, 1929U, 4227U, 866U,
+ 4216U, 1325U, 2923U, 2910U, 3324U, 3982U, 4006U, 1861U,
+ 1908U, 1881U, 1810U, 691U, 452U, 2542U, 4491U, 4498U,
+ 2573U, 2580U, 792U, 3501U, 3474U, 1452U, 1645U, 4831U,
+ 1385U, 3935U, 3615U, 4295U, 3632U, 3436U, 522U, 3654U,
+ 4238U, 3597U, 4312U, 496U, 848U, 3349U, 654U, 598U,
+ 628U, 639U, 579U, 609U, 1354U, 1338U, 3694U, 1530U,
+ 1547U, 707U, 458U, 798U, 769U, 3506U, 3480U, 4815U,
+ 2682U, 4798U, 2665U, 668U, 429U, 1214U, 839U, 3954U,
+ 474U, 3724U, 4354U, 514U, 4098U, 4086U, 4270U, 1571U,
+ 4347U, 1503U, 4363U, 1830U, 3408U, 3401U, 2870U, 2863U,
+ 3945U, 2773U, 1243U, 2757U, 1206U, 2765U, 1235U, 2749U,
+ 1198U, 2789U, 2781U, 1587U, 1579U, 661U, 422U, 2535U,
+ 383U, 572U, 4484U, 2566U, 4605U, 3021U, 317U, 1564U,
+ 309U, 0U, 1467U, 4339U, 486U, 1684U, 1711U, 2845U,
+ 2854U, 3608U, 2639U, 1400U, 2619U, 2629U, 1251U, 1266U,
+ 2597U, 2608U, 697U, 1748U, 2651U, 4784U, 2658U, 4791U,
+ 3284U, 4030U, 4062U, 4041U, 3451U, 4887U, 1434U, 4873U,
+ 1416U, 2902U, 2837U, 1362U, 1847U, 3647U, 2698U, 4304U,
+ 3427U, 4249U, 4257U, 4322U, 3311U, 1301U, 543U, 3368U,
+ 3384U, 2732U, 3006U, 4937U, 4922U, 109U, 325U, 3302U,
+ 827U, 1941U, 4990U, 4908U, 154U, 348U, 745U, 4561U,
+ 889U, 4624U, 374U, 723U, 1285U, 404U, 4370U, 760U,
+ 1595U, 4391U, 1670U, 364U, 4591U, 4454U, 52U, 281U,
+ 199U, 80U, 24U, 252U, 170U, 227U, 132U, 3996U,
+ 413U, 904U, 1604U, 4639U, 1836U, 4971U, 4894U, 3521U,
+ 3547U, 3573U, 4956U, 664U, 1629U, 4537U, 4524U, 966U,
+ 3036U, 2102U, 1973U, 4670U, 3162U, 2261U, 2417U, 975U,
+ 3048U, 2117U, 1985U, 4679U, 3174U, 2276U, 2429U, 1139U,
+ 3129U, 2219U, 2066U, 4757U, 3255U, 2378U, 2510U, 1172U,
+ 3142U, 2235U, 2079U, 4767U, 3268U, 2394U, 2523U, 1119U,
+ 3116U, 2203U, 2053U, 4747U, 3242U, 2362U, 2497U, 1021U,
+ 3060U, 2132U, 1997U, 4697U, 3186U, 2291U, 2441U, 1060U,
+ 3093U, 2174U, 2030U, 4721U, 3219U, 2333U, 2474U, 1039U,
+ 3072U, 2147U, 2009U, 4706U, 3198U, 2306U, 2453U, 1068U,
+ 3104U, 2188U, 2041U, 4729U, 3230U, 2347U, 2485U, 782U,
+ 1636U, 560U, 3280U, 1281U, 4380U, 4037U, 4439U, 1321U,
+ 566U, 1620U, 3671U, 1693U, 4612U, 1720U, 685U, 1627U,
+ 2935U, 2721U, 4535U, 2797U, 9U, 2891U, 4522U, 4151U,
+ 786U, 1634U, 4880U, 4866U, 1739U, 739U, 2946U, 4555U,
+ 2976U, 883U, 2961U, 4618U, 2991U, 1735U, 1759U, 3420U,
+ 3415U, 755U, 2954U, 1665U, 4174U, 1705U, 4184U, 4586U,
+ 2984U, 4505U, 4206U, 2885U, 4195U, 3496U, 899U, 2969U,
+ 1651U, 4123U, 4162U, 1613U, 4109U, 1658U, 4137U, 446U,
+ 4515U, 4634U, 2999U, 2877U, 3468U, 4487U, 4449U, 4654U,
+ 4660U, 1741U, 1855U, 942U, 3775U, 1077U, 3860U, 2548U,
+ 4407U, 3799U, 4688U, 4464U, 1109U, 3883U, 1005U, 3829U,
+ 1086U, 2557U, 4417U, 4738U, 4474U, 1129U, 3893U, 1156U,
+ 3910U, 1149U, 3903U, 1216U, 1727U, 2818U, 1049U, 3854U,
+ 741U, 984U, 3808U, 1095U, 3869U, 4557U, 949U, 3782U,
+ 1165U, 3919U, 1014U, 3838U, 920U, 3758U, 998U, 3822U,
+ 4845U, 4853U, 1190U, 4776U, 957U, 3790U, 928U, 3766U,
+ 885U, 1030U, 3845U, 1181U, 3926U, 990U, 3814U, 1101U,
+ 3875U, 913U, 3751U, 4620U, 1761U, 3422U, 410U, 4376U,
+ 742U, 1584U, 4387U, 1055U, 3085U, 2163U, 2022U, 4716U,
+ 3211U, 2322U, 2466U, 1707U, 4558U, 4460U, 3967U, 2538U,
+ 1582U, 4432U, 4385U, 4581U, 3433U, 1680U, 2569U, 4427U,
+ 4648U, 4600U, 419U, 937U, 3028U, 2091U, 1965U, 4665U,
+ 3154U, 2250U, 2409U, 886U, 389U, 1610U, 1957U, 1653U,
+ 4543U, 4571U, 4082U, 1700U, 4401U, 4444U, 400U, 1615U,
+ 4529U, 4510U, 3972U, 1961U, 1660U, 4549U, 4576U, 425U,
+ 4517U, 4621U, 2879U, 3977U, 1641U, 3470U, 1679U,
+};
+
+static inline void InitRISCVMCInstrInfo(MCInstrInfo *II) {
+ II->InitMCInstrInfo(RISCVInsts, RISCVInstrNameIndices, RISCVInstrNameData, 511);
+}
+
+} // end namespace llvm
+#endif // GET_INSTRINFO_MC_DESC
+
+#ifdef GET_INSTRINFO_HEADER
+#undef GET_INSTRINFO_HEADER
+namespace llvm {
+struct RISCVGenInstrInfo : public TargetInstrInfo {
+ explicit RISCVGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1);
+ ~RISCVGenInstrInfo() override = default;
+
+};
+} // end namespace llvm
+#endif // GET_INSTRINFO_HEADER
+
+#ifdef GET_INSTRINFO_HELPER_DECLS
+#undef GET_INSTRINFO_HELPER_DECLS
+
+
+#endif // GET_INSTRINFO_HELPER_DECLS
+
+#ifdef GET_INSTRINFO_HELPERS
+#undef GET_INSTRINFO_HELPERS
+
+#endif // GET_INSTRINFO_HELPERS
+
+#ifdef GET_INSTRINFO_CTOR_DTOR
+#undef GET_INSTRINFO_CTOR_DTOR
+namespace llvm {
+extern const MCInstrDesc RISCVInsts[];
+extern const unsigned RISCVInstrNameIndices[];
+extern const char RISCVInstrNameData[];
+RISCVGenInstrInfo::RISCVGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode)
+ : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
+ InitMCInstrInfo(RISCVInsts, RISCVInstrNameIndices, RISCVInstrNameData, 511);
+}
+} // end namespace llvm
+#endif // GET_INSTRINFO_CTOR_DTOR
+
+#ifdef GET_INSTRINFO_OPERAND_ENUM
+#undef GET_INSTRINFO_OPERAND_ENUM
+namespace llvm {
+namespace RISCV {
+namespace OpName {
+enum {
+OPERAND_LAST
+};
+} // end namespace OpName
+} // end namespace RISCV
+} // end namespace llvm
+#endif //GET_INSTRINFO_OPERAND_ENUM
+
+#ifdef GET_INSTRINFO_NAMED_OPS
+#undef GET_INSTRINFO_NAMED_OPS
+namespace llvm {
+namespace RISCV {
+LLVM_READONLY
+int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
+ return -1;
+}
+} // end namespace RISCV
+} // end namespace llvm
+#endif //GET_INSTRINFO_NAMED_OPS
+
+#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
+#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
+namespace llvm {
+namespace RISCV {
+namespace OpTypes {
+enum OperandType {
+ bare_symbol = 0,
+ c_lui_imm = 1,
+ call_symbol = 2,
+ csr_sysreg = 3,
+ f32imm = 4,
+ f64imm = 5,
+ fencearg = 6,
+ frmarg = 7,
+ i16imm = 8,
+ i1imm = 9,
+ i32imm = 10,
+ i64imm = 11,
+ i8imm = 12,
+ immzero = 13,
+ ixlenimm = 14,
+ ixlenimm_li = 15,
+ ptype0 = 16,
+ ptype1 = 17,
+ ptype2 = 18,
+ ptype3 = 19,
+ ptype4 = 20,
+ ptype5 = 21,
+ simm10_lsb0000nonzero = 22,
+ simm12 = 23,
+ simm12_lsb0 = 24,
+ simm13_lsb0 = 25,
+ simm21_lsb0_jal = 26,
+ simm6 = 27,
+ simm6nonzero = 28,
+ simm9_lsb0 = 29,
+ tprel_add_symbol = 30,
+ type0 = 31,
+ type1 = 32,
+ type2 = 33,
+ type3 = 34,
+ type4 = 35,
+ type5 = 36,
+ uimm10_lsb00nonzero = 37,
+ uimm20_auipc = 38,
+ uimm20_lui = 39,
+ uimm5 = 40,
+ uimm7_lsb00 = 41,
+ uimm8_lsb00 = 42,
+ uimm8_lsb000 = 43,
+ uimm9_lsb000 = 44,
+ uimmlog2xlen = 45,
+ uimmlog2xlennonzero = 46,
+ untyped_imm_0 = 47,
+ GPRMemAtomic = 48,
+ FPR32 = 49,
+ FPR32C = 50,
+ FPR64 = 51,
+ FPR64C = 52,
+ GPR = 53,
+ GPRC = 54,
+ GPRNoX0 = 55,
+ GPRNoX0X2 = 56,
+ GPRTC = 57,
+ GPRX0 = 58,
+ SP = 59,
+ OPERAND_TYPE_LIST_END
+};
+} // end namespace OpTypes
+} // end namespace RISCV
+} // end namespace llvm
+#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
+
+#ifdef GET_INSTRINFO_OPERAND_TYPE
+#undef GET_INSTRINFO_OPERAND_TYPE
+namespace llvm {
+namespace RISCV {
+LLVM_READONLY
+static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
+ const int Offsets[] = {
+ 0,
+ 1,
+ 1,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 5,
+ 8,
+ 12,
+ 13,
+ 17,
+ 20,
+ 20,
+ 21,
+ 23,
+ 25,
+ 25,
+ 26,
+ 27,
+ 29,
+ 29,
+ 35,
+ 36,
+ 36,
+ 38,
+ 39,
+ 39,
+ 39,
+ 39,
+ 39,
+ 39,
+ 41,
+ 44,
+ 44,
+ 47,
+ 50,
+ 53,
+ 56,
+ 59,
+ 62,
+ 65,
+ 68,
+ 71,
+ 74,
+ 75,
+ 76,
+ 78,
+ 80,
+ 83,
+ 85,
+ 89,
+ 91,
+ 93,
+ 95,
+ 97,
+ 99,
+ 101,
+ 103,
+ 105,
+ 107,
+ 108,
+ 110,
+ 112,
+ 114,
+ 119,
+ 124,
+ 129,
+ 131,
+ 136,
+ 141,
+ 145,
+ 148,
+ 151,
+ 154,
+ 157,
+ 160,
+ 163,
+ 166,
+ 169,
+ 172,
+ 175,
+ 178,
+ 181,
+ 184,
+ 186,
+ 188,
+ 189,
+ 190,
+ 191,
+ 193,
+ 195,
+ 197,
+ 199,
+ 200,
+ 203,
+ 205,
+ 208,
+ 210,
+ 213,
+ 216,
+ 219,
+ 223,
+ 227,
+ 231,
+ 235,
+ 240,
+ 244,
+ 249,
+ 253,
+ 258,
+ 262,
+ 267,
+ 271,
+ 275,
+ 278,
+ 281,
+ 284,
+ 287,
+ 290,
+ 294,
+ 298,
+ 301,
+ 304,
+ 307,
+ 309,
+ 311,
+ 313,
+ 315,
+ 317,
+ 319,
+ 321,
+ 323,
+ 325,
+ 327,
+ 329,
+ 331,
+ 333,
+ 336,
+ 338,
+ 341,
+ 344,
+ 347,
+ 350,
+ 353,
+ 356,
+ 359,
+ 362,
+ 365,
+ 368,
+ 371,
+ 374,
+ 375,
+ 378,
+ 382,
+ 385,
+ 389,
+ 391,
+ 393,
+ 395,
+ 397,
+ 399,
+ 401,
+ 403,
+ 405,
+ 407,
+ 409,
+ 411,
+ 413,
+ 415,
+ 417,
+ 419,
+ 421,
+ 423,
+ 426,
+ 428,
+ 430,
+ 432,
+ 434,
+ 437,
+ 441,
+ 446,
+ 451,
+ 452,
+ 454,
+ 455,
+ 456,
+ 458,
+ 464,
+ 470,
+ 473,
+ 476,
+ 479,
+ 482,
+ 484,
+ 486,
+ 488,
+ 490,
+ 492,
+ 494,
+ 496,
+ 498,
+ 500,
+ 502,
+ 504,
+ 506,
+ 512,
+ 520,
+ 528,
+ 534,
+ 540,
+ 547,
+ 554,
+ 560,
+ 567,
+ 567,
+ 570,
+ 573,
+ 576,
+ 579,
+ 580,
+ 581,
+ 583,
+ 589,
+ 595,
+ 601,
+ 604,
+ 607,
+ 610,
+ 613,
+ 616,
+ 619,
+ 622,
+ 625,
+ 628,
+ 631,
+ 634,
+ 637,
+ 640,
+ 643,
+ 646,
+ 649,
+ 652,
+ 655,
+ 658,
+ 661,
+ 664,
+ 667,
+ 670,
+ 673,
+ 676,
+ 679,
+ 682,
+ 685,
+ 688,
+ 691,
+ 694,
+ 697,
+ 700,
+ 703,
+ 706,
+ 709,
+ 712,
+ 715,
+ 718,
+ 721,
+ 724,
+ 727,
+ 730,
+ 733,
+ 736,
+ 739,
+ 742,
+ 745,
+ 748,
+ 751,
+ 754,
+ 757,
+ 760,
+ 763,
+ 766,
+ 769,
+ 772,
+ 775,
+ 778,
+ 781,
+ 784,
+ 787,
+ 790,
+ 793,
+ 796,
+ 799,
+ 802,
+ 805,
+ 808,
+ 811,
+ 814,
+ 817,
+ 820,
+ 823,
+ 826,
+ 829,
+ 832,
+ 835,
+ 838,
+ 840,
+ 843,
+ 846,
+ 849,
+ 852,
+ 855,
+ 858,
+ 861,
+ 864,
+ 867,
+ 870,
+ 873,
+ 876,
+ 879,
+ 882,
+ 885,
+ 888,
+ 891,
+ 894,
+ 897,
+ 900,
+ 903,
+ 906,
+ 909,
+ 912,
+ 914,
+ 916,
+ 916,
+ 919,
+ 922,
+ 925,
+ 928,
+ 931,
+ 934,
+ 937,
+ 940,
+ 941,
+ 942,
+ 943,
+ 944,
+ 947,
+ 950,
+ 952,
+ 954,
+ 956,
+ 958,
+ 961,
+ 964,
+ 966,
+ 968,
+ 968,
+ 969,
+ 972,
+ 975,
+ 978,
+ 981,
+ 983,
+ 986,
+ 989,
+ 991,
+ 994,
+ 996,
+ 999,
+ 1002,
+ 1005,
+ 1008,
+ 1008,
+ 1011,
+ 1014,
+ 1017,
+ 1020,
+ 1023,
+ 1023,
+ 1023,
+ 1027,
+ 1031,
+ 1033,
+ 1035,
+ 1038,
+ 1041,
+ 1043,
+ 1045,
+ 1047,
+ 1050,
+ 1053,
+ 1056,
+ 1059,
+ 1062,
+ 1065,
+ 1068,
+ 1071,
+ 1074,
+ 1077,
+ 1080,
+ 1083,
+ 1086,
+ 1090,
+ 1094,
+ 1096,
+ 1096,
+ 1096,
+ 1099,
+ 1102,
+ 1105,
+ 1108,
+ 1111,
+ 1114,
+ 1117,
+ 1120,
+ 1125,
+ 1130,
+ 1133,
+ 1136,
+ 1139,
+ 1142,
+ 1147,
+ 1152,
+ 1156,
+ 1160,
+ 1162,
+ 1164,
+ 1166,
+ 1168,
+ 1173,
+ 1178,
+ 1183,
+ 1188,
+ 1191,
+ 1194,
+ 1197,
+ 1200,
+ 1203,
+ 1206,
+ 1209,
+ 1212,
+ 1215,
+ 1219,
+ 1223,
+ 1226,
+ 1228,
+ 1231,
+ 1234,
+ 1237,
+ 1240,
+ 1243,
+ 1246,
+ 1248,
+ 1250,
+ 1252,
+ 1254,
+ 1256,
+ 1258,
+ 1260,
+ 1262,
+ 1264,
+ 1267,
+ 1270,
+ 1272,
+ 1275,
+ 1278,
+ 1281,
+ 1284,
+ 1287,
+ 1290,
+ 1293,
+ 1296,
+ 1299,
+ 1302,
+ 1305,
+ 1308,
+ 1311,
+ 1314,
+ 1317,
+ 1320,
+ 1323,
+ 1326,
+ 1329,
+ 1332,
+ 1335,
+ 1337,
+ 1340,
+ 1343,
+ 1346,
+ 1349,
+ 1352,
+ 1355,
+ 1358,
+ 1361,
+ 1364,
+ 1367,
+ 1370,
+ 1373,
+ 1376,
+ 1378,
+ 1381,
+ 1384,
+ 1387,
+ 1390,
+ 1393,
+ 1396,
+ 1399,
+ 1399,
+ 1401,
+ 1403,
+ 1406,
+ };
+ const int OpcodeOperandTypes[] = {
+ -1,
+ /**/
+ /**/
+ OpTypes::i32imm,
+ OpTypes::i32imm,
+ OpTypes::i32imm,
+ OpTypes::i32imm,
+ /**/
+ -1, -1, OpTypes::i32imm,
+ -1, -1, -1, OpTypes::i32imm,
+ -1,
+ -1, -1, -1, OpTypes::i32imm,
+ -1, -1, OpTypes::i32imm,
+ /**/
+ -1,
+ -1, -1,
+ -1, -1,
+ /**/
+ OpTypes::i32imm,
+ OpTypes::i32imm,
+ OpTypes::i64imm, OpTypes::i32imm,
+ /**/
+ -1, OpTypes::i64imm, OpTypes::i32imm, -1, OpTypes::i32imm, OpTypes::i32imm,
+ -1,
+ /**/
+ -1, OpTypes::i32imm,
+ -1,
+ /**/
+ /**/
+ /**/
+ /**/
+ /**/
+ -1, -1,
+ -1, -1, -1,
+ /**/
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0,
+ OpTypes::type0,
+ OpTypes::type0, -1,
+ OpTypes::type0, -1,
+ OpTypes::type0, OpTypes::type1, -1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0, OpTypes::type1, -1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1,
+ OpTypes::type0, OpTypes::ptype1,
+ OpTypes::type0, OpTypes::ptype1,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1,
+ OpTypes::type0, OpTypes::ptype1,
+ OpTypes::ptype0, OpTypes::type1, OpTypes::ptype0, OpTypes::ptype2, -1,
+ OpTypes::type0, OpTypes::type1, OpTypes::type2, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::type0, OpTypes::ptype1, OpTypes::type0,
+ OpTypes::i32imm, OpTypes::i32imm,
+ OpTypes::type0, -1,
+ OpTypes::type0,
+ -1,
+ -1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, -1,
+ OpTypes::type0, -1,
+ OpTypes::type0,
+ OpTypes::type0, OpTypes::type1, -1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0, OpTypes::untyped_imm_0,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, -1, OpTypes::type1, OpTypes::type1,
+ OpTypes::type0, -1, OpTypes::type1, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0, -1,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0, OpTypes::type0,
+ -1,
+ OpTypes::ptype0, -1, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0, OpTypes::type1, OpTypes::type2,
+ OpTypes::type0, OpTypes::type1, OpTypes::type2,
+ OpTypes::type0, OpTypes::type1, OpTypes::type1, -1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type0,
+ OpTypes::type0, OpTypes::type1,
+ OpTypes::type0, -1,
+ OpTypes::type0, -1,
+ OpTypes::ptype0, OpTypes::type1, OpTypes::i32imm,
+ OpTypes::type0, -1,
+ -1, OpTypes::type0,
+ OpTypes::i32imm, OpTypes::i32imm,
+ OpTypes::i32imm, OpTypes::i32imm,
+ OpTypes::FPR64, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::tprel_add_symbol,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::simm21_lsb0_jal,
+ OpTypes::GPR, OpTypes::simm12,
+ OpTypes::call_symbol,
+ OpTypes::GPR,
+ OpTypes::GPR, OpTypes::call_symbol,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::FPR64, OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::FPR64, OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::ixlenimm_li,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm,
+ /**/
+ OpTypes::GPR, OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::bare_symbol,
+ OpTypes::call_symbol,
+ OpTypes::GPRTC,
+ OpTypes::GPR, OpTypes::GPR,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR, OpTypes::ixlenimm, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::FPR64,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::uimm20_auipc,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm13_lsb0,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm13_lsb0,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm13_lsb0,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm13_lsb0,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm13_lsb0,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm13_lsb0,
+ OpTypes::GPR, OpTypes::csr_sysreg, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::csr_sysreg, OpTypes::uimm5,
+ OpTypes::GPR, OpTypes::csr_sysreg, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::csr_sysreg, OpTypes::uimm5,
+ OpTypes::GPR, OpTypes::csr_sysreg, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::csr_sysreg, OpTypes::uimm5,
+ OpTypes::GPRNoX0, OpTypes::GPRNoX0, OpTypes::GPRNoX0,
+ OpTypes::GPRNoX0, OpTypes::GPRNoX0, OpTypes::simm6nonzero,
+ OpTypes::SP, OpTypes::SP, OpTypes::simm10_lsb0000nonzero,
+ OpTypes::GPRC, OpTypes::SP, OpTypes::uimm10_lsb00nonzero,
+ OpTypes::GPRNoX0, OpTypes::GPRNoX0, OpTypes::simm6,
+ OpTypes::GPRNoX0, OpTypes::GPRNoX0, OpTypes::immzero,
+ OpTypes::GPRX0, OpTypes::GPRX0, OpTypes::simm6nonzero,
+ OpTypes::GPRX0, OpTypes::GPRX0, OpTypes::immzero,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::GPRC,
+ OpTypes::GPRX0, OpTypes::GPRX0, OpTypes::GPRNoX0,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::GPRC,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::simm6,
+ OpTypes::GPRC, OpTypes::simm9_lsb0,
+ OpTypes::GPRC, OpTypes::simm9_lsb0,
+ /**/
+ OpTypes::FPR64C, OpTypes::GPRC, OpTypes::uimm8_lsb000,
+ OpTypes::FPR64, OpTypes::SP, OpTypes::uimm9_lsb000,
+ OpTypes::FPR32C, OpTypes::GPRC, OpTypes::uimm7_lsb00,
+ OpTypes::FPR32, OpTypes::SP, OpTypes::uimm8_lsb00,
+ OpTypes::FPR64C, OpTypes::GPRC, OpTypes::uimm8_lsb000,
+ OpTypes::FPR64, OpTypes::SP, OpTypes::uimm9_lsb000,
+ OpTypes::FPR32C, OpTypes::GPRC, OpTypes::uimm7_lsb00,
+ OpTypes::FPR32, OpTypes::SP, OpTypes::uimm8_lsb00,
+ OpTypes::simm12_lsb0,
+ OpTypes::simm12_lsb0,
+ OpTypes::GPRNoX0,
+ OpTypes::GPRNoX0,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::uimm8_lsb000,
+ OpTypes::GPRNoX0, OpTypes::SP, OpTypes::uimm9_lsb000,
+ OpTypes::GPRNoX0, OpTypes::simm6,
+ OpTypes::GPRX0, OpTypes::simm6,
+ OpTypes::GPRNoX0X2, OpTypes::c_lui_imm,
+ OpTypes::GPRX0, OpTypes::c_lui_imm,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::uimm7_lsb00,
+ OpTypes::GPRNoX0, OpTypes::SP, OpTypes::uimm8_lsb00,
+ OpTypes::GPRNoX0, OpTypes::GPRNoX0,
+ OpTypes::GPRX0, OpTypes::GPRNoX0,
+ /**/
+ OpTypes::simm6nonzero,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::GPRC,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::uimm8_lsb000,
+ OpTypes::GPR, OpTypes::SP, OpTypes::uimm9_lsb000,
+ OpTypes::GPRNoX0, OpTypes::GPRNoX0, OpTypes::uimmlog2xlennonzero,
+ OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPRX0, OpTypes::GPRX0, OpTypes::uimmlog2xlennonzero,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::uimmlog2xlennonzero,
+ OpTypes::GPRC, OpTypes::GPRC,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::uimmlog2xlennonzero,
+ OpTypes::GPRC, OpTypes::GPRC,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::GPRC,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::GPRC,
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::uimm7_lsb00,
+ OpTypes::GPR, OpTypes::SP, OpTypes::uimm8_lsb00,
+ /**/
+ OpTypes::GPRC, OpTypes::GPRC, OpTypes::GPRC,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ /**/
+ /**/
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::GPR, OpTypes::FPR64,
+ OpTypes::GPR, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::GPR, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::GPR, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::GPR,
+ OpTypes::FPR64, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::GPR, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::GPR, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::GPR, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::frmarg,
+ OpTypes::GPR, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::GPR, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::GPR, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::GPR, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::fencearg, OpTypes::fencearg,
+ /**/
+ /**/
+ OpTypes::GPR, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::GPR, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::GPR, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::GPR, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::GPR, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::GPR,
+ OpTypes::FPR32, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::FPR64,
+ OpTypes::GPR, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR64, OpTypes::FPR64, OpTypes::FPR64, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::FPR32, OpTypes::FPR32, OpTypes::frmarg,
+ OpTypes::FPR32, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::simm21_lsb0_jal,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPRMemAtomic,
+ OpTypes::GPR, OpTypes::GPRMemAtomic,
+ OpTypes::GPR, OpTypes::GPRMemAtomic,
+ OpTypes::GPR, OpTypes::GPRMemAtomic,
+ OpTypes::GPR, OpTypes::GPRMemAtomic,
+ OpTypes::GPR, OpTypes::GPRMemAtomic,
+ OpTypes::GPR, OpTypes::GPRMemAtomic,
+ OpTypes::GPR, OpTypes::GPRMemAtomic,
+ OpTypes::GPR, OpTypes::uimm20_lui,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPRMemAtomic, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::uimmlog2xlen,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::uimm5,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::uimmlog2xlen,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::uimm5,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::uimmlog2xlen,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::uimm5,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ /**/
+ OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::GPR,
+ OpTypes::GPR, OpTypes::GPR, OpTypes::simm12,
+ };
+ return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
+}
+} // end namespace RISCV
+} // end namespace llvm
+#endif // GET_INSTRINFO_OPERAND_TYPE
+
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc
new file mode 100644
index 0000000..6b78802
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc
@@ -0,0 +1,2024 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Machine Code Emitter *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+uint64_t RISCVMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ static const uint64_t InstBits[] = {
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(0),
+ UINT64_C(51), // ADD
+ UINT64_C(19), // ADDI
+ UINT64_C(27), // ADDIW
+ UINT64_C(59), // ADDW
+ UINT64_C(12335), // AMOADD_D
+ UINT64_C(67121199), // AMOADD_D_AQ
+ UINT64_C(100675631), // AMOADD_D_AQ_RL
+ UINT64_C(33566767), // AMOADD_D_RL
+ UINT64_C(8239), // AMOADD_W
+ UINT64_C(67117103), // AMOADD_W_AQ
+ UINT64_C(100671535), // AMOADD_W_AQ_RL
+ UINT64_C(33562671), // AMOADD_W_RL
+ UINT64_C(1610625071), // AMOAND_D
+ UINT64_C(1677733935), // AMOAND_D_AQ
+ UINT64_C(1711288367), // AMOAND_D_AQ_RL
+ UINT64_C(1644179503), // AMOAND_D_RL
+ UINT64_C(1610620975), // AMOAND_W
+ UINT64_C(1677729839), // AMOAND_W_AQ
+ UINT64_C(1711284271), // AMOAND_W_AQ_RL
+ UINT64_C(1644175407), // AMOAND_W_RL
+ UINT64_C(3758108719), // AMOMAXU_D
+ UINT64_C(3825217583), // AMOMAXU_D_AQ
+ UINT64_C(3858772015), // AMOMAXU_D_AQ_RL
+ UINT64_C(3791663151), // AMOMAXU_D_RL
+ UINT64_C(3758104623), // AMOMAXU_W
+ UINT64_C(3825213487), // AMOMAXU_W_AQ
+ UINT64_C(3858767919), // AMOMAXU_W_AQ_RL
+ UINT64_C(3791659055), // AMOMAXU_W_RL
+ UINT64_C(2684366895), // AMOMAX_D
+ UINT64_C(2751475759), // AMOMAX_D_AQ
+ UINT64_C(2785030191), // AMOMAX_D_AQ_RL
+ UINT64_C(2717921327), // AMOMAX_D_RL
+ UINT64_C(2684362799), // AMOMAX_W
+ UINT64_C(2751471663), // AMOMAX_W_AQ
+ UINT64_C(2785026095), // AMOMAX_W_AQ_RL
+ UINT64_C(2717917231), // AMOMAX_W_RL
+ UINT64_C(3221237807), // AMOMINU_D
+ UINT64_C(3288346671), // AMOMINU_D_AQ
+ UINT64_C(3321901103), // AMOMINU_D_AQ_RL
+ UINT64_C(3254792239), // AMOMINU_D_RL
+ UINT64_C(3221233711), // AMOMINU_W
+ UINT64_C(3288342575), // AMOMINU_W_AQ
+ UINT64_C(3321897007), // AMOMINU_W_AQ_RL
+ UINT64_C(3254788143), // AMOMINU_W_RL
+ UINT64_C(2147495983), // AMOMIN_D
+ UINT64_C(2214604847), // AMOMIN_D_AQ
+ UINT64_C(2248159279), // AMOMIN_D_AQ_RL
+ UINT64_C(2181050415), // AMOMIN_D_RL
+ UINT64_C(2147491887), // AMOMIN_W
+ UINT64_C(2214600751), // AMOMIN_W_AQ
+ UINT64_C(2248155183), // AMOMIN_W_AQ_RL
+ UINT64_C(2181046319), // AMOMIN_W_RL
+ UINT64_C(1073754159), // AMOOR_D
+ UINT64_C(1140863023), // AMOOR_D_AQ
+ UINT64_C(1174417455), // AMOOR_D_AQ_RL
+ UINT64_C(1107308591), // AMOOR_D_RL
+ UINT64_C(1073750063), // AMOOR_W
+ UINT64_C(1140858927), // AMOOR_W_AQ
+ UINT64_C(1174413359), // AMOOR_W_AQ_RL
+ UINT64_C(1107304495), // AMOOR_W_RL
+ UINT64_C(134230063), // AMOSWAP_D
+ UINT64_C(201338927), // AMOSWAP_D_AQ
+ UINT64_C(234893359), // AMOSWAP_D_AQ_RL
+ UINT64_C(167784495), // AMOSWAP_D_RL
+ UINT64_C(134225967), // AMOSWAP_W
+ UINT64_C(201334831), // AMOSWAP_W_AQ
+ UINT64_C(234889263), // AMOSWAP_W_AQ_RL
+ UINT64_C(167780399), // AMOSWAP_W_RL
+ UINT64_C(536883247), // AMOXOR_D
+ UINT64_C(603992111), // AMOXOR_D_AQ
+ UINT64_C(637546543), // AMOXOR_D_AQ_RL
+ UINT64_C(570437679), // AMOXOR_D_RL
+ UINT64_C(536879151), // AMOXOR_W
+ UINT64_C(603988015), // AMOXOR_W_AQ
+ UINT64_C(637542447), // AMOXOR_W_AQ_RL
+ UINT64_C(570433583), // AMOXOR_W_RL
+ UINT64_C(28723), // AND
+ UINT64_C(28691), // ANDI
+ UINT64_C(23), // AUIPC
+ UINT64_C(99), // BEQ
+ UINT64_C(20579), // BGE
+ UINT64_C(28771), // BGEU
+ UINT64_C(16483), // BLT
+ UINT64_C(24675), // BLTU
+ UINT64_C(4195), // BNE
+ UINT64_C(12403), // CSRRC
+ UINT64_C(28787), // CSRRCI
+ UINT64_C(8307), // CSRRS
+ UINT64_C(24691), // CSRRSI
+ UINT64_C(4211), // CSRRW
+ UINT64_C(20595), // CSRRWI
+ UINT64_C(36866), // C_ADD
+ UINT64_C(1), // C_ADDI
+ UINT64_C(24833), // C_ADDI16SP
+ UINT64_C(0), // C_ADDI4SPN
+ UINT64_C(8193), // C_ADDIW
+ UINT64_C(1), // C_ADDI_HINT_IMM_ZERO
+ UINT64_C(1), // C_ADDI_HINT_X0
+ UINT64_C(1), // C_ADDI_NOP
+ UINT64_C(39969), // C_ADDW
+ UINT64_C(36866), // C_ADD_HINT
+ UINT64_C(35937), // C_AND
+ UINT64_C(34817), // C_ANDI
+ UINT64_C(49153), // C_BEQZ
+ UINT64_C(57345), // C_BNEZ
+ UINT64_C(36866), // C_EBREAK
+ UINT64_C(8192), // C_FLD
+ UINT64_C(8194), // C_FLDSP
+ UINT64_C(24576), // C_FLW
+ UINT64_C(24578), // C_FLWSP
+ UINT64_C(40960), // C_FSD
+ UINT64_C(40962), // C_FSDSP
+ UINT64_C(57344), // C_FSW
+ UINT64_C(57346), // C_FSWSP
+ UINT64_C(40961), // C_J
+ UINT64_C(8193), // C_JAL
+ UINT64_C(36866), // C_JALR
+ UINT64_C(32770), // C_JR
+ UINT64_C(24576), // C_LD
+ UINT64_C(24578), // C_LDSP
+ UINT64_C(16385), // C_LI
+ UINT64_C(16385), // C_LI_HINT
+ UINT64_C(24577), // C_LUI
+ UINT64_C(24577), // C_LUI_HINT
+ UINT64_C(16384), // C_LW
+ UINT64_C(16386), // C_LWSP
+ UINT64_C(32770), // C_MV
+ UINT64_C(32770), // C_MV_HINT
+ UINT64_C(1), // C_NOP
+ UINT64_C(1), // C_NOP_HINT
+ UINT64_C(35905), // C_OR
+ UINT64_C(57344), // C_SD
+ UINT64_C(57346), // C_SDSP
+ UINT64_C(2), // C_SLLI
+ UINT64_C(2), // C_SLLI64_HINT
+ UINT64_C(2), // C_SLLI_HINT
+ UINT64_C(33793), // C_SRAI
+ UINT64_C(33793), // C_SRAI64_HINT
+ UINT64_C(32769), // C_SRLI
+ UINT64_C(32769), // C_SRLI64_HINT
+ UINT64_C(35841), // C_SUB
+ UINT64_C(39937), // C_SUBW
+ UINT64_C(49152), // C_SW
+ UINT64_C(49154), // C_SWSP
+ UINT64_C(0), // C_UNIMP
+ UINT64_C(35873), // C_XOR
+ UINT64_C(33570867), // DIV
+ UINT64_C(33574963), // DIVU
+ UINT64_C(33574971), // DIVUW
+ UINT64_C(33570875), // DIVW
+ UINT64_C(1048691), // EBREAK
+ UINT64_C(115), // ECALL
+ UINT64_C(33554515), // FADD_D
+ UINT64_C(83), // FADD_S
+ UINT64_C(3791654995), // FCLASS_D
+ UINT64_C(3758100563), // FCLASS_S
+ UINT64_C(3525312595), // FCVT_D_L
+ UINT64_C(3526361171), // FCVT_D_LU
+ UINT64_C(1107296339), // FCVT_D_S
+ UINT64_C(3523215443), // FCVT_D_W
+ UINT64_C(3524264019), // FCVT_D_WU
+ UINT64_C(3257925715), // FCVT_LU_D
+ UINT64_C(3224371283), // FCVT_LU_S
+ UINT64_C(3256877139), // FCVT_L_D
+ UINT64_C(3223322707), // FCVT_L_S
+ UINT64_C(1074790483), // FCVT_S_D
+ UINT64_C(3491758163), // FCVT_S_L
+ UINT64_C(3492806739), // FCVT_S_LU
+ UINT64_C(3489661011), // FCVT_S_W
+ UINT64_C(3490709587), // FCVT_S_WU
+ UINT64_C(3255828563), // FCVT_WU_D
+ UINT64_C(3222274131), // FCVT_WU_S
+ UINT64_C(3254779987), // FCVT_W_D
+ UINT64_C(3221225555), // FCVT_W_S
+ UINT64_C(436207699), // FDIV_D
+ UINT64_C(402653267), // FDIV_S
+ UINT64_C(15), // FENCE
+ UINT64_C(4111), // FENCE_I
+ UINT64_C(2200961039), // FENCE_TSO
+ UINT64_C(2717917267), // FEQ_D
+ UINT64_C(2684362835), // FEQ_S
+ UINT64_C(12295), // FLD
+ UINT64_C(2717909075), // FLE_D
+ UINT64_C(2684354643), // FLE_S
+ UINT64_C(2717913171), // FLT_D
+ UINT64_C(2684358739), // FLT_S
+ UINT64_C(8199), // FLW
+ UINT64_C(33554499), // FMADD_D
+ UINT64_C(67), // FMADD_S
+ UINT64_C(704647251), // FMAX_D
+ UINT64_C(671092819), // FMAX_S
+ UINT64_C(704643155), // FMIN_D
+ UINT64_C(671088723), // FMIN_S
+ UINT64_C(33554503), // FMSUB_D
+ UINT64_C(71), // FMSUB_S
+ UINT64_C(301989971), // FMUL_D
+ UINT64_C(268435539), // FMUL_S
+ UINT64_C(4060086355), // FMV_D_X
+ UINT64_C(4026531923), // FMV_W_X
+ UINT64_C(3791650899), // FMV_X_D
+ UINT64_C(3758096467), // FMV_X_W
+ UINT64_C(33554511), // FNMADD_D
+ UINT64_C(79), // FNMADD_S
+ UINT64_C(33554507), // FNMSUB_D
+ UINT64_C(75), // FNMSUB_S
+ UINT64_C(12327), // FSD
+ UINT64_C(570429523), // FSGNJN_D
+ UINT64_C(536875091), // FSGNJN_S
+ UINT64_C(570433619), // FSGNJX_D
+ UINT64_C(536879187), // FSGNJX_S
+ UINT64_C(570425427), // FSGNJ_D
+ UINT64_C(536870995), // FSGNJ_S
+ UINT64_C(1509949523), // FSQRT_D
+ UINT64_C(1476395091), // FSQRT_S
+ UINT64_C(167772243), // FSUB_D
+ UINT64_C(134217811), // FSUB_S
+ UINT64_C(8231), // FSW
+ UINT64_C(111), // JAL
+ UINT64_C(103), // JALR
+ UINT64_C(3), // LB
+ UINT64_C(16387), // LBU
+ UINT64_C(12291), // LD
+ UINT64_C(4099), // LH
+ UINT64_C(20483), // LHU
+ UINT64_C(268447791), // LR_D
+ UINT64_C(335556655), // LR_D_AQ
+ UINT64_C(369111087), // LR_D_AQ_RL
+ UINT64_C(302002223), // LR_D_RL
+ UINT64_C(268443695), // LR_W
+ UINT64_C(335552559), // LR_W_AQ
+ UINT64_C(369106991), // LR_W_AQ_RL
+ UINT64_C(301998127), // LR_W_RL
+ UINT64_C(55), // LUI
+ UINT64_C(8195), // LW
+ UINT64_C(24579), // LWU
+ UINT64_C(807403635), // MRET
+ UINT64_C(33554483), // MUL
+ UINT64_C(33558579), // MULH
+ UINT64_C(33562675), // MULHSU
+ UINT64_C(33566771), // MULHU
+ UINT64_C(33554491), // MULW
+ UINT64_C(24627), // OR
+ UINT64_C(24595), // ORI
+ UINT64_C(33579059), // REM
+ UINT64_C(33583155), // REMU
+ UINT64_C(33583163), // REMUW
+ UINT64_C(33579067), // REMW
+ UINT64_C(35), // SB
+ UINT64_C(402665519), // SC_D
+ UINT64_C(469774383), // SC_D_AQ
+ UINT64_C(503328815), // SC_D_AQ_RL
+ UINT64_C(436219951), // SC_D_RL
+ UINT64_C(402661423), // SC_W
+ UINT64_C(469770287), // SC_W_AQ
+ UINT64_C(503324719), // SC_W_AQ_RL
+ UINT64_C(436215855), // SC_W_RL
+ UINT64_C(12323), // SD
+ UINT64_C(301990003), // SFENCE_VMA
+ UINT64_C(4131), // SH
+ UINT64_C(4147), // SLL
+ UINT64_C(4115), // SLLI
+ UINT64_C(4123), // SLLIW
+ UINT64_C(4155), // SLLW
+ UINT64_C(8243), // SLT
+ UINT64_C(8211), // SLTI
+ UINT64_C(12307), // SLTIU
+ UINT64_C(12339), // SLTU
+ UINT64_C(1073762355), // SRA
+ UINT64_C(1073762323), // SRAI
+ UINT64_C(1073762331), // SRAIW
+ UINT64_C(1073762363), // SRAW
+ UINT64_C(270532723), // SRET
+ UINT64_C(20531), // SRL
+ UINT64_C(20499), // SRLI
+ UINT64_C(20507), // SRLIW
+ UINT64_C(20539), // SRLW
+ UINT64_C(1073741875), // SUB
+ UINT64_C(1073741883), // SUBW
+ UINT64_C(8227), // SW
+ UINT64_C(3221229683), // UNIMP
+ UINT64_C(2097267), // URET
+ UINT64_C(273678451), // WFI
+ UINT64_C(16435), // XOR
+ UINT64_C(16403), // XORI
+ UINT64_C(0)
+ };
+ const unsigned opcode = MI.getOpcode();
+ uint64_t Value = InstBits[opcode];
+ uint64_t op = 0;
+ (void)op; // suppress warning
+ switch (opcode) {
+ case RISCV::C_EBREAK:
+ case RISCV::C_NOP:
+ case RISCV::C_UNIMP:
+ case RISCV::EBREAK:
+ case RISCV::ECALL:
+ case RISCV::FENCE_I:
+ case RISCV::FENCE_TSO:
+ case RISCV::MRET:
+ case RISCV::SRET:
+ case RISCV::UNIMP:
+ case RISCV::URET:
+ case RISCV::WFI: {
+ break;
+ }
+ case RISCV::C_NOP_HINT: {
+ // op: imm
+ op = getImmOpValue(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(31)) << 2;
+ break;
+ }
+ case RISCV::C_LI_HINT:
+ case RISCV::C_LUI_HINT: {
+ // op: imm
+ op = getImmOpValue(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(31)) << 2;
+ break;
+ }
+ case RISCV::C_LI:
+ case RISCV::C_LUI: {
+ // op: imm
+ op = getImmOpValue(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(31)) << 2;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_FLDSP:
+ case RISCV::C_LDSP: {
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(24)) << 2;
+ Value |= (op & UINT64_C(448)) >> 4;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_FLWSP:
+ case RISCV::C_LWSP: {
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(28)) << 2;
+ Value |= (op & UINT64_C(192)) >> 4;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_ADDI:
+ case RISCV::C_ADDIW:
+ case RISCV::C_ADDI_HINT_X0: {
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(31)) << 2;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_ANDI: {
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(31)) << 2;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_ADDI4SPN: {
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(48)) << 7;
+ Value |= (op & UINT64_C(960)) << 1;
+ Value |= (op & UINT64_C(4)) << 4;
+ Value |= (op & UINT64_C(8)) << 2;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 2;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_ADDI16SP: {
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(512)) << 3;
+ Value |= (op & UINT64_C(16)) << 2;
+ Value |= (op & UINT64_C(64)) >> 1;
+ Value |= (op & UINT64_C(384)) >> 4;
+ Value |= (op & UINT64_C(32)) >> 3;
+ break;
+ }
+ case RISCV::C_FSDSP:
+ case RISCV::C_SDSP: {
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(56)) << 7;
+ Value |= (op & UINT64_C(448)) << 1;
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 2;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_FSWSP:
+ case RISCV::C_SWSP: {
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(60)) << 7;
+ Value |= (op & UINT64_C(192)) << 1;
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 2;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_BEQZ:
+ case RISCV::C_BNEZ: {
+ // op: imm
+ op = getImmOpValueAsr1(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(128)) << 5;
+ Value |= (op & UINT64_C(12)) << 8;
+ Value |= (op & UINT64_C(96));
+ Value |= (op & UINT64_C(3)) << 3;
+ Value |= (op & UINT64_C(16)) >> 2;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_SLLI_HINT: {
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(31)) << 2;
+ break;
+ }
+ case RISCV::C_SLLI: {
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(31)) << 2;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_SRAI:
+ case RISCV::C_SRLI: {
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ Value |= (op & UINT64_C(32)) << 7;
+ Value |= (op & UINT64_C(31)) << 2;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_ADDI_HINT_IMM_ZERO:
+ case RISCV::C_ADDI_NOP: {
+ // op: imm
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(32);
+ op <<= 7;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::FSD:
+ case RISCV::FSW:
+ case RISCV::SB:
+ case RISCV::SD:
+ case RISCV::SH:
+ case RISCV::SW: {
+ // op: imm12
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(4064)) << 20;
+ Value |= (op & UINT64_C(31)) << 7;
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ break;
+ }
+ case RISCV::ADDI:
+ case RISCV::ADDIW:
+ case RISCV::ANDI:
+ case RISCV::FLD:
+ case RISCV::FLW:
+ case RISCV::JALR:
+ case RISCV::LB:
+ case RISCV::LBU:
+ case RISCV::LD:
+ case RISCV::LH:
+ case RISCV::LHU:
+ case RISCV::LW:
+ case RISCV::LWU:
+ case RISCV::ORI:
+ case RISCV::SLTI:
+ case RISCV::SLTIU:
+ case RISCV::XORI: {
+ // op: imm12
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ op &= UINT64_C(4095);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::BEQ:
+ case RISCV::BGE:
+ case RISCV::BGEU:
+ case RISCV::BLT:
+ case RISCV::BLTU:
+ case RISCV::BNE: {
+ // op: imm12
+ op = getImmOpValueAsr1(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(2048)) << 20;
+ Value |= (op & UINT64_C(1008)) << 21;
+ Value |= (op & UINT64_C(15)) << 8;
+ Value |= (op & UINT64_C(1024)) >> 3;
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ break;
+ }
+ case RISCV::CSRRC:
+ case RISCV::CSRRCI:
+ case RISCV::CSRRS:
+ case RISCV::CSRRSI:
+ case RISCV::CSRRW:
+ case RISCV::CSRRWI: {
+ // op: imm12
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(4095);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::AUIPC:
+ case RISCV::LUI: {
+ // op: imm20
+ op = getImmOpValue(MI, 1, Fixups, STI);
+ op &= UINT64_C(1048575);
+ op <<= 12;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::JAL: {
+ // op: imm20
+ op = getImmOpValueAsr1(MI, 1, Fixups, STI);
+ Value |= (op & UINT64_C(524288)) << 12;
+ Value |= (op & UINT64_C(1023)) << 21;
+ Value |= (op & UINT64_C(1024)) << 10;
+ Value |= (op & UINT64_C(522240)) << 1;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_J:
+ case RISCV::C_JAL: {
+ // op: offset
+ op = getImmOpValueAsr1(MI, 0, Fixups, STI);
+ Value |= (op & UINT64_C(1024)) << 2;
+ Value |= (op & UINT64_C(8)) << 8;
+ Value |= (op & UINT64_C(384)) << 2;
+ Value |= (op & UINT64_C(512)) >> 1;
+ Value |= (op & UINT64_C(32)) << 2;
+ Value |= (op & UINT64_C(64));
+ Value |= (op & UINT64_C(7)) << 3;
+ Value |= (op & UINT64_C(16)) >> 2;
+ break;
+ }
+ case RISCV::FENCE: {
+ // op: pred
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(15);
+ op <<= 24;
+ Value |= op;
+ // op: succ
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(15);
+ op <<= 20;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_FLD:
+ case RISCV::C_LD: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 2;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(56)) << 7;
+ Value |= (op & UINT64_C(192)) >> 1;
+ break;
+ }
+ case RISCV::C_FLW:
+ case RISCV::C_LW: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 2;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(56)) << 7;
+ Value |= (op & UINT64_C(4)) << 4;
+ Value |= (op & UINT64_C(64)) >> 1;
+ break;
+ }
+ case RISCV::C_SLLI64_HINT: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_SRAI64_HINT:
+ case RISCV::C_SRLI64_HINT: {
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_JALR:
+ case RISCV::C_JR: {
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_MV: {
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 2;
+ Value |= op;
+ break;
+ }
+ case RISCV::FCVT_D_L:
+ case RISCV::FCVT_D_LU:
+ case RISCV::FCVT_LU_D:
+ case RISCV::FCVT_LU_S:
+ case RISCV::FCVT_L_D:
+ case RISCV::FCVT_L_S:
+ case RISCV::FCVT_S_D:
+ case RISCV::FCVT_S_L:
+ case RISCV::FCVT_S_LU:
+ case RISCV::FCVT_S_W:
+ case RISCV::FCVT_S_WU:
+ case RISCV::FCVT_WU_D:
+ case RISCV::FCVT_WU_S:
+ case RISCV::FCVT_W_D:
+ case RISCV::FCVT_W_S:
+ case RISCV::FSQRT_D:
+ case RISCV::FSQRT_S: {
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: funct3
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 12;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::FCLASS_D:
+ case RISCV::FCLASS_S:
+ case RISCV::FCVT_D_S:
+ case RISCV::FCVT_D_W:
+ case RISCV::FCVT_D_WU:
+ case RISCV::FMV_D_X:
+ case RISCV::FMV_W_X:
+ case RISCV::FMV_X_D:
+ case RISCV::FMV_X_W:
+ case RISCV::LR_D:
+ case RISCV::LR_D_AQ:
+ case RISCV::LR_D_AQ_RL:
+ case RISCV::LR_D_RL:
+ case RISCV::LR_W:
+ case RISCV::LR_W_AQ:
+ case RISCV::LR_W_AQ_RL:
+ case RISCV::LR_W_RL: {
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_ADD: {
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 2;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_FSD:
+ case RISCV::C_SD: {
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 2;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(56)) << 7;
+ Value |= (op & UINT64_C(192)) >> 1;
+ break;
+ }
+ case RISCV::C_FSW:
+ case RISCV::C_SW: {
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 2;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ // op: imm
+ op = getImmOpValue(MI, 2, Fixups, STI);
+ Value |= (op & UINT64_C(56)) << 7;
+ Value |= (op & UINT64_C(4)) << 4;
+ Value |= (op & UINT64_C(64)) >> 1;
+ break;
+ }
+ case RISCV::SFENCE_VMA: {
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_MV_HINT: {
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 2;
+ Value |= op;
+ break;
+ }
+ case RISCV::FADD_D:
+ case RISCV::FADD_S:
+ case RISCV::FDIV_D:
+ case RISCV::FDIV_S:
+ case RISCV::FMUL_D:
+ case RISCV::FMUL_S:
+ case RISCV::FSUB_D:
+ case RISCV::FSUB_S: {
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: funct3
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 12;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::ADD:
+ case RISCV::ADDW:
+ case RISCV::AMOADD_D:
+ case RISCV::AMOADD_D_AQ:
+ case RISCV::AMOADD_D_AQ_RL:
+ case RISCV::AMOADD_D_RL:
+ case RISCV::AMOADD_W:
+ case RISCV::AMOADD_W_AQ:
+ case RISCV::AMOADD_W_AQ_RL:
+ case RISCV::AMOADD_W_RL:
+ case RISCV::AMOAND_D:
+ case RISCV::AMOAND_D_AQ:
+ case RISCV::AMOAND_D_AQ_RL:
+ case RISCV::AMOAND_D_RL:
+ case RISCV::AMOAND_W:
+ case RISCV::AMOAND_W_AQ:
+ case RISCV::AMOAND_W_AQ_RL:
+ case RISCV::AMOAND_W_RL:
+ case RISCV::AMOMAXU_D:
+ case RISCV::AMOMAXU_D_AQ:
+ case RISCV::AMOMAXU_D_AQ_RL:
+ case RISCV::AMOMAXU_D_RL:
+ case RISCV::AMOMAXU_W:
+ case RISCV::AMOMAXU_W_AQ:
+ case RISCV::AMOMAXU_W_AQ_RL:
+ case RISCV::AMOMAXU_W_RL:
+ case RISCV::AMOMAX_D:
+ case RISCV::AMOMAX_D_AQ:
+ case RISCV::AMOMAX_D_AQ_RL:
+ case RISCV::AMOMAX_D_RL:
+ case RISCV::AMOMAX_W:
+ case RISCV::AMOMAX_W_AQ:
+ case RISCV::AMOMAX_W_AQ_RL:
+ case RISCV::AMOMAX_W_RL:
+ case RISCV::AMOMINU_D:
+ case RISCV::AMOMINU_D_AQ:
+ case RISCV::AMOMINU_D_AQ_RL:
+ case RISCV::AMOMINU_D_RL:
+ case RISCV::AMOMINU_W:
+ case RISCV::AMOMINU_W_AQ:
+ case RISCV::AMOMINU_W_AQ_RL:
+ case RISCV::AMOMINU_W_RL:
+ case RISCV::AMOMIN_D:
+ case RISCV::AMOMIN_D_AQ:
+ case RISCV::AMOMIN_D_AQ_RL:
+ case RISCV::AMOMIN_D_RL:
+ case RISCV::AMOMIN_W:
+ case RISCV::AMOMIN_W_AQ:
+ case RISCV::AMOMIN_W_AQ_RL:
+ case RISCV::AMOMIN_W_RL:
+ case RISCV::AMOOR_D:
+ case RISCV::AMOOR_D_AQ:
+ case RISCV::AMOOR_D_AQ_RL:
+ case RISCV::AMOOR_D_RL:
+ case RISCV::AMOOR_W:
+ case RISCV::AMOOR_W_AQ:
+ case RISCV::AMOOR_W_AQ_RL:
+ case RISCV::AMOOR_W_RL:
+ case RISCV::AMOSWAP_D:
+ case RISCV::AMOSWAP_D_AQ:
+ case RISCV::AMOSWAP_D_AQ_RL:
+ case RISCV::AMOSWAP_D_RL:
+ case RISCV::AMOSWAP_W:
+ case RISCV::AMOSWAP_W_AQ:
+ case RISCV::AMOSWAP_W_AQ_RL:
+ case RISCV::AMOSWAP_W_RL:
+ case RISCV::AMOXOR_D:
+ case RISCV::AMOXOR_D_AQ:
+ case RISCV::AMOXOR_D_AQ_RL:
+ case RISCV::AMOXOR_D_RL:
+ case RISCV::AMOXOR_W:
+ case RISCV::AMOXOR_W_AQ:
+ case RISCV::AMOXOR_W_AQ_RL:
+ case RISCV::AMOXOR_W_RL:
+ case RISCV::AND:
+ case RISCV::DIV:
+ case RISCV::DIVU:
+ case RISCV::DIVUW:
+ case RISCV::DIVW:
+ case RISCV::FEQ_D:
+ case RISCV::FEQ_S:
+ case RISCV::FLE_D:
+ case RISCV::FLE_S:
+ case RISCV::FLT_D:
+ case RISCV::FLT_S:
+ case RISCV::FMAX_D:
+ case RISCV::FMAX_S:
+ case RISCV::FMIN_D:
+ case RISCV::FMIN_S:
+ case RISCV::FSGNJN_D:
+ case RISCV::FSGNJN_S:
+ case RISCV::FSGNJX_D:
+ case RISCV::FSGNJX_S:
+ case RISCV::FSGNJ_D:
+ case RISCV::FSGNJ_S:
+ case RISCV::MUL:
+ case RISCV::MULH:
+ case RISCV::MULHSU:
+ case RISCV::MULHU:
+ case RISCV::MULW:
+ case RISCV::OR:
+ case RISCV::REM:
+ case RISCV::REMU:
+ case RISCV::REMUW:
+ case RISCV::REMW:
+ case RISCV::SC_D:
+ case RISCV::SC_D_AQ:
+ case RISCV::SC_D_AQ_RL:
+ case RISCV::SC_D_RL:
+ case RISCV::SC_W:
+ case RISCV::SC_W_AQ:
+ case RISCV::SC_W_AQ_RL:
+ case RISCV::SC_W_RL:
+ case RISCV::SLL:
+ case RISCV::SLLW:
+ case RISCV::SLT:
+ case RISCV::SLTU:
+ case RISCV::SRA:
+ case RISCV::SRAW:
+ case RISCV::SRL:
+ case RISCV::SRLW:
+ case RISCV::SUB:
+ case RISCV::SUBW:
+ case RISCV::XOR: {
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_ADD_HINT: {
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 2;
+ Value |= op;
+ break;
+ }
+ case RISCV::C_ADDW:
+ case RISCV::C_AND:
+ case RISCV::C_OR:
+ case RISCV::C_SUB:
+ case RISCV::C_SUBW:
+ case RISCV::C_XOR: {
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 2;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::FMADD_D:
+ case RISCV::FMADD_S:
+ case RISCV::FMSUB_D:
+ case RISCV::FMSUB_S:
+ case RISCV::FNMADD_D:
+ case RISCV::FNMADD_S:
+ case RISCV::FNMSUB_D:
+ case RISCV::FNMSUB_S: {
+ // op: rs3
+ op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 27;
+ Value |= op;
+ // op: rs2
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: funct3
+ op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
+ op &= UINT64_C(7);
+ op <<= 12;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::SLLIW:
+ case RISCV::SRAIW:
+ case RISCV::SRLIW: {
+ // op: shamt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ case RISCV::SLLI:
+ case RISCV::SRAI:
+ case RISCV::SRLI: {
+ // op: shamt
+ op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
+ op &= UINT64_C(63);
+ op <<= 20;
+ Value |= op;
+ // op: rs1
+ op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 15;
+ Value |= op;
+ // op: rd
+ op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
+ op &= UINT64_C(31);
+ op <<= 7;
+ Value |= op;
+ break;
+ }
+ default:
+ std::string msg;
+ raw_string_ostream Msg(msg);
+ Msg << "Not supported instr: " << MI;
+ report_fatal_error(Msg.str());
+ }
+ return Value;
+}
+
+#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
+#undef ENABLE_INSTR_PREDICATE_VERIFIER
+#include <sstream>
+
+// Bits for subtarget features that participate in instruction matching.
+enum SubtargetFeatureBits : uint8_t {
+ Feature_HasStdExtMBit = 5,
+ Feature_HasStdExtABit = 1,
+ Feature_HasStdExtFBit = 4,
+ Feature_HasStdExtDBit = 3,
+ Feature_HasStdExtCBit = 2,
+ Feature_HasRVCHintsBit = 0,
+ Feature_IsRV64Bit = 8,
+ Feature_IsRV32Bit = 6,
+ Feature_IsRV32EBit = 7,
+};
+
+#ifndef NDEBUG
+static const char *SubtargetFeatureNames[] = {
+ "Feature_HasRVCHints",
+ "Feature_HasStdExtA",
+ "Feature_HasStdExtC",
+ "Feature_HasStdExtD",
+ "Feature_HasStdExtF",
+ "Feature_HasStdExtM",
+ "Feature_IsRV32",
+ "Feature_IsRV32E",
+ "Feature_IsRV64",
+ nullptr
+};
+
+#endif // NDEBUG
+FeatureBitset RISCVMCCodeEmitter::
+computeAvailableFeatures(const FeatureBitset& FB) const {
+ FeatureBitset Features;
+ if ((FB[RISCV::FeatureStdExtM]))
+ Features.set(Feature_HasStdExtMBit);
+ if ((FB[RISCV::FeatureStdExtA]))
+ Features.set(Feature_HasStdExtABit);
+ if ((FB[RISCV::FeatureStdExtF]))
+ Features.set(Feature_HasStdExtFBit);
+ if ((FB[RISCV::FeatureStdExtD]))
+ Features.set(Feature_HasStdExtDBit);
+ if ((FB[RISCV::FeatureStdExtC]))
+ Features.set(Feature_HasStdExtCBit);
+ if ((FB[RISCV::FeatureRVCHints]))
+ Features.set(Feature_HasRVCHintsBit);
+ if ((FB[RISCV::Feature64Bit]))
+ Features.set(Feature_IsRV64Bit);
+ if ((!FB[RISCV::Feature64Bit]))
+ Features.set(Feature_IsRV32Bit);
+ if ((FB[RISCV::FeatureRV32E]))
+ Features.set(Feature_IsRV32EBit);
+ return Features;
+}
+
+#ifndef NDEBUG
+// Feature bitsets.
+enum : uint8_t {
+ CEFBS_None,
+ CEFBS_HasStdExtA,
+ CEFBS_HasStdExtC,
+ CEFBS_HasStdExtD,
+ CEFBS_HasStdExtF,
+ CEFBS_HasStdExtM,
+ CEFBS_IsRV32,
+ CEFBS_IsRV64,
+ CEFBS_HasStdExtA_IsRV64,
+ CEFBS_HasStdExtC_HasRVCHints,
+ CEFBS_HasStdExtC_HasStdExtD,
+ CEFBS_HasStdExtC_IsRV32,
+ CEFBS_HasStdExtC_IsRV64,
+ CEFBS_HasStdExtD_IsRV64,
+ CEFBS_HasStdExtF_IsRV64,
+ CEFBS_HasStdExtM_IsRV64,
+ CEFBS_HasStdExtC_HasStdExtF_IsRV32,
+};
+
+static constexpr FeatureBitset FeatureBitsets[] = {
+ {}, // CEFBS_None
+ {Feature_HasStdExtABit, },
+ {Feature_HasStdExtCBit, },
+ {Feature_HasStdExtDBit, },
+ {Feature_HasStdExtFBit, },
+ {Feature_HasStdExtMBit, },
+ {Feature_IsRV32Bit, },
+ {Feature_IsRV64Bit, },
+ {Feature_HasStdExtABit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtCBit, Feature_HasRVCHintsBit, },
+ {Feature_HasStdExtCBit, Feature_HasStdExtDBit, },
+ {Feature_HasStdExtCBit, Feature_IsRV32Bit, },
+ {Feature_HasStdExtCBit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtDBit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtFBit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtMBit, Feature_IsRV64Bit, },
+ {Feature_HasStdExtCBit, Feature_HasStdExtFBit, Feature_IsRV32Bit, },
+};
+#endif // NDEBUG
+
+void RISCVMCCodeEmitter::verifyInstructionPredicates(
+ const MCInst &Inst, const FeatureBitset &AvailableFeatures) const {
+#ifndef NDEBUG
+ static uint8_t RequiredFeaturesRefs[] = {
+ CEFBS_None, // PHI = 0
+ CEFBS_None, // INLINEASM = 1
+ CEFBS_None, // INLINEASM_BR = 2
+ CEFBS_None, // CFI_INSTRUCTION = 3
+ CEFBS_None, // EH_LABEL = 4
+ CEFBS_None, // GC_LABEL = 5
+ CEFBS_None, // ANNOTATION_LABEL = 6
+ CEFBS_None, // KILL = 7
+ CEFBS_None, // EXTRACT_SUBREG = 8
+ CEFBS_None, // INSERT_SUBREG = 9
+ CEFBS_None, // IMPLICIT_DEF = 10
+ CEFBS_None, // SUBREG_TO_REG = 11
+ CEFBS_None, // COPY_TO_REGCLASS = 12
+ CEFBS_None, // DBG_VALUE = 13
+ CEFBS_None, // DBG_LABEL = 14
+ CEFBS_None, // REG_SEQUENCE = 15
+ CEFBS_None, // COPY = 16
+ CEFBS_None, // BUNDLE = 17
+ CEFBS_None, // LIFETIME_START = 18
+ CEFBS_None, // LIFETIME_END = 19
+ CEFBS_None, // STACKMAP = 20
+ CEFBS_None, // FENTRY_CALL = 21
+ CEFBS_None, // PATCHPOINT = 22
+ CEFBS_None, // LOAD_STACK_GUARD = 23
+ CEFBS_None, // STATEPOINT = 24
+ CEFBS_None, // LOCAL_ESCAPE = 25
+ CEFBS_None, // FAULTING_OP = 26
+ CEFBS_None, // PATCHABLE_OP = 27
+ CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 28
+ CEFBS_None, // PATCHABLE_RET = 29
+ CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 30
+ CEFBS_None, // PATCHABLE_TAIL_CALL = 31
+ CEFBS_None, // PATCHABLE_EVENT_CALL = 32
+ CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 33
+ CEFBS_None, // ICALL_BRANCH_FUNNEL = 34
+ CEFBS_None, // G_ADD = 35
+ CEFBS_None, // G_SUB = 36
+ CEFBS_None, // G_MUL = 37
+ CEFBS_None, // G_SDIV = 38
+ CEFBS_None, // G_UDIV = 39
+ CEFBS_None, // G_SREM = 40
+ CEFBS_None, // G_UREM = 41
+ CEFBS_None, // G_AND = 42
+ CEFBS_None, // G_OR = 43
+ CEFBS_None, // G_XOR = 44
+ CEFBS_None, // G_IMPLICIT_DEF = 45
+ CEFBS_None, // G_PHI = 46
+ CEFBS_None, // G_FRAME_INDEX = 47
+ CEFBS_None, // G_GLOBAL_VALUE = 48
+ CEFBS_None, // G_EXTRACT = 49
+ CEFBS_None, // G_UNMERGE_VALUES = 50
+ CEFBS_None, // G_INSERT = 51
+ CEFBS_None, // G_MERGE_VALUES = 52
+ CEFBS_None, // G_BUILD_VECTOR = 53
+ CEFBS_None, // G_BUILD_VECTOR_TRUNC = 54
+ CEFBS_None, // G_CONCAT_VECTORS = 55
+ CEFBS_None, // G_PTRTOINT = 56
+ CEFBS_None, // G_INTTOPTR = 57
+ CEFBS_None, // G_BITCAST = 58
+ CEFBS_None, // G_INTRINSIC_TRUNC = 59
+ CEFBS_None, // G_INTRINSIC_ROUND = 60
+ CEFBS_None, // G_READCYCLECOUNTER = 61
+ CEFBS_None, // G_LOAD = 62
+ CEFBS_None, // G_SEXTLOAD = 63
+ CEFBS_None, // G_ZEXTLOAD = 64
+ CEFBS_None, // G_INDEXED_LOAD = 65
+ CEFBS_None, // G_INDEXED_SEXTLOAD = 66
+ CEFBS_None, // G_INDEXED_ZEXTLOAD = 67
+ CEFBS_None, // G_STORE = 68
+ CEFBS_None, // G_INDEXED_STORE = 69
+ CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70
+ CEFBS_None, // G_ATOMIC_CMPXCHG = 71
+ CEFBS_None, // G_ATOMICRMW_XCHG = 72
+ CEFBS_None, // G_ATOMICRMW_ADD = 73
+ CEFBS_None, // G_ATOMICRMW_SUB = 74
+ CEFBS_None, // G_ATOMICRMW_AND = 75
+ CEFBS_None, // G_ATOMICRMW_NAND = 76
+ CEFBS_None, // G_ATOMICRMW_OR = 77
+ CEFBS_None, // G_ATOMICRMW_XOR = 78
+ CEFBS_None, // G_ATOMICRMW_MAX = 79
+ CEFBS_None, // G_ATOMICRMW_MIN = 80
+ CEFBS_None, // G_ATOMICRMW_UMAX = 81
+ CEFBS_None, // G_ATOMICRMW_UMIN = 82
+ CEFBS_None, // G_ATOMICRMW_FADD = 83
+ CEFBS_None, // G_ATOMICRMW_FSUB = 84
+ CEFBS_None, // G_FENCE = 85
+ CEFBS_None, // G_BRCOND = 86
+ CEFBS_None, // G_BRINDIRECT = 87
+ CEFBS_None, // G_INTRINSIC = 88
+ CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 89
+ CEFBS_None, // G_ANYEXT = 90
+ CEFBS_None, // G_TRUNC = 91
+ CEFBS_None, // G_CONSTANT = 92
+ CEFBS_None, // G_FCONSTANT = 93
+ CEFBS_None, // G_VASTART = 94
+ CEFBS_None, // G_VAARG = 95
+ CEFBS_None, // G_SEXT = 96
+ CEFBS_None, // G_SEXT_INREG = 97
+ CEFBS_None, // G_ZEXT = 98
+ CEFBS_None, // G_SHL = 99
+ CEFBS_None, // G_LSHR = 100
+ CEFBS_None, // G_ASHR = 101
+ CEFBS_None, // G_ICMP = 102
+ CEFBS_None, // G_FCMP = 103
+ CEFBS_None, // G_SELECT = 104
+ CEFBS_None, // G_UADDO = 105
+ CEFBS_None, // G_UADDE = 106
+ CEFBS_None, // G_USUBO = 107
+ CEFBS_None, // G_USUBE = 108
+ CEFBS_None, // G_SADDO = 109
+ CEFBS_None, // G_SADDE = 110
+ CEFBS_None, // G_SSUBO = 111
+ CEFBS_None, // G_SSUBE = 112
+ CEFBS_None, // G_UMULO = 113
+ CEFBS_None, // G_SMULO = 114
+ CEFBS_None, // G_UMULH = 115
+ CEFBS_None, // G_SMULH = 116
+ CEFBS_None, // G_FADD = 117
+ CEFBS_None, // G_FSUB = 118
+ CEFBS_None, // G_FMUL = 119
+ CEFBS_None, // G_FMA = 120
+ CEFBS_None, // G_FMAD = 121
+ CEFBS_None, // G_FDIV = 122
+ CEFBS_None, // G_FREM = 123
+ CEFBS_None, // G_FPOW = 124
+ CEFBS_None, // G_FEXP = 125
+ CEFBS_None, // G_FEXP2 = 126
+ CEFBS_None, // G_FLOG = 127
+ CEFBS_None, // G_FLOG2 = 128
+ CEFBS_None, // G_FLOG10 = 129
+ CEFBS_None, // G_FNEG = 130
+ CEFBS_None, // G_FPEXT = 131
+ CEFBS_None, // G_FPTRUNC = 132
+ CEFBS_None, // G_FPTOSI = 133
+ CEFBS_None, // G_FPTOUI = 134
+ CEFBS_None, // G_SITOFP = 135
+ CEFBS_None, // G_UITOFP = 136
+ CEFBS_None, // G_FABS = 137
+ CEFBS_None, // G_FCOPYSIGN = 138
+ CEFBS_None, // G_FCANONICALIZE = 139
+ CEFBS_None, // G_FMINNUM = 140
+ CEFBS_None, // G_FMAXNUM = 141
+ CEFBS_None, // G_FMINNUM_IEEE = 142
+ CEFBS_None, // G_FMAXNUM_IEEE = 143
+ CEFBS_None, // G_FMINIMUM = 144
+ CEFBS_None, // G_FMAXIMUM = 145
+ CEFBS_None, // G_PTR_ADD = 146
+ CEFBS_None, // G_PTR_MASK = 147
+ CEFBS_None, // G_SMIN = 148
+ CEFBS_None, // G_SMAX = 149
+ CEFBS_None, // G_UMIN = 150
+ CEFBS_None, // G_UMAX = 151
+ CEFBS_None, // G_BR = 152
+ CEFBS_None, // G_BRJT = 153
+ CEFBS_None, // G_INSERT_VECTOR_ELT = 154
+ CEFBS_None, // G_EXTRACT_VECTOR_ELT = 155
+ CEFBS_None, // G_SHUFFLE_VECTOR = 156
+ CEFBS_None, // G_CTTZ = 157
+ CEFBS_None, // G_CTTZ_ZERO_UNDEF = 158
+ CEFBS_None, // G_CTLZ = 159
+ CEFBS_None, // G_CTLZ_ZERO_UNDEF = 160
+ CEFBS_None, // G_CTPOP = 161
+ CEFBS_None, // G_BSWAP = 162
+ CEFBS_None, // G_BITREVERSE = 163
+ CEFBS_None, // G_FCEIL = 164
+ CEFBS_None, // G_FCOS = 165
+ CEFBS_None, // G_FSIN = 166
+ CEFBS_None, // G_FSQRT = 167
+ CEFBS_None, // G_FFLOOR = 168
+ CEFBS_None, // G_FRINT = 169
+ CEFBS_None, // G_FNEARBYINT = 170
+ CEFBS_None, // G_ADDRSPACE_CAST = 171
+ CEFBS_None, // G_BLOCK_ADDR = 172
+ CEFBS_None, // G_JUMP_TABLE = 173
+ CEFBS_None, // G_DYN_STACKALLOC = 174
+ CEFBS_None, // G_READ_REGISTER = 175
+ CEFBS_None, // G_WRITE_REGISTER = 176
+ CEFBS_None, // ADJCALLSTACKDOWN = 177
+ CEFBS_None, // ADJCALLSTACKUP = 178
+ CEFBS_HasStdExtD, // BuildPairF64Pseudo = 179
+ CEFBS_None, // PseudoAddTPRel = 180
+ CEFBS_HasStdExtA, // PseudoAtomicLoadNand32 = 181
+ CEFBS_HasStdExtA_IsRV64, // PseudoAtomicLoadNand64 = 182
+ CEFBS_None, // PseudoBR = 183
+ CEFBS_None, // PseudoBRIND = 184
+ CEFBS_None, // PseudoCALL = 185
+ CEFBS_None, // PseudoCALLIndirect = 186
+ CEFBS_None, // PseudoCALLReg = 187
+ CEFBS_HasStdExtA, // PseudoCmpXchg32 = 188
+ CEFBS_HasStdExtA_IsRV64, // PseudoCmpXchg64 = 189
+ CEFBS_HasStdExtD, // PseudoFLD = 190
+ CEFBS_HasStdExtF, // PseudoFLW = 191
+ CEFBS_HasStdExtD, // PseudoFSD = 192
+ CEFBS_HasStdExtF, // PseudoFSW = 193
+ CEFBS_None, // PseudoLA = 194
+ CEFBS_None, // PseudoLA_TLS_GD = 195
+ CEFBS_None, // PseudoLA_TLS_IE = 196
+ CEFBS_None, // PseudoLB = 197
+ CEFBS_None, // PseudoLBU = 198
+ CEFBS_IsRV64, // PseudoLD = 199
+ CEFBS_None, // PseudoLH = 200
+ CEFBS_None, // PseudoLHU = 201
+ CEFBS_None, // PseudoLI = 202
+ CEFBS_None, // PseudoLLA = 203
+ CEFBS_None, // PseudoLW = 204
+ CEFBS_IsRV64, // PseudoLWU = 205
+ CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadAdd32 = 206
+ CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadMax32 = 207
+ CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadMin32 = 208
+ CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadNand32 = 209
+ CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadSub32 = 210
+ CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadUMax32 = 211
+ CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadUMin32 = 212
+ CEFBS_HasStdExtA, // PseudoMaskedAtomicSwap32 = 213
+ CEFBS_HasStdExtA, // PseudoMaskedCmpXchg32 = 214
+ CEFBS_None, // PseudoRET = 215
+ CEFBS_None, // PseudoSB = 216
+ CEFBS_IsRV64, // PseudoSD = 217
+ CEFBS_None, // PseudoSH = 218
+ CEFBS_None, // PseudoSW = 219
+ CEFBS_None, // PseudoTAIL = 220
+ CEFBS_None, // PseudoTAILIndirect = 221
+ CEFBS_IsRV32, // ReadCycleWide = 222
+ CEFBS_HasStdExtF, // Select_FPR32_Using_CC_GPR = 223
+ CEFBS_HasStdExtD, // Select_FPR64_Using_CC_GPR = 224
+ CEFBS_None, // Select_GPR_Using_CC_GPR = 225
+ CEFBS_HasStdExtD, // SplitF64Pseudo = 226
+ CEFBS_None, // ADD = 227
+ CEFBS_None, // ADDI = 228
+ CEFBS_IsRV64, // ADDIW = 229
+ CEFBS_IsRV64, // ADDW = 230
+ CEFBS_HasStdExtA_IsRV64, // AMOADD_D = 231
+ CEFBS_HasStdExtA_IsRV64, // AMOADD_D_AQ = 232
+ CEFBS_HasStdExtA_IsRV64, // AMOADD_D_AQ_RL = 233
+ CEFBS_HasStdExtA_IsRV64, // AMOADD_D_RL = 234
+ CEFBS_HasStdExtA, // AMOADD_W = 235
+ CEFBS_HasStdExtA, // AMOADD_W_AQ = 236
+ CEFBS_HasStdExtA, // AMOADD_W_AQ_RL = 237
+ CEFBS_HasStdExtA, // AMOADD_W_RL = 238
+ CEFBS_HasStdExtA_IsRV64, // AMOAND_D = 239
+ CEFBS_HasStdExtA_IsRV64, // AMOAND_D_AQ = 240
+ CEFBS_HasStdExtA_IsRV64, // AMOAND_D_AQ_RL = 241
+ CEFBS_HasStdExtA_IsRV64, // AMOAND_D_RL = 242
+ CEFBS_HasStdExtA, // AMOAND_W = 243
+ CEFBS_HasStdExtA, // AMOAND_W_AQ = 244
+ CEFBS_HasStdExtA, // AMOAND_W_AQ_RL = 245
+ CEFBS_HasStdExtA, // AMOAND_W_RL = 246
+ CEFBS_HasStdExtA_IsRV64, // AMOMAXU_D = 247
+ CEFBS_HasStdExtA_IsRV64, // AMOMAXU_D_AQ = 248
+ CEFBS_HasStdExtA_IsRV64, // AMOMAXU_D_AQ_RL = 249
+ CEFBS_HasStdExtA_IsRV64, // AMOMAXU_D_RL = 250
+ CEFBS_HasStdExtA, // AMOMAXU_W = 251
+ CEFBS_HasStdExtA, // AMOMAXU_W_AQ = 252
+ CEFBS_HasStdExtA, // AMOMAXU_W_AQ_RL = 253
+ CEFBS_HasStdExtA, // AMOMAXU_W_RL = 254
+ CEFBS_HasStdExtA_IsRV64, // AMOMAX_D = 255
+ CEFBS_HasStdExtA_IsRV64, // AMOMAX_D_AQ = 256
+ CEFBS_HasStdExtA_IsRV64, // AMOMAX_D_AQ_RL = 257
+ CEFBS_HasStdExtA_IsRV64, // AMOMAX_D_RL = 258
+ CEFBS_HasStdExtA, // AMOMAX_W = 259
+ CEFBS_HasStdExtA, // AMOMAX_W_AQ = 260
+ CEFBS_HasStdExtA, // AMOMAX_W_AQ_RL = 261
+ CEFBS_HasStdExtA, // AMOMAX_W_RL = 262
+ CEFBS_HasStdExtA_IsRV64, // AMOMINU_D = 263
+ CEFBS_HasStdExtA_IsRV64, // AMOMINU_D_AQ = 264
+ CEFBS_HasStdExtA_IsRV64, // AMOMINU_D_AQ_RL = 265
+ CEFBS_HasStdExtA_IsRV64, // AMOMINU_D_RL = 266
+ CEFBS_HasStdExtA, // AMOMINU_W = 267
+ CEFBS_HasStdExtA, // AMOMINU_W_AQ = 268
+ CEFBS_HasStdExtA, // AMOMINU_W_AQ_RL = 269
+ CEFBS_HasStdExtA, // AMOMINU_W_RL = 270
+ CEFBS_HasStdExtA_IsRV64, // AMOMIN_D = 271
+ CEFBS_HasStdExtA_IsRV64, // AMOMIN_D_AQ = 272
+ CEFBS_HasStdExtA_IsRV64, // AMOMIN_D_AQ_RL = 273
+ CEFBS_HasStdExtA_IsRV64, // AMOMIN_D_RL = 274
+ CEFBS_HasStdExtA, // AMOMIN_W = 275
+ CEFBS_HasStdExtA, // AMOMIN_W_AQ = 276
+ CEFBS_HasStdExtA, // AMOMIN_W_AQ_RL = 277
+ CEFBS_HasStdExtA, // AMOMIN_W_RL = 278
+ CEFBS_HasStdExtA_IsRV64, // AMOOR_D = 279
+ CEFBS_HasStdExtA_IsRV64, // AMOOR_D_AQ = 280
+ CEFBS_HasStdExtA_IsRV64, // AMOOR_D_AQ_RL = 281
+ CEFBS_HasStdExtA_IsRV64, // AMOOR_D_RL = 282
+ CEFBS_HasStdExtA, // AMOOR_W = 283
+ CEFBS_HasStdExtA, // AMOOR_W_AQ = 284
+ CEFBS_HasStdExtA, // AMOOR_W_AQ_RL = 285
+ CEFBS_HasStdExtA, // AMOOR_W_RL = 286
+ CEFBS_HasStdExtA_IsRV64, // AMOSWAP_D = 287
+ CEFBS_HasStdExtA_IsRV64, // AMOSWAP_D_AQ = 288
+ CEFBS_HasStdExtA_IsRV64, // AMOSWAP_D_AQ_RL = 289
+ CEFBS_HasStdExtA_IsRV64, // AMOSWAP_D_RL = 290
+ CEFBS_HasStdExtA, // AMOSWAP_W = 291
+ CEFBS_HasStdExtA, // AMOSWAP_W_AQ = 292
+ CEFBS_HasStdExtA, // AMOSWAP_W_AQ_RL = 293
+ CEFBS_HasStdExtA, // AMOSWAP_W_RL = 294
+ CEFBS_HasStdExtA_IsRV64, // AMOXOR_D = 295
+ CEFBS_HasStdExtA_IsRV64, // AMOXOR_D_AQ = 296
+ CEFBS_HasStdExtA_IsRV64, // AMOXOR_D_AQ_RL = 297
+ CEFBS_HasStdExtA_IsRV64, // AMOXOR_D_RL = 298
+ CEFBS_HasStdExtA, // AMOXOR_W = 299
+ CEFBS_HasStdExtA, // AMOXOR_W_AQ = 300
+ CEFBS_HasStdExtA, // AMOXOR_W_AQ_RL = 301
+ CEFBS_HasStdExtA, // AMOXOR_W_RL = 302
+ CEFBS_None, // AND = 303
+ CEFBS_None, // ANDI = 304
+ CEFBS_None, // AUIPC = 305
+ CEFBS_None, // BEQ = 306
+ CEFBS_None, // BGE = 307
+ CEFBS_None, // BGEU = 308
+ CEFBS_None, // BLT = 309
+ CEFBS_None, // BLTU = 310
+ CEFBS_None, // BNE = 311
+ CEFBS_None, // CSRRC = 312
+ CEFBS_None, // CSRRCI = 313
+ CEFBS_None, // CSRRS = 314
+ CEFBS_None, // CSRRSI = 315
+ CEFBS_None, // CSRRW = 316
+ CEFBS_None, // CSRRWI = 317
+ CEFBS_HasStdExtC, // C_ADD = 318
+ CEFBS_HasStdExtC, // C_ADDI = 319
+ CEFBS_HasStdExtC, // C_ADDI16SP = 320
+ CEFBS_HasStdExtC, // C_ADDI4SPN = 321
+ CEFBS_HasStdExtC_IsRV64, // C_ADDIW = 322
+ CEFBS_HasStdExtC_HasRVCHints, // C_ADDI_HINT_IMM_ZERO = 323
+ CEFBS_HasStdExtC_HasRVCHints, // C_ADDI_HINT_X0 = 324
+ CEFBS_HasStdExtC, // C_ADDI_NOP = 325
+ CEFBS_HasStdExtC_IsRV64, // C_ADDW = 326
+ CEFBS_HasStdExtC_HasRVCHints, // C_ADD_HINT = 327
+ CEFBS_HasStdExtC, // C_AND = 328
+ CEFBS_HasStdExtC, // C_ANDI = 329
+ CEFBS_HasStdExtC, // C_BEQZ = 330
+ CEFBS_HasStdExtC, // C_BNEZ = 331
+ CEFBS_HasStdExtC, // C_EBREAK = 332
+ CEFBS_HasStdExtC_HasStdExtD, // C_FLD = 333
+ CEFBS_HasStdExtC_HasStdExtD, // C_FLDSP = 334
+ CEFBS_HasStdExtC_HasStdExtF_IsRV32, // C_FLW = 335
+ CEFBS_HasStdExtC_HasStdExtF_IsRV32, // C_FLWSP = 336
+ CEFBS_HasStdExtC_HasStdExtD, // C_FSD = 337
+ CEFBS_HasStdExtC_HasStdExtD, // C_FSDSP = 338
+ CEFBS_HasStdExtC_HasStdExtF_IsRV32, // C_FSW = 339
+ CEFBS_HasStdExtC_HasStdExtF_IsRV32, // C_FSWSP = 340
+ CEFBS_HasStdExtC, // C_J = 341
+ CEFBS_HasStdExtC_IsRV32, // C_JAL = 342
+ CEFBS_HasStdExtC, // C_JALR = 343
+ CEFBS_HasStdExtC, // C_JR = 344
+ CEFBS_HasStdExtC_IsRV64, // C_LD = 345
+ CEFBS_HasStdExtC_IsRV64, // C_LDSP = 346
+ CEFBS_HasStdExtC, // C_LI = 347
+ CEFBS_HasStdExtC_HasRVCHints, // C_LI_HINT = 348
+ CEFBS_HasStdExtC, // C_LUI = 349
+ CEFBS_HasStdExtC_HasRVCHints, // C_LUI_HINT = 350
+ CEFBS_HasStdExtC, // C_LW = 351
+ CEFBS_HasStdExtC, // C_LWSP = 352
+ CEFBS_HasStdExtC, // C_MV = 353
+ CEFBS_HasStdExtC_HasRVCHints, // C_MV_HINT = 354
+ CEFBS_HasStdExtC, // C_NOP = 355
+ CEFBS_HasStdExtC_HasRVCHints, // C_NOP_HINT = 356
+ CEFBS_HasStdExtC, // C_OR = 357
+ CEFBS_HasStdExtC_IsRV64, // C_SD = 358
+ CEFBS_HasStdExtC_IsRV64, // C_SDSP = 359
+ CEFBS_HasStdExtC, // C_SLLI = 360
+ CEFBS_HasStdExtC_HasRVCHints, // C_SLLI64_HINT = 361
+ CEFBS_HasStdExtC_HasRVCHints, // C_SLLI_HINT = 362
+ CEFBS_HasStdExtC, // C_SRAI = 363
+ CEFBS_HasStdExtC_HasRVCHints, // C_SRAI64_HINT = 364
+ CEFBS_HasStdExtC, // C_SRLI = 365
+ CEFBS_HasStdExtC_HasRVCHints, // C_SRLI64_HINT = 366
+ CEFBS_HasStdExtC, // C_SUB = 367
+ CEFBS_HasStdExtC_IsRV64, // C_SUBW = 368
+ CEFBS_HasStdExtC, // C_SW = 369
+ CEFBS_HasStdExtC, // C_SWSP = 370
+ CEFBS_HasStdExtC, // C_UNIMP = 371
+ CEFBS_HasStdExtC, // C_XOR = 372
+ CEFBS_HasStdExtM, // DIV = 373
+ CEFBS_HasStdExtM, // DIVU = 374
+ CEFBS_HasStdExtM_IsRV64, // DIVUW = 375
+ CEFBS_HasStdExtM_IsRV64, // DIVW = 376
+ CEFBS_None, // EBREAK = 377
+ CEFBS_None, // ECALL = 378
+ CEFBS_HasStdExtD, // FADD_D = 379
+ CEFBS_HasStdExtF, // FADD_S = 380
+ CEFBS_HasStdExtD, // FCLASS_D = 381
+ CEFBS_HasStdExtF, // FCLASS_S = 382
+ CEFBS_HasStdExtD_IsRV64, // FCVT_D_L = 383
+ CEFBS_HasStdExtD_IsRV64, // FCVT_D_LU = 384
+ CEFBS_HasStdExtD, // FCVT_D_S = 385
+ CEFBS_HasStdExtD, // FCVT_D_W = 386
+ CEFBS_HasStdExtD, // FCVT_D_WU = 387
+ CEFBS_HasStdExtD_IsRV64, // FCVT_LU_D = 388
+ CEFBS_HasStdExtF_IsRV64, // FCVT_LU_S = 389
+ CEFBS_HasStdExtD_IsRV64, // FCVT_L_D = 390
+ CEFBS_HasStdExtF_IsRV64, // FCVT_L_S = 391
+ CEFBS_HasStdExtD, // FCVT_S_D = 392
+ CEFBS_HasStdExtF_IsRV64, // FCVT_S_L = 393
+ CEFBS_HasStdExtF_IsRV64, // FCVT_S_LU = 394
+ CEFBS_HasStdExtF, // FCVT_S_W = 395
+ CEFBS_HasStdExtF, // FCVT_S_WU = 396
+ CEFBS_HasStdExtD, // FCVT_WU_D = 397
+ CEFBS_HasStdExtF, // FCVT_WU_S = 398
+ CEFBS_HasStdExtD, // FCVT_W_D = 399
+ CEFBS_HasStdExtF, // FCVT_W_S = 400
+ CEFBS_HasStdExtD, // FDIV_D = 401
+ CEFBS_HasStdExtF, // FDIV_S = 402
+ CEFBS_None, // FENCE = 403
+ CEFBS_None, // FENCE_I = 404
+ CEFBS_None, // FENCE_TSO = 405
+ CEFBS_HasStdExtD, // FEQ_D = 406
+ CEFBS_HasStdExtF, // FEQ_S = 407
+ CEFBS_HasStdExtD, // FLD = 408
+ CEFBS_HasStdExtD, // FLE_D = 409
+ CEFBS_HasStdExtF, // FLE_S = 410
+ CEFBS_HasStdExtD, // FLT_D = 411
+ CEFBS_HasStdExtF, // FLT_S = 412
+ CEFBS_HasStdExtF, // FLW = 413
+ CEFBS_HasStdExtD, // FMADD_D = 414
+ CEFBS_HasStdExtF, // FMADD_S = 415
+ CEFBS_HasStdExtD, // FMAX_D = 416
+ CEFBS_HasStdExtF, // FMAX_S = 417
+ CEFBS_HasStdExtD, // FMIN_D = 418
+ CEFBS_HasStdExtF, // FMIN_S = 419
+ CEFBS_HasStdExtD, // FMSUB_D = 420
+ CEFBS_HasStdExtF, // FMSUB_S = 421
+ CEFBS_HasStdExtD, // FMUL_D = 422
+ CEFBS_HasStdExtF, // FMUL_S = 423
+ CEFBS_HasStdExtD_IsRV64, // FMV_D_X = 424
+ CEFBS_HasStdExtF, // FMV_W_X = 425
+ CEFBS_HasStdExtD_IsRV64, // FMV_X_D = 426
+ CEFBS_HasStdExtF, // FMV_X_W = 427
+ CEFBS_HasStdExtD, // FNMADD_D = 428
+ CEFBS_HasStdExtF, // FNMADD_S = 429
+ CEFBS_HasStdExtD, // FNMSUB_D = 430
+ CEFBS_HasStdExtF, // FNMSUB_S = 431
+ CEFBS_HasStdExtD, // FSD = 432
+ CEFBS_HasStdExtD, // FSGNJN_D = 433
+ CEFBS_HasStdExtF, // FSGNJN_S = 434
+ CEFBS_HasStdExtD, // FSGNJX_D = 435
+ CEFBS_HasStdExtF, // FSGNJX_S = 436
+ CEFBS_HasStdExtD, // FSGNJ_D = 437
+ CEFBS_HasStdExtF, // FSGNJ_S = 438
+ CEFBS_HasStdExtD, // FSQRT_D = 439
+ CEFBS_HasStdExtF, // FSQRT_S = 440
+ CEFBS_HasStdExtD, // FSUB_D = 441
+ CEFBS_HasStdExtF, // FSUB_S = 442
+ CEFBS_HasStdExtF, // FSW = 443
+ CEFBS_None, // JAL = 444
+ CEFBS_None, // JALR = 445
+ CEFBS_None, // LB = 446
+ CEFBS_None, // LBU = 447
+ CEFBS_IsRV64, // LD = 448
+ CEFBS_None, // LH = 449
+ CEFBS_None, // LHU = 450
+ CEFBS_HasStdExtA_IsRV64, // LR_D = 451
+ CEFBS_HasStdExtA_IsRV64, // LR_D_AQ = 452
+ CEFBS_HasStdExtA_IsRV64, // LR_D_AQ_RL = 453
+ CEFBS_HasStdExtA_IsRV64, // LR_D_RL = 454
+ CEFBS_HasStdExtA, // LR_W = 455
+ CEFBS_HasStdExtA, // LR_W_AQ = 456
+ CEFBS_HasStdExtA, // LR_W_AQ_RL = 457
+ CEFBS_HasStdExtA, // LR_W_RL = 458
+ CEFBS_None, // LUI = 459
+ CEFBS_None, // LW = 460
+ CEFBS_IsRV64, // LWU = 461
+ CEFBS_None, // MRET = 462
+ CEFBS_HasStdExtM, // MUL = 463
+ CEFBS_HasStdExtM, // MULH = 464
+ CEFBS_HasStdExtM, // MULHSU = 465
+ CEFBS_HasStdExtM, // MULHU = 466
+ CEFBS_HasStdExtM_IsRV64, // MULW = 467
+ CEFBS_None, // OR = 468
+ CEFBS_None, // ORI = 469
+ CEFBS_HasStdExtM, // REM = 470
+ CEFBS_HasStdExtM, // REMU = 471
+ CEFBS_HasStdExtM_IsRV64, // REMUW = 472
+ CEFBS_HasStdExtM_IsRV64, // REMW = 473
+ CEFBS_None, // SB = 474
+ CEFBS_HasStdExtA_IsRV64, // SC_D = 475
+ CEFBS_HasStdExtA_IsRV64, // SC_D_AQ = 476
+ CEFBS_HasStdExtA_IsRV64, // SC_D_AQ_RL = 477
+ CEFBS_HasStdExtA_IsRV64, // SC_D_RL = 478
+ CEFBS_HasStdExtA, // SC_W = 479
+ CEFBS_HasStdExtA, // SC_W_AQ = 480
+ CEFBS_HasStdExtA, // SC_W_AQ_RL = 481
+ CEFBS_HasStdExtA, // SC_W_RL = 482
+ CEFBS_IsRV64, // SD = 483
+ CEFBS_None, // SFENCE_VMA = 484
+ CEFBS_None, // SH = 485
+ CEFBS_None, // SLL = 486
+ CEFBS_None, // SLLI = 487
+ CEFBS_IsRV64, // SLLIW = 488
+ CEFBS_IsRV64, // SLLW = 489
+ CEFBS_None, // SLT = 490
+ CEFBS_None, // SLTI = 491
+ CEFBS_None, // SLTIU = 492
+ CEFBS_None, // SLTU = 493
+ CEFBS_None, // SRA = 494
+ CEFBS_None, // SRAI = 495
+ CEFBS_IsRV64, // SRAIW = 496
+ CEFBS_IsRV64, // SRAW = 497
+ CEFBS_None, // SRET = 498
+ CEFBS_None, // SRL = 499
+ CEFBS_None, // SRLI = 500
+ CEFBS_IsRV64, // SRLIW = 501
+ CEFBS_IsRV64, // SRLW = 502
+ CEFBS_None, // SUB = 503
+ CEFBS_IsRV64, // SUBW = 504
+ CEFBS_None, // SW = 505
+ CEFBS_None, // UNIMP = 506
+ CEFBS_None, // URET = 507
+ CEFBS_None, // WFI = 508
+ CEFBS_None, // XOR = 509
+ CEFBS_None, // XORI = 510
+ };
+
+ assert(Inst.getOpcode() < 511);
+ const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
+ FeatureBitset MissingFeatures =
+ (AvailableFeatures & RequiredFeatures) ^
+ RequiredFeatures;
+ if (MissingFeatures.any()) {
+ std::ostringstream Msg;
+ Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
+ << " instruction but the ";
+ for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
+ if (MissingFeatures.test(i))
+ Msg << SubtargetFeatureNames[i] << " ";
+ Msg << "predicate(s) are not met";
+ report_fatal_error(Msg.str());
+ }
+#else
+// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF).
+(void)MCII;
+#endif // NDEBUG
+}
+#endif
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenMCPseudoLowering.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenMCPseudoLowering.inc
new file mode 100644
index 0000000..d98f46f
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenMCPseudoLowering.inc
@@ -0,0 +1,85 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Pseudo-instruction MC lowering Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+bool RISCVAsmPrinter::
+emitPseudoExpansionLowering(MCStreamer &OutStreamer,
+ const MachineInstr *MI) {
+ switch (MI->getOpcode()) {
+ default: return false;
+ case RISCV::PseudoBR: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(RISCV::JAL);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: imm20
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case RISCV::PseudoBRIND: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(RISCV::JALR);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: rs1
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: imm12
+ lowerOperand(MI->getOperand(1), MCOp);
+ TmpInst.addOperand(MCOp);
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case RISCV::PseudoCALLIndirect: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(RISCV::JALR);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(RISCV::X1));
+ // Operand: rs1
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: imm12
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case RISCV::PseudoRET: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(RISCV::JALR);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: rs1
+ TmpInst.addOperand(MCOperand::createReg(RISCV::X1));
+ // Operand: imm12
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ case RISCV::PseudoTAILIndirect: {
+ MCInst TmpInst;
+ MCOperand MCOp;
+ TmpInst.setOpcode(RISCV::JALR);
+ // Operand: rd
+ TmpInst.addOperand(MCOperand::createReg(RISCV::X0));
+ // Operand: rs1
+ lowerOperand(MI->getOperand(0), MCOp);
+ TmpInst.addOperand(MCOp);
+ // Operand: imm12
+ TmpInst.addOperand(MCOperand::createImm(0));
+ EmitToStreamer(OutStreamer, TmpInst);
+ break;
+ }
+ }
+ return true;
+}
+
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenRegisterBank.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenRegisterBank.inc
new file mode 100644
index 0000000..3c9c6e7
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenRegisterBank.inc
@@ -0,0 +1,65 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Register Bank Source Fragments *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+#ifdef GET_REGBANK_DECLARATIONS
+#undef GET_REGBANK_DECLARATIONS
+namespace llvm {
+namespace RISCV {
+enum {
+ GPRRegBankID,
+ NumRegisterBanks,
+};
+} // end namespace RISCV
+} // end namespace llvm
+#endif // GET_REGBANK_DECLARATIONS
+
+#ifdef GET_TARGET_REGBANK_CLASS
+#undef GET_TARGET_REGBANK_CLASS
+private:
+ static RegisterBank *RegBanks[];
+
+protected:
+ RISCVGenRegisterBankInfo();
+
+#endif // GET_TARGET_REGBANK_CLASS
+
+#ifdef GET_TARGET_REGBANK_IMPL
+#undef GET_TARGET_REGBANK_IMPL
+namespace llvm {
+namespace RISCV {
+const uint32_t GPRRegBankCoverageData[] = {
+ // 0-31
+ (1u << (RISCV::GPRRegClassID - 0)) |
+ (1u << (RISCV::GPRNoX0RegClassID - 0)) |
+ (1u << (RISCV::GPRNoX0X2RegClassID - 0)) |
+ (1u << (RISCV::GPRTCRegClassID - 0)) |
+ (1u << (RISCV::GPRC_and_GPRTCRegClassID - 0)) |
+ (1u << (RISCV::GPRCRegClassID - 0)) |
+ (1u << (RISCV::SPRegClassID - 0)) |
+ (1u << (RISCV::GPRX0RegClassID - 0)) |
+ 0,
+};
+
+RegisterBank GPRRegBank(/* ID */ RISCV::GPRRegBankID, /* Name */ "GPRB", /* Size */ 32, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 12);
+} // end namespace RISCV
+
+RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = {
+ &RISCV::GPRRegBank,
+};
+
+RISCVGenRegisterBankInfo::RISCVGenRegisterBankInfo()
+ : RegisterBankInfo(RegBanks, RISCV::NumRegisterBanks) {
+ // Assert that RegBank indices match their ID's
+#ifndef NDEBUG
+ unsigned Index = 0;
+ for (const auto &RB : RegBanks)
+ assert(Index++ == RB->getID() && "Index != ID");
+#endif // NDEBUG
+}
+} // end namespace llvm
+#endif // GET_TARGET_REGBANK_IMPL
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenRegisterInfo.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenRegisterInfo.inc
new file mode 100644
index 0000000..fcaefb1
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenRegisterInfo.inc
@@ -0,0 +1,1911 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Register Enum Values *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_ENUM
+#undef GET_REGINFO_ENUM
+
+namespace llvm {
+
+class MCRegisterClass;
+extern const MCRegisterClass RISCVMCRegisterClasses[];
+
+namespace RISCV {
+enum {
+ NoRegister,
+ X0 = 1,
+ X1 = 2,
+ X2 = 3,
+ X3 = 4,
+ X4 = 5,
+ X5 = 6,
+ X6 = 7,
+ X7 = 8,
+ X8 = 9,
+ X9 = 10,
+ X10 = 11,
+ X11 = 12,
+ X12 = 13,
+ X13 = 14,
+ X14 = 15,
+ X15 = 16,
+ X16 = 17,
+ X17 = 18,
+ X18 = 19,
+ X19 = 20,
+ X20 = 21,
+ X21 = 22,
+ X22 = 23,
+ X23 = 24,
+ X24 = 25,
+ X25 = 26,
+ X26 = 27,
+ X27 = 28,
+ X28 = 29,
+ X29 = 30,
+ X30 = 31,
+ X31 = 32,
+ F0_D = 33,
+ F1_D = 34,
+ F2_D = 35,
+ F3_D = 36,
+ F4_D = 37,
+ F5_D = 38,
+ F6_D = 39,
+ F7_D = 40,
+ F8_D = 41,
+ F9_D = 42,
+ F10_D = 43,
+ F11_D = 44,
+ F12_D = 45,
+ F13_D = 46,
+ F14_D = 47,
+ F15_D = 48,
+ F16_D = 49,
+ F17_D = 50,
+ F18_D = 51,
+ F19_D = 52,
+ F20_D = 53,
+ F21_D = 54,
+ F22_D = 55,
+ F23_D = 56,
+ F24_D = 57,
+ F25_D = 58,
+ F26_D = 59,
+ F27_D = 60,
+ F28_D = 61,
+ F29_D = 62,
+ F30_D = 63,
+ F31_D = 64,
+ F0_F = 65,
+ F1_F = 66,
+ F2_F = 67,
+ F3_F = 68,
+ F4_F = 69,
+ F5_F = 70,
+ F6_F = 71,
+ F7_F = 72,
+ F8_F = 73,
+ F9_F = 74,
+ F10_F = 75,
+ F11_F = 76,
+ F12_F = 77,
+ F13_F = 78,
+ F14_F = 79,
+ F15_F = 80,
+ F16_F = 81,
+ F17_F = 82,
+ F18_F = 83,
+ F19_F = 84,
+ F20_F = 85,
+ F21_F = 86,
+ F22_F = 87,
+ F23_F = 88,
+ F24_F = 89,
+ F25_F = 90,
+ F26_F = 91,
+ F27_F = 92,
+ F28_F = 93,
+ F29_F = 94,
+ F30_F = 95,
+ F31_F = 96,
+ NUM_TARGET_REGS // 97
+};
+} // end namespace RISCV
+
+// Register classes
+
+namespace RISCV {
+enum {
+ FPR32RegClassID = 0,
+ GPRRegClassID = 1,
+ GPRNoX0RegClassID = 2,
+ GPRNoX0X2RegClassID = 3,
+ GPRTCRegClassID = 4,
+ FPR32CRegClassID = 5,
+ GPRCRegClassID = 6,
+ GPRC_and_GPRTCRegClassID = 7,
+ GPRX0RegClassID = 8,
+ SPRegClassID = 9,
+ FPR64RegClassID = 10,
+ FPR64CRegClassID = 11,
+
+ };
+} // end namespace RISCV
+
+
+// Register alternate name indices
+
+namespace RISCV {
+enum {
+ ABIRegAltName, // 0
+ NoRegAltName, // 1
+ NUM_TARGET_REG_ALT_NAMES = 2
+};
+} // end namespace RISCV
+
+
+// Subregister indices
+
+namespace RISCV {
+enum {
+ NoSubRegister,
+ sub_32, // 1
+ NUM_TARGET_SUBREGS
+};
+} // end namespace RISCV
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_ENUM
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* MC Register Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_MC_DESC
+#undef GET_REGINFO_MC_DESC
+
+namespace llvm {
+
+extern const MCPhysReg RISCVRegDiffLists[] = {
+ /* 0 */ 32, 0,
+ /* 2 */ 65503, 0,
+ /* 4 */ 65504, 0,
+ /* 6 */ 65535, 0,
+};
+
+extern const LaneBitmask RISCVLaneMaskLists[] = {
+ /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(),
+ /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(),
+};
+
+extern const uint16_t RISCVSubRegIdxLists[] = {
+ /* 0 */ 1, 0,
+};
+
+extern const MCRegisterInfo::SubRegCoveredBits RISCVSubRegIdxRanges[] = {
+ { 65535, 65535 },
+ { 0, 32 }, // sub_32
+};
+
+extern const char RISCVRegStrings[] = {
+ /* 0 */ 'X', '1', '0', 0,
+ /* 4 */ 'X', '2', '0', 0,
+ /* 8 */ 'X', '3', '0', 0,
+ /* 12 */ 'X', '0', 0,
+ /* 15 */ 'X', '1', '1', 0,
+ /* 19 */ 'X', '2', '1', 0,
+ /* 23 */ 'X', '3', '1', 0,
+ /* 27 */ 'X', '1', 0,
+ /* 30 */ 'X', '1', '2', 0,
+ /* 34 */ 'X', '2', '2', 0,
+ /* 38 */ 'X', '2', 0,
+ /* 41 */ 'X', '1', '3', 0,
+ /* 45 */ 'X', '2', '3', 0,
+ /* 49 */ 'X', '3', 0,
+ /* 52 */ 'X', '1', '4', 0,
+ /* 56 */ 'X', '2', '4', 0,
+ /* 60 */ 'X', '4', 0,
+ /* 63 */ 'X', '1', '5', 0,
+ /* 67 */ 'X', '2', '5', 0,
+ /* 71 */ 'X', '5', 0,
+ /* 74 */ 'X', '1', '6', 0,
+ /* 78 */ 'X', '2', '6', 0,
+ /* 82 */ 'X', '6', 0,
+ /* 85 */ 'X', '1', '7', 0,
+ /* 89 */ 'X', '2', '7', 0,
+ /* 93 */ 'X', '7', 0,
+ /* 96 */ 'X', '1', '8', 0,
+ /* 100 */ 'X', '2', '8', 0,
+ /* 104 */ 'X', '8', 0,
+ /* 107 */ 'X', '1', '9', 0,
+ /* 111 */ 'X', '2', '9', 0,
+ /* 115 */ 'X', '9', 0,
+ /* 118 */ 'F', '1', '0', '_', 'D', 0,
+ /* 124 */ 'F', '2', '0', '_', 'D', 0,
+ /* 130 */ 'F', '3', '0', '_', 'D', 0,
+ /* 136 */ 'F', '0', '_', 'D', 0,
+ /* 141 */ 'F', '1', '1', '_', 'D', 0,
+ /* 147 */ 'F', '2', '1', '_', 'D', 0,
+ /* 153 */ 'F', '3', '1', '_', 'D', 0,
+ /* 159 */ 'F', '1', '_', 'D', 0,
+ /* 164 */ 'F', '1', '2', '_', 'D', 0,
+ /* 170 */ 'F', '2', '2', '_', 'D', 0,
+ /* 176 */ 'F', '2', '_', 'D', 0,
+ /* 181 */ 'F', '1', '3', '_', 'D', 0,
+ /* 187 */ 'F', '2', '3', '_', 'D', 0,
+ /* 193 */ 'F', '3', '_', 'D', 0,
+ /* 198 */ 'F', '1', '4', '_', 'D', 0,
+ /* 204 */ 'F', '2', '4', '_', 'D', 0,
+ /* 210 */ 'F', '4', '_', 'D', 0,
+ /* 215 */ 'F', '1', '5', '_', 'D', 0,
+ /* 221 */ 'F', '2', '5', '_', 'D', 0,
+ /* 227 */ 'F', '5', '_', 'D', 0,
+ /* 232 */ 'F', '1', '6', '_', 'D', 0,
+ /* 238 */ 'F', '2', '6', '_', 'D', 0,
+ /* 244 */ 'F', '6', '_', 'D', 0,
+ /* 249 */ 'F', '1', '7', '_', 'D', 0,
+ /* 255 */ 'F', '2', '7', '_', 'D', 0,
+ /* 261 */ 'F', '7', '_', 'D', 0,
+ /* 266 */ 'F', '1', '8', '_', 'D', 0,
+ /* 272 */ 'F', '2', '8', '_', 'D', 0,
+ /* 278 */ 'F', '8', '_', 'D', 0,
+ /* 283 */ 'F', '1', '9', '_', 'D', 0,
+ /* 289 */ 'F', '2', '9', '_', 'D', 0,
+ /* 295 */ 'F', '9', '_', 'D', 0,
+ /* 300 */ 'F', '1', '0', '_', 'F', 0,
+ /* 306 */ 'F', '2', '0', '_', 'F', 0,
+ /* 312 */ 'F', '3', '0', '_', 'F', 0,
+ /* 318 */ 'F', '0', '_', 'F', 0,
+ /* 323 */ 'F', '1', '1', '_', 'F', 0,
+ /* 329 */ 'F', '2', '1', '_', 'F', 0,
+ /* 335 */ 'F', '3', '1', '_', 'F', 0,
+ /* 341 */ 'F', '1', '_', 'F', 0,
+ /* 346 */ 'F', '1', '2', '_', 'F', 0,
+ /* 352 */ 'F', '2', '2', '_', 'F', 0,
+ /* 358 */ 'F', '2', '_', 'F', 0,
+ /* 363 */ 'F', '1', '3', '_', 'F', 0,
+ /* 369 */ 'F', '2', '3', '_', 'F', 0,
+ /* 375 */ 'F', '3', '_', 'F', 0,
+ /* 380 */ 'F', '1', '4', '_', 'F', 0,
+ /* 386 */ 'F', '2', '4', '_', 'F', 0,
+ /* 392 */ 'F', '4', '_', 'F', 0,
+ /* 397 */ 'F', '1', '5', '_', 'F', 0,
+ /* 403 */ 'F', '2', '5', '_', 'F', 0,
+ /* 409 */ 'F', '5', '_', 'F', 0,
+ /* 414 */ 'F', '1', '6', '_', 'F', 0,
+ /* 420 */ 'F', '2', '6', '_', 'F', 0,
+ /* 426 */ 'F', '6', '_', 'F', 0,
+ /* 431 */ 'F', '1', '7', '_', 'F', 0,
+ /* 437 */ 'F', '2', '7', '_', 'F', 0,
+ /* 443 */ 'F', '7', '_', 'F', 0,
+ /* 448 */ 'F', '1', '8', '_', 'F', 0,
+ /* 454 */ 'F', '2', '8', '_', 'F', 0,
+ /* 460 */ 'F', '8', '_', 'F', 0,
+ /* 465 */ 'F', '1', '9', '_', 'F', 0,
+ /* 471 */ 'F', '2', '9', '_', 'F', 0,
+ /* 477 */ 'F', '9', '_', 'F', 0,
+};
+
+extern const MCRegisterDesc RISCVRegDesc[] = { // Descriptors
+ { 3, 0, 0, 0, 0, 0 },
+ { 12, 1, 1, 1, 97, 0 },
+ { 27, 1, 1, 1, 97, 0 },
+ { 38, 1, 1, 1, 97, 0 },
+ { 49, 1, 1, 1, 97, 0 },
+ { 60, 1, 1, 1, 97, 0 },
+ { 71, 1, 1, 1, 97, 0 },
+ { 82, 1, 1, 1, 97, 0 },
+ { 93, 1, 1, 1, 97, 0 },
+ { 104, 1, 1, 1, 97, 0 },
+ { 115, 1, 1, 1, 97, 0 },
+ { 0, 1, 1, 1, 97, 0 },
+ { 15, 1, 1, 1, 97, 0 },
+ { 30, 1, 1, 1, 97, 0 },
+ { 41, 1, 1, 1, 97, 0 },
+ { 52, 1, 1, 1, 97, 0 },
+ { 63, 1, 1, 1, 97, 0 },
+ { 74, 1, 1, 1, 97, 0 },
+ { 85, 1, 1, 1, 97, 0 },
+ { 96, 1, 1, 1, 97, 0 },
+ { 107, 1, 1, 1, 97, 0 },
+ { 4, 1, 1, 1, 97, 0 },
+ { 19, 1, 1, 1, 97, 0 },
+ { 34, 1, 1, 1, 97, 0 },
+ { 45, 1, 1, 1, 97, 0 },
+ { 56, 1, 1, 1, 97, 0 },
+ { 67, 1, 1, 1, 97, 0 },
+ { 78, 1, 1, 1, 97, 0 },
+ { 89, 1, 1, 1, 97, 0 },
+ { 100, 1, 1, 1, 97, 0 },
+ { 111, 1, 1, 1, 97, 0 },
+ { 8, 1, 1, 1, 97, 0 },
+ { 23, 1, 1, 1, 97, 0 },
+ { 136, 0, 1, 0, 97, 2 },
+ { 159, 0, 1, 0, 97, 2 },
+ { 176, 0, 1, 0, 97, 2 },
+ { 193, 0, 1, 0, 97, 2 },
+ { 210, 0, 1, 0, 97, 2 },
+ { 227, 0, 1, 0, 97, 2 },
+ { 244, 0, 1, 0, 97, 2 },
+ { 261, 0, 1, 0, 97, 2 },
+ { 278, 0, 1, 0, 97, 2 },
+ { 295, 0, 1, 0, 97, 2 },
+ { 118, 0, 1, 0, 97, 2 },
+ { 141, 0, 1, 0, 97, 2 },
+ { 164, 0, 1, 0, 97, 2 },
+ { 181, 0, 1, 0, 97, 2 },
+ { 198, 0, 1, 0, 97, 2 },
+ { 215, 0, 1, 0, 97, 2 },
+ { 232, 0, 1, 0, 97, 2 },
+ { 249, 0, 1, 0, 97, 2 },
+ { 266, 0, 1, 0, 97, 2 },
+ { 283, 0, 1, 0, 97, 2 },
+ { 124, 0, 1, 0, 97, 2 },
+ { 147, 0, 1, 0, 97, 2 },
+ { 170, 0, 1, 0, 97, 2 },
+ { 187, 0, 1, 0, 97, 2 },
+ { 204, 0, 1, 0, 97, 2 },
+ { 221, 0, 1, 0, 97, 2 },
+ { 238, 0, 1, 0, 97, 2 },
+ { 255, 0, 1, 0, 97, 2 },
+ { 272, 0, 1, 0, 97, 2 },
+ { 289, 0, 1, 0, 97, 2 },
+ { 130, 0, 1, 0, 97, 2 },
+ { 153, 0, 1, 0, 97, 2 },
+ { 318, 1, 4, 1, 33, 0 },
+ { 341, 1, 4, 1, 33, 0 },
+ { 358, 1, 4, 1, 33, 0 },
+ { 375, 1, 4, 1, 33, 0 },
+ { 392, 1, 4, 1, 33, 0 },
+ { 409, 1, 4, 1, 33, 0 },
+ { 426, 1, 4, 1, 33, 0 },
+ { 443, 1, 4, 1, 33, 0 },
+ { 460, 1, 4, 1, 33, 0 },
+ { 477, 1, 4, 1, 33, 0 },
+ { 300, 1, 4, 1, 33, 0 },
+ { 323, 1, 4, 1, 33, 0 },
+ { 346, 1, 4, 1, 33, 0 },
+ { 363, 1, 4, 1, 33, 0 },
+ { 380, 1, 4, 1, 33, 0 },
+ { 397, 1, 4, 1, 33, 0 },
+ { 414, 1, 4, 1, 33, 0 },
+ { 431, 1, 4, 1, 33, 0 },
+ { 448, 1, 4, 1, 33, 0 },
+ { 465, 1, 4, 1, 33, 0 },
+ { 306, 1, 4, 1, 33, 0 },
+ { 329, 1, 4, 1, 33, 0 },
+ { 352, 1, 4, 1, 33, 0 },
+ { 369, 1, 4, 1, 33, 0 },
+ { 386, 1, 4, 1, 33, 0 },
+ { 403, 1, 4, 1, 33, 0 },
+ { 420, 1, 4, 1, 33, 0 },
+ { 437, 1, 4, 1, 33, 0 },
+ { 454, 1, 4, 1, 33, 0 },
+ { 471, 1, 4, 1, 33, 0 },
+ { 312, 1, 4, 1, 33, 0 },
+ { 335, 1, 4, 1, 33, 0 },
+};
+
+extern const MCPhysReg RISCVRegUnitRoots[][2] = {
+ { RISCV::X0 },
+ { RISCV::X1 },
+ { RISCV::X2 },
+ { RISCV::X3 },
+ { RISCV::X4 },
+ { RISCV::X5 },
+ { RISCV::X6 },
+ { RISCV::X7 },
+ { RISCV::X8 },
+ { RISCV::X9 },
+ { RISCV::X10 },
+ { RISCV::X11 },
+ { RISCV::X12 },
+ { RISCV::X13 },
+ { RISCV::X14 },
+ { RISCV::X15 },
+ { RISCV::X16 },
+ { RISCV::X17 },
+ { RISCV::X18 },
+ { RISCV::X19 },
+ { RISCV::X20 },
+ { RISCV::X21 },
+ { RISCV::X22 },
+ { RISCV::X23 },
+ { RISCV::X24 },
+ { RISCV::X25 },
+ { RISCV::X26 },
+ { RISCV::X27 },
+ { RISCV::X28 },
+ { RISCV::X29 },
+ { RISCV::X30 },
+ { RISCV::X31 },
+ { RISCV::F0_F },
+ { RISCV::F1_F },
+ { RISCV::F2_F },
+ { RISCV::F3_F },
+ { RISCV::F4_F },
+ { RISCV::F5_F },
+ { RISCV::F6_F },
+ { RISCV::F7_F },
+ { RISCV::F8_F },
+ { RISCV::F9_F },
+ { RISCV::F10_F },
+ { RISCV::F11_F },
+ { RISCV::F12_F },
+ { RISCV::F13_F },
+ { RISCV::F14_F },
+ { RISCV::F15_F },
+ { RISCV::F16_F },
+ { RISCV::F17_F },
+ { RISCV::F18_F },
+ { RISCV::F19_F },
+ { RISCV::F20_F },
+ { RISCV::F21_F },
+ { RISCV::F22_F },
+ { RISCV::F23_F },
+ { RISCV::F24_F },
+ { RISCV::F25_F },
+ { RISCV::F26_F },
+ { RISCV::F27_F },
+ { RISCV::F28_F },
+ { RISCV::F29_F },
+ { RISCV::F30_F },
+ { RISCV::F31_F },
+};
+
+namespace { // Register classes...
+ // FPR32 Register Class...
+ const MCPhysReg FPR32[] = {
+ RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F,
+ };
+
+ // FPR32 Bit set.
+ const uint8_t FPR32Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // GPR Register Class...
+ const MCPhysReg GPR[] = {
+ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4,
+ };
+
+ // GPR Bit set.
+ const uint8_t GPRBits[] = {
+ 0xfe, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // GPRNoX0 Register Class...
+ const MCPhysReg GPRNoX0[] = {
+ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4,
+ };
+
+ // GPRNoX0 Bit set.
+ const uint8_t GPRNoX0Bits[] = {
+ 0xfc, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // GPRNoX0X2 Register Class...
+ const MCPhysReg GPRNoX0X2[] = {
+ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X3, RISCV::X4,
+ };
+
+ // GPRNoX0X2 Bit set.
+ const uint8_t GPRNoX0X2Bits[] = {
+ 0xf4, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // GPRTC Register Class...
+ const MCPhysReg GPRTC[] = {
+ RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31,
+ };
+
+ // GPRTC Bit set.
+ const uint8_t GPRTCBits[] = {
+ 0xc0, 0xf9, 0x07, 0xe0, 0x01,
+ };
+
+ // FPR32C Register Class...
+ const MCPhysReg FPR32C[] = {
+ RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F8_F, RISCV::F9_F,
+ };
+
+ // FPR32C Bit set.
+ const uint8_t FPR32CBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
+ };
+
+ // GPRC Register Class...
+ const MCPhysReg GPRC[] = {
+ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X8, RISCV::X9,
+ };
+
+ // GPRC Bit set.
+ const uint8_t GPRCBits[] = {
+ 0x00, 0xfe, 0x01,
+ };
+
+ // GPRC_and_GPRTC Register Class...
+ const MCPhysReg GPRC_and_GPRTC[] = {
+ RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
+ };
+
+ // GPRC_and_GPRTC Bit set.
+ const uint8_t GPRC_and_GPRTCBits[] = {
+ 0x00, 0xf8, 0x01,
+ };
+
+ // GPRX0 Register Class...
+ const MCPhysReg GPRX0[] = {
+ RISCV::X0,
+ };
+
+ // GPRX0 Bit set.
+ const uint8_t GPRX0Bits[] = {
+ 0x02,
+ };
+
+ // SP Register Class...
+ const MCPhysReg SP[] = {
+ RISCV::X2,
+ };
+
+ // SP Bit set.
+ const uint8_t SPBits[] = {
+ 0x08,
+ };
+
+ // FPR64 Register Class...
+ const MCPhysReg FPR64[] = {
+ RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D,
+ };
+
+ // FPR64 Bit set.
+ const uint8_t FPR64Bits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
+ };
+
+ // FPR64C Register Class...
+ const MCPhysReg FPR64C[] = {
+ RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F8_D, RISCV::F9_D,
+ };
+
+ // FPR64C Bit set.
+ const uint8_t FPR64CBits[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
+ };
+
+} // end anonymous namespace
+
+extern const char RISCVRegClassStrings[] = {
+ /* 0 */ 'G', 'P', 'R', 'X', '0', 0,
+ /* 6 */ 'G', 'P', 'R', 'N', 'o', 'X', '0', 0,
+ /* 14 */ 'F', 'P', 'R', '3', '2', 0,
+ /* 20 */ 'G', 'P', 'R', 'N', 'o', 'X', '0', 'X', '2', 0,
+ /* 30 */ 'F', 'P', 'R', '6', '4', 0,
+ /* 36 */ 'F', 'P', 'R', '3', '2', 'C', 0,
+ /* 43 */ 'F', 'P', 'R', '6', '4', 'C', 0,
+ /* 50 */ 'G', 'P', 'R', 'C', 0,
+ /* 55 */ 'G', 'P', 'R', 'C', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'T', 'C', 0,
+ /* 70 */ 'S', 'P', 0,
+ /* 73 */ 'G', 'P', 'R', 0,
+};
+
+extern const MCRegisterClass RISCVMCRegisterClasses[] = {
+ { FPR32, FPR32Bits, 14, 32, sizeof(FPR32Bits), RISCV::FPR32RegClassID, 1, true },
+ { GPR, GPRBits, 73, 32, sizeof(GPRBits), RISCV::GPRRegClassID, 1, true },
+ { GPRNoX0, GPRNoX0Bits, 6, 31, sizeof(GPRNoX0Bits), RISCV::GPRNoX0RegClassID, 1, true },
+ { GPRNoX0X2, GPRNoX0X2Bits, 20, 30, sizeof(GPRNoX0X2Bits), RISCV::GPRNoX0X2RegClassID, 1, true },
+ { GPRTC, GPRTCBits, 64, 15, sizeof(GPRTCBits), RISCV::GPRTCRegClassID, 1, true },
+ { FPR32C, FPR32CBits, 36, 8, sizeof(FPR32CBits), RISCV::FPR32CRegClassID, 1, true },
+ { GPRC, GPRCBits, 50, 8, sizeof(GPRCBits), RISCV::GPRCRegClassID, 1, true },
+ { GPRC_and_GPRTC, GPRC_and_GPRTCBits, 55, 6, sizeof(GPRC_and_GPRTCBits), RISCV::GPRC_and_GPRTCRegClassID, 1, true },
+ { GPRX0, GPRX0Bits, 0, 1, sizeof(GPRX0Bits), RISCV::GPRX0RegClassID, 1, true },
+ { SP, SPBits, 70, 1, sizeof(SPBits), RISCV::SPRegClassID, 1, true },
+ { FPR64, FPR64Bits, 30, 32, sizeof(FPR64Bits), RISCV::FPR64RegClassID, 1, true },
+ { FPR64C, FPR64CBits, 43, 8, sizeof(FPR64CBits), RISCV::FPR64CRegClassID, 1, true },
+};
+
+// RISCV Dwarf<->LLVM register mappings.
+extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[] = {
+ { 0U, RISCV::X0 },
+ { 1U, RISCV::X1 },
+ { 2U, RISCV::X2 },
+ { 3U, RISCV::X3 },
+ { 4U, RISCV::X4 },
+ { 5U, RISCV::X5 },
+ { 6U, RISCV::X6 },
+ { 7U, RISCV::X7 },
+ { 8U, RISCV::X8 },
+ { 9U, RISCV::X9 },
+ { 10U, RISCV::X10 },
+ { 11U, RISCV::X11 },
+ { 12U, RISCV::X12 },
+ { 13U, RISCV::X13 },
+ { 14U, RISCV::X14 },
+ { 15U, RISCV::X15 },
+ { 16U, RISCV::X16 },
+ { 17U, RISCV::X17 },
+ { 18U, RISCV::X18 },
+ { 19U, RISCV::X19 },
+ { 20U, RISCV::X20 },
+ { 21U, RISCV::X21 },
+ { 22U, RISCV::X22 },
+ { 23U, RISCV::X23 },
+ { 24U, RISCV::X24 },
+ { 25U, RISCV::X25 },
+ { 26U, RISCV::X26 },
+ { 27U, RISCV::X27 },
+ { 28U, RISCV::X28 },
+ { 29U, RISCV::X29 },
+ { 30U, RISCV::X30 },
+ { 31U, RISCV::X31 },
+ { 32U, RISCV::F0_F },
+ { 33U, RISCV::F1_F },
+ { 34U, RISCV::F2_F },
+ { 35U, RISCV::F3_F },
+ { 36U, RISCV::F4_F },
+ { 37U, RISCV::F5_F },
+ { 38U, RISCV::F6_F },
+ { 39U, RISCV::F7_F },
+ { 40U, RISCV::F8_F },
+ { 41U, RISCV::F9_F },
+ { 42U, RISCV::F10_F },
+ { 43U, RISCV::F11_F },
+ { 44U, RISCV::F12_F },
+ { 45U, RISCV::F13_F },
+ { 46U, RISCV::F14_F },
+ { 47U, RISCV::F15_F },
+ { 48U, RISCV::F16_F },
+ { 49U, RISCV::F17_F },
+ { 50U, RISCV::F18_F },
+ { 51U, RISCV::F19_F },
+ { 52U, RISCV::F20_F },
+ { 53U, RISCV::F21_F },
+ { 54U, RISCV::F22_F },
+ { 55U, RISCV::F23_F },
+ { 56U, RISCV::F24_F },
+ { 57U, RISCV::F25_F },
+ { 58U, RISCV::F26_F },
+ { 59U, RISCV::F27_F },
+ { 60U, RISCV::F28_F },
+ { 61U, RISCV::F29_F },
+ { 62U, RISCV::F30_F },
+ { 63U, RISCV::F31_F },
+};
+extern const unsigned RISCVDwarfFlavour0Dwarf2LSize = array_lengthof(RISCVDwarfFlavour0Dwarf2L);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[] = {
+ { 0U, RISCV::X0 },
+ { 1U, RISCV::X1 },
+ { 2U, RISCV::X2 },
+ { 3U, RISCV::X3 },
+ { 4U, RISCV::X4 },
+ { 5U, RISCV::X5 },
+ { 6U, RISCV::X6 },
+ { 7U, RISCV::X7 },
+ { 8U, RISCV::X8 },
+ { 9U, RISCV::X9 },
+ { 10U, RISCV::X10 },
+ { 11U, RISCV::X11 },
+ { 12U, RISCV::X12 },
+ { 13U, RISCV::X13 },
+ { 14U, RISCV::X14 },
+ { 15U, RISCV::X15 },
+ { 16U, RISCV::X16 },
+ { 17U, RISCV::X17 },
+ { 18U, RISCV::X18 },
+ { 19U, RISCV::X19 },
+ { 20U, RISCV::X20 },
+ { 21U, RISCV::X21 },
+ { 22U, RISCV::X22 },
+ { 23U, RISCV::X23 },
+ { 24U, RISCV::X24 },
+ { 25U, RISCV::X25 },
+ { 26U, RISCV::X26 },
+ { 27U, RISCV::X27 },
+ { 28U, RISCV::X28 },
+ { 29U, RISCV::X29 },
+ { 30U, RISCV::X30 },
+ { 31U, RISCV::X31 },
+ { 32U, RISCV::F0_F },
+ { 33U, RISCV::F1_F },
+ { 34U, RISCV::F2_F },
+ { 35U, RISCV::F3_F },
+ { 36U, RISCV::F4_F },
+ { 37U, RISCV::F5_F },
+ { 38U, RISCV::F6_F },
+ { 39U, RISCV::F7_F },
+ { 40U, RISCV::F8_F },
+ { 41U, RISCV::F9_F },
+ { 42U, RISCV::F10_F },
+ { 43U, RISCV::F11_F },
+ { 44U, RISCV::F12_F },
+ { 45U, RISCV::F13_F },
+ { 46U, RISCV::F14_F },
+ { 47U, RISCV::F15_F },
+ { 48U, RISCV::F16_F },
+ { 49U, RISCV::F17_F },
+ { 50U, RISCV::F18_F },
+ { 51U, RISCV::F19_F },
+ { 52U, RISCV::F20_F },
+ { 53U, RISCV::F21_F },
+ { 54U, RISCV::F22_F },
+ { 55U, RISCV::F23_F },
+ { 56U, RISCV::F24_F },
+ { 57U, RISCV::F25_F },
+ { 58U, RISCV::F26_F },
+ { 59U, RISCV::F27_F },
+ { 60U, RISCV::F28_F },
+ { 61U, RISCV::F29_F },
+ { 62U, RISCV::F30_F },
+ { 63U, RISCV::F31_F },
+};
+extern const unsigned RISCVEHFlavour0Dwarf2LSize = array_lengthof(RISCVEHFlavour0Dwarf2L);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[] = {
+ { RISCV::X0, 0U },
+ { RISCV::X1, 1U },
+ { RISCV::X2, 2U },
+ { RISCV::X3, 3U },
+ { RISCV::X4, 4U },
+ { RISCV::X5, 5U },
+ { RISCV::X6, 6U },
+ { RISCV::X7, 7U },
+ { RISCV::X8, 8U },
+ { RISCV::X9, 9U },
+ { RISCV::X10, 10U },
+ { RISCV::X11, 11U },
+ { RISCV::X12, 12U },
+ { RISCV::X13, 13U },
+ { RISCV::X14, 14U },
+ { RISCV::X15, 15U },
+ { RISCV::X16, 16U },
+ { RISCV::X17, 17U },
+ { RISCV::X18, 18U },
+ { RISCV::X19, 19U },
+ { RISCV::X20, 20U },
+ { RISCV::X21, 21U },
+ { RISCV::X22, 22U },
+ { RISCV::X23, 23U },
+ { RISCV::X24, 24U },
+ { RISCV::X25, 25U },
+ { RISCV::X26, 26U },
+ { RISCV::X27, 27U },
+ { RISCV::X28, 28U },
+ { RISCV::X29, 29U },
+ { RISCV::X30, 30U },
+ { RISCV::X31, 31U },
+ { RISCV::F0_D, 32U },
+ { RISCV::F1_D, 33U },
+ { RISCV::F2_D, 34U },
+ { RISCV::F3_D, 35U },
+ { RISCV::F4_D, 36U },
+ { RISCV::F5_D, 37U },
+ { RISCV::F6_D, 38U },
+ { RISCV::F7_D, 39U },
+ { RISCV::F8_D, 40U },
+ { RISCV::F9_D, 41U },
+ { RISCV::F10_D, 42U },
+ { RISCV::F11_D, 43U },
+ { RISCV::F12_D, 44U },
+ { RISCV::F13_D, 45U },
+ { RISCV::F14_D, 46U },
+ { RISCV::F15_D, 47U },
+ { RISCV::F16_D, 48U },
+ { RISCV::F17_D, 49U },
+ { RISCV::F18_D, 50U },
+ { RISCV::F19_D, 51U },
+ { RISCV::F20_D, 52U },
+ { RISCV::F21_D, 53U },
+ { RISCV::F22_D, 54U },
+ { RISCV::F23_D, 55U },
+ { RISCV::F24_D, 56U },
+ { RISCV::F25_D, 57U },
+ { RISCV::F26_D, 58U },
+ { RISCV::F27_D, 59U },
+ { RISCV::F28_D, 60U },
+ { RISCV::F29_D, 61U },
+ { RISCV::F30_D, 62U },
+ { RISCV::F31_D, 63U },
+ { RISCV::F0_F, 32U },
+ { RISCV::F1_F, 33U },
+ { RISCV::F2_F, 34U },
+ { RISCV::F3_F, 35U },
+ { RISCV::F4_F, 36U },
+ { RISCV::F5_F, 37U },
+ { RISCV::F6_F, 38U },
+ { RISCV::F7_F, 39U },
+ { RISCV::F8_F, 40U },
+ { RISCV::F9_F, 41U },
+ { RISCV::F10_F, 42U },
+ { RISCV::F11_F, 43U },
+ { RISCV::F12_F, 44U },
+ { RISCV::F13_F, 45U },
+ { RISCV::F14_F, 46U },
+ { RISCV::F15_F, 47U },
+ { RISCV::F16_F, 48U },
+ { RISCV::F17_F, 49U },
+ { RISCV::F18_F, 50U },
+ { RISCV::F19_F, 51U },
+ { RISCV::F20_F, 52U },
+ { RISCV::F21_F, 53U },
+ { RISCV::F22_F, 54U },
+ { RISCV::F23_F, 55U },
+ { RISCV::F24_F, 56U },
+ { RISCV::F25_F, 57U },
+ { RISCV::F26_F, 58U },
+ { RISCV::F27_F, 59U },
+ { RISCV::F28_F, 60U },
+ { RISCV::F29_F, 61U },
+ { RISCV::F30_F, 62U },
+ { RISCV::F31_F, 63U },
+};
+extern const unsigned RISCVDwarfFlavour0L2DwarfSize = array_lengthof(RISCVDwarfFlavour0L2Dwarf);
+
+extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[] = {
+ { RISCV::X0, 0U },
+ { RISCV::X1, 1U },
+ { RISCV::X2, 2U },
+ { RISCV::X3, 3U },
+ { RISCV::X4, 4U },
+ { RISCV::X5, 5U },
+ { RISCV::X6, 6U },
+ { RISCV::X7, 7U },
+ { RISCV::X8, 8U },
+ { RISCV::X9, 9U },
+ { RISCV::X10, 10U },
+ { RISCV::X11, 11U },
+ { RISCV::X12, 12U },
+ { RISCV::X13, 13U },
+ { RISCV::X14, 14U },
+ { RISCV::X15, 15U },
+ { RISCV::X16, 16U },
+ { RISCV::X17, 17U },
+ { RISCV::X18, 18U },
+ { RISCV::X19, 19U },
+ { RISCV::X20, 20U },
+ { RISCV::X21, 21U },
+ { RISCV::X22, 22U },
+ { RISCV::X23, 23U },
+ { RISCV::X24, 24U },
+ { RISCV::X25, 25U },
+ { RISCV::X26, 26U },
+ { RISCV::X27, 27U },
+ { RISCV::X28, 28U },
+ { RISCV::X29, 29U },
+ { RISCV::X30, 30U },
+ { RISCV::X31, 31U },
+ { RISCV::F0_D, 32U },
+ { RISCV::F1_D, 33U },
+ { RISCV::F2_D, 34U },
+ { RISCV::F3_D, 35U },
+ { RISCV::F4_D, 36U },
+ { RISCV::F5_D, 37U },
+ { RISCV::F6_D, 38U },
+ { RISCV::F7_D, 39U },
+ { RISCV::F8_D, 40U },
+ { RISCV::F9_D, 41U },
+ { RISCV::F10_D, 42U },
+ { RISCV::F11_D, 43U },
+ { RISCV::F12_D, 44U },
+ { RISCV::F13_D, 45U },
+ { RISCV::F14_D, 46U },
+ { RISCV::F15_D, 47U },
+ { RISCV::F16_D, 48U },
+ { RISCV::F17_D, 49U },
+ { RISCV::F18_D, 50U },
+ { RISCV::F19_D, 51U },
+ { RISCV::F20_D, 52U },
+ { RISCV::F21_D, 53U },
+ { RISCV::F22_D, 54U },
+ { RISCV::F23_D, 55U },
+ { RISCV::F24_D, 56U },
+ { RISCV::F25_D, 57U },
+ { RISCV::F26_D, 58U },
+ { RISCV::F27_D, 59U },
+ { RISCV::F28_D, 60U },
+ { RISCV::F29_D, 61U },
+ { RISCV::F30_D, 62U },
+ { RISCV::F31_D, 63U },
+ { RISCV::F0_F, 32U },
+ { RISCV::F1_F, 33U },
+ { RISCV::F2_F, 34U },
+ { RISCV::F3_F, 35U },
+ { RISCV::F4_F, 36U },
+ { RISCV::F5_F, 37U },
+ { RISCV::F6_F, 38U },
+ { RISCV::F7_F, 39U },
+ { RISCV::F8_F, 40U },
+ { RISCV::F9_F, 41U },
+ { RISCV::F10_F, 42U },
+ { RISCV::F11_F, 43U },
+ { RISCV::F12_F, 44U },
+ { RISCV::F13_F, 45U },
+ { RISCV::F14_F, 46U },
+ { RISCV::F15_F, 47U },
+ { RISCV::F16_F, 48U },
+ { RISCV::F17_F, 49U },
+ { RISCV::F18_F, 50U },
+ { RISCV::F19_F, 51U },
+ { RISCV::F20_F, 52U },
+ { RISCV::F21_F, 53U },
+ { RISCV::F22_F, 54U },
+ { RISCV::F23_F, 55U },
+ { RISCV::F24_F, 56U },
+ { RISCV::F25_F, 57U },
+ { RISCV::F26_F, 58U },
+ { RISCV::F27_F, 59U },
+ { RISCV::F28_F, 60U },
+ { RISCV::F29_F, 61U },
+ { RISCV::F30_F, 62U },
+ { RISCV::F31_F, 63U },
+};
+extern const unsigned RISCVEHFlavour0L2DwarfSize = array_lengthof(RISCVEHFlavour0L2Dwarf);
+
+extern const uint16_t RISCVRegEncodingTable[] = {
+ 0,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+};
+static inline void InitRISCVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
+ RI->InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC, RISCVMCRegisterClasses, 12, RISCVRegUnitRoots, 64, RISCVRegDiffLists, RISCVLaneMaskLists, RISCVRegStrings, RISCVRegClassStrings, RISCVSubRegIdxLists, 2,
+RISCVSubRegIdxRanges, RISCVRegEncodingTable);
+
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapDwarfRegsToLLVMRegs(RISCVDwarfFlavour0Dwarf2L, RISCVDwarfFlavour0Dwarf2LSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapDwarfRegsToLLVMRegs(RISCVEHFlavour0Dwarf2L, RISCVEHFlavour0Dwarf2LSize, true);
+ break;
+ }
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapLLVMRegsToDwarfRegs(RISCVDwarfFlavour0L2Dwarf, RISCVDwarfFlavour0L2DwarfSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ RI->mapLLVMRegsToDwarfRegs(RISCVEHFlavour0L2Dwarf, RISCVEHFlavour0L2DwarfSize, true);
+ break;
+ }
+}
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_MC_DESC
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Register Information Header Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_HEADER
+#undef GET_REGINFO_HEADER
+
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+namespace llvm {
+
+class RISCVFrameLowering;
+
+struct RISCVGenRegisterInfo : public TargetRegisterInfo {
+ explicit RISCVGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
+ unsigned PC = 0, unsigned HwMode = 0);
+ unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
+ LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
+ LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
+ const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
+ const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
+ unsigned getRegUnitWeight(unsigned RegUnit) const override;
+ unsigned getNumRegPressureSets() const override;
+ const char *getRegPressureSetName(unsigned Idx) const override;
+ unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
+ const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
+ const int *getRegUnitPressureSets(unsigned RegUnit) const override;
+ ArrayRef<const char *> getRegMaskNames() const override;
+ ArrayRef<const uint32_t *> getRegMasks() const override;
+ /// Devirtualized TargetFrameLowering.
+ static const RISCVFrameLowering *getFrameLowering(
+ const MachineFunction &MF);
+};
+
+namespace RISCV { // Register classes
+ extern const TargetRegisterClass FPR32RegClass;
+ extern const TargetRegisterClass GPRRegClass;
+ extern const TargetRegisterClass GPRNoX0RegClass;
+ extern const TargetRegisterClass GPRNoX0X2RegClass;
+ extern const TargetRegisterClass GPRTCRegClass;
+ extern const TargetRegisterClass FPR32CRegClass;
+ extern const TargetRegisterClass GPRCRegClass;
+ extern const TargetRegisterClass GPRC_and_GPRTCRegClass;
+ extern const TargetRegisterClass GPRX0RegClass;
+ extern const TargetRegisterClass SPRegClass;
+ extern const TargetRegisterClass FPR64RegClass;
+ extern const TargetRegisterClass FPR64CRegClass;
+} // end namespace RISCV
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_HEADER
+
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Target Register and Register Classes Information *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_REGINFO_TARGET_DESC
+#undef GET_REGINFO_TARGET_DESC
+
+namespace llvm {
+
+extern const MCRegisterClass RISCVMCRegisterClasses[];
+
+static const MVT::SimpleValueType VTLists[] = {
+ /* 0 */ MVT::i32, MVT::Other,
+ /* 2 */ MVT::i64, MVT::Other,
+ /* 4 */ MVT::f32, MVT::Other,
+ /* 6 */ MVT::f64, MVT::Other,
+};
+
+static const char *const SubRegIndexNameTable[] = { "sub_32", "" };
+
+
+static const LaneBitmask SubRegIndexLaneMaskTable[] = {
+ LaneBitmask::getAll(),
+ LaneBitmask(0x00000001), // sub_32
+ };
+
+
+
+static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
+ // Mode = 0 (Default)
+ { 32, 32, 32, VTLists+4 }, // FPR32
+ { 32, 32, 32, VTLists+0 }, // GPR
+ { 32, 32, 32, VTLists+0 }, // GPRNoX0
+ { 32, 32, 32, VTLists+0 }, // GPRNoX0X2
+ { 32, 32, 32, VTLists+0 }, // GPRTC
+ { 32, 32, 32, VTLists+4 }, // FPR32C
+ { 32, 32, 32, VTLists+0 }, // GPRC
+ { 32, 32, 32, VTLists+0 }, // GPRC_and_GPRTC
+ { 32, 32, 32, VTLists+0 }, // GPRX0
+ { 32, 32, 32, VTLists+0 }, // SP
+ { 64, 64, 64, VTLists+6 }, // FPR64
+ { 64, 64, 64, VTLists+6 }, // FPR64C
+ // Mode = 1 (RV32)
+ { 32, 32, 32, VTLists+4 }, // FPR32
+ { 32, 32, 32, VTLists+0 }, // GPR
+ { 32, 32, 32, VTLists+0 }, // GPRNoX0
+ { 32, 32, 32, VTLists+0 }, // GPRNoX0X2
+ { 32, 32, 32, VTLists+0 }, // GPRTC
+ { 32, 32, 32, VTLists+4 }, // FPR32C
+ { 32, 32, 32, VTLists+0 }, // GPRC
+ { 32, 32, 32, VTLists+0 }, // GPRC_and_GPRTC
+ { 32, 32, 32, VTLists+0 }, // GPRX0
+ { 32, 32, 32, VTLists+0 }, // SP
+ { 64, 64, 64, VTLists+6 }, // FPR64
+ { 64, 64, 64, VTLists+6 }, // FPR64C
+ // Mode = 2 (RV64)
+ { 32, 32, 32, VTLists+4 }, // FPR32
+ { 64, 64, 64, VTLists+2 }, // GPR
+ { 64, 64, 64, VTLists+2 }, // GPRNoX0
+ { 64, 64, 64, VTLists+2 }, // GPRNoX0X2
+ { 64, 64, 64, VTLists+2 }, // GPRTC
+ { 32, 32, 32, VTLists+4 }, // FPR32C
+ { 64, 64, 64, VTLists+2 }, // GPRC
+ { 64, 64, 64, VTLists+2 }, // GPRC_and_GPRTC
+ { 64, 64, 64, VTLists+2 }, // GPRX0
+ { 64, 64, 64, VTLists+2 }, // SP
+ { 64, 64, 64, VTLists+6 }, // FPR64
+ { 64, 64, 64, VTLists+6 }, // FPR64C
+};
+
+static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
+
+static const uint32_t FPR32SubClassMask[] = {
+ 0x00000021,
+ 0x00000c00, // sub_32
+};
+
+static const uint32_t GPRSubClassMask[] = {
+ 0x000003de,
+};
+
+static const uint32_t GPRNoX0SubClassMask[] = {
+ 0x000002dc,
+};
+
+static const uint32_t GPRNoX0X2SubClassMask[] = {
+ 0x000000d8,
+};
+
+static const uint32_t GPRTCSubClassMask[] = {
+ 0x00000090,
+};
+
+static const uint32_t FPR32CSubClassMask[] = {
+ 0x00000020,
+ 0x00000800, // sub_32
+};
+
+static const uint32_t GPRCSubClassMask[] = {
+ 0x000000c0,
+};
+
+static const uint32_t GPRC_and_GPRTCSubClassMask[] = {
+ 0x00000080,
+};
+
+static const uint32_t GPRX0SubClassMask[] = {
+ 0x00000100,
+};
+
+static const uint32_t SPSubClassMask[] = {
+ 0x00000200,
+};
+
+static const uint32_t FPR64SubClassMask[] = {
+ 0x00000c00,
+};
+
+static const uint32_t FPR64CSubClassMask[] = {
+ 0x00000800,
+};
+
+static const uint16_t SuperRegIdxSeqs[] = {
+ /* 0 */ 1, 0,
+};
+
+static const TargetRegisterClass *const GPRNoX0Superclasses[] = {
+ &RISCV::GPRRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRNoX0X2Superclasses[] = {
+ &RISCV::GPRRegClass,
+ &RISCV::GPRNoX0RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRTCSuperclasses[] = {
+ &RISCV::GPRRegClass,
+ &RISCV::GPRNoX0RegClass,
+ &RISCV::GPRNoX0X2RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const FPR32CSuperclasses[] = {
+ &RISCV::FPR32RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRCSuperclasses[] = {
+ &RISCV::GPRRegClass,
+ &RISCV::GPRNoX0RegClass,
+ &RISCV::GPRNoX0X2RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRC_and_GPRTCSuperclasses[] = {
+ &RISCV::GPRRegClass,
+ &RISCV::GPRNoX0RegClass,
+ &RISCV::GPRNoX0X2RegClass,
+ &RISCV::GPRTCRegClass,
+ &RISCV::GPRCRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const GPRX0Superclasses[] = {
+ &RISCV::GPRRegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const SPSuperclasses[] = {
+ &RISCV::GPRRegClass,
+ &RISCV::GPRNoX0RegClass,
+ nullptr
+};
+
+static const TargetRegisterClass *const FPR64CSuperclasses[] = {
+ &RISCV::FPR64RegClass,
+ nullptr
+};
+
+
+namespace RISCV { // Register class instances
+ extern const TargetRegisterClass FPR32RegClass = {
+ &RISCVMCRegisterClasses[FPR32RegClassID],
+ FPR32SubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRRegClass = {
+ &RISCVMCRegisterClasses[GPRRegClassID],
+ GPRSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRNoX0RegClass = {
+ &RISCVMCRegisterClasses[GPRNoX0RegClassID],
+ GPRNoX0SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRNoX0Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRNoX0X2RegClass = {
+ &RISCVMCRegisterClasses[GPRNoX0X2RegClassID],
+ GPRNoX0X2SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRNoX0X2Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRTCRegClass = {
+ &RISCVMCRegisterClasses[GPRTCRegClassID],
+ GPRTCSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRTCSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FPR32CRegClass = {
+ &RISCVMCRegisterClasses[FPR32CRegClassID],
+ FPR32CSubClassMask,
+ SuperRegIdxSeqs + 0,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ FPR32CSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRCRegClass = {
+ &RISCVMCRegisterClasses[GPRCRegClassID],
+ GPRCSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRCSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRC_and_GPRTCRegClass = {
+ &RISCVMCRegisterClasses[GPRC_and_GPRTCRegClassID],
+ GPRC_and_GPRTCSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRC_and_GPRTCSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass GPRX0RegClass = {
+ &RISCVMCRegisterClasses[GPRX0RegClassID],
+ GPRX0SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ GPRX0Superclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass SPRegClass = {
+ &RISCVMCRegisterClasses[SPRegClassID],
+ SPSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ SPSuperclasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FPR64RegClass = {
+ &RISCVMCRegisterClasses[FPR64RegClassID],
+ FPR64SubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ NullRegClasses,
+ nullptr
+ };
+
+ extern const TargetRegisterClass FPR64CRegClass = {
+ &RISCVMCRegisterClasses[FPR64CRegClassID],
+ FPR64CSubClassMask,
+ SuperRegIdxSeqs + 1,
+ LaneBitmask(0x00000001),
+ 0,
+ false, /* HasDisjunctSubRegs */
+ false, /* CoveredBySubRegs */
+ FPR64CSuperclasses,
+ nullptr
+ };
+
+} // end namespace RISCV
+
+namespace {
+ const TargetRegisterClass* const RegisterClasses[] = {
+ &RISCV::FPR32RegClass,
+ &RISCV::GPRRegClass,
+ &RISCV::GPRNoX0RegClass,
+ &RISCV::GPRNoX0X2RegClass,
+ &RISCV::GPRTCRegClass,
+ &RISCV::FPR32CRegClass,
+ &RISCV::GPRCRegClass,
+ &RISCV::GPRC_and_GPRTCRegClass,
+ &RISCV::GPRX0RegClass,
+ &RISCV::SPRegClass,
+ &RISCV::FPR64RegClass,
+ &RISCV::FPR64CRegClass,
+ };
+} // end anonymous namespace
+
+static const TargetRegisterInfoDesc RISCVRegInfoDesc[] = { // Extra Descriptors
+ { 0, false },
+ { 0, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 1, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+ { 0, true },
+};
+unsigned RISCVGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
+ static const uint8_t Rows[1][1] = {
+ { 0, },
+ };
+
+ --IdxA; assert(IdxA < 1);
+ --IdxB; assert(IdxB < 1);
+ return Rows[0][IdxB];
+}
+
+ struct MaskRolOp {
+ LaneBitmask Mask;
+ uint8_t RotateLeft;
+ };
+ static const MaskRolOp LaneMaskComposeSequences[] = {
+ { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 } // Sequence 0
+ };
+ static const MaskRolOp *const CompositeSequences[] = {
+ &LaneMaskComposeSequences[0] // to sub_32
+ };
+
+LaneBitmask RISCVGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
+ --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
+ LaneBitmask Result;
+ for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
+ LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
+ if (unsigned S = Ops->RotateLeft)
+ Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
+ else
+ Result |= LaneBitmask(M);
+ }
+ return Result;
+}
+
+LaneBitmask RISCVGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
+ LaneMask &= getSubRegIndexLaneMask(IdxA);
+ --IdxA; assert(IdxA < 1 && "Subregister index out of bounds");
+ LaneBitmask Result;
+ for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
+ LaneBitmask::Type M = LaneMask.getAsInteger();
+ if (unsigned S = Ops->RotateLeft)
+ Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
+ else
+ Result |= LaneBitmask(M);
+ }
+ return Result;
+}
+
+const TargetRegisterClass *RISCVGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
+ static const uint8_t Table[12][1] = {
+ { // FPR32
+ 0, // sub_32
+ },
+ { // GPR
+ 0, // sub_32
+ },
+ { // GPRNoX0
+ 0, // sub_32
+ },
+ { // GPRNoX0X2
+ 0, // sub_32
+ },
+ { // GPRTC
+ 0, // sub_32
+ },
+ { // FPR32C
+ 0, // sub_32
+ },
+ { // GPRC
+ 0, // sub_32
+ },
+ { // GPRC_and_GPRTC
+ 0, // sub_32
+ },
+ { // GPRX0
+ 0, // sub_32
+ },
+ { // SP
+ 0, // sub_32
+ },
+ { // FPR64
+ 11, // sub_32 -> FPR64
+ },
+ { // FPR64C
+ 12, // sub_32 -> FPR64C
+ },
+ };
+ assert(RC && "Missing regclass");
+ if (!Idx) return RC;
+ --Idx;
+ assert(Idx < 1 && "Bad subreg");
+ unsigned TV = Table[RC->getID()][Idx];
+ return TV ? getRegClass(TV - 1) : nullptr;
+}
+
+/// Get the weight in units of pressure for this register class.
+const RegClassWeight &RISCVGenRegisterInfo::
+getRegClassWeight(const TargetRegisterClass *RC) const {
+ static const RegClassWeight RCWeightTable[] = {
+ {1, 32}, // FPR32
+ {1, 32}, // GPR
+ {1, 31}, // GPRNoX0
+ {1, 30}, // GPRNoX0X2
+ {1, 15}, // GPRTC
+ {1, 8}, // FPR32C
+ {1, 8}, // GPRC
+ {1, 6}, // GPRC_and_GPRTC
+ {1, 1}, // GPRX0
+ {1, 1}, // SP
+ {1, 32}, // FPR64
+ {1, 8}, // FPR64C
+ };
+ return RCWeightTable[RC->getID()];
+}
+
+/// Get the weight in units of pressure for this register unit.
+unsigned RISCVGenRegisterInfo::
+getRegUnitWeight(unsigned RegUnit) const {
+ assert(RegUnit < 64 && "invalid register unit");
+ // All register units have unit weight.
+ return 1;
+}
+
+
+// Get the number of dimensions of register pressure.
+unsigned RISCVGenRegisterInfo::getNumRegPressureSets() const {
+ return 7;
+}
+
+// Get the name of this register unit pressure set.
+const char *RISCVGenRegisterInfo::
+getRegPressureSetName(unsigned Idx) const {
+ static const char *const PressureNameTable[] = {
+ "GPRX0",
+ "SP",
+ "FPR32C",
+ "GPRC",
+ "GPRTC",
+ "FPR32",
+ "GPR",
+ };
+ return PressureNameTable[Idx];
+}
+
+// Get the register unit pressure limit for this dimension.
+// This limit must be adjusted dynamically for reserved registers.
+unsigned RISCVGenRegisterInfo::
+getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
+ static const uint8_t PressureLimitTable[] = {
+ 1, // 0: GPRX0
+ 1, // 1: SP
+ 8, // 2: FPR32C
+ 8, // 3: GPRC
+ 17, // 4: GPRTC
+ 32, // 5: FPR32
+ 32, // 6: GPR
+ };
+ return PressureLimitTable[Idx];
+}
+
+/// Table of pressure sets per register class or unit.
+static const int RCSetsTable[] = {
+ /* 0 */ 2, 5, -1,
+ /* 3 */ 0, 6, -1,
+ /* 6 */ 1, 6, -1,
+ /* 9 */ 3, 4, 6, -1,
+};
+
+/// Get the dimensions of register pressure impacted by this register class.
+/// Returns a -1 terminated array of pressure set IDs
+const int* RISCVGenRegisterInfo::
+getRegClassPressureSets(const TargetRegisterClass *RC) const {
+ static const uint8_t RCSetStartTable[] = {
+ 1,4,4,4,10,0,9,9,3,6,1,0,};
+ return &RCSetsTable[RCSetStartTable[RC->getID()]];
+}
+
+/// Get the dimensions of register pressure impacted by this register unit.
+/// Returns a -1 terminated array of pressure set IDs
+const int* RISCVGenRegisterInfo::
+getRegUnitPressureSets(unsigned RegUnit) const {
+ assert(RegUnit < 64 && "invalid register unit");
+ static const uint8_t RUSetStartTable[] = {
+ 3,4,6,4,4,10,10,10,9,9,9,9,9,9,9,9,10,10,4,4,4,4,4,4,4,4,4,4,10,10,10,10,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
+ return &RCSetsTable[RUSetStartTable[RegUnit]];
+}
+
+extern const MCRegisterDesc RISCVRegDesc[];
+extern const MCPhysReg RISCVRegDiffLists[];
+extern const LaneBitmask RISCVLaneMaskLists[];
+extern const char RISCVRegStrings[];
+extern const char RISCVRegClassStrings[];
+extern const MCPhysReg RISCVRegUnitRoots[][2];
+extern const uint16_t RISCVSubRegIdxLists[];
+extern const MCRegisterInfo::SubRegCoveredBits RISCVSubRegIdxRanges[];
+extern const uint16_t RISCVRegEncodingTable[];
+// RISCV Dwarf<->LLVM register mappings.
+extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[];
+extern const unsigned RISCVDwarfFlavour0Dwarf2LSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[];
+extern const unsigned RISCVEHFlavour0Dwarf2LSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[];
+extern const unsigned RISCVDwarfFlavour0L2DwarfSize;
+
+extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[];
+extern const unsigned RISCVEHFlavour0L2DwarfSize;
+
+RISCVGenRegisterInfo::
+RISCVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
+ unsigned PC, unsigned HwMode)
+ : TargetRegisterInfo(RISCVRegInfoDesc, RegisterClasses, RegisterClasses+12,
+ SubRegIndexNameTable, SubRegIndexLaneMaskTable,
+ LaneBitmask(0xFFFFFFFE), RegClassInfos, HwMode) {
+ InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC,
+ RISCVMCRegisterClasses, 12,
+ RISCVRegUnitRoots,
+ 64,
+ RISCVRegDiffLists,
+ RISCVLaneMaskLists,
+ RISCVRegStrings,
+ RISCVRegClassStrings,
+ RISCVSubRegIdxLists,
+ 2,
+ RISCVSubRegIdxRanges,
+ RISCVRegEncodingTable);
+
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapDwarfRegsToLLVMRegs(RISCVDwarfFlavour0Dwarf2L, RISCVDwarfFlavour0Dwarf2LSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapDwarfRegsToLLVMRegs(RISCVEHFlavour0Dwarf2L, RISCVEHFlavour0Dwarf2LSize, true);
+ break;
+ }
+ switch (DwarfFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapLLVMRegsToDwarfRegs(RISCVDwarfFlavour0L2Dwarf, RISCVDwarfFlavour0L2DwarfSize, false);
+ break;
+ }
+ switch (EHFlavour) {
+ default:
+ llvm_unreachable("Unknown DWARF flavour");
+ case 0:
+ mapLLVMRegsToDwarfRegs(RISCVEHFlavour0L2Dwarf, RISCVEHFlavour0L2DwarfSize, true);
+ break;
+ }
+}
+
+static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 0 };
+static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0x1ff80634, 0x1ff80600, 0x1ff80600, 0x00000000, };
+static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 0 };
+static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0x1ff80634, 0x00000000, 0x1ff80600, 0x00000000, };
+static const MCPhysReg CSR_ILP32_LP64_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, 0 };
+static const uint32_t CSR_ILP32_LP64_RegMask[] = { 0x1ff80634, 0x00000000, 0x00000000, 0x00000000, };
+static const MCPhysReg CSR_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 };
+static const uint32_t CSR_Interrupt_RegMask[] = { 0xfffffff4, 0x00000001, 0x00000000, 0x00000000, };
+static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
+static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
+static const MCPhysReg CSR_XLEN_F32_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 0 };
+static const uint32_t CSR_XLEN_F32_Interrupt_RegMask[] = { 0xfffffff4, 0x00000001, 0xfffffffe, 0x00000001, };
+static const MCPhysReg CSR_XLEN_F64_Interrupt_SaveList[] = { RISCV::X1, RISCV::X3, RISCV::X4, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 0 };
+static const uint32_t CSR_XLEN_F64_Interrupt_RegMask[] = { 0xfffffff4, 0xffffffff, 0xffffffff, 0x00000001, };
+
+
+ArrayRef<const uint32_t *> RISCVGenRegisterInfo::getRegMasks() const {
+ static const uint32_t *const Masks[] = {
+ CSR_ILP32D_LP64D_RegMask,
+ CSR_ILP32F_LP64F_RegMask,
+ CSR_ILP32_LP64_RegMask,
+ CSR_Interrupt_RegMask,
+ CSR_NoRegs_RegMask,
+ CSR_XLEN_F32_Interrupt_RegMask,
+ CSR_XLEN_F64_Interrupt_RegMask,
+ };
+ return makeArrayRef(Masks);
+}
+
+ArrayRef<const char *> RISCVGenRegisterInfo::getRegMaskNames() const {
+ static const char *const Names[] = {
+ "CSR_ILP32D_LP64D",
+ "CSR_ILP32F_LP64F",
+ "CSR_ILP32_LP64",
+ "CSR_Interrupt",
+ "CSR_NoRegs",
+ "CSR_XLEN_F32_Interrupt",
+ "CSR_XLEN_F64_Interrupt",
+ };
+ return makeArrayRef(Names);
+}
+
+const RISCVFrameLowering *
+RISCVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
+ return static_cast<const RISCVFrameLowering *>(
+ MF.getSubtarget().getFrameLowering());
+}
+
+} // end namespace llvm
+
+#endif // GET_REGINFO_TARGET_DESC
+
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenSubtargetInfo.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenSubtargetInfo.inc
new file mode 100644
index 0000000..76ef363
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenSubtargetInfo.inc
@@ -0,0 +1,567 @@
+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
+|* *|
+|* Subtarget Enumeration Source Fragment *|
+|* *|
+|* Automatically generated file, do not edit! *|
+|* *|
+\*===----------------------------------------------------------------------===*/
+
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
+
+namespace llvm {
+namespace RISCV {
+enum {
+ Feature64Bit = 0,
+ FeatureRV32E = 1,
+ FeatureRVCHints = 2,
+ FeatureRelax = 3,
+ FeatureReserveX1 = 4,
+ FeatureReserveX2 = 5,
+ FeatureReserveX3 = 6,
+ FeatureReserveX4 = 7,
+ FeatureReserveX5 = 8,
+ FeatureReserveX6 = 9,
+ FeatureReserveX7 = 10,
+ FeatureReserveX8 = 11,
+ FeatureReserveX9 = 12,
+ FeatureReserveX10 = 13,
+ FeatureReserveX11 = 14,
+ FeatureReserveX12 = 15,
+ FeatureReserveX13 = 16,
+ FeatureReserveX14 = 17,
+ FeatureReserveX15 = 18,
+ FeatureReserveX16 = 19,
+ FeatureReserveX17 = 20,
+ FeatureReserveX18 = 21,
+ FeatureReserveX19 = 22,
+ FeatureReserveX20 = 23,
+ FeatureReserveX21 = 24,
+ FeatureReserveX22 = 25,
+ FeatureReserveX23 = 26,
+ FeatureReserveX24 = 27,
+ FeatureReserveX25 = 28,
+ FeatureReserveX26 = 29,
+ FeatureReserveX27 = 30,
+ FeatureReserveX28 = 31,
+ FeatureReserveX29 = 32,
+ FeatureReserveX30 = 33,
+ FeatureReserveX31 = 34,
+ FeatureStdExtA = 35,
+ FeatureStdExtC = 36,
+ FeatureStdExtD = 37,
+ FeatureStdExtF = 38,
+ FeatureStdExtM = 39,
+ NumSubtargetFeatures = 40
+};
+} // end namespace RISCV
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_ENUM
+
+
+#ifdef GET_SUBTARGETINFO_MC_DESC
+#undef GET_SUBTARGETINFO_MC_DESC
+
+namespace llvm {
+// Sorted (by key) array of values for CPU features.
+extern const llvm::SubtargetFeatureKV RISCVFeatureKV[] = {
+ { "64bit", "Implements RV64", RISCV::Feature64Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "a", "'A' (Atomic Instructions)", RISCV::FeatureStdExtA, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "c", "'C' (Compressed Instructions)", RISCV::FeatureStdExtC, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "d", "'D' (Double-Precision Floating-Point)", RISCV::FeatureStdExtD, { { { 0x4000000000ULL, 0x0ULL, 0x0ULL, } } } },
+ { "e", "Implements RV32E (provides 16 rather than 32 GPRs)", RISCV::FeatureRV32E, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "f", "'F' (Single-Precision Floating-Point)", RISCV::FeatureStdExtF, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "m", "'M' (Integer Multiplication and Division)", RISCV::FeatureStdExtM, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "relax", "Enable Linker relaxation.", RISCV::FeatureRelax, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x1", "Reserve X1", RISCV::FeatureReserveX1, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x10", "Reserve X10", RISCV::FeatureReserveX10, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x11", "Reserve X11", RISCV::FeatureReserveX11, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x12", "Reserve X12", RISCV::FeatureReserveX12, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x13", "Reserve X13", RISCV::FeatureReserveX13, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x14", "Reserve X14", RISCV::FeatureReserveX14, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x15", "Reserve X15", RISCV::FeatureReserveX15, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x16", "Reserve X16", RISCV::FeatureReserveX16, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x17", "Reserve X17", RISCV::FeatureReserveX17, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x18", "Reserve X18", RISCV::FeatureReserveX18, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x19", "Reserve X19", RISCV::FeatureReserveX19, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x2", "Reserve X2", RISCV::FeatureReserveX2, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x20", "Reserve X20", RISCV::FeatureReserveX20, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x21", "Reserve X21", RISCV::FeatureReserveX21, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x22", "Reserve X22", RISCV::FeatureReserveX22, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x23", "Reserve X23", RISCV::FeatureReserveX23, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x24", "Reserve X24", RISCV::FeatureReserveX24, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x25", "Reserve X25", RISCV::FeatureReserveX25, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x26", "Reserve X26", RISCV::FeatureReserveX26, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x27", "Reserve X27", RISCV::FeatureReserveX27, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x28", "Reserve X28", RISCV::FeatureReserveX28, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x29", "Reserve X29", RISCV::FeatureReserveX29, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x3", "Reserve X3", RISCV::FeatureReserveX3, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x30", "Reserve X30", RISCV::FeatureReserveX30, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x31", "Reserve X31", RISCV::FeatureReserveX31, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x4", "Reserve X4", RISCV::FeatureReserveX4, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x5", "Reserve X5", RISCV::FeatureReserveX5, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x6", "Reserve X6", RISCV::FeatureReserveX6, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x7", "Reserve X7", RISCV::FeatureReserveX7, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x8", "Reserve X8", RISCV::FeatureReserveX8, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "reserve-x9", "Reserve X9", RISCV::FeatureReserveX9, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+ { "rvc-hints", "Enable RVC Hint Instructions.", RISCV::FeatureRVCHints, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
+};
+
+#ifdef DBGFIELD
+#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
+#endif
+#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
+#define DBGFIELD(x) x,
+#else
+#define DBGFIELD(x)
+#endif
+
+// ===============================================================
+// Data tables for the new per-operand machine model.
+
+// {ProcResourceIdx, Cycles}
+extern const llvm::MCWriteProcResEntry RISCVWriteProcResTable[] = {
+ { 0, 0}, // Invalid
+ { 1, 1}, // #1
+ { 7, 1}, // #2
+ { 2, 1}, // #3
+ { 5, 34}, // #4
+ { 3, 1}, // #5
+ { 4, 20}, // #6
+ { 6, 1}, // #7
+ { 8, 1}, // #8
+ { 6, 33}, // #9
+ { 6, 34}, // #10
+ { 4, 1}, // #11
+ { 5, 20} // #12
+}; // RISCVWriteProcResTable
+
+// {Cycles, WriteResourceID}
+extern const llvm::MCWriteLatencyEntry RISCVWriteLatencyTable[] = {
+ { 0, 0}, // Invalid
+ { 1, 0}, // #1 WriteIALU_WriteJmp_WriteFST64_WriteFST32_WriteJal_WriteJalr_WriteJmpReg_WriteNop_WriteShift_WriteSTW_WriteSTB_WriteAtomicSTW_WriteSTH_WriteIALU32_WriteSTD_WriteAtomicSTD_WriteShift32
+ { 2, 0}, // #2 WriteAtomicW_WriteFLD64_WriteFLD32_WriteLDW_WriteFClass64_WriteFClass32_WriteFCvtF32ToF64_WriteFCvtI32ToF64_WriteFCvtF64ToF32_WriteFCvtI32ToF32_WriteFCvtF64ToI32_WriteFCvtF32ToI32_WriteFCmp64_WriteFCmp32_WriteFMovI32ToF32_WriteFMovF32ToI32_WriteAtomicLDW_WriteAtomicD_WriteLDD_WriteFCvtI64ToF64_WriteFCvtF64ToI64_WriteFCvtF32ToI64_WriteFCvtI64ToF32_WriteFMovI64ToF64_WriteFMovF64ToI64_WriteAtomicLDD_WriteLDWU
+ { 3, 0}, // #3 WriteCSR_WriteLDB_WriteLDH
+ {34, 0}, // #4 WriteIDiv_WriteIDiv32
+ { 6, 0}, // #5 WriteFALU64
+ { 4, 0}, // #6 WriteFALU32_WriteIMul_WriteIMul32
+ {20, 0}, // #7 WriteFDiv32_WriteFSqrt32
+ { 7, 0}, // #8 WriteFMulAdd64_WriteFMulSub64
+ { 5, 0}, // #9 WriteFMulAdd32_WriteFMulSub32_WriteFMul32
+ {33, 0} // #10 WriteIDiv
+}; // RISCVWriteLatencyTable
+
+// {UseIdx, WriteResourceID, Cycles}
+extern const llvm::MCReadAdvanceEntry RISCVReadAdvanceTable[] = {
+ {0, 0, 0}, // Invalid
+ {0, 0, 0}, // #1
+ {1, 0, 0}, // #2
+ {0, 0, 0}, // #3
+ {1, 0, 0}, // #4
+ {2, 0, 0} // #5
+}; // RISCVReadAdvanceTable
+
+// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
+static const llvm::MCSchedClassDesc Rocket32ModelSchedClasses[] = {
+ {DBGFIELD("InvalidSchedClass") 16383, false, false, 0, 0, 0, 0, 0, 0},
+ {DBGFIELD("WriteIALU_ReadIALU_ReadIALU") 1, false, false, 1, 1, 1, 1, 1, 2}, // #1
+ {DBGFIELD("WriteIALU_ReadIALU") 1, false, false, 1, 1, 1, 1, 0, 1}, // #2
+ {DBGFIELD("WriteIALU32_ReadIALU32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #3
+ {DBGFIELD("WriteIALU32_ReadIALU32_ReadIALU32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #4
+ {DBGFIELD("WriteAtomicD_ReadAtomicDA_ReadAtomicDD") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #5
+ {DBGFIELD("WriteAtomicW_ReadAtomicWA_ReadAtomicWD") 1, false, false, 2, 1, 2, 1, 1, 2}, // #6
+ {DBGFIELD("WriteIALU") 1, false, false, 1, 1, 1, 1, 0, 0}, // #7
+ {DBGFIELD("WriteJmp") 1, false, false, 3, 1, 1, 1, 0, 0}, // #8
+ {DBGFIELD("WriteCSR_ReadCSR") 1, false, false, 1, 1, 3, 1, 0, 1}, // #9
+ {DBGFIELD("WriteCSR") 1, false, false, 1, 1, 3, 1, 0, 0}, // #10
+ {DBGFIELD("WriteFLD64_ReadMemBase") 1, false, false, 2, 1, 2, 1, 0, 1}, // #11
+ {DBGFIELD("WriteFLD32_ReadMemBase") 1, false, false, 2, 1, 2, 1, 0, 1}, // #12
+ {DBGFIELD("WriteFST64_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #13
+ {DBGFIELD("WriteFST32_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #14
+ {DBGFIELD("WriteJal") 1, false, false, 3, 1, 1, 1, 0, 0}, // #15
+ {DBGFIELD("WriteJalr_ReadJalr") 1, false, false, 3, 1, 1, 1, 0, 1}, // #16
+ {DBGFIELD("WriteJmpReg") 1, false, false, 3, 1, 1, 1, 0, 0}, // #17
+ {DBGFIELD("WriteLDD_ReadMemBase") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #18
+ {DBGFIELD("WriteLDW_ReadMemBase") 1, false, false, 2, 1, 2, 1, 0, 1}, // #19
+ {DBGFIELD("WriteNop") 1, false, false, 0, 0, 1, 1, 0, 0}, // #20
+ {DBGFIELD("WriteSTD_ReadStoreData_ReadMemBase") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #21
+ {DBGFIELD("WriteShift_ReadShift") 1, false, false, 1, 1, 1, 1, 0, 1}, // #22
+ {DBGFIELD("WriteSTW_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #23
+ {DBGFIELD("WriteIDiv_ReadIDiv_ReadIDiv") 1, false, false, 4, 1, 4, 1, 1, 2}, // #24
+ {DBGFIELD("WriteIDiv32_ReadIDiv32_ReadIDiv32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #25
+ {DBGFIELD("WriteFALU64_ReadFALU64_ReadFALU64") 1, false, false, 5, 1, 5, 1, 1, 2}, // #26
+ {DBGFIELD("WriteFALU32_ReadFALU32_ReadFALU32") 1, false, false, 5, 1, 6, 1, 1, 2}, // #27
+ {DBGFIELD("WriteFClass64_ReadFClass64") 1, false, false, 5, 1, 2, 1, 0, 1}, // #28
+ {DBGFIELD("WriteFClass32_ReadFClass32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #29
+ {DBGFIELD("WriteFCvtI64ToF64_ReadFCvtI64ToF64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #30
+ {DBGFIELD("WriteFCvtF32ToF64_ReadFCvtF32ToF64") 1, false, false, 5, 1, 2, 1, 0, 1}, // #31
+ {DBGFIELD("WriteFCvtI32ToF64_ReadFCvtI32ToF64") 1, false, false, 5, 1, 2, 1, 0, 1}, // #32
+ {DBGFIELD("WriteFCvtF64ToI64_ReadFCvtF64ToI64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #33
+ {DBGFIELD("WriteFCvtF32ToI64_ReadFCvtF32ToI64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #34
+ {DBGFIELD("WriteFCvtF64ToF32_ReadFCvtF64ToF32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #35
+ {DBGFIELD("WriteFCvtI64ToF32_ReadFCvtI64ToF32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #36
+ {DBGFIELD("WriteFCvtI32ToF32_ReadFCvtI32ToF32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #37
+ {DBGFIELD("WriteFCvtF64ToI32_ReadFCvtF64ToI32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #38
+ {DBGFIELD("WriteFCvtF32ToI32_ReadFCvtF32ToI32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #39
+ {DBGFIELD("WriteFDiv32_ReadFDiv32_ReadFDiv32") 1, false, false, 6, 1, 7, 1, 1, 2}, // #40
+ {DBGFIELD("WriteFCmp64_ReadFCmp64_ReadFCmp64") 1, false, false, 5, 1, 2, 1, 1, 2}, // #41
+ {DBGFIELD("WriteFCmp32_ReadFCmp32_ReadFCmp32") 1, false, false, 5, 1, 2, 1, 1, 2}, // #42
+ {DBGFIELD("WriteFMulAdd64_ReadFMulAdd64_ReadFMulAdd64_ReadFMulAdd64") 1, false, false, 5, 1, 8, 1, 3, 3}, // #43
+ {DBGFIELD("WriteFMulAdd32_ReadFMulAdd32_ReadFMulAdd32_ReadFMulAdd32") 1, false, false, 5, 1, 9, 1, 3, 3}, // #44
+ {DBGFIELD("WriteFMulSub64_ReadFMulSub64_ReadFMulSub64_ReadFMulSub64") 1, false, false, 5, 1, 8, 1, 3, 3}, // #45
+ {DBGFIELD("WriteFMulSub32_ReadFMulSub32_ReadFMulSub32_ReadFMulSub32") 1, false, false, 5, 1, 9, 1, 3, 3}, // #46
+ {DBGFIELD("WriteFMul32_ReadFMul32_ReadFMul32") 1, false, false, 5, 1, 9, 1, 1, 2}, // #47
+ {DBGFIELD("WriteFMovI64ToF64_ReadFMovI64ToF64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #48
+ {DBGFIELD("WriteFMovI32ToF32_ReadFMovI32ToF32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #49
+ {DBGFIELD("WriteFMovF64ToI64_ReadFMovF64ToI64") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #50
+ {DBGFIELD("WriteFMovF32ToI32_ReadFMovF32ToI32") 1, false, false, 5, 1, 2, 1, 0, 1}, // #51
+ {DBGFIELD("WriteFSqrt32_ReadFSqrt32") 1, false, false, 6, 1, 7, 1, 0, 1}, // #52
+ {DBGFIELD("WriteLDB_ReadMemBase") 1, false, false, 2, 1, 3, 1, 0, 1}, // #53
+ {DBGFIELD("WriteLDH_ReadMemBase") 1, false, false, 2, 1, 3, 1, 0, 1}, // #54
+ {DBGFIELD("WriteAtomicLDD_ReadAtomicLDD") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #55
+ {DBGFIELD("WriteAtomicLDW_ReadAtomicLDW") 1, false, false, 2, 1, 2, 1, 0, 1}, // #56
+ {DBGFIELD("WriteLDWU_ReadMemBase") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #57
+ {DBGFIELD("WriteIMul_ReadIMul_ReadIMul") 1, false, false, 7, 1, 6, 1, 1, 2}, // #58
+ {DBGFIELD("WriteIMul32_ReadIMul32_ReadIMul32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #59
+ {DBGFIELD("WriteSTB_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #60
+ {DBGFIELD("WriteAtomicSTD_ReadAtomicSTD_ReadAtomicSTD") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #61
+ {DBGFIELD("WriteAtomicSTW_ReadAtomicSTW_ReadAtomicSTW") 1, false, false, 2, 1, 1, 1, 1, 2}, // #62
+ {DBGFIELD("WriteSTH_ReadStoreData_ReadMemBase") 1, false, false, 2, 1, 1, 1, 1, 2}, // #63
+ {DBGFIELD("WriteShift32_ReadShift32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #64
+ {DBGFIELD("COPY") 1, false, false, 1, 1, 1, 1, 0, 0}, // #65
+}; // Rocket32ModelSchedClasses
+
+// {Name, NumMicroOps, BeginGroup, EndGroup, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
+static const llvm::MCSchedClassDesc Rocket64ModelSchedClasses[] = {
+ {DBGFIELD("InvalidSchedClass") 16383, false, false, 0, 0, 0, 0, 0, 0},
+ {DBGFIELD("WriteIALU_ReadIALU_ReadIALU") 1, false, false, 3, 1, 1, 1, 1, 2}, // #1
+ {DBGFIELD("WriteIALU_ReadIALU") 1, false, false, 3, 1, 1, 1, 0, 1}, // #2
+ {DBGFIELD("WriteIALU32_ReadIALU32") 1, false, false, 3, 1, 1, 1, 0, 1}, // #3
+ {DBGFIELD("WriteIALU32_ReadIALU32_ReadIALU32") 1, false, false, 3, 1, 1, 1, 1, 2}, // #4
+ {DBGFIELD("WriteAtomicD_ReadAtomicDA_ReadAtomicDD") 1, false, false, 8, 1, 2, 1, 1, 2}, // #5
+ {DBGFIELD("WriteAtomicW_ReadAtomicWA_ReadAtomicWD") 1, false, false, 8, 1, 2, 1, 1, 2}, // #6
+ {DBGFIELD("WriteIALU") 1, false, false, 3, 1, 1, 1, 0, 0}, // #7
+ {DBGFIELD("WriteJmp") 1, false, false, 5, 1, 1, 1, 0, 0}, // #8
+ {DBGFIELD("WriteCSR_ReadCSR") 1, false, false, 3, 1, 3, 1, 0, 1}, // #9
+ {DBGFIELD("WriteCSR") 1, false, false, 3, 1, 3, 1, 0, 0}, // #10
+ {DBGFIELD("WriteFLD64_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #11
+ {DBGFIELD("WriteFLD32_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #12
+ {DBGFIELD("WriteFST64_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #13
+ {DBGFIELD("WriteFST32_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #14
+ {DBGFIELD("WriteJal") 1, false, false, 5, 1, 1, 1, 0, 0}, // #15
+ {DBGFIELD("WriteJalr_ReadJalr") 1, false, false, 5, 1, 1, 1, 0, 1}, // #16
+ {DBGFIELD("WriteJmpReg") 1, false, false, 5, 1, 1, 1, 0, 0}, // #17
+ {DBGFIELD("WriteLDD_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #18
+ {DBGFIELD("WriteLDW_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #19
+ {DBGFIELD("WriteNop") 1, false, false, 0, 0, 1, 1, 0, 0}, // #20
+ {DBGFIELD("WriteSTD_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #21
+ {DBGFIELD("WriteShift_ReadShift") 1, false, false, 3, 1, 1, 1, 0, 1}, // #22
+ {DBGFIELD("WriteSTW_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #23
+ {DBGFIELD("WriteIDiv_ReadIDiv_ReadIDiv") 1, false, false, 9, 1, 10, 1, 1, 2}, // #24
+ {DBGFIELD("WriteIDiv32_ReadIDiv32_ReadIDiv32") 1, false, false, 10, 1, 4, 1, 1, 2}, // #25
+ {DBGFIELD("WriteFALU64_ReadFALU64_ReadFALU64") 1, false, false, 11, 1, 5, 1, 1, 2}, // #26
+ {DBGFIELD("WriteFALU32_ReadFALU32_ReadFALU32") 1, false, false, 11, 1, 6, 1, 1, 2}, // #27
+ {DBGFIELD("WriteFClass64_ReadFClass64") 1, false, false, 11, 1, 2, 1, 0, 1}, // #28
+ {DBGFIELD("WriteFClass32_ReadFClass32") 1, false, false, 11, 1, 2, 1, 0, 1}, // #29
+ {DBGFIELD("WriteFCvtI64ToF64_ReadFCvtI64ToF64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #30
+ {DBGFIELD("WriteFCvtF32ToF64_ReadFCvtF32ToF64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #31
+ {DBGFIELD("WriteFCvtI32ToF64_ReadFCvtI32ToF64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #32
+ {DBGFIELD("WriteFCvtF64ToI64_ReadFCvtF64ToI64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #33
+ {DBGFIELD("WriteFCvtF32ToI64_ReadFCvtF32ToI64") 1, false, false, 1, 1, 2, 1, 0, 1}, // #34
+ {DBGFIELD("WriteFCvtF64ToF32_ReadFCvtF64ToF32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #35
+ {DBGFIELD("WriteFCvtI64ToF32_ReadFCvtI64ToF32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #36
+ {DBGFIELD("WriteFCvtI32ToF32_ReadFCvtI32ToF32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #37
+ {DBGFIELD("WriteFCvtF64ToI32_ReadFCvtF64ToI32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #38
+ {DBGFIELD("WriteFCvtF32ToI32_ReadFCvtF32ToI32") 1, false, false, 1, 1, 2, 1, 0, 1}, // #39
+ {DBGFIELD("WriteFDiv32_ReadFDiv32_ReadFDiv32") 1, false, false, 12, 1, 7, 1, 1, 2}, // #40
+ {DBGFIELD("WriteFCmp64_ReadFCmp64_ReadFCmp64") 1, false, false, 11, 1, 2, 1, 1, 2}, // #41
+ {DBGFIELD("WriteFCmp32_ReadFCmp32_ReadFCmp32") 1, false, false, 11, 1, 2, 1, 1, 2}, // #42
+ {DBGFIELD("WriteFMulAdd64_ReadFMulAdd64_ReadFMulAdd64_ReadFMulAdd64") 1, false, false, 11, 1, 8, 1, 3, 3}, // #43
+ {DBGFIELD("WriteFMulAdd32_ReadFMulAdd32_ReadFMulAdd32_ReadFMulAdd32") 1, false, false, 11, 1, 9, 1, 3, 3}, // #44
+ {DBGFIELD("WriteFMulSub64_ReadFMulSub64_ReadFMulSub64_ReadFMulSub64") 1, false, false, 11, 1, 8, 1, 3, 3}, // #45
+ {DBGFIELD("WriteFMulSub32_ReadFMulSub32_ReadFMulSub32_ReadFMulSub32") 1, false, false, 11, 1, 9, 1, 3, 3}, // #46
+ {DBGFIELD("WriteFMul32_ReadFMul32_ReadFMul32") 1, false, false, 11, 1, 9, 1, 1, 2}, // #47
+ {DBGFIELD("WriteFMovI64ToF64_ReadFMovI64ToF64") 1, false, false, 11, 1, 2, 1, 0, 1}, // #48
+ {DBGFIELD("WriteFMovI32ToF32_ReadFMovI32ToF32") 1, false, false, 11, 1, 2, 1, 0, 1}, // #49
+ {DBGFIELD("WriteFMovF64ToI64_ReadFMovF64ToI64") 1, false, false, 11, 1, 2, 1, 0, 1}, // #50
+ {DBGFIELD("WriteFMovF32ToI32_ReadFMovF32ToI32") 1, false, false, 11, 1, 2, 1, 0, 1}, // #51
+ {DBGFIELD("WriteFSqrt32_ReadFSqrt32") 1, false, false, 12, 1, 7, 1, 0, 1}, // #52
+ {DBGFIELD("WriteLDB_ReadMemBase") 1, false, false, 8, 1, 3, 1, 0, 1}, // #53
+ {DBGFIELD("WriteLDH_ReadMemBase") 1, false, false, 8, 1, 3, 1, 0, 1}, // #54
+ {DBGFIELD("WriteAtomicLDD_ReadAtomicLDD") 1, false, false, 8, 1, 2, 1, 0, 1}, // #55
+ {DBGFIELD("WriteAtomicLDW_ReadAtomicLDW") 1, false, false, 8, 1, 2, 1, 0, 1}, // #56
+ {DBGFIELD("WriteLDWU_ReadMemBase") 1, false, false, 8, 1, 2, 1, 0, 1}, // #57
+ {DBGFIELD("WriteIMul_ReadIMul_ReadIMul") 1, false, false, 2, 1, 6, 1, 1, 2}, // #58
+ {DBGFIELD("WriteIMul32_ReadIMul32_ReadIMul32") 1, false, false, 2, 1, 6, 1, 1, 2}, // #59
+ {DBGFIELD("WriteSTB_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #60
+ {DBGFIELD("WriteAtomicSTD_ReadAtomicSTD_ReadAtomicSTD") 1, false, false, 8, 1, 1, 1, 1, 2}, // #61
+ {DBGFIELD("WriteAtomicSTW_ReadAtomicSTW_ReadAtomicSTW") 1, false, false, 8, 1, 1, 1, 1, 2}, // #62
+ {DBGFIELD("WriteSTH_ReadStoreData_ReadMemBase") 1, false, false, 8, 1, 1, 1, 1, 2}, // #63
+ {DBGFIELD("WriteShift32_ReadShift32") 1, false, false, 3, 1, 1, 1, 0, 1}, // #64
+ {DBGFIELD("COPY") 1, false, false, 3, 1, 1, 1, 0, 0}, // #65
+}; // Rocket64ModelSchedClasses
+
+#undef DBGFIELD
+
+static const llvm::MCSchedModel NoSchedModel = {
+ MCSchedModel::DefaultIssueWidth,
+ MCSchedModel::DefaultMicroOpBufferSize,
+ MCSchedModel::DefaultLoopMicroOpBufferSize,
+ MCSchedModel::DefaultLoadLatency,
+ MCSchedModel::DefaultHighLatency,
+ MCSchedModel::DefaultMispredictPenalty,
+ false, // PostRAScheduler
+ false, // CompleteModel
+ 0, // Processor ID
+ nullptr, nullptr, 0, 0, // No instruction-level machine model.
+ nullptr, // No Itinerary
+ nullptr // No extra processor descriptor
+};
+
+static const unsigned Rocket32ModelProcResourceSubUnits[] = {
+ 0, // Invalid
+};
+
+// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
+static const llvm::MCProcResourceDesc Rocket32ModelProcResources[] = {
+ {"InvalidUnit", 0, 0, 0, 0},
+ {"Rocket32UnitALU", 1, 0, 0, nullptr}, // #1
+ {"Rocket32UnitB", 1, 0, 0, nullptr}, // #2
+ {"Rocket32UnitFPALU", 1, 0, 0, nullptr}, // #3
+ {"Rocket32UnitFPDivSqrt", 1, 0, 1, nullptr}, // #4
+ {"Rocket32UnitIDiv", 1, 0, 1, nullptr}, // #5
+ {"Rocket32UnitIMul", 1, 0, 0, nullptr}, // #6
+ {"Rocket32UnitMem", 1, 0, 0, nullptr}, // #7
+};
+
+static const llvm::MCSchedModel Rocket32Model = {
+ 1, // IssueWidth
+ 0, // MicroOpBufferSize
+ MCSchedModel::DefaultLoopMicroOpBufferSize,
+ 3, // LoadLatency
+ MCSchedModel::DefaultHighLatency,
+ 3, // MispredictPenalty
+ false, // PostRAScheduler
+ true, // CompleteModel
+ 1, // Processor ID
+ Rocket32ModelProcResources,
+ Rocket32ModelSchedClasses,
+ 8,
+ 66,
+ nullptr, // No Itinerary
+ nullptr // No extra processor descriptor
+};
+
+static const unsigned Rocket64ModelProcResourceSubUnits[] = {
+ 0, // Invalid
+};
+
+// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
+static const llvm::MCProcResourceDesc Rocket64ModelProcResources[] = {
+ {"InvalidUnit", 0, 0, 0, 0},
+ {"Rocket32UnitFPALU", 1, 0, 0, nullptr}, // #1
+ {"Rocket64UnitALU", 1, 0, 0, nullptr}, // #2
+ {"Rocket64UnitB", 1, 0, 0, nullptr}, // #3
+ {"Rocket64UnitFPALU", 1, 0, 0, nullptr}, // #4
+ {"Rocket64UnitFPDivSqrt", 1, 0, 1, nullptr}, // #5
+ {"Rocket64UnitIDiv", 1, 0, 1, nullptr}, // #6
+ {"Rocket64UnitIMul", 1, 0, 0, nullptr}, // #7
+ {"Rocket64UnitMem", 1, 0, 0, nullptr}, // #8
+};
+
+static const llvm::MCSchedModel Rocket64Model = {
+ 1, // IssueWidth
+ 0, // MicroOpBufferSize
+ MCSchedModel::DefaultLoopMicroOpBufferSize,
+ 3, // LoadLatency
+ MCSchedModel::DefaultHighLatency,
+ 3, // MispredictPenalty
+ false, // PostRAScheduler
+ true, // CompleteModel
+ 2, // Processor ID
+ Rocket64ModelProcResources,
+ Rocket64ModelSchedClasses,
+ 9,
+ 66,
+ nullptr, // No Itinerary
+ nullptr // No extra processor descriptor
+};
+
+// Sorted (by key) array of values for CPU subtype.
+extern const llvm::SubtargetSubTypeKV RISCVSubTypeKV[] = {
+ { "generic-rv32", { { { 0x4ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
+ { "generic-rv64", { { { 0x5ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },
+ { "rocket-rv32", { { { 0x4ULL, 0x0ULL, 0x0ULL, } } }, &Rocket32Model },
+ { "rocket-rv64", { { { 0x5ULL, 0x0ULL, 0x0ULL, } } }, &Rocket64Model },
+};
+
+namespace RISCV_MC {
+unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
+ const MCInst *MI, unsigned CPUID) {
+ // Don't know how to resolve this scheduling class.
+ return 0;
+}
+} // end namespace RISCV_MC
+
+struct RISCVGenMCSubtargetInfo : public MCSubtargetInfo {
+ RISCVGenMCSubtargetInfo(const Triple &TT,
+ StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
+ ArrayRef<SubtargetSubTypeKV> PD,
+ const MCWriteProcResEntry *WPR,
+ const MCWriteLatencyEntry *WL,
+ const MCReadAdvanceEntry *RA, const InstrStage *IS,
+ const unsigned *OC, const unsigned *FP) :
+ MCSubtargetInfo(TT, CPU, FS, PF, PD,
+ WPR, WL, RA, IS, OC, FP) { }
+
+ unsigned resolveVariantSchedClass(unsigned SchedClass,
+ const MCInst *MI, unsigned CPUID) const override {
+ return RISCV_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
+ }
+ unsigned getHwMode() const override;
+};
+unsigned RISCVGenMCSubtargetInfo::getHwMode() const {
+ if (checkFeatures("-64bit")) return 1;
+ if (checkFeatures("+64bit")) return 2;
+ return 0;
+}
+
+static inline MCSubtargetInfo *createRISCVMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef FS) {
+ return new RISCVGenMCSubtargetInfo(TT, CPU, FS, RISCVFeatureKV, RISCVSubTypeKV,
+ RISCVWriteProcResTable, RISCVWriteLatencyTable, RISCVReadAdvanceTable,
+ nullptr, nullptr, nullptr);
+}
+
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_MC_DESC
+
+
+#ifdef GET_SUBTARGETINFO_TARGET_DESC
+#undef GET_SUBTARGETINFO_TARGET_DESC
+
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+// ParseSubtargetFeatures - Parses features string setting specified
+// subtarget options.
+void llvm::RISCVSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {
+ LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
+ LLVM_DEBUG(dbgs() << "\nCPU:" << CPU << "\n\n");
+ InitMCProcessorInfo(CPU, FS);
+ const FeatureBitset& Bits = getFeatureBits();
+ if (Bits[RISCV::Feature64Bit]) HasRV64 = true;
+ if (Bits[RISCV::FeatureRV32E]) IsRV32E = true;
+ if (Bits[RISCV::FeatureRVCHints]) EnableRVCHintInstrs = true;
+ if (Bits[RISCV::FeatureRelax]) EnableLinkerRelax = true;
+ if (Bits[RISCV::FeatureReserveX1]) UserReservedRegister[RISCV::X1] = true;
+ if (Bits[RISCV::FeatureReserveX2]) UserReservedRegister[RISCV::X2] = true;
+ if (Bits[RISCV::FeatureReserveX3]) UserReservedRegister[RISCV::X3] = true;
+ if (Bits[RISCV::FeatureReserveX4]) UserReservedRegister[RISCV::X4] = true;
+ if (Bits[RISCV::FeatureReserveX5]) UserReservedRegister[RISCV::X5] = true;
+ if (Bits[RISCV::FeatureReserveX6]) UserReservedRegister[RISCV::X6] = true;
+ if (Bits[RISCV::FeatureReserveX7]) UserReservedRegister[RISCV::X7] = true;
+ if (Bits[RISCV::FeatureReserveX8]) UserReservedRegister[RISCV::X8] = true;
+ if (Bits[RISCV::FeatureReserveX9]) UserReservedRegister[RISCV::X9] = true;
+ if (Bits[RISCV::FeatureReserveX10]) UserReservedRegister[RISCV::X10] = true;
+ if (Bits[RISCV::FeatureReserveX11]) UserReservedRegister[RISCV::X11] = true;
+ if (Bits[RISCV::FeatureReserveX12]) UserReservedRegister[RISCV::X12] = true;
+ if (Bits[RISCV::FeatureReserveX13]) UserReservedRegister[RISCV::X13] = true;
+ if (Bits[RISCV::FeatureReserveX14]) UserReservedRegister[RISCV::X14] = true;
+ if (Bits[RISCV::FeatureReserveX15]) UserReservedRegister[RISCV::X15] = true;
+ if (Bits[RISCV::FeatureReserveX16]) UserReservedRegister[RISCV::X16] = true;
+ if (Bits[RISCV::FeatureReserveX17]) UserReservedRegister[RISCV::X17] = true;
+ if (Bits[RISCV::FeatureReserveX18]) UserReservedRegister[RISCV::X18] = true;
+ if (Bits[RISCV::FeatureReserveX19]) UserReservedRegister[RISCV::X19] = true;
+ if (Bits[RISCV::FeatureReserveX20]) UserReservedRegister[RISCV::X20] = true;
+ if (Bits[RISCV::FeatureReserveX21]) UserReservedRegister[RISCV::X21] = true;
+ if (Bits[RISCV::FeatureReserveX22]) UserReservedRegister[RISCV::X22] = true;
+ if (Bits[RISCV::FeatureReserveX23]) UserReservedRegister[RISCV::X23] = true;
+ if (Bits[RISCV::FeatureReserveX24]) UserReservedRegister[RISCV::X24] = true;
+ if (Bits[RISCV::FeatureReserveX25]) UserReservedRegister[RISCV::X25] = true;
+ if (Bits[RISCV::FeatureReserveX26]) UserReservedRegister[RISCV::X26] = true;
+ if (Bits[RISCV::FeatureReserveX27]) UserReservedRegister[RISCV::X27] = true;
+ if (Bits[RISCV::FeatureReserveX28]) UserReservedRegister[RISCV::X28] = true;
+ if (Bits[RISCV::FeatureReserveX29]) UserReservedRegister[RISCV::X29] = true;
+ if (Bits[RISCV::FeatureReserveX30]) UserReservedRegister[RISCV::X30] = true;
+ if (Bits[RISCV::FeatureReserveX31]) UserReservedRegister[RISCV::X31] = true;
+ if (Bits[RISCV::FeatureStdExtA]) HasStdExtA = true;
+ if (Bits[RISCV::FeatureStdExtC]) HasStdExtC = true;
+ if (Bits[RISCV::FeatureStdExtD]) HasStdExtD = true;
+ if (Bits[RISCV::FeatureStdExtF]) HasStdExtF = true;
+ if (Bits[RISCV::FeatureStdExtM]) HasStdExtM = true;
+}
+#endif // GET_SUBTARGETINFO_TARGET_DESC
+
+
+#ifdef GET_SUBTARGETINFO_HEADER
+#undef GET_SUBTARGETINFO_HEADER
+
+namespace llvm {
+class DFAPacketizer;
+namespace RISCV_MC {
+unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, unsigned CPUID);
+} // end namespace RISCV_MC
+
+struct RISCVGenSubtargetInfo : public TargetSubtargetInfo {
+ explicit RISCVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS);
+public:
+ unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
+ unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const override;
+ DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
+ unsigned getHwMode() const override;
+};
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_HEADER
+
+
+#ifdef GET_SUBTARGETINFO_CTOR
+#undef GET_SUBTARGETINFO_CTOR
+
+#include "llvm/CodeGen/TargetSchedule.h"
+
+namespace llvm {
+extern const llvm::SubtargetFeatureKV RISCVFeatureKV[];
+extern const llvm::SubtargetSubTypeKV RISCVSubTypeKV[];
+extern const llvm::MCWriteProcResEntry RISCVWriteProcResTable[];
+extern const llvm::MCWriteLatencyEntry RISCVWriteLatencyTable[];
+extern const llvm::MCReadAdvanceEntry RISCVReadAdvanceTable[];
+RISCVGenSubtargetInfo::RISCVGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
+ : TargetSubtargetInfo(TT, CPU, FS, makeArrayRef(RISCVFeatureKV, 40), makeArrayRef(RISCVSubTypeKV, 4),
+ RISCVWriteProcResTable, RISCVWriteLatencyTable, RISCVReadAdvanceTable,
+ nullptr, nullptr, nullptr) {}
+
+unsigned RISCVGenSubtargetInfo
+::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
+ report_fatal_error("Expected a variant SchedClass");
+} // RISCVGenSubtargetInfo::resolveSchedClass
+
+unsigned RISCVGenSubtargetInfo
+::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, unsigned CPUID) const {
+ return RISCV_MC::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);
+} // RISCVGenSubtargetInfo::resolveVariantSchedClass
+
+unsigned RISCVGenSubtargetInfo::getHwMode() const {
+ if (checkFeatures("-64bit")) return 1;
+ if (checkFeatures("+64bit")) return 2;
+ return 0;
+}
+} // end namespace llvm
+
+#endif // GET_SUBTARGETINFO_CTOR
+
+
+#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
+#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
+
+#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
+
+
+#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
+#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
+
+#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
+
diff --git a/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenSystemOperands.inc b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenSystemOperands.inc
new file mode 100644
index 0000000..eec53d1
--- /dev/null
+++ b/third_party/llvm-10.0/configs/common/lib/Target/RISCV/RISCVGenSystemOperands.inc
@@ -0,0 +1,502 @@
+#ifdef GET_SysRegsList_DECL
+const SysReg *lookupSysRegByEncoding(uint16_t Encoding);
+const SysReg *lookupSysRegByName(StringRef Name);
+#endif
+
+#ifdef GET_SysRegsList_IMPL
+constexpr SysReg SysRegsList[] = {
+ { "ustatus", 0x0, {} , false }, // 0
+ { "fflags", 0x1, {} , false }, // 1
+ { "frm", 0x2, {} , false }, // 2
+ { "fcsr", 0x3, {} , false }, // 3
+ { "uie", 0x4, {} , false }, // 4
+ { "utvec", 0x5, {} , false }, // 5
+ { "uscratch", 0x40, {} , false }, // 6
+ { "uepc", 0x41, {} , false }, // 7
+ { "ucause", 0x42, {} , false }, // 8
+ { "utval", 0x43, {} , false }, // 9
+ { "uip", 0x44, {} , false }, // 10
+ { "sstatus", 0x100, {} , false }, // 11
+ { "sedeleg", 0x102, {} , false }, // 12
+ { "sideleg", 0x103, {} , false }, // 13
+ { "sie", 0x104, {} , false }, // 14
+ { "stvec", 0x105, {} , false }, // 15
+ { "scounteren", 0x106, {} , false }, // 16
+ { "sscratch", 0x140, {} , false }, // 17
+ { "sepc", 0x141, {} , false }, // 18
+ { "scause", 0x142, {} , false }, // 19
+ { "stval", 0x143, {} , false }, // 20
+ { "sip", 0x144, {} , false }, // 21
+ { "satp", 0x180, {} , false }, // 22
+ { "mstatus", 0x300, {} , false }, // 23
+ { "misa", 0x301, {} , false }, // 24
+ { "medeleg", 0x302, {} , false }, // 25
+ { "mideleg", 0x303, {} , false }, // 26
+ { "mie", 0x304, {} , false }, // 27
+ { "mtvec", 0x305, {} , false }, // 28
+ { "mcounteren", 0x306, {} , false }, // 29
+ { "mhpmevent3", 0x323, {} , false }, // 30
+ { "mhpmevent4", 0x324, {} , false }, // 31
+ { "mhpmevent5", 0x325, {} , false }, // 32
+ { "mhpmevent6", 0x326, {} , false }, // 33
+ { "mhpmevent7", 0x327, {} , false }, // 34
+ { "mhpmevent8", 0x328, {} , false }, // 35
+ { "mhpmevent9", 0x329, {} , false }, // 36
+ { "mhpmevent10", 0x32A, {} , false }, // 37
+ { "mhpmevent11", 0x32B, {} , false }, // 38
+ { "mhpmevent12", 0x32C, {} , false }, // 39
+ { "mhpmevent13", 0x32D, {} , false }, // 40
+ { "mhpmevent14", 0x32E, {} , false }, // 41
+ { "mhpmevent15", 0x32F, {} , false }, // 42
+ { "mhpmevent16", 0x330, {} , false }, // 43
+ { "mhpmevent17", 0x331, {} , false }, // 44
+ { "mhpmevent18", 0x332, {} , false }, // 45
+ { "mhpmevent19", 0x333, {} , false }, // 46
+ { "mhpmevent20", 0x334, {} , false }, // 47
+ { "mhpmevent21", 0x335, {} , false }, // 48
+ { "mhpmevent22", 0x336, {} , false }, // 49
+ { "mhpmevent23", 0x337, {} , false }, // 50
+ { "mhpmevent24", 0x338, {} , false }, // 51
+ { "mhpmevent25", 0x339, {} , false }, // 52
+ { "mhpmevent26", 0x33A, {} , false }, // 53
+ { "mhpmevent27", 0x33B, {} , false }, // 54
+ { "mhpmevent28", 0x33C, {} , false }, // 55
+ { "mhpmevent29", 0x33D, {} , false }, // 56
+ { "mhpmevent30", 0x33E, {} , false }, // 57
+ { "mhpmevent31", 0x33F, {} , false }, // 58
+ { "mscratch", 0x340, {} , false }, // 59
+ { "mepc", 0x341, {} , false }, // 60
+ { "mcause", 0x342, {} , false }, // 61
+ { "mtval", 0x343, {} , false }, // 62
+ { "mip", 0x344, {} , false }, // 63
+ { "pmpcfg0", 0x3A0, {} , false }, // 64
+ { "pmpcfg1", 0x3A1, {} , true }, // 65
+ { "pmpcfg2", 0x3A2, {} , false }, // 66
+ { "pmpcfg3", 0x3A3, {} , true }, // 67
+ { "pmpaddr0", 0x3B0, {} , false }, // 68
+ { "pmpaddr1", 0x3B1, {} , false }, // 69
+ { "pmpaddr2", 0x3B2, {} , false }, // 70
+ { "pmpaddr3", 0x3B3, {} , false }, // 71
+ { "pmpaddr4", 0x3B4, {} , false }, // 72
+ { "pmpaddr5", 0x3B5, {} , false }, // 73
+ { "pmpaddr6", 0x3B6, {} , false }, // 74
+ { "pmpaddr7", 0x3B7, {} , false }, // 75
+ { "pmpaddr8", 0x3B8, {} , false }, // 76
+ { "pmpaddr9", 0x3B9, {} , false }, // 77
+ { "pmpaddr10", 0x3BA, {} , false }, // 78
+ { "pmpaddr11", 0x3BB, {} , false }, // 79
+ { "pmpaddr12", 0x3BC, {} , false }, // 80
+ { "pmpaddr13", 0x3BD, {} , false }, // 81
+ { "pmpaddr14", 0x3BE, {} , false }, // 82
+ { "pmpaddr15", 0x3BF, {} , false }, // 83
+ { "tselect", 0x7A0, {} , false }, // 84
+ { "tdata1", 0x7A1, {} , false }, // 85
+ { "tdata2", 0x7A2, {} , false }, // 86
+ { "tdata3", 0x7A3, {} , false }, // 87
+ { "dcsr", 0x7B0, {} , false }, // 88
+ { "dpc", 0x7B1, {} , false }, // 89
+ { "dscratch", 0x7B2, {} , false }, // 90
+ { "mcycle", 0xB00, {} , false }, // 91
+ { "minstret", 0xB02, {} , false }, // 92
+ { "mhpmcounter3", 0xB03, {} , false }, // 93
+ { "mhpmcounter4", 0xB04, {} , false }, // 94
+ { "mhpmcounter5", 0xB05, {} , false }, // 95
+ { "mhpmcounter6", 0xB06, {} , false }, // 96
+ { "mhpmcounter7", 0xB07, {} , false }, // 97
+ { "mhpmcounter8", 0xB08, {} , false }, // 98
+ { "mhpmcounter9", 0xB09, {} , false }, // 99
+ { "mhpmcounter10", 0xB0A, {} , false }, // 100
+ { "mhpmcounter11", 0xB0B, {} , false }, // 101
+ { "mhpmcounter12", 0xB0C, {} , false }, // 102
+ { "mhpmcounter13", 0xB0D, {} , false }, // 103
+ { "mhpmcounter14", 0xB0E, {} , false }, // 104
+ { "mhpmcounter15", 0xB0F, {} , false }, // 105
+ { "mhpmcounter16", 0xB10, {} , false }, // 106
+ { "mhpmcounter17", 0xB11, {} , false }, // 107
+ { "mhpmcounter18", 0xB12, {} , false }, // 108
+ { "mhpmcounter19", 0xB13, {} , false }, // 109
+ { "mhpmcounter20", 0xB14, {} , false }, // 110
+ { "mhpmcounter21", 0xB15, {} , false }, // 111
+ { "mhpmcounter22", 0xB16, {} , false }, // 112
+ { "mhpmcounter23", 0xB17, {} , false }, // 113
+ { "mhpmcounter24", 0xB18, {} , false }, // 114
+ { "mhpmcounter25", 0xB19, {} , false }, // 115
+ { "mhpmcounter26", 0xB1A, {} , false }, // 116
+ { "mhpmcounter27", 0xB1B, {} , false }, // 117
+ { "mhpmcounter28", 0xB1C, {} , false }, // 118
+ { "mhpmcounter29", 0xB1D, {} , false }, // 119
+ { "mhpmcounter30", 0xB1E, {} , false }, // 120
+ { "mhpmcounter31", 0xB1F, {} , false }, // 121
+ { "mcycleh", 0xB80, {} , true }, // 122
+ { "minstreth", 0xB82, {} , true }, // 123
+ { "mhpmcounter3h", 0xB83, {} , true }, // 124
+ { "mhpmcounter4h", 0xB84, {} , true }, // 125
+ { "mhpmcounter5h", 0xB85, {} , true }, // 126
+ { "mhpmcounter6h", 0xB86, {} , true }, // 127
+ { "mhpmcounter7h", 0xB87, {} , true }, // 128
+ { "mhpmcounter8h", 0xB88, {} , true }, // 129
+ { "mhpmcounter9h", 0xB89, {} , true }, // 130
+ { "mhpmcounter10h", 0xB8A, {} , true }, // 131
+ { "mhpmcounter11h", 0xB8B, {} , true }, // 132
+ { "mhpmcounter12h", 0xB8C, {} , true }, // 133
+ { "mhpmcounter13h", 0xB8D, {} , true }, // 134
+ { "mhpmcounter14h", 0xB8E, {} , true }, // 135
+ { "mhpmcounter15h", 0xB8F, {} , true }, // 136
+ { "mhpmcounter16h", 0xB90, {} , true }, // 137
+ { "mhpmcounter17h", 0xB91, {} , true }, // 138
+ { "mhpmcounter18h", 0xB92, {} , true }, // 139
+ { "mhpmcounter19h", 0xB93, {} , true }, // 140
+ { "mhpmcounter20h", 0xB94, {} , true }, // 141
+ { "mhpmcounter21h", 0xB95, {} , true }, // 142
+ { "mhpmcounter22h", 0xB96, {} , true }, // 143
+ { "mhpmcounter23h", 0xB97, {} , true }, // 144
+ { "mhpmcounter24h", 0xB98, {} , true }, // 145
+ { "mhpmcounter25h", 0xB99, {} , true }, // 146
+ { "mhpmcounter26h", 0xB9A, {} , true }, // 147
+ { "mhpmcounter27h", 0xB9B, {} , true }, // 148
+ { "mhpmcounter28h", 0xB9C, {} , true }, // 149
+ { "mhpmcounter29h", 0xB9D, {} , true }, // 150
+ { "mhpmcounter30h", 0xB9E, {} , true }, // 151
+ { "mhpmcounter31h", 0xB9F, {} , true }, // 152
+ { "cycle", 0xC00, {} , false }, // 153
+ { "time", 0xC01, {} , false }, // 154
+ { "instret", 0xC02, {} , false }, // 155
+ { "hpmcounter3", 0xC03, {} , false }, // 156
+ { "hpmcounter4", 0xC04, {} , false }, // 157
+ { "hpmcounter5", 0xC05, {} , false }, // 158
+ { "hpmcounter6", 0xC06, {} , false }, // 159
+ { "hpmcounter7", 0xC07, {} , false }, // 160
+ { "hpmcounter8", 0xC08, {} , false }, // 161
+ { "hpmcounter9", 0xC09, {} , false }, // 162
+ { "hpmcounter10", 0xC0A, {} , false }, // 163
+ { "hpmcounter11", 0xC0B, {} , false }, // 164
+ { "hpmcounter12", 0xC0C, {} , false }, // 165
+ { "hpmcounter13", 0xC0D, {} , false }, // 166
+ { "hpmcounter14", 0xC0E, {} , false }, // 167
+ { "hpmcounter15", 0xC0F, {} , false }, // 168
+ { "hpmcounter16", 0xC10, {} , false }, // 169
+ { "hpmcounter17", 0xC11, {} , false }, // 170
+ { "hpmcounter18", 0xC12, {} , false }, // 171
+ { "hpmcounter19", 0xC13, {} , false }, // 172
+ { "hpmcounter20", 0xC14, {} , false }, // 173
+ { "hpmcounter21", 0xC15, {} , false }, // 174
+ { "hpmcounter22", 0xC16, {} , false }, // 175
+ { "hpmcounter23", 0xC17, {} , false }, // 176
+ { "hpmcounter24", 0xC18, {} , false }, // 177
+ { "hpmcounter25", 0xC19, {} , false }, // 178
+ { "hpmcounter26", 0xC1A, {} , false }, // 179
+ { "hpmcounter27", 0xC1B, {} , false }, // 180
+ { "hpmcounter28", 0xC1C, {} , false }, // 181
+ { "hpmcounter29", 0xC1D, {} , false }, // 182
+ { "hpmcounter30", 0xC1E, {} , false }, // 183
+ { "hpmcounter31", 0xC1F, {} , false }, // 184
+ { "cycleh", 0xC80, {} , true }, // 185
+ { "timeh", 0xC81, {} , true }, // 186
+ { "instreth", 0xC82, {} , true }, // 187
+ { "hpmcounter3h", 0xC83, {} , true }, // 188
+ { "hpmcounter4h", 0xC84, {} , true }, // 189
+ { "hpmcounter5h", 0xC85, {} , true }, // 190
+ { "hpmcounter6h", 0xC86, {} , true }, // 191
+ { "hpmcounter7h", 0xC87, {} , true }, // 192
+ { "hpmcounter8h", 0xC88, {} , true }, // 193
+ { "hpmcounter9h", 0xC89, {} , true }, // 194
+ { "hpmcounter10h", 0xC8A, {} , true }, // 195
+ { "hpmcounter11h", 0xC8B, {} , true }, // 196
+ { "hpmcounter12h", 0xC8C, {} , true }, // 197
+ { "hpmcounter13h", 0xC8D, {} , true }, // 198
+ { "hpmcounter14h", 0xC8E, {} , true }, // 199
+ { "hpmcounter15h", 0xC8F, {} , true }, // 200
+ { "hpmcounter16h", 0xC90, {} , true }, // 201
+ { "hpmcounter17h", 0xC91, {} , true }, // 202
+ { "hpmcounter18h", 0xC92, {} , true }, // 203
+ { "hpmcounter19h", 0xC93, {} , true }, // 204
+ { "hpmcounter20h", 0xC94, {} , true }, // 205
+ { "hpmcounter21h", 0xC95, {} , true }, // 206
+ { "hpmcounter22h", 0xC96, {} , true }, // 207
+ { "hpmcounter23h", 0xC97, {} , true }, // 208
+ { "hpmcounter24h", 0xC98, {} , true }, // 209
+ { "hpmcounter25h", 0xC99, {} , true }, // 210
+ { "hpmcounter26h", 0xC9A, {} , true }, // 211
+ { "hpmcounter27h", 0xC9B, {} , true }, // 212
+ { "hpmcounter28h", 0xC9C, {} , true }, // 213
+ { "hpmcounter29h", 0xC9D, {} , true }, // 214
+ { "hpmcounter30h", 0xC9E, {} , true }, // 215
+ { "hpmcounter31h", 0xC9F, {} , true }, // 216
+ { "mvendorid", 0xF11, {} , false }, // 217
+ { "marchid", 0xF12, {} , false }, // 218
+ { "mimpid", 0xF13, {} , false }, // 219
+ { "mhartid", 0xF14, {} , false }, // 220
+ };
+
+const SysReg *lookupSysRegByEncoding(uint16_t Encoding) {
+ struct KeyType {
+ uint16_t Encoding;
+ };
+ KeyType Key = { Encoding };
+ auto Table = makeArrayRef(SysRegsList);
+ auto Idx = std::lower_bound(Table.begin(), Table.end(), Key,
+ [](const SysReg &LHS, const KeyType &RHS) {
+ if (LHS.Encoding < RHS.Encoding)
+ return true;
+ if (LHS.Encoding > RHS.Encoding)
+ return false;
+ return false;
+ });
+
+ if (Idx == Table.end() ||
+ Key.Encoding != Idx->Encoding)
+ return nullptr;
+ return &*Idx;
+}
+
+const SysReg *lookupSysRegByName(StringRef Name) {
+ struct IndexType {
+ const char * Name;
+ unsigned _index;
+ };
+ static const struct IndexType Index[] = {
+ { "CYCLE", 153 },
+ { "CYCLEH", 185 },
+ { "DCSR", 88 },
+ { "DPC", 89 },
+ { "DSCRATCH", 90 },
+ { "FCSR", 3 },
+ { "FFLAGS", 1 },
+ { "FRM", 2 },
+ { "HPMCOUNTER10", 163 },
+ { "HPMCOUNTER10H", 195 },
+ { "HPMCOUNTER11", 164 },
+ { "HPMCOUNTER11H", 196 },
+ { "HPMCOUNTER12", 165 },
+ { "HPMCOUNTER12H", 197 },
+ { "HPMCOUNTER13", 166 },
+ { "HPMCOUNTER13H", 198 },
+ { "HPMCOUNTER14", 167 },
+ { "HPMCOUNTER14H", 199 },
+ { "HPMCOUNTER15", 168 },
+ { "HPMCOUNTER15H", 200 },
+ { "HPMCOUNTER16", 169 },
+ { "HPMCOUNTER16H", 201 },
+ { "HPMCOUNTER17", 170 },
+ { "HPMCOUNTER17H", 202 },
+ { "HPMCOUNTER18", 171 },
+ { "HPMCOUNTER18H", 203 },
+ { "HPMCOUNTER19", 172 },
+ { "HPMCOUNTER19H", 204 },
+ { "HPMCOUNTER20", 173 },
+ { "HPMCOUNTER20H", 205 },
+ { "HPMCOUNTER21", 174 },
+ { "HPMCOUNTER21H", 206 },
+ { "HPMCOUNTER22", 175 },
+ { "HPMCOUNTER22H", 207 },
+ { "HPMCOUNTER23", 176 },
+ { "HPMCOUNTER23H", 208 },
+ { "HPMCOUNTER24", 177 },
+ { "HPMCOUNTER24H", 209 },
+ { "HPMCOUNTER25", 178 },
+ { "HPMCOUNTER25H", 210 },
+ { "HPMCOUNTER26", 179 },
+ { "HPMCOUNTER26H", 211 },
+ { "HPMCOUNTER27", 180 },
+ { "HPMCOUNTER27H", 212 },
+ { "HPMCOUNTER28", 181 },
+ { "HPMCOUNTER28H", 213 },
+ { "HPMCOUNTER29", 182 },
+ { "HPMCOUNTER29H", 214 },
+ { "HPMCOUNTER3", 156 },
+ { "HPMCOUNTER30", 183 },
+ { "HPMCOUNTER30H", 215 },
+ { "HPMCOUNTER31", 184 },
+ { "HPMCOUNTER31H", 216 },
+ { "HPMCOUNTER3H", 188 },
+ { "HPMCOUNTER4", 157 },
+ { "HPMCOUNTER4H", 189 },
+ { "HPMCOUNTER5", 158 },
+ { "HPMCOUNTER5H", 190 },
+ { "HPMCOUNTER6", 159 },
+ { "HPMCOUNTER6H", 191 },
+ { "HPMCOUNTER7", 160 },
+ { "HPMCOUNTER7H", 192 },
+ { "HPMCOUNTER8", 161 },
+ { "HPMCOUNTER8H", 193 },
+ { "HPMCOUNTER9", 162 },
+ { "HPMCOUNTER9H", 194 },
+ { "INSTRET", 155 },
+ { "INSTRETH", 187 },
+ { "MARCHID", 218 },
+ { "MCAUSE", 61 },
+ { "MCOUNTEREN", 29 },
+ { "MCYCLE", 91 },
+ { "MCYCLEH", 122 },
+ { "MEDELEG", 25 },
+ { "MEPC", 60 },
+ { "MHARTID", 220 },
+ { "MHPMCOUNTER10", 100 },
+ { "MHPMCOUNTER10H", 131 },
+ { "MHPMCOUNTER11", 101 },
+ { "MHPMCOUNTER11H", 132 },
+ { "MHPMCOUNTER12", 102 },
+ { "MHPMCOUNTER12H", 133 },
+ { "MHPMCOUNTER13", 103 },
+ { "MHPMCOUNTER13H", 134 },
+ { "MHPMCOUNTER14", 104 },
+ { "MHPMCOUNTER14H", 135 },
+ { "MHPMCOUNTER15", 105 },
+ { "MHPMCOUNTER15H", 136 },
+ { "MHPMCOUNTER16", 106 },
+ { "MHPMCOUNTER16H", 137 },
+ { "MHPMCOUNTER17", 107 },
+ { "MHPMCOUNTER17H", 138 },
+ { "MHPMCOUNTER18", 108 },
+ { "MHPMCOUNTER18H", 139 },
+ { "MHPMCOUNTER19", 109 },
+ { "MHPMCOUNTER19H", 140 },
+ { "MHPMCOUNTER20", 110 },
+ { "MHPMCOUNTER20H", 141 },
+ { "MHPMCOUNTER21", 111 },
+ { "MHPMCOUNTER21H", 142 },
+ { "MHPMCOUNTER22", 112 },
+ { "MHPMCOUNTER22H", 143 },
+ { "MHPMCOUNTER23", 113 },
+ { "MHPMCOUNTER23H", 144 },
+ { "MHPMCOUNTER24", 114 },
+ { "MHPMCOUNTER24H", 145 },
+ { "MHPMCOUNTER25", 115 },
+ { "MHPMCOUNTER25H", 146 },
+ { "MHPMCOUNTER26", 116 },
+ { "MHPMCOUNTER26H", 147 },
+ { "MHPMCOUNTER27", 117 },
+ { "MHPMCOUNTER27H", 148 },
+ { "MHPMCOUNTER28", 118 },
+ { "MHPMCOUNTER28H", 149 },
+ { "MHPMCOUNTER29", 119 },
+ { "MHPMCOUNTER29H", 150 },
+ { "MHPMCOUNTER3", 93 },
+ { "MHPMCOUNTER30", 120 },
+ { "MHPMCOUNTER30H", 151 },
+ { "MHPMCOUNTER31", 121 },
+ { "MHPMCOUNTER31H", 152 },
+ { "MHPMCOUNTER3H", 124 },
+ { "MHPMCOUNTER4", 94 },
+ { "MHPMCOUNTER4H", 125 },
+ { "MHPMCOUNTER5", 95 },
+ { "MHPMCOUNTER5H", 126 },
+ { "MHPMCOUNTER6", 96 },
+ { "MHPMCOUNTER6H", 127 },
+ { "MHPMCOUNTER7", 97 },
+ { "MHPMCOUNTER7H", 128 },
+ { "MHPMCOUNTER8", 98 },
+ { "MHPMCOUNTER8H", 129 },
+ { "MHPMCOUNTER9", 99 },
+ { "MHPMCOUNTER9H", 130 },
+ { "MHPMEVENT10", 37 },
+ { "MHPMEVENT11", 38 },
+ { "MHPMEVENT12", 39 },
+ { "MHPMEVENT13", 40 },
+ { "MHPMEVENT14", 41 },
+ { "MHPMEVENT15", 42 },
+ { "MHPMEVENT16", 43 },
+ { "MHPMEVENT17", 44 },
+ { "MHPMEVENT18", 45 },
+ { "MHPMEVENT19", 46 },
+ { "MHPMEVENT20", 47 },
+ { "MHPMEVENT21", 48 },
+ { "MHPMEVENT22", 49 },
+ { "MHPMEVENT23", 50 },
+ { "MHPMEVENT24", 51 },
+ { "MHPMEVENT25", 52 },
+ { "MHPMEVENT26", 53 },
+ { "MHPMEVENT27", 54 },
+ { "MHPMEVENT28", 55 },
+ { "MHPMEVENT29", 56 },
+ { "MHPMEVENT3", 30 },
+ { "MHPMEVENT30", 57 },
+ { "MHPMEVENT31", 58 },
+ { "MHPMEVENT4", 31 },
+ { "MHPMEVENT5", 32 },
+ { "MHPMEVENT6", 33 },
+ { "MHPMEVENT7", 34 },
+ { "MHPMEVENT8", 35 },
+ { "MHPMEVENT9", 36 },
+ { "MIDELEG", 26 },
+ { "MIE", 27 },
+ { "MIMPID", 219 },
+ { "MINSTRET", 92 },
+ { "MINSTRETH", 123 },
+ { "MIP", 63 },
+ { "MISA", 24 },
+ { "MSCRATCH", 59 },
+ { "MSTATUS", 23 },
+ { "MTVAL", 62 },
+ { "MTVEC", 28 },
+ { "MVENDORID", 217 },
+ { "PMPADDR0", 68 },
+ { "PMPADDR1", 69 },
+ { "PMPADDR10", 78 },
+ { "PMPADDR11", 79 },
+ { "PMPADDR12", 80 },
+ { "PMPADDR13", 81 },
+ { "PMPADDR14", 82 },
+ { "PMPADDR15", 83 },
+ { "PMPADDR2", 70 },
+ { "PMPADDR3", 71 },
+ { "PMPADDR4", 72 },
+ { "PMPADDR5", 73 },
+ { "PMPADDR6", 74 },
+ { "PMPADDR7", 75 },
+ { "PMPADDR8", 76 },
+ { "PMPADDR9", 77 },
+ { "PMPCFG0", 64 },
+ { "PMPCFG1", 65 },
+ { "PMPCFG2", 66 },
+ { "PMPCFG3", 67 },
+ { "SATP", 22 },
+ { "SCAUSE", 19 },
+ { "SCOUNTEREN", 16 },
+ { "SEDELEG", 12 },
+ { "SEPC", 18 },
+ { "SIDELEG", 13 },
+ { "SIE", 14 },
+ { "SIP", 21 },
+ { "SSCRATCH", 17 },
+ { "SSTATUS", 11 },
+ { "STVAL", 20 },
+ { "STVEC", 15 },
+ { "TDATA1", 85 },
+ { "TDATA2", 86 },
+ { "TDATA3", 87 },
+ { "TIME", 154 },
+ { "TIMEH", 186 },
+ { "TSELECT", 84 },
+ { "UCAUSE", 8 },
+ { "UEPC", 7 },
+ { "UIE", 4 },
+ { "UIP", 10 },
+ { "USCRATCH", 6 },
+ { "USTATUS", 0 },
+ { "UTVAL", 9 },
+ { "UTVEC", 5 },
+ };
+
+ struct KeyType {
+ std::string Name;
+ };
+ KeyType Key = { Name.upper() };
+ auto Table = makeArrayRef(Index);
+ auto Idx = std::lower_bound(Table.begin(), Table.end(), Key,
+ [](const IndexType &LHS, const KeyType &RHS) {
+ int CmpName = StringRef(LHS.Name).compare(RHS.Name);
+ if (CmpName < 0) return true;
+ if (CmpName > 0) return false;
+ return false;
+ });
+
+ if (Idx == Table.end() ||
+ Key.Name != Idx->Name)
+ return nullptr;
+ return &SysRegsList[Idx->_index];
+}
+#endif
+
+#undef GET_SysRegsList_DECL
+#undef GET_SysRegsList_IMPL
diff --git a/third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmParsers.def b/third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmParsers.def
index bce0713..9893c66 100644
--- a/third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmParsers.def
+++ b/third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmParsers.def
@@ -39,6 +39,9 @@
#if defined(__powerpc64__)
LLVM_ASM_PARSER(PowerPC)
#endif
+#if defined(__riscv)
+LLVM_ASM_PARSER(RISCV)
+#endif
#undef LLVM_ASM_PARSER
diff --git a/third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmPrinters.def b/third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmPrinters.def
index 112b1a4..523ee3b 100644
--- a/third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmPrinters.def
+++ b/third_party/llvm-10.0/configs/linux/include/llvm/Config/AsmPrinters.def
@@ -39,6 +39,9 @@
#if defined(__powerpc64__)
LLVM_ASM_PRINTER(PowerPC)
#endif
+#if defined(__riscv)
+LLVM_ASM_PRINTER(RISCV)
+#endif
#undef LLVM_ASM_PRINTER
diff --git a/third_party/llvm-10.0/configs/linux/include/llvm/Config/Disassemblers.def b/third_party/llvm-10.0/configs/linux/include/llvm/Config/Disassemblers.def
index 850983c..4f61495 100644
--- a/third_party/llvm-10.0/configs/linux/include/llvm/Config/Disassemblers.def
+++ b/third_party/llvm-10.0/configs/linux/include/llvm/Config/Disassemblers.def
@@ -39,6 +39,9 @@
#if defined(__powerpc64__)
LLVM_DISASSEMBLER(PowerPC)
#endif
+#if defined(__riscv)
+LLVM_DISASSEMBLER(RISCV)
+#endif
#undef LLVM_DISASSEMBLER
diff --git a/third_party/llvm-10.0/configs/linux/include/llvm/Config/Targets.def b/third_party/llvm-10.0/configs/linux/include/llvm/Config/Targets.def
index 103d30a..0e68b41 100644
--- a/third_party/llvm-10.0/configs/linux/include/llvm/Config/Targets.def
+++ b/third_party/llvm-10.0/configs/linux/include/llvm/Config/Targets.def
@@ -38,6 +38,9 @@
#if defined(__powerpc64__)
LLVM_TARGET(PowerPC)
#endif
+#if defined(__riscv)
+LLVM_TARGET(RISCV)
+#endif
#undef LLVM_TARGET
diff --git a/third_party/llvm-10.0/configs/linux/include/llvm/Config/abi-breaking.h b/third_party/llvm-10.0/configs/linux/include/llvm/Config/abi-breaking.h
index de80383..fd32bf3 100644
--- a/third_party/llvm-10.0/configs/linux/include/llvm/Config/abi-breaking.h
+++ b/third_party/llvm-10.0/configs/linux/include/llvm/Config/abi-breaking.h
@@ -13,11 +13,7 @@
#define LLVM_ABI_BREAKING_CHECKS_H
/* Define to enable checks that alter the LLVM C++ ABI */
-#if defined(NDEBUG)
#define LLVM_ENABLE_ABI_BREAKING_CHECKS 0
-#else
-#define LLVM_ENABLE_ABI_BREAKING_CHECKS 1
-#endif
/* Define to enable reverse iteration of unordered llvm containers */
#define LLVM_ENABLE_REVERSE_ITERATION 0
diff --git a/third_party/llvm-10.0/configs/linux/include/llvm/Config/config.h b/third_party/llvm-10.0/configs/linux/include/llvm/Config/config.h
index 24bdc67..7392898 100644
--- a/third_party/llvm-10.0/configs/linux/include/llvm/Config/config.h
+++ b/third_party/llvm-10.0/configs/linux/include/llvm/Config/config.h
@@ -4,9 +4,6 @@
/* Exported configuration */
#include "llvm/Config/llvm-config.h"
-/* For detecting __GLIBC__ usage */
-#include <features.h>
-
/* Bug report URL. */
#define BUG_REPORT_URL "https://bugs.llvm.org/"
@@ -130,12 +127,6 @@
/* Define to 1 if you have the `mallinfo' function. */
#define HAVE_MALLINFO 1
-/* Some projects using SwiftShader bypass cmake (eg Chromium via gn) */
-/* so we need to check glibc version for the new API to be safe */
-#if defined(__GLIBC__) && __GLIBC_MINOR__ >= 33
-#define HAVE_MALLINFO2 1
-#endif
-
/* Define to 1 if you have the <malloc/malloc.h> header file. */
/* #undef HAVE_MALLOC_MALLOC_H */
@@ -317,6 +308,8 @@
#define LLVM_DEFAULT_TARGET_TRIPLE "mips64el-linux-gnuabi64"
#elif defined(__powerpc64__)
#define LLVM_DEFAULT_TARGET_TRIPLE "powerpc64le-unknown-linux-gnu"
+#elif defined(__riscv) && __riscv_xlen == 64
+#define LLVM_DEFAULT_TARGET_TRIPLE "riscv64-unknown-linux-gnu"
#else
#error "unknown architecture"
#endif
diff --git a/third_party/llvm-10.0/configs/linux/include/llvm/Config/llvm-config.h b/third_party/llvm-10.0/configs/linux/include/llvm/Config/llvm-config.h
index 6b26751..b709faa 100644
--- a/third_party/llvm-10.0/configs/linux/include/llvm/Config/llvm-config.h
+++ b/third_party/llvm-10.0/configs/linux/include/llvm/Config/llvm-config.h
@@ -42,6 +42,8 @@
#define LLVM_DEFAULT_TARGET_TRIPLE "mips64el-linux-gnuabi64"
#elif defined(__powerpc64__)
#define LLVM_DEFAULT_TARGET_TRIPLE "powerpc64le-unknown-linux-gnu"
+#elif defined(__riscv) && __riscv_xlen == 64
+#define LLVM_DEFAULT_TARGET_TRIPLE "riscv64-unknown-linux-gnu"
#else
#error "unknown architecture"
#endif
@@ -67,6 +69,8 @@
#define LLVM_HOST_TRIPLE "mips64el-linux-gnuabi64"
#elif defined(__powerpc64__)
#define LLVM_HOST_TRIPLE "powerpc64le-unknown-linux-gnu"
+#elif defined(__riscv) && __riscv_xlen == 64
+#define LLVM_HOST_TRIPLE "riscv64-unknown-linux-gnu"
#else
#error "unknown architecture"
#endif
@@ -82,6 +86,8 @@
#define LLVM_NATIVE_ARCH Mips
#elif defined(__powerpc64__)
#define LLVM_NATIVE_ARCH PowerPC
+#elif defined(__riscv)
+#define LLVM_NATIVE_ARCH RISCV
#else
#error "unknown architecture"
#endif
@@ -97,6 +103,8 @@
#define LLVM_NATIVE_ASMPARSER LLVMInitializeMipsAsmParser
#elif defined(__powerpc64__)
#define LLVM_NATIVE_ASMPARSER LLVMInitializePowerPCAsmParser
+#elif defined(__riscv)
+#define LLVM_NATIVE_ASMPARSER LLVMInitializeRISCVAsmParser
#else
#error "unknown architecture"
#endif
@@ -112,6 +120,8 @@
#define LLVM_NATIVE_ASMPRINTER LLVMInitializeMipsAsmPrinter
#elif defined(__powerpc64__)
#define LLVM_NATIVE_ASMPRINTER LLVMInitializePowerPCAsmPrinter
+#elif defined(__riscv)
+#define LLVM_NATIVE_ASMPRINTER LLVMInitializeRISCVAsmPrinter
#else
#error "unknown architecture"
#endif
@@ -127,6 +137,8 @@
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeMipsDisassembler
#elif defined(__powerpc64__)
#define LLVM_NATIVE_DISASSEMBLER LLVMInitializePowerPCDisassembler
+#elif defined(__riscv)
+#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeRISCVDisassembler
#else
#error "unknown architecture"
#endif
@@ -142,6 +154,8 @@
#define LLVM_NATIVE_TARGET LLVMInitializeMipsTarget
#elif defined(__powerpc64__)
#define LLVM_NATIVE_TARGET LLVMInitializePowerPCTarget
+#elif defined(__riscv)
+#define LLVM_NATIVE_TARGET LLVMInitializeRISCVTarget
#else
#error "unknown architecture"
#endif
@@ -157,6 +171,8 @@
#define LLVM_NATIVE_TARGETINFO LLVMInitializeMipsTargetInfo
#elif defined(__powerpc64__)
#define LLVM_NATIVE_TARGETINFO LLVMInitializePowerPCTargetInfo
+#elif defined(__riscv)
+#define LLVM_NATIVE_TARGETINFO LLVMInitializeRISCVTargetInfo
#else
#error "unknown architecture"
#endif
@@ -172,6 +188,8 @@
#define LLVM_NATIVE_TARGETMC LLVMInitializeMipsTargetMC
#elif defined(__powerpc64__)
#define LLVM_NATIVE_TARGETMC LLVMInitializePowerPCTargetMC
+#elif defined(__riscv)
+#define LLVM_NATIVE_TARGETMC LLVMInitializeRISCVTargetMC
#else
#error "unknown architecture"
#endif
