Add support for 32b MIPS architecture

* LLVM reactor backend: requires LLVM 7.0
* Subzero reactor backend: unittests hit unimplemented
  TargetMIPS32::lowerShuffleVector()

Bug: b/117854176
Change-Id: Ie58e3e438db6f1b442b05efecf9b645aff82321a
Reviewed-on: https://swiftshader-review.googlesource.com/c/21748
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
Reviewed-by: Alexis Hétu <sugoi@google.com>
Tested-by: Milko Leporis <milko.leporis@mips.com>
diff --git a/src/Reactor/SubzeroReactor.cpp b/src/Reactor/SubzeroReactor.cpp
index 2126afb..76f5a72 100644
--- a/src/Reactor/SubzeroReactor.cpp
+++ b/src/Reactor/SubzeroReactor.cpp
@@ -106,6 +106,8 @@
 				return true;
 			#elif defined(__i386__) || defined(__x86_64__)
 				return false;
+			#elif defined(__mips__)
+				return false;
 			#else
 				#error "Unknown architecture"
 			#endif
@@ -373,6 +375,8 @@
 			assert(sizeof(void*) == 4 && elfHeader->e_machine == EM_ARM);
 		#elif defined(__aarch64__)
 			assert(sizeof(void*) == 8 && elfHeader->e_machine == EM_AARCH64);
+		#elif defined(__mips__)
+			assert(sizeof(void*) == 4 && elfHeader->e_machine == EM_MIPS);
 		#else
 			#error "Unsupported platform"
 		#endif
@@ -526,6 +530,9 @@
 		#if defined(__arm__)
 			Flags.setTargetArch(Ice::Target_ARM32);
 			Flags.setTargetInstructionSet(Ice::ARM32InstructionSet_HWDivArm);
+		#elif defined(__mips__)
+			Flags.setTargetArch(Ice::Target_MIPS32);
+			Flags.setTargetInstructionSet(Ice::BaseInstructionSet);
 		#else   // x86
 			Flags.setTargetArch(sizeof(void*) == 8 ? Ice::Target_X8664 : Ice::Target_X8632);
 			Flags.setTargetInstructionSet(CPUID::SSE4_1 ? Ice::X86InstructionSet_SSE4_1 : Ice::X86InstructionSet_SSE2);