Add support for 32b MIPS architecture
* LLVM reactor backend: requires LLVM 7.0
* Subzero reactor backend: unittests hit unimplemented
TargetMIPS32::lowerShuffleVector()
Bug: b/117854176
Change-Id: Ie58e3e438db6f1b442b05efecf9b645aff82321a
Reviewed-on: https://swiftshader-review.googlesource.com/c/21748
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
Reviewed-by: Alexis Hétu <sugoi@google.com>
Tested-by: Milko Leporis <milko.leporis@mips.com>
diff --git a/BUILD.gn b/BUILD.gn
index b36d9f9..672e51e 100644
--- a/BUILD.gn
+++ b/BUILD.gn
@@ -96,16 +96,30 @@
"-march=pentium4",
"-mtune=generic",
]
+ } else if (target_cpu == "mipsel" && current_cpu == target_cpu) {
+ cflags += [
+ "-march=mipsel",
+ "-mcpu=mips32r2",
+ "-fPIC",
+ "-mhard-float",
+ "-mfp32",
+ ]
}
if (is_linux) {
- ldflags = [
- "-Wl,--hash-style=both",
- "-Wl,--gc-sections",
- ]
+ ldflags = [ "-Wl,--gc-sections" ]
+
+ if (target_cpu == "mipsel") {
+ ldflags += [
+ "-Wl,--hash-style=sysv",
+ "-mips32r2",
+ ]
+ } else {
+ ldflags += [ "-Wl,--hash-style=both" ]
+ }
# A bug in the gold linker prevents using ICF on 32-bit (crbug.com/729532)
- if (use_gold && target_cpu == "x86") {
+ if (use_gold && (target_cpu == "x86" || target_cpu == "mipsel")) {
ldflags += [ "-Wl,--icf=none" ]
}
}