commit 03532e59cec4d20a774b5aa3e51e5fc3ace1feab
author Jan Voung <jvoung@chromium.org> Tue Sep 23 13:32:18 2014 -0700
committer Jan Voung <jvoung@chromium.org> Tue Sep 23 13:32:18 2014 -0700
tree 076d356cff7bdb3bce086fea11f030644c798c74
parent 8acded039857a42b170c1cbc0ad4d1345419de3c

Handle a few more instructions in assembler (cmov, cdq, cmpxchg, xadd, xchg).

BUG=none
R=stichnot@chromium.org

Review URL: https://codereview.chromium.org/597643002

src/assembler_ia32.cpp

diff --git a/src/assembler_ia32.cpp b/src/assembler_ia32.cpp
index ceed1d1..3cf9e25 100644
--- a/src/assembler_ia32.cpp
+++ b/src/assembler_ia32.cpp
@@ -1110,12 +1110,6 @@
   EmitUint8(0xF7);
 }
 
-void AssemblerX86::xchgl(GPRRegister dst, GPRRegister src) {
-  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
-  EmitUint8(0x87);
-  EmitRegisterOperand(dst, src);
-}
-
 void AssemblerX86::cmpl(GPRRegister reg, const Immediate &imm) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitComplex(7, Operand(reg), imm);
@@ -1307,6 +1301,18 @@
   EmitOperand(reg, address);
 }
 
+void AssemblerX86::cbw() {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandSizeOverride();
+  EmitUint8(0x98);
+}
+
+void AssemblerX86::cwd() {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitOperandSizeOverride();
+  EmitUint8(0x99);
+}
+
 void AssemblerX86::cdq() {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x99);
@@ -1674,11 +1680,46 @@
   EmitUint8(0xF0);
 }
 
-void AssemblerX86::cmpxchgl(const Address &address, GPRRegister reg) {
+void AssemblerX86::cmpxchg(Type Ty, const Address &address, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
+  EmitUint8(0x0F);
+  if (Ty == IceType_i8 || Ty == IceType_i1)
+    EmitUint8(0xB0);
+  else
+    EmitUint8(0xB1);
+  EmitOperand(reg, address);
+}
+
+void AssemblerX86::cmpxchg8b(const Address &address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   EmitUint8(0x0F);
-  EmitUint8(0xB1);
-  EmitOperand(reg, address);
+  EmitUint8(0xC7);
+  EmitOperand(1, address);
+}
+
+void AssemblerX86::xadd(Type Ty, const Address &addr, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
+  EmitUint8(0x0F);
+  if (Ty == IceType_i8 || Ty == IceType_i1)
+    EmitUint8(0xC0);
+  else
+    EmitUint8(0xC1);
+  EmitOperand(reg, addr);
+}
+
+void AssemblerX86::xchg(Type Ty, const Address &addr, GPRRegister reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  if (Ty == IceType_i16)
+    EmitOperandSizeOverride();
+  if (Ty == IceType_i8 || Ty == IceType_i1)
+    EmitUint8(0x86);
+  else
+    EmitUint8(0x87);
+  EmitOperand(reg, addr);
 }
 
 void AssemblerX86::Align(intptr_t alignment, intptr_t offset) {